diff --git a/.gitignore b/.gitignore
index e69de29b..2f7b9bb8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -0,0 +1,12 @@
+*.o
+*.a
+radiochat
+radiopiglatin
+testax5043
+testax5043tx
+testax5043rx
+testax5043init
+testax50432freq
+doc/html/
+doc/latex/
+/.metadata/
diff --git a/LICENSE b/LICENSE
deleted file mode 100644
index 94a9ed02..00000000
--- a/LICENSE
+++ /dev/null
@@ -1,674 +0,0 @@
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-DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
-PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
-EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGES.
-
- 17. Interpretation of Sections 15 and 16.
-
- If the disclaimer of warranty and limitation of liability provided
-above cannot be given local legal effect according to their terms,
-reviewing courts shall apply local law that most closely approximates
-an absolute waiver of all civil liability in connection with the
-Program, unless a warranty or assumption of liability accompanies a
-copy of the Program in return for a fee.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Programs
-
- If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
- To do so, attach the following notices to the program. It is safest
-to attach them to the start of each source file to most effectively
-state the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-
- Copyright (C)
-
- This program is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-
-Also add information on how to contact you by electronic and paper mail.
-
- If the program does terminal interaction, make it output a short
-notice like this when it starts in an interactive mode:
-
- Copyright (C)
- This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
- This is free software, and you are welcome to redistribute it
- under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License. Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
- You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
- .
-
- The GNU General Public License does not permit incorporating your program
-into proprietary programs. If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library. If this is what you want to do, use the GNU Lesser General
-Public License instead of this License. But first, please read
-.
diff --git a/Makefile b/Makefile
new file mode 100644
index 00000000..3909727b
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,245 @@
+all: libax5043.a
+all: radiochat
+all: radiopiglatin
+all: testax5043rx
+all: testax5043tx
+all: testax50432freq
+all: testax5043init
+
+rebuild: clean
+rebuild: all
+
+lib: libax5043.a
+
+clean:
+ rm -f radiochat
+ rm -f radiopiglatin
+ rm -f testax5043rx
+ rm -f testax5043tx
+ rm -f testax50432freq
+ rm -f testax5043init
+ rm -f libax5043.a
+ rm -f */*.o
+ rm -f */*/*.o
+ rm -rf ax5043/doc/html
+ rm -rf ax5043/doc/latex
+
+docs:
+ mkdir -p ax5043/doc; cd ax5043; doxygen Doxyfile
+ cd ax5043/doc/latex && make && cd ../.. && cp doc/latex/refman.pdf doc/TransceiverFramework.pdf
+
+libax5043.a: ax5043/crc/crc.o
+libax5043.a: ax5043/ax5043support/ax5043tx.o
+libax5043.a: ax5043/ax5043support/ax5043init.o
+libax5043.a: ax5043/ax5043support/ax5043rx.o
+libax5043.a: ax5043/axradio/axradiorx.o
+libax5043.a: ax5043/axradio/axradiomode.o
+libax5043.a: ax5043/axradio/axradiotx.o
+libax5043.a: ax5043/axradio/axradioinit.o
+libax5043.a: ax5043/generated/configrx.o
+libax5043.a: ax5043/generated/configtx.o
+libax5043.a: ax5043/generated/config.o
+libax5043.a: ax5043/generated/configcommon.o
+libax5043.a: ax5043/spi/ax5043spi.o
+ ar rcsv libax5043.a ax5043/generated/configcommon.o ax5043/generated/configtx.o ax5043/generated/configrx.o ax5043/generated/config.o ax5043/axradio/axradioinit.o ax5043/axradio/axradiomode.o ax5043/axradio/axradiotx.o ax5043/axradio/axradiorx.o ax5043/crc/crc.o ax5043/spi/ax5043spi.o ax5043/ax5043support/ax5043tx.o ax5043/ax5043support/ax5043init.o ax5043/ax5043support/ax5043rx.o
+
+radiochat: libax5043.a
+radiochat: chat/chat_main.o
+ gcc -o radiochat -pthread -L./ chat/chat_main.o -lwiringPi -lax5043
+
+radiopiglatin: libax5043.a
+radiopiglatin: piglatin/piglatin_main.o
+ gcc -o radiopiglatin -L./ piglatin/piglatin_main.o -lwiringPi -lax5043
+
+testax5043tx: libax5043.a
+testax5043tx: transmit/transmit_main.o
+ gcc -o testax5043tx -L./ transmit/transmit_main.o -lwiringPi -lax5043
+
+testax5043rx: libax5043.a
+testax5043rx: receive/receive_main.o
+ gcc -o testax5043rx -L./ receive/receive_main.o -lwiringPi -lax5043
+
+testax5043init: libax5043.a
+testax5043init: init/init_main.o
+ gcc -o testax5043init -L./ init/init_main.o -lwiringPi -lax5043
+
+testax50432freq: libax5043.a
+testax50432freq: transmit2freq/transmit2freq_main.o
+ gcc -o testax50432freq -L./ transmit2freq/transmit2freq_main.o -lwiringPi -lax5043
+
+ax5043/generated/configcommon.o: ax5043/generated/configcommon.c
+ax5043/generated/configcommon.o: ax5043/generated/configrx.h
+ax5043/generated/configcommon.o: ax5043/generated/configtx.h
+ax5043/generated/configcommon.o: ax5043/axradio/axradioinit.h
+ax5043/generated/configcommon.o: ax5043/axradio/axradioinit_p.h
+ cd ax5043/generated; gcc -pedantic -Wall -Wextra -c configcommon.c
+
+ax5043/generated/configrx.o: ax5043/generated/configrx.c
+ax5043/generated/configrx.o: ax5043/generated/configrx.h
+ax5043/generated/configrx.o: ax5043/axradio/axradioinit.h
+ax5043/generated/configrx.o: ax5043/axradio/axradioinit_p.h
+ cd ax5043/generated; gcc -pedantic -Wall -Wextra -c configrx.c
+
+ax5043/generated/configtx.o: ax5043/generated/configtx.c
+ax5043/generated/configtx.o: ax5043/generated/configtx.h
+ax5043/generated/configtx.o: ax5043/axradio/axradioinit.h
+ax5043/generated/configtx.o: ax5043/axradio/axradioinit_p.h
+ cd ax5043/generated; gcc -pedantic -Wall -Wextra -c configtx.c
+
+ax5043/generated/config.o: ax5043/generated/config.c
+ax5043/generated/config.o: ax5043/generated/config.h
+ax5043/generated/config.o: ax5043/axradio/axradioinit.h
+ax5043/generated/config.o: ax5043/axradio/axradioinit_p.h
+ax5043/generated/config.o: ax5043/spi/ax5043spi.h
+ax5043/generated/config.o: ax5043/spi/ax5043spi_p.h
+ax5043/generated/config.o: ax5043/crc/crc.h
+ cd ax5043/generated; gcc -pedantic -Wall -Wextra -c config.c
+
+ax5043/spi/ax5043spi.o: ax5043/spi/ax5043spi.c
+ax5043/spi/ax5043spi.o: ax5043/spi/ax5043spi.h
+ax5043/spi/ax5043spi.o: ax5043/spi/ax5043spi_p.h
+ cd ax5043/spi; gcc -pedantic -Wall -Wextra -c ax5043spi.c
+
+ax5043/ax5043support/ax5043init.o: ax5043/ax5043support/ax5043init.c
+ax5043/ax5043support/ax5043init.o: ax5043/ax5043support/ax5043init.h
+ax5043/ax5043support/ax5043init.o: ax5043/axradio/axradioinit.h
+ax5043/ax5043support/ax5043init.o: ax5043/axradio/axradioinit_p.h
+ax5043/ax5043support/ax5043init.o: ax5043/spi/ax5043spi.h
+ax5043/ax5043support/ax5043init.o: ax5043/spi/ax5043spi_p.h
+ cd ax5043/ax5043support; gcc -pedantic -Wall -Wextra -c ax5043init.c
+
+ax5043/ax5043support/ax5043rx.o: ax5043/ax5043support/ax5043rx.c
+ax5043/ax5043support/ax5043rx.o: ax5043/ax5043support/ax5043rx.h
+ax5043/ax5043support/ax5043rx.o: ax5043/axradio/axradioinit.h
+ax5043/ax5043support/ax5043rx.o: ax5043/axradio/axradioinit_p.h
+ax5043/ax5043support/ax5043rx.o: ax5043/spi/ax5043spi.h
+ax5043/ax5043support/ax5043rx.o: ax5043/spi/ax5043spi_p.h
+ cd ax5043/ax5043support; gcc -pedantic -Wall -Wextra -c ax5043rx.c
+
+ax5043/ax5043support/ax5043tx.o: ax5043/ax5043support/ax5043tx.c
+ax5043/ax5043support/ax5043tx.o: ax5043/ax5043support/ax5043tx.h
+ax5043/ax5043support/ax5043tx.o: ax5043/axradio/axradioinit.h
+ax5043/ax5043support/ax5043tx.o: ax5043/axradio/axradioinit_p.h
+ax5043/ax5043support/ax5043tx.o: ax5043/spi/ax5043spi.h
+ax5043/ax5043support/ax5043tx.o: ax5043/spi/ax5043spi_p.h
+ cd ax5043/ax5043support; gcc -pedantic -Wall -Wextra -c ax5043tx.c
+
+ax5043/axradio/axradioinit.o: ax5043/axradio/axradioinit.c
+ax5043/axradio/axradioinit.o: ax5043/axradio/axradioinit.h
+ax5043/axradio/axradioinit.o: ax5043/axradio/axradioinit_p.h
+ax5043/axradio/axradioinit.o: ax5043/ax5043support/ax5043init.h
+ax5043/axradio/axradioinit.o: ax5043/spi/ax5043spi.h
+ax5043/axradio/axradioinit.o: ax5043/spi/ax5043spi_p.h
+ax5043/axradio/axradioinit.o: ax5043/generated/config.h
+ax5043/axradio/axradioinit.o: ax5043/crc/crc.h
+ cd ax5043/axradio; gcc -pedantic -Wall -Wextra -c axradioinit.c
+
+ax5043/axradio/axradiomode.o: ax5043/axradio/axradiomode.c
+ax5043/axradio/axradiomode.o: ax5043/axradio/axradiomode.h
+ax5043/axradio/axradiomode.o: ax5043/axradio/axradiomode_p.h
+ax5043/axradio/axradiomode.o: ax5043/axradio/axradioinit.h
+ax5043/axradio/axradiomode.o: ax5043/axradio/axradioinit_p.h
+ax5043/axradio/axradiomode.o: ax5043/spi/ax5043spi.h
+ax5043/axradio/axradiomode.o: ax5043/spi/ax5043spi_p.h
+ax5043/axradio/axradiomode.o: ax5043/generated/config.h
+ cd ax5043/axradio; gcc -pedantic -Wall -Wextra -c axradiomode.c
+
+ax5043/axradio/axradiorx.o: ax5043/axradio/axradiorx.c
+ax5043/axradio/axradiorx.o: ax5043/axradio/axradiorx.h
+ax5043/axradio/axradiorx.o: ax5043/axradio/axradiorx_p.h
+ax5043/axradio/axradiorx.o: ax5043/ax5043support/ax5043rx.h
+ax5043/axradio/axradiorx.o: ax5043/axradio/axradioinit.h
+ax5043/axradio/axradiorx.o: ax5043/axradio/axradioinit_p.h
+ax5043/axradio/axradiorx.o: ax5043/spi/ax5043spi.h
+ax5043/axradio/axradiorx.o: ax5043/spi/ax5043spi_p.h
+ cd ax5043/axradio; gcc -pedantic -Wall -Wextra -c axradiorx.c
+
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradiotx.c
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradiotx.h
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradiotx_p.h
+ax5043/axradio/axradiotx.o: ax5043/ax5043support/ax5043tx.h
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradioinit.h
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradioinit_p.h
+ax5043/axradio/axradiotx.o: ax5043/spi/ax5043spi.h
+ax5043/axradio/axradiotx.o: ax5043/spi/ax5043spi_p.h
+ax5043/axradio/axradiotx.o: ax5043/generated/config.h
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradiomode.h
+ax5043/axradio/axradiotx.o: ax5043/axradio/axradiomode_p.h
+ax5043/axradio/axradiotx.o: ax5043/crc/crc.h
+ cd ax5043/axradio; gcc -pedantic -Wall -Wextra -c axradiotx.c
+
+ax5043/crc/crc.o: ax5043/crc/crc.c
+ax5043/crc/crc.o: ax5043/crc/crc.h
+ cd ax5043/crc; gcc -pedantic -Wall -Wextra -c crc.c
+
+chat/chat_main.o: chat/chat_main.c
+chat/chat_main.o: ax5043/spi/ax5043spi.h
+chat/chat_main.o: ax5043/spi/ax5043spi_p.h
+chat/chat_main.o: ax5043/axradio/axradioinit.h
+chat/chat_main.o: ax5043/axradio/axradioinit_p.h
+chat/chat_main.o: ax5043/axradio/axradiomode.h
+chat/chat_main.o: ax5043/axradio/axradiomode_p.h
+chat/chat_main.o: ax5043/axradio/axradiorx.h
+chat/chat_main.o: ax5043/axradio/axradiorx_p.h
+chat/chat_main.o: ax5043/axradio/axradiotx.h
+chat/chat_main.o: ax5043/axradio/axradiotx_p.h
+chat/chat_main.o: ax5043/generated/configtx.h
+ cd chat; gcc -I../ax5043 -pedantic -Wconversion -Wall -Wextra -c chat_main.c; cd ..
+
+piglatin/piglatin_main.o: piglatin/piglatin_main.c
+piglatin/piglatin_main.o: ax5043/spi/ax5043spi.h
+piglatin/piglatin_main.o: ax5043/spi/ax5043spi_p.h
+piglatin/piglatin_main.o: ax5043/axradio/axradioinit.h
+piglatin/piglatin_main.o: ax5043/axradio/axradioinit_p.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiomode.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiomode_p.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiorx.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiorx_p.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiotx.h
+piglatin/piglatin_main.o: ax5043/axradio/axradiotx_p.h
+piglatin/piglatin_main.o: ax5043/generated/configtx.h
+ cd piglatin; gcc -I ../ax5043 -pedantic -Wconversion -Wall -Wextra -c piglatin_main.c; cd ..
+
+receive/receive_main.o: receive/receive_main.c
+receive/receive_main.o: ax5043/axradio/axradioinit.h
+receive/receive_main.o: ax5043/axradio/axradioinit_p.h
+receive/receive_main.o: ax5043/spi/ax5043spi.h
+receive/receive_main.o: ax5043/spi/ax5043spi_p.h
+receive/receive_main.o: ax5043/axradio/axradiomode.h
+receive/receive_main.o: ax5043/axradio/axradiomode_p.h
+receive/receive_main.o: ax5043/axradio/axradiorx.h
+receive/receive_main.o: ax5043/axradio/axradiorx_p.h
+receive/receive_main.o: ax5043/generated/configrx.h
+ cd receive; gcc -I ../ax5043 -pedantic -Wconversion -Wall -Wextra -c receive_main.c; cd ..
+
+transmit/transmit_main.o: transmit/transmit_main.c
+transmit/transmit_main.o: ax5043/axradio/axradioinit.h
+transmit/transmit_main.o: ax5043/axradio/axradioinit_p.h
+transmit/transmit_main.o: ax5043/spi/ax5043spi.h
+transmit/transmit_main.o: ax5043/spi/ax5043spi_p.h
+transmit/transmit_main.o: ax5043/axradio/axradiomode.h
+transmit/transmit_main.o: ax5043/axradio/axradiomode_p.h
+transmit/transmit_main.o: ax5043/axradio/axradiotx.h
+transmit/transmit_main.o: ax5043/axradio/axradiotx_p.h
+transmit/transmit_main.o: ax5043/generated/configtx.h
+ cd transmit; gcc -I ../ax5043 -pedantic -Wconversion -Wall -Wextra -c transmit_main.c; cd ..
+
+transmit2freq/transmit2freq_main.o: transmit2freq/transmit2freq_main.c
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradioinit.h
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradioinit_p.h
+transmit2freq/transmit2freq_main.o: ax5043/spi/ax5043spi.h
+transmit2freq/transmit2freq_main.o: ax5043/spi/ax5043spi_p.h
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradiomode.h
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradiomode_p.h
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradiotx.h
+transmit2freq/transmit2freq_main.o: ax5043/axradio/axradiotx_p.h
+transmit2freq/transmit2freq_main.o: ax5043/generated/configtx.h
+ cd transmit2freq; gcc -I ../ax5043 -pedantic -Wconversion -Wall -Wextra -c transmit2freq_main.c; cd ..
+
+init/init_main.o: init/init_main.c
+init/init_main.o: ax5043/axradio/axradioinit.h
+init/init_main.o: ax5043/axradio/axradioinit_p.h
+init/init_main.o: ax5043/spi/ax5043spi.h
+init/init_main.o: ax5043/spi/ax5043spi_p.h
+ cd init; gcc -I ../ax5043 -pedantic -Wconversion -Wall -Wextra -c init_main.c; cd ..
+
diff --git a/RemoteSystemsTempFiles/.project b/RemoteSystemsTempFiles/.project
new file mode 100644
index 00000000..5447a64f
--- /dev/null
+++ b/RemoteSystemsTempFiles/.project
@@ -0,0 +1,12 @@
+
+
+ RemoteSystemsTempFiles
+
+
+
+
+
+
+ org.eclipse.rse.ui.remoteSystemsTempNature
+
+
diff --git a/ax5043/.cproject b/ax5043/.cproject
new file mode 100644
index 00000000..76a7eba6
--- /dev/null
+++ b/ax5043/.cproject
@@ -0,0 +1,113 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ax5043/.gitignore b/ax5043/.gitignore
new file mode 100644
index 00000000..3df573fe
--- /dev/null
+++ b/ax5043/.gitignore
@@ -0,0 +1 @@
+/Debug/
diff --git a/ax5043/.project b/ax5043/.project
new file mode 100644
index 00000000..533566cb
--- /dev/null
+++ b/ax5043/.project
@@ -0,0 +1,26 @@
+
+
+ framework
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/ax5043/.settings/language.settings.xml b/ax5043/.settings/language.settings.xml
new file mode 100644
index 00000000..f677357a
--- /dev/null
+++ b/ax5043/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ax5043/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ax5043/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 00000000..026efdd4
--- /dev/null
+++ b/ax5043/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,13 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/CPATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.1761616154/appendContributed=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/CPATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.lib.debug.88294304/appendContributed=true
diff --git a/ax5043/Doxyfile b/ax5043/Doxyfile
new file mode 100644
index 00000000..1fc2e046
--- /dev/null
+++ b/ax5043/Doxyfile
@@ -0,0 +1,2499 @@
+# Doxyfile 1.8.13
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all text
+# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv
+# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv
+# for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME = "Digital Transceiver for the Raspberry Pi"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER = 1.1
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF = "A platform for digital communication applications on the Raspberry Pi"
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO = images/logo55x55.png
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY = doc
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
+# directories (in 2 levels) under the output directory of each output format and
+# will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system.
+# The default value is: NO.
+
+CREATE_SUBDIRS = NO
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,
+# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),
+# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,
+# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),
+# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,
+# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,
+# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,
+# Ukrainian and Vietnamese.
+# The default value is: English.
+
+OUTPUT_LANGUAGE = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+# The default value is: YES.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
+
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# doxygen will generate a detailed section even if there is only a brief
+# description.
+# The default value is: NO.
+
+ALWAYS_DETAILED_SEC = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+# The default value is: NO.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
+
+FULL_PATH_NAMES = YES
+
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
+
+STRIP_FROM_PATH =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
+
+JAVADOC_AUTOBRIEF = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:\n"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". You can put \n's in the value part of an alias to insert
+# newlines.
+
+ALIASES =
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only).
+# A mapping has the form "name=value". For example adding "class=itcl::class"
+# will allow you to use the command class in the itcl::class meaning.
+
+TCL_SUBST =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, Javascript,
+# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran:
+# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran:
+# Fortran. In the later case the parser tries to guess whether the code is fixed
+# or free formatted code, this is the default for Fortran type files), VHDL. For
+# instance to make doxygen treat .inc files as Fortran files (default is PHP),
+# and .f files as C (default is Fortran), use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen.
+
+EXTENSION_MAPPING =
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See http://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT = YES
+
+# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up
+# to that level are automatically included in the table of contents, even if
+# they do not have an id attribute.
+# Note: This feature currently applies only to Markdown headings.
+# Minimum value: 0, maximum value: 99, default value: 0.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+TOC_INCLUDE_HEADINGS = 0
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC = NO
+
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
+
+GROUP_NESTED_COMPOUNDS = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE = NO
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE = NO
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# (class|struct|union) declarations. If set to NO, these declarations will be
+# included in the documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
+# names in lower-case letters. If set to YES, upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+# The default value is: system dependent.
+
+CASE_SENSE_NAMES = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if ... \endif and \cond
+# ... \endcond blocks.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE =
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES =
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some parameters
+# in a documented function, or documenting parameters that don't exist or using
+# markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong or incomplete
+# parameter documentation, but not about the absence of documentation.
+# The default value is: NO.
+
+WARN_NO_PARAMDOC = NO
+
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered.
+# The default value is: NO.
+
+WARN_AS_ERROR = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr).
+
+WARN_LOGFILE =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
+
+INPUT = README.md
+INPUT += axradio/axradioinit_p.h
+INPUT += axradio/axradiomode_p.h
+INPUT += axradio/axradiorx_p.h
+INPUT += axradio/axradiotx_p.h
+INPUT += spi/ax5043spi_p.h
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see: http://www.gnu.org/software/libiconv) for the list of
+# possible encodings.
+# The default value is: UTF-8.
+
+INPUT_ENCODING = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc,
+# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08,
+# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf.
+
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.idl \
+ *.ddl \
+ *.odl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.cs \
+ *.d \
+ *.php \
+ *.php4 \
+ *.php5 \
+ *.phtml \
+ *.inc \
+ *.m \
+ *.markdown \
+ *.md \
+ *.mm \
+ *.dox \
+ *.py \
+ *.pyw \
+ *.f90 \
+ *.f95 \
+ *.f03 \
+ *.f08 \
+ *.f \
+ *.for \
+ *.tcl \
+ *.vhd \
+ *.vhdl \
+ *.ucf \
+ *.qsf
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+#
+#
+# where is the value of the INPUT_FILTER tag, and is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+INPUT_FILTER =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+FILTER_PATTERNS =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS =
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE = README.md
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# function all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see http://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS = NO
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the
+# cost of reduced performance. This can be particularly helpful with template
+# rich C++ code for which doxygen's built-in parser lacks the necessary type
+# information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX = YES
+
+# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
+# which the alphabetical index list will be split.
+# Minimum value: 1, maximum value: 20, default value: 5.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET =
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a colorwheel, see
+# http://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use grayscales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP = NO
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see: http://developer.apple.com/tools/xcode/), introduced with
+# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
+# Makefile in the HTML output directory. Running make will produce the docset in
+# that directory and running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME = "Doxygen generated docs"
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
+# Windows.
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE =
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION =
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the master .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING =
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-
+# folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME =
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
+# filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS =
+
+# The QHG_LOCATION tag can be used to specify the location of Qt's
+# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
+# generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine-tune the look of the index. As an example, the default style
+# sheet generated by doxygen has an example that shows how to put an image at
+# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
+# the same information as the tab index, you could consider setting
+# DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW = NO
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are not
+# supported properly for IE 6.0, but are supported on all modern browsers.
+#
+# Note that when changing this option you need to delete any form_*.png files in
+# the HTML output directory before the changes have effect.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_TRANSPARENT = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# http://www.mathjax.org) which uses client side Javascript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX = NO
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. See the MathJax site (see:
+# http://docs.mathjax.org/en/latest/output.html) for more details.
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility), NativeMML (i.e. MathML) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from http://www.mathjax.org before deployment.
+# The default value is: http://cdn.mathjax.org/mathjax/latest.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS =
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use + S
+# (what the is depends on the OS and browser, but it is typically
+# , /, or both). Inside the search box use the to jump into the search results window, the results can be navigated
+# using the . Press to select an item or to cancel
+# the search. The filter options can be selected when the cursor is inside the
+# search box by pressing +. Also here use the
+# to select a filter and or to activate or cancel the filter
+# option.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SEARCHENGINE = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a web server instead of a web client using Javascript. There
+# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
+# setting. When disabled, doxygen will generate a PHP script for searching and
+# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
+# and searching needs to be provided by external tools. See the section
+# "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SERVER_BASED_SEARCH = NO
+
+# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
+# script for searching. Instead the search results are written to an XML file
+# which needs to be processed by an external indexer. Doxygen will invoke an
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
+# search results.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/).
+#
+# See the section "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH = NO
+
+# The SEARCHENGINE_URL should point to a search engine hosted by a web server
+# which will return the search results when EXTERNAL_SEARCH is enabled.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: http://xapian.org/). See the section "External Indexing and
+# Searching" for details.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHENGINE_URL =
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
+# search data is written to a file for indexing by an external tool. With the
+# SEARCHDATA_FILE tag the name of this file can be specified.
+# The default file is: searchdata.xml.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHDATA_FILE = searchdata.xml
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
+# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
+# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
+# projects and redirect the results back to the right project.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH_ID =
+
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
+# projects other than the one defined by this configuration file, but that are
+# all added to the same external search index. Each project needs to have a
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
+# to a relative location where the documentation can be found. The format is:
+# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTRA_SEARCH_MAPPINGS =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# The default value is: YES.
+
+GENERATE_LATEX = YES
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked.
+#
+# Note that when enabling USE_PDFLATEX this option is only used for generating
+# bitmaps for formulas in the HTML output, but not in the Makefile that is
+# written to the output directory.
+# The default file is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
+# index for LaTeX.
+# The default file is: makeindex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used by the
+# printer.
+# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
+# 14 inches) and executive (7.25 x 10.5 inches).
+# The default value is: a4.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PAPER_TYPE = a4
+
+# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
+# that should be included in the LaTeX output. The package can be specified just
+# by its name or with the correct syntax as to be used with the LaTeX
+# \usepackage command. To get the times font for instance you can specify :
+# EXTRA_PACKAGES=times or EXTRA_PACKAGES={times}
+# To use the option intlimits with the amsmath package you can specify:
+# EXTRA_PACKAGES=[intlimits]{amsmath}
+# If left blank no extra packages will be included.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
+# generated LaTeX document. The header should contain everything until the first
+# chapter. If it is left blank doxygen will generate a standard header. See
+# section "Doxygen usage" for information on how to let doxygen write the
+# default header to a separate file.
+#
+# Note: Only use a user-defined header if you know what you are doing! The
+# following commands have a special meaning inside the header: $title,
+# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
+# $projectbrief, $projectlogo. Doxygen will replace $title with the empty
+# string, for the replacement values of the other commands the user is referred
+# to HTML_HEADER.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HEADER =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
+# generated LaTeX document. The footer should contain everything after the last
+# chapter. If it is left blank doxygen will generate a standard footer. See
+# LATEX_HEADER for more information on how to generate a default footer and what
+# special commands can be used inside the footer.
+#
+# Note: Only use a user-defined footer if you know what you are doing!
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_FOOTER =
+
+# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# LaTeX style sheets that are included after the standard style sheets created
+# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list).
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_STYLESHEET =
+
+# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the LATEX_OUTPUT output
+# directory. Note that the files will be copied as-is; there are no commands or
+# markers available.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_FILES =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
+# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
+# contain links (just like the HTML output) instead of page references. This
+# makes the output suitable for online browsing using a PDF viewer.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
+# the PDF file directly from the LaTeX files. Set this option to YES, to get a
+# higher quality PDF documentation.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+USE_PDFLATEX = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
+# command to the generated LaTeX files. This will instruct LaTeX to keep running
+# if errors occur, instead of asking the user for help. This option is also used
+# when generating formulas in HTML.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BATCHMODE = NO
+
+# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# index chapters (such as File Index, Compound Index, etc.) in the output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HIDE_INDICES = NO
+
+# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
+# code with syntax highlighting in the LaTeX output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_SOURCE_CODE = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+# bibliography, e.g. plainnat, or ieeetr. See
+# http://en.wikipedia.org/wiki/BibTeX and \cite for more info.
+# The default value is: plain.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BIB_STYLE = plain
+
+# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated
+# page will contain the date and time when the page was generated. Setting this
+# to NO can help when comparing the output of multiple runs.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_TIMESTAMP = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# RTF output is optimized for Word 97 and may not look too pretty with other RTF
+# readers/editors.
+# The default value is: NO.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: rtf.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
+# contain hyperlink fields. The RTF file will contain links (just like the HTML
+# output) instead of page references. This makes the output suitable for online
+# browsing using Word or some other Word compatible readers that support those
+# fields.
+#
+# Note: WordPad (write) and others do not support links.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_HYPERLINKS = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's config
+# file, i.e. a series of assignments. You only have to provide replacements,
+# missing definitions are set to their default value.
+#
+# See also section "Doxygen usage" for information on how to generate the
+# default style sheet that doxygen normally uses.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an RTF document. Syntax is
+# similar to doxygen's config file. A template extensions file can be generated
+# using doxygen -e rtf extensionFile.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_EXTENSIONS_FILE =
+
+# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code
+# with syntax highlighting in the RTF output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_SOURCE_CODE = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# classes and files.
+# The default value is: NO.
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it. A directory man3 will be created inside the directory specified by
+# MAN_OUTPUT.
+# The default directory is: man.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to the generated
+# man pages. In case the manual section does not start with a number, the number
+# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
+# optional.
+# The default value is: .3.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_EXTENSION = .3
+
+# The MAN_SUBDIR tag determines the name of the directory created within
+# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
+# MAN_EXTENSION with the initial . removed.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_SUBDIR =
+
+# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# will generate one additional man file for each entity documented in the real
+# man page(s). These additional files only source the real man page, but without
+# them the man command would be unable to find the correct page.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# captures the structure of the code including all documentation.
+# The default value is: NO.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: xml.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_OUTPUT = xml
+
+# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program
+# listings (including syntax highlighting and cross-referencing information) to
+# the XML output. Note that enabling this will significantly increase the size
+# of the XML output.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_XML is set to YES.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files
+# that can be used to generate PDF.
+# The default value is: NO.
+
+GENERATE_DOCBOOK = NO
+
+# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in
+# front of it.
+# The default directory is: docbook.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_OUTPUT = docbook
+
+# If the DOCBOOK_PROGRAMLISTING tag is set to YES, doxygen will include the
+# program listings (including syntax highlighting and cross-referencing
+# information) to the DOCBOOK output. Note that enabling this will significantly
+# increase the size of the DOCBOOK output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
+
+DOCBOOK_PROGRAMLISTING = NO
+
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an
+# AutoGen Definitions (see http://autogen.sf.net) file that captures the
+# structure of the code including all documentation. Note that this feature is
+# still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module
+# file that captures the structure of the code including all documentation.
+#
+# Note that this feature is still experimental and incomplete at the moment.
+# The default value is: NO.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary
+# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
+# output from the Perl module output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES, the Perl module output will be nicely
+# formatted so it can be parsed by a human reader. This is useful if you want to
+# understand what is going on. On the other hand, if this tag is set to NO, the
+# size of the Perl module output will be much smaller and Perl will parse it
+# just the same.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file are
+# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful
+# so different doxyrules.make files included by the same Makefile don't
+# overwrite each other's variables.
+# This tag requires that the tag GENERATE_PERLMOD is set to YES.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES, doxygen will evaluate all
+# C-preprocessor directives found in the sources and include files.
+# The default value is: YES.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES, doxygen will expand all macro names
+# in the source code. If set to NO, only conditional compilation will be
+# performed. Macro expansion can be done in a controlled way by setting
+# EXPAND_ONLY_PREDEF to YES.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+MACRO_EXPANSION = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then
+# the macro expansion is limited to the macros specified with the PREDEFINED and
+# EXPAND_AS_DEFINED tags.
+# The default value is: NO.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_ONLY_PREDEF = NO
+
+# If the SEARCH_INCLUDES tag is set to YES, the include files in the
+# INCLUDE_PATH will be searched if a #include is found.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by the
+# preprocessor.
+# This tag requires that the tag SEARCH_INCLUDES is set to YES.
+
+INCLUDE_PATH =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will be
+# used.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that are
+# defined before the preprocessor is started (similar to the -D option of e.g.
+# gcc). The argument of the tag is a list of macros of the form: name or
+# name=definition (no spaces). If the definition and the "=" are omitted, "=1"
+# is assumed. To prevent a macro definition from being undefined via #undef or
+# recursively expanded use the := operator instead of the = operator.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+PREDEFINED =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
+# tag can be used to specify a list of macro names that should be expanded. The
+# macro definition that is found in the sources will be used. Use the PREDEFINED
+# tag if you want to use a different macro definition that overrules the
+# definition found in the source code.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
+# remove all references to function-like macros that are alone on a line, have
+# an all uppercase name, and do not end with a semicolon. Such function macros
+# are typically used for boiler-plate code, and will confuse the parser if not
+# removed.
+# The default value is: YES.
+# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES tag can be used to specify one or more tag files. For each tag
+# file the location of the external documentation should be added. The format of
+# a tag file without this location is as follows:
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where loc1 and loc2 can be relative or absolute paths or URLs. See the
+# section "Linking to external documentation" for more information about the use
+# of tag files.
+# Note: Each tag file must have a unique name (where the name does NOT include
+# the path). If a tag file is not located in the directory in which doxygen is
+# run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
+# tag file that is based on the input files it reads. See section "Linking to
+# external documentation" for more information about the usage of tag files.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES, all external class will be listed in
+# the class index. If set to NO, only the inherited external classes will be
+# listed.
+# The default value is: NO.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES, all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will be
+# listed.
+# The default value is: YES.
+
+EXTERNAL_GROUPS = YES
+
+# If the EXTERNAL_PAGES tag is set to YES, all external pages will be listed in
+# the related pages index. If set to NO, only the current project's pages will
+# be listed.
+# The default value is: YES.
+
+EXTERNAL_PAGES = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of 'which perl').
+# The default file (with absolute path) is: /usr/bin/perl.
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES, doxygen will generate a class diagram
+# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
+# NO turns the diagrams off. Note that this option also works with HAVE_DOT
+# disabled, but it is recommended to install and use dot, since it yields more
+# powerful graphs.
+# The default value is: YES.
+
+CLASS_DIAGRAMS = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see:
+# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH =
+
+# You can include diagrams made with dia in doxygen documentation. Doxygen will
+# then run dia to produce the diagram and insert it in the documentation. The
+# DIA_PATH tag allows you to specify the directory where the dia binary resides.
+# If left empty dia is assumed to be found in the default search path.
+
+DIA_PATH =
+
+# If set to YES the inheritance and collaboration graphs will hide inheritance
+# and usage relations if the target is undocumented or is not a class.
+# The default value is: YES.
+
+HIDE_UNDOC_RELATIONS = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz (see:
+# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
+# Bell Labs. The other options in this section have no effect if this option is
+# set to NO
+# The default value is: YES.
+
+HAVE_DOT = YES
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
+# to run in parallel. When set to 0 doxygen will base this on the number of
+# processors available in the system. You can set it explicitly to a value
+# larger than 0 to get control over the balance between CPU load and processing
+# speed.
+# Minimum value: 0, maximum value: 32, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_NUM_THREADS = 0
+
+# When you want a differently looking font in the dot files that doxygen
+# generates you can specify the font name using DOT_FONTNAME. You need to make
+# sure dot is able to find the font, which can be done by putting it in a
+# standard location or by setting the DOTFONTPATH environment variable or by
+# setting DOT_FONTPATH to the directory containing the font.
+# The default value is: Helvetica.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTNAME = Helvetica
+
+# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of
+# dot graphs.
+# Minimum value: 4, maximum value: 24, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTSIZE = 10
+
+# By default doxygen will tell dot to use the default font as specified with
+# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set
+# the path where dot can find it using this tag.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTPATH =
+
+# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for
+# each documented class showing the direct and indirect inheritance relations.
+# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# graph for each documented class showing the direct and indirect implementation
+# dependencies (inheritance, containment, and class references variables) of the
+# class with other documented classes.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+COLLABORATION_GRAPH = YES
+
+# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
+# groups, showing the direct groups dependencies.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GROUP_GRAPHS = YES
+
+# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LOOK = NO
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside the
+# class node. If there are many fields or methods and many nodes the graph may
+# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the
+# number of items for each type to make the size more manageable. Set this to 0
+# for no limit. Note that the threshold may be exceeded by 50% before the limit
+# is enforced. So when you set the threshold to 10, up to 15 fields may appear,
+# but if the number exceeds 15, the total amount of fields shown is limited to
+# 10.
+# Minimum value: 0, maximum value: 100, default value: 10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LIMIT_NUM_FIELDS = 10
+
+# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and
+# collaboration graphs will show the relations between templates and their
+# instances.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+TEMPLATE_RELATIONS = NO
+
+# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
+# YES then doxygen will generate a graph for each documented file showing the
+# direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDE_GRAPH = YES
+
+# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
+# set to YES then doxygen will generate a graph for each documented file showing
+# the direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command. Disabling a call graph can be
+# accomplished by means of the command \hidecallgraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALL_GRAPH = NO
+
+# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable caller graphs for selected
+# functions only using the \callergraph command. Disabling a caller graph can be
+# accomplished by means of the command \hidecallergraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALLER_GRAPH = NO
+
+# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical
+# hierarchy of all classes instead of a textual one.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GRAPHICAL_HIERARCHY = YES
+
+# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# dependencies a directory has on other directories in a graphical way. The
+# dependency relations are determined by the #include relations between the
+# files in the directories.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DIRECTORY_GRAPH = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. For an explanation of the image formats see the section
+# output formats in the documentation of the dot tool (Graphviz (see:
+# http://www.graphviz.org/)).
+# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
+# to make the SVG files visible in IE 9+ (other browsers do not have this
+# requirement).
+# Possible values are: png, png:cairo, png:cairo:cairo, png:cairo:gd, png:gd,
+# png:gd:gd, jpg, jpg:cairo, jpg:cairo:gd, jpg:gd, jpg:gd:gd, gif, gif:cairo,
+# gif:cairo:gd, gif:gd, gif:gd:gd, svg, png:gd, png:gd:gd, png:cairo,
+# png:cairo:gd, png:cairo:cairo, png:cairo:gdiplus, png:gdiplus and
+# png:gdiplus:gdiplus.
+# The default value is: png.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_IMAGE_FORMAT = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+# enable generation of interactive SVG images that allow zooming and panning.
+#
+# Note that this requires a modern browser other than Internet Explorer. Tested
+# and working are Firefox, Chrome, Safari, and Opera.
+# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make
+# the SVG files visible. Older versions of IE do not have SVG support.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INTERACTIVE_SVG = NO
+
+# The DOT_PATH tag can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the \dotfile
+# command).
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOTFILE_DIRS =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
+
+MSCFILE_DIRS =
+
+# The DIAFILE_DIRS tag can be used to specify one or more directories that
+# contain dia files that are included in the documentation (see the \diafile
+# command).
+
+DIAFILE_DIRS =
+
+# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# path where java can find the plantuml.jar file. If left blank, it is assumed
+# PlantUML is not used or called during a preprocessing step. Doxygen will
+# generate a warning when it encounters a \startuml command in this case and
+# will not generate output for the diagram.
+
+PLANTUML_JAR_PATH =
+
+# When using plantuml, the PLANTUML_CFG_FILE tag can be used to specify a
+# configuration file for plantuml.
+
+PLANTUML_CFG_FILE =
+
+# When using plantuml, the specified paths are searched for files specified by
+# the !include statement in a plantuml block.
+
+PLANTUML_INCLUDE_PATH =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
+# that will be shown in the graph. If the number of nodes in a graph becomes
+# larger than this value, doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that doxygen if the number of direct
+# children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
+# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# Minimum value: 0, maximum value: 10000, default value: 50.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs
+# generated by dot. A depth value of 3 means that only nodes reachable from the
+# root by following a path via at most 3 edges will be shown. Nodes that lay
+# further from the root node will be omitted. Note that setting this option to 1
+# or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+# Minimum value: 0, maximum value: 1000, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not seem
+# to support this out of the box.
+#
+# Warning: Depending on the platform used, enabling this option may lead to
+# badly anti-aliased labels on the edges of a graph (i.e. they become hard to
+# read).
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_TRANSPARENT = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10) support
+# this, this feature is disabled by default.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_MULTI_TARGETS = NO
+
+# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# explaining the meaning of the various boxes and arrows in the dot generated
+# graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate dot
+# files that are used to generate the various graphs.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_CLEANUP = YES
diff --git a/ax5043/README.md b/ax5043/README.md
new file mode 100644
index 00000000..2fef8e7a
--- /dev/null
+++ b/ax5043/README.md
@@ -0,0 +1,16 @@
+## Overview
+
+The AX5043 library provides an interface to program the transceiver. The library is currently configured with the following settings:
+
+- Carrier Frequency - 435.3 MHz
+- Symbol Rate - 4.8 kS/s
+- Modulation - GFSK
+- Transmit Deviation - 13.6 kHz
+- Transmit Power - 15.0 dBm
+- Receive Bandwidth - 28.2 kHz
+- Encoding: HDLC with FEC
+- Error Detection: CRC-16
+
+## Next Steps
+
+Over time, the AX5043 library will have new functions to change these settings.
diff --git a/ax5043/ax5043support/ax5043init.c b/ax5043/ax5043support/ax5043init.c
new file mode 100644
index 00000000..7edd4c66
--- /dev/null
+++ b/ax5043/ax5043support/ax5043init.c
@@ -0,0 +1,65 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#include "ax5043init.h"
+
+#include
+
+#include "../axradio/axradioinit.h"
+#include "../spi/ax5043spi.h"
+
+uint8_t ax5043_reset(void)
+{
+ //printf("INFO: Resetting AX5043 (ax5043_reset)\n");
+ uint8_t i;
+ // Initialize Interface
+ // Reset Device
+ ax5043WriteReg(AX5043_PWRMODE, 0x80);
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN);
+ // Wait some time for regulator startup
+ usleep(10000);
+
+ // Check Scratch
+ i = ax5043ReadReg(AX5043_SILICONREVISION);
+ i = ax5043ReadReg(AX5043_SILICONREVISION);
+
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+
+ ax5043WriteReg(AX5043_SCRATCH, 0x55);
+ if (ax5043ReadReg(AX5043_SCRATCH) != 0x55)
+ return RADIO_ERR_COMM;
+
+ ax5043WriteReg(AX5043_SCRATCH, 0xAA);
+ if (ax5043ReadReg(AX5043_SCRATCH) != 0xAA)
+ return RADIO_ERR_COMM;
+
+ return RADIO_OK;
+}
+
+
diff --git a/ax5043/ax5043support/ax5043init.h b/ax5043/ax5043support/ax5043init.h
new file mode 100644
index 00000000..4256f9ab
--- /dev/null
+++ b/ax5043/ax5043support/ax5043init.h
@@ -0,0 +1,36 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#ifndef AX5043_AX5043INIT_H_
+#define AX5043_AX5043INIT_H_
+
+#include
+
+uint8_t ax5043_reset(void);
+
+#endif /* AX5043_AX5043INIT_H_ */
diff --git a/ax5043/ax5043support/ax5043rx.c b/ax5043/ax5043support/ax5043rx.c
new file mode 100644
index 00000000..a0a3db01
--- /dev/null
+++ b/ax5043/ax5043support/ax5043rx.c
@@ -0,0 +1,41 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#include "ax5043rx.h"
+
+#include "../axradio/axradioinit.h"
+#include "../spi/ax5043spi.h"
+
+uint8_t ax5043_readfifo(uint8_t axradio_rxbuffer[], uint8_t len) {
+ uint8_t loc = 0;
+ while (len--) {
+ axradio_rxbuffer[loc++] = ax5043ReadReg(AX5043_FIFODATA);
+ }
+ return loc;
+}
+
diff --git a/ax5043/ax5043support/ax5043rx.h b/ax5043/ax5043support/ax5043rx.h
new file mode 100644
index 00000000..3c8092c0
--- /dev/null
+++ b/ax5043/ax5043support/ax5043rx.h
@@ -0,0 +1,37 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#ifndef AX5043SUPPORT_AX5043RX_H_
+#define AX5043SUPPORT_AX5043RX_H_
+
+#include
+
+uint8_t ax5043_readfifo(uint8_t axradio_rxbuffer[], uint8_t len);
+
+
+#endif /* AX5043SUPPORT_AX5043RX_H_ */
diff --git a/ax5043/ax5043support/ax5043tx.c b/ax5043/ax5043support/ax5043tx.c
new file mode 100644
index 00000000..1d016e3b
--- /dev/null
+++ b/ax5043/ax5043support/ax5043tx.c
@@ -0,0 +1,42 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#include "ax5043tx.h"
+
+#include "../axradio/axradioinit.h"
+#include "../spi/ax5043spi.h"
+
+void ax5043_writefifo(const uint8_t *ptr, uint8_t len)
+{
+ if (!len)
+ return;
+ do {
+ ax5043WriteReg(AX5043_FIFODATA, *ptr++);
+ } while (--len);
+}
+
diff --git a/ax5043/ax5043support/ax5043tx.h b/ax5043/ax5043support/ax5043tx.h
new file mode 100644
index 00000000..ed629845
--- /dev/null
+++ b/ax5043/ax5043support/ax5043tx.h
@@ -0,0 +1,36 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The Lib MF documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#ifndef AX5043SUPPORT_AX5043TX_H_
+#define AX5043SUPPORT_AX5043TX_H_
+
+#include
+
+void ax5043_writefifo(const uint8_t *ptr, uint8_t len);
+
+#endif /* AX5043SUPPORT_AX5043TX_H_ */
diff --git a/ax5043/axradio/axradioinit.c b/ax5043/axradio/axradioinit.c
new file mode 100644
index 00000000..e1cce8dd
--- /dev/null
+++ b/ax5043/axradio/axradioinit.c
@@ -0,0 +1,440 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "axradioinit.h"
+
+#include
+
+#include "axradioinit_p.h"
+#include "../ax5043support/ax5043init.h"
+#include "../crc/crc.h"
+#include "../generated/config.h"
+#include "../spi/ax5043spi_p.h"
+
+volatile uint8_t axradio_mode = AXRADIO_MODE_UNINIT;
+volatile axradio_trxstate_t axradio_trxstate = trxstate_off;
+
+struct axradio_address_mask axradio_localaddr;
+uint8_t axradio_rxbuffer[PKTDATA_BUFLEN];
+
+extern const uint32_t axradio_phy_chanfreq[];
+extern const uint8_t axradio_phy_chanpllrnginit[];
+extern uint8_t axradio_phy_chanpllrng[];
+extern const uint8_t axradio_phy_vcocalib;
+extern uint8_t axradio_phy_chanvcoi[];
+extern const uint8_t axradio_phy_chanvcoiinit[];
+extern const uint8_t axradio_framing_swcrclen;
+extern const uint8_t axradio_phy_innerfreqloop;
+extern const uint8_t axradio_phy_pn9;
+extern const uint8_t axradio_framing_addrlen;
+extern const uint8_t axradio_framing_destaddrpos;
+
+static void axradio_setaddrregs(void)
+{
+ uint8_t regValue;
+
+ ax5043WriteReg(AX5043_PKTADDR0, axradio_localaddr.addr[0]);
+ ax5043WriteReg(AX5043_PKTADDR1, axradio_localaddr.addr[1]);
+ ax5043WriteReg(AX5043_PKTADDR2, axradio_localaddr.addr[2]);
+ ax5043WriteReg(AX5043_PKTADDR3, axradio_localaddr.addr[3]);
+
+ ax5043WriteReg(AX5043_PKTADDRMASK0, axradio_localaddr.mask[0]);
+ ax5043WriteReg(AX5043_PKTADDRMASK1, axradio_localaddr.mask[1]);
+ ax5043WriteReg(AX5043_PKTADDRMASK2, axradio_localaddr.mask[2]);
+ ax5043WriteReg(AX5043_PKTADDRMASK3, axradio_localaddr.mask[3]);
+
+ if (axradio_phy_pn9 && axradio_framing_addrlen) {
+ uint16_t pn = 0x1ff;
+ uint8_t inv = -(ax5043ReadReg(AX5043_ENCODING) & 0x01);
+ if (axradio_framing_destaddrpos != 0xff) {
+ pn = pn9_advance_bits(pn, axradio_framing_destaddrpos << 3);
+ }
+ regValue = ax5043ReadReg(AX5043_PKTADDR0);
+ regValue ^= pn ^ inv;
+ ax5043WriteReg(AX5043_PKTADDR0, regValue);
+ pn = pn9_advance_byte(pn);
+
+ regValue = ax5043ReadReg(AX5043_PKTADDR1);
+ regValue ^= pn ^ inv;
+ ax5043WriteReg(AX5043_PKTADDR1, regValue);
+ pn = pn9_advance_byte(pn);
+
+ regValue = ax5043ReadReg(AX5043_PKTADDR2);
+ regValue ^= pn ^ inv;
+ ax5043WriteReg(AX5043_PKTADDR2, regValue);
+ pn = pn9_advance_byte(pn);
+
+ regValue = ax5043ReadReg(AX5043_PKTADDR3);
+ regValue ^= pn ^ inv;
+ ax5043WriteReg(AX5043_PKTADDR3, regValue);
+ }
+}
+
+static void ax5043_init_registers(void)
+{
+ uint8_t regValue;
+
+ ax5043_set_registers();
+
+ regValue = ax5043ReadReg(AX5043_PKTLENOFFSET);
+ regValue += axradio_framing_swcrclen; // add len offs for software CRC16 (used for both, fixed and variable length packets
+ ax5043WriteReg(AX5043_PKTLENOFFSET, regValue);
+
+ ax5043WriteReg(AX5043_PINFUNCIRQ, 0x00); // No IRQ used for now
+ ax5043WriteReg(AX5043_PKTSTOREFLAGS, axradio_phy_innerfreqloop ? 0x13 : 0x15); // store RF offset, RSSI and delimiter timing
+ axradio_setaddrregs();
+}
+
+void axradio_wait_for_xtal(void) {
+ //printf("INFO: Waiting for crystal (axradio_wait_for_xtal)\n");
+ while ((ax5043ReadReg(AX5043_XTALSTATUS) & 0x01) == 0) {
+ usleep(1000);
+ }
+ //printf("INFO: Crystal is ready\n");
+}
+
+static int16_t axradio_tunevoltage(void)
+{
+ int16_t r = 0;
+ uint8_t cnt = 64;
+ do {
+ ax5043WriteReg(AX5043_GPADCCTRL, 0x84);
+ do {} while (ax5043ReadReg(AX5043_GPADCCTRL) & 0x80);
+ } while (--cnt);
+ cnt = 32;
+ do {
+ ax5043WriteReg(AX5043_GPADCCTRL, 0x84);
+ do {} while (ax5043ReadReg(AX5043_GPADCCTRL) & 0x80);
+ {
+ int16_t x = ax5043ReadReg(AX5043_GPADC13VALUE1) & 0x03;
+ x <<= 8;
+ x |= ax5043ReadReg(AX5043_GPADC13VALUE0);
+ r += x;
+ }
+ } while (--cnt);
+ return r;
+}
+
+static uint8_t axradio_adjustvcoi(uint8_t rng)
+{
+ uint8_t offs;
+ uint8_t bestrng;
+ uint16_t bestval = ~0;
+ rng &= 0x7F;
+ bestrng = rng;
+ for (offs = 0; offs != 16; ++offs) {
+ uint16_t val;
+ if (!((uint8_t)(rng + offs) & 0xC0)) {
+ ax5043WriteReg(AX5043_PLLVCOI, 0x80 | (rng + offs));
+ val = axradio_tunevoltage();
+ if (val < bestval) {
+ bestval = val;
+ bestrng = rng + offs;
+ }
+ }
+ if (!offs)
+ continue;
+ if (!((uint8_t)(rng - offs) & 0xC0)) {
+ ax5043WriteReg(AX5043_PLLVCOI, 0x80 | (rng - offs));
+ val = axradio_tunevoltage();
+ if (val < bestval) {
+ bestval = val;
+ bestrng = rng - offs;
+ }
+ }
+ }
+ // if we hit the lower rail, do not change anything
+ if (bestval <= 0x0010)
+ return rng | 0x80;
+ return bestrng | 0x80;
+}
+
+static uint8_t axradio_calvcoi(void)
+{
+ uint8_t i;
+ uint8_t r = 0;
+ uint16_t vmin = 0xffff;
+ uint16_t vmax = 0x0000;
+ for (i = 0x40; i != 0;) {
+ uint16_t curtune;
+ --i;
+ ax5043WriteReg(AX5043_PLLVCOI, 0x80 | i);
+ ax5043ReadReg(AX5043_PLLRANGINGA); // clear PLL lock loss
+ curtune = axradio_tunevoltage();
+ ax5043ReadReg(AX5043_PLLRANGINGA); // clear PLL lock loss
+ ((uint16_t *)axradio_rxbuffer)[i] = curtune;
+ if (curtune > vmax)
+ vmax = curtune;
+ if (curtune < vmin) {
+ vmin = curtune;
+ // check whether the PLL is locked
+ if (!(0xC0 & (uint8_t)~ax5043ReadReg(AX5043_PLLRANGINGA)))
+ r = i | 0x80;
+ }
+ }
+ if (!(r & 0x80) || vmax >= 0xFF00 || vmin < 0x0100 || vmax - vmin < 0x6000)
+ return 0;
+ return r;
+}
+
+uint8_t axradio_init(void)
+{
+ uint8_t regValue;
+
+ axradio_mode = AXRADIO_MODE_UNINIT;
+ axradio_trxstate = trxstate_off;
+ if (ax5043_reset())
+ return AXRADIO_ERR_NOCHIP;
+ ax5043_init_registers();
+ ax5043_set_registers_tx();
+ ax5043WriteReg(AX5043_PLLLOOP, 0x09); // default 100kHz loop BW for ranging
+ ax5043WriteReg(AX5043_PLLCPI, 0x08);
+
+ // range all channels
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_XTAL_ON);
+ ax5043WriteReg(AX5043_MODULATION, 0x08);
+ ax5043WriteReg(AX5043_FSKDEV2, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV1, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV0, 0x00);
+ axradio_wait_for_xtal();
+
+ {
+ uint32_t f = axradio_phy_chanfreq[0];
+ ax5043WriteReg(AX5043_FREQA0, f);
+ ax5043WriteReg(AX5043_FREQA1, f >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f >> 24);
+ }
+ axradio_trxstate = trxstate_pll_ranging;
+ {
+ uint8_t r;
+ if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available
+ r = axradio_phy_chanpllrnginit[0] | 0x10;
+ }
+ else {
+ r = 0x18;
+ }
+ ax5043WriteReg(AX5043_PLLRANGINGA, r); // init ranging process starting from "range"
+ }
+ //printf("INFO: Waiting for PLL ranging process\n");
+ while ((ax5043ReadReg(AX5043_PLLRANGINGA) & 0x10) != 0) {
+ usleep(1000);
+ }
+ //printf("INFO: PLL ranging process complete\n");
+ axradio_trxstate = trxstate_off;
+ axradio_phy_chanpllrng[0] = ax5043ReadReg(AX5043_PLLRANGINGA);
+
+ // VCOI Calibration
+ if (axradio_phy_vcocalib) {
+ ax5043_set_registers_tx();
+ ax5043WriteReg(AX5043_MODULATION, 0x08);
+ ax5043WriteReg(AX5043_FSKDEV2, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV1, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV0, 0x00);
+
+ regValue = ax5043ReadReg(AX5043_PLLLOOP);
+ regValue |= 0x04;
+ ax5043WriteReg(AX5043_PLLLOOP, regValue);
+ {
+ uint8_t x = ax5043ReadReg(AX5043_0xF35);
+ x |= 0x80;
+ if (2 & (uint8_t)~x)
+ ++x;
+ ax5043WriteReg(AX5043_0xF35, x);
+ }
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_SYNTH_TX);
+ {
+ uint8_t vcoisave = ax5043ReadReg(AX5043_PLLVCOI);
+ uint8_t j = 2;
+ axradio_phy_chanvcoi[0] = 0;
+ ax5043WriteReg(AX5043_PLLRANGINGA, axradio_phy_chanpllrng[0] & 0x0F);
+ {
+ uint32_t f = axradio_phy_chanfreq[0];
+ ax5043WriteReg(AX5043_FREQA0, f);
+ ax5043WriteReg(AX5043_FREQA1, f >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f >> 24);
+ }
+ do {
+ if (axradio_phy_chanvcoiinit[0]) {
+ uint8_t x = axradio_phy_chanvcoiinit[0];
+ if (!(axradio_phy_chanpllrnginit[0] & 0xF0))
+ x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F);
+ axradio_phy_chanvcoi[0] = axradio_adjustvcoi(x);
+ } else {
+ axradio_phy_chanvcoi[0] = axradio_calvcoi();
+ }
+ } while (--j);
+ j = 1;
+ ax5043WriteReg(AX5043_PLLVCOI, vcoisave);
+ }
+ }
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN);
+ ax5043_init_registers();
+ ax5043_set_registers_rx();
+ ax5043WriteReg(AX5043_PLLRANGINGA, axradio_phy_chanpllrng[0] & 0x0F);
+ {
+ uint32_t f = axradio_phy_chanfreq[0];
+ ax5043WriteReg(AX5043_FREQA0, f);
+ ax5043WriteReg(AX5043_FREQA1, f >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f >> 24);
+ }
+
+ axradio_mode = AXRADIO_MODE_OFF;
+ if (axradio_phy_chanpllrng[0] & 0x20)
+ return AXRADIO_ERR_RANGING;
+ return AXRADIO_ERR_NOERROR;
+}
+
+uint8_t axradio_setfreq(int32_t f) {
+ uint8_t regValue;
+
+ // range all channels
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_XTAL_ON);
+ axradio_wait_for_xtal();
+
+ {
+ int32_t f1 = axradio_conv_freq_fromhz(f);
+
+ /* Set LSB, per AX5043 documentation, to prevent synthesizer spurs */
+ f1 |= 1;
+
+ ax5043WriteReg(AX5043_FREQA0, f1);
+ ax5043WriteReg(AX5043_FREQA1, f1 >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f1 >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f1 >> 24);
+ }
+ axradio_trxstate = trxstate_pll_ranging;
+ {
+ uint8_t r;
+ if( !(axradio_phy_chanpllrnginit[0] & 0xF0) ) { // start values for ranging available
+ r = axradio_phy_chanpllrnginit[0] | 0x10;
+ }
+ else {
+ r = 0x18;
+ }
+ ax5043WriteReg(AX5043_PLLRANGINGA, r); // init ranging process starting from "range"
+ }
+ //printf("INFO: Waiting for PLL ranging process\n");
+ while ((ax5043ReadReg(AX5043_PLLRANGINGA) & 0x10) != 0) {
+ usleep(1000);
+ }
+ //printf("INFO: PLL ranging process complete\n");
+ axradio_trxstate = trxstate_off;
+ axradio_phy_chanpllrng[0] = ax5043ReadReg(AX5043_PLLRANGINGA);
+
+ // VCOI Calibration
+ if (axradio_phy_vcocalib) {
+ ax5043_set_registers_tx();
+ ax5043WriteReg(AX5043_MODULATION, 0x08);
+ ax5043WriteReg(AX5043_FSKDEV2, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV1, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV0, 0x00);
+
+ regValue = ax5043ReadReg(AX5043_PLLLOOP);
+ regValue |= 0x04;
+ ax5043WriteReg(AX5043_PLLLOOP, regValue);
+ {
+ uint8_t x = ax5043ReadReg(AX5043_0xF35);
+ x |= 0x80;
+ if (2 & (uint8_t)~x)
+ ++x;
+ ax5043WriteReg(AX5043_0xF35, x);
+ }
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_SYNTH_TX);
+ {
+ uint8_t vcoisave = ax5043ReadReg(AX5043_PLLVCOI);
+ uint8_t j = 2;
+ axradio_phy_chanvcoi[0] = 0;
+ ax5043WriteReg(AX5043_PLLRANGINGA, axradio_phy_chanpllrng[0] & 0x0F);
+ {
+ int32_t f1 = axradio_conv_freq_fromhz(f);
+
+ /* Set LSB, per AX5043 documentation, to prevent synthesizer spurs */
+ f1 |= 1;
+
+ ax5043WriteReg(AX5043_FREQA0, f1);
+ ax5043WriteReg(AX5043_FREQA1, f1 >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f1 >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f1 >> 24);
+ }
+ do {
+ if (axradio_phy_chanvcoiinit[0]) {
+ uint8_t x = axradio_phy_chanvcoiinit[0];
+ if (!(axradio_phy_chanpllrnginit[0] & 0xF0))
+ x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F);
+ axradio_phy_chanvcoi[0] = axradio_adjustvcoi(x);
+ } else {
+ axradio_phy_chanvcoi[0] = axradio_calvcoi();
+ }
+ } while (--j);
+ j = 1;
+ ax5043WriteReg(AX5043_PLLVCOI, vcoisave);
+ }
+ }
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN);
+ ax5043_init_registers();
+ ax5043_set_registers_rx();
+ ax5043WriteReg(AX5043_PLLRANGINGA, axradio_phy_chanpllrng[0] & 0x0F);
+ {
+ int32_t f1 = axradio_conv_freq_fromhz(f);
+
+ /* Set LSB, per AX5043 documentation, to prevent synthesizer spurs */
+ f1 |= 1;
+
+ ax5043WriteReg(AX5043_FREQA0, f1);
+ ax5043WriteReg(AX5043_FREQA1, f1 >> 8);
+ ax5043WriteReg(AX5043_FREQA2, f1 >> 16);
+ ax5043WriteReg(AX5043_FREQA3, f1 >> 24);
+ }
+
+ axradio_mode = AXRADIO_MODE_OFF;
+ if (axradio_phy_chanpllrng[0] & 0x20)
+ return AXRADIO_ERR_RANGING;
+ return AXRADIO_ERR_NOERROR;
+}
diff --git a/ax5043/axradio/axradioinit.h b/ax5043/axradio/axradioinit.h
new file mode 100644
index 00000000..dfcf0667
--- /dev/null
+++ b/ax5043/axradio/axradioinit.h
@@ -0,0 +1,428 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef AX5043INIT_H_
+#define AX5043INIT_H_
+
+#include
+
+#define AXRADIO_MODE_UNINIT 0x00
+#define AXRADIO_MODE_OFF 0x01
+#define AXRADIO_MODE_DEEPSLEEP 0x02
+#define AXRADIO_MODE_CW_TRANSMIT 0x03
+#define AXRADIO_MODE_ASYNC_TRANSMIT 0x10
+#define AXRADIO_MODE_WOR_TRANSMIT 0x11
+#define AXRADIO_MODE_ACK_TRANSMIT 0x12
+#define AXRADIO_MODE_WOR_ACK_TRANSMIT 0x13
+#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC 0x18
+#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM 0x19
+#define AXRADIO_MODE_STREAM_TRANSMIT_UNENC_LSB 0x1A
+#define AXRADIO_MODE_STREAM_TRANSMIT_SCRAM_LSB 0x1B
+#define AXRADIO_MODE_STREAM_TRANSMIT 0x1C
+#define AXRADIO_MODE_ASYNC_RECEIVE 0x20
+#define AXRADIO_MODE_WOR_RECEIVE 0x21
+#define AXRADIO_MODE_ACK_RECEIVE 0x22
+#define AXRADIO_MODE_WOR_ACK_RECEIVE 0x23
+#define AXRADIO_MODE_STREAM_RECEIVE_UNENC 0x28
+#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM 0x29
+#define AXRADIO_MODE_STREAM_RECEIVE_UNENC_LSB 0x2A
+#define AXRADIO_MODE_STREAM_RECEIVE_SCRAM_LSB 0x2B
+#define AXRADIO_MODE_STREAM_RECEIVE 0x2C
+#define AXRADIO_MODE_STREAM_RECEIVE_DATAPIN 0x2D
+#define AXRADIO_MODE_SYNC_MASTER 0x30
+#define AXRADIO_MODE_SYNC_ACK_MASTER 0x31
+#define AXRADIO_MODE_SYNC_SLAVE 0x32
+#define AXRADIO_MODE_SYNC_ACK_SLAVE 0x33
+#define AX5043_AFSKCTRL 0x114 /* AFSK Control */
+#define AX5043_AFSKMARK0 0x113 /* AFSK Mark (1) Frequency 0 */
+#define AX5043_AFSKMARK1 0x112 /* AFSK Mark (1) Frequency 1 */
+#define AX5043_AFSKSPACE0 0x111 /* AFSK Space (0) Frequency 0 */
+#define AX5043_AFSKSPACE1 0x110 /* AFSK Space (0) Frequency 1 */
+#define AX5043_AGCCOUNTER 0x043 /* AGC Counter */
+#define AX5043_AMPLFILTER 0x115 /* Amplitude Filter */
+#define AX5043_BBOFFSCAP 0x189 /* Baseband Offset Compensation Capacitors */
+#define AX5043_BBTUNE 0x188 /* Baseband Tuning */
+#define AX5043_BGNDRSSI 0x041 /* Background RSSI */
+#define AX5043_BGNDRSSIGAIN 0x22E /* Background RSSI Averaging Time Constant */
+#define AX5043_BGNDRSSITHR 0x22F /* Background RSSI Relative Threshold */
+#define AX5043_CRCINIT0 0x017 /* CRC Initial Value 0 */
+#define AX5043_CRCINIT1 0x016 /* CRC Initial Value 1 */
+#define AX5043_CRCINIT2 0x015 /* CRC Initial Value 2 */
+#define AX5043_CRCINIT3 0x014 /* CRC Initial Value 3 */
+#define AX5043_DACCONFIG 0x332 /* DAC Configuration */
+#define AX5043_DACVALUE0 0x331 /* DAC Value 0 */
+#define AX5043_DACVALUE1 0x330 /* DAC Value 1 */
+#define AX5043_DECIMATION 0x102 /* Decimation Factor */
+#define AX5043_DIVERSITY 0x042 /* Antenna Diversity Configuration */
+#define AX5043_ENCODING 0x011 /* Encoding */
+#define AX5043_FEC 0x018 /* Forward Error Correction */
+#define AX5043_FECSTATUS 0x01A /* Forward Error Correction Status */
+#define AX5043_FECSYNC 0x019 /* Forward Error Correction Sync Threshold */
+#define AX5043_FIFOCOUNT0 0x02B /* Number of Words currently in FIFO 0 */
+#define AX5043_FIFOCOUNT1 0x02A /* Number of Words currently in FIFO 1 */
+#define AX5043_FIFODATA 0x029 /* FIFO Data */
+#define AX5043_FIFOFREE0 0x02D /* Number of Words that can be written to FIFO 0 */
+#define AX5043_FIFOFREE1 0x02C /* Number of Words that can be written to FIFO 1 */
+#define AX5043_FIFOSTAT 0x028 /* FIFO Control */
+#define AX5043_FIFOTHRESH0 0x02F /* FIFO Threshold 0 */
+#define AX5043_FIFOTHRESH1 0x02E /* FIFO Threshold 1 */
+#define AX5043_FRAMING 0x012 /* Framing Mode */
+#define AX5043_FREQA0 0x037 /* Frequency A 0 */
+#define AX5043_FREQA1 0x036 /* Frequency A 1 */
+#define AX5043_FREQA2 0x035 /* Frequency A 2 */
+#define AX5043_FREQA3 0x034 /* Frequency A 3 */
+#define AX5043_FREQB0 0x03F /* Frequency B 0 */
+#define AX5043_FREQB1 0x03E /* Frequency B 1 */
+#define AX5043_FREQB2 0x03D /* Frequency B 2 */
+#define AX5043_FREQB3 0x03C /* Frequency B 3 */
+#define AX5043_FSKDEV0 0x163 /* FSK Deviation 0 */
+#define AX5043_FSKDEV1 0x162 /* FSK Deviation 1 */
+#define AX5043_FSKDEV2 0x161 /* FSK Deviation 2 */
+#define AX5043_FSKDMAX0 0x10D /* Four FSK Rx Maximum Deviation 0 */
+#define AX5043_FSKDMAX1 0x10C /* Four FSK Rx Maximum Deviation 1 */
+#define AX5043_FSKDMIN0 0x10F /* Four FSK Rx Minimum Deviation 0 */
+#define AX5043_FSKDMIN1 0x10E /* Four FSK Rx Minimum Deviation 1 */
+#define AX5043_GPADC13VALUE0 0x309 /* GPADC13 Value 0 */
+#define AX5043_GPADC13VALUE1 0x308 /* GPADC13 Value 1 */
+#define AX5043_GPADCCTRL 0x300 /* General Purpose ADC Control */
+#define AX5043_GPADCPERIOD 0x301 /* GPADC Sampling Period */
+#define AX5043_IFFREQ0 0x101 /* 2nd LO / IF Frequency 0 */
+#define AX5043_IFFREQ1 0x100 /* 2nd LO / IF Frequency 1 */
+#define AX5043_IRQINVERSION0 0x00B /* IRQ Inversion 0 */
+#define AX5043_IRQINVERSION1 0x00A /* IRQ Inversion 1 */
+#define AX5043_IRQMASK0 0x007 /* IRQ Mask 0 */
+#define AX5043_IRQMASK1 0x006 /* IRQ Mask 1 */
+#define AX5043_IRQREQUEST0 0x00D /* IRQ Request 0 */
+#define AX5043_IRQREQUEST1 0x00C /* IRQ Request 1 */
+#define AX5043_LPOSCCONFIG 0x310 /* Low Power Oscillator Calibration Configuration */
+#define AX5043_LPOSCFREQ0 0x317 /* Low Power Oscillator Frequency Tuning Low Byte */
+#define AX5043_LPOSCFREQ1 0x316 /* Low Power Oscillator Frequency Tuning High Byte */
+#define AX5043_LPOSCKFILT0 0x313 /* Low Power Oscillator Calibration Filter Constant Low Byte */
+#define AX5043_LPOSCKFILT1 0x312 /* Low Power Oscillator Calibration Filter Constant High Byte */
+#define AX5043_LPOSCPER0 0x319 /* Low Power Oscillator Period Low Byte */
+#define AX5043_LPOSCPER1 0x318 /* Low Power Oscillator Period High Byte */
+#define AX5043_LPOSCREF0 0x315 /* Low Power Oscillator Reference Frequency Low Byte */
+#define AX5043_LPOSCREF1 0x314 /* Low Power Oscillator Reference Frequency High Byte */
+#define AX5043_LPOSCSTATUS 0x311 /* Low Power Oscillator Calibration Status */
+#define AX5043_MATCH0LEN 0x214 /* Pattern Match Unit 0, Pattern Length */
+#define AX5043_MATCH0MAX 0x216 /* Pattern Match Unit 0, Maximum Match */
+#define AX5043_MATCH0MIN 0x215 /* Pattern Match Unit 0, Minimum Match */
+#define AX5043_MATCH0PAT0 0x213 /* Pattern Match Unit 0, Pattern 0 */
+#define AX5043_MATCH0PAT1 0x212 /* Pattern Match Unit 0, Pattern 1 */
+#define AX5043_MATCH0PAT2 0x211 /* Pattern Match Unit 0, Pattern 2 */
+#define AX5043_MATCH0PAT3 0x210 /* Pattern Match Unit 0, Pattern 3 */
+#define AX5043_MATCH1LEN 0x21C /* Pattern Match Unit 1, Pattern Length */
+#define AX5043_MATCH1MAX 0x21E /* Pattern Match Unit 1, Maximum Match */
+#define AX5043_MATCH1MIN 0x21D /* Pattern Match Unit 1, Minimum Match */
+#define AX5043_MATCH1PAT0 0x219 /* Pattern Match Unit 1, Pattern 0 */
+#define AX5043_MATCH1PAT1 0x218 /* Pattern Match Unit 1, Pattern 1 */
+#define AX5043_MAXDROFFSET0 0x108 /* Maximum Receiver Datarate Offset 0 */
+#define AX5043_MAXDROFFSET1 0x107 /* Maximum Receiver Datarate Offset 1 */
+#define AX5043_MAXDROFFSET2 0x106 /* Maximum Receiver Datarate Offset 2 */
+#define AX5043_MAXRFOFFSET0 0x10B /* Maximum Receiver RF Offset 0 */
+#define AX5043_MAXRFOFFSET1 0x10A /* Maximum Receiver RF Offset 1 */
+#define AX5043_MAXRFOFFSET2 0x109 /* Maximum Receiver RF Offset 2 */
+#define AX5043_MODCFGA 0x164 /* Modulator Configuration A */
+#define AX5043_MODCFGF 0x160 /* Modulator Configuration F */
+#define AX5043_MODCFGP 0xF5F /* Modulator Configuration P */
+#define AX5043_MODULATION 0x010 /* Modulation */
+#define AX5043_PINFUNCANTSEL 0x025 /* Pin Function ANTSEL */
+#define AX5043_PINFUNCDATA 0x023 /* Pin Function DATA */
+#define AX5043_PINFUNCDCLK 0x022 /* Pin Function DCLK */
+#define AX5043_PINFUNCIRQ 0x024 /* Pin Function IRQ */
+#define AX5043_PINFUNCPWRAMP 0x026 /* Pin Function PWRAMP */
+#define AX5043_PINFUNCSYSCLK 0x021 /* Pin Function SYSCLK */
+#define AX5043_PINSTATE 0x020 /* Pin State */
+#define AX5043_PKTACCEPTFLAGS 0x233 /* Packet Controller Accept Flags */
+#define AX5043_PKTCHUNKSIZE 0x230 /* Packet Chunk Size */
+#define AX5043_PKTMISCFLAGS 0x231 /* Packet Controller Miscellaneous Flags */
+#define AX5043_PKTSTOREFLAGS 0x232 /* Packet Controller Store Flags */
+#define AX5043_PLLCPI 0x031 /* PLL Charge Pump Current */
+#define AX5043_PLLCPIBOOST 0x039 /* PLL Charge Pump Current (Boosted) */
+#define AX5043_PLLLOCKDET 0x182 /* PLL Lock Detect Delay */
+#define AX5043_PLLLOOP 0x030 /* PLL Loop Filter Settings */
+#define AX5043_PLLLOOPBOOST 0x038 /* PLL Loop Filter Settings (Boosted) */
+#define AX5043_PLLRANGINGA 0x033 /* PLL Autoranging A */
+#define AX5043_PLLRANGINGB 0x03B /* PLL Autoranging B */
+#define AX5043_PLLRNGCLK 0x183 /* PLL Autoranging Clock */
+#define AX5043_PLLVCODIV 0x032 /* PLL Divider Settings */
+#define AX5043_PLLVCOI 0x180 /* PLL VCO Current */
+#define AX5043_PLLVCOIR 0x181 /* PLL VCO Current Readback */
+#define AX5043_POWCTRL1 0xF08 /* Power Control 1 */
+#define AX5043_POWIRQMASK 0x005 /* Power Management Interrupt Mask */
+#define AX5043_POWSTAT 0x003 /* Power Management Status */
+#define AX5043_POWSTICKYSTAT 0x004 /* Power Management Sticky Status */
+#define AX5043_PWRAMP 0x027 /* PWRAMP Control */
+#define AX5043_PWRMODE 0x002 /* Power Mode */
+#define AX5043_RADIOEVENTMASK0 0x009 /* Radio Event Mask 0 */
+#define AX5043_RADIOEVENTMASK1 0x008 /* Radio Event Mask 1 */
+#define AX5043_RADIOEVENTREQ0 0x00F /* Radio Event Request 0 */
+#define AX5043_RADIOEVENTREQ1 0x00E /* Radio Event Request 1 */
+#define AX5043_RADIOSTATE 0x01C /* Radio Controller State */
+#define AX5043_REF 0xF0D /* Reference */
+#define AX5043_RSSI 0x040 /* Received Signal Strength Indicator */
+#define AX5043_RSSIABSTHR 0x22D /* RSSI Absolute Threshold */
+#define AX5043_RSSIREFERENCE 0x22C /* RSSI Offset */
+#define AX5043_RXDATARATE0 0x105 /* Receiver Datarate 0 */
+#define AX5043_RXDATARATE1 0x104 /* Receiver Datarate 1 */
+#define AX5043_RXDATARATE2 0x103 /* Receiver Datarate 2 */
+#define AX5043_SCRATCH 0x001 /* Scratch */
+#define AX5043_SILICONREVISION 0x000 /* Silicon Revision */
+#define AX5043_TIMER0 0x05B /* 1MHz Timer 0 */
+#define AX5043_TIMER1 0x05A /* 1MHz Timer 1 */
+#define AX5043_TIMER2 0x059 /* 1MHz Timer 2 */
+#define AX5043_TMGRXAGC 0x227 /* Receiver AGC Settling Time */
+#define AX5043_TMGRXBOOST 0x223 /* Receive PLL Boost Time */
+#define AX5043_TMGRXCOARSEAGC 0x226 /* Receive Coarse AGC Time */
+#define AX5043_TMGRXOFFSACQ 0x225 /* Receive Baseband DC Offset Acquisition Time */
+#define AX5043_TMGRXPREAMBLE1 0x229 /* Receiver Preamble 1 Timeout */
+#define AX5043_TMGRXPREAMBLE2 0x22A /* Receiver Preamble 2 Timeout */
+#define AX5043_TMGRXPREAMBLE3 0x22B /* Receiver Preamble 3 Timeout */
+#define AX5043_TMGRXRSSI 0x228 /* Receiver RSSI Settling Time */
+#define AX5043_TMGRXSETTLE 0x224 /* Receive PLL (post Boost) Settling Time */
+#define AX5043_TMGTXBOOST 0x220 /* Transmit PLL Boost Time */
+#define AX5043_TMGTXSETTLE 0x221 /* Transmit PLL (post Boost) Settling Time */
+#define AX5043_TRKAFSKDEMOD0 0x055 /* AFSK Demodulator Tracking 0 */
+#define AX5043_TRKAFSKDEMOD1 0x054 /* AFSK Demodulator Tracking 1 */
+#define AX5043_TRKAMPLITUDE0 0x049 /* Amplitude Tracking 0 */
+#define AX5043_TRKAMPLITUDE1 0x048 /* Amplitude Tracking 1 */
+#define AX5043_TRKDATARATE0 0x047 /* Datarate Tracking 0 */
+#define AX5043_TRKDATARATE1 0x046 /* Datarate Tracking 1 */
+#define AX5043_TRKDATARATE2 0x045 /* Datarate Tracking 2 */
+#define AX5043_TRKFREQ0 0x051 /* Frequency Tracking 0 */
+#define AX5043_TRKFREQ1 0x050 /* Frequency Tracking 1 */
+#define AX5043_TRKFSKDEMOD0 0x053 /* FSK Demodulator Tracking 0 */
+#define AX5043_TRKFSKDEMOD1 0x052 /* FSK Demodulator Tracking 1 */
+#define AX5043_TRKPHASE0 0x04B /* Phase Tracking 0 */
+#define AX5043_TRKPHASE1 0x04A /* Phase Tracking 1 */
+#define AX5043_TRKRFFREQ0 0x04F /* RF Frequency Tracking 0 */
+#define AX5043_TRKRFFREQ1 0x04E /* RF Frequency Tracking 1 */
+#define AX5043_TRKRFFREQ2 0x04D /* RF Frequency Tracking 2 */
+#define AX5043_TXPWRCOEFFA0 0x169 /* Transmitter Predistortion Coefficient A 0 */
+#define AX5043_TXPWRCOEFFA1 0x168 /* Transmitter Predistortion Coefficient A 1 */
+#define AX5043_TXPWRCOEFFB0 0x16B /* Transmitter Predistortion Coefficient B 0 */
+#define AX5043_TXPWRCOEFFB1 0x16A /* Transmitter Predistortion Coefficient B 1 */
+#define AX5043_TXPWRCOEFFC0 0x16D /* Transmitter Predistortion Coefficient C 0 */
+#define AX5043_TXPWRCOEFFC1 0x16C /* Transmitter Predistortion Coefficient C 1 */
+#define AX5043_TXPWRCOEFFD0 0x16F /* Transmitter Predistortion Coefficient D 0 */
+#define AX5043_TXPWRCOEFFD1 0x16E /* Transmitter Predistortion Coefficient D 1 */
+#define AX5043_TXPWRCOEFFE0 0x171 /* Transmitter Predistortion Coefficient E 0 */
+#define AX5043_TXPWRCOEFFE1 0x170 /* Transmitter Predistortion Coefficient E 1 */
+#define AX5043_TXRATE0 0x167 /* Transmitter Bitrate 0 */
+#define AX5043_TXRATE1 0x166 /* Transmitter Bitrate 1 */
+#define AX5043_TXRATE2 0x165 /* Transmitter Bitrate 2 */
+#define AX5043_WAKEUP0 0x06B /* Wakeup Time 0 */
+#define AX5043_WAKEUP1 0x06A /* Wakeup Time 1 */
+#define AX5043_WAKEUPFREQ0 0x06D /* Wakeup Frequency 0 */
+#define AX5043_WAKEUPFREQ1 0x06C /* Wakeup Frequency 1 */
+#define AX5043_WAKEUPTIMER0 0x069 /* Wakeup Timer 0 */
+#define AX5043_WAKEUPTIMER1 0x068 /* Wakeup Timer 1 */
+#define AX5043_WAKEUPXOEARLY 0x06E /* Wakeup Crystal Oscillator Early */
+#define AX5043_XTALAMPL 0xF11 /* Crystal Oscillator Amplitude Control */
+#define AX5043_XTALCAP 0x184 /* Crystal Oscillator Load Capacitance */
+#define AX5043_XTALOSC 0xF10 /* Crystal Oscillator Control */
+#define AX5043_XTALSTATUS 0x01D /* Crystal Oscillator Status */
+
+#define AX5043_0xF00 0xF00
+#define AX5043_0xF0C 0xF0C
+#define AX5043_0xF18 0xF18
+#define AX5043_0xF1C 0xF1C
+#define AX5043_0xF21 0xF21
+#define AX5043_0xF22 0xF22
+#define AX5043_0xF23 0xF23
+#define AX5043_0xF26 0xF26
+#define AX5043_0xF30 0xF30
+#define AX5043_0xF31 0xF31
+#define AX5043_0xF32 0xF32
+#define AX5043_0xF33 0xF33
+#define AX5043_0xF34 0xF34
+#define AX5043_0xF35 0xF35
+#define AX5043_0xF44 0xF44
+
+#define AX5043_AGCAHYST0 0x122 /* AGC Analog Hysteresis */
+#define AX5043_AGCAHYST1 0x132 /* AGC Analog Hysteresis */
+#define AX5043_AGCAHYST2 0x142 /* AGC Analog Hysteresis */
+#define AX5043_AGCAHYST3 0x152 /* AGC Analog Hysteresis */
+#define AX5043_AGCGAIN0 0x120 /* AGC Speed */
+#define AX5043_AGCGAIN1 0x130 /* AGC Speed */
+#define AX5043_AGCGAIN2 0x140 /* AGC Speed */
+#define AX5043_AGCGAIN3 0x150 /* AGC Speed */
+#define AX5043_AGCMINMAX0 0x123 /* AGC Analog Update Behaviour */
+#define AX5043_AGCMINMAX1 0x133 /* AGC Analog Update Behaviour */
+#define AX5043_AGCMINMAX2 0x143 /* AGC Analog Update Behaviour */
+#define AX5043_AGCMINMAX3 0x153 /* AGC Analog Update Behaviour */
+#define AX5043_AGCTARGET0 0x121 /* AGC Target */
+#define AX5043_AGCTARGET1 0x131 /* AGC Target */
+#define AX5043_AGCTARGET2 0x141 /* AGC Target */
+#define AX5043_AGCTARGET3 0x151 /* AGC Target */
+#define AX5043_AMPLITUDEGAIN0 0x12B /* Amplitude Estimator Bandwidth */
+#define AX5043_AMPLITUDEGAIN1 0x13B /* Amplitude Estimator Bandwidth */
+#define AX5043_AMPLITUDEGAIN2 0x14B /* Amplitude Estimator Bandwidth */
+#define AX5043_AMPLITUDEGAIN3 0x15B /* Amplitude Estimator Bandwidth */
+#define AX5043_BBOFFSRES0 0x12F /* Baseband Offset Compensation Resistors */
+#define AX5043_BBOFFSRES1 0x13F /* Baseband Offset Compensation Resistors */
+#define AX5043_BBOFFSRES2 0x14F /* Baseband Offset Compensation Resistors */
+#define AX5043_BBOFFSRES3 0x15F /* Baseband Offset Compensation Resistors */
+#define AX5043_DRGAIN0 0x125 /* Data Rate Estimator Bandwidth */
+#define AX5043_DRGAIN1 0x135 /* Data Rate Estimator Bandwidth */
+#define AX5043_DRGAIN2 0x145 /* Data Rate Estimator Bandwidth */
+#define AX5043_DRGAIN3 0x155 /* Data Rate Estimator Bandwidth */
+#define AX5043_FOURFSK0 0x12E /* Four FSK Control */
+#define AX5043_FOURFSK1 0x13E /* Four FSK Control */
+#define AX5043_FOURFSK2 0x14E /* Four FSK Control */
+#define AX5043_FOURFSK3 0x15E /* Four FSK Control */
+#define AX5043_FREQDEV00 0x12D /* Receiver Frequency Deviation 0 */
+#define AX5043_FREQDEV01 0x13D /* Receiver Frequency Deviation 0 */
+#define AX5043_FREQDEV02 0x14D /* Receiver Frequency Deviation 0 */
+#define AX5043_FREQDEV03 0x15D /* Receiver Frequency Deviation 0 */
+#define AX5043_FREQDEV10 0x12C /* Receiver Frequency Deviation 1 */
+#define AX5043_FREQDEV11 0x13C /* Receiver Frequency Deviation 1 */
+#define AX5043_FREQDEV12 0x14C /* Receiver Frequency Deviation 1 */
+#define AX5043_FREQDEV13 0x15C /* Receiver Frequency Deviation 1 */
+#define AX5043_FREQUENCYGAINA0 0x127 /* Frequency Estimator Bandwidth A */
+#define AX5043_FREQUENCYGAINA1 0x137 /* Frequency Estimator Bandwidth A */
+#define AX5043_FREQUENCYGAINA2 0x147 /* Frequency Estimator Bandwidth A */
+#define AX5043_FREQUENCYGAINA3 0x157 /* Frequency Estimator Bandwidth A */
+#define AX5043_FREQUENCYGAINB0 0x128 /* Frequency Estimator Bandwidth B */
+#define AX5043_FREQUENCYGAINB1 0x138 /* Frequency Estimator Bandwidth B */
+#define AX5043_FREQUENCYGAINB2 0x148 /* Frequency Estimator Bandwidth B */
+#define AX5043_FREQUENCYGAINB3 0x158 /* Frequency Estimator Bandwidth B */
+#define AX5043_FREQUENCYGAINC0 0x129 /* Frequency Estimator Bandwidth C */
+#define AX5043_FREQUENCYGAINC1 0x139 /* Frequency Estimator Bandwidth C */
+#define AX5043_FREQUENCYGAINC2 0x149 /* Frequency Estimator Bandwidth C */
+#define AX5043_FREQUENCYGAINC3 0x159 /* Frequency Estimator Bandwidth C */
+#define AX5043_FREQUENCYGAIND0 0x12A /* Frequency Estimator Bandwidth D */
+#define AX5043_FREQUENCYGAIND1 0x13A /* Frequency Estimator Bandwidth D */
+#define AX5043_FREQUENCYGAIND2 0x14A /* Frequency Estimator Bandwidth D */
+#define AX5043_FREQUENCYGAIND3 0x15A /* Frequency Estimator Bandwidth D */
+#define AX5043_FREQUENCYLEAK 0x116 /* Baseband Frequency Recovery Loop Leakiness */
+#define AX5043_PHASEGAIN0 0x126 /* Phase Estimator Bandwidth */
+#define AX5043_PHASEGAIN1 0x136 /* Phase Estimator Bandwidth */
+#define AX5043_PHASEGAIN2 0x146 /* Phase Estimator Bandwidth */
+#define AX5043_PHASEGAIN3 0x156 /* Phase Estimator Bandwidth */
+#define AX5043_PKTADDR0 0x207 /* Packet Address 0 */
+#define AX5043_PKTADDR1 0x206 /* Packet Address 1 */
+#define AX5043_PKTADDR2 0x205 /* Packet Address 2 */
+#define AX5043_PKTADDR3 0x204 /* Packet Address 3 */
+#define AX5043_PKTADDRCFG 0x200 /* Packet Address Config */
+#define AX5043_PKTADDRMASK0 0x20B /* Packet Address Mask 0 */
+#define AX5043_PKTADDRMASK1 0x20A /* Packet Address Mask 1 */
+#define AX5043_PKTADDRMASK2 0x209 /* Packet Address Mask 2 */
+#define AX5043_PKTADDRMASK3 0x208 /* Packet Address Mask 3 */
+#define AX5043_PKTLENCFG 0x201 /* Packet Length Configuration */
+#define AX5043_PKTLENOFFSET 0x202 /* Packet Length Offset */
+#define AX5043_PKTMAXLEN 0x203 /* Packet Maximum Length */
+#define AX5043_RXPARAMCURSET 0x118 /* Receiver Parameter Current Set */
+#define AX5043_RXPARAMSETS 0x117 /* Receiver Parameter Set Indirection */
+#define AX5043_TIMEGAIN0 0x124 /* Time Estimator Bandwidth */
+#define AX5043_TIMEGAIN1 0x134 /* Time Estimator Bandwidth */
+#define AX5043_TIMEGAIN2 0x144 /* Time Estimator Bandwidth */
+#define AX5043_TIMEGAIN3 0x154 /* Time Estimator Bandwidth */
+
+// power states
+#define AX5043_PWRSTATE_POWERDOWN 0x0
+#define AX5043_PWRSTATE_DEEPSLEEP 0x1
+#define AX5043_PWRSTATE_REGS_ON 0x4
+#define AX5043_PWRSTATE_XTAL_ON 0x5
+#define AX5043_PWRSTATE_FIFO_ON 0x7
+#define AX5043_PWRSTATE_SYNTH_RX 0x8
+#define AX5043_PWRSTATE_FULL_RX 0x9
+#define AX5043_PWRSTATE_WOR_RX 0xb
+#define AX5043_PWRSTATE_SYNTH_TX 0xc
+#define AX5043_PWRSTATE_FULL_TX 0xd
+
+//fifo commands
+#define AX5043_FIFOCMD_NOP 0x00
+#define AX5043_FIFOCMD_DATA 0x01
+#define AX5043_FIFOCMD_REPEATDATA 0x02
+#define AX5043_FIFOCMD_TIMER 0x10
+#define AX5043_FIFOCMD_RSSI 0x11
+#define AX5043_FIFOCMD_FREQOFFS 0x12
+#define AX5043_FIFOCMD_RFFREQOFFS 0x13
+#define AX5043_FIFOCMD_DATARATE 0x14
+#define AX5043_FIFOCMD_ANTRSSI 0x15
+#define AX5043_FIFOCMD_TXCTRL 0x1C
+#define AX5043_FIFOCMD_TXPWR 0x1D
+
+#define SILICONREV1 0x51
+\
+#define RADIO_OK 0
+#define RADIO_ERR_REVISION 1
+#define RADIO_ERR_COMM 2
+#define RADIO_ERR_IRQ 3
+#define RADIO_ERR_WAKEUPTIMEOUT 4
+
+#define PKTDATA_BUFLEN 260
+
+typedef enum {
+ trxstate_off,
+ trxstate_rx,
+ trxstate_rxwor,
+ trxstate_wait_xtal,
+ trxstate_xtal_ready,
+ trxstate_pll_ranging,
+ trxstate_pll_ranging_done,
+ trxstate_pll_settling,
+ trxstate_pll_settled,
+ trxstate_tx_xtalwait,
+ trxstate_tx_longpreamble,
+ trxstate_tx_shortpreamble,
+ trxstate_tx_packet,
+ trxstate_tx_waitdone,
+ trxstate_txcw_xtalwait,
+ trxstate_txstream_xtalwait,
+ trxstate_txstream
+} axradio_trxstate_t;
+
+struct axradio_address_mask {
+ uint8_t addr[4];
+ uint8_t mask[4];
+};
+
+void axradio_wait_for_xtal(void);
+
+#endif /* AX5043INIT_H_ */
diff --git a/ax5043/axradio/axradioinit_p.h b/ax5043/axradio/axradioinit_p.h
new file mode 100644
index 00000000..8d221be8
--- /dev/null
+++ b/ax5043/axradio/axradioinit_p.h
@@ -0,0 +1,91 @@
+/*!
+ \copyright
+ Copyright (c) 2018 Brandenburg Tech, LLC
+ All rights reserved.
+
+ THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+ AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1.Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2.Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3.Neither the name of AXSEM AG, Duebendorf nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ 4.All advertising materials mentioning features or use of this software
+ must display the following acknowledgement:
+ This product includes software developed by AXSEM AG and its contributors.
+ 5.The usage of this source code is only granted for operation with AX5043
+ and AX8052F143. Porting to other radio or communication devices is
+ strictly prohibited.
+
+ THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ \file axradioinit_p.h
+ \brief Provides an interface to initialze the AX5043 transceiver.
+*/
+
+#ifndef AX5043INIT_P_H_
+#define AX5043INIT_P_H_
+
+#include
+
+#define AXRADIO_ERR_NOERROR 0x00 //!< Operation successful
+#define AXRADIO_ERR_NOTSUPPORTED 0x01 //!< Operation not supported
+#define AXRADIO_ERR_BUSY 0x02 //!< Transceiver busy
+#define AXRADIO_ERR_TIMEOUT 0x03 //!< Operation timed out
+#define AXRADIO_ERR_INVALID 0x04 //!< Invalid parameter
+#define AXRADIO_ERR_NOCHIP 0x05 //!< Transceiver not found
+#define AXRADIO_ERR_RANGING 0x06 //!< Frequency could not be ranged
+#define AXRADIO_ERR_LOCKLOST 0x07 //!< Lost PLL lock
+#define AXRADIO_ERR_RETRANSMISSION 0x08 //!< Retrasnmitted packet
+#define AXRADIO_ERR_RESYNC 0x09 //!< Restarts synchronization
+#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a //!< Synchronization timed out
+#define AXRADIO_ERR_RECEIVESTART 0x0b //!< Receiver restarted
+
+//! Structure containing a four byte X.25 address
+struct axradio_address {
+ uint8_t addr[4]; //!< Four byte X.25 address
+};
+
+/*! \fn uint8_t axradio_init(void)
+ \brief Initialize the AX5043 radio transceiver.
+ \return AXRADIO_ERR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t axradio_init(void);
+
+/*! \fn uint8_t axradio_setfreq(int32_t f)
+ \brief Set the receive and transmit frequency.
+ \param f The frequency in Hertz.
+ \return AXRADIO_ERR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t axradio_setfreq(int32_t f);
+
+#endif /* AX5043INIT_P_H_ */
diff --git a/ax5043/axradio/axradiomode.c b/ax5043/axradio/axradiomode.c
new file mode 100644
index 00000000..c2f7d441
--- /dev/null
+++ b/ax5043/axradio/axradiomode.c
@@ -0,0 +1,188 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "axradiomode.h"
+
+#include "../generated/config.h"
+#include "../spi/ax5043spi_p.h"
+#include "axradioinit.h"
+#include "axradioinit_p.h"
+
+extern uint8_t axradio_phy_chanpllrng[];
+extern const uint8_t axradio_phy_vcocalib;
+extern uint8_t axradio_phy_chanvcoi[];
+extern const uint8_t axradio_phy_chanvcoiinit[];
+extern const uint8_t axradio_phy_chanpllrnginit[];
+extern const int8_t axradio_phy_rssireference;
+
+static uint8_t ax5043_init_registers_common(void);
+
+uint8_t mode_tx() {
+ int retVal;
+
+ retVal = ax5043_off();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ retVal = ax5043_init_registers_tx();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ return AXRADIO_ERR_NOERROR;
+}
+
+uint8_t mode_rx() {
+ int retVal;
+
+ retVal = ax5043_off();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ retVal = ax5043_init_registers_rx();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ retVal = ax5043_receiver_on_continuous();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ return AXRADIO_ERR_NOERROR;
+}
+
+
+uint8_t ax5043_off(void)
+{
+ uint8_t retVal;
+
+ retVal = ax5043_off_xtal();
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ return retVal;
+ }
+
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_POWERDOWN);
+
+ return AXRADIO_ERR_NOERROR;
+}
+
+uint8_t ax5043_off_xtal(void)
+{
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_XTAL_ON);
+ ax5043WriteReg(AX5043_LPOSCCONFIG, 0x00); // LPOSC off
+ return AXRADIO_ERR_NOERROR;
+}
+
+uint8_t ax5043_init_registers_tx(void)
+{
+ ax5043_set_registers_tx();
+ return ax5043_init_registers_common();
+}
+
+static uint8_t ax5043_init_registers_common(void)
+{
+ uint8_t rng = axradio_phy_chanpllrng[0];
+ if (rng & 0x20)
+ return AXRADIO_ERR_RANGING;
+ if (ax5043ReadReg(AX5043_PLLLOOP) & 0x80) {
+ ax5043WriteReg(AX5043_PLLRANGINGB, rng & 0x0F);
+ } else {
+ ax5043WriteReg(AX5043_PLLRANGINGA, rng & 0x0F);
+ }
+ rng = axradio_get_pllvcoi();
+ if (rng & 0x80)
+ ax5043WriteReg(AX5043_PLLVCOI, rng);
+
+ return AXRADIO_ERR_NOERROR;
+}
+
+uint8_t axradio_get_pllvcoi(void)
+{
+ if (axradio_phy_vcocalib) {
+ uint8_t x = axradio_phy_chanvcoi[0];
+ if (x & 0x80)
+ return x;
+ }
+ {
+ uint8_t x = axradio_phy_chanvcoiinit[0];
+ if (x & 0x80) {
+ if (!(axradio_phy_chanpllrnginit[0] & 0xF0)) {
+ x += (axradio_phy_chanpllrng[0] & 0x0F) - (axradio_phy_chanpllrnginit[0] & 0x0F);
+ x &= 0x3f;
+ x |= 0x80;
+ }
+ return x;
+ }
+ }
+ return ax5043ReadReg(AX5043_PLLVCOI);
+}
+
+uint8_t ax5043_init_registers_rx(void) {
+ ax5043_set_registers_rx();
+ return ax5043_init_registers_common();
+
+}
+
+uint8_t ax5043_receiver_on_continuous(void) {
+ uint8_t regValue;
+
+ ax5043WriteReg(AX5043_RSSIREFERENCE, axradio_phy_rssireference);
+ ax5043_set_registers_rxcont();
+
+ regValue = ax5043ReadReg(AX5043_PKTSTOREFLAGS);
+ regValue &= (uint8_t)~0x40;
+ ax5043WriteReg(AX5043_PKTSTOREFLAGS, regValue);
+
+
+ ax5043WriteReg(AX5043_FIFOSTAT, 3); // clear FIFO data & flags
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_FULL_RX);
+
+ return AXRADIO_ERR_NOERROR;
+}
diff --git a/ax5043/axradio/axradiomode.h b/ax5043/axradio/axradiomode.h
new file mode 100644
index 00000000..0911eae9
--- /dev/null
+++ b/ax5043/axradio/axradiomode.h
@@ -0,0 +1,61 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef AX5043MODE_H_
+#define AX5043MODE_H_
+
+#include
+
+uint8_t ax5043_off(void);
+uint8_t ax5043_off_xtal(void);
+uint8_t ax5043_init_registers_tx(void);
+uint8_t axradio_get_pllvcoi(void);
+uint8_t ax5043_init_registers_rx(void);
+uint8_t ax5043_receiver_on_continuous(void);
+
+
+#endif /* AX5043MODE_H_ */
diff --git a/ax5043/axradio/axradiomode_p.h b/ax5043/axradio/axradiomode_p.h
new file mode 100644
index 00000000..af99f534
--- /dev/null
+++ b/ax5043/axradio/axradiomode_p.h
@@ -0,0 +1,75 @@
+/*!
+ \copyright
+ Copyright (c) 2018 Brandenburg Tech, LLC
+ All rights reserved.
+
+ THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+ AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1.Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2.Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3.Neither the name of AXSEM AG, Duebendorf nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ 4.All advertising materials mentioning features or use of this software
+ must display the following acknowledgement:
+ This product includes software developed by AXSEM AG and its contributors.
+ 5.The usage of this source code is only granted for operation with AX5043
+ and AX8052F143. Porting to other radio or communication devices is
+ strictly prohibited.
+
+ THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ \file axradiomode_p.h
+ \brief Provides an interface to change the transceiver mode.
+*/
+
+#ifndef AX5043MODE_P_H_
+#define AX5043MODE_P_H_
+
+#include
+
+/*! \fn uint8_t mode_tx()
+ \brief Switch the tranceiver into transmit mode.
+ \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t mode_tx(void);
+
+/*! \fn uint8_t mode_rx()
+ \brief Switch the tranceiver into receive mode.
+
+ The receive buffer may contain garbage and reading from the buffer
+ will obtain and discard that garbage.
+ \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t mode_rx(void);
+
+#endif /* AX5043MODE_P_H_ */
diff --git a/ax5043/axradio/axradiorx.c b/ax5043/axradio/axradiorx.c
new file mode 100644
index 00000000..584c78c7
--- /dev/null
+++ b/ax5043/axradio/axradiorx.c
@@ -0,0 +1,147 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "axradiorx.h"
+
+#include "../ax5043support/ax5043rx.h"
+#include "../spi/ax5043spi_p.h"
+#include "axradioinit.h"
+
+extern const uint8_t axradio_phy_innerfreqloop;
+extern uint8_t axradio_rxbuffer[];
+
+static uint8_t receive_loop(void);
+
+uint8_t receive_packet(void) {
+ return receive_loop();
+}
+
+uint8_t receive_loop(void) {
+ uint8_t fifo_cmd;
+ uint8_t i;
+ uint8_t b0 __attribute__((unused));
+ uint8_t b1 __attribute__((unused));
+ uint8_t b2 __attribute__((unused));
+ uint8_t b3 __attribute__((unused));
+
+ uint8_t len = ax5043ReadReg(AX5043_RADIOEVENTREQ0); // clear request so interrupt does not fire again. sync_rx enables interrupt on radio state changed in order to wake up on SDF detected
+
+ uint8_t bytesRead = 0;
+
+ //printf("INFO: Waiting for a packet\n");
+
+ while ((ax5043ReadReg(AX5043_FIFOSTAT) & 0x01) != 1) { // FIFO not empty
+ fifo_cmd = ax5043ReadReg(AX5043_FIFODATA); // read command
+ len = (fifo_cmd & 0xE0) >> 5; // top 3 bits encode payload len
+ if (len == 7)
+ len = ax5043ReadReg(AX5043_FIFODATA); // 7 means variable length, -> get length byte
+ fifo_cmd &= 0x1F;
+ switch (fifo_cmd) {
+ case AX5043_FIFOCMD_DATA:
+ if (!len)
+ break;
+
+ ax5043ReadReg(AX5043_FIFODATA); // Discard the flags
+ --len;
+ bytesRead = ax5043_readfifo(axradio_rxbuffer, len);
+ break;
+
+ case AX5043_FIFOCMD_RFFREQOFFS:
+ if (axradio_phy_innerfreqloop || len != 3)
+ goto dropchunk;
+ i = ax5043ReadReg(AX5043_FIFODATA);
+ i &= 0x0F;
+ i |= 1 + (uint8_t)~(i & 0x08);
+
+ b3 = ((int8_t)i) >> 8;
+ b2 = i;
+ b1 = ax5043ReadReg(AX5043_FIFODATA);
+ b0 = ax5043ReadReg(AX5043_FIFODATA);
+
+ //printf("INFO: RF Frequency Offset: 0x%02x%02x%02x%02x\n", b3, b2, b1, b0);
+ break;
+
+ case AX5043_FIFOCMD_FREQOFFS:
+ if (!axradio_phy_innerfreqloop || len != 2)
+ goto dropchunk;
+
+ b1 = ax5043ReadReg(AX5043_FIFODATA);
+ b0 = ax5043ReadReg(AX5043_FIFODATA);
+
+ //printf("INFO: Frequency offset: 0x%02x%02x\n", b1, b2);
+ break;
+
+ case AX5043_FIFOCMD_RSSI:
+ if (len != 1)
+ goto dropchunk;
+ {
+ int8_t r __attribute__((unused));
+ r = ax5043ReadReg(AX5043_FIFODATA);
+
+ //printf("INFO: RSSI %d\n", (int)r);
+ }
+ break;
+
+ default:
+ //fprintf(stderr, "ERROR: Unknown chunk in FIFO\n");
+ dropchunk:
+ //fprintf(stderr, "WARNING: Discarding chunk in FIFO\n");
+ if (!len)
+ break;
+ i = len;
+ do {
+ ax5043ReadReg(AX5043_FIFODATA); // purge FIFO
+ }
+ while (--i);
+ break;
+ }
+ }
+
+ //printf("INFO: Done waiting for a packet\n");
+
+ return bytesRead;
+}
diff --git a/ax5043/axradio/axradiorx.h b/ax5043/axradio/axradiorx.h
new file mode 100644
index 00000000..446da953
--- /dev/null
+++ b/ax5043/axradio/axradiorx.h
@@ -0,0 +1,55 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef AX5043RX_H_
+#define AX5043RX_H_
+
+#include
+
+#include "axradiorx_p.h"
+
+#endif /* AX5043RX_H_ */
diff --git a/ax5043/axradio/axradiorx_p.h b/ax5043/axradio/axradiorx_p.h
new file mode 100644
index 00000000..810642aa
--- /dev/null
+++ b/ax5043/axradio/axradiorx_p.h
@@ -0,0 +1,65 @@
+/*!
+ \copyright
+ Copyright (c) 2018 Brandenburg Tech, LLC
+ All rights reserved.
+
+ THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+ AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1.Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2.Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3.Neither the name of AXSEM AG, Duebendorf nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ 4.All advertising materials mentioning features or use of this software
+ must display the following acknowledgement:
+ This product includes software developed by AXSEM AG and its contributors.
+ 5.The usage of this source code is only granted for operation with AX5043
+ and AX8052F143. Porting to other radio or communication devices is
+ strictly prohibited.
+
+ THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ \file axradiorx_p.h
+ \brief Provides an interface to receive packets using the digital transceiver.
+*/
+
+#ifndef AX5043RX_P_H_
+#define AX5043RX_P_H_
+
+#include
+
+/*! \fn uint8_t receive_packet(void)
+ \brief Receive a packet from the digital transceiver receive buffer.
+ \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t receive_packet(void);
+
+#endif /* AX5043RX_P_H_ */
diff --git a/ax5043/axradio/axradiotx.c b/ax5043/axradio/axradiotx.c
new file mode 100644
index 00000000..007b24e1
--- /dev/null
+++ b/ax5043/axradio/axradiotx.c
@@ -0,0 +1,301 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "axradiotx.h"
+
+//#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../ax5043support/ax5043tx.h"
+#include "../crc/crc.h"
+#include "../generated/config.h"
+#include "../spi/ax5043spi_p.h"
+#include "axradioinit.h"
+#include "axradioinit_p.h"
+#include "axradiomode.h"
+
+static void transmit_loop(axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,
+ uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt);
+
+extern const uint16_t axradio_phy_preamble_len;
+extern const uint8_t axradio_phy_preamble_flags;
+extern const uint8_t axradio_phy_preamble_byte;
+extern const uint8_t axradio_phy_preamble_appendbits;
+extern const uint8_t axradio_phy_preamble_appendpattern;
+extern const uint16_t axradio_phy_preamble_longlen;
+extern const uint8_t axradio_phy_pn9;
+
+extern const uint8_t axradio_framing_synclen;
+extern const uint8_t axradio_framing_syncflags;
+extern const uint8_t axradio_framing_syncword[];
+
+extern const uint8_t axradio_framing_maclen;
+extern const uint8_t axradio_framing_addrlen;
+extern const uint8_t axradio_framing_destaddrpos;
+extern const uint8_t axradio_framing_sourceaddrpos;
+extern const uint8_t axradio_framing_lenpos;
+extern const uint8_t axradio_framing_lenoffs;
+extern const uint8_t axradio_framing_lenmask;
+extern const uint8_t axradio_framing_swcrclen;
+
+uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen) {
+ axradio_trxstate_t axradio_trxstate;
+ uint16_t axradio_txbuffer_len;
+ uint8_t axradio_txbuffer[PKTDATA_BUFLEN];
+ struct axradio_address_mask axradio_localaddr;
+ uint16_t axradio_txbuffer_cnt = 0;
+
+ axradio_txbuffer_len = pktlen + axradio_framing_maclen;
+ if (axradio_txbuffer_len > sizeof(axradio_txbuffer))
+ return AXRADIO_ERR_INVALID;
+ memset(axradio_txbuffer, 0, axradio_framing_maclen);
+ memcpy(&axradio_txbuffer[axradio_framing_maclen], pkt, pktlen);
+ if (axradio_framing_destaddrpos != 0xff)
+ memcpy(&axradio_txbuffer[axradio_framing_destaddrpos], &addr->addr, axradio_framing_addrlen);
+ if (axradio_framing_sourceaddrpos != 0xff)
+ memcpy(&axradio_txbuffer[axradio_framing_sourceaddrpos], &axradio_localaddr.addr, axradio_framing_addrlen);
+ if (axradio_framing_lenmask) {
+ uint8_t len_byte = (uint8_t)(axradio_txbuffer_len - axradio_framing_lenoffs) & axradio_framing_lenmask; // if you prefer not counting the len byte itself, set LENOFFS = 1
+ axradio_txbuffer[axradio_framing_lenpos] = (axradio_txbuffer[axradio_framing_lenpos] & (uint8_t)~axradio_framing_lenmask) | len_byte;
+ }
+ if (axradio_framing_swcrclen)
+ axradio_txbuffer_len = axradio_framing_append_crc(axradio_txbuffer, axradio_txbuffer_len);
+ if (axradio_phy_pn9)
+ pn9_buffer(axradio_txbuffer, axradio_txbuffer_len, 0x1ff, -(ax5043ReadReg(AX5043_ENCODING) & 0x01));
+ axradio_txbuffer_cnt = axradio_phy_preamble_longlen;
+
+ ax5043_prepare_tx();
+
+ ax5043ReadReg(AX5043_RADIOEVENTREQ0); // make sure REVRDONE bit is cleared, so it is a reliable indicator that the packet is out
+ ax5043WriteReg(AX5043_FIFOSTAT, 3); // clear FIFO data & flags (prevent transmitting anything left over in the FIFO, this has no effect if the FIFO is not powerered, in this case it is reset any way)
+ axradio_trxstate = trxstate_tx_longpreamble;
+
+ if ((ax5043ReadReg(AX5043_MODULATION) & 0x0F) == 9) { // 4-FSK
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, 2); // length (including flags)
+ ax5043WriteReg(AX5043_FIFODATA, 0x01); // flag PKTSTART -> dibit sync
+ ax5043WriteReg(AX5043_FIFODATA, 0x11); // dummy byte for forcing dibit sync
+ }
+ transmit_loop(axradio_trxstate, axradio_txbuffer_len, axradio_txbuffer, axradio_txbuffer_cnt);
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_FULL_TX);
+
+ ax5043ReadReg(AX5043_RADIOEVENTREQ0);
+ //printf("INFO: Waiting for transmission to complete\n");
+ while (ax5043ReadReg(AX5043_RADIOSTATE) != 0) {
+ usleep(1000);
+ }
+ //printf("INFO: Transmission complete\n");
+
+ ax5043WriteReg(AX5043_RADIOEVENTMASK0, 0x00);
+
+ return AXRADIO_ERR_NOERROR;
+}
+
+static void transmit_loop(axradio_trxstate_t axradio_trxstate, uint16_t axradio_txbuffer_len,
+ uint8_t axradio_txbuffer[], uint16_t axradio_txbuffer_cnt)
+{
+
+ for (;;) {
+ uint8_t cnt = ax5043ReadReg(AX5043_FIFOFREE0);
+
+ if (ax5043ReadReg(AX5043_FIFOFREE1))
+ cnt = 0xff;
+
+ switch (axradio_trxstate) {
+ case trxstate_tx_longpreamble:
+ if (!axradio_txbuffer_cnt) {
+ axradio_trxstate = trxstate_tx_shortpreamble;
+ axradio_txbuffer_cnt = axradio_phy_preamble_len;
+ goto shortpreamble;
+ }
+ if (cnt < 4) {
+ ax5043WriteReg(AX5043_FIFOSTAT, 4); // commit
+ usleep(1000);
+ continue;
+ }
+ cnt = 7;
+ if (axradio_txbuffer_cnt < 7)
+ cnt = axradio_txbuffer_cnt;
+ axradio_txbuffer_cnt -= cnt;
+ cnt <<= 5;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, axradio_phy_preamble_flags);
+ ax5043WriteReg(AX5043_FIFODATA, cnt);
+ ax5043WriteReg(AX5043_FIFODATA, axradio_phy_preamble_byte);
+ break;
+
+ case trxstate_tx_shortpreamble:
+ shortpreamble:
+ if (!axradio_txbuffer_cnt) {
+ if (cnt < 15) {
+ ax5043WriteReg(AX5043_FIFOSTAT, 4); // commit
+ usleep(1000);
+ continue;
+ }
+ if (axradio_phy_preamble_appendbits) {
+ uint8_t byte;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, 0x1C);
+ byte = axradio_phy_preamble_appendpattern;
+ if (ax5043ReadReg(AX5043_PKTADDRCFG) & 0x80) {
+ // msb first -> stop bit below
+ byte &= 0xFF << (8-axradio_phy_preamble_appendbits);
+ byte |= 0x80 >> axradio_phy_preamble_appendbits;
+ } else {
+ // lsb first -> stop bit above
+ byte &= 0xFF >> (8-axradio_phy_preamble_appendbits);
+ byte |= 0x01 << axradio_phy_preamble_appendbits;
+ }
+ ax5043WriteReg(AX5043_FIFODATA, byte);
+ }
+ if ((ax5043ReadReg(AX5043_FRAMING) & 0x0E) == 0x06 && axradio_framing_synclen) {
+ // write SYNC word if framing mode is raw_patternmatch, might use SYNCLEN > 0 as a criterion, but need to make sure SYNCLEN=0 for WMBUS (chip automatically sends SYNCWORD but matching in RX works via MATCH0PAT)
+ uint8_t len_byte = axradio_framing_synclen;
+ uint8_t i = (len_byte & 0x07) ? 0x04 : 0;
+ // SYNCLEN in bytes, rather than bits. Ceiled to next integer e.g. fractional bits are counted as full bits;
+ len_byte += 7;
+ len_byte >>= 3;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_DATA | ((len_byte + 1) << 5));
+ ax5043WriteReg(AX5043_FIFODATA, axradio_framing_syncflags | i);
+ for (i = 0; i < len_byte; ++i) {
+ // better put a brace, it might prevent SDCC from optimizing away the assignement...
+ ax5043WriteReg(AX5043_FIFODATA, axradio_framing_syncword[i]);
+ }
+ }
+ axradio_trxstate = trxstate_tx_packet;
+ continue;
+ }
+ if (cnt < 4) {
+ ax5043WriteReg(AX5043_FIFOSTAT, 4); // commit
+ usleep(1000);
+ continue;
+ }
+ cnt = 255;
+ if (axradio_txbuffer_cnt < 255*8)
+ cnt = axradio_txbuffer_cnt >> 3;
+ if (cnt) {
+ axradio_txbuffer_cnt -= ((uint16_t)cnt) << 3;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_REPEATDATA | (3 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, axradio_phy_preamble_flags);
+ ax5043WriteReg(AX5043_FIFODATA, cnt);
+ ax5043WriteReg(AX5043_FIFODATA, axradio_phy_preamble_byte);
+ continue;
+ }
+ {
+ uint8_t byte = axradio_phy_preamble_byte;
+ cnt = axradio_txbuffer_cnt;
+ axradio_txbuffer_cnt = 0;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_DATA | (2 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, 0x1C);
+ if (ax5043ReadReg(AX5043_PKTADDRCFG) & 0x80) {
+ // msb first -> stop bit below
+ byte &= 0xFF << (8-cnt);
+ byte |= 0x80 >> cnt;
+ } else {
+ // lsb first -> stop bit above
+ byte &= 0xFF >> (8-cnt);
+ byte |= 0x01 << cnt;
+ }
+ ax5043WriteReg(AX5043_FIFODATA, byte);
+ }
+ continue;
+
+ case trxstate_tx_packet:
+ if (cnt < 11) {
+ ax5043WriteReg(AX5043_FIFOSTAT, 4); // commit
+ usleep(1000);
+ continue;
+ }
+ {
+ uint8_t flags = 0;
+ if (!axradio_txbuffer_cnt)
+ flags |= 0x01; // flag byte: pkt_start
+ {
+ uint16_t len = axradio_txbuffer_len - axradio_txbuffer_cnt;
+ cnt -= 3;
+ if (cnt >= len) {
+ cnt = len;
+ flags |= 0x02; // flag byte: pkt_end
+ }
+ }
+ if (!cnt)
+ goto pktend;
+ ax5043WriteReg(AX5043_FIFODATA, AX5043_FIFOCMD_DATA | (7 << 5));
+ ax5043WriteReg(AX5043_FIFODATA, cnt + 1); // write FIFO chunk length byte (length includes the flag byte, thus the +1)
+ ax5043WriteReg(AX5043_FIFODATA, flags);
+ ax5043_writefifo(&axradio_txbuffer[axradio_txbuffer_cnt], cnt);
+ axradio_txbuffer_cnt += cnt;
+ if (flags & 0x02)
+ goto pktend;
+ }
+ break;
+
+ default:
+ fprintf(stderr, "ERROR: Unexpected state found in transmit_isr\n");
+ exit(EXIT_FAILURE);
+ }
+ }
+
+pktend:
+ ax5043WriteReg(AX5043_RADIOEVENTMASK0, 0x01); // enable REVRDONE event
+ ax5043WriteReg(AX5043_FIFOSTAT, 4); // commit
+}
+
+void ax5043_prepare_tx(void)
+{
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_XTAL_ON);
+ ax5043WriteReg(AX5043_PWRMODE, AX5043_PWRSTATE_FIFO_ON);
+ ax5043_init_registers_tx();
+ ax5043WriteReg(AX5043_FIFOTHRESH1, 0);
+ ax5043WriteReg(AX5043_FIFOTHRESH0, 0x80);
+ axradio_wait_for_xtal();
+ ax5043ReadReg(AX5043_POWSTICKYSTAT); // clear pwr management sticky status --> brownout gate works
+}
diff --git a/ax5043/axradio/axradiotx.h b/ax5043/axradio/axradiotx.h
new file mode 100644
index 00000000..c3df650f
--- /dev/null
+++ b/ax5043/axradio/axradiotx.h
@@ -0,0 +1,53 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef AX5043TX_H_
+#define AX5043TX_H_
+
+void ax5043_prepare_tx(void);
+
+#endif /* AX5043TX_H_ */
diff --git a/ax5043/axradio/axradiotx_p.h b/ax5043/axradio/axradiotx_p.h
new file mode 100644
index 00000000..2abf86a5
--- /dev/null
+++ b/ax5043/axradio/axradiotx_p.h
@@ -0,0 +1,68 @@
+/*!
+ \copyright
+ Copyright (c) 2018 Brandenburg Tech, LLC
+ All rights reserved.
+
+ THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+ AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1.Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2.Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3.Neither the name of AXSEM AG, Duebendorf nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ 4.All advertising materials mentioning features or use of this software
+ must display the following acknowledgement:
+ This product includes software developed by AXSEM AG and its contributors.
+ 5.The usage of this source code is only granted for operation with AX5043
+ and AX8052F143. Porting to other radio or communication devices is
+ strictly prohibited.
+
+ THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ \file axradiotx_p.h
+ \brief Provides an interface to transmit packets using the digital transceiver.
+*/
+
+#ifndef AX5043TX_P_H_
+#define AX5043TX_P_H_
+
+#include
+
+/*! \fn uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen)
+ \brief Transmit a packet using the digital transceiver
+ \param addr The address of the desired destiantion radio, if used.
+ \param pkt The byte data to be transmitted.
+ \param pktlen The number of bytes in pkt to be transmitted.
+ \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
+ \sa AXRADIO_ERR_NOERROR
+*/
+uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen);
+
+#endif /* AX5043TX_P_H_ */
diff --git a/ax5043/crc/crc.c b/ax5043/crc/crc.c
new file mode 100644
index 00000000..ed497f9d
--- /dev/null
+++ b/ax5043/crc/crc.c
@@ -0,0 +1,111 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#include "crc.h"
+
+/* Polynomial: x^16 + x^15 + x^2 + 1 = 0x18005 LSB first */
+
+const uint16_t crc_crc16_table[256] = {
+ 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241,
+ 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440,
+ 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40,
+ 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841,
+ 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40,
+ 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41,
+ 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641,
+ 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040,
+ 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240,
+ 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441,
+ 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41,
+ 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840,
+ 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41,
+ 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40,
+ 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640,
+ 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041,
+ 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240,
+ 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441,
+ 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41,
+ 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840,
+ 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41,
+ 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40,
+ 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640,
+ 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041,
+ 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241,
+ 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440,
+ 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40,
+ 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841,
+ 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40,
+ 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41,
+ 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641,
+ 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040
+};
+
+uint16_t crc_crc16(const uint8_t *buf, uint16_t buflen, uint16_t crc)
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_crc16_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+uint16_t crc_crc16_byte(uint16_t crc, uint8_t c)
+{
+ return (crc >> 8) ^ crc_crc16_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+uint16_t pn9_buffer(uint8_t *buf, uint16_t buflen, uint16_t pn9, uint8_t xor)
+{
+ if (!buflen)
+ return pn9;
+ do {
+ *buf++ ^= pn9 ^ xor;
+ pn9 = pn9_advance_byte(pn9);
+ } while (--buflen);
+ return pn9;
+}
+
+uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits)
+{
+ if (!bits)
+ return pn9;
+ do {
+ pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
+ } while (--bits);
+ return pn9;
+}
+
+uint16_t pn9_advance_byte(uint16_t pn9)
+{
+ uint8_t bits = 8;
+ do {
+ pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
+ } while (--bits);
+ return pn9;
+}
diff --git a/ax5043/crc/crc.h b/ax5043/crc/crc.h
new file mode 100644
index 00000000..ea221ed4
--- /dev/null
+++ b/ax5043/crc/crc.h
@@ -0,0 +1,40 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All rights reserved.
+//
+// This file is derived from LibMF, a library provided AXSEM AG. Based on the
+// context of the library and the provision of source code, it is assumed
+// the source code can be modified for specific applications of the AX5043.
+//
+// The documentation provides the following notice:
+// LibMF is available in source and binary form for SDCC, Keil C51 and IAR
+// ICC.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// The original files did not contain a copyright notice for AXSEM AG, but the
+// documentation contained the following notice.
+//
+// Copyright (c) 2011, 2012, 2013 AXSEM AG
+
+#ifndef CRC_H_
+#define CRC_H_
+
+#include
+
+uint16_t crc_crc16(const uint8_t *buf, uint16_t buflen, uint16_t crc);
+uint16_t crc_crc16_byte(uint16_t crc, uint8_t c);
+uint16_t pn9_buffer(uint8_t *buf, uint16_t buflen, uint16_t pn9, uint8_t xor);
+uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits);
+uint16_t pn9_advance_byte(uint16_t pn9);
+
+#endif /* CRC_H_ */
diff --git a/ax5043/doc/TransceiverFramework.pdf b/ax5043/doc/TransceiverFramework.pdf
new file mode 100644
index 00000000..9739e121
Binary files /dev/null and b/ax5043/doc/TransceiverFramework.pdf differ
diff --git a/ax5043/generated/config.c b/ax5043/generated/config.c
new file mode 100644
index 00000000..621d0c05
--- /dev/null
+++ b/ax5043/generated/config.c
@@ -0,0 +1,399 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+/* Warning: This file is automatically generated by AX-RadioLAB.
+ Manual changes are overwritten! */
+
+#include "config.h"
+
+#include "../axradio/axradioinit.h"
+#include "../spi/ax5043spi.h"
+#include "../crc/crc.h"
+
+// TX: fcarrier=435.300MHz dev= 13.600kHz br= 4.800kBit/s pwr= 15.0dBm
+// RX: fcarrier=435.300MHz bw= 28.200kHz br= 4.800kBit/s
+
+ void ax5043_set_registers(void)
+{
+ ax5043WriteReg(AX5043_MODULATION, 0x08);
+ ax5043WriteReg(AX5043_ENCODING, 0x00);
+ ax5043WriteReg(AX5043_FRAMING, 0x24);
+ ax5043WriteReg(AX5043_FEC, 0x13);
+ ax5043WriteReg(AX5043_PINFUNCSYSCLK, 0x01);
+ ax5043WriteReg(AX5043_PINFUNCDCLK, 0x01);
+ ax5043WriteReg(AX5043_PINFUNCDATA, 0x01);
+ ax5043WriteReg(AX5043_PINFUNCANTSEL, 0x01);
+ ax5043WriteReg(AX5043_PINFUNCPWRAMP, 0x01);
+ ax5043WriteReg(AX5043_WAKEUPXOEARLY, 0x01);
+ ax5043WriteReg(AX5043_IFFREQ1, 0x06);
+ ax5043WriteReg(AX5043_IFFREQ0, 0x04);
+ ax5043WriteReg(AX5043_DECIMATION, 0x07);
+ ax5043WriteReg(AX5043_RXDATARATE2, 0x00);
+ ax5043WriteReg(AX5043_RXDATARATE1, 0xEE);
+ ax5043WriteReg(AX5043_RXDATARATE0, 0x18);
+ ax5043WriteReg(AX5043_MAXDROFFSET2, 0x00);
+ ax5043WriteReg(AX5043_MAXDROFFSET1, 0x00);
+ ax5043WriteReg(AX5043_MAXDROFFSET0, 0x00);
+ ax5043WriteReg(AX5043_MAXRFOFFSET2, 0x80);
+ ax5043WriteReg(AX5043_MAXRFOFFSET1, 0x23);
+ ax5043WriteReg(AX5043_MAXRFOFFSET0, 0xA9);
+ ax5043WriteReg(AX5043_FSKDMAX1, 0x05);
+ ax5043WriteReg(AX5043_FSKDMAX0, 0x76);
+ ax5043WriteReg(AX5043_FSKDMIN1, 0xFA);
+ ax5043WriteReg(AX5043_FSKDMIN0, 0x8A);
+ ax5043WriteReg(AX5043_AMPLFILTER, 0x00);
+ ax5043WriteReg(AX5043_RXPARAMSETS, 0xF4);
+ ax5043WriteReg(AX5043_AGCGAIN0, 0xC6);
+ ax5043WriteReg(AX5043_AGCTARGET0, 0x84);
+ ax5043WriteReg(AX5043_TIMEGAIN0, 0xEA);
+ ax5043WriteReg(AX5043_DRGAIN0, 0xE4);
+ ax5043WriteReg(AX5043_PHASEGAIN0, 0xC3);
+ ax5043WriteReg(AX5043_FREQUENCYGAINA0, 0x0F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINB0, 0x1F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINC0, 0x0A);
+ ax5043WriteReg(AX5043_FREQUENCYGAIND0, 0x0A);
+ ax5043WriteReg(AX5043_AMPLITUDEGAIN0, 0x06);
+ ax5043WriteReg(AX5043_FREQDEV10, 0x00);
+ ax5043WriteReg(AX5043_FREQDEV00, 0x00);
+ ax5043WriteReg(AX5043_BBOFFSRES0, 0x00);
+ ax5043WriteReg(AX5043_AGCGAIN1, 0xC6);
+ ax5043WriteReg(AX5043_AGCTARGET1, 0x84);
+ ax5043WriteReg(AX5043_AGCAHYST1, 0x00);
+ ax5043WriteReg(AX5043_AGCMINMAX1, 0x00);
+ ax5043WriteReg(AX5043_TIMEGAIN1, 0xE8);
+ ax5043WriteReg(AX5043_DRGAIN1, 0xE3);
+ ax5043WriteReg(AX5043_PHASEGAIN1, 0xC3);
+ ax5043WriteReg(AX5043_FREQUENCYGAINA1, 0x0F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINB1, 0x1F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINC1, 0x0A);
+ ax5043WriteReg(AX5043_FREQUENCYGAIND1, 0x0A);
+ ax5043WriteReg(AX5043_AMPLITUDEGAIN1, 0x06);
+ ax5043WriteReg(AX5043_FREQDEV11, 0x02);
+ ax5043WriteReg(AX5043_FREQDEV01, 0x36);
+ ax5043WriteReg(AX5043_FOURFSK1, 0x16);
+ ax5043WriteReg(AX5043_BBOFFSRES1, 0x00);
+ ax5043WriteReg(AX5043_AGCGAIN3, 0xFF);
+ ax5043WriteReg(AX5043_AGCTARGET3, 0x84);
+ ax5043WriteReg(AX5043_AGCAHYST3, 0x00);
+ ax5043WriteReg(AX5043_AGCMINMAX3, 0x00);
+ ax5043WriteReg(AX5043_TIMEGAIN3, 0xE7);
+ ax5043WriteReg(AX5043_DRGAIN3, 0xE2);
+ ax5043WriteReg(AX5043_PHASEGAIN3, 0xC3);
+ ax5043WriteReg(AX5043_FREQUENCYGAINA3, 0x0F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINB3, 0x1F);
+ ax5043WriteReg(AX5043_FREQUENCYGAINC3, 0x0D);
+ ax5043WriteReg(AX5043_FREQUENCYGAIND3, 0x0D);
+ ax5043WriteReg(AX5043_AMPLITUDEGAIN3, 0x06);
+ ax5043WriteReg(AX5043_FREQDEV13, 0x02);
+ ax5043WriteReg(AX5043_FREQDEV03, 0x36);
+ ax5043WriteReg(AX5043_FOURFSK3, 0x16);
+ ax5043WriteReg(AX5043_BBOFFSRES3, 0x00);
+ ax5043WriteReg(AX5043_MODCFGF, 0x03);
+ ax5043WriteReg(AX5043_FSKDEV2, 0x00);
+ ax5043WriteReg(AX5043_FSKDEV1, 0x37);
+ ax5043WriteReg(AX5043_FSKDEV0, 0xB5);
+ ax5043WriteReg(AX5043_MODCFGA, 0x05);
+ ax5043WriteReg(AX5043_TXRATE2, 0x00);
+ ax5043WriteReg(AX5043_TXRATE1, 0x13);
+ ax5043WriteReg(AX5043_TXRATE0, 0xA9);
+ ax5043WriteReg(AX5043_TXPWRCOEFFB1, 0x0F);
+ ax5043WriteReg(AX5043_TXPWRCOEFFB0, 0xFF);
+ ax5043WriteReg(AX5043_PLLVCOI, 0x99);
+ ax5043WriteReg(AX5043_PLLRNGCLK, 0x03);
+ ax5043WriteReg(AX5043_BBTUNE, 0x0F);
+ ax5043WriteReg(AX5043_BBOFFSCAP, 0x77);
+ ax5043WriteReg(AX5043_PKTADDRCFG, 0x00);
+ ax5043WriteReg(AX5043_PKTLENCFG, 0x80);
+ ax5043WriteReg(AX5043_PKTLENOFFSET, 0x00);
+ ax5043WriteReg(AX5043_PKTMAXLEN, 0xC8);
+ ax5043WriteReg(AX5043_MATCH0PAT3, 0xAA);
+ ax5043WriteReg(AX5043_MATCH0PAT2, 0xCC);
+ ax5043WriteReg(AX5043_MATCH0PAT1, 0xAA);
+ ax5043WriteReg(AX5043_MATCH0PAT0, 0xCC);
+ ax5043WriteReg(AX5043_MATCH1PAT1, 0x7E);
+ ax5043WriteReg(AX5043_MATCH1PAT0, 0x7E);
+ ax5043WriteReg(AX5043_MATCH1LEN, 0x8A);
+ ax5043WriteReg(AX5043_MATCH1MAX, 0x0A);
+ ax5043WriteReg(AX5043_TMGTXBOOST, 0x32);
+ ax5043WriteReg(AX5043_TMGTXSETTLE, 0x14);
+ ax5043WriteReg(AX5043_TMGRXBOOST, 0x32);
+ ax5043WriteReg(AX5043_TMGRXSETTLE, 0x14);
+ ax5043WriteReg(AX5043_TMGRXOFFSACQ, 0x00);
+ ax5043WriteReg(AX5043_TMGRXCOARSEAGC, 0x73);
+ ax5043WriteReg(AX5043_TMGRXRSSI, 0x03);
+ ax5043WriteReg(AX5043_TMGRXPREAMBLE2, 0x17);
+ ax5043WriteReg(AX5043_RSSIABSTHR, 0xE6);
+ ax5043WriteReg(AX5043_BGNDRSSITHR, 0x00);
+ ax5043WriteReg(AX5043_PKTCHUNKSIZE, 0x0D);
+ ax5043WriteReg(AX5043_PKTACCEPTFLAGS, 0x20);
+ ax5043WriteReg(AX5043_DACVALUE1, 0x00);
+ ax5043WriteReg(AX5043_DACVALUE0, 0x00);
+ ax5043WriteReg(AX5043_DACCONFIG, 0x00);
+ ax5043WriteReg(AX5043_REF, 0x03);
+ ax5043WriteReg(AX5043_XTALOSC, 0x03);
+ ax5043WriteReg(AX5043_XTALAMPL, 0x07);
+ ax5043WriteReg(AX5043_0xF1C, 0x07);
+ ax5043WriteReg(AX5043_0xF21, 0x68);
+ ax5043WriteReg(AX5043_0xF22, 0xFF);
+ ax5043WriteReg(AX5043_0xF23, 0x84);
+ ax5043WriteReg(AX5043_0xF26, 0x98);
+ ax5043WriteReg(AX5043_0xF34, 0x28);
+ ax5043WriteReg(AX5043_0xF35, 0x10);
+ ax5043WriteReg(AX5043_0xF44, 0x25);
+}
+
+
+ void ax5043_set_registers_tx(void)
+{
+ ax5043WriteReg(AX5043_PLLLOOP, 0x09);
+ ax5043WriteReg(AX5043_PLLCPI, 0x02);
+ ax5043WriteReg(AX5043_PLLVCODIV, 0x24);
+ ax5043WriteReg(AX5043_XTALCAP, 0x0C);
+ ax5043WriteReg(AX5043_0xF00, 0x0F);
+ ax5043WriteReg(AX5043_0xF18, 0x06);
+}
+
+
+ void ax5043_set_registers_rx(void)
+{
+ ax5043WriteReg(AX5043_PLLLOOP, 0x0B);
+ ax5043WriteReg(AX5043_PLLCPI, 0x10);
+ ax5043WriteReg(AX5043_PLLVCODIV, 0x24);
+ ax5043WriteReg(AX5043_XTALCAP, 0x0C);
+ ax5043WriteReg(AX5043_0xF00, 0x0F);
+ ax5043WriteReg(AX5043_0xF18, 0x02);
+}
+
+
+ void ax5043_set_registers_rxwor(void)
+{
+ ax5043WriteReg(AX5043_TMGRXAGC, 0x37);
+ ax5043WriteReg(AX5043_TMGRXPREAMBLE1, 0x19);
+ ax5043WriteReg(AX5043_PKTMISCFLAGS, 0x03);
+}
+
+
+ void ax5043_set_registers_rxcont(void)
+{
+ ax5043WriteReg(AX5043_TMGRXAGC, 0x00);
+ ax5043WriteReg(AX5043_TMGRXPREAMBLE1, 0x00);
+ ax5043WriteReg(AX5043_PKTMISCFLAGS, 0x00);
+}
+
+
+ void ax5043_set_registers_rxcont_singleparamset(void)
+{
+ ax5043WriteReg(AX5043_RXPARAMSETS, 0xFF);
+ ax5043WriteReg(AX5043_FREQDEV13, 0x00);
+ ax5043WriteReg(AX5043_FREQDEV03, 0x00);
+ ax5043WriteReg(AX5043_AGCGAIN3, 0xE8);
+}
+
+
+#define MUL8_16(x,y) ((uint8_t)((x)&0xff)*(uint16_t)(uint8_t)((y)&0xff))
+
+#define CONSTMULFIX24(x) \
+ if (f >= 0) { \
+ uint32_t r = MUL8_16((x)>>16,f); \
+ r += MUL8_16((x)>>8,f>>8); \
+ r += MUL8_16((x),f>>16); \
+ r >>= 8; \
+ r += MUL8_16((x)>>24,f); \
+ r += MUL8_16((x)>>16,f>>8); \
+ r += MUL8_16((x)>>8,f>>16); \
+ r += MUL8_16((x),f>>24); \
+ r += ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
+ r += ((uint32_t)MUL8_16((x)>>16,f>>16))<<8; \
+ r += ((uint32_t)MUL8_16((x)>>8,f>>24))<<8; \
+ r += ((uint32_t)MUL8_16((x)>>24,f>>16))<<16; \
+ r += ((uint32_t)MUL8_16((x)>>16,f>>24))<<16; \
+ r += ((uint32_t)MUL8_16((x)>>24,f>>24))<<24; \
+ return r; \
+ } \
+ { \
+ int32_t r; \
+ f = -f; \
+ r = -(uint32_t)MUL8_16((x)>>16,f); \
+ r -= (uint32_t)MUL8_16((x)>>8,f>>8); \
+ r -= (uint32_t)MUL8_16((x),f>>16); \
+ r >>= 8; \
+ r -= (uint32_t)MUL8_16((x)>>24,f); \
+ r -= (uint32_t)MUL8_16((x)>>16,f>>8); \
+ r -= (uint32_t)MUL8_16((x)>>8,f>>16); \
+ r -= (uint32_t)MUL8_16((x),f>>24); \
+ r -= ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
+ r -= ((uint32_t)MUL8_16((x)>>16,f>>16))<<8; \
+ r -= ((uint32_t)MUL8_16((x)>>8,f>>24))<<8; \
+ r -= ((uint32_t)MUL8_16((x)>>24,f>>16))<<16; \
+ r -= ((uint32_t)MUL8_16((x)>>16,f>>24))<<16; \
+ r -= ((uint32_t)MUL8_16((x)>>24,f>>24))<<24; \
+ return r; \
+ }
+
+#define CONSTMULFIX16(x) \
+ if (f >= 0) { \
+ uint32_t r = MUL8_16((x)>>16,f); \
+ r += MUL8_16((x)>>8,f>>8); \
+ r >>= 8; \
+ r += MUL8_16((x)>>24,f); \
+ r += MUL8_16((x)>>16,f>>8); \
+ r += ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
+ return r; \
+ } \
+ { \
+ int32_t r; \
+ f = -f; \
+ r = -(uint32_t)MUL8_16((x)>>16,f); \
+ r -= (uint32_t)MUL8_16((x)>>8,f>>8); \
+ r >>= 8; \
+ r -= (uint32_t)MUL8_16((x)>>24,f); \
+ r -= (uint32_t)MUL8_16((x)>>16,f>>8); \
+ r -= ((uint32_t)MUL8_16((x)>>24,f>>8))<<8; \
+ return r; \
+ }
+
+ int32_t axradio_conv_freq_fromhz(int32_t f)
+{
+ /* scale by 1.048576 (true 1.048576) */
+ CONSTMULFIX24(0x10c6f7a);
+}
+
+ int32_t axradio_conv_freq_tohz(int32_t f)
+{
+ /* scale by 0.953674 (true 0.953674) */
+ CONSTMULFIX24(0xf42400);
+}
+
+const uint8_t axradio_phy_innerfreqloop = 0;
+
+ int32_t axradio_conv_freq_fromreg(int32_t f)
+{
+ /* scale by 1.000000 (true 1.000000) */
+ CONSTMULFIX16(0x1000000);
+}
+
+ int32_t axradio_conv_timeinterval_totimer0(int32_t dt)
+{
+ /* scale by 0.032776 (true 0.032768) */
+ int32_t r;
+ dt >>= 5;
+ r = dt;
+ dt >>= 4;
+ r += dt;
+ dt >>= 2;
+ r -= dt;
+ dt >>= 3;
+ r += dt;
+ return r;
+}
+
+ uint8_t axradio_byteconv(uint8_t b)
+{
+ return b;
+}
+
+
+ void axradio_byteconv_buffer(uint8_t *buf __attribute__((unused)), uint16_t buflen __attribute__((unused)))
+{
+}
+
+ uint16_t axradio_framing_check_crc(uint8_t *pkt, uint16_t cnt)
+{
+ if (crc_crc16(pkt, cnt, 0xFFFF) != 0xB001)
+ return 0;
+ return cnt;
+}
+
+ uint16_t axradio_framing_append_crc(uint8_t *pkt, uint16_t cnt)
+{
+ uint16_t s = 0xFFFF;
+ s = crc_crc16(pkt, cnt, s);
+ pkt += cnt;
+ *pkt++ = ~(uint8_t)(s);
+ *pkt++ = ~(uint8_t)(s >> 8);
+ return cnt + 2;
+}
+
+
+
+
+
+// physical layer
+const uint8_t axradio_phy_pn9 = 0;
+const uint8_t axradio_phy_nrchannels = 1;
+const uint32_t axradio_phy_chanfreq[1] = { 0x1b34cccd };
+const uint8_t axradio_phy_chanpllrnginit[1] = { 0x0a };
+const uint8_t axradio_phy_chanvcoiinit[1] = { 0x99 };
+uint8_t axradio_phy_chanpllrng[1];
+uint8_t axradio_phy_chanvcoi[1];
+const uint8_t axradio_phy_vcocalib = 0;
+const int32_t axradio_phy_maxfreqoffset = 27387;
+const int8_t axradio_phy_rssioffset = 64;
+// axradio_phy_rssioffset is added to AX5043_RSSIREFERENCE and subtracted from chip RSSI value to prevent overflows (8bit RSSI only goes down to -128)
+// axradio_phy_rssioffset is also added to AX5043_RSSIABSTHR
+const int8_t axradio_phy_rssireference = (int8_t)(0xF8 + 64);
+const int8_t axradio_phy_channelbusy = -90 + 64;
+const uint16_t axradio_phy_cs_period = 7; // timer0 units, 10ms
+const uint8_t axradio_phy_cs_enabled = 0;
+const uint8_t axradio_phy_lbt_retries = 0;
+const uint8_t axradio_phy_lbt_forcetx = 0;
+const uint16_t axradio_phy_preamble_wor_longlen = 2; // wor_longlen + wor_len totals to 240.0ms plus 112bits
+const uint16_t axradio_phy_preamble_wor_len = 176;
+const uint16_t axradio_phy_preamble_longlen = 0;
+const uint16_t axradio_phy_preamble_len = 112;
+const uint8_t axradio_phy_preamble_byte = 0x7e;
+const uint8_t axradio_phy_preamble_flags = 0x38;
+const uint8_t axradio_phy_preamble_appendbits = 0;
+const uint8_t axradio_phy_preamble_appendpattern = 0x00;
+
+//framing
+const uint8_t axradio_framing_maclen = 1;
+const uint8_t axradio_framing_addrlen = 0;
+const uint8_t axradio_framing_destaddrpos = 0;
+const uint8_t axradio_framing_sourceaddrpos = 0xff;
+const uint8_t axradio_framing_lenpos = 0;
+const uint8_t axradio_framing_lenoffs = 0;
+const uint8_t axradio_framing_lenmask = 0xff;
+const uint8_t axradio_framing_swcrclen = 0;
+
+const uint8_t axradio_framing_synclen = 32;
+const uint8_t axradio_framing_syncword[] = { 0xcc, 0xaa, 0xcc, 0xaa};
+const uint8_t axradio_framing_syncflags = 0x18;
+const uint8_t axradio_framing_enable_sfdcallback = 0;
+
+const uint32_t axradio_framing_ack_timeout = 65; // 98.9ms in wtimer0 units (640Hz)
+const uint32_t axradio_framing_ack_delay = 313; // 1.0ms in wtimer1 units (20MHz/64)
+const uint8_t axradio_framing_ack_retransmissions = 0;
+const uint8_t axradio_framing_ack_seqnrpos = 0xff;
+
+const uint8_t axradio_framing_minpayloadlen = 0; // must be set to 1 if the payload directly follows the destination address, and a CRC is configured
+//WOR
+const uint16_t axradio_wor_period = 128;
+
+// synchronous mode
+const uint32_t axradio_sync_period = 32768; // ACTUALLY FREQ, NOT PERIOD!
+const uint32_t axradio_sync_xoscstartup = 49;
+const uint32_t axradio_sync_slave_syncwindow = 98304; // 3.000s
+const uint32_t axradio_sync_slave_initialsyncwindow = 5898240; //180.000s
+const uint32_t axradio_sync_slave_syncpause = 19660800; // 600.000s
+const int16_t axradio_sync_slave_maxperiod = 2020; // in (2^SYNC_K1) * wtimer0 units
+const uint8_t axradio_sync_slave_resyncloss = 11; // resyncloss is one more than the number of missed packets to cause a resync
+// window 0 is the first window after synchronisation
+// window 1 is the window normally used when there are no lost packets
+// window 2 is used after one packet is lost, etc
+const uint8_t axradio_sync_slave_nrrx = 3;
+const uint32_t axradio_sync_slave_rxadvance[] = { 1833, 1796, 1874 };// 55.918ms, 54.788ms, 57.167ms
+const uint32_t axradio_sync_slave_rxwindow[] = { 1847, 1773, 1929 }; // 56.346ms, 54.086ms, 58.844ms
+const uint32_t axradio_sync_slave_rxtimeout = 3032; // 92.5ms, maximum duration of a packet
diff --git a/ax5043/generated/config.h b/ax5043/generated/config.h
new file mode 100644
index 00000000..3631b81e
--- /dev/null
+++ b/ax5043/generated/config.h
@@ -0,0 +1,29 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#include
+
+void ax5043_set_registers(void);
+void ax5043_set_registers_tx(void);
+void ax5043_set_registers_rx(void);
+void ax5043_set_registers_rxcont(void);
+int32_t axradio_conv_freq_fromhz(int32_t f);
+
+uint16_t axradio_framing_append_crc(uint8_t *pkt, uint16_t cnt);
+
+#endif /* CONFIG_H_ */
diff --git a/ax5043/generated/configcommon.c b/ax5043/generated/configcommon.c
new file mode 100644
index 00000000..75ce3cdd
--- /dev/null
+++ b/ax5043/generated/configcommon.c
@@ -0,0 +1,23 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "../axradio/axradioinit.h"
+#include "configrx.h"
+#include "configtx.h"
+
+const uint8_t framing_insert_counter = 1;
+const uint8_t framing_counter_pos = 0;
+
+const uint16_t lpxosc_settlingtime = 3000;
diff --git a/ax5043/generated/configrx.c b/ax5043/generated/configrx.c
new file mode 100644
index 00000000..377e1000
--- /dev/null
+++ b/ax5043/generated/configrx.c
@@ -0,0 +1,32 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+/* Warning: This file is automatically generated by AX-RadioLAB.
+ Manual changes are overwritten! */
+
+#include "configrx.h"
+
+#include "../axradio/axradioinit.h"
+#include "../axradio/axradioinit_p.h"
+
+const struct axradio_address remoteaddr_rx = {
+ { 0x32, 0x34, 0x00, 0x00}
+};
+const struct axradio_address_mask localaddr_rx = {
+ { 0x33, 0x34, 0x00, 0x00},
+ { 0x00, 0x00, 0x00, 0x00}
+};
+
+const uint16_t lposckfiltmax = 0xaec;
diff --git a/ax5043/generated/configrx.h b/ax5043/generated/configrx.h
new file mode 100644
index 00000000..1ba1ff2d
--- /dev/null
+++ b/ax5043/generated/configrx.h
@@ -0,0 +1,40 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+/* Warning: This file is automatically generated by AX-RadioLAB.
+Manual changes are overwritten! */
+
+#include "../axradio/axradioinit.h"
+
+
+#define USE_LCD
+#define USE_DBGLINK
+//#define USE_COM0
+//#define DEBUGMSG
+#define MCU_SLEEP
+#define WTIMER0_CLKSRC CLKSRC_LPOSC
+#define WTIMER0_PRESCALER 0x01
+#define RADIO_MODE_RX AXRADIO_MODE_ASYNC_RECEIVE
+#define FXTAL 48000000
+
+extern const struct axradio_address remoteaddr_rx;
+extern const struct axradio_address_mask localaddr_rx;
+
+extern const uint8_t framing_insert_counter;
+extern const uint8_t framing_counter_pos;
+
+extern const uint16_t lposckfiltmax;
+
+extern const uint16_t lpxosc_settlingtime;
diff --git a/ax5043/generated/configtx.c b/ax5043/generated/configtx.c
new file mode 100644
index 00000000..8e2157a6
--- /dev/null
+++ b/ax5043/generated/configtx.c
@@ -0,0 +1,32 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+/* Warning: This file is automatically generated by AX-RadioLAB.
+ Manual changes are overwritten! */
+
+#include "configtx.h"
+
+#include "../axradio/axradioinit.h"
+
+
+const struct axradio_address remoteaddr_tx = {
+ { 0x33, 0x34, 0x00, 0x00}
+};
+const struct axradio_address_mask localaddr_tx = {
+ { 0x32, 0x34, 0x00, 0x00},
+ { 0x00, 0x00, 0x00, 0x00}
+};
+
+const uint8_t demo_packet[] = { 0x00, 0x00, 0x55, 0x66, 0x77, 0x88 };
diff --git a/ax5043/generated/configtx.h b/ax5043/generated/configtx.h
new file mode 100644
index 00000000..94612bb4
--- /dev/null
+++ b/ax5043/generated/configtx.h
@@ -0,0 +1,36 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+/* Warning: This file is automatically generated by AX-RadioLAB.
+Manual changes are overwritten! */
+
+#include "../axradio/axradioinit_p.h"
+
+//#define USE_LCD
+//#define USE_DBGLINK
+#define USE_COM0
+//#define DEBUGMSG
+//#define MCU_SLEEP
+#define WTIMER0_CLKSRC CLKSRC_LPOSC
+#define WTIMER0_PRESCALER 0x01
+#define WTIMER0_PERIOD 0x0280
+#define RADIO_MODE_TX AXRADIO_MODE_ASYNC_TRANSMIT
+extern const struct axradio_address remoteaddr_tx;
+extern const struct axradio_address_mask localaddr_tx;
+extern const uint8_t demo_packet[6];
+extern const uint8_t framing_insert_counter;
+extern const uint8_t framing_counter_pos;
+
+extern const uint16_t lpxosc_settlingtime;
diff --git a/ax5043/images/logo55x55.png b/ax5043/images/logo55x55.png
new file mode 100644
index 00000000..7848ebe6
Binary files /dev/null and b/ax5043/images/logo55x55.png differ
diff --git a/ax5043/spi/ax5043spi.c b/ax5043/spi/ax5043spi.c
new file mode 100644
index 00000000..2392185b
--- /dev/null
+++ b/ax5043/spi/ax5043spi.c
@@ -0,0 +1,111 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "ax5043spi.h"
+
+//#include
+#include
+#include
+#include
+#include
+#include
+
+//#include "dummyspi.h"
+//#warning "For production builds, must not include dummyspi.h"
+#include
+#include
+
+int spiChannel = -1;
+int spiSpeed = -1;
+
+void setSpiChannel(int newSpiChannel) {
+ spiChannel = newSpiChannel;
+}
+
+void setSpiSpeed(int newSpiSpeed) {
+ spiSpeed = newSpiSpeed;
+}
+
+void initializeSpi() {
+ //printf("INFO: Initializing SPI\n");
+
+ if (spiChannel < 0) {
+ fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
+ exit(EXIT_FAILURE);
+ }
+ if (spiSpeed < 0) {
+ fprintf(stderr, "ERROR: invalid SPI speed %d\n", spiSpeed);
+ exit(EXIT_FAILURE);
+ }
+
+
+ int fd;
+
+ wiringPiSetup();
+
+ fd = wiringPiSPISetup(spiChannel, spiSpeed);
+ if (fd < 0) {
+ fprintf(stderr, "ERROR: Cannot open SPI bus with error %d, %s\n",
+ errno, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ //printf("INFO: Finished initializing SPI\n");
+}
+
+void ax5043WriteReg(uint16_t reg, uint8_t val) {
+ uint8_t buf[3];
+ int result;
+
+ if (spiChannel < 0) {
+ fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
+ exit(EXIT_FAILURE);
+ }
+
+ buf[0] = (unsigned char)(0x00f0 | ((reg & 0xf00) >> 8));
+ buf[1] = (reg & 0xff);
+ buf[2] = val & 0xff;
+
+ result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
+ if (result < 0) {
+ fprintf(stderr, "Failed to write the register with result %d and error %s\n",
+ result, strerror(result));
+ exit(EXIT_FAILURE);
+ }
+}
+
+uint8_t ax5043ReadReg(uint16_t reg) {
+ uint8_t buf[3];
+ int result;
+
+ if (spiChannel < 0) {
+ fprintf(stderr, "ERROR: invalid SPI channel %d\n", spiChannel);
+ exit(EXIT_FAILURE);
+ }
+
+ buf[0] = (unsigned char)(0x0070 | ((reg & 0xf00) >> 8));
+ buf[1] = (reg & 0xff);
+ buf[2] = 0x0000;
+
+ result = wiringPiSPIDataRW(spiChannel, buf, sizeof(buf));
+ if (result < 0) {
+ fprintf(stderr, "Failed to read register with result = %d and error %s\n",
+ result, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ //printf("DEBUG: read value: %d\n", (int)buf[2]);
+ return (buf[2] & 0xff);
+}
diff --git a/ax5043/spi/ax5043spi.h b/ax5043/spi/ax5043spi.h
new file mode 100644
index 00000000..51190cfd
--- /dev/null
+++ b/ax5043/spi/ax5043spi.h
@@ -0,0 +1,23 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef AX5043SPI_H_
+#define AX5043SPI_H_
+
+#include
+
+#include "ax5043spi_p.h"
+
+#endif /* AX5043SPI_H_ */
diff --git a/chat/spi/ax5043spi_p.h b/ax5043/spi/ax5043spi_p.h
similarity index 63%
rename from chat/spi/ax5043spi_p.h
rename to ax5043/spi/ax5043spi_p.h
index b6d4dc88..c81c0d8e 100644
--- a/chat/spi/ax5043spi_p.h
+++ b/ax5043/spi/ax5043spi_p.h
@@ -1,7 +1,23 @@
-/*! \file ax5043spi_p.h
- \brief Provides an abstraction layer for the SPI interface communicating to the digital transceiver
+/*! \copyright
+ Copyright (c) 2018 Brandenburg Tech, LLC
+ All right reserved.
+ ---
+ THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+ AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ \file ax5043spi_p.h
+ \brief Provides an abstraction layer for the SPI interface communicating to the digital transceiver
*/
-
+
#ifndef AX5043SPI_P_H_
#define AX5043SPI_P_H_
diff --git a/ax5043/spi/dummyspi.c b/ax5043/spi/dummyspi.c
new file mode 100644
index 00000000..64df3eee
--- /dev/null
+++ b/ax5043/spi/dummyspi.c
@@ -0,0 +1,29 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "dummyspi.h"
+
+int wiringPiSPIDataRW(int spiChannel __attribute__((unused)),
+ unsigned char buf[] __attribute__((unused)), int len __attribute__((unused))) {
+ return 0;
+}
+
+void wiringPiSetup() {
+}
+
+int wiringPiSPISetup(int spiChannel __attribute__((unused)),
+ int spiSpeed __attribute__((unused))) {
+ return 0;
+}
diff --git a/ax5043/spi/dummyspi.h b/ax5043/spi/dummyspi.h
new file mode 100644
index 00000000..32d7801b
--- /dev/null
+++ b/ax5043/spi/dummyspi.h
@@ -0,0 +1,23 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef DUMMYSPI_H_
+#define DUMMYSPI_H_
+
+int wiringPiSPIDataRW(int spiChannel, unsigned char buf[], int len);
+void wiringPiSetup();
+int wiringPiSPISetup(int spiChannel, int spiSpeed);
+
+#endif /* DUMMYSPI_H_ */
diff --git a/chat/.cproject b/chat/.cproject
new file mode 100644
index 00000000..adafe502
--- /dev/null
+++ b/chat/.cproject
@@ -0,0 +1,118 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/chat/.gitignore b/chat/.gitignore
index 37c3d007..3df573fe 100644
--- a/chat/.gitignore
+++ b/chat/.gitignore
@@ -1,2 +1 @@
-radiochat
-*.o
+/Debug/
diff --git a/chat/.project b/chat/.project
new file mode 100644
index 00000000..26855828
--- /dev/null
+++ b/chat/.project
@@ -0,0 +1,26 @@
+
+
+ chat
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/chat/.settings/language.settings.xml b/chat/.settings/language.settings.xml
new file mode 100644
index 00000000..33aecbb9
--- /dev/null
+++ b/chat/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/chat/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/chat/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 00000000..dc262ac2
--- /dev/null
+++ b/chat/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/CPATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1377630500/appendContributed=true
diff --git a/chat/Makefile b/chat/Makefile
deleted file mode 100644
index 31098c74..00000000
--- a/chat/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-all: radiochat
-
-rebuild: clean
-rebuild: all
-
-clean:
- rm -f radiochat
- rm -f *.o
- rm -f */*.o
-
-radiochat: chat/chat_main.o
- gcc -Wall -Wextra -o radiochat -pthread -Llibs/. chat/chat_main.o -lwiringPi -lax5043
-
-chat/chat_main.o: chat/chat_main.c
-chat/chat_main.o: spi/ax5043spi_p.h
-chat/chat_main.o: ax5043/ax5043mode_p.h
-chat/chat_main.o: ax5043/ax5043rx_p.h
-chat/chat_main.o: ax5043/ax5043tx_p.h
-chat/chat_main.o: generated/configtx.h
- cd chat; gcc -Wall -Wextra -c chat_main.c; cd ..
-
diff --git a/chat/ax5043/ax5043init_p.h b/chat/ax5043/ax5043init_p.h
deleted file mode 100644
index 314930a6..00000000
--- a/chat/ax5043/ax5043init_p.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*! \file ax5043init_p.h
- \brief Provides an interface to initialze the AX5043 transceiver.
- */
-
-#ifndef AX5043INIT_P_H_
-#define AX5043INIT_P_H_
-
-#include
-
-#define AXRADIO_ERR_NOERROR 0x00 //!< Operation successful
-#define AXRADIO_ERR_NOTSUPPORTED 0x01 //!< Operation not supported
-#define AXRADIO_ERR_BUSY 0x02 //!< Transceiver busy
-#define AXRADIO_ERR_TIMEOUT 0x03 //!< Operation timed out
-#define AXRADIO_ERR_INVALID 0x04 //!< Invalid parameter
-#define AXRADIO_ERR_NOCHIP 0x05 //!< Transceiver not found
-#define AXRADIO_ERR_RANGING 0x06 //!< Frequency could not be ranged
-#define AXRADIO_ERR_LOCKLOST 0x07 //!< Lost PLL lock
-#define AXRADIO_ERR_RETRANSMISSION 0x08 //!< Retrasnmitted packet
-#define AXRADIO_ERR_RESYNC 0x09 //!< Restarts synchronization
-#define AXRADIO_ERR_RESYNCTIMEOUT 0x0a //!< Synchronization timed out
-#define AXRADIO_ERR_RECEIVESTART 0x0b //!< Receiver restarted
-
-//! Structure containing a four byte X.25 address
-struct axradio_address {
- uint8_t addr[4]; //!< Four byte X.25 address
-};
-
-/*! \fn uint8_t axradio_init(void)
- \brief Initialize the AX5043 radio transceiver.
- \return AXRADIO_ERR_NOERROR on success, otherwise a value indicating an error.
- \sa AXRADIO_ERR_NOERROR
-*/
-uint8_t axradio_init(void);
-
-#endif /* AX5043INIT_P_H_ */
diff --git a/chat/ax5043/ax5043mode_p.h b/chat/ax5043/ax5043mode_p.h
deleted file mode 100644
index 01833f29..00000000
--- a/chat/ax5043/ax5043mode_p.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*! \file ax5043mode_p.h
- \brief Provides an interface to change the transceiver mode.
-*/
-
-#ifndef AX5043MODE_P_H_
-#define AX5043MODE_P_H_
-
-#include
-
-/*! \fn uint8_t mode_tx()
- \brief Switch the tranceiver into transmit mode.
- \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
- \sa AXRADIO_ERR_NOERROR
-*/
-uint8_t mode_tx(void);
-
-/*! \fn uint8_t mode_rx()
- \brief Switch the tranceiver into receive mode.
-
- The receive buffer may contain garbage and reading from the buffer
- will obtain and discard that garbage.
- \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
- \sa AXRADIO_ERR_NOERROR
-*/
-uint8_t mode_rx(void);
-
-#endif /* AX5043MODE_P_H_ */
diff --git a/chat/ax5043/ax5043rx_p.h b/chat/ax5043/ax5043rx_p.h
deleted file mode 100644
index 1320873e..00000000
--- a/chat/ax5043/ax5043rx_p.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*! \file ax5043rx_p.h
- \brief Provides an interface to receive packets using the digital transceiver.
-*/
-#ifndef AX5043RX_P_H_
-#define AX5043RX_P_H_
-
-#include
-
-/*! \fn uint8_t receive_packet(void)
- \brief Receive a packet from the digital transceiver receive buffer.
- \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
- \sa AXRADIO_ERR_NOERROR
-*/
-uint8_t receive_packet(void);
-
-#endif /* AX5043RX_P_H_ */
diff --git a/chat/ax5043/ax5043tx_p.h b/chat/ax5043/ax5043tx_p.h
deleted file mode 100644
index 3d3209f6..00000000
--- a/chat/ax5043/ax5043tx_p.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*! \file ax5043tx_p.h
- \brief Provides an interface to transmit packets using the digital transceiver.
-*/
-#ifndef AX5043TX_P_H_
-#define AX5043TX_P_H_
-
-#include
-
-#include "ax5043init_p.h"
-
-/*! \fn uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen)
- \brief Transmit a packet using the digital transceiver
- \param addr The address of the desired destiantion radio, if used.
- \param pkt The byte data to be transmitted.
- \param pktlen The number of bytes in pkt to be transmitted.
- \return AXRADIO_ERROR_NOERROR on success, otherwise a value indicating an error.
- \sa AXRADIO_ERR_NOERROR
-*/
-uint8_t transmit_packet(const struct axradio_address *addr, const uint8_t *pkt, uint16_t pktlen);
-
-#endif /* AX5043TX_P_H_ */
diff --git a/chat/chat/chat_main.c b/chat/chat_main.c
similarity index 82%
rename from chat/chat/chat_main.c
rename to chat/chat_main.c
index 50d38949..52016210 100644
--- a/chat/chat/chat_main.c
+++ b/chat/chat_main.c
@@ -1,29 +1,40 @@
// Copyright (c) 2018 Brandenburg Tech, LLC
-// All rights reserved.
-
-#include
-#include
-#include
-#include
-#include
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include
+#include
+#include
+#include
+#include
#include
#include
+#include
+#include
+#include
+#include
#include
+#include
#include
-#include "../spi/ax5043spi_p.h"
-#include "../ax5043/ax5043mode_p.h"
-#include "../ax5043/ax5043rx_p.h"
-#include "../ax5043/ax5043tx_p.h"
-#include "../generated/configtx.h"
-
#define MAX_MESSAGE_LENGTH (197)
extern uint8_t axradio_rxbuffer[];
void *receive(void *arg);
void *transmit(void *arg);
-int get_message(uint8_t *buffer, int avail);
+size_t get_message(uint8_t *buffer, size_t avail);
enum RadioState {UnknownState, RxState, TxState};
enum RadioState currentState = UnknownState;
@@ -138,7 +149,7 @@ void *receive(void *arg) {
currentReceiveState = WaitingForPacketCounter2;
break;
case WaitingForPacketCounter2:
- packetNumber |= (int)axradio_rxbuffer[counter++] << 8;
+ packetNumber |= (uint16_t)(axradio_rxbuffer[counter++] << 8);
printf("Pkt Num: %d ", (int)packetNumber);
currentReceiveState = WaitingForMessageLength1;
break;
@@ -147,7 +158,7 @@ void *receive(void *arg) {
currentReceiveState = WaitingForMessageLength2;
break;
case WaitingForMessageLength2:
- messageLength |= (int)axradio_rxbuffer[counter++] << 8;
+ messageLength |= (uint16_t)(axradio_rxbuffer[counter++] << 8);
printf("Msg Len: %d ", (int)messageLength);
currentReceiveState = WaitingForMessage;
break;
@@ -166,7 +177,7 @@ void *receive(void *arg) {
currentReceiveState = WaitingForChecksum2;
break;
case WaitingForChecksum2:
- checksum |= (int)axradio_rxbuffer[counter++] << 8;
+ checksum |= (uint16_t)(axradio_rxbuffer[counter++] << 8);
printf("(Chksum: %d)\n", (int)checksum);
currentReceiveState = WaitingForNewPacket;
break;
@@ -209,7 +220,7 @@ void *transmit(void *arg) {
++pkt_counter;
// Calculate the number of reserved bytes at the beginning of the packet
- int reserved_space = 0;
+ size_t reserved_space = 0;
// if transmitting a packet counter, reserve two bytes
if (framing_insert_counter) {
@@ -221,7 +232,7 @@ void *transmit(void *arg) {
reserved_space += 2;
// get a message to transmit.
- int msg_length = get_message(&packet[reserved_space], (MAX_MESSAGE_LENGTH + 1) - reserved_space);
+ size_t msg_length = get_message(&packet[reserved_space], (MAX_MESSAGE_LENGTH + 1) - reserved_space);
// if message consists only of a newline, terminate
if (msg_length <= 1) {
@@ -229,8 +240,8 @@ void *transmit(void *arg) {
}
if (framing_insert_counter) {
- packet[framing_counter_pos] = pkt_counter & 0xFF ;
- packet[framing_counter_pos+1] = (pkt_counter>>8) & 0xFF;
+ packet[framing_counter_pos] = (uint8_t)(pkt_counter & 0xFF);
+ packet[framing_counter_pos+1] = (uint8_t)((pkt_counter>>8) & 0xFF);
// include the message length
packet[framing_counter_pos+2] = msg_length & 0xFF ;
@@ -260,7 +271,7 @@ void *transmit(void *arg) {
//printf("INFO: Sending another packet...\n");
//printf("DEBUG: msg_length = %d\n", msg_length);
//printf("DEBUG: reserved_space = %d\n", reserved_space);
- retVal = transmit_packet(&remoteaddr_tx, packet, msg_length + reserved_space);
+ retVal = transmit_packet(&remoteaddr_tx, packet, (uint16_t)(msg_length + reserved_space));
if (retVal != AXRADIO_ERR_NOERROR) {
fprintf(stderr, "ERROR: Unable to transmit a packet\n");
exit(EXIT_FAILURE);
@@ -278,17 +289,17 @@ void *transmit(void *arg) {
return NULL;
}
-int get_message(uint8_t *buffer, int avail) {
+size_t get_message(uint8_t *buffer, size_t avail) {
static int instructionsPrinted = 0;
// obtain a line of text. We state the message is limited to avail-2 to
// leave space for the newline and the null terminator
if (!instructionsPrinted) {
- printf("Please enter your message, up to %d characters\n (empty message to terminate the program):\n", avail-2);
+ printf("Please enter your message, up to %d characters\n (empty message to terminate the program):\n", (int)(avail-2));
instructionsPrinted = 1;
}
- fgets((char *)buffer, avail, stdin);
+ fgets((char *)buffer, (int)avail, stdin);
// check for end-of-file (for redirecting stdin)
if (feof(stdin)) {
diff --git a/chat/generated/configtx.h b/chat/generated/configtx.h
deleted file mode 100644
index 9fdae29d..00000000
--- a/chat/generated/configtx.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Warning: This file is automatically generated by AX-RadioLAB.
-Manual changes are overwritten! */
-
-#include "../ax5043/ax5043init_p.h"
-
-//#define USE_LCD
-//#define USE_DBGLINK
-#define USE_COM0
-//#define DEBUGMSG
-//#define MCU_SLEEP
-#define WTIMER0_CLKSRC CLKSRC_LPOSC
-#define WTIMER0_PRESCALER 0x01
-#define WTIMER0_PERIOD 0x0280
-#define RADIO_MODE_TX AXRADIO_MODE_ASYNC_TRANSMIT
-extern const struct axradio_address remoteaddr_tx;
-extern const struct axradio_address_mask localaddr_tx;
-extern const uint8_t demo_packet[6];
-extern const uint8_t framing_insert_counter;
-extern const uint8_t framing_counter_pos;
-
-extern const uint16_t lpxosc_settlingtime;
diff --git a/chat/libs/libax5043.a b/chat/libs/libax5043.a
deleted file mode 100644
index 7d4a8a56..00000000
Binary files a/chat/libs/libax5043.a and /dev/null differ
diff --git a/init/.cproject b/init/.cproject
new file mode 100644
index 00000000..98cdbec4
--- /dev/null
+++ b/init/.cproject
@@ -0,0 +1,123 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/init/.gitignore b/init/.gitignore
new file mode 100644
index 00000000..3df573fe
--- /dev/null
+++ b/init/.gitignore
@@ -0,0 +1 @@
+/Debug/
diff --git a/init/.project b/init/.project
new file mode 100644
index 00000000..2779fd51
--- /dev/null
+++ b/init/.project
@@ -0,0 +1,26 @@
+
+
+ init
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/init/.settings/language.settings.xml b/init/.settings/language.settings.xml
new file mode 100644
index 00000000..e20d703e
--- /dev/null
+++ b/init/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/init/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/init/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 00000000..33833f65
--- /dev/null
+++ b/init/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/CPATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/CPATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/append=true
+environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/appendContributed=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/append=true
+environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.37615557/appendContributed=true
diff --git a/init/init_main.c b/init/init_main.c
new file mode 100644
index 00000000..6047c926
--- /dev/null
+++ b/init/init_main.c
@@ -0,0 +1,81 @@
+// Copyright (c) 2018 Brandenburg Tech, LLC
+// All right reserved.
+//
+// THIS SOFTWARE IS PROVIDED BY BRANDENBURG TECH, LLC AND CONTRIBUTORS
+// ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BRANDENBURT TECH, LLC
+// AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Copyright (c) 2007,2008,2009,2010,2011,2012,2013, 2014 AXSEM AG
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// 1.Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2.Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 3.Neither the name of AXSEM AG, Duebendorf nor the
+// names of its contributors may be used to endorse or promote products
+// derived from this software without specific prior written permission.
+// 4.All advertising materials mentioning features or use of this software
+// must display the following acknowledgement:
+// This product includes software developed by AXSEM AG and its contributors.
+// 5.The usage of this source code is only granted for operation with AX5043
+// and AX8052F143. Porting to other radio or communication devices is
+// strictly prohibited.
+//
+// THIS SOFTWARE IS PROVIDED BY AXSEM AG AND CONTRIBUTORS ``AS IS'' AND ANY
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL AXSEM AG AND CONTRIBUTORS BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "spi/ax5043spi.h"
+
+int main(void)
+{
+ uint8_t retVal;
+
+ setSpiChannel(SPI_CHANNEL);
+ setSpiSpeed(SPI_SPEED);
+ initializeSpi();
+
+ retVal = axradio_init();
+ if (retVal == AXRADIO_ERR_NOCHIP) {
+ fprintf(stderr, "ERROR: No AX5043 RF chip found\n");
+ exit(EXIT_FAILURE);
+ }
+ if (retVal != AXRADIO_ERR_NOERROR) {
+ fprintf(stderr, "ERROR: Unable to initialize AX5043\n");
+ exit(EXIT_FAILURE);
+ }
+
+ printf("INFO: Found and initialized AX5043\n");
+
+
+ return 0;
+}
+
diff --git a/libs/libmf/buildiar/Makefile b/libs/libmf/buildiar/Makefile
new file mode 100644
index 00000000..94273dd9
--- /dev/null
+++ b/libs/libmf/buildiar/Makefile
@@ -0,0 +1,539 @@
+TARGET_MODEL := --calling_convention=data_overlay --data_model=small --place_constants=code
+TARGET_DEFINES := -D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=0
+LIBSUFFIX :=
+#TARGET_INSTDIR := C:/EDA/IAR\ Systems/Embedded\ Workbench\ 6.0\ Kickstart/8051
+#TARGET_INSTDIR := C:/EDA/IAR\ Systems/Embedded\ Workbench\ 6.5/8051
+#TARGET_INSTDIR := C:/Program\ Files\ \(x86\)/IAR\ Systems/Embedded\ Workbench\ 6.5/8051
+TARGET_INSTDIR := C:/Program\ Files\ \(x86\)/IAR\ Systems/Embedded\ Workbench\ 7.3/8051
+TARGET_ASM := $(TARGET_INSTDIR)/bin/a8051.exe
+TARGET_LD := $(TARGET_INSTDIR)/bin/xlink.exe
+TARGET_CC := $(TARGET_INSTDIR)/bin/icc8051.exe
+TARGET_AR := $(TARGET_INSTDIR)/bin/xar.exe
+TARGET_ASMFLAGS := -v0 -D__CORE__=1 -D__CODE_MODEL__=1 -D__NUMBER_OF_DPTRS__=1 $(TARGET_DEFINES) -s+ -M"<>" -r -w+ -I$(TARGET_INSTDIR)/src/lib
+TARGET_LNKFLAGS := -D_NR_OF_BANKS=0 -D_CODEBANK_END=0 -D_CODEBANK_START=0 -I$(TARGET_INSTDIR)/config -e_small_write=_formatted_write -e_medium_read=_formatted_read -Faomf8051 -Y0 -I$(TARGET_INSTDIR)/lib -f $(TARGET_INSTDIR)/config/devices/_generic/lnk51ew_plain.xcl -D?DPMASK=0x01 -D_NR_OF_VIRTUAL_REGISTERS=8 -D?DPS=0x85 -D?PBANK=0xD9 -D?DPL1=0x84 -D?DPH1=0x85 -s __program_start $(TARGET_INSTDIR)/LIB/CLIB/cl-pli-nsdc-2e16inc.r51 -D_IDATA_STACK_SIZE=0x40 -D_EXTENDED_STACK_START=0x00 -D_EXTENDED_STACK_SIZE=0x00 -D_PDATA_STACK_SIZE=0x80 -D_XDATA_STACK_SIZE=0xEFF -D_XDATA_HEAP_SIZE=0xFF -D_FAR_HEAP_SIZE=0xFFF -D_HUGE_HEAP_SIZE=0xFFF -D_FAR22_HEAP_SIZE=0xFFF
+TARGET_CFLAGS := -e --no_unroll --no_inline --no_tbaa --debug --core=plain --dptr=16,1,separate,xor $(TARGET_MODEL) --code_model=near --nr_virtual_regs 8 -Om --library_module --diag_suppress=Pa050 -I../source
+
+LIBMFOBJ := lcdinit.r51 lcdsetpos.r51 lcdwrstr.r51 lcdclear.r51 lcdclrdisp.r51 lcdwru16.r51 lcdwru32.r51 \
+ lcdwrhexu16.r51 lcdwrhexu32.r51 lcduwrnum16.r51 lcduwrnum32.r51 lcduwrhex16.r51 lcduwrhex32.r51 \
+ dbglink.r51 dbglnktxbuf.r51 dbglnkrxbuf.r51 dbglnktx.r51 dbglnkrx.r51 dbglnkwrhexu16.r51 dbglnkwrhexu32.r51 dbglnkwrstr.r51 \
+ dbglnkwru16.r51 dbglnkwru32.r51 dbglnkwrnum16.r51 dbglnkwrnum32.r51 dbglnkwrhex16.r51 dbglnkwrhex32.r51 \
+ crc8ccitt.r51 crc8onewire.r51 crc8tccitt.r51 crc8tccittmsb.r51 crc8tonewire.r51 crc8tonewiremsb.r51 \
+ crc8ccittb.r51 crc8ccittmsbb.r51 crc8onewireb.r51 crc8onewiremsbb.r51 \
+ crc8ccitttable.r51 crc8onewiretable.r51 crc8ccittmsbtable.r51 crc8onewiremsbtable.r51 \
+ crcccitt.r51 crcccittmsb.r51 crc16ansi.r51 crc16ansimsb.r51 crc16dnp.r51 crc16dnpmsb.r51 crc32ansi.r51 crc32ansimsb.r51 \
+ crcccittb.r51 crcccittmsbb.r51 crc16ansib.r51 crc16ansimsbb.r51 crc16dnpb.r51 crc16dnpmsbb.r51 crc32ansib.r51 crc32ansimsbb.r51 \
+ crcccitttable.r51 crc16table.r51 crc16dnptable.r51 crcccittmsbtable.r51 crc16msbtable.r51 \
+ crc16dnpmsbtable.r51 crc32table.r51 crc32msbtable.r51 pn9.r51 pn9table.r51 pn9bit.r51 pn9bits.r51 pn9byte.r51 pn9buf.r51 \
+ pn15advtable.r51 pn15outtable.r51 pn15adv.r51 pn15out.r51 \
+ rev8.r51 hweight8.r51 hweight16.r51 hweight32.r51 signext12.r51 signext16.r51 signext20.r51 signext24.r51 \
+ chksgnlim16.r51 sgnlim16.r51 chksgnlim32.r51 sgnlim32.r51 grayenc8.r51 graydec8.r51 fmemsetiar.r51 fmemcpyiar.r51 \
+ delay.r51 random.r51 sleep.r51 sleepcont.r51 deepsleep.r51 standby.r51 resetcpu.r51 \
+ flashunlock.r51 flashlock.r51 flashwait.r51 flashpgerase.r51 flashwrite.r51 flashread.r51 flashcal.r51 flashcsec.r51 \
+ uarttimer0.r51 uarttimer1.r51 uarttimer2.r51 uart0init.r51 uart1init.r51 uart0stop.r51 uart1stop.r51 \
+ uart0txbuf.r51 uart1txbuf.r51 uart0rxbuf.r51 uart1rxbuf.r51 \
+ uart0tx.r51 uart1tx.r51 uart0rx.r51 uart1rx.r51 uart0wrhexu16.r51 uart1wrhexu16.r51 uart0wrhexu32.r51 uart1wrhexu32.r51 \
+ uart0wrstr.r51 uart1wrstr.r51 uart0wru16.r51 uart1wru16.r51 uart0wru32.r51 uart1wru32.r51 \
+ uart0wrnum16.r51 uart0wrnum32.r51 uart0wrhex16.r51 uart0wrhex32.r51 \
+ uart1wrnum16.r51 uart1wrnum32.r51 uart1wrhex16.r51 uart1wrhex32.r51 \
+ adctemp.r51 adccal.r51 adccalg.r51 adccalt.r51 adcuncal.r51 adcseoffs00.r51 adcseoffs01.r51 adcseoffs10.r51 \
+ bch3121dec.r51 bch3121decp.r51 bch3121enc.r51 bch3121encp.r51 bch3121stab.r51 bch3121syn.r51 \
+ wrnum16.r51 wrnum32.r51 offxosc.r51 offlpxosc.r51 setuplpxosc.r51 setupxosc.r51 setupcal.r51 \
+ wtimer.r51 wtrem.r51 wtcbadd.r51 wtcbrem.r51 wt0setcfg.r51 wt1setcfg.r51 wtstdby.r51 \
+ wt0adda.r51 wt1adda.r51 wt0addr.r51 wt1addr.r51 wt0curt.r51 wt1curt.r51 wt0rem.r51 wt1rem.r51 wt01rem.r51 \
+ radiord16.r51 radiord24.r51 radiord32.r51 radiowr16.r51 radiowr24.r51 radiowr32.r51 radiodswakecore.r51 \
+ ax5031comminit.r51 ax5031commslpexit.r51 ax5031reset.r51 ax5031deepsleep.r51 ax5031rclkena.r51 ax5031rclkdis.r51 \
+ ax5031rdfifo.r51 ax5031wrfifo.r51 \
+ ax5042comminit.r51 ax5042commslpexit.r51 ax5042reset.r51 ax5042deepsleep.r51 ax5042rclkena.r51 ax5042rclkdis.r51 \
+ ax5042rdfifo.r51 ax5042wrfifo.r51 \
+ ax5043comminit.r51 ax5043commslpexit.r51 ax5043reset.r51 ax5043deepsleep.r51 ax5043rclkena.r51 ax5043rclkdis.r51 \
+ ax5043rdfifo.r51 ax5043wrfifo.r51 \
+ ax5051comminit.r51 ax5051commslpexit.r51 ax5051reset.r51 ax5051deepsleep.r51 ax5051rclkena.r51 ax5051rclkdis.r51 \
+ ax5051rdfifo.r51 ax5051wrfifo.r51 \
+ ax8052regs.r51 radioregs.r51 CStartup.r51 getpspiar.r51 getxspiar.r51
+
+BINARIES :=
+LIBBINARIES := libmf.r51 libmflarge.r51 \
+ libmf-pli-nlpc-1e16x01.r51 libmf-pli-nlpd-1e16x01.r51 libmf-pli-nlxc-1e16x01.r51 libmf-pli-nlxd-1e16x01.r51 \
+ libmf-pli-nsdc-1e16x01.r51 libmf-pli-nsdd-1e16x01.r51 libmf-pli-nsic-1e16x01.r51 libmf-pli-nsid-1e16x01.r51 libmf-pli-nsoc-1e16x01.r51 libmf-pli-nsod-1e16x01.r51 \
+ libmf-pli-ntdc-1e16x01.r51 libmf-pli-ntdd-1e16x01.r51 libmf-pli-ntic-1e16x01.r51 libmf-pli-ntid-1e16x01.r51 libmf-pli-ntoc-1e16x01.r51 libmf-pli-ntod-1e16x01.r51
+
+ifeq ($(LIBSUFFIX),)
+all: $(LIBBINARIES) $(BINARIES) $(patsubst %.omf,%.cdb,$(BINARIES)) $(patsubst %.omf,%.ihx,$(BINARIES))
+else
+all: libmf$(LIBSUFFIX).r51
+endif
+
+clean:
+ rm -rf *.lnk radioregs.s51 $(LIBBINARIES) $(patsubst %.r51,%,$(LIBBINARIES)) mflibbiniar.tar.gz
+
+tar: mflibbiniar.tar.gz
+
+mflibbiniar.tar.gz: $(LIBBINARIES)
+ tar -c -v -z -f $@ $(LIBBINARIES)
+
+ifeq ($(LIBSUFFIX),)
+.PHONY: libmflarge.r51
+.PHONY: libmf-pli-nlpc-1e16x01.r51
+.PHONY: libmf-pli-nlpd-1e16x01.r51
+.PHONY: libmf-pli-nlxc-1e16x01.r51
+.PHONY: libmf-pli-nlxd-1e16x01.r51
+.PHONY: libmf-pli-nsdc-1e16x01.r51
+.PHONY: libmf-pli-nsdd-1e16x01.r51
+.PHONY: libmf-pli-nsic-1e16x01.r51
+.PHONY: libmf-pli-nsid-1e16x01.r51
+.PHONY: libmf-pli-nsoc-1e16x01.r51
+.PHONY: libmf-pli-nsod-1e16x01.r51
+.PHONY: libmf-pli-ntdc-1e16x01.r51
+.PHONY: libmf-pli-ntdd-1e16x01.r51
+.PHONY: libmf-pli-ntic-1e16x01.r51
+.PHONY: libmf-pli-ntid-1e16x01.r51
+.PHONY: libmf-pli-ntoc-1e16x01.r51
+.PHONY: libmf-pli-ntod-1e16x01.r51
+
+libmflarge.r51:
+ make TARGET_MODEL="--calling_convention=pdata_reentrant --data_model=large --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=2 -D__CALLING_CONVENTION__=3" LIBSUFFIX=large
+
+# name format: -pli-n(1)(2)(3)-1e16x01
+# page 152
+# (1): data model
+# t - --data_model=tiny -D__DATA_MODEL__=0
+# s - --data_model=small -D__DATA_MODEL__=1
+# l - --data_model=large -D__DATA_MODEL__=2
+# g - --data_model=generic -D__DATA_MODEL__=3
+# j - --data_model=far_generic -D__DATA_MODEL__=5
+# f - --data_model=far -D__DATA_MODEL__=4
+# (2): calling convention
+# d - --calling_convention=data_overlay -D__CALLING_CONVENTION__=0
+# o - --calling_convention=idata_overlay -D__CALLING_CONVENTION__=1
+# i - --calling_convention=idata_reentrant -D__CALLING_CONVENTION__=2
+# p - --calling_convention=pdata_reentrant -D__CALLING_CONVENTION__=3
+# x - --calling_convention=xdata_reentrant -D__CALLING_CONVENTION__=4
+# e - --calling_convention=ext_stack_reentrant -D__CALLING_CONVENTION__=5
+# (3): constant location
+# c - --place_constants=code
+# d - --place_constants=data
+
+libmf-pli-nlpc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=large --calling_convention=pdata_reentrant --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=2 -D__CALLING_CONVENTION__=3" LIBSUFFIX=-pli-nlpc-1e16x01
+
+libmf-pli-nlpd-1e16x01.r51:
+ make TARGET_MODEL="--data_model=large --calling_convention=pdata_reentrant --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=2 -D__CALLING_CONVENTION__=3" LIBSUFFIX=-pli-nlpd-1e16x01
+
+libmf-pli-nlxc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=large --calling_convention=xdata_reentrant --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=2 -D__CALLING_CONVENTION__=4" LIBSUFFIX=-pli-nlxc-1e16x01
+
+libmf-pli-nlxd-1e16x01.r51:
+ make TARGET_MODEL="--data_model=large --calling_convention=xdata_reentrant --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=2 -D__CALLING_CONVENTION__=4" LIBSUFFIX=-pli-nlxd-1e16x01
+
+libmf-pli-nsdc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=data_overlay --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=0" LIBSUFFIX=-pli-nsdc-1e16x01
+
+libmf-pli-nsdd-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=data_overlay --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=0" LIBSUFFIX=-pli-nsdd-1e16x01
+
+libmf-pli-nsic-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=idata_reentrant --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=2" LIBSUFFIX=-pli-nsic-1e16x01
+
+libmf-pli-nsid-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=idata_reentrant --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=2" LIBSUFFIX=-pli-nsid-1e16x01
+
+libmf-pli-nsoc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=idata_overlay --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=1" LIBSUFFIX=-pli-nsoc-1e16x01
+
+libmf-pli-nsod-1e16x01.r51:
+ make TARGET_MODEL="--data_model=small --calling_convention=idata_overlay --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=1 -D__CALLING_CONVENTION__=1" LIBSUFFIX=-pli-nsod-1e16x01
+
+libmf-pli-ntdc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=data_overlay --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=0" LIBSUFFIX=-pli-ntdc-1e16x01
+
+libmf-pli-ntdd-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=data_overlay --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=0" LIBSUFFIX=-pli-ntdd-1e16x01
+
+libmf-pli-ntic-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=idata_reentrant --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=2" LIBSUFFIX=-pli-ntic-1e16x01
+
+libmf-pli-ntid-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=idata_reentrant --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=2" LIBSUFFIX=-pli-ntid-1e16x01
+
+libmf-pli-ntoc-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=idata_overlay --place_constants=code" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=1" LIBSUFFIX=-pli-ntoc-1e16x01
+
+libmf-pli-ntod-1e16x01.r51:
+ make TARGET_MODEL="--data_model=tiny --calling_convention=idata_overlay --place_constants=data" TARGET_DEFINES="-D__DATA_MODEL__=0 -D__CALLING_CONVENTION__=1" LIBSUFFIX=-pli-ntod-1e16x01
+
+endif
+
+.PRECIOUS: radioregs.s51
+
+radioregs.s51: ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h
+ ./genrregs.pl $^ > $@
+
+libmf$(LIBSUFFIX):
+ [ ! -d $@ ] && mkdir -p $@
+
+.PRECIOUS: %.r51 %.omf %.ihx %.cdb
+
+%.r51: ../%.c
+ $(TARGET_CC) $(TARGET_CFLAGS) -o $@ -lC `basename $@ .r51`.lst $<
+
+%.omf %.ihx %.cdb: %.r51 libmf$(LIBSUFFIX).r51
+ (libdir=`pwd`; dn=`dirname $<`/; fn=`basename $< .r51`; cd $${dn}; $(TARGET_LD) -V $(TARGET_LNKFLAGS) -L$${libdir} -llibmf$(LIBSUFFIX) $${fn}.r51; x=$$?; mv $${fn} $${fn}.omf; exit $${x})
+
+libmf$(LIBSUFFIX)/%.r51: ../source/%.c | libmf$(LIBSUFFIX)
+ $(TARGET_CC) $(TARGET_CFLAGS) -o $@ -lC libmf$(LIBSUFFIX)/`basename $@ .r51`.lst $<
+
+libmf$(LIBSUFFIX)/%.r51: libmf$(LIBSUFFIX)/%.c | libmf$(LIBSUFFIX)
+ $(TARGET_CC) $(TARGET_CFLAGS) -o $@ -lC libmf$(LIBSUFFIX)/`basename $@ .r51`.lst $<
+
+libmf$(LIBSUFFIX)/%.r51: ../source/%.s51 | libmf$(LIBSUFFIX)
+ $(TARGET_ASM) $(TARGET_ASMFLAGS) -o $@ -l libmf$(LIBSUFFIX)/`basename $@ .r51`.lst -t8 $<
+
+libmf$(LIBSUFFIX)/%.r51: %.s51 | libmf$(LIBSUFFIX)
+ $(TARGET_ASM) $(TARGET_ASMFLAGS) -o $@ -l libmf$(LIBSUFFIX)/`basename $@ .r51`.lst -t8 $<
+
+libmf$(LIBSUFFIX)/%.s51: ../source/%.c | libmf$(LIBSUFFIX)
+ $(TARGET_CC) $(TARGET_CFLAGS) -o libmf$(LIBSUFFIX)/`basename $@ .s51`.r51 -lA $@ $<
+
+libmf$(LIBSUFFIX)/%.s51: libmf$(LIBSUFFIX)/%.c | libmf$(LIBSUFFIX)
+ $(TARGET_CC) $(TARGET_CFLAGS) -o libmf$(LIBSUFFIX)/`basename $@ .s51`.r51 -lA $@ $<
+
+libmf$(LIBSUFFIX).r51: $(patsubst %.r51,libmf$(LIBSUFFIX)/%.r51,$(LIBMFOBJ)) | libmf$(LIBSUFFIX)
+ $(TARGET_AR) -o $@ $(patsubst %.r51,libmf$(LIBSUFFIX)/%.r51,$(LIBMFOBJ))
+
+libmf$(LIBSUFFIX)/uarttimer0.c: ../source/uarttimer.c
+ (unifdef -DTIMER=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer1.c: ../source/uarttimer.c
+ (unifdef -DTIMER=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer2.c: ../source/uarttimer.c
+ (unifdef -DTIMER=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0init.c: ../source/uartinit.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0stop.c: ../source/uartstop.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1init.c: ../source/uartinit.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1stop.c: ../source/uartstop.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0%.c: ../source/io%.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1%.c: ../source/io%.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/dbglnk%.c: ../source/io%.c
+ (unifdef -DUART=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdu%.c: ../source/io%.c
+ (unifdef -DUART=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5031%.c: ../source/radio%.c
+ (unifdef -DRADIO=5031 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5042%.c: ../source/radio%.c
+ (unifdef -DRADIO=5042 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5043%.c: ../source/radio%.c
+ (unifdef -DRADIO=5043 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5051%.c: ../source/radio%.c
+ (unifdef -DRADIO=5051 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccitt.c: ../source/crc8.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccittmsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewire.c: ../source/crc8.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewiremsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansi.c: ../source/crc16.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnp.c: ../source/crc16.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccitt.c: ../source/crc16.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansi.c: ../source/crc32.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsb.c: ../source/crc32msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittmsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewireb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewiremsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansib.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=4 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=5 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansib.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsbb.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdinit.r51: ../source/lcdinit.c ../source/libmflcd.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdsetpos.r51: ../source/lcdsetpos.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrstr.r51: ../source/lcdwrstr.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclear.r51: ../source/lcdclear.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclrdisp.r51: ../source/lcdclrdisp.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru16.r51: ../source/lcdwru16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru32.r51: ../source/lcdwru32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu16.r51: ../source/lcdwrhexu16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu32.r51: ../source/lcdwrhexu32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum16.r51: libmf$(LIBSUFFIX)/lcduwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum32.r51: libmf$(LIBSUFFIX)/lcduwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex16.r51: libmf$(LIBSUFFIX)/lcduwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex32.r51: libmf$(LIBSUFFIX)/lcduwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/delay.r51: ../source/delay.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/random.r51: ../source/random.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitt.r51: ../source/crc8ccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewire.r51: ../source/crc8onewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitttable.r51: ../source/crc8ccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiretable.r51: ../source/crc8onewiretable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbtable.r51: ../source/crc8ccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbtable.r51: ../source/crc8onewiremsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitttable.r51: ../source/crcccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16table.r51: ../source/crc16table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnptable.r51: ../source/crc16dnptable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbtable.r51: ../source/crcccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16msbtable.r51: ../source/crc16msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbtable.r51: ../source/crc16dnpmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32table.r51: ../source/crc32table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32msbtable.r51: ../source/crc32msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccitt.r51: libmf$(LIBSUFFIX)/crc8tccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccittmsb.r51: libmf$(LIBSUFFIX)/crc8tccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewire.r51: libmf$(LIBSUFFIX)/crc8tonewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewiremsb.r51: libmf$(LIBSUFFIX)/crc8tonewiremsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansi.r51: libmf$(LIBSUFFIX)/crc16ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsb.r51: libmf$(LIBSUFFIX)/crc16ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnp.r51: libmf$(LIBSUFFIX)/crc16dnp.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsb.r51: libmf$(LIBSUFFIX)/crc16dnpmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitt.r51: libmf$(LIBSUFFIX)/crcccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsb.r51: libmf$(LIBSUFFIX)/crcccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansi.r51: libmf$(LIBSUFFIX)/crc32ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsb.r51: libmf$(LIBSUFFIX)/crc32ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittb.r51: libmf$(LIBSUFFIX)/crc8ccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbb.r51: libmf$(LIBSUFFIX)/crc8ccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewireb.r51: libmf$(LIBSUFFIX)/crc8onewireb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbb.r51: libmf$(LIBSUFFIX)/crc8onewiremsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansib.r51: libmf$(LIBSUFFIX)/crc16ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsbb.r51: libmf$(LIBSUFFIX)/crc16ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpb.r51: libmf$(LIBSUFFIX)/crc16dnpb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbb.r51: libmf$(LIBSUFFIX)/crc16dnpmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittb.r51: libmf$(LIBSUFFIX)/crcccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbb.r51: libmf$(LIBSUFFIX)/crcccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansib.r51: libmf$(LIBSUFFIX)/crc32ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsbb.r51: libmf$(LIBSUFFIX)/crc32ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9.r51: ../source/pn9.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9table.r51: ../source/pn9table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bit.r51: ../source/pn9bit.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bits.r51: ../source/pn9bits.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9byte.r51: ../source/pn9byte.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9buf.r51: ../source/pn9buf.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15advtable.r51: ../source/pn15advtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15outtable.r51: ../source/pn15outtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15adv.r51: ../source/pn15adv.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15out.r51: ../source/pn15out.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/rev8.r51: ../source/rev8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight8.r51: ../source/hweight8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight16.r51: ../source/hweight16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight32.r51: ../source/hweight32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext12.r51: ../source/signext12.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext16.r51: ../source/signext16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext20.r51: ../source/signext20.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext24.r51: ../source/signext24.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim16.r51: ../source/chksgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim16.r51: ../source/sgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim32.r51: ../source/chksgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim32.r51: ../source/sgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/grayenc8.r51: ../source/grayenc8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/graydec8.r51: ../source/graydec8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemset.r51: ../source/fmemset.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemcpy.r51: ../source/fmemcpy.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemsetiar.r51: ../source/fmemsetiar.s51 | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemcpyiar.r51: ../source/fmemcpyiar.s51 | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/standby.r51: ../source/standby.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleep.r51: ../source/sleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleepcont.r51: ../source/sleepcont.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/deepsleep.r51: ../source/deepsleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/resetcpu.r51: ../source/resetcpu.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashunlock.r51: ../source/flashunlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashlock.r51: ../source/flashlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwait.r51: ../source/flashwait.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashpgerase.r51: ../source/flashpgerase.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwrite.r51: ../source/flashwrite.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashread.r51: ../source/flashread.c ../source/libmfflash.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcal.r51: ../source/flashcal.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcsec.r51: ../source/flashcsec.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0init.r51: libmf$(LIBSUFFIX)/uart0init.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1init.r51: libmf$(LIBSUFFIX)/uart1init.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0stop.r51: libmf$(LIBSUFFIX)/uart0stop.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1stop.r51: libmf$(LIBSUFFIX)/uart1stop.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0txbuf.r51: libmf$(LIBSUFFIX)/uart0txbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1txbuf.r51: libmf$(LIBSUFFIX)/uart1txbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rxbuf.r51: libmf$(LIBSUFFIX)/uart0rxbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rxbuf.r51: libmf$(LIBSUFFIX)/uart1rxbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0tx.r51: libmf$(LIBSUFFIX)/uart0tx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1tx.r51: libmf$(LIBSUFFIX)/uart1tx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rx.r51: libmf$(LIBSUFFIX)/uart0rx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rx.r51: libmf$(LIBSUFFIX)/uart1rx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu16.r51: libmf$(LIBSUFFIX)/uart0wrhexu16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu16.r51: libmf$(LIBSUFFIX)/uart1wrhexu16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu32.r51: libmf$(LIBSUFFIX)/uart0wrhexu32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu32.r51: libmf$(LIBSUFFIX)/uart1wrhexu32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrstr.r51: libmf$(LIBSUFFIX)/uart0wrstr.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrstr.r51: libmf$(LIBSUFFIX)/uart1wrstr.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru16.r51: libmf$(LIBSUFFIX)/uart0wru16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru16.r51: libmf$(LIBSUFFIX)/uart1wru16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru32.r51: libmf$(LIBSUFFIX)/uart0wru32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru32.r51: libmf$(LIBSUFFIX)/uart1wru32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum16.r51: libmf$(LIBSUFFIX)/uart0wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum16.r51: libmf$(LIBSUFFIX)/uart1wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum32.r51: libmf$(LIBSUFFIX)/uart0wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum32.r51: libmf$(LIBSUFFIX)/uart1wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex16.r51: libmf$(LIBSUFFIX)/uart0wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex16.r51: libmf$(LIBSUFFIX)/uart1wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex32.r51: libmf$(LIBSUFFIX)/uart0wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex32.r51: libmf$(LIBSUFFIX)/uart1wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglink.r51: ../source/dbglink.c ../source/libmfdbglink.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktxbuf.r51: libmf$(LIBSUFFIX)/dbglnktxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrxbuf.r51: libmf$(LIBSUFFIX)/dbglnkrxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktx.r51: libmf$(LIBSUFFIX)/dbglnktx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrx.r51: libmf$(LIBSUFFIX)/dbglnkrx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu16.r51: libmf$(LIBSUFFIX)/dbglnkwrhexu16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu32.r51: libmf$(LIBSUFFIX)/dbglnkwrhexu32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrstr.r51: libmf$(LIBSUFFIX)/dbglnkwrstr.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru16.r51: libmf$(LIBSUFFIX)/dbglnkwru16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru32.r51: libmf$(LIBSUFFIX)/dbglnkwru32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum16.r51: libmf$(LIBSUFFIX)/dbglnkwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum32.r51: libmf$(LIBSUFFIX)/dbglnkwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex16.r51: libmf$(LIBSUFFIX)/dbglnkwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex32.r51: libmf$(LIBSUFFIX)/dbglnkwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adctemp.r51: ../source/adctemp.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccal.r51: ../source/adccal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalg.r51: ../source/adccalg.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalt.r51: ../source/adccalt.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcuncal.r51: ../source/adcuncal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs00.r51: ../source/adcseoffs00.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs01.r51: ../source/adcseoffs01.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs10.r51: ../source/adcseoffs10.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121dec.r51: ../source/bch3121dec.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121decp.r51: ../source/bch3121decp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121enc.r51: ../source/bch3121enc.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121encp.r51: ../source/bch3121encp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121stab.r51: ../source/bch3121stab.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121syn.r51: ../source/bch3121syn.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum16.r51: ../source/wrnum16.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum32.r51: ../source/wrnum32.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offxosc.r51: ../source/offxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offlpxosc.r51: ../source/offlpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setuplpxosc.r51: ../source/setuplpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupxosc.r51: ../source/setupxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupcal.r51: ../source/setupcal.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtimer.r51: ../source/wtimer.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtrem.r51: ../source/wtrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbadd.r51: ../source/wtcbadd.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbrem.r51: ../source/wtcbrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0setcfg.r51: ../source/wt0setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1setcfg.r51: ../source/wt1setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtstdby.r51: ../source/wtstdby.c ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0adda.r51: ../source/wt0adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1adda.r51: ../source/wt1adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0addr.r51: ../source/wt0addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1addr.r51: ../source/wt1addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0curt.r51: ../source/wt0curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1curt.r51: ../source/wt1curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0rem.r51: ../source/wt0rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1rem.r51: ../source/wt1rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt01rem.r51: ../source/wt01rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord16.r51: ../source/radiord16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord24.r51: ../source/radiord24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord32.r51: ../source/radiord32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr16.r51: ../source/radiowr16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr24.r51: ../source/radiowr24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr32.r51: ../source/radiowr32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiodswakecore.r51: ../source/radiodswakecore.c ../source/radiodefs.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031comminit.r51: libmf$(LIBSUFFIX)/ax5031comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031commslpexit.r51: libmf$(LIBSUFFIX)/ax5031commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031reset.r51: libmf$(LIBSUFFIX)/ax5031reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031deepsleep.r51: libmf$(LIBSUFFIX)/ax5031deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkena.r51: ../source/ax5031rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkdis.r51: ../source/ax5031rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rdfifo.r51: libmf$(LIBSUFFIX)/ax5031rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031wrfifo.r51: libmf$(LIBSUFFIX)/ax5031wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031regs.r51: ../source/ax5031regs.c ../source/ax8052f131.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042comminit.r51: libmf$(LIBSUFFIX)/ax5042comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042commslpexit.r51: libmf$(LIBSUFFIX)/ax5042commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042reset.r51: libmf$(LIBSUFFIX)/ax5042reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042deepsleep.r51: libmf$(LIBSUFFIX)/ax5042deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkena.r51: ../source/ax5042rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkdis.r51: ../source/ax5042rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rdfifo.r51: libmf$(LIBSUFFIX)/ax5042rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042wrfifo.r51: libmf$(LIBSUFFIX)/ax5042wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042regs.r51: ../source/ax5042regs.c ../source/ax8052f142.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043comminit.r51: libmf$(LIBSUFFIX)/ax5043comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043commslpexit.r51: libmf$(LIBSUFFIX)/ax5043commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043reset.r51: libmf$(LIBSUFFIX)/ax5043reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043deepsleep.r51: libmf$(LIBSUFFIX)/ax5043deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkena.r51: ../source/ax5043rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkdis.r51: ../source/ax5043rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rdfifo.r51: libmf$(LIBSUFFIX)/ax5043rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043wrfifo.r51: libmf$(LIBSUFFIX)/ax5043wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043regs.r51: ../source/ax5043regs.c ../source/ax8052f143.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051comminit.r51: libmf$(LIBSUFFIX)/ax5051comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051commslpexit.r51: libmf$(LIBSUFFIX)/ax5051commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051reset.r51: libmf$(LIBSUFFIX)/ax5051reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051deepsleep.r51: libmf$(LIBSUFFIX)/ax5051deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkena.r51: ../source/ax5051rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkdis.r51: ../source/ax5051rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rdfifo.r51: libmf$(LIBSUFFIX)/ax5051rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051wrfifo.r51: libmf$(LIBSUFFIX)/ax5051wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051regs.r51: ../source/ax5051regs.c ../source/ax8052f151.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax8052regs.r51: ../source/ax8052regs.c ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radioregs.r51: radioregs.s51 | libmf$(LIBSUFFIX)
diff --git a/libs/libmf/buildiar/genrregs.pl b/libs/libmf/buildiar/genrregs.pl
new file mode 100644
index 00000000..97bb4d71
--- /dev/null
+++ b/libs/libmf/buildiar/genrregs.pl
@@ -0,0 +1,32 @@
+#!/usr/bin/perl
+
+my %regs;
+
+while (<>) {
+ next unless /^\s*SFRX\(\s*([A-Za-z0-9_]+)\s*,\s*(0x(?:[0-9A-Fa-f])+)\s*\)/;
+ my $name = $1;
+ my $addr = hex($2);
+ next if $addr < 0x4000 || $addr > 0x5fff;
+ #printf "%s 0x%x\n", $name, $addr;
+ ${$regs{$addr}}{$name} = 1;
+}
+
+# foreach $addr (sort keys(%regs)) {
+# printf "0x%x:\n", $addr;
+# foreach $name (sort keys(%{$regs{$addr}})) {
+# printf "%s 0x%x\n", $name, $addr;
+# }
+# }
+
+printf "\tMODULE radioregs\n\n", $addr;
+foreach $addr (sort keys(%regs)) {
+ foreach $name (sort keys(%{$regs{$addr}})) {
+ printf "\tPUBWEAK %s\n", $name;
+ }
+ printf "\n\tASEGN XDATA_AN:XDATA:ROOT,%05XH\n", $addr;
+ foreach $name (sort keys(%{$regs{$addr}})) {
+ printf "%s:\n", $name;
+ }
+ printf "\tDATA8\n\tDS 1\n\n";
+}
+print "\tEND\n\n";
diff --git a/libs/libmf/buildkeil/Makefile b/libs/libmf/buildkeil/Makefile
new file mode 100644
index 00000000..4a2753a4
--- /dev/null
+++ b/libs/libmf/buildkeil/Makefile
@@ -0,0 +1,433 @@
+TARGET_MODEL := SMALL
+LIBSUFFIX :=
+KEILPATH := C:/EDA/Keil
+C51INC := $(KEILPATH)/C51/INC
+C51LIB := $(KEILPATH)/C51/LIB
+C51FLAGS := OBJECTEXTEND $(TARGET_MODEL) DEBUG INCDIR "($(shell cygpath -w ../source))"
+A51OPT := "SET ($(TARGET_MODEL))" EP DEBUG
+L51OPT := "RAMSIZE(256) XDATA(0x0-0x1FFF) CODE(0x0-0xFFFF)"
+CPU_TYPE := 8052AH
+CPU_VENDOR := Intel
+CPU_XTAL := 0x01312D00
+
+LIBMFOBJ := lcdinit.obj lcdsetpos.obj lcdwrstr.obj lcdclear.obj lcdclrdisp.obj lcdwru16.obj lcdwru32.obj \
+ lcdwrhexu16.obj lcdwrhexu32.obj lcduwrnum16.obj lcduwrnum32.obj lcduwrhex16.obj lcduwrhex32.obj \
+ dbglink.obj dbglnktxbuf.obj dbglnkrxbuf.obj dbglnktx.obj dbglnkrx.obj dbglnkwrhexu16.obj dbglnkwrhexu32.obj dbglnkwrstr.obj \
+ dbglnkwru16.obj dbglnkwru32.obj dbglnkwrnum16.obj dbglnkwrnum32.obj dbglnkwrhex16.obj dbglnkwrhex32.obj \
+ crc8ccitt.obj crc8onewire.obj crc8tccitt.obj crc8tccittmsb.obj crc8tonewire.obj crc8tonewiremsb.obj \
+ crc8ccittb.obj crc8ccittmsbb.obj crc8onewireb.obj crc8onewiremsbb.obj \
+ crc8ccitttable.obj crc8onewiretable.obj crc8ccittmsbtable.obj crc8onewiremsbtable.obj \
+ crcccitt.obj crcccittmsb.obj crc16ansi.obj crc16ansimsb.obj crc16dnp.obj crc16dnpmsb.obj crc32ansi.obj crc32ansimsb.obj \
+ crcccittb.obj crcccittmsbb.obj crc16ansib.obj crc16ansimsbb.obj crc16dnpb.obj crc16dnpmsbb.obj crc32ansib.obj crc32ansimsbb.obj \
+ crcccitttable.obj crc16table.obj crc16dnptable.obj crcccittmsbtable.obj crc16msbtable.obj \
+ crc16dnpmsbtable.obj crc32table.obj crc32msbtable.obj pn9.obj pn9table.obj pn9bit.obj pn9bits.obj pn9byte.obj pn9buf.obj \
+ pn15advtable.obj pn15outtable.obj pn15adv.obj pn15out.obj \
+ rev8.obj hweight8.obj hweight16.obj hweight32.obj signext12.obj signext16.obj signext20.obj signext24.obj \
+ chksgnlim16.obj sgnlim16.obj chksgnlim32.obj sgnlim32.obj grayenc8.obj graydec8.obj fmemset.obj fmemcpy.obj \
+ delay.obj random.obj sleep.obj sleepcont.obj deepsleep.obj standby.obj resetcpu.obj \
+ flashunlock.obj flashlock.obj flashwait.obj flashpgerase.obj flashwrite.obj flashread.obj flashcal.obj flashcsec.obj \
+ uarttimer0.obj uarttimer1.obj uarttimer2.obj uart0init.obj uart1init.obj uart0stop.obj uart1stop.obj \
+ uart0txbuf.obj uart1txbuf.obj uart0rxbuf.obj uart1rxbuf.obj \
+ uart0tx.obj uart1tx.obj uart0rx.obj uart1rx.obj uart0wrhexu16.obj uart1wrhexu16.obj uart0wrhexu32.obj uart1wrhexu32.obj \
+ uart0wrstr.obj uart1wrstr.obj uart0wru16.obj uart1wru16.obj uart0wru32.obj uart1wru32.obj \
+ uart0wrnum16.obj uart0wrnum32.obj uart0wrhex16.obj uart0wrhex32.obj \
+ uart1wrnum16.obj uart1wrnum32.obj uart1wrhex16.obj uart1wrhex32.obj \
+ adctemp.obj adccal.obj adccalg.obj adccalt.obj adcuncal.obj adcseoffs00.obj adcseoffs01.obj adcseoffs10.obj \
+ bch3121dec.obj bch3121decp.obj bch3121enc.obj bch3121encp.obj bch3121stab.obj bch3121syn.obj \
+ wrnum16.obj wrnum32.obj offxosc.obj offlpxosc.obj setuplpxosc.obj setupxosc.obj setupcal.obj \
+ wtimer.obj wtrem.obj wtcbadd.obj wtcbrem.obj wt0setcfg.obj wt1setcfg.obj wtstdby.obj \
+ wt0adda.obj wt1adda.obj wt0addr.obj wt1addr.obj wt0curt.obj wt1curt.obj wt0rem.obj wt1rem.obj wt01rem.obj \
+ radiord16.obj radiord24.obj radiord32.obj radiowr16.obj radiowr24.obj radiowr32.obj radiodswakecore.obj \
+ ax5031comminit.obj ax5031commslpexit.obj ax5031reset.obj ax5031deepsleep.obj ax5031rclkena.obj ax5031rclkdis.obj \
+ ax5031rdfifo.obj ax5031wrfifo.obj ax5031regs.obj \
+ ax5042comminit.obj ax5042commslpexit.obj ax5042reset.obj ax5042deepsleep.obj ax5042rclkena.obj ax5042rclkdis.obj \
+ ax5042rdfifo.obj ax5042wrfifo.obj ax5042regs.obj \
+ ax5043comminit.obj ax5043commslpexit.obj ax5043reset.obj ax5043deepsleep.obj ax5043rclkena.obj ax5043rclkdis.obj \
+ ax5043rdfifo.obj ax5043wrfifo.obj ax5043regs.obj \
+ ax5051comminit.obj ax5051commslpexit.obj ax5051reset.obj ax5051deepsleep.obj ax5051rclkena.obj ax5051rclkdis.obj \
+ ax5051rdfifo.obj ax5051wrfifo.obj ax5051regs.obj \
+ ax8052regs.obj
+
+BINARIES :=
+
+comma := ,
+empty :=
+space := $(empty) $(empty)
+
+all: libmf.lib libmflarge.lib $(BINARIES) $(patsubst %.omf,%.hex,$(BINARIES))
+
+clean:
+ rm -rf LIBMF.LIB libmf.lib libmf LIBMFLARGE.LIB libmflarge.lib libmflarge mflibbinkeil.tar.gz
+
+tar: mflibbinkeil.tar.gz
+
+mflibbinkeil.tar.gz:
+ [ -f LIBMF.LIB ] && mv LIBMF.LIB libmf.lib ; \
+ [ -f LIBMFLARGE.LIB ] && mv LIBMFLARGE.LIB libmflarge.lib ; \
+ tar -c -v -z -f $@ libmf.lib libmflarge.lib
+
+ifeq ($(LIBSUFFIX),)
+libmflarge.lib:
+ make TARGET_MODEL=LARGE LIBSUFFIX=large
+endif
+
+libmf$(LIBSUFFIX):
+ [ ! -d $@ ] && mkdir -p $@
+
+.PRECIOUS: %.src %.obj %.omf
+
+%.obj: %.src
+ $(KEILPATH)/C51/BIN/A51.EXE "$(shell cygpath -w $<)" "PR($(shell cygpath -w $(patsubst %.obj,%.ls1,$@)))" $(A51OPT)
+
+%.src: %.src1
+ ./fixmodname.pl $@ < $< > $@
+
+%.omf: %.obj libmf$(LIBSUFFIX).lib $(shell cygpath -u $(C51LIB)/C51S.LIB)
+ ($(KEILPATH)/C51/BIN/BL51.EXE "$(subst $(space),$(comma),$(foreach fn,$^,$(shell cygpath -w $(fn))))" TO "$(shell cygpath -w $@)" $(L51OPT); x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+%.hex: %.omf
+ $(KEILPATH)/C51/BIN/OH51.EXE "$(shell cygpath -w $<)" HEXFILE "($(shell cygpath -w $@))"
+
+libmf$(LIBSUFFIX)/%.src: ../source/%.c | libmf$(LIBSUFFIX)
+ ($(KEILPATH)/C51/BIN/C51.EXE "$(shell cygpath -w $<)" $(C51FLAGS) SRC "($(shell cygpath -w $@))" PR "($(shell cygpath -w $(patsubst %.src,%.lst,$@)))"; x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/%.src: libmf$(LIBSUFFIX)/%.c | libmf$(LIBSUFFIX)
+ ($(KEILPATH)/C51/BIN/C51.EXE "$(shell cygpath -w $<)" $(C51FLAGS) SRC "($(shell cygpath -w $@))" PR "($(shell cygpath -w $(patsubst %.src,%.lst,$@)))"; x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX).lib: $(patsubst %.obj,libmf$(LIBSUFFIX)/%.obj,$(LIBMFOBJ)) | libmf$(LIBSUFFIX)
+ $(KEILPATH)/C51/BIN/LIB51.EXE TRANSFER "$(subst $(space),$(comma),$(foreach fn,$(patsubst %.obj,libmf$(LIBSUFFIX)/%.obj,$(LIBMFOBJ)),$(shell cygpath -w $(fn))))" TO $@
+
+libmf$(LIBSUFFIX)/uarttimer0.c: ../source/uarttimer.c
+ (unifdef -DTIMER=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer1.c: ../source/uarttimer.c
+ (unifdef -DTIMER=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer2.c: ../source/uarttimer.c
+ (unifdef -DTIMER=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0init.c: ../source/uartinit.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0stop.c: ../source/uartstop.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1init.c: ../source/uartinit.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1stop.c: ../source/uartstop.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0%.c: ../source/io%.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1%.c: ../source/io%.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/dbglnk%.c: ../source/io%.c
+ (unifdef -DUART=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdu%.c: ../source/io%.c
+ (unifdef -DUART=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5031%.c: ../source/radio%.c
+ (unifdef -DRADIO=5031 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5042%.c: ../source/radio%.c
+ (unifdef -DRADIO=5042 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5043%.c: ../source/radio%.c
+ (unifdef -DRADIO=5043 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5051%.c: ../source/radio%.c
+ (unifdef -DRADIO=5051 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccitt.c: ../source/crc8.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccittmsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewire.c: ../source/crc8.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewiremsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansi.c: ../source/crc16.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnp.c: ../source/crc16.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccitt.c: ../source/crc16.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansi.c: ../source/crc32.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsb.c: ../source/crc32msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittmsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewireb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewiremsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansib.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=4 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=5 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansib.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsbb.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdinit.src: ../source/lcdinit.c ../source/libmflcd.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdsetpos.src: ../source/lcdsetpos.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrstr.src: ../source/lcdwrstr.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclear.src: ../source/lcdclear.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclrdisp.src: ../source/lcdclrdisp.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru16.src: ../source/lcdwru16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru32.src: ../source/lcdwru32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu16.src: ../source/lcdwrhexu16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu32.src: ../source/lcdwrhexu32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum16.src: libmf$(LIBSUFFIX)/lcduwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum32.src: libmf$(LIBSUFFIX)/lcduwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex16.src: libmf$(LIBSUFFIX)/lcduwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex32.src: libmf$(LIBSUFFIX)/lcduwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/delay.src: ../source/delay.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/random.src: ../source/random.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitt.src: ../source/crc8ccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewire.src: ../source/crc8onewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitttable.src: ../source/crc8ccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiretable.src: ../source/crc8onewiretable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbtable.src: ../source/crc8ccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbtable.src: ../source/crc8onewiremsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitttable.src: ../source/crcccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16table.src: ../source/crc16table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnptable.src: ../source/crc16dnptable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbtable.src: ../source/crcccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16msbtable.src: ../source/crc16msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbtable.src: ../source/crc16dnpmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32table.src: ../source/crc32table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32msbtable.src: ../source/crc32msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccitt.src: libmf$(LIBSUFFIX)/crc8tccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccittmsb.src: libmf$(LIBSUFFIX)/crc8tccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewire.src: libmf$(LIBSUFFIX)/crc8tonewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewiremsb.src: libmf$(LIBSUFFIX)/crc8tonewiremsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansi.src: libmf$(LIBSUFFIX)/crc16ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsb.src: libmf$(LIBSUFFIX)/crc16ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnp.src: libmf$(LIBSUFFIX)/crc16dnp.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsb.src: libmf$(LIBSUFFIX)/crc16dnpmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitt.src: libmf$(LIBSUFFIX)/crcccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsb.src: libmf$(LIBSUFFIX)/crcccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansi.src: libmf$(LIBSUFFIX)/crc32ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsb.src: libmf$(LIBSUFFIX)/crc32ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittb.src: libmf$(LIBSUFFIX)/crc8ccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbb.src: libmf$(LIBSUFFIX)/crc8ccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewireb.src: libmf$(LIBSUFFIX)/crc8onewireb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbb.src: libmf$(LIBSUFFIX)/crc8onewiremsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansib.src: libmf$(LIBSUFFIX)/crc16ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsbb.src: libmf$(LIBSUFFIX)/crc16ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpb.src: libmf$(LIBSUFFIX)/crc16dnpb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbb.src: libmf$(LIBSUFFIX)/crc16dnpmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittb.src: libmf$(LIBSUFFIX)/crcccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbb.src: libmf$(LIBSUFFIX)/crcccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansib.src: libmf$(LIBSUFFIX)/crc32ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsbb.src: libmf$(LIBSUFFIX)/crc32ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9.src: ../source/pn9.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9table.src: ../source/pn9table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bit.src: ../source/pn9bit.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bits.src: ../source/pn9bits.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9byte.src: ../source/pn9byte.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9buf.src: ../source/pn9buf.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15advtable.src: ../source/pn15advtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15outtable.src: ../source/pn15outtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15adv.src: ../source/pn15adv.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15out.src: ../source/pn15out.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/rev8.src: ../source/rev8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight8.src: ../source/hweight8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight16.src: ../source/hweight16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight32.src: ../source/hweight32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext12.src: ../source/signext12.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext16.src: ../source/signext16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext20.src: ../source/signext20.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext24.src: ../source/signext24.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim16.src: ../source/chksgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim16.src: ../source/sgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim32.src: ../source/chksgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim32.src: ../source/sgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/grayenc8.src: ../source/grayenc8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/graydec8.src: ../source/graydec8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemset.src: ../source/fmemset.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemcpy.src: ../source/fmemcpy.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/standby.src: ../source/standby.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleep.src: ../source/sleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleepcont.src: ../source/sleepcont.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/deepsleep.src: ../source/deepsleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/resetcpu.src: ../source/resetcpu.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashunlock.src: ../source/flashunlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashlock.src: ../source/flashlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwait.src: ../source/flashwait.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashpgerase.src: ../source/flashpgerase.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwrite.src: ../source/flashwrite.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashread.src: ../source/flashread.c ../source/libmfflash.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcal.src: ../source/flashcal.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcsec.src: ../source/flashcsec.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0init.src: libmf$(LIBSUFFIX)/uart0init.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1init.src: libmf$(LIBSUFFIX)/uart1init.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0stop.src: libmf$(LIBSUFFIX)/uart0stop.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1stop.src: libmf$(LIBSUFFIX)/uart1stop.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0txbuf.src: libmf$(LIBSUFFIX)/uart0txbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1txbuf.src: libmf$(LIBSUFFIX)/uart1txbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rxbuf.src: libmf$(LIBSUFFIX)/uart0rxbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rxbuf.src: libmf$(LIBSUFFIX)/uart1rxbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0tx.src: libmf$(LIBSUFFIX)/uart0tx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1tx.src: libmf$(LIBSUFFIX)/uart1tx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rx.src: libmf$(LIBSUFFIX)/uart0rx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rx.src: libmf$(LIBSUFFIX)/uart1rx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu16.src: libmf$(LIBSUFFIX)/uart0wrhexu16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu16.src: libmf$(LIBSUFFIX)/uart1wrhexu16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu32.src: libmf$(LIBSUFFIX)/uart0wrhexu32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu32.src: libmf$(LIBSUFFIX)/uart1wrhexu32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrstr.src: libmf$(LIBSUFFIX)/uart0wrstr.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrstr.src: libmf$(LIBSUFFIX)/uart1wrstr.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru16.src: libmf$(LIBSUFFIX)/uart0wru16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru16.src: libmf$(LIBSUFFIX)/uart1wru16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru32.src: libmf$(LIBSUFFIX)/uart0wru32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru32.src: libmf$(LIBSUFFIX)/uart1wru32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum16.src: libmf$(LIBSUFFIX)/uart0wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum16.src: libmf$(LIBSUFFIX)/uart1wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum32.src: libmf$(LIBSUFFIX)/uart0wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum32.src: libmf$(LIBSUFFIX)/uart1wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex16.src: libmf$(LIBSUFFIX)/uart0wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex16.src: libmf$(LIBSUFFIX)/uart1wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex32.src: libmf$(LIBSUFFIX)/uart0wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex32.src: libmf$(LIBSUFFIX)/uart1wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglink.src: ../source/dbglink.c ../source/libmfdbglink.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktxbuf.src: libmf$(LIBSUFFIX)/dbglnktxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrxbuf.src: libmf$(LIBSUFFIX)/dbglnkrxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktx.src: libmf$(LIBSUFFIX)/dbglnktx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrx.src: libmf$(LIBSUFFIX)/dbglnkrx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu16.src: libmf$(LIBSUFFIX)/dbglnkwrhexu16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu32.src: libmf$(LIBSUFFIX)/dbglnkwrhexu32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrstr.src: libmf$(LIBSUFFIX)/dbglnkwrstr.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru16.src: libmf$(LIBSUFFIX)/dbglnkwru16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru32.src: libmf$(LIBSUFFIX)/dbglnkwru32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum16.src: libmf$(LIBSUFFIX)/dbglnkwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum32.src: libmf$(LIBSUFFIX)/dbglnkwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex16.src: libmf$(LIBSUFFIX)/dbglnkwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex32.src: libmf$(LIBSUFFIX)/dbglnkwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adctemp.src: ../source/adctemp.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccal.src: ../source/adccal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalg.src: ../source/adccalg.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalt.src: ../source/adccalt.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcuncal.src: ../source/adcuncal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs00.src: ../source/adcseoffs00.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs01.src: ../source/adcseoffs01.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs10.src: ../source/adcseoffs10.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121dec.src: ../source/bch3121dec.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121decp.src: ../source/bch3121decp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121enc.src: ../source/bch3121enc.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121encp.src: ../source/bch3121encp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121stab.src: ../source/bch3121stab.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121syn.src: ../source/bch3121syn.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum16.src: ../source/wrnum16.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum32.src: ../source/wrnum32.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offxosc.src: ../source/offxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offlpxosc.src: ../source/offlpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setuplpxosc.src: ../source/setuplpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupxosc.src: ../source/setupxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupcal.src: ../source/setupcal.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtimer.src: ../source/wtimer.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtrem.src: ../source/wtrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbadd.src: ../source/wtcbadd.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbrem.src: ../source/wtcbrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0setcfg.src: ../source/wt0setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1setcfg.src: ../source/wt1setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtstdby.src: ../source/wtstdby.c ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0adda.src: ../source/wt0adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1adda.src: ../source/wt1adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0addr.src: ../source/wt0addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1addr.src: ../source/wt1addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0curt.src: ../source/wt0curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1curt.src: ../source/wt1curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0rem.src: ../source/wt0rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1rem.src: ../source/wt1rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt01rem.src: ../source/wt01rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord16.src: ../source/radiord16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord24.src: ../source/radiord24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord32.src: ../source/radiord32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr16.src: ../source/radiowr16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr24.src: ../source/radiowr24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr32.src: ../source/radiowr32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiodswakecore.src: ../source/radiodswakecore.c ../source/radiodefs.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031comminit.src: libmf$(LIBSUFFIX)/ax5031comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031commslpexit.src: libmf$(LIBSUFFIX)/ax5031commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031reset.src: libmf$(LIBSUFFIX)/ax5031reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031deepsleep.src: libmf$(LIBSUFFIX)/ax5031deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkena.src: ../source/ax5031rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkdis.src: ../source/ax5031rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rdfifo.src: libmf$(LIBSUFFIX)/ax5031rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031wrfifo.src: libmf$(LIBSUFFIX)/ax5031wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031regs.src: ../source/ax5031regs.c ../source/ax8052f131.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042comminit.src: libmf$(LIBSUFFIX)/ax5042comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042commslpexit.src: libmf$(LIBSUFFIX)/ax5042commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042reset.src: libmf$(LIBSUFFIX)/ax5042reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042deepsleep.src: libmf$(LIBSUFFIX)/ax5042deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkena.src: ../source/ax5042rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkdis.src: ../source/ax5042rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rdfifo.src: libmf$(LIBSUFFIX)/ax5042rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042wrfifo.src: libmf$(LIBSUFFIX)/ax5042wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042regs.src: ../source/ax5042regs.c ../source/ax8052f142.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043comminit.src: libmf$(LIBSUFFIX)/ax5043comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043commslpexit.src: libmf$(LIBSUFFIX)/ax5043commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043reset.src: libmf$(LIBSUFFIX)/ax5043reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043deepsleep.src: libmf$(LIBSUFFIX)/ax5043deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkena.src: ../source/ax5043rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkdis.src: ../source/ax5043rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rdfifo.src: libmf$(LIBSUFFIX)/ax5043rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043wrfifo.src: libmf$(LIBSUFFIX)/ax5043wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043regs.src: ../source/ax5043regs.c ../source/ax8052f143.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051comminit.src: libmf$(LIBSUFFIX)/ax5051comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051commslpexit.src: libmf$(LIBSUFFIX)/ax5051commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051reset.src: libmf$(LIBSUFFIX)/ax5051reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051deepsleep.src: libmf$(LIBSUFFIX)/ax5051deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkena.src: ../source/ax5051rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkdis.src: ../source/ax5051rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rdfifo.src: libmf$(LIBSUFFIX)/ax5051rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051wrfifo.src: libmf$(LIBSUFFIX)/ax5051wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051regs.src: ../source/ax5051regs.c ../source/ax8052f151.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax8052regs.src: ../source/ax8052regs.c ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
diff --git a/libs/libmf/buildkeilx/Makefile b/libs/libmf/buildkeilx/Makefile
new file mode 100644
index 00000000..8c8bee09
--- /dev/null
+++ b/libs/libmf/buildkeilx/Makefile
@@ -0,0 +1,432 @@
+TARGET_MODEL := SMALL
+LIBSUFFIX :=
+KEILPATH := C:/EDA/Keil
+C51INC := $(KEILPATH)/C51/INC
+C51LIB := $(KEILPATH)/C51/LIB
+C51FLAGS := OMF2 OBJECTADVANCED $(TARGET_MODEL) DEBUG INCDIR "($(shell cygpath -w ../source))"
+A51OPT := "SET ($(TARGET_MODEL))" EP DEBUG
+L51OPT := "CLASSES (XDATA (X:0x0-X:0x1FFF), HDATA (X:0x0-X:0x1FFF), CODE (C:0x0-C:0xFFFF), CONST (C:0x0-C:0xFFFF), ECODE (C:0x0-C:0xFFFF), HCONST (C:0x0-C:0xFFFF))"
+CPU_TYPE := 8052AH
+CPU_VENDOR := Intel
+CPU_XTAL := 0x01312D00
+
+LIBMFOBJ := lcdinit.obj lcdsetpos.obj lcdwrstr.obj lcdclear.obj lcdclrdisp.obj lcdwru16.obj lcdwru32.obj \
+ lcdwrhexu16.obj lcdwrhexu32.obj lcduwrnum16.obj lcduwrnum32.obj lcduwrhex16.obj lcduwrhex32.obj \
+ dbglink.obj dbglnktxbuf.obj dbglnkrxbuf.obj dbglnktx.obj dbglnkrx.obj dbglnkwrhexu16.obj dbglnkwrhexu32.obj dbglnkwrstr.obj \
+ dbglnkwru16.obj dbglnkwru32.obj dbglnkwrnum16.obj dbglnkwrnum32.obj dbglnkwrhex16.obj dbglnkwrhex32.obj \
+ crc8ccitt.obj crc8onewire.obj crc8tccitt.obj crc8tccittmsb.obj crc8tonewire.obj crc8tonewiremsb.obj \
+ crc8ccittb.obj crc8ccittmsbb.obj crc8onewireb.obj crc8onewiremsbb.obj \
+ crc8ccitttable.obj crc8onewiretable.obj crc8ccittmsbtable.obj crc8onewiremsbtable.obj \
+ crcccitt.obj crcccittmsb.obj crc16ansi.obj crc16ansimsb.obj crc16dnp.obj crc16dnpmsb.obj crc32ansi.obj crc32ansimsb.obj \
+ crcccittb.obj crcccittmsbb.obj crc16ansib.obj crc16ansimsbb.obj crc16dnpb.obj crc16dnpmsbb.obj crc32ansib.obj crc32ansimsbb.obj \
+ crcccitttable.obj crc16table.obj crc16dnptable.obj crcccittmsbtable.obj crc16msbtable.obj \
+ crc16dnpmsbtable.obj crc32table.obj crc32msbtable.obj pn9.obj pn9table.obj pn9bit.obj pn9bits.obj pn9byte.obj pn9buf.obj \
+ pn15advtable.obj pn15outtable.obj pn15adv.obj pn15out.obj \
+ rev8.obj hweight8.obj hweight16.obj hweight32.obj signext12.obj signext16.obj signext20.obj signext24.obj \
+ chksgnlim16.obj sgnlim16.obj chksgnlim32.obj sgnlim32.obj grayenc8.obj graydec8.obj fmemset.obj fmemcpy.obj \
+ delay.obj random.obj sleep.obj sleepcont.obj deepsleep.obj standby.obj resetcpu.obj \
+ flashunlock.obj flashlock.obj flashwait.obj flashpgerase.obj flashwrite.obj flashread.obj flashcal.obj flashcsec.obj \
+ uarttimer0.obj uarttimer1.obj uarttimer2.obj uart0init.obj uart1init.obj uart0txbuf.obj uart1txbuf.obj uart0rxbuf.obj uart1rxbuf.obj \
+ uart0tx.obj uart1tx.obj uart0rx.obj uart1rx.obj uart0wrhexu16.obj uart1wrhexu16.obj uart0wrhexu32.obj uart1wrhexu32.obj \
+ uart0wrstr.obj uart1wrstr.obj uart0wru16.obj uart1wru16.obj uart0wru32.obj uart1wru32.obj \
+ uart0wrnum16.obj uart0wrnum32.obj uart0wrhex16.obj uart0wrhex32.obj \
+ uart1wrnum16.obj uart1wrnum32.obj uart1wrhex16.obj uart1wrhex32.obj \
+ adctemp.obj adccal.obj adccalg.obj adccalt.obj adcuncal.obj adcseoffs00.obj adcseoffs01.obj adcseoffs10.obj \
+ bch3121dec.obj bch3121decp.obj bch3121enc.obj bch3121encp.obj bch3121stab.obj bch3121syn.obj \
+ wrnum16.obj wrnum32.obj offxosc.obj offlpxosc.obj setuplpxosc.obj setupxosc.obj setupcal.obj \
+ wtimer.obj wtrem.obj wtcbadd.obj wtcbrem.obj wt0setcfg.obj wt1setcfg.obj wtstdby.obj \
+ wt0adda.obj wt1adda.obj wt0addr.obj wt1addr.obj wt0curt.obj wt1curt.obj wt0rem.obj wt1rem.obj wt01rem.obj \
+ radiord16.obj radiord24.obj radiord32.obj radiowr16.obj radiowr24.obj radiowr32.obj radiodswakecore.obj \
+ ax5031comminit.obj ax5031commslpexit.obj ax5031reset.obj ax5031deepsleep.obj ax5031rclkena.obj ax5031rclkdis.obj \
+ ax5031rdfifo.obj ax5031wrfifo.obj ax5031regs.obj \
+ ax5042comminit.obj ax5042commslpexit.obj ax5042reset.obj ax5042deepsleep.obj ax5042rclkena.obj ax5042rclkdis.obj \
+ ax5042rdfifo.obj ax5042wrfifo.obj ax5042regs.obj \
+ ax5043comminit.obj ax5043commslpexit.obj ax5043reset.obj ax5043deepsleep.obj ax5043rclkena.obj ax5043rclkdis.obj \
+ ax5043rdfifo.obj ax5043wrfifo.obj ax5043regs.obj \
+ ax5051comminit.obj ax5051commslpexit.obj ax5051reset.obj ax5051deepsleep.obj ax5051rclkena.obj ax5051rclkdis.obj \
+ ax5051rdfifo.obj ax5051wrfifo.obj ax5051regs.obj \
+ ax8052regs.obj
+
+BINARIES :=
+
+comma := ,
+empty :=
+space := $(empty) $(empty)
+
+all: libmf.lib libmflarge.lib $(BINARIES) $(patsubst %.omf,%.hex,$(BINARIES))
+
+clean:
+ rm -rf LIBMF.LIB libmf.lib libmf LIBMFLARGE.LIB libmflarge.lib libmflarge mflibbinkeil2.tar.gz
+
+tar: mflibbinkeil2.tar.gz
+
+mflibbinkeil2.tar.gz:
+ [ -f LIBMF.LIB ] && mv LIBMF.LIB libmf.lib ; \
+ [ -f LIBMFLARGE.LIB ] && mv LIBMFLARGE.LIB libmflarge.lib ; \
+ tar -c -v -z -f $@ libmf.lib libmflarge.lib
+
+ifeq ($(LIBSUFFIX),)
+libmflarge.lib:
+ make TARGET_MODEL=LARGE LIBSUFFIX=large
+endif
+
+libmf$(LIBSUFFIX):
+ [ ! -d $@ ] && mkdir -p $@
+
+.PRECIOUS: %.src %.obj %.omf
+
+%.obj: %.src
+ $(KEILPATH)/C51/BIN/AX51.EXE "$(shell cygpath -w $<)" "PR($(shell cygpath -w $(patsubst %.obj,%.ls1,$@)))" $(A51OPT)
+
+%.src: %.src1
+ ./fixmodname.pl $@ < $< > $@
+
+%.omf: %.obj libmf$(LIBSUFFIX).lib $(shell cygpath -u $(C51LIB)/C51S.LIB)
+ ($(KEILPATH)/C51/BIN/LX51.EXE "$(subst $(space),$(comma),$(foreach fn,$^,$(shell cygpath -w $(fn))))" TO "$(shell cygpath -w $@)" CODE "($(shell cygpath -w $(patsubst %.omf,%.cod,$@)))" $(L51OPT); x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+%.hex: %.omf
+ $(KEILPATH)/C51/BIN/OHX51.EXE "$(shell cygpath -w $<)" HEXFILE "($(shell cygpath -w $@))"
+
+libmf$(LIBSUFFIX)/%.src: ../source/%.c | libmf$(LIBSUFFIX)
+ ($(KEILPATH)/C51/BIN/C51.EXE "$(shell cygpath -w $<)" $(C51FLAGS) DEFINE "(AX5043_DISABLE_XSFR,AX5043_DISABLE_NONBLOCKING)" SRC "($(shell cygpath -w $@))" PR "($(shell cygpath -w $(patsubst %.src,%.lst,$@)))"; x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/%.src: libmf$(LIBSUFFIX)/%.c | libmf$(LIBSUFFIX)
+ ($(KEILPATH)/C51/BIN/C51.EXE "$(shell cygpath -w $<)" $(C51FLAGS) DEFINE "(AX5043_DISABLE_XSFR,AX5043_DISABLE_NONBLOCKING)" SRC "($(shell cygpath -w $@))" PR "($(shell cygpath -w $(patsubst %.src,%.lst,$@)))"; x=$$?; if [ $${x} -lt 2 ]; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX).lib: $(patsubst %.obj,libmf$(LIBSUFFIX)/%.obj,$(LIBMFOBJ)) | libmf$(LIBSUFFIX)
+ $(KEILPATH)/C51/BIN/LIBX51.EXE TRANSFER "$(subst $(space),$(comma),$(foreach fn,$(patsubst %.obj,libmf$(LIBSUFFIX)/%.obj,$(LIBMFOBJ)),$(shell cygpath -w $(fn))))" TO $@
+
+libmf$(LIBSUFFIX)/uarttimer0.c: ../source/uarttimer.c
+ (unifdef -DTIMER=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer1.c: ../source/uarttimer.c
+ (unifdef -DTIMER=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer2.c: ../source/uarttimer.c
+ (unifdef -DTIMER=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0init.c: ../source/uartinit.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0stop.c: ../source/uartstop.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1init.c: ../source/uartinit.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1stop.c: ../source/uartstop.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0%.c: ../source/io%.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1%.c: ../source/io%.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/dbglnk%.c: ../source/io%.c
+ (unifdef -DUART=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdu%.c: ../source/io%.c
+ (unifdef -DUART=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5031%.c: ../source/radio%.c
+ (unifdef -DRADIO=5031 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5042%.c: ../source/radio%.c
+ (unifdef -DRADIO=5042 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5043%.c: ../source/radio%.c
+ (unifdef -DRADIO=5043 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5051%.c: ../source/radio%.c
+ (unifdef -DRADIO=5051 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccitt.c: ../source/crc8.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccittmsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewire.c: ../source/crc8.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewiremsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansi.c: ../source/crc16.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnp.c: ../source/crc16.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccitt.c: ../source/crc16.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansi.c: ../source/crc32.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsb.c: ../source/crc32msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittmsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewireb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewiremsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansib.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=4 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=5 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansib.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsbb.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdinit.src: ../source/lcdinit.c ../source/libmflcd.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdsetpos.src: ../source/lcdsetpos.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrstr.src: ../source/lcdwrstr.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclear.src: ../source/lcdclear.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdclrdisp.src: ../source/lcdclrdisp.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru16.src: ../source/lcdwru16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwru32.src: ../source/lcdwru32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu16.src: ../source/lcdwrhexu16.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcdwrhexu32.src: ../source/lcdwrhexu32.c ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum16.src: libmf$(LIBSUFFIX)/lcduwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrnum32.src: libmf$(LIBSUFFIX)/lcduwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex16.src: libmf$(LIBSUFFIX)/lcduwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/lcduwrhex32.src: libmf$(LIBSUFFIX)/lcduwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/delay.src: ../source/delay.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/random.src: ../source/random.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitt.src: ../source/crc8ccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewire.src: ../source/crc8onewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccitttable.src: ../source/crc8ccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiretable.src: ../source/crc8onewiretable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbtable.src: ../source/crc8ccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbtable.src: ../source/crc8onewiremsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitttable.src: ../source/crcccitttable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16table.src: ../source/crc16table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnptable.src: ../source/crc16dnptable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbtable.src: ../source/crcccittmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16msbtable.src: ../source/crc16msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbtable.src: ../source/crc16dnpmsbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32table.src: ../source/crc32table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32msbtable.src: ../source/crc32msbtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccitt.src: libmf$(LIBSUFFIX)/crc8tccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tccittmsb.src: libmf$(LIBSUFFIX)/crc8tccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewire.src: libmf$(LIBSUFFIX)/crc8tonewire.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8tonewiremsb.src: libmf$(LIBSUFFIX)/crc8tonewiremsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansi.src: libmf$(LIBSUFFIX)/crc16ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsb.src: libmf$(LIBSUFFIX)/crc16ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnp.src: libmf$(LIBSUFFIX)/crc16dnp.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsb.src: libmf$(LIBSUFFIX)/crc16dnpmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccitt.src: libmf$(LIBSUFFIX)/crcccitt.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsb.src: libmf$(LIBSUFFIX)/crcccittmsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansi.src: libmf$(LIBSUFFIX)/crc32ansi.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsb.src: libmf$(LIBSUFFIX)/crc32ansimsb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittb.src: libmf$(LIBSUFFIX)/crc8ccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8ccittmsbb.src: libmf$(LIBSUFFIX)/crc8ccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewireb.src: libmf$(LIBSUFFIX)/crc8onewireb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc8onewiremsbb.src: libmf$(LIBSUFFIX)/crc8onewiremsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansib.src: libmf$(LIBSUFFIX)/crc16ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16ansimsbb.src: libmf$(LIBSUFFIX)/crc16ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpb.src: libmf$(LIBSUFFIX)/crc16dnpb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc16dnpmsbb.src: libmf$(LIBSUFFIX)/crc16dnpmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittb.src: libmf$(LIBSUFFIX)/crcccittb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crcccittmsbb.src: libmf$(LIBSUFFIX)/crcccittmsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansib.src: libmf$(LIBSUFFIX)/crc32ansib.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/crc32ansimsbb.src: libmf$(LIBSUFFIX)/crc32ansimsbb.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9.src: ../source/pn9.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9table.src: ../source/pn9table.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bit.src: ../source/pn9bit.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9bits.src: ../source/pn9bits.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9byte.src: ../source/pn9byte.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn9buf.src: ../source/pn9buf.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15advtable.src: ../source/pn15advtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15outtable.src: ../source/pn15outtable.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15adv.src: ../source/pn15adv.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/pn15out.src: ../source/pn15out.c ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/rev8.src: ../source/rev8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight8.src: ../source/hweight8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight16.src: ../source/hweight16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/hweight32.src: ../source/hweight32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext12.src: ../source/signext12.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext16.src: ../source/signext16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext20.src: ../source/signext20.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/signext24.src: ../source/signext24.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim16.src: ../source/chksgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim16.src: ../source/sgnlim16.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/chksgnlim32.src: ../source/chksgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sgnlim32.src: ../source/sgnlim32.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/grayenc8.src: ../source/grayenc8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/graydec8.src: ../source/graydec8.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemset.src: ../source/fmemset.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/fmemcpy.src: ../source/fmemcpy.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/standby.src: ../source/standby.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleep.src: ../source/sleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/sleepcont.src: ../source/sleepcont.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/deepsleep.src: ../source/deepsleep.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/resetcpu.src: ../source/resetcpu.c ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashunlock.src: ../source/flashunlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashlock.src: ../source/flashlock.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwait.src: ../source/flashwait.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashpgerase.src: ../source/flashpgerase.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashwrite.src: ../source/flashwrite.c ../source/libmfflash.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashread.src: ../source/flashread.c ../source/libmfflash.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcal.src: ../source/flashcal.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/flashcsec.src: ../source/flashcsec.c ../source/libmfcalsector.h ../source/libmfflash.h ../source/libmfcrc.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0init.src: libmf$(LIBSUFFIX)/uart0init.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1init.src: libmf$(LIBSUFFIX)/uart1init.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0stop.src: libmf$(LIBSUFFIX)/uart0stop.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1stop.src: libmf$(LIBSUFFIX)/uart1stop.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0txbuf.src: libmf$(LIBSUFFIX)/uart0txbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1txbuf.src: libmf$(LIBSUFFIX)/uart1txbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rxbuf.src: libmf$(LIBSUFFIX)/uart0rxbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rxbuf.src: libmf$(LIBSUFFIX)/uart1rxbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0tx.src: libmf$(LIBSUFFIX)/uart0tx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1tx.src: libmf$(LIBSUFFIX)/uart1tx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rx.src: libmf$(LIBSUFFIX)/uart0rx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rx.src: libmf$(LIBSUFFIX)/uart1rx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu16.src: libmf$(LIBSUFFIX)/uart0wrhexu16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu16.src: libmf$(LIBSUFFIX)/uart1wrhexu16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu32.src: libmf$(LIBSUFFIX)/uart0wrhexu32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu32.src: libmf$(LIBSUFFIX)/uart1wrhexu32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrstr.src: libmf$(LIBSUFFIX)/uart0wrstr.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrstr.src: libmf$(LIBSUFFIX)/uart1wrstr.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru16.src: libmf$(LIBSUFFIX)/uart0wru16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru16.src: libmf$(LIBSUFFIX)/uart1wru16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru32.src: libmf$(LIBSUFFIX)/uart0wru32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru32.src: libmf$(LIBSUFFIX)/uart1wru32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum16.src: libmf$(LIBSUFFIX)/uart0wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum16.src: libmf$(LIBSUFFIX)/uart1wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum32.src: libmf$(LIBSUFFIX)/uart0wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum32.src: libmf$(LIBSUFFIX)/uart1wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex16.src: libmf$(LIBSUFFIX)/uart0wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex16.src: libmf$(LIBSUFFIX)/uart1wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex32.src: libmf$(LIBSUFFIX)/uart0wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex32.src: libmf$(LIBSUFFIX)/uart1wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglink.src: ../source/dbglink.c ../source/libmfdbglink.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktxbuf.src: libmf$(LIBSUFFIX)/dbglnktxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrxbuf.src: libmf$(LIBSUFFIX)/dbglnkrxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktx.src: libmf$(LIBSUFFIX)/dbglnktx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrx.src: libmf$(LIBSUFFIX)/dbglnkrx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu16.src: libmf$(LIBSUFFIX)/dbglnkwrhexu16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu32.src: libmf$(LIBSUFFIX)/dbglnkwrhexu32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrstr.src: libmf$(LIBSUFFIX)/dbglnkwrstr.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru16.src: libmf$(LIBSUFFIX)/dbglnkwru16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru32.src: libmf$(LIBSUFFIX)/dbglnkwru32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum16.src: libmf$(LIBSUFFIX)/dbglnkwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum32.src: libmf$(LIBSUFFIX)/dbglnkwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex16.src: libmf$(LIBSUFFIX)/dbglnkwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex32.src: libmf$(LIBSUFFIX)/dbglnkwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adctemp.src: ../source/adctemp.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccal.src: ../source/adccal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalg.src: ../source/adccalg.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalt.src: ../source/adccalt.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcuncal.src: ../source/adcuncal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs00.src: ../source/adcseoffs00.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs01.src: ../source/adcseoffs01.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs10.src: ../source/adcseoffs10.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121dec.src: ../source/bch3121dec.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121decp.src: ../source/bch3121decp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121enc.src: ../source/bch3121enc.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121encp.src: ../source/bch3121encp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121stab.src: ../source/bch3121stab.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121syn.src: ../source/bch3121syn.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum16.src: ../source/wrnum16.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum32.src: ../source/wrnum32.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offxosc.src: ../source/offxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offlpxosc.src: ../source/offlpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setuplpxosc.src: ../source/setuplpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupxosc.src: ../source/setupxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupcal.src: ../source/setupcal.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtimer.src: ../source/wtimer.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtrem.src: ../source/wtrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbadd.src: ../source/wtcbadd.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbrem.src: ../source/wtcbrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0setcfg.src: ../source/wt0setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1setcfg.src: ../source/wt1setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtstdby.src: ../source/wtstdby.c ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0adda.src: ../source/wt0adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1adda.src: ../source/wt1adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0addr.src: ../source/wt0addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1addr.src: ../source/wt1addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0curt.src: ../source/wt0curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1curt.src: ../source/wt1curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0rem.src: ../source/wt0rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1rem.src: ../source/wt1rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt01rem.src: ../source/wt01rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord16.src: ../source/radiord16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord24.src: ../source/radiord24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord32.src: ../source/radiord32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr16.src: ../source/radiowr16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr24.src: ../source/radiowr24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr32.src: ../source/radiowr32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiodswakecore.src: ../source/radiodswakecore.c ../source/radiodefs.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031comminit.src: libmf$(LIBSUFFIX)/ax5031comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031commslpexit.src: libmf$(LIBSUFFIX)/ax5031commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031reset.src: libmf$(LIBSUFFIX)/ax5031reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031deepsleep.src: libmf$(LIBSUFFIX)/ax5031deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkena.src: ../source/ax5031rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkdis.src: ../source/ax5031rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rdfifo.src: libmf$(LIBSUFFIX)/ax5031rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031wrfifo.src: libmf$(LIBSUFFIX)/ax5031wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031regs.src: ../source/ax5031regs.c ../source/ax8052f131.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042comminit.src: libmf$(LIBSUFFIX)/ax5042comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042commslpexit.src: libmf$(LIBSUFFIX)/ax5042commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042reset.src: libmf$(LIBSUFFIX)/ax5042reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042deepsleep.src: libmf$(LIBSUFFIX)/ax5042deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkena.src: ../source/ax5042rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkdis.src: ../source/ax5042rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rdfifo.src: libmf$(LIBSUFFIX)/ax5042rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042wrfifo.src: libmf$(LIBSUFFIX)/ax5042wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042regs.src: ../source/ax5042regs.c ../source/ax8052f142.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043comminit.src: libmf$(LIBSUFFIX)/ax5043comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043commslpexit.src: libmf$(LIBSUFFIX)/ax5043commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043reset.src: libmf$(LIBSUFFIX)/ax5043reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043deepsleep.src: libmf$(LIBSUFFIX)/ax5043deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkena.src: ../source/ax5043rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkdis.src: ../source/ax5043rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rdfifo.src: libmf$(LIBSUFFIX)/ax5043rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043wrfifo.src: libmf$(LIBSUFFIX)/ax5043wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043regs.src: ../source/ax5043regs.c ../source/ax8052f143.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051comminit.src: libmf$(LIBSUFFIX)/ax5051comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051commslpexit.src: libmf$(LIBSUFFIX)/ax5051commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051reset.src: libmf$(LIBSUFFIX)/ax5051reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051deepsleep.src: libmf$(LIBSUFFIX)/ax5051deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkena.src: ../source/ax5051rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkdis.src: ../source/ax5051rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rdfifo.src: libmf$(LIBSUFFIX)/ax5051rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051wrfifo.src: libmf$(LIBSUFFIX)/ax5051wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051regs.src: ../source/ax5051regs.c ../source/ax8052f151.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax8052regs.src: ../source/ax8052regs.c ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
diff --git a/libs/libmf/buildsdcc/Makefile b/libs/libmf/buildsdcc/Makefile
new file mode 100644
index 00000000..38355a13
--- /dev/null
+++ b/libs/libmf/buildsdcc/Makefile
@@ -0,0 +1,423 @@
+TARGET_ASM := sdcc-asx8051
+TARGET_LD := sdcc-sdcc
+TARGET_CC := sdcc-sdcc
+TARGET_AR := sdcc-sdcclib
+TARGET_MODEL := --model-small
+TARGET_ASMFLAGS := -xlosg
+TARGET_LNKFLAGS := -mmcs51 --debug --code-loc 0x0000 --code-size 0x2000 --xram-loc 0x0000 --xram-size 0x100 $(TARGET_MODEL) --data-loc 0x08
+TARGET_CFLAGS := --debug -I../source $(TARGET_LNKFLAGS)
+LIBSUFFIX :=
+
+LIBMFOBJ := lcdinit.rel lcdsetpos.rel lcdwrstr.rel lcdclear.rel lcdclrdisp.rel lcdwru16.rel lcdwru32.rel \
+ lcdwrhexu16.rel lcdwrhexu32.rel lcduwrnum16.rel lcduwrnum32.rel lcduwrhex16.rel lcduwrhex32.rel \
+ dbglink.rel dbglnktxbuf.rel dbglnkrxbuf.rel dbglnktx.rel dbglnkrx.rel dbglnkwrhexu16.rel dbglnkwrhexu32.rel dbglnkwrstr.rel \
+ dbglnkwru16.rel dbglnkwru32.rel dbglnkwrnum16.rel dbglnkwrnum32.rel dbglnkwrhex16.rel dbglnkwrhex32.rel \
+ crc8ccitt.rel crc8onewire.rel crc8tccitt.rel crc8tccittmsb.rel crc8tonewire.rel crc8tonewiremsb.rel \
+ crc8ccittb.rel crc8ccittmsbb.rel crc8onewireb.rel crc8onewiremsbb.rel \
+ crc8ccitttable.rel crc8onewiretable.rel crc8ccittmsbtable.rel crc8onewiremsbtable.rel \
+ crcccitt.rel crcccittmsb.rel crc16ansi.rel crc16ansimsb.rel crc16dnp.rel crc16dnpmsb.rel crc32ansi.rel crc32ansimsb.rel \
+ crcccittb.rel crcccittmsbb.rel crc16ansib.rel crc16ansimsbb.rel crc16dnpb.rel crc16dnpmsbb.rel crc32ansib.rel crc32ansimsbb.rel \
+ crcccitttable.rel crc16table.rel crc16dnptable.rel crcccittmsbtable.rel crc16msbtable.rel \
+ crc16dnpmsbtable.rel crc32table.rel crc32msbtable.rel pn9.rel pn9table.rel pn9bit.rel pn9bits.rel pn9byte.rel pn9buf.rel \
+ pn15advtable.rel pn15outtable.rel pn15adv.rel pn15out.rel \
+ rev8.rel hweight8.rel hweight16.rel hweight32.rel signext12.rel signext16.rel signext20.rel signext24.rel \
+ chksgnlim16.rel sgnlim16.rel chksgnlim32.rel sgnlim32.rel grayenc8.rel graydec8.rel fmemset.rel fmemcpy.rel \
+ delay.rel random.rel sleep.rel deepsleep.rel sleepcont.rel standby.rel resetcpu.rel \
+ flashunlock.rel flashlock.rel flashwait.rel flashpgerase.rel flashwrite.rel flashread.rel flashcal.rel flashcsec.rel \
+ uarttimer0.rel uarttimer1.rel uarttimer2.rel uart0init.rel uart1init.rel uart0stop.rel uart1stop.rel \
+ uart0txbuf.rel uart1txbuf.rel uart0rxbuf.rel uart1rxbuf.rel \
+ uart0tx.rel uart1tx.rel uart0rx.rel uart1rx.rel uart0wrhexu16.rel uart1wrhexu16.rel uart0wrhexu32.rel uart1wrhexu32.rel \
+ uart0wrstr.rel uart1wrstr.rel uart0wru16.rel uart1wru16.rel uart0wru32.rel uart1wru32.rel \
+ uart0wrnum16.rel uart0wrnum32.rel uart0wrhex16.rel uart0wrhex32.rel \
+ uart1wrnum16.rel uart1wrnum32.rel uart1wrhex16.rel uart1wrhex32.rel \
+ adctemp.rel adccal.rel adccalg.rel adccalt.rel adcuncal.rel adcseoffs00.rel adcseoffs01.rel adcseoffs10.rel \
+ bch3121dec.rel bch3121decp.rel bch3121enc.rel bch3121encp.rel bch3121stab.rel bch3121syn.rel \
+ wrnum16.rel wrnum32.rel offxosc.rel offlpxosc.rel setuplpxosc.rel setupxosc.rel setupcal.rel \
+ wtimer.rel wtrem.rel wtcbadd.rel wtcbrem.rel wt0setcfg.rel wt1setcfg.rel wtstdby.rel \
+ wt0adda.rel wt1adda.rel wt0addr.rel wt1addr.rel wt0curt.rel wt1curt.rel wt0rem.rel wt1rem.rel wt01rem.rel \
+ radiord16.rel radiord24.rel radiord32.rel radiowr16.rel radiowr24.rel radiowr32.rel radiodswakecore.rel \
+ ax5031comminit.rel ax5031commslpexit.rel ax5031reset.rel ax5031deepsleep.rel ax5031rclkena.rel ax5031rclkdis.rel \
+ ax5031rdfifo.rel ax5031wrfifo.rel ax5031regs.rel \
+ ax5042comminit.rel ax5042commslpexit.rel ax5042reset.rel ax5042deepsleep.rel ax5042rclkena.rel ax5042rclkdis.rel \
+ ax5042rdfifo.rel ax5042wrfifo.rel ax5042regs.rel \
+ ax5043comminit.rel ax5043commslpexit.rel ax5043reset.rel ax5043deepsleep.rel ax5043rclkena.rel ax5043rclkdis.rel \
+ ax5043rdfifo.rel ax5043wrfifo.rel ax5043regs.rel \
+ ax5051comminit.rel ax5051commslpexit.rel ax5051reset.rel ax5051deepsleep.rel ax5051rclkena.rel ax5051rclkdis.rel \
+ ax5051rdfifo.rel ax5051wrfifo.rel ax5051regs.rel \
+ ax8052regs.rel
+
+BINARIES :=
+
+all: libmf.lib libmflarge.lib $(BINARIES) $(patsubst %.omf,%.cdb,$(BINARIES)) $(patsubst %.omf,%.ihx,$(BINARIES))
+
+clean:
+ rm -rf *.lnk libmf.lib libmf libmflarge.lib libmflarge mflibbinsdcc.tar.gz mflibsrc.tar.gz
+
+tar: mflibbinsdcc.tar.gz mflibsrc.tar.gz
+
+mflibbinsdcc.tar.gz: libmf.lib libmflarge.lib
+ tar -c -v -z -f $@ libmf.lib libmflarge.lib
+
+mflibsrc.tar.gz:
+ cd .. ; \
+ tar -c -v -z -f buildsdcc/$@ build*/Makefile source/*.c source/*.h source/*.s51 doc/LibMF.pdf buildiar/genrregs.pl
+
+ifeq ($(LIBSUFFIX),)
+libmflarge.lib:
+ make TARGET_MODEL=--model-large LIBSUFFIX=large
+endif
+
+libmf$(LIBSUFFIX):
+ [ ! -d $@ ] && mkdir -p $@
+
+.PRECIOUS: %.rel %.omf %.ihx %.cdb
+
+%.rel: ../%.c
+ ($(TARGET_CC) -c $(TARGET_CFLAGS) -o $@ $<; x=$$?; dn=`dirname $<`/; fn=`basename $< .c`; rm -f $${dn}$${fn}.asm ; exit $${x})
+
+%.omf %.ihx %.cdb: %.rel libmf$(LIBSUFFIX).lib
+ (libdir=`pwd`; dn=`dirname $<`/; fn=`basename $< .rel`; cd $${dn}; $(TARGET_LD) -V $(TARGET_LNKFLAGS) -L$${libdir} -llibmf$(LIBSUFFIX) $${fn}.rel; x=$$?; mv $${fn} $${fn}.omf; exit $${x})
+
+libmf$(LIBSUFFIX)/%.rel: ../source/%.c | libmf$(LIBSUFFIX)
+ ($(TARGET_CC) -c $(TARGET_CFLAGS) -o $@ $<; x=$$?; dn=`dirname $<`/; fn=`basename $< .c`; rm -f $${dn}$${fn}.asm ; exit $${x})
+
+libmf$(LIBSUFFIX)/%.rel: libmf$(LIBSUFFIX)/%.c | libmf$(LIBSUFFIX)
+ ($(TARGET_CC) -c $(TARGET_CFLAGS) -o $@ $<; x=$$?; dn=`dirname $<`/; fn=`basename $< .c`; rm -f $${dn}$${fn}.asm ; exit $${x})
+
+libmf$(LIBSUFFIX).lib: $(patsubst %.rel,libmf$(LIBSUFFIX)/%.rel,$(LIBMFOBJ)) | libmf$(LIBSUFFIX)
+ $(TARGET_AR) -a $@ $(patsubst %.rel,libmf$(LIBSUFFIX)/%.rel,$(LIBMFOBJ))
+
+libmf$(LIBSUFFIX)/uarttimer0.c: ../source/uarttimer.c
+ (unifdef -DTIMER=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer1.c: ../source/uarttimer.c
+ (unifdef -DTIMER=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uarttimer2.c: ../source/uarttimer.c
+ (unifdef -DTIMER=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0init.c: ../source/uartinit.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0stop.c: ../source/uartstop.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1init.c: ../source/uartinit.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1stop.c: ../source/uartstop.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart0%.c: ../source/io%.c
+ (unifdef -DUART=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/uart1%.c: ../source/io%.c
+ (unifdef -DUART=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/dbglnk%.c: ../source/io%.c
+ (unifdef -DUART=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/lcdu%.c: ../source/io%.c
+ (unifdef -DUART=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5031%.c: ../source/radio%.c
+ (unifdef -DRADIO=5031 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5042%.c: ../source/radio%.c
+ (unifdef -DRADIO=5042 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5043%.c: ../source/radio%.c
+ (unifdef -DRADIO=5043 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/ax5051%.c: ../source/radio%.c
+ (unifdef -DRADIO=5051 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccitt.c: ../source/crc8.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tccittmsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewire.c: ../source/crc8.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8tonewiremsb.c: ../source/crc8msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansi.c: ../source/crc16.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnp.c: ../source/crc16.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccitt.c: ../source/crc16.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsb.c: ../source/crc16msb.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansi.c: ../source/crc32.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsb.c: ../source/crc32msb.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8ccittmsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewireb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc8onewiremsbb.c: ../source/crc8b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansib.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16ansimsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=2 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc16dnpmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=3 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=4 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crcccittmsbb.c: ../source/crc16b.c
+ (unifdef -DCRCMODE=5 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansib.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=0 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
+libmf$(LIBSUFFIX)/crc32ansimsbb.c: ../source/crc32b.c
+ (unifdef -DCRCMODE=1 -o $@ $<; x=$$?; if [ $${x} -lt 2 ] ; then x=0; fi; exit $${x})
+
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+libmf$(LIBSUFFIX)/uart0txbuf.rel: libmf$(LIBSUFFIX)/uart0txbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1txbuf.rel: libmf$(LIBSUFFIX)/uart1txbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rxbuf.rel: libmf$(LIBSUFFIX)/uart0rxbuf.c ../source/libmfuart0.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rxbuf.rel: libmf$(LIBSUFFIX)/uart1rxbuf.c ../source/libmfuart1.h ../source/libmfuart.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0tx.rel: libmf$(LIBSUFFIX)/uart0tx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1tx.rel: libmf$(LIBSUFFIX)/uart1tx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0rx.rel: libmf$(LIBSUFFIX)/uart0rx.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1rx.rel: libmf$(LIBSUFFIX)/uart1rx.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu16.rel: libmf$(LIBSUFFIX)/uart0wrhexu16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu16.rel: libmf$(LIBSUFFIX)/uart1wrhexu16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhexu32.rel: libmf$(LIBSUFFIX)/uart0wrhexu32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhexu32.rel: libmf$(LIBSUFFIX)/uart1wrhexu32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrstr.rel: libmf$(LIBSUFFIX)/uart0wrstr.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrstr.rel: libmf$(LIBSUFFIX)/uart1wrstr.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru16.rel: libmf$(LIBSUFFIX)/uart0wru16.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru16.rel: libmf$(LIBSUFFIX)/uart1wru16.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wru32.rel: libmf$(LIBSUFFIX)/uart0wru32.c ../source/libmfuart0.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wru32.rel: libmf$(LIBSUFFIX)/uart1wru32.c ../source/libmfuart1.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum16.rel: libmf$(LIBSUFFIX)/uart0wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum16.rel: libmf$(LIBSUFFIX)/uart1wrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrnum32.rel: libmf$(LIBSUFFIX)/uart0wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrnum32.rel: libmf$(LIBSUFFIX)/uart1wrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex16.rel: libmf$(LIBSUFFIX)/uart0wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex16.rel: libmf$(LIBSUFFIX)/uart1wrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart0wrhex32.rel: libmf$(LIBSUFFIX)/uart0wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/uart1wrhex32.rel: libmf$(LIBSUFFIX)/uart1wrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglink.rel: ../source/dbglink.c ../source/libmfdbglink.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktxbuf.rel: libmf$(LIBSUFFIX)/dbglnktxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrxbuf.rel: libmf$(LIBSUFFIX)/dbglnkrxbuf.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnktx.rel: libmf$(LIBSUFFIX)/dbglnktx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkrx.rel: libmf$(LIBSUFFIX)/dbglnkrx.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu16.rel: libmf$(LIBSUFFIX)/dbglnkwrhexu16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhexu32.rel: libmf$(LIBSUFFIX)/dbglnkwrhexu32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrstr.rel: libmf$(LIBSUFFIX)/dbglnkwrstr.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru16.rel: libmf$(LIBSUFFIX)/dbglnkwru16.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwru32.rel: libmf$(LIBSUFFIX)/dbglnkwru32.c ../source/libmfdbglink.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum16.rel: libmf$(LIBSUFFIX)/dbglnkwrnum16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrnum32.rel: libmf$(LIBSUFFIX)/dbglnkwrnum32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex16.rel: libmf$(LIBSUFFIX)/dbglnkwrhex16.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/dbglnkwrhex32.rel: libmf$(LIBSUFFIX)/dbglnkwrhex32.c ../source/wrnum.h ../source/libmfuart0.h ../source/libmfuart1.h ../source/libmfdbglink.h ../source/libmflcd.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adctemp.rel: ../source/adctemp.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccal.rel: ../source/adccal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalg.rel: ../source/adccalg.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adccalt.rel: ../source/adccalt.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcuncal.rel: ../source/adcuncal.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs00.rel: ../source/adcseoffs00.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs01.rel: ../source/adcseoffs01.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/adcseoffs10.rel: ../source/adcseoffs10.c ../source/libmfadc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121dec.rel: ../source/bch3121dec.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121decp.rel: ../source/bch3121decp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121enc.rel: ../source/bch3121enc.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121encp.rel: ../source/bch3121encp.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121stab.rel: ../source/bch3121stab.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/bch3121syn.rel: ../source/bch3121syn.c ../source/libmfbch.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum16.rel: ../source/wrnum16.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wrnum32.rel: ../source/wrnum32.c ../source/wrnum.h ../source/libmftypes.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offxosc.rel: ../source/offxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/offlpxosc.rel: ../source/offlpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setuplpxosc.rel: ../source/setuplpxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupxosc.rel: ../source/setupxosc.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/setupcal.rel: ../source/setupcal.c ../source/libmfosc.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtimer.rel: ../source/wtimer.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtrem.rel: ../source/wtrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbadd.rel: ../source/wtcbadd.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtcbrem.rel: ../source/wtcbrem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0setcfg.rel: ../source/wt0setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1setcfg.rel: ../source/wt1setcfg.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wtstdby.rel: ../source/wtstdby.c ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0adda.rel: ../source/wt0adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1adda.rel: ../source/wt1adda.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0addr.rel: ../source/wt0addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1addr.rel: ../source/wt1addr.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0curt.rel: ../source/wt0curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1curt.rel: ../source/wt1curt.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt0rem.rel: ../source/wt0rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt1rem.rel: ../source/wt1rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/wt01rem.rel: ../source/wt01rem.c ../source/wtimer.h ../source/libmfwtimer.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord16.rel: ../source/radiord16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord24.rel: ../source/radiord24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiord32.rel: ../source/radiord32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr16.rel: ../source/radiowr16.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr24.rel: ../source/radiowr24.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiowr32.rel: ../source/radiowr32.c ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/radiodswakecore.rel: ../source/radiodswakecore.c ../source/radiodefs.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031comminit.rel: libmf$(LIBSUFFIX)/ax5031comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031commslpexit.rel: libmf$(LIBSUFFIX)/ax5031commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031reset.rel: libmf$(LIBSUFFIX)/ax5031reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031deepsleep.rel: libmf$(LIBSUFFIX)/ax5031deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkena.rel: ../source/ax5031rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rclkdis.rel: ../source/ax5031rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031rdfifo.rel: libmf$(LIBSUFFIX)/ax5031rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031wrfifo.rel: libmf$(LIBSUFFIX)/ax5031wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5031regs.rel: ../source/ax5031regs.c ../source/ax8052f131.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042comminit.rel: libmf$(LIBSUFFIX)/ax5042comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042commslpexit.rel: libmf$(LIBSUFFIX)/ax5042commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042reset.rel: libmf$(LIBSUFFIX)/ax5042reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042deepsleep.rel: libmf$(LIBSUFFIX)/ax5042deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkena.rel: ../source/ax5042rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rclkdis.rel: ../source/ax5042rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042rdfifo.rel: libmf$(LIBSUFFIX)/ax5042rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042wrfifo.rel: libmf$(LIBSUFFIX)/ax5042wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5042regs.rel: ../source/ax5042regs.c ../source/ax8052f142.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043comminit.rel: libmf$(LIBSUFFIX)/ax5043comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043commslpexit.rel: libmf$(LIBSUFFIX)/ax5043commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043reset.rel: libmf$(LIBSUFFIX)/ax5043reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043deepsleep.rel: libmf$(LIBSUFFIX)/ax5043deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkena.rel: ../source/ax5043rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rclkdis.rel: ../source/ax5043rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043rdfifo.rel: libmf$(LIBSUFFIX)/ax5043rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043wrfifo.rel: libmf$(LIBSUFFIX)/ax5043wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5043regs.rel: ../source/ax5043regs.c ../source/ax8052f143.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051comminit.rel: libmf$(LIBSUFFIX)/ax5051comminit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051commslpexit.rel: libmf$(LIBSUFFIX)/ax5051commslpexit.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051reset.rel: libmf$(LIBSUFFIX)/ax5051reset.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051deepsleep.rel: libmf$(LIBSUFFIX)/ax5051deepsleep.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkena.rel: ../source/ax5051rclkena.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rclkdis.rel: ../source/ax5051rclkdis.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051rdfifo.rel: libmf$(LIBSUFFIX)/ax5051rdfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051wrfifo.rel: libmf$(LIBSUFFIX)/ax5051wrfifo.c ../source/radiodefs.h ../source/libmfradio.h ../source/libmftypes.h ../source/ax8052.h ../source/ax8052f131.h ../source/ax8052f142.h ../source/ax8052f143.h ../source/ax8052f151.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax5051regs.rel: ../source/ax5051regs.c ../source/ax8052f151.h ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
+libmf$(LIBSUFFIX)/ax8052regs.rel: ../source/ax8052regs.c ../source/ax8052.h ../source/axcompiler.h | libmf$(LIBSUFFIX)
diff --git a/libs/libmf/builtsource/ax5031comminit.c b/libs/libmf/builtsource/ax5031comminit.c
new file mode 100644
index 00000000..ac3c4569
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031comminit.c
@@ -0,0 +1,24 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+__reentrantb void radio_comminit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x47;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+}
diff --git a/libs/libmf/builtsource/ax5031commslpexit.c b/libs/libmf/builtsource/ax5031commslpexit.c
new file mode 100644
index 00000000..33110be5
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031commslpexit.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+__reentrantb void radio_commsleepexit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX |= 0x40;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ // restore IRQ setting and pullup
+ radio_probeirq();
+}
diff --git a/libs/libmf/builtsource/ax5031deepsleep.c b/libs/libmf/builtsource/ax5031deepsleep.c
new file mode 100644
index 00000000..199b0122
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031deepsleep.c
@@ -0,0 +1,49 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+#if DEEPSLEEP
+
+__reentrantb void radio_enter_deepsleep(void) __reentrant
+{
+ PORTR |= 0x09;
+ // ensure last bit read before entering deep sleep is a zero;
+ // this is held until after wakeup is complete; otherwise,
+ // the wakeup protocol will not work
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ RADIO_PWRMODE = PWRMODE_DEEPSLEEP;
+ RADIOMUX &= (uint8_t)~0x40;
+ // turn off pull-up if MISO is driven low
+ PORTR &= 0xF7 | PINR;
+}
+
+__reentrantb uint8_t radio_wakeup_deepsleep(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x07;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+ {
+ uint8_t i = radio_wakeup_deepsleep_core();
+ if (i)
+ return i;
+ }
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5031rdfifo.c b/libs/libmf/builtsource/ax5031rdfifo.c
new file mode 100644
index 00000000..f536b4a0
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031rdfifo.c
@@ -0,0 +1,88 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ movx a,@dptr
+ mov @r0,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ movx a,@r0
+ ;movc @dptr,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *ptr++ = *(const uint8_t __xdata *)(AX8052_RADIOBASE | FDATA);
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5031reset.c b/libs/libmf/builtsource/ax5031reset.c
new file mode 100644
index 00000000..a3da797d
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031reset.c
@@ -0,0 +1,96 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_reset(void) __reentrant
+{
+ uint8_t i;
+ // Initialize Interface
+ DIRR = 0x15;
+ PORTR = 0xEB;
+#if DEEPSLEEP
+ RADIOMUX = 0x07;
+#else
+ RADIOMUX = 0x47;
+#endif
+ RADIOACC = RACC;
+ GPIOENABLE = 1;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+#if DEEPSLEEP
+ // Ensure Device is not in Deep Sleep
+ radio_wakeup_deepsleep_core();
+#endif
+ // Reset Device
+ RADIO_PWRMODE = 0x80;
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ // Wait some time for regulator startup
+#if defined(VREGDELAY) && VREGDELAY > 0
+ delay(VREGDELAY);
+#endif
+ // Check Scratch
+ i = RADIO_SILICONREVISION;
+ i = RADIO_SILICONREVISION;
+#ifdef SILICONREV2
+ if (i != SILICONREV1 && i != SILICONREV2)
+ return RADIO_ERR_REVISION;
+#else
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+#endif
+ RADIO_SCRATCH = 0x55;
+ if (RADIO_SCRATCH != 0x55)
+ return RADIO_ERR_COMM;
+ RADIO_SCRATCH = 0xAA;
+ if (RADIO_SCRATCH != 0xAA)
+ return RADIO_ERR_COMM;
+ // Initialize Radio Interface Registers
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return RADIO_OK;
+}
+
+
+__reentrantb uint8_t ax5031_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5031_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5031_PINCFG1 = pc1;
+ AX5031_PINCFG2 = 0x22; /* IRQ Line 1 */
+ p &= PINR;
+ AX5031_PINCFG2 = 0x20; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5031_PINCFG2 = 0x00;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5031_PINCFG1 = 0x20 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
diff --git a/libs/libmf/builtsource/ax5031wrfifo.c b/libs/libmf/builtsource/ax5031wrfifo.c
new file mode 100644
index 00000000..f80c55b1
--- /dev/null
+++ b/libs/libmf/builtsource/ax5031wrfifo.c
@@ -0,0 +1,89 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5031
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ mov a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ clr a
+ movc a,@a+dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *(uint8_t __xdata *)(AX8052_RADIOBASE | FDATA) = *ptr++;
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5042comminit.c b/libs/libmf/builtsource/ax5042comminit.c
new file mode 100644
index 00000000..4cae66a3
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042comminit.c
@@ -0,0 +1,24 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+__reentrantb void radio_comminit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x47;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+}
diff --git a/libs/libmf/builtsource/ax5042commslpexit.c b/libs/libmf/builtsource/ax5042commslpexit.c
new file mode 100644
index 00000000..ad1b8244
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042commslpexit.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+__reentrantb void radio_commsleepexit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX |= 0x40;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ // restore IRQ setting and pullup
+ radio_probeirq();
+}
diff --git a/libs/libmf/builtsource/ax5042deepsleep.c b/libs/libmf/builtsource/ax5042deepsleep.c
new file mode 100644
index 00000000..24a8a5e5
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042deepsleep.c
@@ -0,0 +1,49 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+#if DEEPSLEEP
+
+__reentrantb void radio_enter_deepsleep(void) __reentrant
+{
+ PORTR |= 0x09;
+ // ensure last bit read before entering deep sleep is a zero;
+ // this is held until after wakeup is complete; otherwise,
+ // the wakeup protocol will not work
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ RADIO_PWRMODE = PWRMODE_DEEPSLEEP;
+ RADIOMUX &= (uint8_t)~0x40;
+ // turn off pull-up if MISO is driven low
+ PORTR &= 0xF7 | PINR;
+}
+
+__reentrantb uint8_t radio_wakeup_deepsleep(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x07;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+ {
+ uint8_t i = radio_wakeup_deepsleep_core();
+ if (i)
+ return i;
+ }
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5042rdfifo.c b/libs/libmf/builtsource/ax5042rdfifo.c
new file mode 100644
index 00000000..d135d6ff
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042rdfifo.c
@@ -0,0 +1,88 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ movx a,@dptr
+ mov @r0,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ movx a,@r0
+ ;movc @dptr,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *ptr++ = *(const uint8_t __xdata *)(AX8052_RADIOBASE | FDATA);
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5042reset.c b/libs/libmf/builtsource/ax5042reset.c
new file mode 100644
index 00000000..b7883a9f
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042reset.c
@@ -0,0 +1,100 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_reset(void) __reentrant
+{
+ uint8_t i;
+ // Initialize Interface
+ DIRR = 0x15;
+ PORTR = 0xEB;
+#if DEEPSLEEP
+ RADIOMUX = 0x07;
+#else
+ RADIOMUX = 0x47;
+#endif
+ RADIOACC = RACC;
+ GPIOENABLE = 1;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+#if DEEPSLEEP
+ // Ensure Device is not in Deep Sleep
+ radio_wakeup_deepsleep_core();
+#endif
+ // Reset Device
+ RADIO_PWRMODE = 0x80;
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ // Wait some time for regulator startup
+#if defined(VREGDELAY) && VREGDELAY > 0
+ delay(VREGDELAY);
+#endif
+ // Check Scratch
+ i = RADIO_SILICONREVISION;
+ i = RADIO_SILICONREVISION;
+#ifdef SILICONREV2
+ if (i != SILICONREV1 && i != SILICONREV2)
+ return RADIO_ERR_REVISION;
+#else
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+#endif
+ RADIO_SCRATCH = 0x55;
+ if (RADIO_SCRATCH != 0x55)
+ return RADIO_ERR_COMM;
+ RADIO_SCRATCH = 0xAA;
+ if (RADIO_SCRATCH != 0xAA)
+ return RADIO_ERR_COMM;
+ // Initialize Radio Interface Registers
+ AX5042_IFMODE = 0x00;
+ AX5042_AGCTARGET = 0x0E;
+ AX5042_PLLRNGMISC = 0x01;
+ AX5042_RXMISC = 0x35;
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return RADIO_OK;
+}
+
+
+__reentrantb uint8_t ax5042_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5042_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5042_PINCFG1 = 0xD0 | pc1;
+ AX5042_PINCFG2 = 0xE2; /* IRQ Line 1 */
+ p &= PINR;
+ AX5042_PINCFG2 = 0xE0; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5042_PINCFG2 = 0xC0;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5042_PINCFG1 = 0xF0 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
diff --git a/libs/libmf/builtsource/ax5042wrfifo.c b/libs/libmf/builtsource/ax5042wrfifo.c
new file mode 100644
index 00000000..c6f88a2b
--- /dev/null
+++ b/libs/libmf/builtsource/ax5042wrfifo.c
@@ -0,0 +1,89 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5042
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ mov a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ clr a
+ movc a,@a+dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *(uint8_t __xdata *)(AX8052_RADIOBASE | FDATA) = *ptr++;
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5043comminit.c b/libs/libmf/builtsource/ax5043comminit.c
new file mode 100644
index 00000000..68a53af2
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043comminit.c
@@ -0,0 +1,24 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+__reentrantb void radio_comminit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x47;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+}
diff --git a/libs/libmf/builtsource/ax5043commslpexit.c b/libs/libmf/builtsource/ax5043commslpexit.c
new file mode 100644
index 00000000..dd82439f
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043commslpexit.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+__reentrantb void radio_commsleepexit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX |= 0x40;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ // restore IRQ setting and pullup
+ radio_probeirq();
+}
diff --git a/libs/libmf/builtsource/ax5043deepsleep.c b/libs/libmf/builtsource/ax5043deepsleep.c
new file mode 100644
index 00000000..ae15faf6
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043deepsleep.c
@@ -0,0 +1,50 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+#if DEEPSLEEP
+
+__reentrantb void radio_enter_deepsleep(void) __reentrant
+{
+ PORTR |= 0x0B;
+ AX5043_PINFUNCSYSCLK = 0x01;
+ // ensure last bit read before entering deep sleep is a zero;
+ // this is held until after wakeup is complete; otherwise,
+ // the wakeup protocol will not work
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ RADIO_PWRMODE = PWRMODE_DEEPSLEEP;
+ RADIOMUX &= (uint8_t)~0x40;
+ // turn off pull-up if MISO is driven low
+ PORTR &= 0xF7 | PINR;
+}
+
+__reentrantb uint8_t radio_wakeup_deepsleep(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x07;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+ {
+ uint8_t i = radio_wakeup_deepsleep_core();
+ if (i)
+ return i;
+ }
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5043rdfifo.c b/libs/libmf/builtsource/ax5043rdfifo.c
new file mode 100644
index 00000000..870fb001
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043rdfifo.c
@@ -0,0 +1,88 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ movx a,@dptr
+ mov @r0,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ movx a,@r0
+ ;movc @dptr,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *ptr++ = *(const uint8_t __xdata *)(AX8052_RADIOBASE | FDATA);
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5043reset.c b/libs/libmf/builtsource/ax5043reset.c
new file mode 100644
index 00000000..c86f880b
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043reset.c
@@ -0,0 +1,97 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_reset(void) __reentrant
+{
+ uint8_t i;
+ // Initialize Interface
+ DIRR = 0x15;
+ PORTR = 0xEB;
+#if DEEPSLEEP
+ RADIOMUX = 0x07;
+#else
+ RADIOMUX = 0x47;
+#endif
+ RADIOACC = RACC;
+ GPIOENABLE = 1;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+#if DEEPSLEEP
+ // Ensure Device is not in Deep Sleep
+ radio_wakeup_deepsleep_core();
+#endif
+ // Reset Device
+ RADIO_PWRMODE = 0x80;
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ // Wait some time for regulator startup
+#if defined(VREGDELAY) && VREGDELAY > 0
+ delay(VREGDELAY);
+#endif
+ // Check Scratch
+ i = RADIO_SILICONREVISION;
+ i = RADIO_SILICONREVISION;
+#ifdef SILICONREV2
+ if (i != SILICONREV1 && i != SILICONREV2)
+ return RADIO_ERR_REVISION;
+#else
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+#endif
+ RADIO_SCRATCH = 0x55;
+ if (RADIO_SCRATCH != 0x55)
+ return RADIO_ERR_COMM;
+ RADIO_SCRATCH = 0xAA;
+ if (RADIO_SCRATCH != 0xAA)
+ return RADIO_ERR_COMM;
+ // Initialize Radio Interface Registers
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return RADIO_OK;
+}
+
+
+SFRX(RADIODRV, 0x7045)
+
+__reentrantb uint8_t ax5043_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR &= 0xEB;
+ PORTR |= 0x2B;
+ AX5043_PINFUNCIRQ = 0x01; /* IRQ Line 1 */
+ p &= PINR;
+ AX5043_PINFUNCIRQ = 0x00; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5043_PINFUNCIRQ = 0x03;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5043_PINFUNCIRQ = 0x02; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
diff --git a/libs/libmf/builtsource/ax5043wrfifo.c b/libs/libmf/builtsource/ax5043wrfifo.c
new file mode 100644
index 00000000..b6c4d4a5
--- /dev/null
+++ b/libs/libmf/builtsource/ax5043wrfifo.c
@@ -0,0 +1,89 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5043
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ mov a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ clr a
+ movc a,@a+dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *(uint8_t __xdata *)(AX8052_RADIOBASE | FDATA) = *ptr++;
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5051comminit.c b/libs/libmf/builtsource/ax5051comminit.c
new file mode 100644
index 00000000..afded27c
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051comminit.c
@@ -0,0 +1,24 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+__reentrantb void radio_comminit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x47;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+}
diff --git a/libs/libmf/builtsource/ax5051commslpexit.c b/libs/libmf/builtsource/ax5051commslpexit.c
new file mode 100644
index 00000000..32d8b89a
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051commslpexit.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+__reentrantb void radio_commsleepexit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX |= 0x40;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ // restore IRQ setting and pullup
+ radio_probeirq();
+}
diff --git a/libs/libmf/builtsource/ax5051deepsleep.c b/libs/libmf/builtsource/ax5051deepsleep.c
new file mode 100644
index 00000000..665b86a8
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051deepsleep.c
@@ -0,0 +1,49 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+#if DEEPSLEEP
+
+__reentrantb void radio_enter_deepsleep(void) __reentrant
+{
+ PORTR |= 0x09;
+ // ensure last bit read before entering deep sleep is a zero;
+ // this is held until after wakeup is complete; otherwise,
+ // the wakeup protocol will not work
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ RADIO_PWRMODE = PWRMODE_DEEPSLEEP;
+ RADIOMUX &= (uint8_t)~0x40;
+ // turn off pull-up if MISO is driven low
+ PORTR &= 0xF7 | PINR;
+}
+
+__reentrantb uint8_t radio_wakeup_deepsleep(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x07;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+ {
+ uint8_t i = radio_wakeup_deepsleep_core();
+ if (i)
+ return i;
+ }
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5051rdfifo.c b/libs/libmf/builtsource/ax5051rdfifo.c
new file mode 100644
index 00000000..4d1b23b5
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051rdfifo.c
@@ -0,0 +1,88 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ movx a,@dptr
+ mov @r0,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ movx a,@r0
+ ;movc @dptr,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *ptr++ = *(const uint8_t __xdata *)(AX8052_RADIOBASE | FDATA);
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/ax5051reset.c b/libs/libmf/builtsource/ax5051reset.c
new file mode 100644
index 00000000..465f5563
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051reset.c
@@ -0,0 +1,119 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_reset(void) __reentrant
+{
+ uint8_t i;
+ // Initialize Interface
+ DIRR = 0x15;
+ PORTR = 0xEB;
+#if DEEPSLEEP
+ RADIOMUX = 0x07;
+#else
+ RADIOMUX = 0x47;
+#endif
+ RADIOACC = RACC;
+ GPIOENABLE = 1;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+#if DEEPSLEEP
+ // Ensure Device is not in Deep Sleep
+ radio_wakeup_deepsleep_core();
+#endif
+ // Reset Device
+ RADIO_PWRMODE = 0x80;
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ // Wait some time for regulator startup
+#if defined(VREGDELAY) && VREGDELAY > 0
+ delay(VREGDELAY);
+#endif
+ // Check Scratch
+ i = RADIO_SILICONREVISION;
+ i = RADIO_SILICONREVISION;
+#ifdef SILICONREV2
+ if (i != SILICONREV1 && i != SILICONREV2)
+ return RADIO_ERR_REVISION;
+#else
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+#endif
+ RADIO_SCRATCH = 0x55;
+ if (RADIO_SCRATCH != 0x55)
+ return RADIO_ERR_COMM;
+ RADIO_SCRATCH = 0xAA;
+ if (RADIO_SCRATCH != 0xAA)
+ return RADIO_ERR_COMM;
+ // Initialize Radio Interface Registers
+ AX5051_IFMODE = 0x00;
+ AX5051_PLLVCOI = 0x01;
+ AX5051_RXMISC = 0x35;
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return RADIO_OK;
+}
+
+
+__reentrantb uint8_t ax5051_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5051_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5051_PINCFG1 = 0xD0 | pc1;
+ AX5051_PINCFG2 = 0xF2; /* IRQ Line 1 */
+ p &= PINR;
+ AX5051_PINCFG2 = 0xF0; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5051_PINCFG2 = 0xD0;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5051_PINCFG1 = 0xA0 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ /*
+ * Check voltage on test mode pins and drive them
+ * to the correct level. This is somewhat dangerous - we
+ * may momentarily short circuit the output driver (4mA)
+ * no short circuit will happen if the board complies
+ * to AX5051/AX5151/AX8052F151 programming manual
+ */
+ EA = 0;
+ /* check T2 */
+ AX5051_PINCFG1 = 0xC0 | pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x01;
+ /* check T1 */
+ AX5051_PINCFG1 = 0x80 | pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x04;
+ /* check TST3 */
+ AX5051_PINCFG1 = pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x08;
+ IE |= p;
+ /* check whether TST3 is connected to PR5 - if so disable pullup */
+ PORTR &= PINR | (uint8_t)~0x20;
+ IE = iesave;
+ return 0;
+}
+
diff --git a/libs/libmf/builtsource/ax5051wrfifo.c b/libs/libmf/builtsource/ax5051wrfifo.c
new file mode 100644
index 00000000..ac5cb020
--- /dev/null
+++ b/libs/libmf/builtsource/ax5051wrfifo.c
@@ -0,0 +1,89 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#define RADIO 5051
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ mov a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ clr a
+ movc a,@a+dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *(uint8_t __xdata *)(AX8052_RADIOBASE | FDATA) = *ptr++;
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16ansi.c b/libs/libmf/builtsource/crc16ansi.c
new file mode 100644
index 00000000..36f90bd5
--- /dev/null
+++ b/libs/libmf/builtsource/crc16ansi.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_crc16_byte
+#define crc_table crc_crc16_table
+#define crc_table_asm _crc_crc16_table
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_table_asm
+ add a,r2
+ mov dpl,a
+ mov a,#(crc_table_asm >> 8)
+ addc a,r3
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#1
+ movc a,@a+dptr
+ mov dph,a
+ mov dpl,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16ansib.c b/libs/libmf/builtsource/crc16ansib.c
new file mode 100644
index 00000000..b1425e33
--- /dev/null
+++ b/libs/libmf/builtsource/crc16ansib.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc16
+#define crc_byte crc_crc16_byte
+#define crc_table_asm _crc_crc16_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16ansimsb.c b/libs/libmf/builtsource/crc16ansimsb.c
new file mode 100644
index 00000000..9220c6a8
--- /dev/null
+++ b/libs/libmf/builtsource/crc16ansimsb.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_crc16_msb_byte
+#define crc_msbtable crc_crc16_msbtable
+#define crc_msbtable_asm _crc_crc16_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dph
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_msbtable_asm
+ add a,r2
+ xch a,dpl
+ mov r2,a
+ mov a,#(crc_msbtable_asm >> 8)
+ addc a,r3
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16ansimsbb.c b/libs/libmf/builtsource/crc16ansimsbb.c
new file mode 100644
index 00000000..cad0748f
--- /dev/null
+++ b/libs/libmf/builtsource/crc16ansimsbb.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc16_msb
+#define crc_byte crc_crc16_msb_byte
+#define crc_table_asm _crc_crc16_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16dnp.c b/libs/libmf/builtsource/crc16dnp.c
new file mode 100644
index 00000000..48d5f5cd
--- /dev/null
+++ b/libs/libmf/builtsource/crc16dnp.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_crc16dnp_byte
+#define crc_table crc_crc16dnp_table
+#define crc_table_asm _crc_crc16dnp_table
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_table_asm
+ add a,r2
+ mov dpl,a
+ mov a,#(crc_table_asm >> 8)
+ addc a,r3
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#1
+ movc a,@a+dptr
+ mov dph,a
+ mov dpl,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16dnpb.c b/libs/libmf/builtsource/crc16dnpb.c
new file mode 100644
index 00000000..c3d2fab1
--- /dev/null
+++ b/libs/libmf/builtsource/crc16dnpb.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc16dnp
+#define crc_byte crc_crc16dnp_byte
+#define crc_table_asm _crc_crc16dnp_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16dnpmsb.c b/libs/libmf/builtsource/crc16dnpmsb.c
new file mode 100644
index 00000000..a8a1f3ea
--- /dev/null
+++ b/libs/libmf/builtsource/crc16dnpmsb.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_crc16dnp_msb_byte
+#define crc_msbtable crc_crc16dnp_msbtable
+#define crc_msbtable_asm _crc_crc16dnp_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dph
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_msbtable_asm
+ add a,r2
+ xch a,dpl
+ mov r2,a
+ mov a,#(crc_msbtable_asm >> 8)
+ addc a,r3
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc16dnpmsbb.c b/libs/libmf/builtsource/crc16dnpmsbb.c
new file mode 100644
index 00000000..f5510132
--- /dev/null
+++ b/libs/libmf/builtsource/crc16dnpmsbb.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc16dnp_msb
+#define crc_byte crc_crc16dnp_msb_byte
+#define crc_table_asm _crc_crc16dnp_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc32ansi.c b/libs/libmf/builtsource/crc32ansi.c
new file mode 100644
index 00000000..bc9534fe
--- /dev/null
+++ b/libs/libmf/builtsource/crc32ansi.c
@@ -0,0 +1,60 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_crc32_byte
+#define crc_table crc_crc32_table
+#define crc_table_asm _crc_crc32_table
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_byte(uint32_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r4,a
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ rl a
+ rl a
+ mov r3,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ mov dpl,a
+ mov a,r3
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r4
+ mov r3,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,b
+ mov dph,a
+ mov dpl,r2
+ mov b,r3
+ mov a,r4
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_byte(uint32_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc32ansib.c b/libs/libmf/builtsource/crc32ansib.c
new file mode 100644
index 00000000..9416c23a
--- /dev/null
+++ b/libs/libmf/builtsource/crc32ansib.c
@@ -0,0 +1,326 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc32
+#define crc_byte crc_crc32_byte
+#define crc_table_asm _crc_crc32_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r6,a
+ inc r0
+ mov a,@r0
+ mov r7,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00011$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ mov b,r6
+ mov a,r7
+ ret
+
+00011$:
+ sjmp 00010$
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc32ansimsb.c b/libs/libmf/builtsource/crc32ansimsb.c
new file mode 100644
index 00000000..6080fca4
--- /dev/null
+++ b/libs/libmf/builtsource/crc32ansimsb.c
@@ -0,0 +1,61 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_crc32_msb_byte
+#define crc_msbtable crc_crc32_msbtable
+#define crc_msbtable_asm _crc_crc32_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_msb_byte(uint32_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r2,a
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,r2
+ rl a
+ rl a
+ mov r3,a
+ anl a,#0xfc
+ add a,#crc_msbtable_asm
+ xch a,dpl
+ mov r2,a
+ mov a,r3
+ anl a,#0x03
+ addc a,#(crc_msbtable_asm >> 8)
+ xch a,dph
+ mov r3,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r3
+ mov r3,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,b
+ mov r4,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ mov b,r3
+ mov a,r4
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_msb_byte(uint32_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc32ansimsbb.c b/libs/libmf/builtsource/crc32ansimsbb.c
new file mode 100644
index 00000000..1bee7eb5
--- /dev/null
+++ b/libs/libmf/builtsource/crc32ansimsbb.c
@@ -0,0 +1,326 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc32_msb
+#define crc_byte crc_crc32_msb_byte
+#define crc_table_asm _crc_crc32_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r6,a
+ inc r0
+ mov a,@r0
+ mov r7,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00011$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ mov b,r6
+ mov a,r7
+ ret
+
+00011$:
+ sjmp 00010$
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8ccittb.c b/libs/libmf/builtsource/crc8ccittb.c
new file mode 100644
index 00000000..e23158a3
--- /dev/null
+++ b/libs/libmf/builtsource/crc8ccittb.c
@@ -0,0 +1,111 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc8ccitt
+#define crc_byte crc_crc8ccitt_byte
+#define crc_table_asm _crc_crc8ccitt_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8ccittmsbb.c b/libs/libmf/builtsource/crc8ccittmsbb.c
new file mode 100644
index 00000000..9e4831e6
--- /dev/null
+++ b/libs/libmf/builtsource/crc8ccittmsbb.c
@@ -0,0 +1,111 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc8ccitt_msb
+#define crc_byte crc_crc8ccitt_msb_byte
+#define crc_table_asm _crc_crc8ccitt_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8onewireb.c b/libs/libmf/builtsource/crc8onewireb.c
new file mode 100644
index 00000000..c2788cfc
--- /dev/null
+++ b/libs/libmf/builtsource/crc8onewireb.c
@@ -0,0 +1,111 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc8onewire
+#define crc_byte crc_crc8onewire_byte
+#define crc_table_asm _crc_crc8onewire_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8onewiremsbb.c b/libs/libmf/builtsource/crc8onewiremsbb.c
new file mode 100644
index 00000000..9678b5c6
--- /dev/null
+++ b/libs/libmf/builtsource/crc8onewiremsbb.c
@@ -0,0 +1,111 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_crc8onewire_msb
+#define crc_byte crc_crc8onewire_msb_byte
+#define crc_table_asm _crc_crc8onewire_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8tccitt.c b/libs/libmf/builtsource/crc8tccitt.c
new file mode 100644
index 00000000..22e0d8d8
--- /dev/null
+++ b/libs/libmf/builtsource/crc8tccitt.c
@@ -0,0 +1,33 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_crc8ccitt_byte
+#define crc_table crc_crc8ccitt_table
+#define crc_table_asm _crc_crc8ccitt_table
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_table[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8tccittmsb.c b/libs/libmf/builtsource/crc8tccittmsb.c
new file mode 100644
index 00000000..d5c1620f
--- /dev/null
+++ b/libs/libmf/builtsource/crc8tccittmsb.c
@@ -0,0 +1,33 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_crc8ccitt_msb_byte
+#define crc_msbtable crc_crc8ccitt_msbtable
+#define crc_msbtable_asm _crc_crc8ccitt_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_msbtable_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_msbtable[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8tonewire.c b/libs/libmf/builtsource/crc8tonewire.c
new file mode 100644
index 00000000..4d24d059
--- /dev/null
+++ b/libs/libmf/builtsource/crc8tonewire.c
@@ -0,0 +1,33 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_crc8onewire_byte
+#define crc_table crc_crc8onewire_table
+#define crc_table_asm _crc_crc8onewire_table
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_table[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crc8tonewiremsb.c b/libs/libmf/builtsource/crc8tonewiremsb.c
new file mode 100644
index 00000000..819b7e68
--- /dev/null
+++ b/libs/libmf/builtsource/crc8tonewiremsb.c
@@ -0,0 +1,33 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_crc8onewire_msb_byte
+#define crc_msbtable crc_crc8onewire_msbtable
+#define crc_msbtable_asm _crc_crc8onewire_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_msbtable_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_msbtable[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crcccitt.c b/libs/libmf/builtsource/crcccitt.c
new file mode 100644
index 00000000..89b0c9dc
--- /dev/null
+++ b/libs/libmf/builtsource/crcccitt.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_byte crc_ccitt_byte
+#define crc_table crc_ccitt_table
+#define crc_table_asm _crc_ccitt_table
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_table_asm
+ add a,r2
+ mov dpl,a
+ mov a,#(crc_table_asm >> 8)
+ addc a,r3
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#1
+ movc a,@a+dptr
+ mov dph,a
+ mov dpl,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crcccittb.c b/libs/libmf/builtsource/crcccittb.c
new file mode 100644
index 00000000..9b0b8a49
--- /dev/null
+++ b/libs/libmf/builtsource/crcccittb.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_ccitt
+#define crc_byte crc_ccitt_byte
+#define crc_table_asm _crc_ccitt_table
+#define CRCMSB 0
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crcccittmsb.c b/libs/libmf/builtsource/crcccittmsb.c
new file mode 100644
index 00000000..db77abd7
--- /dev/null
+++ b/libs/libmf/builtsource/crcccittmsb.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#define crc_msb_byte crc_ccitt_msb_byte
+#define crc_msbtable crc_ccitt_msbtable
+#define crc_msbtable_asm _crc_ccitt_msbtable
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dph
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_msbtable_asm
+ add a,r2
+ xch a,dpl
+ mov r2,a
+ mov a,#(crc_msbtable_asm >> 8)
+ addc a,r3
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/builtsource/crcccittmsbb.c b/libs/libmf/builtsource/crcccittmsbb.c
new file mode 100644
index 00000000..e9d3f7d3
--- /dev/null
+++ b/libs/libmf/builtsource/crcccittmsbb.c
@@ -0,0 +1,243 @@
+#include "libmfcrc.h"
+
+#define crc_buf crc_ccitt_msb
+#define crc_byte crc_ccitt_msb_byte
+#define crc_table_asm _crc_ccitt_msbtable
+#define CRCMSB 1
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkrx.c b/libs/libmf/builtsource/dbglnkrx.c
new file mode 100644
index 00000000..7e26ab2a
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkrx.c
@@ -0,0 +1,45 @@
+#include "ax8052.h"
+
+#include "libmfdbglink.h"
+#define uart_poll dbglink_poll
+#define uart_txidle dbglink_txidle
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txdone dbglink_wait_txdone
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+__reentrantb void uart_wait_rxcount(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_rxcount() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb uint8_t uart_rx(void) __reentrant
+{
+ uint8_t x;
+ uart_wait_rxcount(1);
+ x = uart_rxpeek(0);
+ uart_rxadvance(1);
+ return x;
+}
diff --git a/libs/libmf/builtsource/dbglnkrxbuf.c b/libs/libmf/builtsource/dbglnkrxbuf.c
new file mode 100644
index 00000000..9005b863
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkrxbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfdbglink.h"
+
+DBGLINK_DEFINE_RXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/dbglnktx.c b/libs/libmf/builtsource/dbglnktx.c
new file mode 100644
index 00000000..233b2f42
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnktx.c
@@ -0,0 +1,57 @@
+#include "ax8052.h"
+
+#include "libmfdbglink.h"
+#define uart_poll dbglink_poll
+#define uart_txidle dbglink_txidle
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txdone dbglink_wait_txdone
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+__reentrantb void uart_wait_txfree(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txfree() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_wait_txdone(void) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txidle())
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_tx(uint8_t v) __reentrant
+{
+ uart_wait_txfree(1);
+ uart_txpoke(0, v);
+ uart_txadvance(1);
+}
diff --git a/libs/libmf/builtsource/dbglnktxbuf.c b/libs/libmf/builtsource/dbglnktxbuf.c
new file mode 100644
index 00000000..9e2ea649
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnktxbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfdbglink.h"
+
+DBGLINK_DEFINE_TXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/dbglnkwrhex16.c b/libs/libmf/builtsource/dbglnkwrhex16.c
new file mode 100644
index 00000000..943e7329
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrhex16.c
@@ -0,0 +1,335 @@
+#include "wrnum.h"
+
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writehex16 dbglink_writehex16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 4;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkwrhex32.c b/libs/libmf/builtsource/dbglnkwrhex32.c
new file mode 100644
index 00000000..221c5e73
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrhex32.c
@@ -0,0 +1,353 @@
+#include "wrnum.h"
+
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writehex32 dbglink_writehex32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: dec a
+ jnz 00034$
+ mov a,r7
+ sjmp 00031$
+00034$: dec a
+ jnz 00035$
+ mov a,r6
+ sjmp 00031$
+00035$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 8;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkwrhexu16.c b/libs/libmf/builtsource/dbglnkwrhexu16.c
new file mode 100644
index 00000000..02222944
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrhexu16.c
@@ -0,0 +1,30 @@
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+__reentrantb void uart_writehexu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/dbglnkwrhexu32.c b/libs/libmf/builtsource/dbglnkwrhexu32.c
new file mode 100644
index 00000000..74ab2299
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrhexu32.c
@@ -0,0 +1,30 @@
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+void uart_writehexu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/dbglnkwrnum16.c b/libs/libmf/builtsource/dbglnkwrnum16.c
new file mode 100644
index 00000000..22efbf7f
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrnum16.c
@@ -0,0 +1,305 @@
+#include "wrnum.h"
+
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writenum16 dbglink_writenum16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-4
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ mov a,r3
+ mov r4,a
+ ; val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ mov a,#ar4
+ push acc
+ lcall _libmf_num16_digit
+ dec sp
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 5;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkwrnum32.c b/libs/libmf/builtsource/dbglnkwrnum32.c
new file mode 100644
index 00000000..c20762cb
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrnum32.c
@@ -0,0 +1,345 @@
+#include "wrnum.h"
+
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writenum32 dbglink_writenum32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 9)
+ ; --nrdig;
+ ; if (nrdig > 6)
+ ; --nrdig;
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00022$
+ mov a,r2
+ add a,#-10
+ jnc 00020$
+ dec r2
+00020$: mov a,r2
+ add a,#-7
+ jnc 00021$
+ dec r2
+00021$: mov a,r2
+ add a,#-4
+ jnc 00022$
+ dec r2
+00022$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ push ar3
+ ; val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ mov a,sp
+ push b
+ push acc
+ mov b,r7
+ mov a,r6
+ lcall _libmf_num32_digit
+ mov r6,a
+ mov r7,b
+ dec sp
+ pop b
+ pop acc
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov r4,a
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00042$
+ add a,#-3
+ jz 00042$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx(' ');
+00042$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00050$
+ add a,#-3
+ jz 00050$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx('\'');
+00050$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 10;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && ((int32_t)val) < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 9)
+ --nrdig;
+ if (nrdig > 6)
+ --nrdig;
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkwrstr.c b/libs/libmf/builtsource/dbglnkwrstr.c
new file mode 100644
index 00000000..37ef9465
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwrstr.c
@@ -0,0 +1,135 @@
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define _uart_wait_txfree _dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_txbufptr dbglink_txbufptr
+#define _uart_txbufptr _dbglink_txbufptr
+#define uart_txfreelinear dbglink_txfreelinear
+#define _uart_txfreelinear _dbglink_txfreelinear
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define _uart_txadvance _dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+#if defined(SDCC)
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ ch;
+ __asm;
+ mov r0,dpl
+ mov r7,dph
+ clr a
+ mov r3,a
+ mov r2,a
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00011$ ; <0x40 far
+ jb _B_5,00012$ ; >0x60 pdata
+ ;; idata
+ mov a,@r0
+ inc r0
+ sjmp 00013$
+00010$: ;; code
+ mov dpl,r0
+ mov dph,r7
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00011$: ;; xdata
+ mov dpl,r0
+ mov dph,r7
+ movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00012$: ;; pdata
+ movx a,@r0
+ inc r0
+00013$: jz 00001$
+ mov r1,a
+ mov a,r3
+ jnz 00002$
+ mov a,r2
+ jz 00003$
+ mov dpl,a
+ lcall _uart_txadvance
+00003$: lcall _uart_txfreelinear
+ mov a,dpl
+ jnz 00004$
+ mov r4,b
+ mov dpl,#1
+ lcall _uart_wait_txfree
+ mov b,r4
+ lcall _uart_txfreelinear
+ mov a,dpl
+00004$: mov r3,a
+ clr a
+ mov r2,a
+ mov dpl,a
+ lcall _uart_txbufptr
+ mov r4,dpl
+ mov r5,dph
+00002$: mov dpl,r4
+ mov dph,r5
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov r4,dpl
+ mov r5,dph
+ inc r2
+ dec r3
+ sjmp 00000$
+00001$: mov a,r2
+ jz 00005$
+ mov dpl,a
+ lcall _uart_txadvance
+00005$:
+ __endasm;
+}
+
+#else
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ uint8_t __xdata *p;
+ uint8_t f = 0;
+ uint8_t a = 0;
+ for (;;) {
+ char c = *ch++;
+ if (!c)
+ break;
+ if (!f) {
+ if (a)
+ uart_txadvance(a);
+ f = uart_txfreelinear();
+ if (!f) {
+ uart_wait_txfree(1);
+ f = uart_txfreelinear();
+ }
+ p = uart_txbufptr(0);
+ a = 0;
+ }
+ *p++ = c;
+ ++a;
+ --f;
+ }
+ if (a)
+ uart_txadvance(a);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/dbglnkwru16.c b/libs/libmf/builtsource/dbglnkwru16.c
new file mode 100644
index 00000000..a8bb9cc4
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwru16.c
@@ -0,0 +1,32 @@
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+__reentrantb void uart_writeu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/dbglnkwru32.c b/libs/libmf/builtsource/dbglnkwru32.c
new file mode 100644
index 00000000..e0d85ee7
--- /dev/null
+++ b/libs/libmf/builtsource/dbglnkwru32.c
@@ -0,0 +1,32 @@
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+
+void uart_writeu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/lcduwrhex16.c b/libs/libmf/builtsource/lcduwrhex16.c
new file mode 100644
index 00000000..c6d3273f
--- /dev/null
+++ b/libs/libmf/builtsource/lcduwrhex16.c
@@ -0,0 +1,73 @@
+#include "wrnum.h"
+
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writehex16 lcd_writehex16
+
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 4;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
diff --git a/libs/libmf/builtsource/lcduwrhex32.c b/libs/libmf/builtsource/lcduwrhex32.c
new file mode 100644
index 00000000..b327878b
--- /dev/null
+++ b/libs/libmf/builtsource/lcduwrhex32.c
@@ -0,0 +1,73 @@
+#include "wrnum.h"
+
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writehex32 lcd_writehex32
+
+
+uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 8;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
diff --git a/libs/libmf/builtsource/lcduwrnum16.c b/libs/libmf/builtsource/lcduwrnum16.c
new file mode 100644
index 00000000..fee217f8
--- /dev/null
+++ b/libs/libmf/builtsource/lcduwrnum16.c
@@ -0,0 +1,67 @@
+#include "wrnum.h"
+
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writenum16 lcd_writenum16
+
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 5;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
diff --git a/libs/libmf/builtsource/lcduwrnum32.c b/libs/libmf/builtsource/lcduwrnum32.c
new file mode 100644
index 00000000..9849f7d9
--- /dev/null
+++ b/libs/libmf/builtsource/lcduwrnum32.c
@@ -0,0 +1,71 @@
+#include "wrnum.h"
+
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writenum32 lcd_writenum32
+
+
+uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 10;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && ((int32_t)val) < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 9)
+ --nrdig;
+ if (nrdig > 6)
+ --nrdig;
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
diff --git a/libs/libmf/builtsource/uart0init.c b/libs/libmf/builtsource/uart0init.c
new file mode 100644
index 00000000..31787b4d
--- /dev/null
+++ b/libs/libmf/builtsource/uart0init.c
@@ -0,0 +1,1039 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#include "libmfuart0.h"
+#define UARTS0 UART0S0
+#define UARTS1 UART0S1
+#define UARTS2 UART0S2
+#define UARTS3 UART0S3
+#define UARTS4 UART0S4
+#define UARTS5 UART0S5
+#define USHREG U0SHREG
+#define UMODE U0MODE
+#define UCTRL U0CTRL
+#define USTATUS U0STATUS
+#define _USHREG _U0SHREG
+#define _UMODE _U0MODE
+#define _UCTRL _U0CTRL
+#define _USTATUS _U0STATUS
+#define IRQENA EIE_4
+#define uart_irq_nr 11
+#define uart_vector_addr 0x5B
+#define uart_init uart0_init
+#define uart_stop uart0_stop
+#define uart_iocore uart0_iocore
+#define _uart_iocore _uart0_iocore
+#define uart_irq uart0_irq
+#define uart_poll uart0_poll
+#define uart_rxbufptr uart0_rxbufptr
+#define _uart_rxbufptr _uart0_rxbufptr
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txidle _uart0_txidle
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcountlinear uart0_rxcountlinear
+#define uart_rxcount uart0_rxcount
+#define uart_txbuffersize uart0_txbuffersize
+#define uart_rxbuffersize uart0_rxbuffersize
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define _uart_txpoke _uart0_txpoke
+#define uart_rxbuffer uart0_rxbuffer
+#define _uart_rxbuffer _uart0_rxbuffer
+#define uart_txbuffer uart0_txbuffer
+#define _uart_txbuffer _uart0_txbuffer
+#define _uart_buffer_size _uart0_buffer_size
+#define _uart_buffer_negsize _uart0_buffer_negsize
+#define uart_rxbuffer_size uart0_rxbuffer_size
+#define _uart_rxbuffer_size _uart0_rxbuffer_size
+#define uart_txbuffer_size uart0_txbuffer_size
+#define _uart_txbuffer_size _uart0_txbuffer_size
+#define uart_fiforxwr uart0_fiforxwr
+#define _uart_fiforxwr _uart0_fiforxwr
+#define uart_fiforxrd uart0_fiforxrd
+#define _uart_fiforxrd _uart0_fiforxrd
+#define uart_fifotxwr uart0_fifotxwr
+#define _uart_fifotxwr _uart0_fifotxwr
+#define uart_fifotxrd uart0_fifotxrd
+#define _uart_fifotxrd _uart0_fifotxrd
+
+static volatile uint8_t __data uart_fiforxwr;
+static volatile uint8_t __data uart_fiforxrd;
+static volatile uint8_t __data uart_fifotxwr;
+static volatile uint8_t __data uart_fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+#if defined(SDCC)
+
+static void dummy0(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area HOME (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) __interrupt(uart_irq_nr) __naked
+{
+ __asm;
+ push acc
+ push psw
+ push _DPS
+ push dpl
+ push dph
+ push b
+ mov _DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop _DPS
+ pop psw
+ pop acc
+ reti
+ __endasm;
+}
+
+uint8_t uart_poll(void) __reentrant __naked
+{
+ __asm;
+ mov a,#0x80
+ anl a,_IE
+ rl a
+ mov b,a
+ clr _EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov _EA,c
+ mov dpl,a
+ ret
+
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area UARTS0 (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,_USTATUS
+ jnb acc.0,iocnorx
+ mov dptr,#_uart_rxbuffer
+ mov a,_uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ mov a,#_uart_buffer_negsize+3-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fiforxwr
+ jc 00001$
+ mov a,_uart_fiforxwr
+ inc a
+00001$: cjne a,_uart_fiforxrd,00000$
+ anl _UCTRL,#~0x04
+ sjmp iocnorx
+00000$: mov _uart_fiforxwr,a
+ mov a,_USHREG
+ movx @dptr,a
+ orl _UCTRL,#0x04
+ setb _B_1
+iocnorx:
+ mov a,_USTATUS
+ jnb acc.2,iocnotx
+ mov a,_uart_fifotxrd
+ cjne a,_uart_fifotxwr,00000$
+ anl _UCTRL,#~0x08
+ sjmp iocnotx
+00000$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov _USHREG,a
+ mov a,#_uart_buffer_negsize+1-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fifotxrd
+ jc 00001$
+ mov a,_uart_fifotxrd
+ inc a
+00001$: mov _uart_fifotxrd,a
+ orl _UCTRL,#0x08
+ setb _B_2
+iocnotx:
+ ret
+ __endasm;
+}
+
+void uart_rxadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fiforxrd,a
+ orl _UCTRL,#0x04
+00000$: ret
+ __endasm;
+}
+
+void uart_txadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fifotxwr,a
+ orl _UCTRL,#0x08
+00000$: ret
+ __endasm;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_rxbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+ __endasm;
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+
+_uart_buffer_negsize:
+ .area UARTS3 (CODE)
+ __endasm;
+}
+
+uint8_t uart_txfreelinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ jnc 00000$
+ mov a,_uart_fifotxrd
+ add a,#0xff
+ cpl c
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: subb a,_uart_fifotxwr
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_txfree(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_rxcountlinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: clr c
+ subb a,_uart_fiforxrd
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxcount(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_txbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size+1-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+
+_uart_buffer_size:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+uint8_t uart_rxpeek(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ lcall _uart_rxbufptr
+ movx a,@dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+_uart_txpoke_hexentry:
+ lcall _uart_txbufptr
+ mov a,@r0
+ movx @dptr,a
+ pop ar0
+ ret
+ __endasm;
+}
+
+void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ anl a,#0x0F
+ add a,#256-10
+ jnc 00000$
+ add a,#'A-'9-1
+00000$: add a,#10+'0 ; '
+ mov @r0,a
+ ljmp _uart_txpoke_hexentry
+ __endasm;
+}
+
+uint8_t uart_txidle(void) __reentrant __naked
+{
+ __asm;
+ mov a,_UCTRL
+ jnb acc.1,00001$
+ anl a,#0x08
+ jnz 00000$
+ mov a,_USTATUS
+ anl a,#0x40
+ jz 00000$
+00001$: mov dpl,#1
+ ret
+00000$: mov dpl,#0
+ ret
+ __endasm;
+}
+
+static void wtimer_cansleep_dummy(void) __naked
+{
+ __asm
+ .area HOME (CODE)
+ .area WTCANSLP0 (CODE)
+ .area WTCANSLP1 (CODE)
+ .area WTCANSLP2 (CODE)
+
+ .area WTCANSLP1 (CODE)
+ lcall _uart_txidle
+ mov a,dpl
+ jnz 00000$
+ ret
+00000$:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) interrupt uart_irq_nr
+{
+#pragma asm
+ push acc
+ push psw
+ push DPS
+ push dpl
+ push dph
+ push b
+ mov DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop DPS
+ pop psw
+ pop acc
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant __naked
+{
+#pragma asm
+ mov a,#0x80
+ anl a,IE
+ rl a
+ mov b,a
+ clr EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov EA,c
+ mov r7,a
+#pragma endasm
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ uart_rxbuffer[0];
+ uart_rxbuffer_size[0];
+ uart_txbuffer[0];
+ uart_txbuffer_size[0];
+#pragma asm
+;ar2 equ 0x02
+;ar3 equ 0x03
+;ar4 equ 0x04
+;ar5 equ 0x05
+;ar6 equ 0x06
+;ar7 equ 0x07
+;ar0 equ 0x00
+;ar1 equ 0x01
+
+_uart_iocore:
+ mov a,USTATUS
+ jnb acc.0,iocnorx
+ clr a
+ mov dptr,#uart_rxbuffer_size+2
+ movc a,@a+dptr
+ push acc
+ mov dptr,#uart_rxbuffer
+ mov a,uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ pop acc
+ add a,uart_fiforxwr
+ jc ioc1
+ mov a,uart_fiforxwr
+ inc a
+ioc1: cjne a,uart_fiforxrd,ioc0
+ anl UCTRL,#~0x04
+ sjmp iocnorx
+ioc0: mov uart_fiforxwr,a
+ mov a,USHREG
+ movx @dptr,a
+ orl UCTRL,#0x04
+ setb B_1
+iocnorx:
+ mov a,USTATUS
+ jnb acc.2,iocnotx
+ mov a,uart_fifotxrd
+ cjne a,uart_fifotxwr,ioc2
+ anl UCTRL,#~0x08
+ sjmp iocnotx
+ioc2: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov USHREG,a
+ clr a
+ mov dptr,#uart_txbuffer_size+2
+ movc a,@a+dptr
+ add a,uart_fifotxrd
+ jc ioc3
+ mov a,uart_fifotxrd
+ inc a
+ioc3: mov uart_fifotxrd,a
+ orl UCTRL,#0x08
+ setb B_2
+iocnotx:
+#pragma endasm
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz rxad0
+ add a,uart_fiforxrd
+ jnc rxad2
+ add a,r7
+ sjmp rxad1
+rxad2: xch a,r7
+ add a,r7
+ jc rxad1
+ mov a,r7
+rxad1: mov uart_fiforxrd,a
+ orl UCTRL,#0x04
+rxad0:
+#pragma endasm
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz txad0
+ add a,uart_fifotxwr
+ jnc txad2
+ add a,r7
+ sjmp txad1
+txad2: xch a,r7
+ add a,r7
+ jc txad1
+ mov a,r7
+txad1: mov uart_fifotxwr,a
+ orl UCTRL,#0x08
+txad0:
+#pragma endasm
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_rxbufptr:
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fiforxrd
+ jnc rxp2
+ add a,r7
+ sjmp rxp1
+rxp2: xch a,r7
+ add a,r7
+ jc rxp1
+ mov a,r7
+rxp1: mov dptr,#uart_rxbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_txbufptr:
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fifotxwr
+ jnc txp2
+ add a,r7
+ sjmp txp1
+txp2: xch a,r7
+ add a,r7
+ jc txp1
+ mov a,r7
+txp1: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfrl0
+ mov a,uart_fifotxrd
+ add a,#0xff
+ cpl c
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ subb a,uart_fifotxwr
+txfrl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfr0
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+txfr0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ jnc rxcl0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ clr c
+ subb a,uart_fiforxrd
+rxcl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ mov r7,a
+ jnc rxc0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+rxc0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ lcall _uart_rxbufptr
+ mov dpl,r7
+ mov dph,r6
+ movx a,@dptr
+ mov r7,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+_uart_txpokehex_entry:
+ lcall _uart_txbufptr
+ mov dpl,r7
+ mov dph,r6
+ mov a,r5
+ movx @dptr,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+ mov a,r5
+ anl a,#0x0F
+ add a,#256-10
+ jnc txph0
+ add a,#'A'-'9'-1
+txph0: add a,#10+'0'
+ mov r5,a
+ ljmp _uart_txpokehex_entry
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+#pragma asm
+ mov r7,#0
+ mov a,UCTRL
+ jnb acc.1,txidle
+ anl a,#0x08
+ jnz txnotidle
+ mov a,USTATUS
+ anl a,#0x40
+ jz txnotidle
+txidle:
+ mov r7,#1
+txnotidle:
+#pragma endasm
+}
+
+#elif defined __ICC8051__
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant;
+
+#pragma vector=uart_vector_addr
+__interrupt void uart_irq(void)
+{
+ uint8_t __autodata dpssave = DPS;
+ DPS = 0;
+ uart_iocore();
+ DPS = dpssave;
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant
+{
+ uint8_t flg;
+ uint8_t irq = IE & 0x80;
+ EA = 0;
+ flg = uart_iocore();
+ IE |= irq;
+ return flg;
+}
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant
+{
+ uint8_t flg = 0;
+ if (USTATUS & 0x01) {
+ uint8_t wp = uart_fiforxwr + 1;
+ uint8_t sz = uart_rxbuffer_size[0];
+ if (wp >= sz)
+ wp -= sz;
+ if (wp != uart_fiforxrd) {
+ uart_rxbuffer[uart_fiforxwr] = USHREG;
+ uart_fiforxwr = wp;
+ UCTRL |= 0x04;
+ flg |= 1;
+ } else {
+ UCTRL &= (uint8_t)~0x04;
+ }
+ }
+ if (USTATUS & 0x04) {
+ if (uart_fifotxrd != uart_fifotxwr) {
+ uint8_t rp = uart_fifotxrd + 1;
+ uint8_t sz = uart_txbuffer_size[0];
+ USHREG = uart_txbuffer[uart_fifotxrd];
+ if (rp >= sz)
+ rp -= sz;
+ uart_fifotxrd = rp;
+ UCTRL |= 0x08;
+ flg |= 2;
+ } else {
+ UCTRL &= (uint8_t)~0x08;
+ }
+ }
+ return flg;
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ uint8_t rd;
+ uint8_t sz;
+ if (!idx)
+ return;
+ rd = uart_fiforxrd;
+ idx += rd;
+ sz = uart_rxbuffer_size[0];
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ uart_fiforxrd = idx;
+ UCTRL |= 0x04;
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ uint8_t wr;
+ uint8_t sz;
+ if (!idx)
+ return;
+ wr = uart_fifotxwr;
+ idx += wr;
+ sz = uart_txbuffer_size[0];
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ uart_fifotxwr = idx;
+ UCTRL |= 0x08;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t sz = uart_rxbuffer_size[0];
+ idx += rd;
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ return &uart_rxbuffer[idx];
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ uint8_t wr = uart_fifotxwr;
+ uint8_t sz = uart_txbuffer_size[0];
+ idx += wr;
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ return &uart_txbuffer[idx];
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ if (rd <= wr) {
+ uint8_t r = uart_txbuffer_size[0] - wr;
+ if (!rd)
+ --r;
+ return r;
+ }
+ return rd - wr - 1;
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ uint8_t r = rd - wr;
+ if (rd <= wr)
+ r += uart_txbuffer_size[0];
+ --r;
+ return r;
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ if (wr < rd)
+ return uart_rxbuffer_size[0] - rd;
+ return wr - rd;
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ uint8_t r = wr - rd;
+ if (wr < rd)
+ r += uart_rxbuffer_size[0];
+ return r;
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ const uint8_t __xdata *bp = uart_rxbufptr(idx);
+ return *bp;
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ uint8_t __xdata *bp = uart_txbufptr(idx);
+ *bp = ch;
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ ch &= 0x0F;
+ if (ch >= 10)
+ ch += 'A' - '9' - 1;
+ ch += '0';
+ uart_txpoke(idx, ch);
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+ if (!(UCTRL & 0x02))
+ return 1;
+ if ((UCTRL & 0x08) || !(USTATUS & 0x40))
+ return 0;
+ return 1;
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
+
+void uart_init(uint8_t timernr, uint8_t wl, uint8_t stop)
+{
+ uart_fiforxwr = uart_fiforxrd = uart_fifotxwr = uart_fifotxrd = 0;
+ UMODE = ((timernr + 1) & 3) | ((wl & 7) << 2) | ((stop >= 2) << 5) | 0x40;
+ UCTRL = 0x07;
+ IRQENA = 1;
+}
diff --git a/libs/libmf/builtsource/uart0rx.c b/libs/libmf/builtsource/uart0rx.c
new file mode 100644
index 00000000..43fb7772
--- /dev/null
+++ b/libs/libmf/builtsource/uart0rx.c
@@ -0,0 +1,45 @@
+#include "ax8052.h"
+
+#include "libmfuart0.h"
+#define uart_poll uart0_poll
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txdone uart0_wait_txdone
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+__reentrantb void uart_wait_rxcount(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_rxcount() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb uint8_t uart_rx(void) __reentrant
+{
+ uint8_t x;
+ uart_wait_rxcount(1);
+ x = uart_rxpeek(0);
+ uart_rxadvance(1);
+ return x;
+}
diff --git a/libs/libmf/builtsource/uart0rxbuf.c b/libs/libmf/builtsource/uart0rxbuf.c
new file mode 100644
index 00000000..61d0be7a
--- /dev/null
+++ b/libs/libmf/builtsource/uart0rxbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfuart0.h"
+
+UART0_DEFINE_RXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/uart0stop.c b/libs/libmf/builtsource/uart0stop.c
new file mode 100644
index 00000000..dc68aced
--- /dev/null
+++ b/libs/libmf/builtsource/uart0stop.c
@@ -0,0 +1,79 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#include "libmfuart0.h"
+#define UARTS0 UART0S0
+#define UARTS1 UART0S1
+#define UARTS2 UART0S2
+#define UARTS3 UART0S3
+#define UARTS4 UART0S4
+#define UARTS5 UART0S5
+#define USHREG U0SHREG
+#define UMODE U0MODE
+#define UCTRL U0CTRL
+#define USTATUS U0STATUS
+#define _USHREG _U0SHREG
+#define _UMODE _U0MODE
+#define _UCTRL _U0CTRL
+#define _USTATUS _U0STATUS
+#define IRQENA EIE_4
+#define uart_irq_nr 11
+#define uart_vector_addr 0x5B
+#define uart_init uart0_init
+#define uart_stop uart0_stop
+#define uart_iocore uart0_iocore
+#define _uart_iocore _uart0_iocore
+#define uart_irq uart0_irq
+#define uart_poll uart0_poll
+#define uart_rxbufptr uart0_rxbufptr
+#define _uart_rxbufptr _uart0_rxbufptr
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txidle _uart0_txidle
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcountlinear uart0_rxcountlinear
+#define uart_rxcount uart0_rxcount
+#define uart_txbuffersize uart0_txbuffersize
+#define uart_rxbuffersize uart0_rxbuffersize
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define _uart_txpoke _uart0_txpoke
+#define uart_rxbuffer uart0_rxbuffer
+#define _uart_rxbuffer _uart0_rxbuffer
+#define uart_txbuffer uart0_txbuffer
+#define _uart_txbuffer _uart0_txbuffer
+#define _uart_buffer_size _uart0_buffer_size
+#define _uart_buffer_negsize _uart0_buffer_negsize
+#define uart_rxbuffer_size uart0_rxbuffer_size
+#define _uart_rxbuffer_size _uart0_rxbuffer_size
+#define uart_txbuffer_size uart0_txbuffer_size
+#define _uart_txbuffer_size _uart0_txbuffer_size
+
+static volatile uint8_t __data fiforxwr;
+static volatile uint8_t __data fiforxrd;
+static volatile uint8_t __data fifotxwr;
+static volatile uint8_t __data fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+void uart_stop(void)
+{
+ IRQENA = 0;
+ UMODE = 0;
+ UCTRL = 0;
+}
diff --git a/libs/libmf/builtsource/uart0tx.c b/libs/libmf/builtsource/uart0tx.c
new file mode 100644
index 00000000..a9b2c5ae
--- /dev/null
+++ b/libs/libmf/builtsource/uart0tx.c
@@ -0,0 +1,57 @@
+#include "ax8052.h"
+
+#include "libmfuart0.h"
+#define uart_poll uart0_poll
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txdone uart0_wait_txdone
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+__reentrantb void uart_wait_txfree(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txfree() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_wait_txdone(void) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txidle())
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_tx(uint8_t v) __reentrant
+{
+ uart_wait_txfree(1);
+ uart_txpoke(0, v);
+ uart_txadvance(1);
+}
diff --git a/libs/libmf/builtsource/uart0txbuf.c b/libs/libmf/builtsource/uart0txbuf.c
new file mode 100644
index 00000000..3c2e73c1
--- /dev/null
+++ b/libs/libmf/builtsource/uart0txbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfuart0.h"
+
+UART0_DEFINE_TXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/uart0wrhex16.c b/libs/libmf/builtsource/uart0wrhex16.c
new file mode 100644
index 00000000..00c8e8c3
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrhex16.c
@@ -0,0 +1,335 @@
+#include "wrnum.h"
+
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writehex16 uart0_writehex16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 4;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart0wrhex32.c b/libs/libmf/builtsource/uart0wrhex32.c
new file mode 100644
index 00000000..90404fe5
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrhex32.c
@@ -0,0 +1,353 @@
+#include "wrnum.h"
+
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writehex32 uart0_writehex32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: dec a
+ jnz 00034$
+ mov a,r7
+ sjmp 00031$
+00034$: dec a
+ jnz 00035$
+ mov a,r6
+ sjmp 00031$
+00035$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 8;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart0wrhexu16.c b/libs/libmf/builtsource/uart0wrhexu16.c
new file mode 100644
index 00000000..61e2acbb
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrhexu16.c
@@ -0,0 +1,30 @@
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+__reentrantb void uart_writehexu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart0wrhexu32.c b/libs/libmf/builtsource/uart0wrhexu32.c
new file mode 100644
index 00000000..e98ec384
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrhexu32.c
@@ -0,0 +1,30 @@
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+void uart_writehexu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart0wrnum16.c b/libs/libmf/builtsource/uart0wrnum16.c
new file mode 100644
index 00000000..1ab125f5
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrnum16.c
@@ -0,0 +1,305 @@
+#include "wrnum.h"
+
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writenum16 uart0_writenum16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-4
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ mov a,r3
+ mov r4,a
+ ; val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ mov a,#ar4
+ push acc
+ lcall _libmf_num16_digit
+ dec sp
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 5;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart0wrnum32.c b/libs/libmf/builtsource/uart0wrnum32.c
new file mode 100644
index 00000000..e1d6ea3b
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrnum32.c
@@ -0,0 +1,345 @@
+#include "wrnum.h"
+
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writenum32 uart0_writenum32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 9)
+ ; --nrdig;
+ ; if (nrdig > 6)
+ ; --nrdig;
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00022$
+ mov a,r2
+ add a,#-10
+ jnc 00020$
+ dec r2
+00020$: mov a,r2
+ add a,#-7
+ jnc 00021$
+ dec r2
+00021$: mov a,r2
+ add a,#-4
+ jnc 00022$
+ dec r2
+00022$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ push ar3
+ ; val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ mov a,sp
+ push b
+ push acc
+ mov b,r7
+ mov a,r6
+ lcall _libmf_num32_digit
+ mov r6,a
+ mov r7,b
+ dec sp
+ pop b
+ pop acc
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov r4,a
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00042$
+ add a,#-3
+ jz 00042$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx(' ');
+00042$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00050$
+ add a,#-3
+ jz 00050$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx('\'');
+00050$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 10;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && ((int32_t)val) < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 9)
+ --nrdig;
+ if (nrdig > 6)
+ --nrdig;
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart0wrstr.c b/libs/libmf/builtsource/uart0wrstr.c
new file mode 100644
index 00000000..0194b431
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wrstr.c
@@ -0,0 +1,135 @@
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define _uart_wait_txfree _uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txfreelinear _uart0_txfreelinear
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define _uart_txadvance _uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+#if defined(SDCC)
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ ch;
+ __asm;
+ mov r0,dpl
+ mov r7,dph
+ clr a
+ mov r3,a
+ mov r2,a
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00011$ ; <0x40 far
+ jb _B_5,00012$ ; >0x60 pdata
+ ;; idata
+ mov a,@r0
+ inc r0
+ sjmp 00013$
+00010$: ;; code
+ mov dpl,r0
+ mov dph,r7
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00011$: ;; xdata
+ mov dpl,r0
+ mov dph,r7
+ movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00012$: ;; pdata
+ movx a,@r0
+ inc r0
+00013$: jz 00001$
+ mov r1,a
+ mov a,r3
+ jnz 00002$
+ mov a,r2
+ jz 00003$
+ mov dpl,a
+ lcall _uart_txadvance
+00003$: lcall _uart_txfreelinear
+ mov a,dpl
+ jnz 00004$
+ mov r4,b
+ mov dpl,#1
+ lcall _uart_wait_txfree
+ mov b,r4
+ lcall _uart_txfreelinear
+ mov a,dpl
+00004$: mov r3,a
+ clr a
+ mov r2,a
+ mov dpl,a
+ lcall _uart_txbufptr
+ mov r4,dpl
+ mov r5,dph
+00002$: mov dpl,r4
+ mov dph,r5
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov r4,dpl
+ mov r5,dph
+ inc r2
+ dec r3
+ sjmp 00000$
+00001$: mov a,r2
+ jz 00005$
+ mov dpl,a
+ lcall _uart_txadvance
+00005$:
+ __endasm;
+}
+
+#else
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ uint8_t __xdata *p;
+ uint8_t f = 0;
+ uint8_t a = 0;
+ for (;;) {
+ char c = *ch++;
+ if (!c)
+ break;
+ if (!f) {
+ if (a)
+ uart_txadvance(a);
+ f = uart_txfreelinear();
+ if (!f) {
+ uart_wait_txfree(1);
+ f = uart_txfreelinear();
+ }
+ p = uart_txbufptr(0);
+ a = 0;
+ }
+ *p++ = c;
+ ++a;
+ --f;
+ }
+ if (a)
+ uart_txadvance(a);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart0wru16.c b/libs/libmf/builtsource/uart0wru16.c
new file mode 100644
index 00000000..f925388a
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wru16.c
@@ -0,0 +1,32 @@
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+__reentrantb void uart_writeu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart0wru32.c b/libs/libmf/builtsource/uart0wru32.c
new file mode 100644
index 00000000..c067436d
--- /dev/null
+++ b/libs/libmf/builtsource/uart0wru32.c
@@ -0,0 +1,32 @@
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+
+void uart_writeu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart1init.c b/libs/libmf/builtsource/uart1init.c
new file mode 100644
index 00000000..4c915787
--- /dev/null
+++ b/libs/libmf/builtsource/uart1init.c
@@ -0,0 +1,1039 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#include "libmfuart1.h"
+#define UARTS0 UART1S0
+#define UARTS1 UART1S1
+#define UARTS2 UART1S2
+#define UARTS3 UART1S3
+#define UARTS4 UART1S4
+#define UARTS5 UART1S5
+#define USHREG U1SHREG
+#define UMODE U1MODE
+#define UCTRL U1CTRL
+#define USTATUS U1STATUS
+#define _USHREG _U1SHREG
+#define _UMODE _U1MODE
+#define _UCTRL _U1CTRL
+#define _USTATUS _U1STATUS
+#define IRQENA EIE_5
+#define uart_irq_nr 12
+#define uart_vector_addr 0x63
+#define uart_init uart1_init
+#define uart_stop uart1_stop
+#define uart_iocore uart1_iocore
+#define _uart_iocore _uart1_iocore
+#define uart_irq uart1_irq
+#define uart_poll uart1_poll
+#define uart_rxbufptr uart1_rxbufptr
+#define _uart_rxbufptr _uart1_rxbufptr
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txidle _uart1_txidle
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcountlinear uart1_rxcountlinear
+#define uart_rxcount uart1_rxcount
+#define uart_txbuffersize uart1_txbuffersize
+#define uart_rxbuffersize uart1_rxbuffersize
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define _uart_txpoke _uart1_txpoke
+#define uart_rxbuffer uart1_rxbuffer
+#define _uart_rxbuffer _uart1_rxbuffer
+#define uart_txbuffer uart1_txbuffer
+#define _uart_txbuffer _uart1_txbuffer
+#define _uart_buffer_size _uart1_buffer_size
+#define _uart_buffer_negsize _uart1_buffer_negsize
+#define uart_rxbuffer_size uart1_rxbuffer_size
+#define _uart_rxbuffer_size _uart1_rxbuffer_size
+#define uart_txbuffer_size uart1_txbuffer_size
+#define _uart_txbuffer_size _uart1_txbuffer_size
+#define uart_fiforxwr uart1_fiforxwr
+#define _uart_fiforxwr _uart1_fiforxwr
+#define uart_fiforxrd uart1_fiforxrd
+#define _uart_fiforxrd _uart1_fiforxrd
+#define uart_fifotxwr uart1_fifotxwr
+#define _uart_fifotxwr _uart1_fifotxwr
+#define uart_fifotxrd uart1_fifotxrd
+#define _uart_fifotxrd _uart1_fifotxrd
+
+static volatile uint8_t __data uart_fiforxwr;
+static volatile uint8_t __data uart_fiforxrd;
+static volatile uint8_t __data uart_fifotxwr;
+static volatile uint8_t __data uart_fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+#if defined(SDCC)
+
+static void dummy0(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area HOME (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) __interrupt(uart_irq_nr) __naked
+{
+ __asm;
+ push acc
+ push psw
+ push _DPS
+ push dpl
+ push dph
+ push b
+ mov _DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop _DPS
+ pop psw
+ pop acc
+ reti
+ __endasm;
+}
+
+uint8_t uart_poll(void) __reentrant __naked
+{
+ __asm;
+ mov a,#0x80
+ anl a,_IE
+ rl a
+ mov b,a
+ clr _EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov _EA,c
+ mov dpl,a
+ ret
+
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area UARTS0 (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,_USTATUS
+ jnb acc.0,iocnorx
+ mov dptr,#_uart_rxbuffer
+ mov a,_uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ mov a,#_uart_buffer_negsize+3-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fiforxwr
+ jc 00001$
+ mov a,_uart_fiforxwr
+ inc a
+00001$: cjne a,_uart_fiforxrd,00000$
+ anl _UCTRL,#~0x04
+ sjmp iocnorx
+00000$: mov _uart_fiforxwr,a
+ mov a,_USHREG
+ movx @dptr,a
+ orl _UCTRL,#0x04
+ setb _B_1
+iocnorx:
+ mov a,_USTATUS
+ jnb acc.2,iocnotx
+ mov a,_uart_fifotxrd
+ cjne a,_uart_fifotxwr,00000$
+ anl _UCTRL,#~0x08
+ sjmp iocnotx
+00000$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov _USHREG,a
+ mov a,#_uart_buffer_negsize+1-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fifotxrd
+ jc 00001$
+ mov a,_uart_fifotxrd
+ inc a
+00001$: mov _uart_fifotxrd,a
+ orl _UCTRL,#0x08
+ setb _B_2
+iocnotx:
+ ret
+ __endasm;
+}
+
+void uart_rxadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fiforxrd,a
+ orl _UCTRL,#0x04
+00000$: ret
+ __endasm;
+}
+
+void uart_txadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fifotxwr,a
+ orl _UCTRL,#0x08
+00000$: ret
+ __endasm;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_rxbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+ __endasm;
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+
+_uart_buffer_negsize:
+ .area UARTS3 (CODE)
+ __endasm;
+}
+
+uint8_t uart_txfreelinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ jnc 00000$
+ mov a,_uart_fifotxrd
+ add a,#0xff
+ cpl c
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: subb a,_uart_fifotxwr
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_txfree(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_rxcountlinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: clr c
+ subb a,_uart_fiforxrd
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxcount(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_txbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size+1-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+
+_uart_buffer_size:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+uint8_t uart_rxpeek(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ lcall _uart_rxbufptr
+ movx a,@dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+_uart_txpoke_hexentry:
+ lcall _uart_txbufptr
+ mov a,@r0
+ movx @dptr,a
+ pop ar0
+ ret
+ __endasm;
+}
+
+void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ anl a,#0x0F
+ add a,#256-10
+ jnc 00000$
+ add a,#'A-'9-1
+00000$: add a,#10+'0 ; '
+ mov @r0,a
+ ljmp _uart_txpoke_hexentry
+ __endasm;
+}
+
+uint8_t uart_txidle(void) __reentrant __naked
+{
+ __asm;
+ mov a,_UCTRL
+ jnb acc.1,00001$
+ anl a,#0x08
+ jnz 00000$
+ mov a,_USTATUS
+ anl a,#0x40
+ jz 00000$
+00001$: mov dpl,#1
+ ret
+00000$: mov dpl,#0
+ ret
+ __endasm;
+}
+
+static void wtimer_cansleep_dummy(void) __naked
+{
+ __asm
+ .area HOME (CODE)
+ .area WTCANSLP0 (CODE)
+ .area WTCANSLP1 (CODE)
+ .area WTCANSLP2 (CODE)
+
+ .area WTCANSLP1 (CODE)
+ lcall _uart_txidle
+ mov a,dpl
+ jnz 00000$
+ ret
+00000$:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) interrupt uart_irq_nr
+{
+#pragma asm
+ push acc
+ push psw
+ push DPS
+ push dpl
+ push dph
+ push b
+ mov DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop DPS
+ pop psw
+ pop acc
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant __naked
+{
+#pragma asm
+ mov a,#0x80
+ anl a,IE
+ rl a
+ mov b,a
+ clr EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov EA,c
+ mov r7,a
+#pragma endasm
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ uart_rxbuffer[0];
+ uart_rxbuffer_size[0];
+ uart_txbuffer[0];
+ uart_txbuffer_size[0];
+#pragma asm
+;ar2 equ 0x02
+;ar3 equ 0x03
+;ar4 equ 0x04
+;ar5 equ 0x05
+;ar6 equ 0x06
+;ar7 equ 0x07
+;ar0 equ 0x00
+;ar1 equ 0x01
+
+_uart_iocore:
+ mov a,USTATUS
+ jnb acc.0,iocnorx
+ clr a
+ mov dptr,#uart_rxbuffer_size+2
+ movc a,@a+dptr
+ push acc
+ mov dptr,#uart_rxbuffer
+ mov a,uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ pop acc
+ add a,uart_fiforxwr
+ jc ioc1
+ mov a,uart_fiforxwr
+ inc a
+ioc1: cjne a,uart_fiforxrd,ioc0
+ anl UCTRL,#~0x04
+ sjmp iocnorx
+ioc0: mov uart_fiforxwr,a
+ mov a,USHREG
+ movx @dptr,a
+ orl UCTRL,#0x04
+ setb B_1
+iocnorx:
+ mov a,USTATUS
+ jnb acc.2,iocnotx
+ mov a,uart_fifotxrd
+ cjne a,uart_fifotxwr,ioc2
+ anl UCTRL,#~0x08
+ sjmp iocnotx
+ioc2: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov USHREG,a
+ clr a
+ mov dptr,#uart_txbuffer_size+2
+ movc a,@a+dptr
+ add a,uart_fifotxrd
+ jc ioc3
+ mov a,uart_fifotxrd
+ inc a
+ioc3: mov uart_fifotxrd,a
+ orl UCTRL,#0x08
+ setb B_2
+iocnotx:
+#pragma endasm
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz rxad0
+ add a,uart_fiforxrd
+ jnc rxad2
+ add a,r7
+ sjmp rxad1
+rxad2: xch a,r7
+ add a,r7
+ jc rxad1
+ mov a,r7
+rxad1: mov uart_fiforxrd,a
+ orl UCTRL,#0x04
+rxad0:
+#pragma endasm
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz txad0
+ add a,uart_fifotxwr
+ jnc txad2
+ add a,r7
+ sjmp txad1
+txad2: xch a,r7
+ add a,r7
+ jc txad1
+ mov a,r7
+txad1: mov uart_fifotxwr,a
+ orl UCTRL,#0x08
+txad0:
+#pragma endasm
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_rxbufptr:
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fiforxrd
+ jnc rxp2
+ add a,r7
+ sjmp rxp1
+rxp2: xch a,r7
+ add a,r7
+ jc rxp1
+ mov a,r7
+rxp1: mov dptr,#uart_rxbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_txbufptr:
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fifotxwr
+ jnc txp2
+ add a,r7
+ sjmp txp1
+txp2: xch a,r7
+ add a,r7
+ jc txp1
+ mov a,r7
+txp1: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfrl0
+ mov a,uart_fifotxrd
+ add a,#0xff
+ cpl c
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ subb a,uart_fifotxwr
+txfrl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfr0
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+txfr0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ jnc rxcl0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ clr c
+ subb a,uart_fiforxrd
+rxcl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ mov r7,a
+ jnc rxc0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+rxc0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ lcall _uart_rxbufptr
+ mov dpl,r7
+ mov dph,r6
+ movx a,@dptr
+ mov r7,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+_uart_txpokehex_entry:
+ lcall _uart_txbufptr
+ mov dpl,r7
+ mov dph,r6
+ mov a,r5
+ movx @dptr,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+ mov a,r5
+ anl a,#0x0F
+ add a,#256-10
+ jnc txph0
+ add a,#'A'-'9'-1
+txph0: add a,#10+'0'
+ mov r5,a
+ ljmp _uart_txpokehex_entry
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+#pragma asm
+ mov r7,#0
+ mov a,UCTRL
+ jnb acc.1,txidle
+ anl a,#0x08
+ jnz txnotidle
+ mov a,USTATUS
+ anl a,#0x40
+ jz txnotidle
+txidle:
+ mov r7,#1
+txnotidle:
+#pragma endasm
+}
+
+#elif defined __ICC8051__
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant;
+
+#pragma vector=uart_vector_addr
+__interrupt void uart_irq(void)
+{
+ uint8_t __autodata dpssave = DPS;
+ DPS = 0;
+ uart_iocore();
+ DPS = dpssave;
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant
+{
+ uint8_t flg;
+ uint8_t irq = IE & 0x80;
+ EA = 0;
+ flg = uart_iocore();
+ IE |= irq;
+ return flg;
+}
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant
+{
+ uint8_t flg = 0;
+ if (USTATUS & 0x01) {
+ uint8_t wp = uart_fiforxwr + 1;
+ uint8_t sz = uart_rxbuffer_size[0];
+ if (wp >= sz)
+ wp -= sz;
+ if (wp != uart_fiforxrd) {
+ uart_rxbuffer[uart_fiforxwr] = USHREG;
+ uart_fiforxwr = wp;
+ UCTRL |= 0x04;
+ flg |= 1;
+ } else {
+ UCTRL &= (uint8_t)~0x04;
+ }
+ }
+ if (USTATUS & 0x04) {
+ if (uart_fifotxrd != uart_fifotxwr) {
+ uint8_t rp = uart_fifotxrd + 1;
+ uint8_t sz = uart_txbuffer_size[0];
+ USHREG = uart_txbuffer[uart_fifotxrd];
+ if (rp >= sz)
+ rp -= sz;
+ uart_fifotxrd = rp;
+ UCTRL |= 0x08;
+ flg |= 2;
+ } else {
+ UCTRL &= (uint8_t)~0x08;
+ }
+ }
+ return flg;
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ uint8_t rd;
+ uint8_t sz;
+ if (!idx)
+ return;
+ rd = uart_fiforxrd;
+ idx += rd;
+ sz = uart_rxbuffer_size[0];
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ uart_fiforxrd = idx;
+ UCTRL |= 0x04;
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ uint8_t wr;
+ uint8_t sz;
+ if (!idx)
+ return;
+ wr = uart_fifotxwr;
+ idx += wr;
+ sz = uart_txbuffer_size[0];
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ uart_fifotxwr = idx;
+ UCTRL |= 0x08;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t sz = uart_rxbuffer_size[0];
+ idx += rd;
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ return &uart_rxbuffer[idx];
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ uint8_t wr = uart_fifotxwr;
+ uint8_t sz = uart_txbuffer_size[0];
+ idx += wr;
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ return &uart_txbuffer[idx];
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ if (rd <= wr) {
+ uint8_t r = uart_txbuffer_size[0] - wr;
+ if (!rd)
+ --r;
+ return r;
+ }
+ return rd - wr - 1;
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ uint8_t r = rd - wr;
+ if (rd <= wr)
+ r += uart_txbuffer_size[0];
+ --r;
+ return r;
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ if (wr < rd)
+ return uart_rxbuffer_size[0] - rd;
+ return wr - rd;
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ uint8_t r = wr - rd;
+ if (wr < rd)
+ r += uart_rxbuffer_size[0];
+ return r;
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ const uint8_t __xdata *bp = uart_rxbufptr(idx);
+ return *bp;
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ uint8_t __xdata *bp = uart_txbufptr(idx);
+ *bp = ch;
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ ch &= 0x0F;
+ if (ch >= 10)
+ ch += 'A' - '9' - 1;
+ ch += '0';
+ uart_txpoke(idx, ch);
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+ if (!(UCTRL & 0x02))
+ return 1;
+ if ((UCTRL & 0x08) || !(USTATUS & 0x40))
+ return 0;
+ return 1;
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
+
+void uart_init(uint8_t timernr, uint8_t wl, uint8_t stop)
+{
+ uart_fiforxwr = uart_fiforxrd = uart_fifotxwr = uart_fifotxrd = 0;
+ UMODE = ((timernr + 1) & 3) | ((wl & 7) << 2) | ((stop >= 2) << 5) | 0x40;
+ UCTRL = 0x07;
+ IRQENA = 1;
+}
diff --git a/libs/libmf/builtsource/uart1rx.c b/libs/libmf/builtsource/uart1rx.c
new file mode 100644
index 00000000..ff734aff
--- /dev/null
+++ b/libs/libmf/builtsource/uart1rx.c
@@ -0,0 +1,45 @@
+#include "ax8052.h"
+
+#include "libmfuart1.h"
+#define uart_poll uart1_poll
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txdone uart1_wait_txdone
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+__reentrantb void uart_wait_rxcount(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_rxcount() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb uint8_t uart_rx(void) __reentrant
+{
+ uint8_t x;
+ uart_wait_rxcount(1);
+ x = uart_rxpeek(0);
+ uart_rxadvance(1);
+ return x;
+}
diff --git a/libs/libmf/builtsource/uart1rxbuf.c b/libs/libmf/builtsource/uart1rxbuf.c
new file mode 100644
index 00000000..8f767b09
--- /dev/null
+++ b/libs/libmf/builtsource/uart1rxbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfuart1.h"
+
+UART1_DEFINE_RXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/uart1stop.c b/libs/libmf/builtsource/uart1stop.c
new file mode 100644
index 00000000..b9c9df80
--- /dev/null
+++ b/libs/libmf/builtsource/uart1stop.c
@@ -0,0 +1,79 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#include "libmfuart1.h"
+#define UARTS0 UART1S0
+#define UARTS1 UART1S1
+#define UARTS2 UART1S2
+#define UARTS3 UART1S3
+#define UARTS4 UART1S4
+#define UARTS5 UART1S5
+#define USHREG U1SHREG
+#define UMODE U1MODE
+#define UCTRL U1CTRL
+#define USTATUS U1STATUS
+#define _USHREG _U1SHREG
+#define _UMODE _U1MODE
+#define _UCTRL _U1CTRL
+#define _USTATUS _U1STATUS
+#define IRQENA EIE_5
+#define uart_irq_nr 12
+#define uart_vector_addr 0x63
+#define uart_init uart1_init
+#define uart_stop uart1_stop
+#define uart_iocore uart1_iocore
+#define _uart_iocore _uart1_iocore
+#define uart_irq uart1_irq
+#define uart_poll uart1_poll
+#define uart_rxbufptr uart1_rxbufptr
+#define _uart_rxbufptr _uart1_rxbufptr
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txidle _uart1_txidle
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcountlinear uart1_rxcountlinear
+#define uart_rxcount uart1_rxcount
+#define uart_txbuffersize uart1_txbuffersize
+#define uart_rxbuffersize uart1_rxbuffersize
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define _uart_txpoke _uart1_txpoke
+#define uart_rxbuffer uart1_rxbuffer
+#define _uart_rxbuffer _uart1_rxbuffer
+#define uart_txbuffer uart1_txbuffer
+#define _uart_txbuffer _uart1_txbuffer
+#define _uart_buffer_size _uart1_buffer_size
+#define _uart_buffer_negsize _uart1_buffer_negsize
+#define uart_rxbuffer_size uart1_rxbuffer_size
+#define _uart_rxbuffer_size _uart1_rxbuffer_size
+#define uart_txbuffer_size uart1_txbuffer_size
+#define _uart_txbuffer_size _uart1_txbuffer_size
+
+static volatile uint8_t __data fiforxwr;
+static volatile uint8_t __data fiforxrd;
+static volatile uint8_t __data fifotxwr;
+static volatile uint8_t __data fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+void uart_stop(void)
+{
+ IRQENA = 0;
+ UMODE = 0;
+ UCTRL = 0;
+}
diff --git a/libs/libmf/builtsource/uart1tx.c b/libs/libmf/builtsource/uart1tx.c
new file mode 100644
index 00000000..da74e943
--- /dev/null
+++ b/libs/libmf/builtsource/uart1tx.c
@@ -0,0 +1,57 @@
+#include "ax8052.h"
+
+#include "libmfuart1.h"
+#define uart_poll uart1_poll
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txdone uart1_wait_txdone
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+__reentrantb void uart_wait_txfree(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txfree() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_wait_txdone(void) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txidle())
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_tx(uint8_t v) __reentrant
+{
+ uart_wait_txfree(1);
+ uart_txpoke(0, v);
+ uart_txadvance(1);
+}
diff --git a/libs/libmf/builtsource/uart1txbuf.c b/libs/libmf/builtsource/uart1txbuf.c
new file mode 100644
index 00000000..31e92023
--- /dev/null
+++ b/libs/libmf/builtsource/uart1txbuf.c
@@ -0,0 +1,6 @@
+#include "ax8052.h"
+
+#include "libmfuart1.h"
+
+UART1_DEFINE_TXBUFFER(64)
+
diff --git a/libs/libmf/builtsource/uart1wrhex16.c b/libs/libmf/builtsource/uart1wrhex16.c
new file mode 100644
index 00000000..2e468f9e
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrhex16.c
@@ -0,0 +1,335 @@
+#include "wrnum.h"
+
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writehex16 uart1_writehex16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 4;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart1wrhex32.c b/libs/libmf/builtsource/uart1wrhex32.c
new file mode 100644
index 00000000..930138e2
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrhex32.c
@@ -0,0 +1,353 @@
+#include "wrnum.h"
+
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writehex32 uart1_writehex32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: dec a
+ jnz 00034$
+ mov a,r7
+ sjmp 00031$
+00034$: dec a
+ jnz 00035$
+ mov a,r6
+ sjmp 00031$
+00035$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 8;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart1wrhexu16.c b/libs/libmf/builtsource/uart1wrhexu16.c
new file mode 100644
index 00000000..747ba915
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrhexu16.c
@@ -0,0 +1,30 @@
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+__reentrantb void uart_writehexu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart1wrhexu32.c b/libs/libmf/builtsource/uart1wrhexu32.c
new file mode 100644
index 00000000..7d8a9b51
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrhexu32.c
@@ -0,0 +1,30 @@
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+void uart_writehexu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart1wrnum16.c b/libs/libmf/builtsource/uart1wrnum16.c
new file mode 100644
index 00000000..e38ab8e4
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrnum16.c
@@ -0,0 +1,305 @@
+#include "wrnum.h"
+
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writenum16 uart1_writenum16
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-4
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ mov a,r3
+ mov r4,a
+ ; val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ mov a,#ar4
+ push acc
+ lcall _libmf_num16_digit
+ dec sp
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 5;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart1wrnum32.c b/libs/libmf/builtsource/uart1wrnum32.c
new file mode 100644
index 00000000..9e480b4c
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrnum32.c
@@ -0,0 +1,345 @@
+#include "wrnum.h"
+
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writenum32 uart1_writenum32
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 9)
+ ; --nrdig;
+ ; if (nrdig > 6)
+ ; --nrdig;
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00022$
+ mov a,r2
+ add a,#-10
+ jnc 00020$
+ dec r2
+00020$: mov a,r2
+ add a,#-7
+ jnc 00021$
+ dec r2
+00021$: mov a,r2
+ add a,#-4
+ jnc 00022$
+ dec r2
+00022$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ push ar3
+ ; val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ mov a,sp
+ push b
+ push acc
+ mov b,r7
+ mov a,r6
+ lcall _libmf_num32_digit
+ mov r6,a
+ mov r7,b
+ dec sp
+ pop b
+ pop acc
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov r4,a
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00042$
+ add a,#-3
+ jz 00042$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx(' ');
+00042$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00050$
+ add a,#-3
+ jz 00050$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx('\'');
+00050$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 10;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && ((int32_t)val) < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 9)
+ --nrdig;
+ if (nrdig > 6)
+ --nrdig;
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart1wrstr.c b/libs/libmf/builtsource/uart1wrstr.c
new file mode 100644
index 00000000..f951e878
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wrstr.c
@@ -0,0 +1,135 @@
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define _uart_wait_txfree _uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txfreelinear _uart1_txfreelinear
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define _uart_txadvance _uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+#if defined(SDCC)
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ ch;
+ __asm;
+ mov r0,dpl
+ mov r7,dph
+ clr a
+ mov r3,a
+ mov r2,a
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00011$ ; <0x40 far
+ jb _B_5,00012$ ; >0x60 pdata
+ ;; idata
+ mov a,@r0
+ inc r0
+ sjmp 00013$
+00010$: ;; code
+ mov dpl,r0
+ mov dph,r7
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00011$: ;; xdata
+ mov dpl,r0
+ mov dph,r7
+ movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00012$: ;; pdata
+ movx a,@r0
+ inc r0
+00013$: jz 00001$
+ mov r1,a
+ mov a,r3
+ jnz 00002$
+ mov a,r2
+ jz 00003$
+ mov dpl,a
+ lcall _uart_txadvance
+00003$: lcall _uart_txfreelinear
+ mov a,dpl
+ jnz 00004$
+ mov r4,b
+ mov dpl,#1
+ lcall _uart_wait_txfree
+ mov b,r4
+ lcall _uart_txfreelinear
+ mov a,dpl
+00004$: mov r3,a
+ clr a
+ mov r2,a
+ mov dpl,a
+ lcall _uart_txbufptr
+ mov r4,dpl
+ mov r5,dph
+00002$: mov dpl,r4
+ mov dph,r5
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov r4,dpl
+ mov r5,dph
+ inc r2
+ dec r3
+ sjmp 00000$
+00001$: mov a,r2
+ jz 00005$
+ mov dpl,a
+ lcall _uart_txadvance
+00005$:
+ __endasm;
+}
+
+#else
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ uint8_t __xdata *p;
+ uint8_t f = 0;
+ uint8_t a = 0;
+ for (;;) {
+ char c = *ch++;
+ if (!c)
+ break;
+ if (!f) {
+ if (a)
+ uart_txadvance(a);
+ f = uart_txfreelinear();
+ if (!f) {
+ uart_wait_txfree(1);
+ f = uart_txfreelinear();
+ }
+ p = uart_txbufptr(0);
+ a = 0;
+ }
+ *p++ = c;
+ ++a;
+ --f;
+ }
+ if (a)
+ uart_txadvance(a);
+}
+
+#endif
diff --git a/libs/libmf/builtsource/uart1wru16.c b/libs/libmf/builtsource/uart1wru16.c
new file mode 100644
index 00000000..4334b1f5
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wru16.c
@@ -0,0 +1,32 @@
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+__reentrantb void uart_writeu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uart1wru32.c b/libs/libmf/builtsource/uart1wru32.c
new file mode 100644
index 00000000..9c11ac9e
--- /dev/null
+++ b/libs/libmf/builtsource/uart1wru32.c
@@ -0,0 +1,32 @@
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+
+void uart_writeu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/builtsource/uarttimer0.c b/libs/libmf/builtsource/uarttimer0.c
new file mode 100644
index 00000000..5487d380
--- /dev/null
+++ b/libs/libmf/builtsource/uarttimer0.c
@@ -0,0 +1,46 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#define uart_timer_baud uart_timer0_baud
+#define TCLKSRC T0CLKSRC
+#define TMODE T0MODE
+#define TPERIOD T0PERIOD
+
+__reentrantb void uart_timer_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant
+{
+ uint8_t sh = 26;
+ while (sh) {
+ uint8_t bdhi = baud >> 24;
+ if (!bdhi && sh >= 8) {
+ baud <<= 8;
+ sh -= 8;
+ continue;
+ }
+ if (!(bdhi & 0xF0) && sh >= 4) {
+ baud <<= 4;
+ sh -= 4;
+ continue;
+ }
+ if (!(bdhi & 0xC0) && sh >= 2) {
+ baud <<= 2;
+ sh -= 2;
+ continue;
+ }
+ if (!(bdhi & 0x80)) {
+ baud <<= 1;
+ --sh;
+ continue;
+ }
+ break;
+ }
+ clkfreq >>= sh;
+ baud /= clkfreq;
+ sh = 0x38;
+ while (baud >= 16384 && (sh & 0xF0)) {
+ baud >>= 1;
+ sh -= 8;
+ }
+ TCLKSRC = sh | (clksrc & 7);
+ TMODE = 0x04;
+ TPERIOD = baud;
+}
diff --git a/libs/libmf/builtsource/uarttimer1.c b/libs/libmf/builtsource/uarttimer1.c
new file mode 100644
index 00000000..b339ad45
--- /dev/null
+++ b/libs/libmf/builtsource/uarttimer1.c
@@ -0,0 +1,46 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#define uart_timer_baud uart_timer1_baud
+#define TCLKSRC T1CLKSRC
+#define TMODE T1MODE
+#define TPERIOD T1PERIOD
+
+__reentrantb void uart_timer_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant
+{
+ uint8_t sh = 26;
+ while (sh) {
+ uint8_t bdhi = baud >> 24;
+ if (!bdhi && sh >= 8) {
+ baud <<= 8;
+ sh -= 8;
+ continue;
+ }
+ if (!(bdhi & 0xF0) && sh >= 4) {
+ baud <<= 4;
+ sh -= 4;
+ continue;
+ }
+ if (!(bdhi & 0xC0) && sh >= 2) {
+ baud <<= 2;
+ sh -= 2;
+ continue;
+ }
+ if (!(bdhi & 0x80)) {
+ baud <<= 1;
+ --sh;
+ continue;
+ }
+ break;
+ }
+ clkfreq >>= sh;
+ baud /= clkfreq;
+ sh = 0x38;
+ while (baud >= 16384 && (sh & 0xF0)) {
+ baud >>= 1;
+ sh -= 8;
+ }
+ TCLKSRC = sh | (clksrc & 7);
+ TMODE = 0x04;
+ TPERIOD = baud;
+}
diff --git a/libs/libmf/builtsource/uarttimer2.c b/libs/libmf/builtsource/uarttimer2.c
new file mode 100644
index 00000000..4737b536
--- /dev/null
+++ b/libs/libmf/builtsource/uarttimer2.c
@@ -0,0 +1,46 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#define uart_timer_baud uart_timer2_baud
+#define TCLKSRC T2CLKSRC
+#define TMODE T2MODE
+#define TPERIOD T2PERIOD
+
+__reentrantb void uart_timer_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant
+{
+ uint8_t sh = 26;
+ while (sh) {
+ uint8_t bdhi = baud >> 24;
+ if (!bdhi && sh >= 8) {
+ baud <<= 8;
+ sh -= 8;
+ continue;
+ }
+ if (!(bdhi & 0xF0) && sh >= 4) {
+ baud <<= 4;
+ sh -= 4;
+ continue;
+ }
+ if (!(bdhi & 0xC0) && sh >= 2) {
+ baud <<= 2;
+ sh -= 2;
+ continue;
+ }
+ if (!(bdhi & 0x80)) {
+ baud <<= 1;
+ --sh;
+ continue;
+ }
+ break;
+ }
+ clkfreq >>= sh;
+ baud /= clkfreq;
+ sh = 0x38;
+ while (baud >= 16384 && (sh & 0xF0)) {
+ baud >>= 1;
+ sh -= 8;
+ }
+ TCLKSRC = sh | (clksrc & 7);
+ TMODE = 0x04;
+ TPERIOD = baud;
+}
diff --git a/libs/libmf/doc/LibMF.pdf b/libs/libmf/doc/LibMF.pdf
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diff --git a/libs/libmf/include/ax8052.h b/libs/libmf/include/ax8052.h
new file mode 100644
index 00000000..0d85a9f2
--- /dev/null
+++ b/libs/libmf/include/ax8052.h
@@ -0,0 +1,588 @@
+/*-------------------------------------------------------------------------
+ AX8052.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052_H
+#define AX8052_H
+
+#include
+
+/* SFR Address Space */
+
+SFR(ACC, 0xE0) /* Accumulator */
+SBIT(ACC_0, 0xE0, 0) /* Accumulator bit 0 */
+SBIT(ACC_1, 0xE0, 1) /* Accumulator bit 1 */
+SBIT(ACC_2, 0xE0, 2) /* Accumulator bit 2 */
+SBIT(ACC_3, 0xE0, 3) /* Accumulator bit 3 */
+SBIT(ACC_4, 0xE0, 4) /* Accumulator bit 4 */
+SBIT(ACC_5, 0xE0, 5) /* Accumulator bit 5 */
+SBIT(ACC_6, 0xE0, 6) /* Accumulator bit 6 */
+SBIT(ACC_7, 0xE0, 7) /* Accumulator bit 7 */
+SFR(B, 0xF0) /* B Register */
+SBIT(B_0, 0xF0, 0) /* Register B bit 0 */
+SBIT(B_1, 0xF0, 1) /* Register B bit 1 */
+SBIT(B_2, 0xF0, 2) /* Register B bit 2 */
+SBIT(B_3, 0xF0, 3) /* Register B bit 3 */
+SBIT(B_4, 0xF0, 4) /* Register B bit 4 */
+SBIT(B_5, 0xF0, 5) /* Register B bit 5 */
+SBIT(B_6, 0xF0, 6) /* Register B bit 6 */
+SBIT(B_7, 0xF0, 7) /* Register B bit 7 */
+SFR(DPH, 0x83) /* Data Pointer 0 High Byte */
+SFR(DPH1, 0x85) /* Data Pointer 1 High Byte */
+SFR(DPL, 0x82) /* Data Pointer 0 Low Byte */
+SFR(DPL1, 0x84) /* Data Pointer 1 Low Byte */
+SFR16(DPTR0, 0x82) /* Data Pointer 0 */
+SFR16(DPTR1, 0x84) /* Data Pointer 1 */
+SFR(DPS, 0x86) /* Data Pointer Select */
+SFR(E2IE, 0xA0) /* 2nd Extended Interrupt Enable */
+SBIT(E2IE_0, 0xA0, 0) /* Output Compare 0 Interrupt Enable */
+SBIT(E2IE_1, 0xA0, 1) /* Output Compare 1 Interrupt Enable */
+SBIT(E2IE_2, 0xA0, 2) /* Input Capture 0 Interrupt Enable */
+SBIT(E2IE_3, 0xA0, 3) /* Input Capture 1 Interrupt Enable */
+SBIT(E2IE_4, 0xA0, 4) /* */
+SBIT(E2IE_5, 0xA0, 5) /* */
+SBIT(E2IE_6, 0xA0, 6) /* DebugLink Interrupt Enable */
+SBIT(E2IE_7, 0xA0, 7) /* */
+SFR(E2IP, 0xC0) /* 2nd Extended Interrupt Priority */
+SBIT(E2IP_0, 0xC0, 0) /* Output Compare 0 Interrupt Priority */
+SBIT(E2IP_1, 0xC0, 1) /* Output Compare 1 Interrupt Priority */
+SBIT(E2IP_2, 0xC0, 2) /* Input Capture 0 Interrupt Priority */
+SBIT(E2IP_3, 0xC0, 3) /* Input Capture 1 Interrupt Priority */
+SBIT(E2IP_4, 0xC0, 4) /* */
+SBIT(E2IP_5, 0xC0, 5) /* */
+SBIT(E2IP_6, 0xC0, 6) /* DebugLink Interrupt Priority */
+SBIT(E2IP_7, 0xC0, 7) /* */
+SFR(EIE, 0x98) /* Extended Interrupt Enable */
+SBIT(EIE_0, 0x98, 0) /* Timer 0 Interrupt Enable */
+SBIT(EIE_1, 0x98, 1) /* Timer 1 Interrupt Enable */
+SBIT(EIE_2, 0x98, 2) /* Timer 2 Interrupt Enable */
+SBIT(EIE_3, 0x98, 3) /* SPI 0 Interrupt Enable */
+SBIT(EIE_4, 0x98, 4) /* UART 0 Interrupt Enable */
+SBIT(EIE_5, 0x98, 5) /* UART 1 Interrupt Enable */
+SBIT(EIE_6, 0x98, 6) /* GPADC Interrupt Enable */
+SBIT(EIE_7, 0x98, 7) /* DMA Interrupt Enable */
+SFR(EIP, 0xB0) /* Extended Interrupt Priority */
+SBIT(EIP_0, 0xB0, 0) /* Timer 0 Interrupt Priority */
+SBIT(EIP_1, 0xB0, 1) /* Timer 1 Interrupt Priority */
+SBIT(EIP_2, 0xB0, 2) /* Timer 2 Interrupt Priority */
+SBIT(EIP_3, 0xB0, 3) /* SPI 0 Interrupt Priority */
+SBIT(EIP_4, 0xB0, 4) /* UART 0 Interrupt Priority */
+SBIT(EIP_5, 0xB0, 5) /* UART 1 Interrupt Priority */
+SBIT(EIP_6, 0xB0, 6) /* GPADC Interrupt Priority */
+SBIT(EIP_7, 0xB0, 7) /* DMA Interrupt Priority */
+SFR(IE, 0xA8) /* Interrupt Enable */
+SBIT(IE_0, 0xA8, 0) /* External 0 Interrupt Enable */
+SBIT(IE_1, 0xA8, 1) /* Wakeup Timer Interrupt Enable */
+SBIT(IE_2, 0xA8, 2) /* External 1 Interrupt Enable */
+SBIT(IE_3, 0xA8, 3) /* GPIO Interrupt Enable */
+SBIT(IE_4, 0xA8, 4) /* Radio Interrupt Enable */
+SBIT(IE_5, 0xA8, 5) /* Clock Management Interrupt Enable */
+SBIT(IE_6, 0xA8, 6) /* Power Management Interrupt Enable */
+SBIT(IE_7, 0xA8, 7) /* Global Interrupt Enable */
+SBIT(EA, 0xA8, 7) /* Global Interrupt Enable */
+SFR(IP, 0xB8) /* Interrupt Priority */
+SBIT(IP_0, 0xB8, 0) /* External 0 Interrupt Priority */
+SBIT(IP_1, 0xB8, 1) /* Wakeup Timer Interrupt Priority */
+SBIT(IP_2, 0xB8, 2) /* External 1 Interrupt Priority */
+SBIT(IP_3, 0xB8, 3) /* GPIO Interrupt Priority */
+SBIT(IP_4, 0xB8, 4) /* Radio Interrupt Priority */
+SBIT(IP_5, 0xB8, 5) /* Clock Management Interrupt Priority */
+SBIT(IP_6, 0xB8, 6) /* Power Management Interrupt Priority */
+SBIT(IP_7, 0xB8, 7) /* */
+SFR(PCON, 0x87) /* Power Mode Control */
+SFR(PSW, 0xD0) /* Program Status Word */
+SBIT(P, 0xD0, 0) /* Parity Flag */
+SBIT(F1, 0xD0, 1) /* User-Defined Flag */
+SBIT(OV, 0xD0, 2) /* Overflow Flag */
+SBIT(RS0, 0xD0, 3) /* Register Bank Select 0 */
+SBIT(RS1, 0xD0, 4) /* Register Bank Select 1 */
+SBIT(F0, 0xD0, 5) /* User-Defined Flag */
+SBIT(AC, 0xD0, 6) /* Auxiliary Carry Flag */
+SBIT(CY, 0xD0, 7) /* Carry Flag */
+SFR(SP, 0x81) /* Stack Pointer */
+SFR(XPAGE, 0xD9) /* Memory Page Select */
+SFR(_XPAGE, 0xD9) /* Memory Page Select, SDCC name */
+SFR(ADCCH0CONFIG, 0xCA) /* ADC Channel 0 Configuration */
+SFR(ADCCH1CONFIG, 0xCB) /* ADC Channel 1 Configuration */
+SFR(ADCCH2CONFIG, 0xD2) /* ADC Channel 2 Configuration */
+SFR(ADCCH3CONFIG, 0xD3) /* ADC Channel 3 Configuration */
+SFR(ADCCLKSRC, 0xD1) /* ADC Clock Source */
+SFR(ADCCONV, 0xC9) /* ADC Conversion Source */
+SFR(ANALOGCOMP, 0xE1) /* Analog Comparators */
+SFR(CLKCON, 0xC6) /* Clock Control */
+SFR(CLKSTAT, 0xC7) /* Clock Status */
+SFR(CODECONFIG, 0x97) /* Code Space Configuration */
+SFR(DBGLNKBUF, 0xE3) /* Debug Link Buffer */
+SFR(DBGLNKSTAT, 0xE2) /* Debug Link Status */
+SFR(DIRA, 0x89) /* Port A Direction */
+SFR(DIRB, 0x8A) /* Port B Direction */
+SFR(DIRC, 0x8B) /* Port C Direction */
+SFR(DIRR, 0x8E) /* Port R Direction */
+SFR(PINA, 0xC8) /* Port A Input */
+SBIT(PINA_0, 0xC8, 0) /* */
+SBIT(PINA_1, 0xC8, 1) /* */
+SBIT(PINA_2, 0xC8, 2) /* */
+SBIT(PINA_3, 0xC8, 3) /* */
+SBIT(PINA_4, 0xC8, 4) /* */
+SBIT(PINA_5, 0xC8, 5) /* */
+SBIT(PINA_6, 0xC8, 6) /* */
+SBIT(PINA_7, 0xC8, 7) /* */
+SFR(PINB, 0xE8) /* Port B Input */
+SBIT(PINB_0, 0xE8, 0) /* */
+SBIT(PINB_1, 0xE8, 1) /* */
+SBIT(PINB_2, 0xE8, 2) /* */
+SBIT(PINB_3, 0xE8, 3) /* */
+SBIT(PINB_4, 0xE8, 4) /* */
+SBIT(PINB_5, 0xE8, 5) /* */
+SBIT(PINB_6, 0xE8, 6) /* */
+SBIT(PINB_7, 0xE8, 7) /* */
+SFR(PINC, 0xF8) /* Port C Input */
+SBIT(PINC_0, 0xF8, 0) /* */
+SBIT(PINC_1, 0xF8, 1) /* */
+SBIT(PINC_2, 0xF8, 2) /* */
+SBIT(PINC_3, 0xF8, 3) /* */
+SBIT(PINC_4, 0xF8, 4) /* */
+SBIT(PINC_5, 0xF8, 5) /* */
+SBIT(PINC_6, 0xF8, 6) /* */
+SBIT(PINC_7, 0xF8, 7) /* */
+SFR(PINR, 0x8D) /* Port R Input */
+SFR(PORTA, 0x80) /* Port A Output */
+SBIT(PORTA_0, 0x80, 0) /* */
+SBIT(PORTA_1, 0x80, 1) /* */
+SBIT(PORTA_2, 0x80, 2) /* */
+SBIT(PORTA_3, 0x80, 3) /* */
+SBIT(PORTA_4, 0x80, 4) /* */
+SBIT(PORTA_5, 0x80, 5) /* */
+SBIT(PORTA_6, 0x80, 6) /* */
+SBIT(PORTA_7, 0x80, 7) /* */
+SFR(PORTB, 0x88) /* Port B Output */
+SBIT(PORTB_0, 0x88, 0) /* */
+SBIT(PORTB_1, 0x88, 1) /* */
+SBIT(PORTB_2, 0x88, 2) /* */
+SBIT(PORTB_3, 0x88, 3) /* */
+SBIT(PORTB_4, 0x88, 4) /* */
+SBIT(PORTB_5, 0x88, 5) /* */
+SBIT(PORTB_6, 0x88, 6) /* */
+SBIT(PORTB_7, 0x88, 7) /* */
+SFR(PORTC, 0x90) /* Port C Output */
+SBIT(PORTC_0, 0x90, 0) /* */
+SBIT(PORTC_1, 0x90, 1) /* */
+SBIT(PORTC_2, 0x90, 2) /* */
+SBIT(PORTC_3, 0x90, 3) /* */
+SBIT(PORTC_4, 0x90, 4) /* */
+SBIT(PORTC_5, 0x90, 5) /* */
+SBIT(PORTC_6, 0x90, 6) /* */
+SBIT(PORTC_7, 0x90, 7) /* */
+SFR(PORTR, 0x8C) /* Port R Output */
+SFR(IC0CAPT0, 0xCE) /* Input Capture 0 Low Byte */
+SFR(IC0CAPT1, 0xCF) /* Input Capture 0 High Byte */
+SFR16(IC0CAPT, 0xCE) /* Input Capture 0 */
+SFR(IC0MODE, 0xCC) /* Input Capture 0 Mode */
+SFR(IC0STATUS, 0xCD) /* Input Capture 0 Status */
+SFR(IC1CAPT0, 0xD6) /* Input Capture 1 Low Byte */
+SFR(IC1CAPT1, 0xD7) /* Input Capture 1 High Byte */
+SFR16(IC1CAPT, 0xD6) /* Input Capture 1 */
+SFR(IC1MODE, 0xD4) /* Input Capture 1 Mode */
+SFR(IC1STATUS, 0xD5) /* Input Capture 1 Status */
+SFR(NVADDR0, 0x92) /* Non-Volatile Memory Address Low Byte */
+SFR(NVADDR1, 0x93) /* Non-Volatile Memory Address High Byte */
+SFR16(NVADDR, 0x92) /* Non-Volatile Memory Address */
+SFR(NVDATA0, 0x94) /* Non-Volatile Memory Data Low Byte */
+SFR(NVDATA1, 0x95) /* Non-Volatile Memory Data High Byte */
+SFR16(NVDATA, 0x94) /* Non-Volatile Memory Data */
+SFR(NVKEY, 0x96) /* Non-Volatile Memory Write/Erase Key */
+SFR(NVSTATUS, 0x91) /* Non-Volatile Memory Command / Status */
+SFR(OC0COMP0, 0xBC) /* Output Compare 0 Low Byte */
+SFR(OC0COMP1, 0xBD) /* Output Compare 0 High Byte */
+SFR16(OC0COMP, 0xBC) /* Output Compare 0 */
+SFR(OC0MODE, 0xB9) /* Output Compare 0 Mode */
+SFR(OC0PIN, 0xBA) /* Output Compare 0 Pin Configuration */
+SFR(OC0STATUS, 0xBB) /* Output Compare 0 Status */
+SFR(OC1COMP0, 0xC4) /* Output Compare 1 Low Byte */
+SFR(OC1COMP1, 0xC5) /* Output Compare 1 High Byte */
+SFR16(OC1COMP, 0xC4) /* Output Compare 1 */
+SFR(OC1MODE, 0xC1) /* Output Compare 1 Mode */
+SFR(OC1PIN, 0xC2) /* Output Compare 1 Pin Configuration */
+SFR(OC1STATUS, 0xC3) /* Output Compare 1 Status */
+SFR(RADIOACC, 0xB1) /* Radio Controller Access Mode */
+SFR(RADIOADDR0, 0xB3) /* Radio Register Address Low Byte */
+SFR(RADIOADDR1, 0xB2) /* Radio Register Address High Byte */
+SFR16E(RADIOADDR, 0xB2B3) /* Radio Register Address */
+SFR(RADIODATA0, 0xB7) /* Radio Register Data 0 */
+SFR(RADIODATA1, 0xB6) /* Radio Register Data 1 */
+SFR(RADIODATA2, 0xB5) /* Radio Register Data 2 */
+SFR(RADIODATA3, 0xB4) /* Radio Register Data 3 */
+SFR32E(RADIODATA, 0xB4B5B6B7) /* Radio Register Data */
+SFR(RADIOSTAT0, 0xBE) /* Radio Access Status Low Byte */
+SFR(RADIOSTAT1, 0xBF) /* Radio Access Status High Byte */
+SFR16(RADIOSTAT, 0xBE) /* Radio Access Status */
+SFR(SPCLKSRC, 0xDF) /* SPI Clock Source */
+SFR(SPMODE, 0xDC) /* SPI Mode */
+SFR(SPSHREG, 0xDE) /* SPI Shift Register */
+SFR(SPSTATUS, 0xDD) /* SPI Status */
+SFR(T0CLKSRC, 0x9A) /* Timer 0 Clock Source */
+SFR(T0CNT0, 0x9C) /* Timer 0 Count Low Byte */
+SFR(T0CNT1, 0x9D) /* Timer 0 Count High Byte */
+SFR16(T0CNT, 0x9C) /* Timer 0 Count */
+SFR(T0MODE, 0x99) /* Timer 0 Mode */
+SFR(T0PERIOD0, 0x9E) /* Timer 0 Period Low Byte */
+SFR(T0PERIOD1, 0x9F) /* Timer 0 Period High Byte */
+SFR16(T0PERIOD, 0x9E) /* Timer 0 Period */
+SFR(T0STATUS, 0x9B) /* Timer 0 Status */
+SFR(T1CLKSRC, 0xA2) /* Timer 1 Clock Source */
+SFR(T1CNT0, 0xA4) /* Timer 1 Count Low Byte */
+SFR(T1CNT1, 0xA5) /* Timer 1 Count High Byte */
+SFR16(T1CNT, 0xA4) /* Timer 1 Count */
+SFR(T1MODE, 0xA1) /* Timer 1 Mode */
+SFR(T1PERIOD0, 0xA6) /* Timer 1 Period Low Byte */
+SFR(T1PERIOD1, 0xA7) /* Timer 1 Period High Byte */
+SFR16(T1PERIOD, 0xA6) /* Timer 1 Period */
+SFR(T1STATUS, 0xA3) /* Timer 1 Status */
+SFR(T2CLKSRC, 0xAA) /* Timer 2 Clock Source */
+SFR(T2CNT0, 0xAC) /* Timer 2 Count Low Byte */
+SFR(T2CNT1, 0xAD) /* Timer 2 Count High Byte */
+SFR16(T2CNT, 0xAC) /* Timer 2 Count */
+SFR(T2MODE, 0xA9) /* Timer 2 Mode */
+SFR(T2PERIOD0, 0xAE) /* Timer 2 Period Low Byte */
+SFR(T2PERIOD1, 0xAF) /* Timer 2 Period High Byte */
+SFR16(T2PERIOD, 0xAE) /* Timer 2 Period */
+SFR(T2STATUS, 0xAB) /* Timer 2 Status */
+SFR(U0CTRL, 0xE4) /* UART 0 Control */
+SFR(U0MODE, 0xE7) /* UART 0 Mode */
+SFR(U0SHREG, 0xE6) /* UART 0 Shift Register */
+SFR(U0STATUS, 0xE5) /* UART 0 Status */
+SFR(U1CTRL, 0xEC) /* UART 1 Control */
+SFR(U1MODE, 0xEF) /* UART 1 Mode */
+SFR(U1SHREG, 0xEE) /* UART 1 Shift Register */
+SFR(U1STATUS, 0xED) /* UART 1 Status */
+SFR(WDTCFG, 0xDA) /* Watchdog Configuration */
+SFR(WDTRESET, 0xDB) /* Watchdog Reset */
+SFR(WTCFGA, 0xF1) /* Wakeup Timer A Configuration */
+SFR(WTCFGB, 0xF9) /* Wakeup Timer B Configuration */
+SFR(WTCNTA0, 0xF2) /* Wakeup Counter A Low Byte */
+SFR(WTCNTA1, 0xF3) /* Wakeup Counter A High Byte */
+SFR16(WTCNTA, 0xF2) /* Wakeup Counter A */
+SFR(WTCNTB0, 0xFA) /* Wakeup Counter B Low Byte */
+SFR(WTCNTB1, 0xFB) /* Wakeup Counter B High Byte */
+SFR16(WTCNTB, 0xFA) /* Wakeup Counter B */
+SFR(WTCNTR1, 0xEB) /* Wakeup Counter High Byte Latch */
+SFR(WTEVTA0, 0xF4) /* Wakeup Event A Low Byte */
+SFR(WTEVTA1, 0xF5) /* Wakeup Event A High Byte */
+SFR16(WTEVTA, 0xF4) /* Wakeup Event A */
+SFR(WTEVTB0, 0xF6) /* Wakeup Event B Low Byte */
+SFR(WTEVTB1, 0xF7) /* Wakeup Event B High Byte */
+SFR16(WTEVTB, 0xF6) /* Wakeup Event B */
+SFR(WTEVTC0, 0xFC) /* Wakeup Event C Low Byte */
+SFR(WTEVTC1, 0xFD) /* Wakeup Event C High Byte */
+SFR16(WTEVTC, 0xFC) /* Wakeup Event C */
+SFR(WTEVTD0, 0xFE) /* Wakeup Event D Low Byte */
+SFR(WTEVTD1, 0xFF) /* Wakeup Event D High Byte */
+SFR16(WTEVTD, 0xFE) /* Wakeup Event D */
+SFR(WTIRQEN, 0xE9) /* Wakeup Timer Interrupt Enable */
+SFR(WTSTAT, 0xEA) /* Wakeup Timer Status */
+
+/* X Address Space */
+
+#define AX8052_RADIOBASE 0x4000
+#define AX8052_RADIOBASENB 0x5000
+
+SFRX(ADCCH0VAL0, 0x7020) /* ADC Channel 0 Low Byte */
+SFRX(ADCCH0VAL1, 0x7021) /* ADC Channel 0 High Byte */
+SFR16LEX(ADCCH0VAL, 0x7020) /* ADC Channel 0 */
+SFRX(ADCCH1VAL0, 0x7022) /* ADC Channel 1 Low Byte */
+SFRX(ADCCH1VAL1, 0x7023) /* ADC Channel 1 High Byte */
+SFR16LEX(ADCCH1VAL, 0x7022) /* ADC Channel 1 */
+SFRX(ADCCH2VAL0, 0x7024) /* ADC Channel 2 Low Byte */
+SFRX(ADCCH2VAL1, 0x7025) /* ADC Channel 2 High Byte */
+SFR16LEX(ADCCH2VAL, 0x7024) /* ADC Channel 2 */
+SFRX(ADCCH3VAL0, 0x7026) /* ADC Channel 3 Low Byte */
+SFRX(ADCCH3VAL1, 0x7027) /* ADC Channel 3 High Byte */
+SFR16LEX(ADCCH3VAL, 0x7026) /* ADC Channel 3 */
+SFRX(ADCTUNE0, 0x7028) /* ADC Tuning 0 */
+SFRX(ADCTUNE1, 0x7029) /* ADC Tuning 1 */
+SFRX(ADCTUNE2, 0x702A) /* ADC Tuning 2 */
+SFRX(DMA0ADDR0, 0x7010) /* DMA Channel 0 Address Low Byte */
+SFRX(DMA0ADDR1, 0x7011) /* DMA Channel 0 Address High Byte */
+SFR16LEX(DMA0ADDR, 0x7010) /* DMA Channel 0 Address */
+SFRX(DMA0CONFIG, 0x7014) /* DMA Channel 0 Configuration */
+SFRX(DMA1ADDR0, 0x7012) /* DMA Channel 1 Address Low Byte */
+SFRX(DMA1ADDR1, 0x7013) /* DMA Channel 1 Address High Byte */
+SFR16LEX(DMA1ADDR, 0x7012) /* DMA Channel 1 Address */
+SFRX(DMA1CONFIG, 0x7015) /* DMA Channel 1 Configuration */
+SFRX(FRCOSCCONFIG, 0x7070) /* Fast RC Oscillator Calibration Configuration */
+SFRX(FRCOSCCTRL, 0x7071) /* Fast RC Oscillator Control */
+SFRX(FRCOSCFREQ0, 0x7076) /* Fast RC Oscillator Frequency Tuning Low Byte */
+SFRX(FRCOSCFREQ1, 0x7077) /* Fast RC Oscillator Frequency Tuning High Byte */
+SFR16LEX(FRCOSCFREQ, 0x7076) /* Fast RC Oscillator Frequency Tuning */
+SFRX(FRCOSCKFILT0, 0x7072) /* Fast RC Oscillator Calibration Filter Constant Low Byte */
+SFRX(FRCOSCKFILT1, 0x7073) /* Fast RC Oscillator Calibration Filter Constant High Byte */
+SFR16LEX(FRCOSCKFILT, 0x7072) /* Fast RC Oscillator Calibration Filter Constant */
+SFRX(FRCOSCPER0, 0x7078) /* Fast RC Oscillator Period Low Byte */
+SFRX(FRCOSCPER1, 0x7079) /* Fast RC Oscillator Period High Byte */
+SFR16LEX(FRCOSCPER, 0x7078) /* Fast RC Oscillator Period */
+SFRX(FRCOSCREF0, 0x7074) /* Fast RC Oscillator Reference Frequency Low Byte */
+SFRX(FRCOSCREF1, 0x7075) /* Fast RC Oscillator Reference Frequency High Byte */
+SFR16LEX(FRCOSCREF, 0x7074) /* Fast RC Oscillator Reference Frequency */
+SFRX(ANALOGA, 0x7007) /* Port A Analog Mode */
+SFRX(GPIOENABLE, 0x700C) /* GPIO Port Enable */
+SFRX(EXTIRQ, 0x7003) /* External IRQ Configuration */
+SFRX(INTCHGA, 0x7000) /* Port A Interrupt on Change */
+SFRX(INTCHGB, 0x7001) /* Port B Interrupt on Change */
+SFRX(INTCHGC, 0x7002) /* Port C Interrupt on Change */
+SFRX(PALTA, 0x7008) /* Port A Alternate Function */
+SFRX(PALTB, 0x7009) /* Port B Alternate Function */
+SFRX(PALTC, 0x700A) /* Port C Alternate Function */
+SFRX(PALTRADIO, 0x7046) /* Port Radio Alternate Function */
+SFRX(PINCHGA, 0x7004) /* Port A Level Change */
+SFRX(PINCHGB, 0x7005) /* Port B Level Change */
+SFRX(PINCHGC, 0x7006) /* Port C Level Change */
+SFRX(PINSEL, 0x700B) /* Port Input Selection */
+SFRX(LPOSCCONFIG, 0x7060) /* Low Power Oscillator Calibration Configuration */
+SFRX(LPOSCFREQ0, 0x7066) /* Low Power Oscillator Frequency Tuning Low Byte */
+SFRX(LPOSCFREQ1, 0x7067) /* Low Power Oscillator Frequency Tuning High Byte */
+SFR16LEX(LPOSCFREQ, 0x7066) /* Low Power Oscillator Frequency Tuning */
+SFRX(LPOSCKFILT0, 0x7062) /* Low Power Oscillator Calibration Filter Constant Low Byte */
+SFRX(LPOSCKFILT1, 0x7063) /* Low Power Oscillator Calibration Filter Constant High Byte */
+SFR16LEX(LPOSCKFILT, 0x7062) /* Low Power Oscillator Calibration Filter Constant */
+SFRX(LPOSCPER0, 0x7068) /* Low Power Oscillator Period Low Byte */
+SFRX(LPOSCPER1, 0x7069) /* Low Power Oscillator Period High Byte */
+SFR16LEX(LPOSCPER, 0x7068) /* Low Power Oscillator Period */
+SFRX(LPOSCREF0, 0x7064) /* Low Power Oscillator Reference Frequency Low Byte */
+SFRX(LPOSCREF1, 0x7065) /* Low Power Oscillator Reference Frequency High Byte */
+SFR16LEX(LPOSCREF, 0x7064) /* Low Power Oscillator Reference Frequency */
+SFRX(LPXOSCGM, 0x7054) /* Low Power Crystal Oscillator Transconductance */
+SFRX(MISCCTRL, 0x7F01) /* Miscellaneous Control */
+SFRX(OSCCALIB, 0x7053) /* Oscillator Calibration Interrupt / Status */
+SFRX(OSCFORCERUN, 0x7050) /* Oscillator Run Force */
+SFRX(OSCREADY, 0x7052) /* Oscillator Ready Status */
+SFRX(OSCRUN, 0x7051) /* Oscillator Run Status */
+SFRX(RADIOFDATAADDR0, 0x7040) /* Radio FIFO Data Register Address Low Byte */
+SFRX(RADIOFDATAADDR1, 0x7041) /* Radio FIFO Data Register Address High Byte */
+SFR16LEX(RADIOFDATAADDR, 0x7040) /* Radio FIFO Data Register Address */
+SFRX(RADIOFSTATADDR0, 0x7042) /* Radio FIFO Status Register Address Low Byte */
+SFRX(RADIOFSTATADDR1, 0x7043) /* Radio FIFO Status Register Address High Byte */
+SFR16LEX(RADIOFSTATADDR, 0x7042) /* Radio FIFO Status Register Address */
+SFRX(RADIOMUX, 0x7044) /* Radio Multiplexer Control */
+SFRX(SCRATCH0, 0x7084) /* Scratch Register 0 */
+SFRX(SCRATCH1, 0x7085) /* Scratch Register 1 */
+SFRX(SCRATCH2, 0x7086) /* Scratch Register 2 */
+SFRX(SCRATCH3, 0x7087) /* Scratch Register 3 */
+SFRX(SILICONREV, 0x7F00) /* Silicon Revision */
+SFRX(XTALAMPL, 0x7F19) /* Crystal Oscillator Amplitude Control */
+SFRX(XTALOSC, 0x7F18) /* Crystal Oscillator Configuration */
+SFRX(XTALREADY, 0x7F1A) /* Crystal Oscillator Ready Mode */
+
+/* X Address Space aliases of SFR Address Space Registers */
+
+#if defined AX8052F143_H && !defined AX5043_DISABLE_XSFR
+SFR16LEX(XDPTR0, 0x3F82) /* Data Pointer 0 */
+SFR16LEX(XDPTR1, 0x3F84) /* Data Pointer 1 */
+SFRX(XIE, 0x3FA8) /* Interrupt Enable */
+SFRX(XIP, 0x3FB8) /* Interrupt Priority */
+SFRX(XPCON, 0x3F87) /* Power Mode Control */
+SFRX(XADCCH0CONFIG, 0x3FCA) /* ADC Channel 0 Configuration */
+SFRX(XADCCH1CONFIG, 0x3FCB) /* ADC Channel 1 Configuration */
+SFRX(XADCCH2CONFIG, 0x3FD2) /* ADC Channel 2 Configuration */
+SFRX(XADCCH3CONFIG, 0x3FD3) /* ADC Channel 3 Configuration */
+SFRX(XADCCLKSRC, 0x3FD1) /* ADC Clock Source */
+SFRX(XADCCONV, 0x3FC9) /* ADC Conversion Source */
+SFRX(XANALOGCOMP, 0x3FE1) /* Analog Comparators */
+SFRX(XCLKCON, 0x3FC6) /* Clock Control */
+SFRX(XCLKSTAT, 0x3FC7) /* Clock Status */
+SFRX(XCODECONFIG, 0x3F97) /* Code Space Configuration */
+SFRX(XDBGLNKBUF, 0x3FE3) /* Debug Link Buffer */
+SFRX(XDBGLNKSTAT, 0x3FE2) /* Debug Link Status */
+SFRX(XDIRA, 0x3F89) /* Port A Direction */
+SFRX(XDIRB, 0x3F8A) /* Port B Direction */
+SFRX(XDIRC, 0x3F8B) /* Port C Direction */
+SFRX(XDIRR, 0x3F8E) /* Port R Direction */
+SFRX(XPINA, 0x3FC8) /* Port A Input */
+SFRX(XPINB, 0x3FE8) /* Port B Input */
+SFRX(XPINC, 0x3FF8) /* Port C Input */
+SFRX(XPINR, 0x3F8D) /* Port R Input */
+SFRX(XPORTA, 0x3F80) /* Port A Output */
+SFRX(XPORTB, 0x3F88) /* Port B Output */
+SFRX(XPORTC, 0x3F90) /* Port C Output */
+SFRX(XPORTR, 0x3F8C) /* Port R Output */
+SFRX(XIC0CAPT0, 0x3FCE) /* Input Capture 0 Low Byte */
+SFRX(XIC0CAPT1, 0x3FCF) /* Input Capture 0 High Byte */
+SFR16LEX(XIC0CAPT, 0x3FCE) /* Input Capture 0 */
+SFRX(XIC0MODE, 0x3FCC) /* Input Capture 0 Mode */
+SFRX(XIC0STATUS, 0x3FCD) /* Input Capture 0 Status */
+SFRX(XIC1CAPT0, 0x3FD6) /* Input Capture 1 Low Byte */
+SFRX(XIC1CAPT1, 0x3FD7) /* Input Capture 1 High Byte */
+SFR16LEX(XIC1CAPT, 0x3FD6) /* Input Capture 1 */
+SFRX(XIC1MODE, 0x3FD4) /* Input Capture 1 Mode */
+SFRX(XIC1STATUS, 0x3FD5) /* Input Capture 1 Status */
+SFRX(XNVADDR0, 0x3F92) /* Non-Volatile Memory Address Low Byte */
+SFRX(XNVADDR1, 0x3F93) /* Non-Volatile Memory Address High Byte */
+SFR16LEX(XNVADDR, 0x3F92) /* Non-Volatile Memory Address */
+SFRX(XNVDATA0, 0x3F94) /* Non-Volatile Memory Data Low Byte */
+SFRX(XNVDATA1, 0x3F95) /* Non-Volatile Memory Data High Byte */
+SFR16LEX(XNVDATA, 0x3F94) /* Non-Volatile Memory Data */
+SFRX(XNVKEY, 0x3F96) /* Non-Volatile Memory Write/Erase Key */
+SFRX(XNVSTATUS, 0x3F91) /* Non-Volatile Memory Command / Status */
+SFRX(XOC0COMP0, 0x3FBC) /* Output Compare 0 Low Byte */
+SFRX(XOC0COMP1, 0x3FBD) /* Output Compare 0 High Byte */
+SFR16LEX(XOC0COMP, 0x3FBC) /* Output Compare 0 */
+SFRX(XOC0MODE, 0x3FB9) /* Output Compare 0 Mode */
+SFRX(XOC0PIN, 0x3FBA) /* Output Compare 0 Pin Configuration */
+SFRX(XOC0STATUS, 0x3FBB) /* Output Compare 0 Status */
+SFRX(XOC1COMP0, 0x3FC4) /* Output Compare 1 Low Byte */
+SFRX(XOC1COMP1, 0x3FC5) /* Output Compare 1 High Byte */
+SFR16LEX(XOC1COMP, 0x3FC4) /* Output Compare 1 */
+SFRX(XOC1MODE, 0x3FC1) /* Output Compare 1 Mode */
+SFRX(XOC1PIN, 0x3FC2) /* Output Compare 1 Pin Configuration */
+SFRX(XOC1STATUS, 0x3FC3) /* Output Compare 1 Status */
+SFRX(XRADIOACC, 0x3FB1) /* Radio Controller Access Mode */
+SFRX(XRADIOADDR0, 0x3FB3) /* Radio Register Address Low Byte */
+SFRX(XRADIOADDR1, 0x3FB2) /* Radio Register Address High Byte */
+SFRX(XRADIODATA0, 0x3FB7) /* Radio Register Data 0 */
+SFRX(XRADIODATA1, 0x3FB6) /* Radio Register Data 1 */
+SFRX(XRADIODATA2, 0x3FB5) /* Radio Register Data 2 */
+SFRX(XRADIODATA3, 0x3FB4) /* Radio Register Data 3 */
+SFRX(XRADIOSTAT0, 0x3FBE) /* Radio Access Status Low Byte */
+SFRX(XRADIOSTAT1, 0x3FBF) /* Radio Access Status High Byte */
+SFR16LEX(XRADIOSTAT, 0x3FBE) /* Radio Access Status */
+SFRX(XSPCLKSRC, 0x3FDF) /* SPI Clock Source */
+SFRX(XSPMODE, 0x3FDC) /* SPI Mode */
+SFRX(XSPSHREG, 0x3FDE) /* SPI Shift Register */
+SFRX(XSPSTATUS, 0x3FDD) /* SPI Status */
+SFRX(XT0CLKSRC, 0x3F9A) /* Timer 0 Clock Source */
+SFRX(XT0CNT0, 0x3F9C) /* Timer 0 Count Low Byte */
+SFRX(XT0CNT1, 0x3F9D) /* Timer 0 Count High Byte */
+SFR16LEX(XT0CNT, 0x3F9C) /* Timer 0 Count */
+SFRX(XT0MODE, 0x3F99) /* Timer 0 Mode */
+SFRX(XT0PERIOD0, 0x3F9E) /* Timer 0 Period Low Byte */
+SFRX(XT0PERIOD1, 0x3F9F) /* Timer 0 Period High Byte */
+SFR16LEX(XT0PERIOD, 0x3F9E) /* Timer 0 Period */
+SFRX(XT0STATUS, 0x3F9B) /* Timer 0 Status */
+SFRX(XT1CLKSRC, 0x3FA2) /* Timer 1 Clock Source */
+SFRX(XT1CNT0, 0x3FA4) /* Timer 1 Count Low Byte */
+SFRX(XT1CNT1, 0x3FA5) /* Timer 1 Count High Byte */
+SFR16LEX(XT1CNT, 0x3FA4) /* Timer 1 Count */
+SFRX(XT1MODE, 0x3FA1) /* Timer 1 Mode */
+SFRX(XT1PERIOD0, 0x3FA6) /* Timer 1 Period Low Byte */
+SFRX(XT1PERIOD1, 0x3FA7) /* Timer 1 Period High Byte */
+SFR16LEX(XT1PERIOD, 0x3FA6) /* Timer 1 Period */
+SFRX(XT1STATUS, 0x3FA3) /* Timer 1 Status */
+SFRX(XT2CLKSRC, 0x3FAA) /* Timer 2 Clock Source */
+SFRX(XT2CNT0, 0x3FAC) /* Timer 2 Count Low Byte */
+SFRX(XT2CNT1, 0x3FAD) /* Timer 2 Count High Byte */
+SFR16LEX(XT2CNT, 0x3FAC) /* Timer 2 Count */
+SFRX(XT2MODE, 0x3FA9) /* Timer 2 Mode */
+SFRX(XT2PERIOD0, 0x3FAE) /* Timer 2 Period Low Byte */
+SFRX(XT2PERIOD1, 0x3FAF) /* Timer 2 Period High Byte */
+SFR16LEX(XT2PERIOD, 0x3FAE) /* Timer 2 Period */
+SFRX(XT2STATUS, 0x3FAB) /* Timer 2 Status */
+SFRX(XU0CTRL, 0x3FE4) /* UART 0 Control */
+SFRX(XU0MODE, 0x3FE7) /* UART 0 Mode */
+SFRX(XU0SHREG, 0x3FE6) /* UART 0 Shift Register */
+SFRX(XU0STATUS, 0x3FE5) /* UART 0 Status */
+SFRX(XU1CTRL, 0x3FEC) /* UART 1 Control */
+SFRX(XU1MODE, 0x3FEF) /* UART 1 Mode */
+SFRX(XU1SHREG, 0x3FEE) /* UART 1 Shift Register */
+SFRX(XU1STATUS, 0x3FED) /* UART 1 Status */
+SFRX(XWDTCFG, 0x3FDA) /* Watchdog Configuration */
+SFRX(XWDTRESET, 0x3FDB) /* Watchdog Reset */
+SFRX(XWTCFGA, 0x3FF1) /* Wakeup Timer A Configuration */
+SFRX(XWTCFGB, 0x3FF9) /* Wakeup Timer B Configuration */
+SFRX(XWTCNTA0, 0x3FF2) /* Wakeup Counter A Low Byte */
+SFRX(XWTCNTA1, 0x3FF3) /* Wakeup Counter A High Byte */
+SFR16LEX(XWTCNTA, 0x3FF2) /* Wakeup Counter A */
+SFRX(XWTCNTB0, 0x3FFA) /* Wakeup Counter B Low Byte */
+SFRX(XWTCNTB1, 0x3FFB) /* Wakeup Counter B High Byte */
+SFR16LEX(XWTCNTB, 0x3FFA) /* Wakeup Counter B */
+SFRX(XWTCNTR1, 0x3FEB) /* Wakeup Counter High Byte Latch */
+SFRX(XWTEVTA0, 0x3FF4) /* Wakeup Event A Low Byte */
+SFRX(XWTEVTA1, 0x3FF5) /* Wakeup Event A High Byte */
+SFR16LEX(XWTEVTA, 0x3FF4) /* Wakeup Event A */
+SFRX(XWTEVTB0, 0x3FF6) /* Wakeup Event B Low Byte */
+SFRX(XWTEVTB1, 0x3FF7) /* Wakeup Event B High Byte */
+SFR16LEX(XWTEVTB, 0x3FF6) /* Wakeup Event B */
+SFRX(XWTEVTC0, 0x3FFC) /* Wakeup Event C Low Byte */
+SFRX(XWTEVTC1, 0x3FFD) /* Wakeup Event C High Byte */
+SFR16LEX(XWTEVTC, 0x3FFC) /* Wakeup Event C */
+SFRX(XWTEVTD0, 0x3FFE) /* Wakeup Event D Low Byte */
+SFRX(XWTEVTD1, 0x3FFF) /* Wakeup Event D High Byte */
+SFR16LEX(XWTEVTD, 0x3FFE) /* Wakeup Event D */
+SFRX(XWTIRQEN, 0x3FE9) /* Wakeup Timer Interrupt Enable */
+SFRX(XWTSTAT, 0x3FEA) /* Wakeup Timer Status */
+#endif
+
+/* Interrupt Numbers */
+
+#define INT_EXTERNAL0 0
+#define INT_WAKEUPTIMER 1
+#define INT_EXTERNAL1 2
+#define INT_GPIO 3
+#define INT_RADIO 4
+#define INT_CLOCKMGMT 5
+#define INT_POWERMGMT 6
+#define INT_TIMER0 7
+#define INT_TIMER1 8
+#define INT_TIMER2 9
+#define INT_SPI0 10
+#define INT_UART0 11
+#define INT_UART1 12
+#define INT_GPADC 13
+#define INT_DMA 14
+#define INT_OUTPUTCOMP0 15
+#define INT_OUTPUTCOMP1 16
+#define INT_INPUTCAPT0 17
+#define INT_INPUTCAPT1 18
+#define INT_DEBUGLINK 21
+
+/* DMA Sources */
+
+#define DMASOURCE_XRAMTOOTHER 0x00
+#define DMASOURCE_SPITX 0x01
+#define DMASOURCE_UART0TX 0x02
+#define DMASOURCE_UART1TX 0x03
+#define DMASOURCE_TIMER0 0x04
+#define DMASOURCE_TIMER1 0x05
+#define DMASOURCE_TIMER2 0x06
+#define DMASOURCE_RADIOTX 0x07
+#define DMASOURCE_OC0 0x08
+#define DMASOURCE_OC1 0x09
+#define DMASOURCE_OTHERTOXRAM 0x10
+#define DMASOURCE_SPIRX 0x11
+#define DMASOURCE_UART0RX 0x12
+#define DMASOURCE_UART1RX 0x13
+#define DMASOURCE_ADC 0x14
+#define DMASOURCE_RADIORX 0x17
+#define DMASOURCE_IC0 0x18
+#define DMASOURCE_IC1 0x19
+
+/* Silicon Revision Numbers */
+
+#define SILICONREVISION_V1 0x8E
+#define SILICONREVISION_V1C 0x8F
+
+#endif /* AX8052_H */
diff --git a/libs/libmf/include/ax8052f131.h b/libs/libmf/include/ax8052f131.h
new file mode 100644
index 00000000..402af3d7
--- /dev/null
+++ b/libs/libmf/include/ax8052f131.h
@@ -0,0 +1,148 @@
+/*-------------------------------------------------------------------------
+ AX8052F131.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F131_H
+#define AX8052F131_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5031_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5031_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5031_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5031_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5031_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5031_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5031_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5031_FIFOCONTROL2, 0x4037) /* FIFO Control 2 */
+SFRX(AX5031_FIFOCOUNT, 0x4035) /* FIFO Count */
+SFRX(AX5031_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5031_FIFOTHRESH, 0x4036) /* FIFO Threshold */
+SFRX(AX5031_FOURFSK, 0x4050) /* 4-FSK Control */
+SFRX(AX5031_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5031_FREQA0, 0x4023) /* Frequency A 0 */
+SFRX(AX5031_FREQA1, 0x4022) /* Frequency A 1 */
+SFRX(AX5031_FREQA2, 0x4021) /* Frequency A 2 */
+SFRX(AX5031_FREQA3, 0x4020) /* Frequency A 3 */
+SFRX(AX5031_FREQB0, 0x401F) /* Frequency B 0 */
+SFRX(AX5031_FREQB1, 0x401E) /* Frequency B 1 */
+SFRX(AX5031_FREQB2, 0x401D) /* Frequency B 2 */
+SFRX(AX5031_FREQB3, 0x401C) /* Frequency B 3 */
+SFRX(AX5031_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5031_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5031_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5031_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5031_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5031_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5031_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5031_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5031_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5031_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5031_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5031_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5031_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5031_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5031_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5031_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5031_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5031_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5031_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5031_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5031_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5031_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5031_VREG, 0x401B) /* Voltage Regulator */
+SFRX(AX5031_XTALCAP, 0x404F) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5031_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+SFRX(AX5031_XTALOSCCFG, 0x4051) /* Crystal Oscillator Mode Configuration */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5031_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5031_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5031_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5031_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5031_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5031_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5031_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5031_FIFOCONTROL2NB, 0x5037) /* FIFO Control 2, Non-Blocking */
+SFRX(AX5031_FIFOCOUNTNB, 0x5035) /* FIFO Count, Non-Blocking */
+SFRX(AX5031_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5031_FIFOTHRESHNB, 0x5036) /* FIFO Threshold, Non-Blocking */
+SFRX(AX5031_FOURFSKNB, 0x5050) /* 4-FSK Control, Non-Blocking */
+SFRX(AX5031_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5031_FREQA0NB, 0x5023) /* Frequency A 0, Non-Blocking */
+SFRX(AX5031_FREQA1NB, 0x5022) /* Frequency A 1, Non-Blocking */
+SFRX(AX5031_FREQA2NB, 0x5021) /* Frequency A 2, Non-Blocking */
+SFRX(AX5031_FREQA3NB, 0x5020) /* Frequency A 3, Non-Blocking */
+SFRX(AX5031_FREQB0NB, 0x501F) /* Frequency B 0, Non-Blocking */
+SFRX(AX5031_FREQB1NB, 0x501E) /* Frequency B 1, Non-Blocking */
+SFRX(AX5031_FREQB2NB, 0x501D) /* Frequency B 2, Non-Blocking */
+SFRX(AX5031_FREQB3NB, 0x501C) /* Frequency B 3, Non-Blocking */
+SFRX(AX5031_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5031_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5031_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5031_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5031_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5031_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5031_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5031_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5031_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5031_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5031_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5031_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5031_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5031_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5031_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5031_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5031_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5031_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5031_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5031_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5031_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5031_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5031_VREGNB, 0x501B) /* Voltage Regulator, Non-Blocking */
+SFRX(AX5031_XTALCAPNB, 0x504F) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5031_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+SFRX(AX5031_XTALOSCCFGNB, 0x5051) /* Crystal Oscillator Mode Configuration, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5031_MODMISC AX5031_MODULATORMISC
+#define AX5031_TXRATEHI AX5031_TXBITRATEHI
+#define AX5031_TXRATELO AX5031_TXBITRATELO
+#define AX5031_TXRATEMID AX5031_TXBITRATEMID
+
+#define AX5031_MODMISCNB AX5031_MODULATORMISCNB
+#define AX5031_TXRATEHINB AX5031_TXBITRATEHINB
+#define AX5031_TXRATELONB AX5031_TXBITRATELONB
+#define AX5031_TXRATEMIDNB AX5031_TXBITRATEMIDNB
+
+#endif /* AX8052F131_H */
diff --git a/libs/libmf/include/ax8052f142.h b/libs/libmf/include/ax8052f142.h
new file mode 100644
index 00000000..6d0d8f8d
--- /dev/null
+++ b/libs/libmf/include/ax8052f142.h
@@ -0,0 +1,202 @@
+/*-------------------------------------------------------------------------
+ AX8052F142.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F142_H
+#define AX8052F142_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5042_ADCMISC, 0x4038) /* ADC Miscellaneous Control */
+SFRX(AX5042_AGCATTACK, 0x403A) /* AGC Attack Speed */
+SFRX(AX5042_AGCCOUNTER, 0x403C) /* AGC Counter */
+SFRX(AX5042_AGCDECAY, 0x403B) /* AGC Decay Speed */
+SFRX(AX5042_AGCTARGET, 0x4039) /* AGC Target Value */
+SFRX(AX5042_AMPLITUDEGAIN, 0x4047) /* Amplitude Estimator Bandwidth */
+SFRX(AX5042_APEOVERRIDE, 0x4070) /* APE Override */
+SFRX(AX5042_CICDECHI, 0x403E) /* Decimation Factor High */
+SFRX(AX5042_CICDECLO, 0x403F) /* Decimation Factor Low */
+SFRX(AX5042_CICSHIFT, 0x403D) /* Decimation Filter Attenuation */
+SFRX(AX5042_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5042_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5042_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5042_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5042_DATARATEHI, 0x4040) /* Datarate High */
+SFRX(AX5042_DATARATELO, 0x4041) /* Datarate Low */
+SFRX(AX5042_DSPMODE, 0x4009) /* DSP Mode Interface Control */
+SFRX(AX5042_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5042_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5042_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5042_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5042_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5042_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5042_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5042_FREQ0, 0x4023) /* Frequency 0 */
+SFRX(AX5042_FREQ1, 0x4022) /* Frequency 1 */
+SFRX(AX5042_FREQ2, 0x4021) /* Frequency 2 */
+SFRX(AX5042_FREQ3, 0x4020) /* Frequency 3 */
+SFRX(AX5042_FREQUENCYGAIN, 0x4045) /* Frequency Estimator Bandwidth */
+SFRX(AX5042_FREQUENCYGAIN2, 0x4046) /* Frequency Estimator Bandwidth 2 */
+SFRX(AX5042_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5042_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5042_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5042_IFFREQHI, 0x4028) /* IF Frequency Low */
+SFRX(AX5042_IFFREQLO, 0x4029) /* IF Frequency High */
+SFRX(AX5042_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5042_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5042_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5042_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5042_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5042_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5042_PHASEGAIN, 0x4044) /* Phase Estimator Bandwidth */
+SFRX(AX5042_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5042_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5042_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5042_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5042_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5042_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5042_PLLRNGMISC, 0x4074) /* PLL Autoranging Miscellaneous */
+SFRX(AX5042_PLLVCOI, 0x4072) /* PLL VCO Current */
+SFRX(AX5042_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5042_REF, 0x407C) /* Reference */
+SFRX(AX5042_RXMISC, 0x407D) /* Receiver Miscellaneous Control */
+SFRX(AX5042_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5042_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5042_TIMINGGAINHI, 0x4042) /* Timing Estimator Bandwidth High */
+SFRX(AX5042_TIMINGGAINLO, 0x4043) /* Timing Estimator Bandwidth Low */
+SFRX(AX5042_TRKAMPLITUDEHI, 0x4048) /* Amplitude Tracking High */
+SFRX(AX5042_TRKAMPLITUDELO, 0x4049) /* Amplitude Tracking Low */
+SFRX(AX5042_TRKFREQHI, 0x404C) /* Frequency Tracking High */
+SFRX(AX5042_TRKFREQLO, 0x404D) /* Frequency Tracking Low */
+SFRX(AX5042_TRKPHASEHI, 0x404A) /* Phase Tracking High */
+SFRX(AX5042_TRKPHASELO, 0x404B) /* Phase Tracking Low */
+SFRX(AX5042_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5042_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5042_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5042_TXDSPMODE, 0x400A) /* Transmit DSP Mode */
+SFRX(AX5042_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5042_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5042_ADCMISCNB, 0x5038) /* ADC Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_AGCATTACKNB, 0x503A) /* AGC Attack Speed, Non-Blocking */
+SFRX(AX5042_AGCCOUNTERNB, 0x503C) /* AGC Counter, Non-Blocking */
+SFRX(AX5042_AGCDECAYNB, 0x503B) /* AGC Decay Speed, Non-Blocking */
+SFRX(AX5042_AGCTARGETNB, 0x5039) /* AGC Target Value, Non-Blocking */
+SFRX(AX5042_AMPLITUDEGAINNB, 0x5047) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_APEOVERRIDENB, 0x5070) /* APE Override, Non-Blocking */
+SFRX(AX5042_CICDECHINB, 0x503E) /* Decimation Factor High, Non-Blocking */
+SFRX(AX5042_CICDECLONB, 0x503F) /* Decimation Factor Low, Non-Blocking */
+SFRX(AX5042_CICSHIFTNB, 0x503D) /* Decimation Filter Attenuation, Non-Blocking */
+SFRX(AX5042_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5042_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5042_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5042_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5042_DATARATEHINB, 0x5040) /* Datarate High, Non-Blocking */
+SFRX(AX5042_DATARATELONB, 0x5041) /* Datarate Low, Non-Blocking */
+SFRX(AX5042_DSPMODENB, 0x5009) /* DSP Mode Interface Control, Non-Blocking */
+SFRX(AX5042_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5042_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5042_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5042_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5042_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5042_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5042_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5042_FREQ0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5042_FREQ1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5042_FREQ2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5042_FREQ3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5042_FREQUENCYGAINNB, 0x5045) /* Frequency Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_FREQUENCYGAIN2NB, 0x5046) /* Frequency Estimator Bandwidth 2, Non-Blocking */
+SFRX(AX5042_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5042_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5042_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5042_IFFREQHINB, 0x5028) /* IF Frequency Low, Non-Blocking */
+SFRX(AX5042_IFFREQLONB, 0x5029) /* IF Frequency High, Non-Blocking */
+SFRX(AX5042_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5042_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5042_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5042_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5042_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5042_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_PHASEGAINNB, 0x5044) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5042_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5042_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5042_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5042_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5042_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5042_PLLRNGMISCNB, 0x5074) /* PLL Autoranging Miscellaneous, Non-Blocking */
+SFRX(AX5042_PLLVCOINB, 0x5072) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5042_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5042_REFNB, 0x507C) /* Reference, Non-Blocking */
+SFRX(AX5042_RXMISCNB, 0x507D) /* Receiver Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5042_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5042_TIMINGGAINHINB, 0x5042) /* Timing Estimator Bandwidth High, Non-Blocking */
+SFRX(AX5042_TIMINGGAINLONB, 0x5043) /* Timing Estimator Bandwidth Low, Non-Blocking */
+SFRX(AX5042_TRKAMPLITUDEHINB, 0x5048) /* Amplitude Tracking High, Non-Blocking */
+SFRX(AX5042_TRKAMPLITUDELONB, 0x5049) /* Amplitude Tracking Low, Non-Blocking */
+SFRX(AX5042_TRKFREQHINB, 0x504C) /* Frequency Tracking High, Non-Blocking */
+SFRX(AX5042_TRKFREQLONB, 0x504D) /* Frequency Tracking Low, Non-Blocking */
+SFRX(AX5042_TRKPHASEHINB, 0x504A) /* Phase Tracking High, Non-Blocking */
+SFRX(AX5042_TRKPHASELONB, 0x504B) /* Phase Tracking Low, Non-Blocking */
+SFRX(AX5042_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5042_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5042_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5042_TXDSPMODENB, 0x500A) /* Transmit DSP Mode, Non-Blocking */
+SFRX(AX5042_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5042_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5042_AMPLGAIN AX5042_AMPLITUDEGAIN
+#define AX5042_FREQGAIN AX5042_FREQUENCYGAIN
+#define AX5042_FREQGAIN2 AX5042_FREQUENCYGAIN2
+#define AX5042_MODMISC AX5042_MODULATORMISC
+#define AX5042_TMGGAINHI AX5042_TIMINGGAINHI
+#define AX5042_TMGGAINLO AX5042_TIMINGGAINLO
+#define AX5042_TXRATEHI AX5042_TXBITRATEHI
+#define AX5042_TXRATELO AX5042_TXBITRATELO
+#define AX5042_TXRATEMID AX5042_TXBITRATEMID
+
+#define AX5042_AMPLGAINNB AX5042_AMPLITUDEGAINNB
+#define AX5042_FREQGAINNB AX5042_FREQUENCYGAINNB
+#define AX5042_FREQGAIN2NB AX5042_FREQUENCYGAIN2NB
+#define AX5042_MODMISCNB AX5042_MODULATORMISCNB
+#define AX5042_TMGGAINHINB AX5042_TIMINGGAINHINB
+#define AX5042_TMGGAINLONB AX5042_TIMINGGAINLONB
+#define AX5042_TXRATEHINB AX5042_TXBITRATEHINB
+#define AX5042_TXRATELONB AX5042_TXBITRATELONB
+#define AX5042_TXRATEMIDNB AX5042_TXBITRATEMIDNB
+
+#endif /* AX8052F142_H */
diff --git a/libs/libmf/include/ax8052f143.h b/libs/libmf/include/ax8052f143.h
new file mode 100644
index 00000000..9f46cd2f
--- /dev/null
+++ b/libs/libmf/include/ax8052f143.h
@@ -0,0 +1,885 @@
+/*-------------------------------------------------------------------------
+ ax8052f143.h - Register Declarations for the Axsem Integrated Radio
+
+ Copyright (C) 2010, 2011, 2012, 2014, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+#ifndef AX8052F143_H
+#define AX8052F143_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5043_AFSKCTRL, 0x4114) /* AFSK Control */
+SFRX(AX5043_AFSKMARK0, 0x4113) /* AFSK Mark (1) Frequency 0 */
+SFRX(AX5043_AFSKMARK1, 0x4112) /* AFSK Mark (1) Frequency 1 */
+SFRX(AX5043_AFSKSPACE0, 0x4111) /* AFSK Space (0) Frequency 0 */
+SFRX(AX5043_AFSKSPACE1, 0x4110) /* AFSK Space (0) Frequency 1 */
+SFRX(AX5043_AGCCOUNTER, 0x4043) /* AGC Counter */
+SFRX(AX5043_AMPLFILTER, 0x4115) /* Amplitude Filter */
+SFRX(AX5043_BBOFFSCAP, 0x4189) /* Baseband Offset Compensation Capacitors */
+SFRX(AX5043_BBTUNE, 0x4188) /* Baseband Tuning */
+SFRX(AX5043_BGNDRSSI, 0x4041) /* Background RSSI */
+SFRX(AX5043_BGNDRSSIGAIN, 0x422E) /* Background RSSI Averaging Time Constant */
+SFRX(AX5043_BGNDRSSITHR, 0x422F) /* Background RSSI Relative Threshold */
+SFRX(AX5043_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5043_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5043_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5043_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5043_DACCONFIG, 0x4332) /* DAC Configuration */
+SFRX(AX5043_DACVALUE0, 0x4331) /* DAC Value 0 */
+SFRX(AX5043_DACVALUE1, 0x4330) /* DAC Value 1 */
+SFRX(AX5043_DECIMATION, 0x4102) /* Decimation Factor */
+SFRX(AX5043_DIVERSITY, 0x4042) /* Antenna Diversity Configuration */
+SFRX(AX5043_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5043_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5043_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5043_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5043_FIFOCOUNT0, 0x402B) /* Number of Words currently in FIFO 0 */
+SFRX(AX5043_FIFOCOUNT1, 0x402A) /* Number of Words currently in FIFO 1 */
+SFRX(AX5043_FIFODATA, 0x4029) /* FIFO Data */
+SFRX(AX5043_FIFOFREE0, 0x402D) /* Number of Words that can be written to FIFO 0 */
+SFRX(AX5043_FIFOFREE1, 0x402C) /* Number of Words that can be written to FIFO 1 */
+SFRX(AX5043_FIFOSTAT, 0x4028) /* FIFO Control */
+SFRX(AX5043_FIFOTHRESH0, 0x402F) /* FIFO Threshold 0 */
+SFRX(AX5043_FIFOTHRESH1, 0x402E) /* FIFO Threshold 1 */
+SFRX(AX5043_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5043_FREQA0, 0x4037) /* Frequency A 0 */
+SFRX(AX5043_FREQA1, 0x4036) /* Frequency A 1 */
+SFRX(AX5043_FREQA2, 0x4035) /* Frequency A 2 */
+SFRX(AX5043_FREQA3, 0x4034) /* Frequency A 3 */
+SFRX(AX5043_FREQB0, 0x403F) /* Frequency B 0 */
+SFRX(AX5043_FREQB1, 0x403E) /* Frequency B 1 */
+SFRX(AX5043_FREQB2, 0x403D) /* Frequency B 2 */
+SFRX(AX5043_FREQB3, 0x403C) /* Frequency B 3 */
+SFRX(AX5043_FSKDEV0, 0x4163) /* FSK Deviation 0 */
+SFRX(AX5043_FSKDEV1, 0x4162) /* FSK Deviation 1 */
+SFRX(AX5043_FSKDEV2, 0x4161) /* FSK Deviation 2 */
+SFRX(AX5043_FSKDMAX0, 0x410D) /* Four FSK Rx Maximum Deviation 0 */
+SFRX(AX5043_FSKDMAX1, 0x410C) /* Four FSK Rx Maximum Deviation 1 */
+SFRX(AX5043_FSKDMIN0, 0x410F) /* Four FSK Rx Minimum Deviation 0 */
+SFRX(AX5043_FSKDMIN1, 0x410E) /* Four FSK Rx Minimum Deviation 1 */
+SFRX(AX5043_GPADC13VALUE0, 0x4309) /* GPADC13 Value 0 */
+SFRX(AX5043_GPADC13VALUE1, 0x4308) /* GPADC13 Value 1 */
+SFRX(AX5043_GPADCCTRL, 0x4300) /* General Purpose ADC Control */
+SFRX(AX5043_GPADCPERIOD, 0x4301) /* GPADC Sampling Period */
+SFRX(AX5043_IFFREQ0, 0x4101) /* 2nd LO / IF Frequency 0 */
+SFRX(AX5043_IFFREQ1, 0x4100) /* 2nd LO / IF Frequency 1 */
+SFRX(AX5043_IRQINVERSION0, 0x400B) /* IRQ Inversion 0 */
+SFRX(AX5043_IRQINVERSION1, 0x400A) /* IRQ Inversion 1 */
+SFRX(AX5043_IRQMASK0, 0x4007) /* IRQ Mask 0 */
+SFRX(AX5043_IRQMASK1, 0x4006) /* IRQ Mask 1 */
+SFRX(AX5043_IRQREQUEST0, 0x400D) /* IRQ Request 0 */
+SFRX(AX5043_IRQREQUEST1, 0x400C) /* IRQ Request 1 */
+SFRX(AX5043_LPOSCCONFIG, 0x4310) /* Low Power Oscillator Calibration Configuration */
+SFRX(AX5043_LPOSCFREQ0, 0x4317) /* Low Power Oscillator Frequency Tuning Low Byte */
+SFRX(AX5043_LPOSCFREQ1, 0x4316) /* Low Power Oscillator Frequency Tuning High Byte */
+SFRX(AX5043_LPOSCKFILT0, 0x4313) /* Low Power Oscillator Calibration Filter Constant Low Byte */
+SFRX(AX5043_LPOSCKFILT1, 0x4312) /* Low Power Oscillator Calibration Filter Constant High Byte */
+SFRX(AX5043_LPOSCPER0, 0x4319) /* Low Power Oscillator Period Low Byte */
+SFRX(AX5043_LPOSCPER1, 0x4318) /* Low Power Oscillator Period High Byte */
+SFRX(AX5043_LPOSCREF0, 0x4315) /* Low Power Oscillator Reference Frequency Low Byte */
+SFRX(AX5043_LPOSCREF1, 0x4314) /* Low Power Oscillator Reference Frequency High Byte */
+SFRX(AX5043_LPOSCSTATUS, 0x4311) /* Low Power Oscillator Calibration Status */
+SFRX(AX5043_MATCH0LEN, 0x4214) /* Pattern Match Unit 0, Pattern Length */
+SFRX(AX5043_MATCH0MAX, 0x4216) /* Pattern Match Unit 0, Maximum Match */
+SFRX(AX5043_MATCH0MIN, 0x4215) /* Pattern Match Unit 0, Minimum Match */
+SFRX(AX5043_MATCH0PAT0, 0x4213) /* Pattern Match Unit 0, Pattern 0 */
+SFRX(AX5043_MATCH0PAT1, 0x4212) /* Pattern Match Unit 0, Pattern 1 */
+SFRX(AX5043_MATCH0PAT2, 0x4211) /* Pattern Match Unit 0, Pattern 2 */
+SFRX(AX5043_MATCH0PAT3, 0x4210) /* Pattern Match Unit 0, Pattern 3 */
+SFRX(AX5043_MATCH1LEN, 0x421C) /* Pattern Match Unit 1, Pattern Length */
+SFRX(AX5043_MATCH1MAX, 0x421E) /* Pattern Match Unit 1, Maximum Match */
+SFRX(AX5043_MATCH1MIN, 0x421D) /* Pattern Match Unit 1, Minimum Match */
+SFRX(AX5043_MATCH1PAT0, 0x4219) /* Pattern Match Unit 1, Pattern 0 */
+SFRX(AX5043_MATCH1PAT1, 0x4218) /* Pattern Match Unit 1, Pattern 1 */
+SFRX(AX5043_MAXDROFFSET0, 0x4108) /* Maximum Receiver Datarate Offset 0 */
+SFRX(AX5043_MAXDROFFSET1, 0x4107) /* Maximum Receiver Datarate Offset 1 */
+SFRX(AX5043_MAXDROFFSET2, 0x4106) /* Maximum Receiver Datarate Offset 2 */
+SFRX(AX5043_MAXRFOFFSET0, 0x410B) /* Maximum Receiver RF Offset 0 */
+SFRX(AX5043_MAXRFOFFSET1, 0x410A) /* Maximum Receiver RF Offset 1 */
+SFRX(AX5043_MAXRFOFFSET2, 0x4109) /* Maximum Receiver RF Offset 2 */
+SFRX(AX5043_MODCFGA, 0x4164) /* Modulator Configuration A */
+SFRX(AX5043_MODCFGF, 0x4160) /* Modulator Configuration F */
+SFRX(AX5043_MODCFGP, 0x4F5F) /* Modulator Configuration P */
+SFRX(AX5043_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5043_PINFUNCANTSEL, 0x4025) /* Pin Function ANTSEL */
+SFRX(AX5043_PINFUNCDATA, 0x4023) /* Pin Function DATA */
+SFRX(AX5043_PINFUNCDCLK, 0x4022) /* Pin Function DCLK */
+SFRX(AX5043_PINFUNCIRQ, 0x4024) /* Pin Function IRQ */
+SFRX(AX5043_PINFUNCPWRAMP, 0x4026) /* Pin Function PWRAMP */
+SFRX(AX5043_PINFUNCSYSCLK, 0x4021) /* Pin Function SYSCLK */
+SFRX(AX5043_PINSTATE, 0x4020) /* Pin State */
+SFRX(AX5043_PKTACCEPTFLAGS, 0x4233) /* Packet Controller Accept Flags */
+SFRX(AX5043_PKTCHUNKSIZE, 0x4230) /* Packet Chunk Size */
+SFRX(AX5043_PKTMISCFLAGS, 0x4231) /* Packet Controller Miscellaneous Flags */
+SFRX(AX5043_PKTSTOREFLAGS, 0x4232) /* Packet Controller Store Flags */
+SFRX(AX5043_PLLCPI, 0x4031) /* PLL Charge Pump Current */
+SFRX(AX5043_PLLCPIBOOST, 0x4039) /* PLL Charge Pump Current (Boosted) */
+SFRX(AX5043_PLLLOCKDET, 0x4182) /* PLL Lock Detect Delay */
+SFRX(AX5043_PLLLOOP, 0x4030) /* PLL Loop Filter Settings */
+SFRX(AX5043_PLLLOOPBOOST, 0x4038) /* PLL Loop Filter Settings (Boosted) */
+SFRX(AX5043_PLLRANGINGA, 0x4033) /* PLL Autoranging A */
+SFRX(AX5043_PLLRANGINGB, 0x403B) /* PLL Autoranging B */
+SFRX(AX5043_PLLRNGCLK, 0x4183) /* PLL Autoranging Clock */
+SFRX(AX5043_PLLVCODIV, 0x4032) /* PLL Divider Settings */
+SFRX(AX5043_PLLVCOI, 0x4180) /* PLL VCO Current */
+SFRX(AX5043_PLLVCOIR, 0x4181) /* PLL VCO Current Readback */
+SFRX(AX5043_POWCTRL1, 0x4F08) /* Power Control 1 */
+SFRX(AX5043_POWIRQMASK, 0x4005) /* Power Management Interrupt Mask */
+SFRX(AX5043_POWSTAT, 0x4003) /* Power Management Status */
+SFRX(AX5043_POWSTICKYSTAT, 0x4004) /* Power Management Sticky Status */
+SFRX(AX5043_PWRAMP, 0x4027) /* PWRAMP Control */
+SFRX(AX5043_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5043_RADIOEVENTMASK0, 0x4009) /* Radio Event Mask 0 */
+SFRX(AX5043_RADIOEVENTMASK1, 0x4008) /* Radio Event Mask 1 */
+SFRX(AX5043_RADIOEVENTREQ0, 0x400F) /* Radio Event Request 0 */
+SFRX(AX5043_RADIOEVENTREQ1, 0x400E) /* Radio Event Request 1 */
+SFRX(AX5043_RADIOSTATE, 0x401C) /* Radio Controller State */
+SFRX(AX5043_REF, 0x4F0D) /* Reference */
+SFRX(AX5043_RSSI, 0x4040) /* Received Signal Strength Indicator */
+SFRX(AX5043_RSSIABSTHR, 0x422D) /* RSSI Absolute Threshold */
+SFRX(AX5043_RSSIREFERENCE, 0x422C) /* RSSI Offset */
+SFRX(AX5043_RXDATARATE0, 0x4105) /* Receiver Datarate 0 */
+SFRX(AX5043_RXDATARATE1, 0x4104) /* Receiver Datarate 1 */
+SFRX(AX5043_RXDATARATE2, 0x4103) /* Receiver Datarate 2 */
+SFRX(AX5043_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5043_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5043_TIMER0, 0x405B) /* 1MHz Timer 0 */
+SFRX(AX5043_TIMER1, 0x405A) /* 1MHz Timer 1 */
+SFRX(AX5043_TIMER2, 0x4059) /* 1MHz Timer 2 */
+SFRX(AX5043_TMGRXAGC, 0x4227) /* Receiver AGC Settling Time */
+SFRX(AX5043_TMGRXBOOST, 0x4223) /* Receive PLL Boost Time */
+SFRX(AX5043_TMGRXCOARSEAGC, 0x4226) /* Receive Coarse AGC Time */
+SFRX(AX5043_TMGRXOFFSACQ, 0x4225) /* Receive Baseband DC Offset Acquisition Time */
+SFRX(AX5043_TMGRXPREAMBLE1, 0x4229) /* Receiver Preamble 1 Timeout */
+SFRX(AX5043_TMGRXPREAMBLE2, 0x422A) /* Receiver Preamble 2 Timeout */
+SFRX(AX5043_TMGRXPREAMBLE3, 0x422B) /* Receiver Preamble 3 Timeout */
+SFRX(AX5043_TMGRXRSSI, 0x4228) /* Receiver RSSI Settling Time */
+SFRX(AX5043_TMGRXSETTLE, 0x4224) /* Receive PLL (post Boost) Settling Time */
+SFRX(AX5043_TMGTXBOOST, 0x4220) /* Transmit PLL Boost Time */
+SFRX(AX5043_TMGTXSETTLE, 0x4221) /* Transmit PLL (post Boost) Settling Time */
+SFRX(AX5043_TRKAFSKDEMOD0, 0x4055) /* AFSK Demodulator Tracking 0 */
+SFRX(AX5043_TRKAFSKDEMOD1, 0x4054) /* AFSK Demodulator Tracking 1 */
+SFRX(AX5043_TRKAMPLITUDE0, 0x4049) /* Amplitude Tracking 0 */
+SFRX(AX5043_TRKAMPLITUDE1, 0x4048) /* Amplitude Tracking 1 */
+SFRX(AX5043_TRKDATARATE0, 0x4047) /* Datarate Tracking 0 */
+SFRX(AX5043_TRKDATARATE1, 0x4046) /* Datarate Tracking 1 */
+SFRX(AX5043_TRKDATARATE2, 0x4045) /* Datarate Tracking 2 */
+SFRX(AX5043_TRKFREQ0, 0x4051) /* Frequency Tracking 0 */
+SFRX(AX5043_TRKFREQ1, 0x4050) /* Frequency Tracking 1 */
+SFRX(AX5043_TRKFSKDEMOD0, 0x4053) /* FSK Demodulator Tracking 0 */
+SFRX(AX5043_TRKFSKDEMOD1, 0x4052) /* FSK Demodulator Tracking 1 */
+SFRX(AX5043_TRKPHASE0, 0x404B) /* Phase Tracking 0 */
+SFRX(AX5043_TRKPHASE1, 0x404A) /* Phase Tracking 1 */
+SFRX(AX5043_TRKRFFREQ0, 0x404F) /* RF Frequency Tracking 0 */
+SFRX(AX5043_TRKRFFREQ1, 0x404E) /* RF Frequency Tracking 1 */
+SFRX(AX5043_TRKRFFREQ2, 0x404D) /* RF Frequency Tracking 2 */
+SFRX(AX5043_TXPWRCOEFFA0, 0x4169) /* Transmitter Predistortion Coefficient A 0 */
+SFRX(AX5043_TXPWRCOEFFA1, 0x4168) /* Transmitter Predistortion Coefficient A 1 */
+SFRX(AX5043_TXPWRCOEFFB0, 0x416B) /* Transmitter Predistortion Coefficient B 0 */
+SFRX(AX5043_TXPWRCOEFFB1, 0x416A) /* Transmitter Predistortion Coefficient B 1 */
+SFRX(AX5043_TXPWRCOEFFC0, 0x416D) /* Transmitter Predistortion Coefficient C 0 */
+SFRX(AX5043_TXPWRCOEFFC1, 0x416C) /* Transmitter Predistortion Coefficient C 1 */
+SFRX(AX5043_TXPWRCOEFFD0, 0x416F) /* Transmitter Predistortion Coefficient D 0 */
+SFRX(AX5043_TXPWRCOEFFD1, 0x416E) /* Transmitter Predistortion Coefficient D 1 */
+SFRX(AX5043_TXPWRCOEFFE0, 0x4171) /* Transmitter Predistortion Coefficient E 0 */
+SFRX(AX5043_TXPWRCOEFFE1, 0x4170) /* Transmitter Predistortion Coefficient E 1 */
+SFRX(AX5043_TXRATE0, 0x4167) /* Transmitter Bitrate 0 */
+SFRX(AX5043_TXRATE1, 0x4166) /* Transmitter Bitrate 1 */
+SFRX(AX5043_TXRATE2, 0x4165) /* Transmitter Bitrate 2 */
+SFRX(AX5043_WAKEUP0, 0x406B) /* Wakeup Time 0 */
+SFRX(AX5043_WAKEUP1, 0x406A) /* Wakeup Time 1 */
+SFRX(AX5043_WAKEUPFREQ0, 0x406D) /* Wakeup Frequency 0 */
+SFRX(AX5043_WAKEUPFREQ1, 0x406C) /* Wakeup Frequency 1 */
+SFRX(AX5043_WAKEUPTIMER0, 0x4069) /* Wakeup Timer 0 */
+SFRX(AX5043_WAKEUPTIMER1, 0x4068) /* Wakeup Timer 1 */
+SFRX(AX5043_WAKEUPXOEARLY, 0x406E) /* Wakeup Crystal Oscillator Early */
+SFRX(AX5043_XTALAMPL, 0x4F11) /* Crystal Oscillator Amplitude Control */
+SFRX(AX5043_XTALCAP, 0x4184) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5043_XTALOSC, 0x4F10) /* Crystal Oscillator Control */
+SFRX(AX5043_XTALSTATUS, 0x401D) /* Crystal Oscillator Status */
+
+SFRX(AX5043_0xF00, 0x4F00)
+SFRX(AX5043_0xF0C, 0x4F0C)
+SFRX(AX5043_0xF18, 0x4F18)
+SFRX(AX5043_0xF1C, 0x4F1C)
+SFRX(AX5043_0xF21, 0x4F21)
+SFRX(AX5043_0xF22, 0x4F22)
+SFRX(AX5043_0xF23, 0x4F23)
+SFRX(AX5043_0xF26, 0x4F26)
+SFRX(AX5043_0xF30, 0x4F30)
+SFRX(AX5043_0xF31, 0x4F31)
+SFRX(AX5043_0xF32, 0x4F32)
+SFRX(AX5043_0xF33, 0x4F33)
+SFRX(AX5043_0xF34, 0x4F34)
+SFRX(AX5043_0xF35, 0x4F35)
+SFRX(AX5043_0xF44, 0x4F44)
+
+#if defined AX5043V1
+SFRX(AX5043_AGCGAIN0_V1, 0x4120) /* AGC Speed */
+SFRX(AX5043_AGCGAIN1_V1, 0x412E) /* AGC Speed */
+SFRX(AX5043_AGCGAIN2_V1, 0x413C) /* AGC Speed */
+SFRX(AX5043_AGCGAIN3_V1, 0x414A) /* AGC Speed */
+SFRX(AX5043_AGCTARGET0_V1, 0x4121) /* AGC Target */
+SFRX(AX5043_AGCTARGET1_V1, 0x412F) /* AGC Target */
+SFRX(AX5043_AGCTARGET2_V1, 0x413D) /* AGC Target */
+SFRX(AX5043_AGCTARGET3_V1, 0x414B) /* AGC Target */
+SFRX(AX5043_AMPLITUDEGAIN0_V1, 0x4129) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN1_V1, 0x4137) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN2_V1, 0x4145) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN3_V1, 0x4153) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_BBOFFSRES0_V1, 0x412D) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES1_V1, 0x413B) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES2_V1, 0x4149) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES3_V1, 0x4157) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_DRGAIN0_V1, 0x4123) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN1_V1, 0x4131) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN2_V1, 0x413F) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN3_V1, 0x414D) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_FOURFSK0_V1, 0x412C) /* Four FSK Control */
+SFRX(AX5043_FOURFSK1_V1, 0x413A) /* Four FSK Control */
+SFRX(AX5043_FOURFSK2_V1, 0x4148) /* Four FSK Control */
+SFRX(AX5043_FOURFSK3_V1, 0x4156) /* Four FSK Control */
+SFRX(AX5043_FREQDEV00_V1, 0x412B) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV01_V1, 0x4139) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV02_V1, 0x4147) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV03_V1, 0x4155) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV10_V1, 0x412A) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV11_V1, 0x4138) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV12_V1, 0x4146) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV13_V1, 0x4154) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQUENCYGAINA0_V1, 0x4125) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA1_V1, 0x4133) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA2_V1, 0x4141) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA3_V1, 0x414F) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINB0_V1, 0x4126) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB1_V1, 0x4134) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB2_V1, 0x4142) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB3_V1, 0x4150) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINC0_V1, 0x4127) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC1_V1, 0x4135) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC2_V1, 0x4143) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC3_V1, 0x4151) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAIND0_V1, 0x4128) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND1_V1, 0x4136) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND2_V1, 0x4144) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND3_V1, 0x4152) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_PHASEGAIN0_V1, 0x4124) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN1_V1, 0x4132) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN2_V1, 0x4140) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN3_V1, 0x414E) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PKTADDR0_V1, 0x4203) /* Packet Address 0 */
+SFRX(AX5043_PKTADDR1_V1, 0x4202) /* Packet Address 1 */
+SFRX(AX5043_PKTADDRCFG_V1, 0x4201) /* Packet Address Config */
+SFRX(AX5043_PKTADDRMASK0_V1, 0x4205) /* Packet Address Mask 0 */
+SFRX(AX5043_PKTADDRMASK1_V1, 0x4204) /* Packet Address Mask 1 */
+SFRX(AX5043_PKTLENCFG_V1, 0x4206) /* Packet Length Configuration */
+SFRX(AX5043_PKTLENOFFSET_V1, 0x4207) /* Packet Length Offset */
+SFRX(AX5043_PKTMAXLEN_V1, 0x4208) /* Packet Maximum Length */
+SFRX(AX5043_RXPARAMCURSET_V1, 0x4117) /* Receiver Parameter Current Set */
+SFRX(AX5043_RXPARAMSETS_V1, 0x4116) /* Receiver Parameter Set Indirection */
+SFRX(AX5043_TIMEGAIN0_V1, 0x4122) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN1_V1, 0x4130) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN2_V1, 0x413E) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN3_V1, 0x414C) /* Time Estimator Bandwidth */
+
+#define AX5043_AGCGAIN0 AX5043_AGCGAIN0_V1
+#define AX5043_AGCGAIN1 AX5043_AGCGAIN1_V1
+#define AX5043_AGCGAIN2 AX5043_AGCGAIN2_V1
+#define AX5043_AGCGAIN3 AX5043_AGCGAIN3_V1
+#define AX5043_AGCTARGET0 AX5043_AGCTARGET0_V1
+#define AX5043_AGCTARGET1 AX5043_AGCTARGET1_V1
+#define AX5043_AGCTARGET2 AX5043_AGCTARGET2_V1
+#define AX5043_AGCTARGET3 AX5043_AGCTARGET3_V1
+#define AX5043_AMPLITUDEGAIN0 AX5043_AMPLITUDEGAIN0_V1
+#define AX5043_AMPLITUDEGAIN1 AX5043_AMPLITUDEGAIN1_V1
+#define AX5043_AMPLITUDEGAIN2 AX5043_AMPLITUDEGAIN2_V1
+#define AX5043_AMPLITUDEGAIN3 AX5043_AMPLITUDEGAIN3_V1
+#define AX5043_BBOFFSRES0 AX5043_BBOFFSRES0_V1
+#define AX5043_BBOFFSRES1 AX5043_BBOFFSRES1_V1
+#define AX5043_BBOFFSRES2 AX5043_BBOFFSRES2_V1
+#define AX5043_BBOFFSRES3 AX5043_BBOFFSRES3_V1
+#define AX5043_DRGAIN0 AX5043_DRGAIN0_V1
+#define AX5043_DRGAIN1 AX5043_DRGAIN1_V1
+#define AX5043_DRGAIN2 AX5043_DRGAIN2_V1
+#define AX5043_DRGAIN3 AX5043_DRGAIN3_V1
+#define AX5043_FOURFSK0 AX5043_FOURFSK0_V1
+#define AX5043_FOURFSK1 AX5043_FOURFSK1_V1
+#define AX5043_FOURFSK2 AX5043_FOURFSK2_V1
+#define AX5043_FOURFSK3 AX5043_FOURFSK3_V1
+#define AX5043_FREQDEV00 AX5043_FREQDEV00_V1
+#define AX5043_FREQDEV01 AX5043_FREQDEV01_V1
+#define AX5043_FREQDEV02 AX5043_FREQDEV02_V1
+#define AX5043_FREQDEV03 AX5043_FREQDEV03_V1
+#define AX5043_FREQDEV10 AX5043_FREQDEV10_V1
+#define AX5043_FREQDEV11 AX5043_FREQDEV11_V1
+#define AX5043_FREQDEV12 AX5043_FREQDEV12_V1
+#define AX5043_FREQDEV13 AX5043_FREQDEV13_V1
+#define AX5043_FREQUENCYGAINA0 AX5043_FREQUENCYGAINA0_V1
+#define AX5043_FREQUENCYGAINA1 AX5043_FREQUENCYGAINA1_V1
+#define AX5043_FREQUENCYGAINA2 AX5043_FREQUENCYGAINA2_V1
+#define AX5043_FREQUENCYGAINA3 AX5043_FREQUENCYGAINA3_V1
+#define AX5043_FREQUENCYGAINB0 AX5043_FREQUENCYGAINB0_V1
+#define AX5043_FREQUENCYGAINB1 AX5043_FREQUENCYGAINB1_V1
+#define AX5043_FREQUENCYGAINB2 AX5043_FREQUENCYGAINB2_V1
+#define AX5043_FREQUENCYGAINB3 AX5043_FREQUENCYGAINB3_V1
+#define AX5043_FREQUENCYGAINC0 AX5043_FREQUENCYGAINC0_V1
+#define AX5043_FREQUENCYGAINC1 AX5043_FREQUENCYGAINC1_V1
+#define AX5043_FREQUENCYGAINC2 AX5043_FREQUENCYGAINC2_V1
+#define AX5043_FREQUENCYGAINC3 AX5043_FREQUENCYGAINC3_V1
+#define AX5043_FREQUENCYGAIND0 AX5043_FREQUENCYGAIND0_V1
+#define AX5043_FREQUENCYGAIND1 AX5043_FREQUENCYGAIND1_V1
+#define AX5043_FREQUENCYGAIND2 AX5043_FREQUENCYGAIND2_V1
+#define AX5043_FREQUENCYGAIND3 AX5043_FREQUENCYGAIND3_V1
+#define AX5043_PHASEGAIN0 AX5043_PHASEGAIN0_V1
+#define AX5043_PHASEGAIN1 AX5043_PHASEGAIN1_V1
+#define AX5043_PHASEGAIN2 AX5043_PHASEGAIN2_V1
+#define AX5043_PHASEGAIN3 AX5043_PHASEGAIN3_V1
+#define AX5043_PKTADDR0 AX5043_PKTADDR0_V1
+#define AX5043_PKTADDR1 AX5043_PKTADDR1_V1
+#define AX5043_PKTADDRCFG AX5043_PKTADDRCFG_V1
+#define AX5043_PKTADDRMASK0 AX5043_PKTADDRMASK0_V1
+#define AX5043_PKTADDRMASK1 AX5043_PKTADDRMASK1_V1
+#define AX5043_PKTLENCFG AX5043_PKTLENCFG_V1
+#define AX5043_PKTLENOFFSET AX5043_PKTLENOFFSET_V1
+#define AX5043_PKTMAXLEN AX5043_PKTMAXLEN_V1
+#define AX5043_RXPARAMCURSET AX5043_RXPARAMCURSET_V1
+#define AX5043_RXPARAMSETS AX5043_RXPARAMSETS_V1
+#define AX5043_TIMEGAIN0 AX5043_TIMEGAIN0_V1
+#define AX5043_TIMEGAIN1 AX5043_TIMEGAIN1_V1
+#define AX5043_TIMEGAIN2 AX5043_TIMEGAIN2_V1
+#define AX5043_TIMEGAIN3 AX5043_TIMEGAIN3_V1
+#else
+SFRX(AX5043_AGCAHYST0, 0x4122) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST1, 0x4132) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST2, 0x4142) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST3, 0x4152) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCGAIN0, 0x4120) /* AGC Speed */
+SFRX(AX5043_AGCGAIN1, 0x4130) /* AGC Speed */
+SFRX(AX5043_AGCGAIN2, 0x4140) /* AGC Speed */
+SFRX(AX5043_AGCGAIN3, 0x4150) /* AGC Speed */
+SFRX(AX5043_AGCMINMAX0, 0x4123) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX1, 0x4133) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX2, 0x4143) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX3, 0x4153) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCTARGET0, 0x4121) /* AGC Target */
+SFRX(AX5043_AGCTARGET1, 0x4131) /* AGC Target */
+SFRX(AX5043_AGCTARGET2, 0x4141) /* AGC Target */
+SFRX(AX5043_AGCTARGET3, 0x4151) /* AGC Target */
+SFRX(AX5043_AMPLITUDEGAIN0, 0x412B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN1, 0x413B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN2, 0x414B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN3, 0x415B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_BBOFFSRES0, 0x412F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES1, 0x413F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES2, 0x414F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES3, 0x415F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_DRGAIN0, 0x4125) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN1, 0x4135) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN2, 0x4145) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN3, 0x4155) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_FOURFSK0, 0x412E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK1, 0x413E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK2, 0x414E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK3, 0x415E) /* Four FSK Control */
+SFRX(AX5043_FREQDEV00, 0x412D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV01, 0x413D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV02, 0x414D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV03, 0x415D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV10, 0x412C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV11, 0x413C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV12, 0x414C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV13, 0x415C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQUENCYGAINA0, 0x4127) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA1, 0x4137) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA2, 0x4147) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA3, 0x4157) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINB0, 0x4128) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB1, 0x4138) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB2, 0x4148) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB3, 0x4158) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINC0, 0x4129) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC1, 0x4139) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC2, 0x4149) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC3, 0x4159) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAIND0, 0x412A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND1, 0x413A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND2, 0x414A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND3, 0x415A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYLEAK, 0x4116) /* Baseband Frequency Recovery Loop Leakiness */
+SFRX(AX5043_PHASEGAIN0, 0x4126) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN1, 0x4136) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN2, 0x4146) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN3, 0x4156) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PKTADDR0, 0x4207) /* Packet Address 0 */
+SFRX(AX5043_PKTADDR1, 0x4206) /* Packet Address 1 */
+SFRX(AX5043_PKTADDR2, 0x4205) /* Packet Address 2 */
+SFRX(AX5043_PKTADDR3, 0x4204) /* Packet Address 3 */
+SFRX(AX5043_PKTADDRCFG, 0x4200) /* Packet Address Config */
+SFRX(AX5043_PKTADDRMASK0, 0x420B) /* Packet Address Mask 0 */
+SFRX(AX5043_PKTADDRMASK1, 0x420A) /* Packet Address Mask 1 */
+SFRX(AX5043_PKTADDRMASK2, 0x4209) /* Packet Address Mask 2 */
+SFRX(AX5043_PKTADDRMASK3, 0x4208) /* Packet Address Mask 3 */
+SFRX(AX5043_PKTLENCFG, 0x4201) /* Packet Length Configuration */
+SFRX(AX5043_PKTLENOFFSET, 0x4202) /* Packet Length Offset */
+SFRX(AX5043_PKTMAXLEN, 0x4203) /* Packet Maximum Length */
+SFRX(AX5043_RXPARAMCURSET, 0x4118) /* Receiver Parameter Current Set */
+SFRX(AX5043_RXPARAMSETS, 0x4117) /* Receiver Parameter Set Indirection */
+SFRX(AX5043_TIMEGAIN0, 0x4124) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN1, 0x4134) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN2, 0x4144) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN3, 0x4154) /* Time Estimator Bandwidth */
+#endif
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+#if !defined AX5043_DISABLE_NONBLOCKING
+SFRX(AX5043_AFSKCTRLNB, 0x5114) /* AFSK Control, Non-Blocking */
+SFRX(AX5043_AFSKMARK0NB, 0x5113) /* AFSK Mark (1) Frequency 0, Non-Blocking */
+SFRX(AX5043_AFSKMARK1NB, 0x5112) /* AFSK Mark (1) Frequency 1, Non-Blocking */
+SFRX(AX5043_AFSKSPACE0NB, 0x5111) /* AFSK Space (0) Frequency 0, Non-Blocking */
+SFRX(AX5043_AFSKSPACE1NB, 0x5110) /* AFSK Space (0) Frequency 1, Non-Blocking */
+SFRX(AX5043_AGCCOUNTERNB, 0x5043) /* AGC Counter, Non-Blocking */
+SFRX(AX5043_AMPLFILTERNB, 0x5115) /* Amplitude Filter, Non-Blocking */
+SFRX(AX5043_BBOFFSCAPNB, 0x5189) /* Baseband Offset Compensation Capacitors, Non-Blocking */
+SFRX(AX5043_BBTUNENB, 0x5188) /* Baseband Tuning, Non-Blocking */
+SFRX(AX5043_BGNDRSSINB, 0x5041) /* Background RSSI, Non-Blocking */
+SFRX(AX5043_BGNDRSSIGAINNB, 0x522E) /* Background RSSI Averaging Time Constant, Non-Blocking */
+SFRX(AX5043_BGNDRSSITHRNB, 0x522F) /* Background RSSI Relative Threshold, Non-Blocking */
+SFRX(AX5043_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5043_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5043_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5043_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5043_DACCONFIGNB, 0x5332) /* DAC Configuration, Non-Blocking */
+SFRX(AX5043_DACVALUE0NB, 0x5331) /* DAC Value 0, Non-Blocking */
+SFRX(AX5043_DACVALUE1NB, 0x5330) /* DAC Value 1, Non-Blocking */
+SFRX(AX5043_DECIMATIONNB, 0x5102) /* Decimation Factor , Non-Blocking */
+SFRX(AX5043_DIVERSITYNB, 0x5042) /* Antenna Diversity Configuration, Non-Blocking */
+SFRX(AX5043_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5043_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5043_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5043_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5043_FIFOCOUNT0NB, 0x502B) /* Number of Words currently in FIFO 0, Non-Blocking */
+SFRX(AX5043_FIFOCOUNT1NB, 0x502A) /* Number of Words currently in FIFO 1, Non-Blocking */
+SFRX(AX5043_FIFODATANB, 0x5029) /* FIFO Data, Non-Blocking */
+SFRX(AX5043_FIFOFREE0NB, 0x502D) /* Number of Words that can be written to FIFO 0, Non-Blocking */
+SFRX(AX5043_FIFOFREE1NB, 0x502C) /* Number of Words that can be written to FIFO 1, Non-Blocking */
+SFRX(AX5043_FIFOSTATNB, 0x5028) /* FIFO Control, Non-Blocking */
+SFRX(AX5043_FIFOTHRESH0NB, 0x502F) /* FIFO Threshold 0, Non-Blocking */
+SFRX(AX5043_FIFOTHRESH1NB, 0x502E) /* FIFO Threshold 1, Non-Blocking */
+SFRX(AX5043_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5043_FREQA0NB, 0x5037) /* Frequency A 0, Non-Blocking */
+SFRX(AX5043_FREQA1NB, 0x5036) /* Frequency A 1, Non-Blocking */
+SFRX(AX5043_FREQA2NB, 0x5035) /* Frequency A 2, Non-Blocking */
+SFRX(AX5043_FREQA3NB, 0x5034) /* Frequency A 3, Non-Blocking */
+SFRX(AX5043_FREQB0NB, 0x503F) /* Frequency B 0, Non-Blocking */
+SFRX(AX5043_FREQB1NB, 0x503E) /* Frequency B 1, Non-Blocking */
+SFRX(AX5043_FREQB2NB, 0x503D) /* Frequency B 2, Non-Blocking */
+SFRX(AX5043_FREQB3NB, 0x503C) /* Frequency B 3, Non-Blocking */
+SFRX(AX5043_FSKDEV0NB, 0x5163) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDEV1NB, 0x5162) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5043_FSKDEV2NB, 0x5161) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5043_FSKDMAX0NB, 0x510D) /* Four FSK Rx Maximum Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDMAX1NB, 0x510C) /* Four FSK Rx Maximum Deviation 1, Non-Blocking */
+SFRX(AX5043_FSKDMIN0NB, 0x510F) /* Four FSK Rx Minimum Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDMIN1NB, 0x510E) /* Four FSK Rx Minimum Deviation 1, Non-Blocking */
+SFRX(AX5043_GPADC13VALUE0NB, 0x5309) /* GPADC13 Value 0, Non-Blocking */
+SFRX(AX5043_GPADC13VALUE1NB, 0x5308) /* GPADC13 Value 1, Non-Blocking */
+SFRX(AX5043_GPADCCTRLNB, 0x5300) /* General Purpose ADC Control, Non-Blocking */
+SFRX(AX5043_GPADCPERIODNB, 0x5301) /* GPADC Sampling Period, Non-Blocking */
+SFRX(AX5043_IFFREQ0NB, 0x5101) /* 2nd LO / IF Frequency 0, Non-Blocking */
+SFRX(AX5043_IFFREQ1NB, 0x5100) /* 2nd LO / IF Frequency 1, Non-Blocking */
+SFRX(AX5043_IRQINVERSION0NB, 0x500B) /* IRQ Inversion 0, Non-Blocking */
+SFRX(AX5043_IRQINVERSION1NB, 0x500A) /* IRQ Inversion 1, Non-Blocking */
+SFRX(AX5043_IRQMASK0NB, 0x5007) /* IRQ Mask 0, Non-Blocking */
+SFRX(AX5043_IRQMASK1NB, 0x5006) /* IRQ Mask 1, Non-Blocking */
+SFRX(AX5043_IRQREQUEST0NB, 0x500D) /* IRQ Request 0, Non-Blocking */
+SFRX(AX5043_IRQREQUEST1NB, 0x500C) /* IRQ Request 1, Non-Blocking */
+SFRX(AX5043_LPOSCCONFIGNB, 0x5310) /* Low Power Oscillator Calibration Configuration, Non-Blocking */
+SFRX(AX5043_LPOSCFREQ0NB, 0x5317) /* Low Power Oscillator Frequency Tuning Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCFREQ1NB, 0x5316) /* Low Power Oscillator Frequency Tuning High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCKFILT0NB, 0x5313) /* Low Power Oscillator Calibration Filter Constant Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCKFILT1NB, 0x5312) /* Low Power Oscillator Calibration Filter Constant High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCPER0NB, 0x5319) /* Low Power Oscillator Period Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCPER1NB, 0x5318) /* Low Power Oscillator Period High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCREF0NB, 0x5315) /* Low Power Oscillator Reference Frequency Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCREF1NB, 0x5314) /* Low Power Oscillator Reference Frequency High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCSTATUSNB, 0x5311) /* Low Power Oscillator Calibration Status, Non-Blocking */
+SFRX(AX5043_MATCH0LENNB, 0x5214) /* Pattern Match Unit 0, Pattern Length, Non-Blocking */
+SFRX(AX5043_MATCH0MAXNB, 0x5216) /* Pattern Match Unit 0, Maximum Match, Non-Blocking */
+SFRX(AX5043_MATCH0MINNB, 0x5215) /* Pattern Match Unit 0, Minimum Match, Non-Blocking */
+SFRX(AX5043_MATCH0PAT0NB, 0x5213) /* Pattern Match Unit 0, Pattern 0, Non-Blocking */
+SFRX(AX5043_MATCH0PAT1NB, 0x5212) /* Pattern Match Unit 0, Pattern 1, Non-Blocking */
+SFRX(AX5043_MATCH0PAT2NB, 0x5211) /* Pattern Match Unit 0, Pattern 2, Non-Blocking */
+SFRX(AX5043_MATCH0PAT3NB, 0x5210) /* Pattern Match Unit 0, Pattern 3, Non-Blocking */
+SFRX(AX5043_MATCH1LENNB, 0x521C) /* Pattern Match Unit 1, Pattern Length, Non-Blocking */
+SFRX(AX5043_MATCH1MAXNB, 0x521E) /* Pattern Match Unit 1, Maximum Match, Non-Blocking */
+SFRX(AX5043_MATCH1MINNB, 0x521D) /* Pattern Match Unit 1, Minimum Match, Non-Blocking */
+SFRX(AX5043_MATCH1PAT0NB, 0x5219) /* Pattern Match Unit 1, Pattern 0, Non-Blocking */
+SFRX(AX5043_MATCH1PAT1NB, 0x5218) /* Pattern Match Unit 1, Pattern 1, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET0NB, 0x5108) /* Maximum Receiver Datarate Offset 0, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET1NB, 0x5107) /* Maximum Receiver Datarate Offset 1, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET2NB, 0x5106) /* Maximum Receiver Datarate Offset 2, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET0NB, 0x510B) /* Maximum Receiver RF Offset 0, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET1NB, 0x510A) /* Maximum Receiver RF Offset 1, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET2NB, 0x5109) /* Maximum Receiver RF Offset 2, Non-Blocking */
+SFRX(AX5043_MODCFGANB, 0x5164) /* Modulator Configuration A, Non-Blocking */
+SFRX(AX5043_MODCFGFNB, 0x5160) /* Modulator Configuration F, Non-Blocking */
+SFRX(AX5043_MODCFGPNB, 0x5F5F) /* Modulator Configuration P, Non-Blocking */
+SFRX(AX5043_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5043_PINFUNCANTSELNB, 0x5025) /* Pin Function ANTSEL, Non-Blocking */
+SFRX(AX5043_PINFUNCDATANB, 0x5023) /* Pin Function DATA, Non-Blocking */
+SFRX(AX5043_PINFUNCDCLKNB, 0x5022) /* Pin Function DCLK, Non-Blocking */
+SFRX(AX5043_PINFUNCIRQNB, 0x5024) /* Pin Function IRQ, Non-Blocking */
+SFRX(AX5043_PINFUNCPWRAMPNB, 0x5026) /* Pin Function PWRAMP, Non-Blocking */
+SFRX(AX5043_PINFUNCSYSCLKNB, 0x5021) /* Pin Function SYSCLK, Non-Blocking */
+SFRX(AX5043_PINSTATENB, 0x5020) /* Pin State, Non-Blocking */
+SFRX(AX5043_PKTACCEPTFLAGSNB, 0x5233) /* Packet Controller Accept Flags, Non-Blocking */
+SFRX(AX5043_PKTCHUNKSIZENB, 0x5230) /* Packet Chunk Size, Non-Blocking */
+SFRX(AX5043_PKTMISCFLAGSNB, 0x5231) /* Packet Controller Miscellaneous Flags, Non-Blocking */
+SFRX(AX5043_PKTSTOREFLAGSNB, 0x5232) /* Packet Controller Store Flags, Non-Blocking */
+SFRX(AX5043_PLLCPINB, 0x5031) /* PLL Charge Pump Current, Non-Blocking */
+SFRX(AX5043_PLLCPIBOOSTNB, 0x5039) /* PLL Charge Pump Current (Boosted), Non-Blocking */
+SFRX(AX5043_PLLLOCKDETNB, 0x5182) /* PLL Lock Detect Delay, Non-Blocking */
+SFRX(AX5043_PLLLOOPNB, 0x5030) /* PLL Loop Filter Settings, Non-Blocking */
+SFRX(AX5043_PLLLOOPBOOSTNB, 0x5038) /* PLL Loop Filter Settings (Boosted), Non-Blocking */
+SFRX(AX5043_PLLRANGINGANB, 0x5033) /* PLL Autoranging A, Non-Blocking */
+SFRX(AX5043_PLLRANGINGBNB, 0x503B) /* PLL Autoranging B, Non-Blocking */
+SFRX(AX5043_PLLRNGCLKNB, 0x5183) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5043_PLLVCODIVNB, 0x5032) /* PLL Divider Settings, Non-Blocking */
+SFRX(AX5043_PLLVCOINB, 0x5180) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5043_PLLVCOIRNB, 0x5181) /* PLL VCO Current Readback, Non-Blocking */
+SFRX(AX5043_POWCTRL1NB, 0x5F08) /* Power Control 1, Non-Blocking */
+SFRX(AX5043_POWIRQMASKNB, 0x5005) /* Power Management Interrupt Mask, Non-Blocking */
+SFRX(AX5043_POWSTATNB, 0x5003) /* Power Management Status, Non-Blocking */
+SFRX(AX5043_POWSTICKYSTATNB, 0x5004) /* Power Management Sticky Status, Non-Blocking */
+SFRX(AX5043_PWRAMPNB, 0x5027) /* PWRAMP Control, Non-Blocking */
+SFRX(AX5043_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5043_RADIOEVENTMASK0NB, 0x5009) /* Radio Event Mask 0, Non-Blocking */
+SFRX(AX5043_RADIOEVENTMASK1NB, 0x5008) /* Radio Event Mask 1, Non-Blocking */
+SFRX(AX5043_RADIOEVENTREQ0NB, 0x500F) /* Radio Event Request 0, Non-Blocking */
+SFRX(AX5043_RADIOEVENTREQ1NB, 0x500E) /* Radio Event Request 1, Non-Blocking */
+SFRX(AX5043_RADIOSTATENB, 0x501C) /* Radio Controller State, Non-Blocking */
+SFRX(AX5043_REFNB, 0x5F0D) /* Reference, Non-Blocking */
+SFRX(AX5043_RSSINB, 0x5040) /* Received Signal Strength Indicator, Non-Blocking */
+SFRX(AX5043_RSSIABSTHRNB, 0x522D) /* RSSI Absolute Threshold, Non-Blocking */
+SFRX(AX5043_RSSIREFERENCENB, 0x522C) /* RSSI Offset, Non-Blocking */
+SFRX(AX5043_RXDATARATE0NB, 0x5105) /* Receiver Datarate 0, Non-Blocking */
+SFRX(AX5043_RXDATARATE1NB, 0x5104) /* Receiver Datarate 1, Non-Blocking */
+SFRX(AX5043_RXDATARATE2NB, 0x5103) /* Receiver Datarate 2, Non-Blocking */
+SFRX(AX5043_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5043_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5043_TIMER0NB, 0x505B) /* 1MHz Timer 0, Non-Blocking */
+SFRX(AX5043_TIMER1NB, 0x505A) /* 1MHz Timer 1, Non-Blocking */
+SFRX(AX5043_TIMER2NB, 0x5059) /* 1MHz Timer 2, Non-Blocking */
+SFRX(AX5043_TMGRXAGCNB, 0x5227) /* Receiver AGC Settling Time, Non-Blocking */
+SFRX(AX5043_TMGRXBOOSTNB, 0x5223) /* Receive PLL Boost Time, Non-Blocking */
+SFRX(AX5043_TMGRXCOARSEAGCNB, 0x5226) /* Receive Coarse AGC Time, Non-Blocking */
+SFRX(AX5043_TMGRXOFFSACQNB, 0x5225) /* Receive Baseband DC Offset Acquisition Time, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE1NB, 0x5229) /* Receiver Preamble 1 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE2NB, 0x522A) /* Receiver Preamble 2 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE3NB, 0x522B) /* Receiver Preamble 3 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXRSSINB, 0x5228) /* Receiver RSSI Settling Time, Non-Blocking */
+SFRX(AX5043_TMGRXSETTLENB, 0x5224) /* Receive PLL (post Boost) Settling Time, Non-Blocking */
+SFRX(AX5043_TMGTXBOOSTNB, 0x5220) /* Transmit PLL Boost Time, Non-Blocking */
+SFRX(AX5043_TMGTXSETTLENB, 0x5221) /* Transmit PLL (post Boost) Settling Time, Non-Blocking */
+SFRX(AX5043_TRKAFSKDEMOD0NB, 0x5055) /* AFSK Demodulator Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKAFSKDEMOD1NB, 0x5054) /* AFSK Demodulator Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKAMPLITUDE0NB, 0x5049) /* Amplitude Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKAMPLITUDE1NB, 0x5048) /* Amplitude Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKDATARATE0NB, 0x5047) /* Datarate Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKDATARATE1NB, 0x5046) /* Datarate Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKDATARATE2NB, 0x5045) /* Datarate Tracking 2, Non-Blocking */
+SFRX(AX5043_TRKFREQ0NB, 0x5051) /* Frequency Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKFREQ1NB, 0x5050) /* Frequency Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKFSKDEMOD0NB, 0x5053) /* FSK Demodulator Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKFSKDEMOD1NB, 0x5052) /* FSK Demodulator Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKPHASE0NB, 0x504B) /* Phase Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKPHASE1NB, 0x504A) /* Phase Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ0NB, 0x504F) /* RF Frequency Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ1NB, 0x504E) /* RF Frequency Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ2NB, 0x504D) /* RF Frequency Tracking 2, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFA0NB, 0x5169) /* Transmitter Predistortion Coefficient A 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFA1NB, 0x5168) /* Transmitter Predistortion Coefficient A 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFB0NB, 0x516B) /* Transmitter Predistortion Coefficient B 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFB1NB, 0x516A) /* Transmitter Predistortion Coefficient B 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFC0NB, 0x516D) /* Transmitter Predistortion Coefficient C 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFC1NB, 0x516C) /* Transmitter Predistortion Coefficient C 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFD0NB, 0x516F) /* Transmitter Predistortion Coefficient D 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFD1NB, 0x516E) /* Transmitter Predistortion Coefficient D 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFE0NB, 0x5171) /* Transmitter Predistortion Coefficient E 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFE1NB, 0x5170) /* Transmitter Predistortion Coefficient E 1, Non-Blocking */
+SFRX(AX5043_TXRATE0NB, 0x5167) /* Transmitter Bitrate 0, Non-Blocking */
+SFRX(AX5043_TXRATE1NB, 0x5166) /* Transmitter Bitrate 1, Non-Blocking */
+SFRX(AX5043_TXRATE2NB, 0x5165) /* Transmitter Bitrate 2, Non-Blocking */
+SFRX(AX5043_WAKEUP0NB, 0x506B) /* Wakeup Time 0, Non-Blocking */
+SFRX(AX5043_WAKEUP1NB, 0x506A) /* Wakeup Time 1, Non-Blocking */
+SFRX(AX5043_WAKEUPFREQ0NB, 0x506D) /* Wakeup Frequency 0, Non-Blocking */
+SFRX(AX5043_WAKEUPFREQ1NB, 0x506C) /* Wakeup Frequency 1, Non-Blocking */
+SFRX(AX5043_WAKEUPTIMER0NB, 0x5069) /* Wakeup Timer 0, Non-Blocking */
+SFRX(AX5043_WAKEUPTIMER1NB, 0x5068) /* Wakeup Timer 1, Non-Blocking */
+SFRX(AX5043_WAKEUPXOEARLYNB, 0x506E) /* Wakeup Crystal Oscillator Early, Non-Blocking */
+SFRX(AX5043_XTALAMPLNB, 0x5F11) /* Crystal Oscillator Amplitude Control, Non-Blocking */
+SFRX(AX5043_XTALCAPNB, 0x5184) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5043_XTALOSCNB, 0x5F10) /* Crystal Oscillator Control, Non-Blocking */
+SFRX(AX5043_XTALSTATUSNB, 0x501D) /* Crystal Oscillator Status, Non-Blocking */
+
+SFRX(AX5043_0xF00NB, 0x5F00)
+SFRX(AX5043_0xF0CNB, 0x5F0C)
+SFRX(AX5043_0xF18NB, 0x5F18)
+SFRX(AX5043_0xF1CNB, 0x5F1C)
+SFRX(AX5043_0xF21NB, 0x5F21)
+SFRX(AX5043_0xF22NB, 0x5F22)
+SFRX(AX5043_0xF23NB, 0x5F23)
+SFRX(AX5043_0xF26NB, 0x5F26)
+SFRX(AX5043_0xF30NB, 0x5F30)
+SFRX(AX5043_0xF31NB, 0x5F31)
+SFRX(AX5043_0xF32NB, 0x5F32)
+SFRX(AX5043_0xF33NB, 0x5F33)
+SFRX(AX5043_0xF34NB, 0x5F34)
+SFRX(AX5043_0xF35NB, 0x5F35)
+SFRX(AX5043_0xF44NB, 0x5F44)
+
+#if defined AX5043V1
+SFRX(AX5043_AGCGAIN0NB_V1, 0x5120) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN1NB_V1, 0x512E) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN2NB_V1, 0x513C) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN3NB_V1, 0x514A) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCTARGET0NB_V1, 0x5121) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET1NB_V1, 0x512F) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET2NB_V1, 0x513D) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET3NB_V1, 0x514B) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN0NB_V1, 0x5129) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN1NB_V1, 0x5137) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN2NB_V1, 0x5145) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN3NB_V1, 0x5153) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_BBOFFSRES0NB_V1, 0x512D) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES1NB_V1, 0x513B) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES2NB_V1, 0x5149) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES3NB_V1, 0x5157) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_DRGAIN0NB_V1, 0x5123) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN1NB_V1, 0x5131) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN2NB_V1, 0x513F) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN3NB_V1, 0x514D) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_FOURFSK0NB_V1, 0x512C) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK1NB_V1, 0x513A) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK2NB_V1, 0x5148) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK3NB_V1, 0x5156) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FREQDEV00NB_V1, 0x512B) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV01NB_V1, 0x5139) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV02NB_V1, 0x5147) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV03NB_V1, 0x5155) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV10NB_V1, 0x512A) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV11NB_V1, 0x5138) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV12NB_V1, 0x5146) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV13NB_V1, 0x5154) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA0NB_V1, 0x5125) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA1NB_V1, 0x5133) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA2NB_V1, 0x5141) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA3NB_V1, 0x514F) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB0NB_V1, 0x5126) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB1NB_V1, 0x5134) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB2NB_V1, 0x5142) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB3NB_V1, 0x5150) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC0NB_V1, 0x5127) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC1NB_V1, 0x5135) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC2NB_V1, 0x5143) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC3NB_V1, 0x5151) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND0NB_V1, 0x5128) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND1NB_V1, 0x5136) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND2NB_V1, 0x5144) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND3NB_V1, 0x5152) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_PHASEGAIN0NB_V1, 0x5124) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN1NB_V1, 0x5132) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN2NB_V1, 0x5140) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN3NB_V1, 0x514E) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PKTADDR0NB_V1, 0x5203) /* Packet Address 0, Non-Blocking */
+SFRX(AX5043_PKTADDR1NB_V1, 0x5202) /* Packet Address 1, Non-Blocking */
+SFRX(AX5043_PKTADDRCFGNB_V1, 0x5201) /* Packet Address Config, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK0NB_V1, 0x5205) /* Packet Address Mask 0, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK1NB_V1, 0x5204) /* Packet Address Mask 1, Non-Blocking */
+SFRX(AX5043_PKTLENCFGNB_V1, 0x5206) /* Packet Length Configuration, Non-Blocking */
+SFRX(AX5043_PKTLENOFFSETNB_V1, 0x5207) /* Packet Length Offset, Non-Blocking */
+SFRX(AX5043_PKTMAXLENNB_V1, 0x5208) /* Packet Maximum Length, Non-Blocking */
+SFRX(AX5043_RXPARAMCURSETNB_V1, 0x5117) /* Receiver Parameter Current Set, Non-Blocking */
+SFRX(AX5043_RXPARAMSETSNB_V1, 0x5116) /* Receiver Parameter Set Indirection, Non-Blocking */
+SFRX(AX5043_TIMEGAIN0NB_V1, 0x5122) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN1NB_V1, 0x5130) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN2NB_V1, 0x513E) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN3NB_V1, 0x514C) /* Time Estimator Bandwidth, Non-Blocking */
+
+#define AX5043_AGCGAIN0NB AX5043_AGCGAIN0NB_V1
+#define AX5043_AGCGAIN1NB AX5043_AGCGAIN1NB_V1
+#define AX5043_AGCGAIN2NB AX5043_AGCGAIN2NB_V1
+#define AX5043_AGCGAIN3NB AX5043_AGCGAIN3NB_V1
+#define AX5043_AGCTARGET0NB AX5043_AGCTARGET0NB_V1
+#define AX5043_AGCTARGET1NB AX5043_AGCTARGET1NB_V1
+#define AX5043_AGCTARGET2NB AX5043_AGCTARGET2NB_V1
+#define AX5043_AGCTARGET3NB AX5043_AGCTARGET3NB_V1
+#define AX5043_AMPLITUDEGAIN0NB AX5043_AMPLITUDEGAIN0NB_V1
+#define AX5043_AMPLITUDEGAIN1NB AX5043_AMPLITUDEGAIN1NB_V1
+#define AX5043_AMPLITUDEGAIN2NB AX5043_AMPLITUDEGAIN2NB_V1
+#define AX5043_AMPLITUDEGAIN3NB AX5043_AMPLITUDEGAIN3NB_V1
+#define AX5043_BBOFFSRES0NB AX5043_BBOFFSRES0NB_V1
+#define AX5043_BBOFFSRES1NB AX5043_BBOFFSRES1NB_V1
+#define AX5043_BBOFFSRES2NB AX5043_BBOFFSRES2NB_V1
+#define AX5043_BBOFFSRES3NB AX5043_BBOFFSRES3NB_V1
+#define AX5043_DRGAIN0NB AX5043_DRGAIN0NB_V1
+#define AX5043_DRGAIN1NB AX5043_DRGAIN1NB_V1
+#define AX5043_DRGAIN2NB AX5043_DRGAIN2NB_V1
+#define AX5043_DRGAIN3NB AX5043_DRGAIN3NB_V1
+#define AX5043_FOURFSK0NB AX5043_FOURFSK0NB_V1
+#define AX5043_FOURFSK1NB AX5043_FOURFSK1NB_V1
+#define AX5043_FOURFSK2NB AX5043_FOURFSK2NB_V1
+#define AX5043_FOURFSK3NB AX5043_FOURFSK3NB_V1
+#define AX5043_FREQDEV00NB AX5043_FREQDEV00NB_V1
+#define AX5043_FREQDEV01NB AX5043_FREQDEV01NB_V1
+#define AX5043_FREQDEV02NB AX5043_FREQDEV02NB_V1
+#define AX5043_FREQDEV03NB AX5043_FREQDEV03NB_V1
+#define AX5043_FREQDEV10NB AX5043_FREQDEV10NB_V1
+#define AX5043_FREQDEV11NB AX5043_FREQDEV11NB_V1
+#define AX5043_FREQDEV12NB AX5043_FREQDEV12NB_V1
+#define AX5043_FREQDEV13NB AX5043_FREQDEV13NB_V1
+#define AX5043_FREQUENCYGAINA0NB AX5043_FREQUENCYGAINA0NB_V1
+#define AX5043_FREQUENCYGAINA1NB AX5043_FREQUENCYGAINA1NB_V1
+#define AX5043_FREQUENCYGAINA2NB AX5043_FREQUENCYGAINA2NB_V1
+#define AX5043_FREQUENCYGAINA3NB AX5043_FREQUENCYGAINA3NB_V1
+#define AX5043_FREQUENCYGAINB0NB AX5043_FREQUENCYGAINB0NB_V1
+#define AX5043_FREQUENCYGAINB1NB AX5043_FREQUENCYGAINB1NB_V1
+#define AX5043_FREQUENCYGAINB2NB AX5043_FREQUENCYGAINB2NB_V1
+#define AX5043_FREQUENCYGAINB3NB AX5043_FREQUENCYGAINB3NB_V1
+#define AX5043_FREQUENCYGAINC0NB AX5043_FREQUENCYGAINC0NB_V1
+#define AX5043_FREQUENCYGAINC1NB AX5043_FREQUENCYGAINC1NB_V1
+#define AX5043_FREQUENCYGAINC2NB AX5043_FREQUENCYGAINC2NB_V1
+#define AX5043_FREQUENCYGAINC3NB AX5043_FREQUENCYGAINC3NB_V1
+#define AX5043_FREQUENCYGAIND0NB AX5043_FREQUENCYGAIND0NB_V1
+#define AX5043_FREQUENCYGAIND1NB AX5043_FREQUENCYGAIND1NB_V1
+#define AX5043_FREQUENCYGAIND2NB AX5043_FREQUENCYGAIND2NB_V1
+#define AX5043_FREQUENCYGAIND3NB AX5043_FREQUENCYGAIND3NB_V1
+#define AX5043_PHASEGAIN0NB AX5043_PHASEGAIN0NB_V1
+#define AX5043_PHASEGAIN1NB AX5043_PHASEGAIN1NB_V1
+#define AX5043_PHASEGAIN2NB AX5043_PHASEGAIN2NB_V1
+#define AX5043_PHASEGAIN3NB AX5043_PHASEGAIN3NB_V1
+#define AX5043_PKTADDR0NB AX5043_PKTADDR0NB_V1
+#define AX5043_PKTADDR1NB AX5043_PKTADDR1NB_V1
+#define AX5043_PKTADDRCFGNB AX5043_PKTADDRCFGNB_V1
+#define AX5043_PKTADDRMASK0NB AX5043_PKTADDRMASK0NB_V1
+#define AX5043_PKTADDRMASK1NB AX5043_PKTADDRMASK1NB_V1
+#define AX5043_PKTLENCFGNB AX5043_PKTLENCFGNB_V1
+#define AX5043_PKTLENOFFSETNB AX5043_PKTLENOFFSETNB_V1
+#define AX5043_PKTMAXLENNB AX5043_PKTMAXLENNB_V1
+#define AX5043_RXPARAMCURSETNB AX5043_RXPARAMCURSETNB_V1
+#define AX5043_RXPARAMSETSNB AX5043_RXPARAMSETSNB_V1
+#define AX5043_TIMEGAIN0NB AX5043_TIMEGAIN0NB_V1
+#define AX5043_TIMEGAIN1NB AX5043_TIMEGAIN1NB_V1
+#define AX5043_TIMEGAIN2NB AX5043_TIMEGAIN2NB_V1
+#define AX5043_TIMEGAIN3NB AX5043_TIMEGAIN3NB_V1
+#else
+SFRX(AX5043_AGCAHYST0NB, 0x5122) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST1NB, 0x5132) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST2NB, 0x5142) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST3NB, 0x5152) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCGAIN0NB, 0x5120) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN1NB, 0x5130) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN2NB, 0x5140) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN3NB, 0x5150) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCMINMAX0NB, 0x5123) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX1NB, 0x5133) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX2NB, 0x5143) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX3NB, 0x5153) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCTARGET0NB, 0x5121) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET1NB, 0x5131) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET2NB, 0x5141) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET3NB, 0x5151) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN0NB, 0x512B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN1NB, 0x513B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN2NB, 0x514B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN3NB, 0x515B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_BBOFFSRES0NB, 0x512F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES1NB, 0x513F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES2NB, 0x514F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES3NB, 0x515F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_DRGAIN0NB, 0x5125) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN1NB, 0x5135) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN2NB, 0x5145) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN3NB, 0x5155) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_FOURFSK0NB, 0x512E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK1NB, 0x513E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK2NB, 0x514E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK3NB, 0x515E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FREQDEV00NB, 0x512D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV01NB, 0x513D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV02NB, 0x514D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV03NB, 0x515D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV10NB, 0x512C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV11NB, 0x513C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV12NB, 0x514C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV13NB, 0x515C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA0NB, 0x5127) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA1NB, 0x5137) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA2NB, 0x5147) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA3NB, 0x5157) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB0NB, 0x5128) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB1NB, 0x5138) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB2NB, 0x5148) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB3NB, 0x5158) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC0NB, 0x5129) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC1NB, 0x5139) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC2NB, 0x5149) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC3NB, 0x5159) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND0NB, 0x512A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND1NB, 0x513A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND2NB, 0x514A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND3NB, 0x515A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYLEAKNB, 0x5116) /* Baseband Frequency Recovery Loop Leakiness, Non-Blocking */
+SFRX(AX5043_PHASEGAIN0NB, 0x5126) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN1NB, 0x5136) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN2NB, 0x5146) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN3NB, 0x5156) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PKTADDR0NB, 0x5207) /* Packet Address 0, Non-Blocking */
+SFRX(AX5043_PKTADDR1NB, 0x5206) /* Packet Address 1, Non-Blocking */
+SFRX(AX5043_PKTADDR2NB, 0x5205) /* Packet Address 2, Non-Blocking */
+SFRX(AX5043_PKTADDR3NB, 0x5204) /* Packet Address 3, Non-Blocking */
+SFRX(AX5043_PKTADDRCFGNB, 0x5200) /* Packet Address Config, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK0NB, 0x520B) /* Packet Address Mask 0, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK1NB, 0x520A) /* Packet Address Mask 1, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK2NB, 0x5209) /* Packet Address Mask 2, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK3NB, 0x5208) /* Packet Address Mask 3, Non-Blocking */
+SFRX(AX5043_PKTLENCFGNB, 0x5201) /* Packet Length Configuration, Non-Blocking */
+SFRX(AX5043_PKTLENOFFSETNB, 0x5202) /* Packet Length Offset, Non-Blocking */
+SFRX(AX5043_PKTMAXLENNB, 0x5203) /* Packet Maximum Length, Non-Blocking */
+SFRX(AX5043_RXPARAMCURSETNB, 0x5118) /* Receiver Parameter Current Set, Non-Blocking */
+SFRX(AX5043_RXPARAMSETSNB, 0x5117) /* Receiver Parameter Set Indirection, Non-Blocking */
+SFRX(AX5043_TIMEGAIN0NB, 0x5124) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN1NB, 0x5134) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN2NB, 0x5144) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN3NB, 0x5154) /* Time Estimator Bandwidth, Non-Blocking */
+#endif
+#endif
+
+#endif /* AX8052F143_H */
diff --git a/libs/libmf/include/ax8052f151.h b/libs/libmf/include/ax8052f151.h
new file mode 100644
index 00000000..07ea03d7
--- /dev/null
+++ b/libs/libmf/include/ax8052f151.h
@@ -0,0 +1,220 @@
+/*-------------------------------------------------------------------------
+ AX8052F151.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F151_H
+#define AX8052F151_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5051_ADCMISC, 0x4038) /* ADC Miscellaneous Control */
+SFRX(AX5051_AGCATTACK, 0x403A) /* AGC Attack Speed */
+SFRX(AX5051_AGCCOUNTER, 0x403C) /* AGC Counter */
+SFRX(AX5051_AGCDECAY, 0x403B) /* AGC Decay Speed */
+SFRX(AX5051_AGCTARGET, 0x4039) /* AGC Target Value */
+SFRX(AX5051_AMPLITUDEGAIN, 0x4047) /* Amplitude Estimator Bandwidth */
+SFRX(AX5051_CICDECHI, 0x403E) /* Decimation Factor High */
+SFRX(AX5051_CICDECLO, 0x403F) /* Decimation Factor Low */
+SFRX(AX5051_CICSHIFT, 0x403D) /* Decimation Filter Attenuation */
+SFRX(AX5051_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5051_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5051_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5051_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5051_DATARATEHI, 0x4040) /* Datarate High */
+SFRX(AX5051_DATARATELO, 0x4041) /* Datarate Low */
+SFRX(AX5051_DSPMODE, 0x4009) /* DSP Mode Interface Control */
+SFRX(AX5051_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5051_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5051_FECMEM, 0x406F) /* Forward Error Correction Memory */
+SFRX(AX5051_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5051_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5051_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5051_FIFOCONTROL2, 0x4037) /* FIFO Control 2 */
+SFRX(AX5051_FIFOCOUNT, 0x4035) /* FIFO Count */
+SFRX(AX5051_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5051_FIFOTHRESH, 0x4036) /* FIFO Threshold */
+SFRX(AX5051_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5051_FREQ0, 0x4023) /* Frequency 0 */
+SFRX(AX5051_FREQ1, 0x4022) /* Frequency 1 */
+SFRX(AX5051_FREQ2, 0x4021) /* Frequency 2 */
+SFRX(AX5051_FREQ3, 0x4020) /* Frequency 3 */
+SFRX(AX5051_FREQA0, 0x4023) /* Frequency 0 */
+SFRX(AX5051_FREQA1, 0x4022) /* Frequency 1 */
+SFRX(AX5051_FREQA2, 0x4021) /* Frequency 2 */
+SFRX(AX5051_FREQA3, 0x4020) /* Frequency 3 */
+SFRX(AX5051_FREQUENCYGAIN, 0x4045) /* Frequency Estimator Bandwidth */
+SFRX(AX5051_FREQUENCYGAIN2, 0x4046) /* Frequency Estimator Bandwidth 2 */
+SFRX(AX5051_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5051_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5051_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5051_IFFREQHI, 0x4028) /* IF Frequency Low */
+SFRX(AX5051_IFFREQLO, 0x4029) /* IF Frequency High */
+SFRX(AX5051_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5051_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5051_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5051_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5051_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5051_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5051_PHASEGAIN, 0x4044) /* Phase Estimator Bandwidth */
+SFRX(AX5051_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5051_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5051_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5051_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5051_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5051_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5051_PLLVCOI, 0x4072) /* PLL VCO Current */
+SFRX(AX5051_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5051_REF, 0x407C) /* Reference */
+SFRX(AX5051_RFMISC, 0x407A) /* RF Miscellaneous Control */
+SFRX(AX5051_RXMISC, 0x407D) /* Receiver Miscellaneous Control */
+SFRX(AX5051_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5051_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5051_TIMINGGAINHI, 0x4042) /* Timing Estimator Bandwidth High */
+SFRX(AX5051_TIMINGGAINLO, 0x4043) /* Timing Estimator Bandwidth Low */
+SFRX(AX5051_TRKAMPLITUDEHI, 0x4048) /* Amplitude Tracking High */
+SFRX(AX5051_TRKAMPLITUDELO, 0x4049) /* Amplitude Tracking Low */
+SFRX(AX5051_TRKFREQHI, 0x404C) /* Frequency Tracking High */
+SFRX(AX5051_TRKFREQLO, 0x404D) /* Frequency Tracking Low */
+SFRX(AX5051_TRKPHASEHI, 0x404A) /* Phase Tracking High */
+SFRX(AX5051_TRKPHASELO, 0x404B) /* Phase Tracking Low */
+SFRX(AX5051_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5051_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5051_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5051_TXDSPMODE, 0x400A) /* Transmit DSP Mode */
+SFRX(AX5051_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5051_VREG, 0x401B) /* Voltage Regulator */
+SFRX(AX5051_XTALCAP, 0x404F) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5051_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5051_ADCMISCNB, 0x5038) /* ADC Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_AGCATTACKNB, 0x503A) /* AGC Attack Speed, Non-Blocking */
+SFRX(AX5051_AGCCOUNTERNB, 0x503C) /* AGC Counter, Non-Blocking */
+SFRX(AX5051_AGCDECAYNB, 0x503B) /* AGC Decay Speed, Non-Blocking */
+SFRX(AX5051_AGCTARGETNB, 0x5039) /* AGC Target Value, Non-Blocking */
+SFRX(AX5051_AMPLITUDEGAINNB, 0x5047) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_CICDECHINB, 0x503E) /* Decimation Factor High, Non-Blocking */
+SFRX(AX5051_CICDECLONB, 0x503F) /* Decimation Factor Low, Non-Blocking */
+SFRX(AX5051_CICSHIFTNB, 0x503D) /* Decimation Filter Attenuation, Non-Blocking */
+SFRX(AX5051_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5051_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5051_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5051_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5051_DATARATEHINB, 0x5040) /* Datarate High, Non-Blocking */
+SFRX(AX5051_DATARATELONB, 0x5041) /* Datarate Low, Non-Blocking */
+SFRX(AX5051_DSPMODENB, 0x5009) /* DSP Mode Interface Control, Non-Blocking */
+SFRX(AX5051_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5051_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5051_FECMEMNB, 0x506F) /* Forward Error Correction Memory, Non-Blocking */
+SFRX(AX5051_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5051_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5051_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5051_FIFOCONTROL2NB, 0x5037) /* FIFO Control 2, Non-Blocking */
+SFRX(AX5051_FIFOCOUNTNB, 0x5035) /* FIFO Count, Non-Blocking */
+SFRX(AX5051_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5051_FIFOTHRESHNB, 0x5036) /* FIFO Threshold, Non-Blocking */
+SFRX(AX5051_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5051_FREQ0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5051_FREQ1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5051_FREQ2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5051_FREQ3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5051_FREQA0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5051_FREQA1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5051_FREQA2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5051_FREQA3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5051_FREQUENCYGAINNB, 0x5045) /* Frequency Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_FREQUENCYGAIN2NB, 0x5046) /* Frequency Estimator Bandwidth 2, Non-Blocking */
+SFRX(AX5051_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5051_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5051_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5051_IFFREQHINB, 0x5028) /* IF Frequency Low, Non-Blocking */
+SFRX(AX5051_IFFREQLONB, 0x5029) /* IF Frequency High, Non-Blocking */
+SFRX(AX5051_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5051_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5051_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5051_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5051_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5051_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_PHASEGAINNB, 0x5044) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5051_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5051_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5051_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5051_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5051_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5051_PLLVCOINB, 0x5072) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5051_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5051_REFNB, 0x507C) /* Reference, Non-Blocking */
+SFRX(AX5051_RFMISCNB, 0x507A) /* RF Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_RXMISCNB, 0x507D) /* Receiver Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5051_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5051_TIMINGGAINHINB, 0x5042) /* Timing Estimator Bandwidth High, Non-Blocking */
+SFRX(AX5051_TIMINGGAINLONB, 0x5043) /* Timing Estimator Bandwidth Low, Non-Blocking */
+SFRX(AX5051_TRKAMPLITUDEHINB, 0x5048) /* Amplitude Tracking High, Non-Blocking */
+SFRX(AX5051_TRKAMPLITUDELONB, 0x5049) /* Amplitude Tracking Low, Non-Blocking */
+SFRX(AX5051_TRKFREQHINB, 0x504C) /* Frequency Tracking High, Non-Blocking */
+SFRX(AX5051_TRKFREQLONB, 0x504D) /* Frequency Tracking Low, Non-Blocking */
+SFRX(AX5051_TRKPHASEHINB, 0x504A) /* Phase Tracking High, Non-Blocking */
+SFRX(AX5051_TRKPHASELONB, 0x504B) /* Phase Tracking Low, Non-Blocking */
+SFRX(AX5051_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5051_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5051_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5051_TXDSPMODENB, 0x500A) /* Transmit DSP Mode, Non-Blocking */
+SFRX(AX5051_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5051_VREGNB, 0x501B) /* Voltage Regulator, Non-Blocking */
+SFRX(AX5051_XTALCAPNB, 0x504F) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5051_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5051_AMPLGAIN AX5051_AMPLITUDEGAIN
+#define AX5051_FREQGAIN AX5051_FREQUENCYGAIN
+#define AX5051_FREQGAIN2 AX5051_FREQUENCYGAIN2
+#define AX5051_MODMISC AX5051_MODULATORMISC
+#define AX5051_TMGGAINHI AX5051_TIMINGGAINHI
+#define AX5051_TMGGAINLO AX5051_TIMINGGAINLO
+#define AX5051_TXRATEHI AX5051_TXBITRATEHI
+#define AX5051_TXRATELO AX5051_TXBITRATELO
+#define AX5051_TXRATEMID AX5051_TXBITRATEMID
+
+#define AX5051_AMPLGAINNB AX5051_AMPLITUDEGAINNB
+#define AX5051_FREQGAINNB AX5051_FREQUENCYGAINNB
+#define AX5051_FREQGAIN2NB AX5051_FREQUENCYGAIN2NB
+#define AX5051_MODMISCNB AX5051_MODULATORMISCNB
+#define AX5051_TMGGAINHINB AX5051_TIMINGGAINHINB
+#define AX5051_TMGGAINLONB AX5051_TIMINGGAINLONB
+#define AX5051_TXRATEHINB AX5051_TXBITRATEHINB
+#define AX5051_TXRATELONB AX5051_TXBITRATELONB
+#define AX5051_TXRATEMIDNB AX5051_TXBITRATEMIDNB
+
+#endif /* AX8052F151_H */
diff --git a/libs/libmf/include/ax8052regaddr.h b/libs/libmf/include/ax8052regaddr.h
new file mode 100644
index 00000000..ff63906b
--- /dev/null
+++ b/libs/libmf/include/ax8052regaddr.h
@@ -0,0 +1,366 @@
+/*-------------------------------------------------------------------------
+ ax8052regaddr.h - Register Address Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052REGADDR_H
+#define AX8052REGADDR_H
+
+/* SFR Address Space */
+
+#define SFRADDR_ACC 0xE0 /* Accumulator */
+#define SFRADDR_B 0xF0 /* B Register */
+#define SFRADDR_DPH 0x83 /* Data Pointer 0 High Byte */
+#define SFRADDR_DPH1 0x85 /* Data Pointer 1 High Byte */
+#define SFRADDR_DPL 0x82 /* Data Pointer 0 Low Byte */
+#define SFRADDR_DPL1 0x84 /* Data Pointer 1 Low Byte */
+#define SFRADDR_DPS 0x86 /* Data Pointer Select */
+#define SFRADDR_E2IE 0xA0 /* 2nd Extended Interrupt Enable */
+#define SFRADDR_E2IP 0xC0 /* 2nd Extended Interrupt Priority */
+#define SFRADDR_EIE 0x98 /* Extended Interrupt Enable */
+#define SFRADDR_EIP 0xB0 /* Extended Interrupt Priority */
+#define SFRADDR_IE 0xA8 /* Interrupt Enable */
+#define SFRADDR_IP 0xB8 /* Interrupt Priority */
+#define SFRADDR_PCON 0x87 /* Power Mode Control */
+#define SFRADDR_PSW 0xD0 /* Program Status Word */
+#define SFRADDR_SP 0x81 /* Stack Pointer */
+#define SFRADDR_WBTEST 0x8F /* Debug Breakpoint Register */
+#define SFRADDR_XPAGE 0xD9 /* Memory Page Select */
+#define SFRADDR_ADCCH0CONFIG 0xCA /* ADC Channel 0 Configuration */
+#define SFRADDR_ADCCH1CONFIG 0xCB /* ADC Channel 1 Configuration */
+#define SFRADDR_ADCCH2CONFIG 0xD2 /* ADC Channel 2 Configuration */
+#define SFRADDR_ADCCH3CONFIG 0xD3 /* ADC Channel 3 Configuration */
+#define SFRADDR_ADCCLKSRC 0xD1 /* ADC Clock Source */
+#define SFRADDR_ADCCONV 0xC9 /* ADC Conversion Source */
+#define SFRADDR_ANALOGCOMP 0xE1 /* Analog Comparators */
+#define SFRADDR_CLKCON 0xC6 /* Clock Control */
+#define SFRADDR_CLKSTAT 0xC7 /* Clock Status */
+#define SFRADDR_CODECONFIG 0x97 /* Code Space Configuration */
+#define SFRADDR_DBGLNKBUF 0xE3 /* Debug Link Buffer */
+#define SFRADDR_DBGLNKSTAT 0xE2 /* Debug Link Status */
+#define SFRADDR_DIRA 0x89 /* Port A Direction */
+#define SFRADDR_DIRB 0x8A /* Port B Direction */
+#define SFRADDR_DIRC 0x8B /* Port C Direction */
+#define SFRADDR_DIRR 0x8E /* Port R Direction */
+#define SFRADDR_PINA 0xC8 /* Port A Input */
+#define SFRADDR_PINB 0xE8 /* Port B Input */
+#define SFRADDR_PINC 0xF8 /* Port C Input */
+#define SFRADDR_PINR 0x8D /* Port R Input */
+#define SFRADDR_PORTA 0x80 /* Port A Output */
+#define SFRADDR_PORTB 0x88 /* Port B Output */
+#define SFRADDR_PORTC 0x90 /* Port C Output */
+#define SFRADDR_PORTR 0x8C /* Port R Output */
+#define SFRADDR_IC0CAPT0 0xCE /* Input Capture 0 Low Byte */
+#define SFRADDR_IC0CAPT1 0xCF /* Input Capture 0 High Byte */
+#define SFRADDR_IC0MODE 0xCC /* Input Capture 0 Mode */
+#define SFRADDR_IC0STATUS 0xCD /* Input Capture 0 Status */
+#define SFRADDR_IC1CAPT0 0xD6 /* Input Capture 1 Low Byte */
+#define SFRADDR_IC1CAPT1 0xD7 /* Input Capture 1 High Byte */
+#define SFRADDR_IC1MODE 0xD4 /* Input Capture 1 Mode */
+#define SFRADDR_IC1STATUS 0xD5 /* Input Capture 1 Status */
+#define SFRADDR_NVADDR0 0x92 /* Non-Volatile Memory Address Low Byte */
+#define SFRADDR_NVADDR1 0x93 /* Non-Volatile Memory Address High Byte */
+#define SFRADDR_NVDATA0 0x94 /* Non-Volatile Memory Data Low Byte */
+#define SFRADDR_NVDATA1 0x95 /* Non-Volatile Memory Data High Byte */
+#define SFRADDR_NVKEY 0x96 /* Non-Volatile Memory Write/Erase Key */
+#define SFRADDR_NVSTATUS 0x91 /* Non-Volatile Memory Command / Status */
+#define SFRADDR_OC0COMP0 0xBC /* Output Compare 0 Low Byte */
+#define SFRADDR_OC0COMP1 0xBD /* Output Compare 0 High Byte */
+#define SFRADDR_OC0MODE 0xB9 /* Output Compare 0 Mode */
+#define SFRADDR_OC0PIN 0xBA /* Output Compare 0 Pin Configuration */
+#define SFRADDR_OC0STATUS 0xBB /* Output Compare 0 Status */
+#define SFRADDR_OC1COMP0 0xC4 /* Output Compare 1 Low Byte */
+#define SFRADDR_OC1COMP1 0xC5 /* Output Compare 1 High Byte */
+#define SFRADDR_OC1MODE 0xC1 /* Output Compare 1 Mode */
+#define SFRADDR_OC1PIN 0xC2 /* Output Compare 1 Pin Configuration */
+#define SFRADDR_OC1STATUS 0xC3 /* Output Compare 1 Status */
+#define SFRADDR_RADIOACC 0xB1 /* Radio Controller Access Mode */
+#define SFRADDR_RADIOADDR0 0xB3 /* Radio Register Address Low Byte */
+#define SFRADDR_RADIOADDR1 0xB2 /* Radio Register Address High Byte */
+#define SFRADDR_RADIODATA0 0xB7 /* Radio Register Data 0 */
+#define SFRADDR_RADIODATA1 0xB6 /* Radio Register Data 1 */
+#define SFRADDR_RADIODATA2 0xB5 /* Radio Register Data 2 */
+#define SFRADDR_RADIODATA3 0xB4 /* Radio Register Data 3 */
+#define SFRADDR_RADIOSTAT0 0xBE /* Radio Access Status Low Byte */
+#define SFRADDR_RADIOSTAT1 0xBF /* Radio Access Status High Byte */
+#define SFRADDR_SPCLKSRC 0xDF /* SPI Clock Source */
+#define SFRADDR_SPMODE 0xDC /* SPI Mode */
+#define SFRADDR_SPSHREG 0xDE /* SPI Shift Register */
+#define SFRADDR_SPSTATUS 0xDD /* SPI Status */
+#define SFRADDR_T0CLKSRC 0x9A /* Timer 0 Clock Source */
+#define SFRADDR_T0CNT0 0x9C /* Timer 0 Count Low Byte */
+#define SFRADDR_T0CNT1 0x9D /* Timer 0 Count High Byte */
+#define SFRADDR_T0MODE 0x99 /* Timer 0 Mode */
+#define SFRADDR_T0PERIOD0 0x9E /* Timer 0 Period Low Byte */
+#define SFRADDR_T0PERIOD1 0x9F /* Timer 0 Period High Byte */
+#define SFRADDR_T0STATUS 0x9B /* Timer 0 Status */
+#define SFRADDR_T1CLKSRC 0xA2 /* Timer 1 Clock Source */
+#define SFRADDR_T1CNT0 0xA4 /* Timer 1 Count Low Byte */
+#define SFRADDR_T1CNT1 0xA5 /* Timer 1 Count High Byte */
+#define SFRADDR_T1MODE 0xA1 /* Timer 1 Mode */
+#define SFRADDR_T1PERIOD0 0xA6 /* Timer 1 Period Low Byte */
+#define SFRADDR_T1PERIOD1 0xA7 /* Timer 1 Period High Byte */
+#define SFRADDR_T1STATUS 0xA3 /* Timer 1 Status */
+#define SFRADDR_T2CLKSRC 0xAA /* Timer 2 Clock Source */
+#define SFRADDR_T2CNT0 0xAC /* Timer 2 Count Low Byte */
+#define SFRADDR_T2CNT1 0xAD /* Timer 2 Count High Byte */
+#define SFRADDR_T2MODE 0xA9 /* Timer 2 Mode */
+#define SFRADDR_T2PERIOD0 0xAE /* Timer 2 Period Low Byte */
+#define SFRADDR_T2PERIOD1 0xAF /* Timer 2 Period High Byte */
+#define SFRADDR_T2STATUS 0xAB /* Timer 2 Status */
+#define SFRADDR_U0CTRL 0xE4 /* UART 0 Control */
+#define SFRADDR_U0MODE 0xE7 /* UART 0 Mode */
+#define SFRADDR_U0SHREG 0xE6 /* UART 0 Shift Register */
+#define SFRADDR_U0STATUS 0xE5 /* UART 0 Status */
+#define SFRADDR_U1CTRL 0xEC /* UART 1 Control */
+#define SFRADDR_U1MODE 0xEF /* UART 1 Mode */
+#define SFRADDR_U1SHREG 0xEE /* UART 1 Shift Register */
+#define SFRADDR_U1STATUS 0xED /* UART 1 Status */
+#define SFRADDR_WDTCFG 0xDA /* Watchdog Configuration */
+#define SFRADDR_WDTRESET 0xDB /* Watchdog Reset */
+#define SFRADDR_WTCFGA 0xF1 /* Wakeup Timer A Configuration */
+#define SFRADDR_WTCFGB 0xF9 /* Wakeup Timer B Configuration */
+#define SFRADDR_WTCNTA0 0xF2 /* Wakeup Counter A Low Byte */
+#define SFRADDR_WTCNTA1 0xF3 /* Wakeup Counter A High Byte */
+#define SFRADDR_WTCNTB0 0xFA /* Wakeup Counter B Low Byte */
+#define SFRADDR_WTCNTB1 0xFB /* Wakeup Counter B High Byte */
+#define SFRADDR_WTCNTR1 0xEB /* Wakeup Counter High Byte Latch */
+#define SFRADDR_WTEVTA0 0xF4 /* Wakeup Event A Low Byte */
+#define SFRADDR_WTEVTA1 0xF5 /* Wakeup Event A High Byte */
+#define SFRADDR_WTEVTB0 0xF6 /* Wakeup Event B Low Byte */
+#define SFRADDR_WTEVTB1 0xF7 /* Wakeup Event B High Byte */
+#define SFRADDR_WTEVTC0 0xFC /* Wakeup Event C Low Byte */
+#define SFRADDR_WTEVTC1 0xFD /* Wakeup Event C High Byte */
+#define SFRADDR_WTEVTD0 0xFE /* Wakeup Event D Low Byte */
+#define SFRADDR_WTEVTD1 0xFF /* Wakeup Event D High Byte */
+#define SFRADDR_WTIRQEN 0xE9 /* Wakeup Timer Interrupt Enable */
+#define SFRADDR_WTSTAT 0xEA /* Wakeup Timer Status */
+
+/* X Address Space */
+
+
+#define SFRXADDR_ADCCALG00GAIN0 0x7030 /* ADC Calibration Range 00 Gain Low Byte */
+#define SFRXADDR_ADCCALG00GAIN1 0x7031 /* ADC Calibration Range 00 Gain High Byte */
+#define SFRXADDR_ADCCALG01GAIN0 0x7032 /* ADC Calibration Range 01 Gain Low Byte */
+#define SFRXADDR_ADCCALG01GAIN1 0x7033 /* ADC Calibration Range 01 Gain High Byte */
+#define SFRXADDR_ADCCALG10GAIN0 0x7034 /* ADC Calibration Range 10 Gain Low Byte */
+#define SFRXADDR_ADCCALG10GAIN1 0x7035 /* ADC Calibration Range 10 Gain High Byte */
+#define SFRXADDR_ADCCALTEMPGAIN0 0x7038 /* ADC Calibration Temperature Gain Low Byte */
+#define SFRXADDR_ADCCALTEMPGAIN1 0x7039 /* ADC Calibration Temperature Gain High Byte */
+#define SFRXADDR_ADCCALTEMPOFFS0 0x703A /* ADC Calibration Temperature Offset Low Byte */
+#define SFRXADDR_ADCCALTEMPOFFS1 0x703B /* ADC Calibration Temperature Offset High Byte */
+#define SFRXADDR_ADCCH0VAL0 0x7020 /* ADC Channel 0 Low Byte */
+#define SFRXADDR_ADCCH0VAL1 0x7021 /* ADC Channel 0 High Byte */
+#define SFRXADDR_ADCCH1VAL0 0x7022 /* ADC Channel 1 Low Byte */
+#define SFRXADDR_ADCCH1VAL1 0x7023 /* ADC Channel 1 High Byte */
+#define SFRXADDR_ADCCH2VAL0 0x7024 /* ADC Channel 2 Low Byte */
+#define SFRXADDR_ADCCH2VAL1 0x7025 /* ADC Channel 2 High Byte */
+#define SFRXADDR_ADCCH3VAL0 0x7026 /* ADC Channel 3 Low Byte */
+#define SFRXADDR_ADCCH3VAL1 0x7027 /* ADC Channel 3 High Byte */
+#define SFRXADDR_ADCTUNE0 0x7028 /* ADC Tuning 0 */
+#define SFRXADDR_ADCTUNE1 0x7029 /* ADC Tuning 1 */
+#define SFRXADDR_ADCTUNE2 0x702A /* ADC Tuning 2 */
+#define SFRXADDR_CLOCKGATE 0x7F1B /* Clock Gating */
+#define SFRXADDR_DMA0ADDR0 0x7010 /* DMA Channel 0 Address Low Byte */
+#define SFRXADDR_DMA0ADDR1 0x7011 /* DMA Channel 0 Address High Byte */
+#define SFRXADDR_DMA0CONFIG 0x7014 /* DMA Channel 0 Configuration */
+#define SFRXADDR_DMA1ADDR0 0x7012 /* DMA Channel 1 Address Low Byte */
+#define SFRXADDR_DMA1ADDR1 0x7013 /* DMA Channel 1 Address High Byte */
+#define SFRXADDR_DMA1CONFIG 0x7015 /* DMA Channel 1 Configuration */
+#define SFRXADDR_FRCOSCCONFIG 0x7070 /* Fast RC Oscillator Calibration Configuration */
+#define SFRXADDR_FRCOSCCTRL 0x7071 /* Fast RC Oscillator Control */
+#define SFRXADDR_FRCOSCFREQ0 0x7076 /* Fast RC Oscillator Frequency Tuning Low Byte */
+#define SFRXADDR_FRCOSCFREQ1 0x7077 /* Fast RC Oscillator Frequency Tuning High Byte */
+#define SFRXADDR_FRCOSCKFILT0 0x7072 /* Fast RC Oscillator Calibration Filter Constant Low Byte */
+#define SFRXADDR_FRCOSCKFILT1 0x7073 /* Fast RC Oscillator Calibration Filter Constant High Byte */
+#define SFRXADDR_FRCOSCPER0 0x7078 /* Fast RC Oscillator Period Low Byte */
+#define SFRXADDR_FRCOSCPER1 0x7079 /* Fast RC Oscillator Period High Byte */
+#define SFRXADDR_FRCOSCREF0 0x7074 /* Fast RC Oscillator Reference Frequency Low Byte */
+#define SFRXADDR_FRCOSCREF1 0x7075 /* Fast RC Oscillator Reference Frequency High Byte */
+#define SFRXADDR_ANALOGA 0x7007 /* Port A Analog Mode */
+#define SFRXADDR_GPIOENABLE 0x700C /* GPIO Port Enable */
+#define SFRXADDR_EXTIRQ 0x7003 /* External IRQ Configuration */
+#define SFRXADDR_INTCHGA 0x7000 /* Port A Interrupt on Change */
+#define SFRXADDR_INTCHGB 0x7001 /* Port B Interrupt on Change */
+#define SFRXADDR_INTCHGC 0x7002 /* Port C Interrupt on Change */
+#define SFRXADDR_PALTA 0x7008 /* Port A Alternate Function */
+#define SFRXADDR_PALTB 0x7009 /* Port B Alternate Function */
+#define SFRXADDR_PALTC 0x700A /* Port C Alternate Function */
+#define SFRXADDR_PALTRADIO 0x7046 /* Port Radio Alternate Function */
+#define SFRXADDR_PINCHGA 0x7004 /* Port A Level Change */
+#define SFRXADDR_PINCHGB 0x7005 /* Port B Level Change */
+#define SFRXADDR_PINCHGC 0x7006 /* Port C Level Change */
+#define SFRXADDR_PINSEL 0x700B /* Port Input Selection */
+#define SFRXADDR_LPOSCCONFIG 0x7060 /* Low Power Oscillator Calibration Configuration */
+#define SFRXADDR_LPOSCFREQ0 0x7066 /* Low Power Oscillator Frequency Tuning Low Byte */
+#define SFRXADDR_LPOSCFREQ1 0x7067 /* Low Power Oscillator Frequency Tuning High Byte */
+#define SFRXADDR_LPOSCKFILT0 0x7062 /* Low Power Oscillator Calibration Filter Constant Low Byte */
+#define SFRXADDR_LPOSCKFILT1 0x7063 /* Low Power Oscillator Calibration Filter Constant High Byte */
+#define SFRXADDR_LPOSCPER0 0x7068 /* Low Power Oscillator Period Low Byte */
+#define SFRXADDR_LPOSCPER1 0x7069 /* Low Power Oscillator Period High Byte */
+#define SFRXADDR_LPOSCREF0 0x7064 /* Low Power Oscillator Reference Frequency Low Byte */
+#define SFRXADDR_LPOSCREF1 0x7065 /* Low Power Oscillator Reference Frequency High Byte */
+#define SFRXADDR_LPXOSCGM 0x7054 /* Low Power Crystal Oscillator Transconductance */
+#define SFRXADDR_MISCCTRL 0x7F01 /* Miscellaneous Control */
+#define SFRXADDR_OSCCALIB 0x7053 /* Oscillator Calibration Interrupt / Status */
+#define SFRXADDR_OSCFORCERUN 0x7050 /* Oscillator Run Force */
+#define SFRXADDR_OSCREADY 0x7052 /* Oscillator Ready Status */
+#define SFRXADDR_OSCRUN 0x7051 /* Oscillator Run Status */
+#define SFRXADDR_POWCTRL0 0x7F10 /* Power Control 0 */
+#define SFRXADDR_POWCTRL1 0x7F11 /* Power Control 1 */
+#define SFRXADDR_POWCTRL2 0x7F12 /* Power Control 2 */
+#define SFRXADDR_RADIOFDATAADDR0 0x7040 /* Radio FIFO Data Register Address Low Byte */
+#define SFRXADDR_RADIOFDATAADDR1 0x7041 /* Radio FIFO Data Register Address High Byte */
+#define SFRXADDR_RADIOFSTATADDR0 0x7042 /* Radio FIFO Status Register Address Low Byte */
+#define SFRXADDR_RADIOFSTATADDR1 0x7043 /* Radio FIFO Status Register Address High Byte */
+#define SFRXADDR_RADIOMUX 0x7044 /* Radio Multiplexer Control */
+#define SFRXADDR_SCRATCH0 0x7084 /* Scratch Register 0 */
+#define SFRXADDR_SCRATCH1 0x7085 /* Scratch Register 1 */
+#define SFRXADDR_SCRATCH2 0x7086 /* Scratch Register 2 */
+#define SFRXADDR_SCRATCH3 0x7087 /* Scratch Register 3 */
+#define SFRXADDR_SILICONREV 0x7F00 /* Silicon Revision */
+#define SFRXADDR_XTALAMPL 0x7F19 /* Crystal Oscillator Amplitude Control */
+#define SFRXADDR_XTALOSC 0x7F18 /* Crystal Oscillator Configuration */
+#define SFRXADDR_XTALREADY 0x7F1A /* Crystal Oscillator Ready Mode */
+
+/* X Address Space aliases of SFR Address Space Registers */
+
+#define SFRXADDR_XIE 0x3FA8 /* Interrupt Enable */
+#define SFRXADDR_XIP 0x3FB8 /* Interrupt Priority */
+#define SFRXADDR_XPCON 0x3F87 /* Power Mode Control */
+#define SFRXADDR_XADCCH0CONFIG 0x3FCA /* ADC Channel 0 Configuration */
+#define SFRXADDR_XADCCH1CONFIG 0x3FCB /* ADC Channel 1 Configuration */
+#define SFRXADDR_XADCCH2CONFIG 0x3FD2 /* ADC Channel 2 Configuration */
+#define SFRXADDR_XADCCH3CONFIG 0x3FD3 /* ADC Channel 3 Configuration */
+#define SFRXADDR_XADCCLKSRC 0x3FD1 /* ADC Clock Source */
+#define SFRXADDR_XADCCONV 0x3FC9 /* ADC Conversion Source */
+#define SFRXADDR_XANALOGCOMP 0x3FE1 /* Analog Comparators */
+#define SFRXADDR_XCLKCON 0x3FC6 /* Clock Control */
+#define SFRXADDR_XCLKSTAT 0x3FC7 /* Clock Status */
+#define SFRXADDR_XCODECONFIG 0x3F97 /* Code Space Configuration */
+#define SFRXADDR_XDBGLNKBUF 0x3FE3 /* Debug Link Buffer */
+#define SFRXADDR_XDBGLNKSTAT 0x3FE2 /* Debug Link Status */
+#define SFRXADDR_XDIRA 0x3F89 /* Port A Direction */
+#define SFRXADDR_XDIRB 0x3F8A /* Port B Direction */
+#define SFRXADDR_XDIRC 0x3F8B /* Port C Direction */
+#define SFRXADDR_XDIRR 0x3F8E /* Port R Direction */
+#define SFRXADDR_XPINA 0x3FC8 /* Port A Input */
+#define SFRXADDR_XPINB 0x3FE8 /* Port B Input */
+#define SFRXADDR_XPINC 0x3FF8 /* Port C Input */
+#define SFRXADDR_XPINR 0x3F8D /* Port R Input */
+#define SFRXADDR_XPORTA 0x3F80 /* Port A Output */
+#define SFRXADDR_XPORTB 0x3F88 /* Port B Output */
+#define SFRXADDR_XPORTC 0x3F90 /* Port C Output */
+#define SFRXADDR_XPORTR 0x3F8C /* Port R Output */
+#define SFRXADDR_XIC0CAPT0 0x3FCE /* Input Capture 0 Low Byte */
+#define SFRXADDR_XIC0CAPT1 0x3FCF /* Input Capture 0 High Byte */
+#define SFRXADDR_XIC0MODE 0x3FCC /* Input Capture 0 Mode */
+#define SFRXADDR_XIC0STATUS 0x3FCD /* Input Capture 0 Status */
+#define SFRXADDR_XIC1CAPT0 0x3FD6 /* Input Capture 1 Low Byte */
+#define SFRXADDR_XIC1CAPT1 0x3FD7 /* Input Capture 1 High Byte */
+#define SFRXADDR_XIC1MODE 0x3FD4 /* Input Capture 1 Mode */
+#define SFRXADDR_XIC1STATUS 0x3FD5 /* Input Capture 1 Status */
+#define SFRXADDR_XNVADDR0 0x3F92 /* Non-Volatile Memory Address Low Byte */
+#define SFRXADDR_XNVADDR1 0x3F93 /* Non-Volatile Memory Address High Byte */
+#define SFRXADDR_XNVDATA0 0x3F94 /* Non-Volatile Memory Data Low Byte */
+#define SFRXADDR_XNVDATA1 0x3F95 /* Non-Volatile Memory Data High Byte */
+#define SFRXADDR_XNVKEY 0x3F96 /* Non-Volatile Memory Write/Erase Key */
+#define SFRXADDR_XNVSTATUS 0x3F91 /* Non-Volatile Memory Command / Status */
+#define SFRXADDR_XOC0COMP0 0x3FBC /* Output Compare 0 Low Byte */
+#define SFRXADDR_XOC0COMP1 0x3FBD /* Output Compare 0 High Byte */
+#define SFRXADDR_XOC0MODE 0x3FB9 /* Output Compare 0 Mode */
+#define SFRXADDR_XOC0PIN 0x3FBA /* Output Compare 0 Pin Configuration */
+#define SFRXADDR_XOC0STATUS 0x3FBB /* Output Compare 0 Status */
+#define SFRXADDR_XOC1COMP0 0x3FC4 /* Output Compare 1 Low Byte */
+#define SFRXADDR_XOC1COMP1 0x3FC5 /* Output Compare 1 High Byte */
+#define SFRXADDR_XOC1MODE 0x3FC1 /* Output Compare 1 Mode */
+#define SFRXADDR_XOC1PIN 0x3FC2 /* Output Compare 1 Pin Configuration */
+#define SFRXADDR_XOC1STATUS 0x3FC3 /* Output Compare 1 Status */
+#define SFRXADDR_XRADIOACC 0x3FB1 /* Radio Controller Access Mode */
+#define SFRXADDR_XRADIOADDR0 0x3FB3 /* Radio Register Address Low Byte */
+#define SFRXADDR_XRADIOADDR1 0x3FB2 /* Radio Register Address High Byte */
+#define SFRXADDR_XRADIODATA0 0x3FB7 /* Radio Register Data 0 */
+#define SFRXADDR_XRADIODATA1 0x3FB6 /* Radio Register Data 1 */
+#define SFRXADDR_XRADIODATA2 0x3FB5 /* Radio Register Data 2 */
+#define SFRXADDR_XRADIODATA3 0x3FB4 /* Radio Register Data 3 */
+#define SFRXADDR_XRADIOSTAT0 0x3FBE /* Radio Access Status Low Byte */
+#define SFRXADDR_XRADIOSTAT1 0x3FBF /* Radio Access Status High Byte */
+#define SFRXADDR_XSPCLKSRC 0x3FDF /* SPI Clock Source */
+#define SFRXADDR_XSPMODE 0x3FDC /* SPI Mode */
+#define SFRXADDR_XSPSHREG 0x3FDE /* SPI Shift Register */
+#define SFRXADDR_XSPSTATUS 0x3FDD /* SPI Status */
+#define SFRXADDR_XT0CLKSRC 0x3F9A /* Timer 0 Clock Source */
+#define SFRXADDR_XT0CNT0 0x3F9C /* Timer 0 Count Low Byte */
+#define SFRXADDR_XT0CNT1 0x3F9D /* Timer 0 Count High Byte */
+#define SFRXADDR_XT0MODE 0x3F99 /* Timer 0 Mode */
+#define SFRXADDR_XT0PERIOD0 0x3F9E /* Timer 0 Period Low Byte */
+#define SFRXADDR_XT0PERIOD1 0x3F9F /* Timer 0 Period High Byte */
+#define SFRXADDR_XT0STATUS 0x3F9B /* Timer 0 Status */
+#define SFRXADDR_XT1CLKSRC 0x3FA2 /* Timer 1 Clock Source */
+#define SFRXADDR_XT1CNT0 0x3FA4 /* Timer 1 Count Low Byte */
+#define SFRXADDR_XT1CNT1 0x3FA5 /* Timer 1 Count High Byte */
+#define SFRXADDR_XT1MODE 0x3FA1 /* Timer 1 Mode */
+#define SFRXADDR_XT1PERIOD0 0x3FA6 /* Timer 1 Period Low Byte */
+#define SFRXADDR_XT1PERIOD1 0x3FA7 /* Timer 1 Period High Byte */
+#define SFRXADDR_XT1STATUS 0x3FA3 /* Timer 1 Status */
+#define SFRXADDR_XT2CLKSRC 0x3FAA /* Timer 2 Clock Source */
+#define SFRXADDR_XT2CNT0 0x3FAC /* Timer 2 Count Low Byte */
+#define SFRXADDR_XT2CNT1 0x3FAD /* Timer 2 Count High Byte */
+#define SFRXADDR_XT2MODE 0x3FA9 /* Timer 2 Mode */
+#define SFRXADDR_XT2PERIOD0 0x3FAE /* Timer 2 Period Low Byte */
+#define SFRXADDR_XT2PERIOD1 0x3FAF /* Timer 2 Period High Byte */
+#define SFRXADDR_XT2STATUS 0x3FAB /* Timer 2 Status */
+#define SFRXADDR_XU0CTRL 0x3FE4 /* UART 0 Control */
+#define SFRXADDR_XU0MODE 0x3FE7 /* UART 0 Mode */
+#define SFRXADDR_XU0SHREG 0x3FE6 /* UART 0 Shift Register */
+#define SFRXADDR_XU0STATUS 0x3FE5 /* UART 0 Status */
+#define SFRXADDR_XU1CTRL 0x3FEC /* UART 1 Control */
+#define SFRXADDR_XU1MODE 0x3FEF /* UART 1 Mode */
+#define SFRXADDR_XU1SHREG 0x3FEE /* UART 1 Shift Register */
+#define SFRXADDR_XU1STATUS 0x3FED /* UART 1 Status */
+#define SFRXADDR_XWDTCFG 0x3FDA /* Watchdog Configuration */
+#define SFRXADDR_XWDTRESET 0x3FDB /* Watchdog Reset */
+#define SFRXADDR_XWTCFGA 0x3FF1 /* Wakeup Timer A Configuration */
+#define SFRXADDR_XWTCFGB 0x3FF9 /* Wakeup Timer B Configuration */
+#define SFRXADDR_XWTCNTA0 0x3FF2 /* Wakeup Counter A Low Byte */
+#define SFRXADDR_XWTCNTA1 0x3FF3 /* Wakeup Counter A High Byte */
+#define SFRXADDR_XWTCNTB0 0x3FFA /* Wakeup Counter B Low Byte */
+#define SFRXADDR_XWTCNTB1 0x3FFB /* Wakeup Counter B High Byte */
+#define SFRXADDR_XWTCNTR1 0x3FEB /* Wakeup Counter High Byte Latch */
+#define SFRXADDR_XWTEVTA0 0x3FF4 /* Wakeup Event A Low Byte */
+#define SFRXADDR_XWTEVTA1 0x3FF5 /* Wakeup Event A High Byte */
+#define SFRXADDR_XWTEVTB0 0x3FF6 /* Wakeup Event B Low Byte */
+#define SFRXADDR_XWTEVTB1 0x3FF7 /* Wakeup Event B High Byte */
+#define SFRXADDR_XWTEVTC0 0x3FFC /* Wakeup Event C Low Byte */
+#define SFRXADDR_XWTEVTC1 0x3FFD /* Wakeup Event C High Byte */
+#define SFRXADDR_XWTEVTD0 0x3FFE /* Wakeup Event D Low Byte */
+#define SFRXADDR_XWTEVTD1 0x3FFF /* Wakeup Event D High Byte */
+#define SFRXADDR_XWTIRQEN 0x3FE9 /* Wakeup Timer Interrupt Enable */
+#define SFRXADDR_XWTSTAT 0x3FEA /* Wakeup Timer Status */
+
+#endif /* AX8052REGADDR_H */
diff --git a/libs/libmf/include/axcompiler.h b/libs/libmf/include/axcompiler.h
new file mode 100644
index 00000000..2494971d
--- /dev/null
+++ b/libs/libmf/include/axcompiler.h
@@ -0,0 +1,201 @@
+/*-------------------------------------------------------------------------
+ axcompiler.h
+
+ Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+ /*
+ * Header file to overcome 8051 compiler differences for specifying
+ * special function registers. The following compilers are supported:
+ * SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhaeuser.
+ * Unfortunately not for use with Dunfield. The compilers are identified by
+ * their unique predefined macros. See also:
+ * http://predef.sourceforge.net/precomp.html
+ *
+ * SBIT and SFR define special bit and special function registers at the given
+ * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in
+ * little-endian format. SFR16E and SFR32E define sfr combinations without
+ * prerequisite byte order or adjacency. None of these multi-byte sfr
+ * combinations will guarantee the order in which they are accessed when read
+ * or written.
+ * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined
+ * to avoid portability issues because of compiler endianness.
+ * SFR16LEX is provided for 16 bit little endian xdata registers. It is usable
+ * on little endian compilers only; on big endian compilers, these registers
+ * will not be defined.
+ * This file is to be included in every microcontroller specific header file.
+ * Example:
+ *
+ * // my_mcu.h: sfr definitions for my mcu
+ * #include
+ *
+ * SBIT (P0_1, 0x80, 1) // Port 0 pin 1
+ *
+ * SFR (P0, 0x80) // Port 0
+ *
+ * SFRX (CPUCS, 0xE600) // Cypress FX2 Control and Status register in xdata memory at 0xE600
+ *
+ * SFR16 (TMR2, 0xCC) // Timer 2, lsb at 0xCC, msb at 0xCD
+ *
+ * SFR16E(TMR0, 0x8C8A) // Timer 0, lsb at 0x8A, msb at 0x8C
+ *
+ * SFR32 (MAC0ACC, 0x93) // SiLabs C8051F120 32 bits MAC0 Accumulator, lsb at 0x93, msb at 0x96
+ *
+ * SFR32E(SUMR, 0xE5E4E3E2) // TI MSC1210 SUMR 32 bits Summation register, lsb at 0xE2, msb at 0xE5
+ *
+ */
+
+#ifndef AXCOMPILER_H
+#define AXCOMPILER_H
+
+/** SDCC - Small Device C Compiler
+ * http://sdcc.sf.net
+ */
+#if defined SDCC
+# define SBIT(name, addr, bit) __sbit __at(addr+bit) name ;
+# define SFR(name, addr) __sfr __at(addr) name ;
+# define SFRX(name, addr) __xdata volatile unsigned char __at(addr) name ;
+# define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name ;
+# define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name ;
+# define SFR16LEX(name, addr) __xdata volatile unsigned short __at(addr) name ;
+# define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name ;
+# define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name ;
+
+/** Keil C51
+ * http://www.keil.com
+ */
+#elif defined __CX51__ || defined __C51__
+# define SBIT(name, addr, bit) sbit name = addr^bit ;
+# define SFR(name, addr) sfr name = addr ;
+# define SFRX(name, addr) static volatile unsigned char xdata name _at_ addr ;
+# define SFR16(name, addr) sfr16 name = addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Raisonance
+ * http://www.raisonance.com
+ */
+#elif defined __RC51__
+# define SBIT(name, addr, bit) at (addr+bit) sbit name ;
+# define SFR(name, addr) sfr at addr name ;
+# define SFRX(name, addr) xdata at addr volatile unsigned char name ;
+# define SFR16(name, addr) sfr16 at addr name ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** IAR 8051
+ * http://www.iar.com
+ */
+#elif defined __ICC8051__
+
+#pragma language=extended
+#include
+
+# define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) ;
+# define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr ;
+# define SFRX(name, addr) extern __xdata __no_init volatile unsigned char name @ addr ;
+# define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr ;
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Tasking / Altium
+ * http://www.altium.com/tasking
+ */
+#elif defined _CC51
+# define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) ;
+# define SFR(name, addr) _sfrbyte name _at(addr) ;
+# define SFRX(name, addr) _xdat volatile unsigned char name _at(addr) ;
+#if _CC51 > 71
+# define SFR16(name, addr) _sfrword _little name _at(addr) ;
+#else
+# define SFR16(name, addr) /* not supported */
+#endif
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Hi-Tech 8051
+ * http://www.htsoft.com
+ */
+#elif defined HI_TECH_C
+# define SBIT(name, addr, bit) volatile bit name @ (addr+bit) ;
+# define SFR(name, addr) volatile unsigned char name @ addr ;
+# define SFRX(name, addr) volatile far unsigned char name @ addr ;
+# define SFR16(name, addr) /* not supported */
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Crossware
+ * http://www.crossware.com
+ */
+#elif defined _XC51_VER
+# define SBIT(name, addr, bit) _sfrbit name = (addr+bit) ;
+# define SFR(name, addr) _sfr name = addr ;
+# define SFRX(name, addr) volatile unsigned char _xdata name _at addr ;
+# define SFR16(name, addr) _sfrword name = addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Wickenhaeuser
+ * http://www.wickenhaeuser.de
+ */
+#elif defined __UC__
+# define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) ;
+# define SFR(name, addr) near unsigned char name @ addr ;
+# define SFRX(name, addr) xdata volatile unsigned char name @ addr ;
+# define SFR16(name, addr) /* not supported */
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** default
+ * unrecognized compiler
+ */
+#else
+# warning unrecognized compiler
+# define SBIT(name, addr, bit) volatile bool name ;
+# define SFR(name, addr) volatile unsigned char name ;
+# define SFRX(name, addr) volatile unsigned char name ;
+# define SFR16(name, addr) volatile unsigned short name ;
+# define SFR16E(name, fulladdr) volatile unsigned short name ;
+# define SFR16LEX(name, addr) volatile unsigned short name ;
+# define SFR32(name, fulladdr) volatile unsigned long name ;
+# define SFR32E(name, fulladdr) volatile unsigned long name ;
+
+#endif
+
+#endif //AXCOMPILER_H
diff --git a/libs/libmf/include/libmf.h b/libs/libmf/include/libmf.h
new file mode 100644
index 00000000..84245000
--- /dev/null
+++ b/libs/libmf/include/libmf.h
@@ -0,0 +1,14 @@
+#ifndef LIBMF_H
+#define LIBMF_H
+
+#include "libmftypes.h"
+#include "libmfdbglink.h"
+#include "libmfcrc.h"
+#include "libmfflash.h"
+#include "libmfuart.h"
+#include "libmfadc.h"
+#include "libmfbch.h"
+#include "libmfcalsector.h"
+#include "libmfradio.h"
+
+#endif /* LIBMF_H */
diff --git a/libs/libmf/include/libmfadc.h b/libs/libmf/include/libmfadc.h
new file mode 100644
index 00000000..5ad25272
--- /dev/null
+++ b/libs/libmf/include/libmfadc.h
@@ -0,0 +1,19 @@
+#ifndef LIBMFADC_H
+#define LIBMFADC_H
+
+#include "libmftypes.h"
+
+/*
+ * AD Converter
+ */
+extern __reentrantb int16_t adc_measure_temperature(void) __reentrant;
+
+extern void adc_calibrate_gain(void);
+extern void adc_calibrate_temp(void);
+extern void adc_calibrate(void);
+extern void adc_uncalibrate(void);
+extern uint16_t adc_singleended_offset_x01(void);
+extern uint16_t adc_singleended_offset_x1(void);
+extern uint16_t adc_singleended_offset_x10(void);
+
+#endif /* LIBMFADC_H */
diff --git a/libs/libmf/include/libmfbch.h b/libs/libmf/include/libmfbch.h
new file mode 100644
index 00000000..e212a34b
--- /dev/null
+++ b/libs/libmf/include/libmfbch.h
@@ -0,0 +1,27 @@
+#ifndef LIBMFBCH_H
+#define LIBMFBCH_H
+
+#include "libmftypes.h"
+
+/*
+ * BCH(31,21,5) Code (with and without parity) routines
+ * Data Format:
+ * Bits 31-11: Data
+ * Bits 10- 1: BCH Parity Bits
+ * Bit 0: Even Parity Bit
+ */
+
+extern uint16_t bch3121_syndrome(uint32_t cw);
+extern uint32_t bch3121_encode(uint32_t cw);
+extern uint32_t bch3121_encode_parity(uint32_t cw);
+
+/* Bit 0 of the return value indicates decoding error */
+extern uint32_t bch3121_decode(uint32_t cw);
+extern uint32_t bch3121_decode_parity(uint32_t cw);
+
+/*
+ * BCH Internals
+ */
+extern const uint16_t __code bch3121_syndrometable[1024];
+
+#endif /* LIBMFBCH_H */
diff --git a/libs/libmf/include/libmfcalsector.h b/libs/libmf/include/libmfcalsector.h
new file mode 100644
index 00000000..55f19d31
--- /dev/null
+++ b/libs/libmf/include/libmfcalsector.h
@@ -0,0 +1,35 @@
+#ifndef LIBMFCALSECTOR_H
+#define LIBMFCALSECTOR_H
+
+#include "libmftypes.h"
+
+/*
+ * FLASH Calibration Sector Layout
+ */
+
+struct calsector {
+ uint8_t id[5]; /* ID: 0x80, 0xFE, CAL */
+ uint8_t len; /* Length, excluding id, but including len */
+ uint8_t devid[6]; /* arbitrary device ID */
+ uint8_t calg00gain[2]; /* ADC x0.1 Gain Calibration */
+ uint8_t calg01gain[2]; /* ADC x1 Gain Calibration */
+ uint8_t calg10gain[2]; /* ADC x10 Gain Calibration */
+ uint8_t caltempgain[2]; /* ADC Temperature Gain Calibration */
+ uint8_t caltempoffs[2]; /* ADC Temperature Offset Calibration */
+ uint8_t frcoscfreq[2]; /* Fast RC Oscillator Frequency Calibration */
+ uint8_t lposcfreq[2]; /* Low Power Oscillator Frequency Calibration, Slow Mode */
+ uint8_t lposcfreq_fast[2]; /* Low Power Oscillator Frequency Calibration, Fast Mode */
+ uint8_t powctrl0; /* VDD_CORE Calibration */
+ uint8_t powctrl1; /* VDD_SLEEP Calibration */
+ uint8_t ref; /* Ref Calibration */
+};
+
+#if defined(SDCC)
+static struct calsector __xdata __at(0xfc00) flash_calsector;
+#elif defined __CX51__ || defined __C51__
+static struct calsector xdata flash_calsector _at_ 0xfc00;
+#elif defined __ICC8051__
+extern __no_init struct calsector __xdata flash_calsector @ 0xfc00;
+#endif
+
+#endif /* LIBMFCALSECTOR_H */
diff --git a/libs/libmf/include/libmfcrc.h b/libs/libmf/include/libmfcrc.h
new file mode 100644
index 00000000..21ce7817
--- /dev/null
+++ b/libs/libmf/include/libmfcrc.h
@@ -0,0 +1,98 @@
+#ifndef LIBMFCRC_H
+#define LIBMFCRC_H
+
+#include "libmftypes.h"
+
+/*
+ * CRC-16 CCITT
+ */
+extern __reentrantb uint16_t crc_ccitt_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_ccitt_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_ccitt(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_ccitt_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_ccitt_table[256];
+extern const uint16_t __code crc_ccitt_msbtable[256];
+
+/*
+ * CRC-16
+ */
+extern __reentrantb uint16_t crc_crc16_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_crc16_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_crc16_table[256];
+extern const uint16_t __code crc_crc16_msbtable[256];
+
+/*
+ * CRC-16 DNP
+ */
+extern __reentrantb uint16_t crc_crc16dnp_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_crc16dnp_table[256];
+extern const uint16_t __code crc_crc16dnp_msbtable[256];
+
+/*
+ * CRC-32
+ */
+extern __reentrantb uint32_t crc_crc32_byte(uint32_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint32_t crc_crc32_msb_byte(uint32_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint32_t crc_crc32(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant;
+extern __reentrantb uint32_t crc_crc32_msb(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant;
+extern const uint32_t __code crc_crc32_table[256];
+extern const uint32_t __code crc_crc32_msbtable[256];
+
+/*
+ * CRC-8 CCITT
+ */
+
+extern __reentrantb uint8_t crc_crc8ccitt_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt_msb_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt_msb(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern const uint8_t __code crc_crc8ccitt_table[256];
+extern const uint8_t __code crc_crc8ccitt_msbtable[256];
+
+/*
+ * CRC-8 OneWire
+ */
+
+extern __reentrantb uint8_t crc_crc8onewire_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire_msb_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire_msb(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern const uint8_t __code crc_crc8onewire_table[256];
+extern const uint8_t __code crc_crc8onewire_msbtable[256];
+
+/*
+ * CRC-8 CCITT, non-table driven routines (slower, but more compact)
+ */
+extern __reentrantb uint8_t crc8_ccitt_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc8_ccitt(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant;
+
+/*
+ * CRC-8 OneWire, non-table driven routines (slower, but more compact)
+ */
+extern __reentrantb uint8_t crc8_onewire_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc8_onewire(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant;
+
+/*
+ * PN9 Whitening Sequence
+ */
+extern __reentrantb uint16_t pn9_advance(uint16_t pn9) __reentrant;
+extern const uint8_t __code pn9_table[512];
+extern __reentrantb uint16_t pn9_advance_bit(uint16_t pn9) __reentrant;
+extern __reentrantb uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits) __reentrant;
+extern __reentrantb uint16_t pn9_advance_byte(uint16_t pn9) __reentrant;
+extern __reentrantb uint16_t pn9_buffer(uint8_t __generic *buf, uint16_t buflen, uint16_t pn9, uint8_t xor) __reentrant;
+
+/*
+ * PN15 Whitening Sequence
+ */
+extern __reentrantb uint16_t pn15_advance(uint16_t pn15) __reentrant;
+extern __reentrantb uint8_t pn15_output(uint16_t pn15) __reentrant;
+extern const uint16_t __code pn15_adv_table[256];
+extern const uint8_t __code pn15_out_table[256];
+
+#endif /* LIBMFCRC_H */
diff --git a/libs/libmf/include/libmfdbglink.h b/libs/libmf/include/libmfdbglink.h
new file mode 100644
index 00000000..47a0a0f4
--- /dev/null
+++ b/libs/libmf/include/libmfdbglink.h
@@ -0,0 +1,140 @@
+#ifndef LIBMFDBGLINK_H
+#define LIBMFDBGLINK_H
+
+#include "libmftypes.h"
+
+/*
+ * DebugLink
+ */
+#if defined SDCC
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+static void dbglink_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _dbglink_rxbuffer \
+_dbglink_rxbuffer: \
+ .ds (sz) \
+ \
+ .area HOME (CODE) \
+ .area DBGLINK0 (CODE) \
+ .area DBGLINK1 (CODE) \
+ .area DBGLINK2 (CODE) \
+ .area DBGLINK3 (CODE) \
+ .area DBGLINK4 (CODE) \
+ .area DBGLINK5 (CODE) \
+ \
+ .area DBGLINK2 (CODE) \
+ .db 256-(sz) \
+ .db 257-(sz) \
+ \
+ .area DBGLINK5 (CODE) \
+ .db (sz) \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+static void dbglink_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _dbglink_txbuffer \
+_dbglink_txbuffer: \
+ .ds (sz) \
+ \
+ .area HOME (CODE) \
+ .area DBGLINK0 (CODE) \
+ .area DBGLINK1 (CODE) \
+ .area DBGLINK2 (CODE) \
+ .area DBGLINK3 (CODE) \
+ .area DBGLINK4 (CODE) \
+ .area DBGLINK5 (CODE) \
+ \
+ .area DBGLINK1 (CODE) \
+ .db 256-(sz) \
+ .db 257-(sz) \
+ \
+ .area DBGLINK4 (CODE) \
+ .db (sz) \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata dbglink_rxbuffer[sz]; \
+const uint8_t __code dbglink_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata dbglink_txbuffer[sz]; \
+const uint8_t __code dbglink_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata dbglink_rxbuffer[sz]; \
+const uint8_t __code dbglink_rxbuffer_size[] = { sz };
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata dbglink_txbuffer[sz]; \
+const uint8_t __code dbglink_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves dbglink_txbufptr,dbglink_txfreelinear,dbglink_rxbufptr,dbglink_rxcountlinear
+#pragma callee_saves dbglink_txfree,dbglink_rxcount,dbglink_wait_txfree,dbglink_wait_rxcount
+#pragma callee_saves dbglink_txbuffersize,dbglink_rxbuffersize,dbglink_rxpeek,dbglink_txpoke,dbglink_txpokehex
+#pragma callee_saves dbglink_init,dbglink_poll,dbglink_wait_txfree,dbglink_wait_rxcount,dbglink_rx,dbglink_tx
+extern void dbglink_irq(void) __interrupt(21) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t dbglink_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *dbglink_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *dbglink_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void dbglink_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void dbglink_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void dbglink_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void dbglink_txadvance(uint8_t idx) __reentrant __naked;
+
+extern __reentrantb void dbglink_init(void) __reentrant;
+extern __reentrantb void dbglink_wait_txdone(void) __reentrant;
+extern __reentrantb void dbglink_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void dbglink_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t dbglink_rx(void) __reentrant;
+extern __reentrantb void dbglink_tx(uint8_t v) __reentrant;
+extern __reentrantb void dbglink_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t dbglink_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t dbglink_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t dbglink_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t dbglink_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t dbglink_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t dbglink_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void dbglink_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void dbglink_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void dbglink_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void dbglink_writeu32(uint32_t val, uint8_t nrdig);
+
+#endif /* LIBMFDBGLINK_H */
diff --git a/libs/libmf/include/libmfflash.h b/libs/libmf/include/libmfflash.h
new file mode 100644
index 00000000..1a3a1e44
--- /dev/null
+++ b/libs/libmf/include/libmfflash.h
@@ -0,0 +1,26 @@
+#ifndef LIBMFFLASH_H
+#define LIBMFFLASH_H
+
+#include "libmftypes.h"
+
+/*
+ * FLASH
+ */
+extern void flash_unlock(void);
+extern void flash_lock(void);
+extern int8_t flash_wait(uint16_t timeout);
+extern int8_t flash_pageerase(uint16_t pgaddr);
+extern int8_t flash_write(uint16_t waddr, uint16_t wdata);
+extern uint16_t flash_read(uint16_t raddr);
+
+extern uint8_t flash_apply_calibration(void);
+typedef uint8_t flash_deviceid_t[6];
+#if defined(SDCC)
+static __xdata flash_deviceid_t __at(0xfc06) flash_deviceid;
+#elif defined __CX51__ || defined __C51__
+static flash_deviceid_t xdata flash_deviceid _at_ 0xfc06;
+#elif defined __ICC8051__
+static __xdata __no_init flash_deviceid_t flash_deviceid @ 0xfc06;
+#endif
+
+#endif /* LIBMFFLASH_H */
diff --git a/libs/libmf/include/libmflcd.h b/libs/libmf/include/libmflcd.h
new file mode 100644
index 00000000..30ed43ad
--- /dev/null
+++ b/libs/libmf/include/libmflcd.h
@@ -0,0 +1,36 @@
+#ifndef LIBMFLCD_H
+#define LIBMFLCD_H
+
+#include "libmftypes.h"
+
+/*
+ * LC Display
+ */
+#if defined SDCC
+#pragma callee_saves lcd_waitlong,lcd_waitshort,lcd_write,lcd_writecmd,lcd_writedata,lcd_portoff,lcd_portinit,lcd_init,lcd_setpos
+#endif
+
+extern void lcd_waitlong(void);
+extern void lcd_waitshort(void);
+extern void lcd_write(uint8_t v);
+extern void lcd_writecmd(uint8_t cmd);
+extern void lcd_writedata(uint8_t d);
+extern void lcd_portoff(void);
+extern void lcd_portinit(void);
+extern void lcd_init(void);
+extern void lcd_setpos(uint8_t v);
+extern void lcd_writestr(const char __generic *ch);
+extern void lcd_cleardisplay(void);
+extern void lcd_clear(uint8_t pos, uint8_t len);
+extern __reentrantb uint8_t lcd_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern uint8_t lcd_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern __reentrantb uint8_t lcd_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern uint8_t lcd_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+
+/* legacy */
+extern void lcd_writehexu16(uint16_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writehexu32(uint32_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writeu16(uint16_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writeu32(uint32_t val, uint8_t nrdig, uint8_t pos);
+
+#endif /* LIBMFLCD_H */
diff --git a/libs/libmf/include/libmfosc.h b/libs/libmf/include/libmfosc.h
new file mode 100644
index 00000000..3b430a0a
--- /dev/null
+++ b/libs/libmf/include/libmfosc.h
@@ -0,0 +1,154 @@
+#ifndef LIBMFOSC_H
+#define LIBMFOSC_H
+
+#include "libmftypes.h"
+
+extern __reentrantb void turn_off_xosc(void) __reentrant;
+extern __reentrantb void turn_off_lpxosc(void) __reentrant;
+
+#if defined SDCC
+#pragma callee_saves setup_xosc,setup_lpxosc
+#endif
+extern __reentrantb void setup_xosc(void) __reentrant;
+extern __reentrantb void setup_lpxosc(void) __reentrant;
+
+extern __reentrantb uint8_t setup_osc_calibration(uint32_t reffreq, uint8_t refosc) __reentrant;
+
+/*
+ * Clock Sources
+ */
+#define CLKSRC_FRCOSC 0
+#define CLKSRC_LPOSC 1
+#define CLKSRC_XOSC 2
+#define CLKSRC_LPXOSC 3
+#define CLKSRC_RSYSCLK 4
+#define CLKSRC_TCLK 5
+#define CLKSRC_SYSCLK 6
+#define CLKSRC_OFF 7
+
+#if defined(__ICC8051__)
+#define __osc_set_frcoscref(x) do { FRCOSCREF0 = (x); FRCOSCREF1 = (x) >> 8; } while(0)
+#define __osc_set_lposcref(x) do { LPOSCREF0 = (x); LPOSCREF1 = (x) >> 8; } while(0)
+#define __osc_set_filt() do { FRCOSCKFILT0 = 0x00; FRCOSCKFILT1 = 0x40; LPOSCKFILT0 = 0x00; LPOSCKFILT1 = 0x40; } while (0)
+#else
+#define __osc_set_frcoscref(x) do { FRCOSCREF = (x); } while(0)
+#define __osc_set_lposcref(x) do { LPOSCREF = (x); } while(0)
+#define __osc_set_filt() do { FRCOSCKFILT = 0x4000; LPOSCKFILT = 0x4000; } while (0)
+#endif
+
+#define setup_osc_calibration_const(reffreq,refosc) \
+do { \
+ uint8_t ret = 0; \
+ uint8_t lposccfg; \
+ uint8_t frcosccfg; \
+ if ((reffreq) >= 32768000UL) { \
+ frcosccfg = 0; \
+ ret |= 1; \
+ } else if ((reffreq) >= 16384000UL) { \
+ frcosccfg = 0x78 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 7)); \
+ } else if ((reffreq) >= 8192000UL) { \
+ frcosccfg = 0x70 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 6)); \
+ } else if ((reffreq) >= 4096000UL) { \
+ frcosccfg = 0x68 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 5)); \
+ } else if ((reffreq) >= 2048000UL) { \
+ frcosccfg = 0x60 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 4)); \
+ } else if ((reffreq) >= 1024000UL) { \
+ frcosccfg = 0x58 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 3)); \
+ } else if ((reffreq) >= 512000UL) { \
+ frcosccfg = 0x50 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 2)); \
+ } else if ((reffreq) >= 256000UL) { \
+ frcosccfg = 0x48 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 1)); \
+ } else if ((reffreq) >= 128000UL) { \
+ frcosccfg = 0x40 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / (reffreq)); \
+ } else if ((reffreq) >= 64000UL) { \
+ frcosccfg = 0x38 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 7) / (reffreq)); \
+ } else if ((reffreq) >= 32000UL) { \
+ frcosccfg = 0x30 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 6) / (reffreq)); \
+ } else if ((reffreq) >= 16000UL) { \
+ frcosccfg = 0x28 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 5) / (reffreq)); \
+ } else if ((reffreq) >= 8000UL) { \
+ frcosccfg = 0x20 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 4) / (reffreq)); \
+ } else if ((reffreq) >= 4000UL) { \
+ frcosccfg = 0x18 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 3) / (reffreq)); \
+ } else if ((reffreq) >= 2000UL) { \
+ frcosccfg = 0x10 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 2) / (reffreq)); \
+ } else if ((reffreq) >= 1000UL) { \
+ frcosccfg = 0x08 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 1) / (reffreq)); \
+ } else if ((reffreq) >= 500UL) { \
+ frcosccfg = 0x00 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 0) / (reffreq)); \
+ } else { \
+ frcosccfg = 0; \
+ ret |= 1; \
+ } \
+ if ((reffreq) >= 2013265920UL || (reffreq) < 7864320UL) { \
+ lposccfg = 0x08 | CLKSRC_FRCOSC; \
+ __osc_set_lposcref(31250); \
+ } else if ((reffreq) >= 1006632960UL) { \
+ lposccfg = 0x38 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 40960UL); \
+ } else if ((reffreq) >= 503316480UL) { \
+ lposccfg = 0x30 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 20480UL); \
+ } else if ((reffreq) >= 251658240UL) { \
+ lposccfg = 0x28 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 10240UL); \
+ } else if ((reffreq) >= 125829120UL) { \
+ lposccfg = 0x20 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 5120UL); \
+ } else if ((reffreq) >= 62914560UL) { \
+ lposccfg = 0x18 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 2560UL); \
+ } else if ((reffreq) >= 31457280UL) { \
+ lposccfg = 0x10 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 1280UL); \
+ } else if ((reffreq) >= 15728640UL) { \
+ lposccfg = 0x08 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 640UL); \
+ } else { \
+ lposccfg = 0x00 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 320UL); \
+ } \
+ if (!ret) { \
+ switch (refosc) { \
+ case CLKSRC_XOSC: \
+ setup_xosc(); \
+ OSCFORCERUN |= 0x04; \
+ break; \
+ \
+ case CLKSRC_LPXOSC: \
+ setup_lpxosc(); \
+ OSCFORCERUN |= 0x08; \
+ break; \
+ \
+ case CLKSRC_RSYSCLK: \
+ break; \
+ \
+ default: \
+ ret = 2; \
+ break; \
+ } \
+ if (!ret) { \
+ __osc_set_filt(); \
+ FRCOSCCONFIG = frcosccfg; \
+ LPOSCCONFIG = lposccfg; \
+ } \
+ } \
+} while (0)
+
+#endif /* LIBMFOSC_H */
diff --git a/libs/libmf/include/libmfradio.h b/libs/libmf/include/libmfradio.h
new file mode 100644
index 00000000..e41b9e6c
--- /dev/null
+++ b/libs/libmf/include/libmfradio.h
@@ -0,0 +1,62 @@
+#ifndef LIBMFRADIO_H
+#define LIBMFRADIO_H
+
+#include "libmftypes.h"
+
+#if defined(SDCC)
+#pragma callee_saves radio_read16,radio_read24,radio_read32,radio_write16,radio_write24,radio_write32
+#endif
+extern __reentrantb uint16_t radio_read16(uint16_t addr) __reentrant;
+extern __reentrantb uint32_t radio_read24(uint16_t addr) __reentrant;
+extern __reentrantb uint32_t radio_read32(uint16_t addr) __reentrant;
+extern __reentrantb void radio_write16(uint16_t addr, uint16_t d) __reentrant;
+extern __reentrantb void radio_write24(uint16_t addr, uint32_t d) __reentrant;
+extern __reentrantb void radio_write32(uint16_t addr, uint32_t d) __reentrant;
+
+/*
+ * AX5031
+ */
+extern __reentrantb void ax5031_comminit(void) __reentrant;
+extern __reentrantb void ax5031_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5031_reset(void) __reentrant;
+extern __reentrantb void ax5031_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5031_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5031_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5031_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5042
+ */
+extern __reentrantb void ax5042_comminit(void) __reentrant;
+extern __reentrantb void ax5042_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5042_reset(void) __reentrant;
+extern __reentrantb void ax5042_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5042_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5042_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5042_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5043
+ */
+extern __reentrantb void ax5043_comminit(void) __reentrant;
+extern __reentrantb void ax5043_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5043_reset(void) __reentrant;
+extern __reentrantb void ax5043_enter_deepsleep(void) __reentrant;
+extern __reentrantb uint8_t ax5043_wakeup_deepsleep(void) __reentrant;
+extern __reentrantb void ax5043_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5043_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5043_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5043_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5051
+ */
+extern __reentrantb void ax5051_comminit(void) __reentrant;
+extern __reentrantb void ax5051_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5051_reset(void) __reentrant;
+extern __reentrantb void ax5051_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5051_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5051_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5051_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+#endif /* LIBMFRADIO_H */
diff --git a/libs/libmf/include/libmftypes.h b/libs/libmf/include/libmftypes.h
new file mode 100644
index 00000000..c9df7225
--- /dev/null
+++ b/libs/libmf/include/libmftypes.h
@@ -0,0 +1,235 @@
+#ifndef LIBMFTYPES_H
+#define LIBMFTYPES_H
+
+#define LIBMFVERSION 20160321L
+
+/*
+ * Address Space Tags
+ */
+
+#if defined SDCC
+#define __autodata __data
+#define __auto __data
+#define __generic
+#define __reentrantb
+#define __interruptb(x)
+#endif
+
+#if defined __CX51__ || defined __C51__
+#include
+
+#define __autodata
+#define __auto data
+#define __code code
+#define __data data
+#define __xdata xdata
+#define __pdata pdata
+#define __generic
+#define __reentrantb
+#define __reentrant small reentrant
+#define __naked
+#define __interruptb(x)
+#define __interrupt(x) interrupt x
+#endif
+
+#if defined __ICC8051__
+#include
+#pragma language=extended
+
+#define __autodata
+#if !defined(__CALLING_CONVENTION__) || __CALLING_CONVENTION__ < 3
+#define __auto __data
+#elif __CALLING_CONVENTION__ == 3
+#define __auto __pdata
+#else
+#define __auto __xdata
+#endif
+#if !defined(__CALLING_CONVENTION__) || __CALLING_CONVENTION__ < 2
+#define __reentrantb __idata_reentrant
+#else
+#define __reentrantb
+#endif
+#define __reentrant
+#define __naked
+#define __interrupt_0 _Pragma("vector=0x03")
+#define __interrupt_1 _Pragma("vector=0x0B")
+#define __interrupt_2 _Pragma("vector=0x13")
+#define __interrupt_3 _Pragma("vector=0x1B")
+#define __interrupt_4 _Pragma("vector=0x23")
+#define __interrupt_5 _Pragma("vector=0x2B")
+#define __interrupt_6 _Pragma("vector=0x33")
+#define __interrupt_7 _Pragma("vector=0x3B")
+#define __interrupt_8 _Pragma("vector=0x43")
+#define __interrupt_9 _Pragma("vector=0x4B")
+#define __interrupt_10 _Pragma("vector=0x53")
+#define __interrupt_11 _Pragma("vector=0x5B")
+#define __interrupt_12 _Pragma("vector=0x63")
+#define __interrupt_13 _Pragma("vector=0x6B")
+#define __interrupt_14 _Pragma("vector=0x73")
+#define __interrupt_15 _Pragma("vector=0x7B")
+#define __interrupt_16 _Pragma("vector=0x83")
+#define __interrupt_17 _Pragma("vector=0x8B")
+#define __interrupt_18 _Pragma("vector=0x93")
+#define __interrupt_19 _Pragma("vector=0x9B")
+#define __interrupt_20 _Pragma("vector=0xA3")
+#define __interrupt_21 _Pragma("vector=0xAB")
+#define __interrupt_INT_EXTERNAL0 __interrupt_0
+#define __interrupt_INT_WAKEUPTIMER __interrupt_1
+#define __interrupt_INT_EXTERNAL1 __interrupt_2
+#define __interrupt_INT_GPIO __interrupt_3
+#define __interrupt_INT_RADIO __interrupt_4
+#define __interrupt_INT_CLOCKMGMT __interrupt_5
+#define __interrupt_INT_POWERMGMT __interrupt_6
+#define __interrupt_INT_TIMER0 __interrupt_7
+#define __interrupt_INT_TIMER1 __interrupt_8
+#define __interrupt_INT_TIMER2 __interrupt_9
+#define __interrupt_INT_SPI0 __interrupt_10
+#define __interrupt_INT_UART0 __interrupt_11
+#define __interrupt_INT_UART1 __interrupt_12
+#define __interrupt_INT_GPADC __interrupt_13
+#define __interrupt_INT_DMA __interrupt_14
+#define __interrupt_INT_OUTPUTCOMP0 __interrupt_15
+#define __interrupt_INT_OUTPUTCOMP1 __interrupt_16
+#define __interrupt_INT_INPUTCAPT0 __interrupt_17
+#define __interrupt_INT_INPUTCAPT1 __interrupt_18
+#define __interrupt_INT_DEBUGLINK __interrupt_21
+#define __interruptb(x) __interrupt_##x __interrupt
+#define __interrupt(x)
+#endif
+
+/*
+ * C99 size types
+ */
+
+typedef signed char int8_t; /**< \brief C99 signed 8bit type */
+typedef signed int int16_t; /**< \brief C99 signed 16bit type */
+typedef signed long int32_t; /**< \brief C99 signed 32bit type */
+typedef unsigned char uint8_t; /**< \brief C99 unsigned 8bit type */
+typedef unsigned int uint16_t; /**< \brief C99 unsigned 16bit type */
+typedef unsigned long uint32_t; /**< \brief C99 unsigned 32bit type */
+
+/*
+ * Delay
+ */
+extern __reentrantb void delay(uint16_t us) __reentrant __naked;
+
+/*
+ * Random Number Generator
+ */
+extern uint16_t __data random_seed;
+extern uint16_t random(void);
+
+/*
+ * Hamming Weight - also sometimes called population count
+ */
+#if defined SDCC
+#pragma callee_saves hweight8,hweight16,hweight32
+#pragma callee_saves signextend12,signextend16,signextend20,signextend24
+extern __reentrantb int32_t signextend12(int16_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend16(int16_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend20(int32_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend24(int32_t x) __reentrant __naked;
+#else
+extern __reentrantb int32_t signextend12(int16_t x) __reentrant;
+extern __reentrantb int32_t signextend16(int16_t x) __reentrant;
+extern __reentrantb int32_t signextend20(int32_t x) __reentrant;
+extern __reentrantb int32_t signextend24(int32_t x) __reentrant;
+#endif
+extern __reentrantb uint8_t hweight8(uint8_t x) __reentrant;
+extern __reentrantb uint8_t hweight16(uint16_t x) __reentrant;
+extern __reentrantb uint8_t hweight32(uint32_t x) __reentrant;
+#define parity8(x) (hweight8(x) & 1)
+#define parity16(x) (hweight16(x) & 1)
+#define parity32(x) (hweight32(x) & 1)
+#if defined SDCC
+#pragma callee_saves signedlimit16,checksignedlimit16,signedlimit32,checksignedlimit32
+#pragma callee_saves gray_encode8,gray_decode8
+extern __reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant __naked;
+extern __reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant __naked;
+extern __reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant __naked;
+extern __reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant __naked;
+extern __reentrantb uint8_t gray_encode8(uint8_t x) __reentrant __naked;
+extern __reentrantb uint8_t gray_decode8(uint8_t x) __reentrant __naked;
+#else
+extern __reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant;
+extern __reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant;
+extern __reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant;
+extern __reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant;
+extern __reentrantb uint8_t gray_encode8(uint8_t x) __reentrant;
+extern __reentrantb uint8_t gray_decode8(uint8_t x) __reentrant;
+#endif
+
+/*
+ * Reverse Bits
+ */
+extern __reentrantb uint8_t rev8(uint8_t x) __reentrant;
+
+/*
+ * fast memset and memcpy
+ */
+
+#if defined __ICC8051__
+__idata_reentrant void fmemset(void __generic *p, char c, uint16_t n);
+__idata_reentrant void fmemcpy(void __generic *d, const void __generic *s, uint16_t n);
+#else
+__reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant;
+__reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant;
+#endif
+
+/*
+ * Power Management
+ */
+
+#if defined SDCC
+#define nop() do { __asm nop __endasm; } while (0)
+#elif defined __CX51__ || defined __C51__
+#define nop() do { _nop_(); } while (0)
+#elif defined __ICC8051__
+#define nop() do { __no_operation(); } while (0)
+#endif
+
+#if defined SDCC
+#pragma callee_saves wtimer_standby,enter_standby,enter_sleep,enter_deepsleep
+#endif
+extern __reentrantb void wtimer_standby(void) __reentrant;
+extern __reentrantb void enter_standby(void) __reentrant;
+extern __reentrantb void enter_sleep(void) __reentrant;
+#if defined(SDCC) || defined(__ICC8051__)
+extern __reentrantb void enter_sleep_cont(void) __reentrant;
+#endif
+extern __reentrantb void enter_deepsleep(void) __reentrant;
+extern __reentrantb void reset_cpu(void) __reentrant;
+extern __reentrantb void turn_off_xosc(void) __reentrant;
+extern __reentrantb void turn_off_lpxosc(void) __reentrant;
+
+/*
+ * Clock Sources
+ */
+#define CLKSRC_FRCOSC 0
+#define CLKSRC_LPOSC 1
+#define CLKSRC_XOSC 2
+#define CLKSRC_LPXOSC 3
+#define CLKSRC_RSYSCLK 4
+#define CLKSRC_TCLK 5
+#define CLKSRC_SYSCLK 6
+#define CLKSRC_OFF 7
+
+/*
+ * wrnum Flags
+ */
+#define WRNUM_SIGNED 0x01
+#define WRNUM_PLUS 0x02
+#define WRNUM_ZEROPLUS 0x04
+#define WRNUM_PADZERO 0x08
+#define WRNUM_TSDSEP 0x10
+#define WRNUM_LCHEX 0x20
+
+/*
+ * IAR Stacks
+ */
+#if defined __ICC8051__
+extern __reentrantb void __pdata *getpsp(void) __reentrant;
+extern __reentrantb void __xdata *getxsp(void) __reentrant;
+#endif
+
+#endif /* LIBMFTYPES_H */
diff --git a/libs/libmf/include/libmfuart.h b/libs/libmf/include/libmfuart.h
new file mode 100644
index 00000000..686a19ad
--- /dev/null
+++ b/libs/libmf/include/libmfuart.h
@@ -0,0 +1,13 @@
+#ifndef LIBMFUART_H
+#define LIBMFUART_H
+
+#include "libmftypes.h"
+
+/*
+ * UART
+ */
+extern __reentrantb void uart_timer0_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+extern __reentrantb void uart_timer1_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+extern __reentrantb void uart_timer2_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+
+#endif /* LIBMFUART_H */
diff --git a/libs/libmf/include/libmfuart0.h b/libs/libmf/include/libmfuart0.h
new file mode 100644
index 00000000..2012d656
--- /dev/null
+++ b/libs/libmf/include/libmfuart0.h
@@ -0,0 +1,142 @@
+#ifndef LIBMFUART0_H
+#define LIBMFUART0_H
+
+#include "libmftypes.h"
+
+/*
+ * UART 0
+ */
+#if defined SDCC
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+static void uart0_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart0_rxbuffer \
+_uart0_rxbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART0S0 (CODE) \
+ .area UART0S1 (CODE) \
+ .area UART0S2 (CODE) \
+ .area UART0S3 (CODE) \
+ .area UART0S4 (CODE) \
+ .area UART0S5 (CODE) \
+ \
+ .area UART0S2 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART0S5 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+static void uart0_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart0_txbuffer \
+_uart0_txbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART0S0 (CODE) \
+ .area UART0S1 (CODE) \
+ .area UART0S2 (CODE) \
+ .area UART0S3 (CODE) \
+ .area UART0S4 (CODE) \
+ .area UART0S5 (CODE) \
+ \
+ .area UART0S1 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART0S4 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart0_rxbuffer[sz]; \
+const uint8_t __code uart0_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart0_txbuffer[sz]; \
+const uint8_t __code uart0_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart0_rxbuffer[sz]; \
+const uint8_t __code uart0_rxbuffer_size[] = { sz };
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart0_txbuffer[sz]; \
+const uint8_t __code uart0_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves uart0_txbufptr,uart0_txfreelinear,uart0_rxbufptr,uart0_rxcountlinear
+#pragma callee_saves uart0_txfree,uart0_rxcount,uart0_wait_txfree,uart0_wait_rxcount
+#pragma callee_saves uart0_txbuffersize,uart0_rxbuffersize,uart0_rxpeek,uart0_txpoke,uart0_txpokehex
+#pragma callee_saves uart0_init,uart0_poll,uart0_wait_txfree,uart0_wait_rxcount,uart0_rx,uart0_tx
+extern __reentrantb void uart0_irq(void) __interrupt(11) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t uart0_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *uart0_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *uart0_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart0_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart0_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart0_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart0_txadvance(uint8_t idx) __reentrant __naked;
+
+extern void uart0_init(uint8_t timernr, uint8_t wl, uint8_t stop);
+extern void uart0_stop(void);
+extern __reentrantb void uart0_wait_txdone(void) __reentrant;
+extern __reentrantb void uart0_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void uart0_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t uart0_rx(void) __reentrant;
+extern __reentrantb void uart0_tx(uint8_t v) __reentrant;
+extern __reentrantb void uart0_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t uart0_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart0_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t uart0_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart0_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t uart0_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t uart0_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void uart0_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart0_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void uart0_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart0_writeu32(uint32_t val, uint8_t nrdig);
+
+
+#endif /* LIBMFUART0_H */
diff --git a/libs/libmf/include/libmfuart1.h b/libs/libmf/include/libmfuart1.h
new file mode 100644
index 00000000..4a1a4d13
--- /dev/null
+++ b/libs/libmf/include/libmfuart1.h
@@ -0,0 +1,142 @@
+#ifndef LIBMFUART1_H
+#define LIBMFUART1_H
+
+#include "libmftypes.h"
+
+/*
+ * UART 1
+ */
+#if defined SDCC
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+static void uart1_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart1_rxbuffer \
+_uart1_rxbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART1S0 (CODE) \
+ .area UART1S1 (CODE) \
+ .area UART1S2 (CODE) \
+ .area UART1S3 (CODE) \
+ .area UART1S4 (CODE) \
+ .area UART1S5 (CODE) \
+ \
+ .area UART1S2 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART1S5 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+static void uart1_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart1_txbuffer \
+_uart1_txbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART1S0 (CODE) \
+ .area UART1S1 (CODE) \
+ .area UART1S2 (CODE) \
+ .area UART1S3 (CODE) \
+ .area UART1S4 (CODE) \
+ .area UART1S5 (CODE) \
+ \
+ .area UART1S1 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART1S4 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart1_rxbuffer[sz]; \
+const uint8_t __code uart1_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart1_txbuffer[sz]; \
+const uint8_t __code uart1_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart1_rxbuffer[sz]; \
+const uint8_t __code uart1_rxbuffer_size[] = { sz };
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart1_txbuffer[sz]; \
+const uint8_t __code uart1_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves uart1_txbufptr,uart1_txfreelinear,uart1_rxbufptr,uart1_rxcountlinear
+#pragma callee_saves uart1_txfree,uart1_rxcount,uart1_wait_txfree,uart1_wait_rxcount
+#pragma callee_saves uart1_txbuffersize,uart1_rxbuffersize,uart1_rxpeek,uart1_txpoke,uart1_txpokehex
+#pragma callee_saves uart1_init,uart1_poll,uart1_wait_txfree,uart1_wait_rxcount,uart1_rx,uart1_tx
+extern __reentrantb void uart1_irq(void) __interrupt(12) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t uart1_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *uart1_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *uart1_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart1_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart1_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart1_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart1_txadvance(uint8_t idx) __reentrant __naked;
+
+extern void uart1_init(uint8_t timernr, uint8_t wl, uint8_t stop);
+extern void uart1_stop(void);
+extern __reentrantb void uart1_wait_txdone(void) __reentrant;
+extern __reentrantb void uart1_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void uart1_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t uart1_rx(void) __reentrant;
+extern __reentrantb void uart1_tx(uint8_t v) __reentrant;
+extern __reentrantb void uart1_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t uart1_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart1_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t uart1_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart1_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t uart1_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t uart1_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void uart1_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart1_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void uart1_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart1_writeu32(uint32_t val, uint8_t nrdig);
+
+
+#endif /* LIBMFUART1_H */
diff --git a/libs/libmf/include/libmfwtimer.h b/libs/libmf/include/libmfwtimer.h
new file mode 100644
index 00000000..e35194bc
--- /dev/null
+++ b/libs/libmf/include/libmfwtimer.h
@@ -0,0 +1,87 @@
+#ifndef LIBMFWTIMER_H
+#define LIBMFWTIMER_H
+
+#include "libmftypes.h"
+
+struct wtimer_callback;
+struct wtimer_desc;
+
+#if defined(__ICC8051__)
+typedef void (*wtimer_callback_handler_t)(struct wtimer_callback __xdata *desc);
+typedef void (*wtimer_desc_handler_t)(struct wtimer_desc __xdata *desc);
+#else
+typedef __reentrantb void (*wtimer_callback_handler_t)(struct wtimer_callback __xdata *desc) __reentrant;
+typedef __reentrantb void (*wtimer_desc_handler_t)(struct wtimer_desc __xdata *desc) __reentrant;
+#endif
+
+struct wtimer_callback {
+ // do not change the order
+ // must be compatible with wtimer_desc
+ struct wtimer_callback __xdata *next;
+ wtimer_callback_handler_t handler;
+};
+
+struct wtimer_desc {
+ // do not change the order
+ struct wtimer_desc __xdata *next;
+ wtimer_desc_handler_t handler;
+ uint32_t time;
+};
+
+#define WTFLAG_CANSLEEP 0x01
+#define WTFLAG_CANSTANDBY 0x02
+#define WTFLAG_CANSLEEPCONT 0x04
+
+#define WTIDLE_WORK 0x01
+#define WTIDLE_SLEEP 0x02
+
+extern __reentrantb void wtimer0_setconfig(uint8_t cfg) __reentrant;
+extern __reentrantb void wtimer1_setconfig(uint8_t cfg) __reentrant;
+
+#define wtimer0_setclksrc(clksrc, prescaler) \
+do { \
+ uint8_t c = clksrc, p = prescaler; \
+ wtimer0_setconfig((c & 0x07) | ((p & 0x07) << 3)); \
+} while (0)
+
+#define wtimer1_setclksrc(clksrc, prescaler) \
+do { \
+ uint8_t c = clksrc, p = prescaler; \
+ wtimer1_setconfig((c & 0x07) | ((p & 0x07) << 3)); \
+} while (0)
+
+extern __reentrantb void wtimer_init(void) __reentrant;
+extern __reentrantb void wtimer_init_deepsleep(void) __reentrant;
+extern __reentrantb uint8_t wtimer_idle(uint8_t flags) __reentrant;
+#if defined(__ICC8051__)
+extern uint8_t wtimer_runcallbacks(void);
+#else
+// note: wtimer_runcallbacks is only reentrant if the handlers
+// it might call are reentrant too
+extern __reentrantb uint8_t wtimer_runcallbacks(void) __reentrant;
+#endif
+
+extern __reentrantb uint32_t wtimer0_curtime(void) __reentrant;
+extern __reentrantb uint32_t wtimer1_curtime(void) __reentrant;
+extern __reentrantb void wtimer0_addabsolute(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer1_addabsolute(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer0_addrelative(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer1_addrelative(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer_remove(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer0_remove(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer1_remove(struct wtimer_desc __xdata *desc) __reentrant;
+
+extern __reentrantb void wtimer_add_callback(struct wtimer_callback __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer_remove_callback(struct wtimer_callback __xdata *desc) __reentrant;
+
+extern __reentrantb uint8_t wtimer_cansleep(void) __reentrant;
+
+#if defined SDCC
+extern void wtimer_irq(void) __interrupt(1);
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+#endif /* LIBMFWTIMER_H */
diff --git a/libs/libmf/keil/libmf.lib b/libs/libmf/keil/libmf.lib
new file mode 100644
index 00000000..213c0d9d
Binary files /dev/null and b/libs/libmf/keil/libmf.lib differ
diff --git a/libs/libmf/keil/libmflarge.lib b/libs/libmf/keil/libmflarge.lib
new file mode 100644
index 00000000..9edf479c
Binary files /dev/null and b/libs/libmf/keil/libmflarge.lib differ
diff --git a/libs/libmf/keil2/libmf.lib b/libs/libmf/keil2/libmf.lib
new file mode 100644
index 00000000..7e1b8ec7
Binary files /dev/null and b/libs/libmf/keil2/libmf.lib differ
diff --git a/libs/libmf/keil2/libmflarge.lib b/libs/libmf/keil2/libmflarge.lib
new file mode 100644
index 00000000..b2c7e55f
Binary files /dev/null and b/libs/libmf/keil2/libmflarge.lib differ
diff --git a/libs/libmf/sdcc/libmf.lib b/libs/libmf/sdcc/libmf.lib
new file mode 100644
index 00000000..a4168287
--- /dev/null
+++ b/libs/libmf/sdcc/libmf.lib
@@ -0,0 +1,307475 @@
+
+
+
+ 1574040
+
+lcdinit 9
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
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+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
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+G$U1MODE$0$0
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+_FRCOSCFREQ1
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$lcdinit$1519
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+A$lcdinit$1456
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+A$lcdinit$1258
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+A$lcdinit$1529
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+A$lcdinit$1494
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+C$lcdinit.c$24$1$52
+C$lcdinit.c$51$1$62
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+C$lcdinit.c$45$1$60
+C$lcdinit.c$30$2$56
+C$lcdinit.c$60$1$64
+C$lcdinit.c$53$1$62
+C$lcdinit.c$46$1$60
+C$lcdinit.c$33$1$55
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+C$lcdinit.c$11$2$49
+C$lcdinit.c$61$1$64
+C$lcdinit.c$47$1$60
+C$lcdinit.c$40$1$58
+C$lcdinit.c$34$1$55
+C$lcdinit.c$19$1$52
+C$lcdinit.c$14$1$48
+C$lcdinit.c$12$2$49
+C$lcdinit.c$62$1$64
+C$lcdinit.c$55$1$62
+C$lcdinit.c$41$1$58
+C$lcdinit.c$35$1$55
+C$lcdinit.c$26$1$55
+C$lcdinit.c$63$1$64
+C$lcdinit.c$49$1$60
+C$lcdinit.c$27$1$55
+C$lcdinit.c$16$1$48
+C$lcdinit.c$80$1$66
+C$lcdinit.c$64$1$64
+C$lcdinit.c$43$1$58
+C$lcdinit.c$37$1$55
+G$lcd_write$0$0
+_lcd_writecmd
+C$lcdinit.c$90$1$66
+C$lcdinit.c$81$1$66
+C$lcdinit.c$72$1$66
+C$lcdinit.c$65$1$64
+C$lcdinit.c$18$1$48
+C$lcdinit.c$82$1$66
+C$lcdinit.c$73$1$66
+C$lcdinit.c$66$1$64
+C$lcdinit.c$29$2$55
+C$lcdinit.c$92$1$66
+C$lcdinit.c$74$1$66
+C$lcdinit.c$67$1$64
+C$lcdinit.c$58$1$64
+C$lcdinit.c$93$1$66
+C$lcdinit.c$84$1$66
+C$lcdinit.c$75$1$66
+C$lcdinit.c$59$1$64
+C$lcdinit.c$76$1$66
+C$lcdinit.c$69$1$64
+C$lcdinit.c$39$1$58
+C$lcdinit.c$95$1$66
+C$lcdinit.c$86$1$66
+C$lcdinit.c$77$1$66
+_lcd_waitshort
+_lcd_waitlong
+C$lcdinit.c$96$1$66
+C$lcdinit.c$87$1$66
+C$lcdinit.c$78$1$66
+C$lcdinit.c$79$1$66
+C$lcdinit.c$98$1$66
+C$lcdinit.c$89$1$66
+G$lcd_init$0$0
+C$lcdinit.c$99$1$66
+XG$lcd_writecmd$0$0
+_lcd_write
+G$lcd_portinit$0$0
+C$lcdinit.c$7$1$48
+C$lcdinit.c$4$0$0
+C$lcdinit.c$8$2$48
+XG$lcd_waitshort$0$0
+XG$lcd_waitlong$0$0
+C$lcdinit.c$6$1$0
+C$lcdinit.c$9$2$49
+G$lcd_portoff$0$0
+_lcd_init
+XG$lcd_write$0$0
+G$lcd_writedata$0$0
+_lcd_portinit
+XG$lcd_init$0$0
+_lcd_portoff
+A$lcdinit$1201
+A$lcdinit$1301
+A$lcdinit$1220
+A$lcdinit$1211
+A$lcdinit$1401
+A$lcdinit$1221
+A$lcdinit$1212
+XG$lcd_portinit$0$0
+_lcd_writedata
+A$lcdinit$1501
+A$lcdinit$1222
+A$lcdinit$1213
+A$lcdinit$1511
+A$lcdinit$1340
+A$lcdinit$1322
+A$lcdinit$1241
+A$lcdinit$1223
+A$lcdinit$1512
+A$lcdinit$1440
+A$lcdinit$1431
+A$lcdinit$1422
+A$lcdinit$1404
+A$lcdinit$1251
+A$lcdinit$1242
+A$lcdinit$1224
+A$lcdinit$1522
+A$lcdinit$1504
+A$lcdinit$1252
+A$lcdinit$1225
+A$lcdinit$1216
+A$lcdinit$1207
+C$lcdinit.c$110$1$66
+C$lcdinit.c$101$1$66
+A$lcdinit$1532
+A$lcdinit$1505
+A$lcdinit$1343
+A$lcdinit$1316
+A$lcdinit$1280
+A$lcdinit$1262
+A$lcdinit$1217
+A$lcdinit$1208
+A$lcdinit$1190
+C$lcdinit.c$111$1$66
+C$lcdinit.c$102$1$66
+A$lcdinit$1515
+A$lcdinit$1470
+A$lcdinit$1452
+A$lcdinit$1443
+A$lcdinit$1434
+A$lcdinit$1425
+A$lcdinit$1380
+A$lcdinit$1362
+A$lcdinit$1290
+A$lcdinit$1245
+A$lcdinit$1191
+C$lcdinit.c$121$1$66
+A$lcdinit$1525
+A$lcdinit$1480
+A$lcdinit$1462
+A$lcdinit$1291
+A$lcdinit$1255
+A$lcdinit$1228
+A$lcdinit$1192
+C$lcdinit.c$113$1$66
+C$lcdinit.c$104$1$66
+XG$lcd_portoff$0$0
+A$lcdinit$1526
+A$lcdinit$1508
+A$lcdinit$1490
+A$lcdinit$1463
+A$lcdinit$1337
+A$lcdinit$1319
+A$lcdinit$1283
+A$lcdinit$1256
+C$lcdinit.c$114$1$66
+C$lcdinit.c$105$1$66
+A$lcdinit$1518
+A$lcdinit$1491
+A$lcdinit$1473
+A$lcdinit$1455
+A$lcdinit$1446
+A$lcdinit$1437
+A$lcdinit$1428
+A$lcdinit$1419
+A$lcdinit$1392
+A$lcdinit$1383
+A$lcdinit$1356
+A$lcdinit$1257
+
+
+
+lcdsetpos 38967
+.__.ABS.
+G$lcd_setpos$0$0
+C$lcdsetpos.c$5$1$48
+C$lcdsetpos.c$6$1$48
+C$lcdsetpos.c$3$0$0
+_lcd_setpos
+XG$lcd_setpos$0$0
+A$lcdsetpos$111
+A$lcdsetpos$112
+A$lcdsetpos$122
+A$lcdsetpos$115
+A$lcdsetpos$116
+A$lcdsetpos$117
+A$lcdsetpos$118
+A$lcdsetpos$119
+
+
+
+lcdwrstr 42469
+.__.ABS.
+XG$lcd_writestr$0$0
+A$lcdwrstr$120
+A$lcdwrstr$130
+A$lcdwrstr$121
+C$lcdwrstr.c$10$3$50
+A$lcdwrstr$131
+A$lcdwrstr$122
+A$lcdwrstr$123
+A$lcdwrstr$114
+A$lcdwrstr$124
+A$lcdwrstr$115
+C$lcdwrstr.c$12$3$51
+A$lcdwrstr$143
+A$lcdwrstr$134
+A$lcdwrstr$125
+A$lcdwrstr$116
+A$lcdwrstr$153
+A$lcdwrstr$144
+A$lcdwrstr$126
+A$lcdwrstr$127
+A$lcdwrstr$137
+A$lcdwrstr$138
+A$lcdwrstr$148
+A$lcdwrstr$139
+A$lcdwrstr$149
+C$lcdwrstr.c$16$1$48
+C$lcdwrstr.c$14$2$49
+G$lcd_writestr$0$0
+C$lcdwrstr.c$3$0$0
+C$lcdwrstr.c$6$2$49
+C$lcdwrstr.c$7$2$49
+C$lcdwrstr.c$9$2$49
+_lcd_writestr
+
+
+
+lcdclear 46990
+.__.ABS.
+Llcdclear.lcd_clear$len$1$47
+_lcd_clear_PARM_2
+XG$lcd_clear$0$0
+A$lcdclear$121
+A$lcdclear$122
+A$lcdclear$150
+A$lcdclear$141
+A$lcdclear$160
+A$lcdclear$151
+A$lcdclear$133
+A$lcdclear$152
+A$lcdclear$125
+A$lcdclear$171
+A$lcdclear$153
+A$lcdclear$126
+C$lcdclear.c$10$1$48
+A$lcdclear$145
+A$lcdclear$136
+C$lcdclear.c$11$1$48
+A$lcdclear$164
+A$lcdclear$146
+C$lcdclear.c$12$1$48
+A$lcdclear$156
+A$lcdclear$147
+A$lcdclear$138
+A$lcdclear$129
+C$lcdclear.c$13$1$48
+A$lcdclear$175
+C$lcdclear.c$14$1$48
+A$lcdclear$167
+C$lcdclear.c$15$1$48
+A$lcdclear$168
+C$lcdclear.c$18$1$48
+C$lcdclear.c$16$2$49
+C$lcdclear.c$19$1$48
+C$lcdclear.c$17$2$49
+G$lcd_clear$0$0
+C$lcdclear.c$6$1$48
+C$lcdclear.c$3$0$0
+C$lcdclear.c$7$1$48
+C$lcdclear.c$8$1$48
+C$lcdclear.c$9$1$48
+_lcd_clear
+
+
+
+lcdclrdisp 52046
+.__.ABS.
+A$lcdclrdisp$111
+A$lcdclrdisp$112
+A$lcdclrdisp$115
+C$lcdclrdisp.c$5$1$48
+C$lcdclrdisp.c$6$1$48
+C$lcdclrdisp.c$3$0$0
+G$lcd_cleardisplay$0$0
+_lcd_cleardisplay
+XG$lcd_cleardisplay$0$0
+
+
+
+lcdwru16 55335
+.__.ABS.
+_lcd_writeu16_PARM_2
+_lcd_writeu16_PARM_3
+Llcdwru16.lcd_writeu16$pos$1$47
+Llcdwru16.lcd_writeu16$nrdig$1$47
+XG$lcd_writeu16$0$0
+A$lcdwru16$140
+A$lcdwru16$131
+A$lcdwru16$150
+A$lcdwru16$141
+A$lcdwru16$132
+A$lcdwru16$160
+A$lcdwru16$142
+A$lcdwru16$124
+A$lcdwru16$170
+A$lcdwru16$143
+A$lcdwru16$125
+A$lcdwru16$171
+A$lcdwru16$153
+A$lcdwru16$144
+A$lcdwru16$135
+A$lcdwru16$172
+A$lcdwru16$163
+A$lcdwru16$154
+A$lcdwru16$145
+A$lcdwru16$182
+A$lcdwru16$173
+A$lcdwru16$164
+A$lcdwru16$155
+A$lcdwru16$146
+A$lcdwru16$128
+C$lcdwru16.c$10$2$49
+A$lcdwru16$183
+A$lcdwru16$156
+A$lcdwru16$147
+A$lcdwru16$138
+A$lcdwru16$129
+C$lcdwru16.c$11$2$49
+A$lcdwru16$157
+A$lcdwru16$148
+A$lcdwru16$139
+C$lcdwru16.c$12$2$49
+A$lcdwru16$176
+A$lcdwru16$167
+A$lcdwru16$158
+A$lcdwru16$149
+C$lcdwru16.c$13$2$49
+A$lcdwru16$159
+C$lcdwru16.c$16$1$48
+C$lcdwru16.c$14$2$49
+A$lcdwru16$187
+A$lcdwru16$179
+G$lcd_writeu16$0$0
+C$lcdwru16.c$5$1$48
+C$lcdwru16.c$3$0$0
+C$lcdwru16.c$7$1$48
+C$lcdwru16.c$6$2$48
+C$lcdwru16.c$8$2$49
+C$lcdwru16.c$9$2$49
+_lcd_writeu16
+
+
+
+lcdwru32 61023
+.__.ABS.
+_lcd_writeu32_PARM_2
+_lcd_writeu32_PARM_3
+Llcdwru32.lcd_writeu32$pos$1$47
+Llcdwru32.lcd_writeu32$nrdig$1$47
+XG$lcd_writeu32$0$0
+A$lcdwru32$130
+A$lcdwru32$140
+A$lcdwru32$131
+A$lcdwru32$150
+A$lcdwru32$141
+A$lcdwru32$151
+A$lcdwru32$142
+A$lcdwru32$133
+A$lcdwru32$124
+A$lcdwru32$152
+A$lcdwru32$143
+A$lcdwru32$134
+A$lcdwru32$125
+A$lcdwru32$180
+A$lcdwru32$162
+A$lcdwru32$153
+A$lcdwru32$144
+A$lcdwru32$126
+A$lcdwru32$181
+A$lcdwru32$172
+A$lcdwru32$163
+A$lcdwru32$154
+A$lcdwru32$145
+A$lcdwru32$127
+A$lcdwru32$191
+A$lcdwru32$182
+A$lcdwru32$173
+A$lcdwru32$164
+A$lcdwru32$155
+A$lcdwru32$146
+A$lcdwru32$137
+C$lcdwru32.c$10$2$49
+A$lcdwru32$192
+A$lcdwru32$165
+A$lcdwru32$156
+A$lcdwru32$147
+C$lcdwru32.c$11$2$49
+A$lcdwru32$166
+A$lcdwru32$157
+A$lcdwru32$148
+C$lcdwru32.c$12$2$49
+A$lcdwru32$185
+A$lcdwru32$176
+A$lcdwru32$167
+A$lcdwru32$158
+A$lcdwru32$149
+C$lcdwru32.c$13$2$49
+A$lcdwru32$168
+A$lcdwru32$159
+C$lcdwru32.c$16$1$48
+C$lcdwru32.c$14$2$49
+A$lcdwru32$196
+A$lcdwru32$169
+A$lcdwru32$188
+A$lcdwru32$179
+G$lcd_writeu32$0$0
+C$lcdwru32.c$5$1$48
+C$lcdwru32.c$3$0$0
+C$lcdwru32.c$7$1$48
+C$lcdwru32.c$6$2$48
+C$lcdwru32.c$8$2$49
+C$lcdwru32.c$9$2$49
+_lcd_writeu32
+
+
+
+lcdwrhexu16 67118
+.__.ABS.
+_lcd_writehexu16_PARM_2
+_lcd_writehexu16_PARM_3
+Llcdwrhexu16.lcd_writehexu16$pos$1$47
+Llcdwrhexu16.lcd_writehexu16$nrdig$1$47
+XG$lcd_writehexu16$0$0
+A$lcdwrhexu16$140
+A$lcdwrhexu16$131
+A$lcdwrhexu16$141
+A$lcdwrhexu16$132
+A$lcdwrhexu16$160
+A$lcdwrhexu16$142
+A$lcdwrhexu16$124
+A$lcdwrhexu16$161
+A$lcdwrhexu16$152
+A$lcdwrhexu16$143
+A$lcdwrhexu16$125
+A$lcdwrhexu16$180
+A$lcdwrhexu16$171
+A$lcdwrhexu16$162
+A$lcdwrhexu16$144
+A$lcdwrhexu16$135
+A$lcdwrhexu16$163
+A$lcdwrhexu16$145
+A$lcdwrhexu16$191
+A$lcdwrhexu16$155
+A$lcdwrhexu16$146
+A$lcdwrhexu16$128
+C$lcdwrhexu16.c$10$2$49
+A$lcdwrhexu16$183
+A$lcdwrhexu16$174
+A$lcdwrhexu16$147
+A$lcdwrhexu16$138
+A$lcdwrhexu16$129
+C$lcdwrhexu16.c$11$2$49
+A$lcdwrhexu16$175
+A$lcdwrhexu16$157
+A$lcdwrhexu16$148
+A$lcdwrhexu16$139
+C$lcdwrhexu16.c$12$2$49
+A$lcdwrhexu16$176
+A$lcdwrhexu16$167
+A$lcdwrhexu16$149
+C$lcdwrhexu16.c$13$2$49
+A$lcdwrhexu16$186
+A$lcdwrhexu16$177
+A$lcdwrhexu16$168
+C$lcdwrhexu16.c$14$2$49
+A$lcdwrhexu16$187
+C$lcdwrhexu16.c$15$2$49
+C$lcdwrhexu16.c$18$1$48
+C$lcdwrhexu16.c$16$2$49
+G$lcd_writehexu16$0$0
+C$lcdwrhexu16.c$5$1$48
+C$lcdwrhexu16.c$3$0$0
+C$lcdwrhexu16.c$6$2$48
+C$lcdwrhexu16.c$7$2$49
+C$lcdwrhexu16.c$8$2$49
+C$lcdwrhexu16.c$9$2$49
+_lcd_writehexu16
+
+
+
+lcdwrhexu32 72921
+.__.ABS.
+_lcd_writehexu32_PARM_2
+_lcd_writehexu32_PARM_3
+Llcdwrhexu32.lcd_writehexu32$pos$1$47
+Llcdwrhexu32.lcd_writehexu32$nrdig$1$47
+XG$lcd_writehexu32$0$0
+A$lcdwrhexu32$210
+A$lcdwrhexu32$202
+A$lcdwrhexu32$130
+A$lcdwrhexu32$140
+A$lcdwrhexu32$131
+A$lcdwrhexu32$150
+A$lcdwrhexu32$141
+A$lcdwrhexu32$205
+A$lcdwrhexu32$160
+A$lcdwrhexu32$151
+A$lcdwrhexu32$142
+A$lcdwrhexu32$133
+A$lcdwrhexu32$124
+A$lcdwrhexu32$206
+A$lcdwrhexu32$161
+A$lcdwrhexu32$152
+A$lcdwrhexu32$143
+A$lcdwrhexu32$134
+A$lcdwrhexu32$125
+A$lcdwrhexu32$180
+A$lcdwrhexu32$171
+A$lcdwrhexu32$162
+A$lcdwrhexu32$153
+A$lcdwrhexu32$144
+A$lcdwrhexu32$126
+A$lcdwrhexu32$190
+A$lcdwrhexu32$181
+A$lcdwrhexu32$163
+A$lcdwrhexu32$154
+A$lcdwrhexu32$145
+A$lcdwrhexu32$127
+A$lcdwrhexu32$182
+A$lcdwrhexu32$164
+A$lcdwrhexu32$155
+A$lcdwrhexu32$146
+A$lcdwrhexu32$137
+C$lcdwrhexu32.c$10$2$49
+A$lcdwrhexu32$174
+A$lcdwrhexu32$165
+A$lcdwrhexu32$156
+A$lcdwrhexu32$147
+C$lcdwrhexu32.c$11$2$49
+A$lcdwrhexu32$193
+A$lcdwrhexu32$166
+A$lcdwrhexu32$157
+A$lcdwrhexu32$148
+C$lcdwrhexu32.c$12$2$49
+A$lcdwrhexu32$194
+A$lcdwrhexu32$176
+A$lcdwrhexu32$167
+A$lcdwrhexu32$158
+A$lcdwrhexu32$149
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+
+
+
+dbglnktxbuf 182379
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+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
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+_EIE_4
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+G$ANALOGA$0$0
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+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
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+_IP_0
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+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
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+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$F0$0$0
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+G$DMA1CONFIG$0$0
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+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+G$PINA_5$0$0
+G$WTCFGA$0$0
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+_PCON
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+_DIRR
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+G$ADCCONV$0$0
+_PALTA
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
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+_ADCTUNE2
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+_LPOSCCONFIG
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+_F1
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+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
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+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
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+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
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+_FRCOSCKFILT
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINC_1
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+G$ACC$0$0
+_PINCHGB
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+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
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+_PINB_3
+_PINC_2
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+_PINCHGC
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+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINB_4
+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
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+_PINB_5
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+_INTCHGA
+_SILICONREV
+_ADCCONV
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+_INTCHGB
+_NVADDR
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+_WDTCFG
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+_PINC_6
+.__.ABS.
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+G$WTEVTD0$0$0
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+G$IE$0$0
+_B
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+_WTCNTB0
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+G$DBGLNKBUF$0$0
+_WTCNTB1
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+_AC
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+G$WTCNTB$0$0
+_PORTA
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+_EA
+G$B_2$0$0
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+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
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+_T1PERIOD
+_T2CLKSRC
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+G$RS0$0$0
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+_OSCFORCERUN
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+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$RS1$0$0
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+_ADCCLKSRC
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+_PINSEL
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+G$ACC_2$0$0
+_RADIOFSTATADDR
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+_WTEVTB0
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+G$ADCCH2VAL1$0$0
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+G$T0CNT0$0$0
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+_DMA0ADDR0
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+G$E2IE_6$0$0
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+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
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+_IE
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+_E2IP
+_P
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+_DPL1
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+__XPAGE
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+_ADCCH0VAL0
+_GPIOENABLE
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+_IC1CAPT1
+_ACC_0
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+_E2IE_2
+_RS1
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+_ADCCH2VAL1
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+_ADCCH3VAL1
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+_RADIOFDATAADDR0
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+_RADIOSTAT0
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+_DPH
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+_CY
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+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+_DMA1ADDR
+_FRCOSCFREQ0
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+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_dbglink_txbuffer
+C$dbglnktxbuf.c$5$1$59
+C$dbglnktxbuf.c$5$0$0
+Fdbglnktxbuf$dbglink_define_txbuffer$0$0
+XFdbglnktxbuf$dbglink_define_txbuffer$0$0
+
+
+
+dbglnkrxbuf 214095
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$NVDATA0$0$0
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+_DIRC
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+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
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+_E2IP_4
+_EIE_1
+_IE_6
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+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
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+_EIE_2
+_IE_7
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+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
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+_OV
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+_ADCCH0VAL
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+_ADCCH1VAL
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+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
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+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_dbglink_rxbuffer
+C$dbglnkrxbuf.c$5$1$59
+C$dbglnkrxbuf.c$5$0$0
+Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0
+XFdbglnkrxbuf$dbglink_define_rxbuffer$0$0
+
+
+
+dbglnktx 245811
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$dbglnktx.c$50$1$62
+C$dbglnktx.c$33$2$60
+C$dbglnktx.c$52$1$62
+C$dbglnktx.c$42$2$63
+C$dbglnktx.c$43$2$63
+C$dbglnktx.c$28$2$60
+C$dbglnktx.c$29$2$60
+_dbglink_tx
+C$dbglnktx.c$45$2$63
+C$dbglnktx.c$54$1$65
+C$dbglnktx.c$46$2$63
+XG$dbglink_wait_txfree$0$0
+C$dbglnktx.c$55$1$65
+C$dbglnktx.c$47$2$63
+C$dbglnktx.c$49$1$62
+C$dbglnktx.c$24$0$0
+C$dbglnktx.c$56$1$65
+C$dbglnktx.c$35$1$59
+C$dbglnktx.c$26$1$59
+C$dbglnktx.c$57$1$65
+C$dbglnktx.c$36$1$59
+XG$dbglink_wait_txdone$0$0
+C$dbglnktx.c$38$1$59
+XG$dbglink_tx$0$0
+A$dbglnktx$1300
+A$dbglnktx$1201
+A$dbglnktx$1310
+A$dbglnktx$1230
+A$dbglnktx$1221
+A$dbglnktx$1212
+A$dbglnktx$1303
+A$dbglnktx$1231
+A$dbglnktx$1222
+A$dbglnktx$1213
+A$dbglnktx$1204
+A$dbglnktx$1313
+A$dbglnktx$1304
+A$dbglnktx$1223
+A$dbglnktx$1214
+A$dbglnktx$1205
+G$dbglink_wait_txfree$0$0
+A$dbglnktx$1314
+A$dbglnktx$1251
+A$dbglnktx$1206
+A$dbglnktx$1315
+A$dbglnktx$1252
+A$dbglnktx$1234
+A$dbglnktx$1207
+A$dbglnktx$1307
+A$dbglnktx$1262
+A$dbglnktx$1253
+A$dbglnktx$1217
+A$dbglnktx$1208
+A$dbglnktx$1190
+A$dbglnktx$1308
+A$dbglnktx$1272
+A$dbglnktx$1263
+A$dbglnktx$1227
+A$dbglnktx$1209
+G$dbglink_wait_txdone$0$0
+A$dbglnktx$1318
+A$dbglnktx$1309
+A$dbglnktx$1282
+A$dbglnktx$1264
+A$dbglnktx$1228
+A$dbglnktx$1283
+A$dbglnktx$1229
+A$dbglnktx$1193
+A$dbglnktx$1194
+A$dbglnktx$1276
+A$dbglnktx$1267
+A$dbglnktx$1195
+A$dbglnktx$1286
+A$dbglnktx$1277
+A$dbglnktx$1268
+A$dbglnktx$1259
+A$dbglnktx$1187
+A$dbglnktx$1278
+A$dbglnktx$1269
+A$dbglnktx$1188
+G$dbglink_tx$0$0
+A$dbglnktx$1189
+_dbglink_wait_txfree
+A$dbglnktx$1299
+C$dbglnktx.c$31$2$60
+C$dbglnktx.c$40$1$62
+C$dbglnktx.c$32$2$60
+_dbglink_wait_txdone
+
+
+
+dbglnkrx 280919
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
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+C$dbglnkrx.c$43$1$62
+_dbglink_wait_rxcount
+C$dbglnkrx.c$44$1$62
+C$dbglnkrx.c$45$1$62
+C$dbglnkrx.c$28$2$60
+C$dbglnkrx.c$29$2$60
+_dbglink_rx
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+C$dbglnkrx.c$26$1$59
+C$dbglnkrx.c$36$1$59
+C$dbglnkrx.c$38$1$59
+XG$dbglink_wait_rxcount$0$0
+XG$dbglink_rx$0$0
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+A$dbglnkrx$1204
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+A$dbglnkrx$1259
+A$dbglnkrx$1187
+A$dbglnkrx$1188
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+C$dbglnkrx.c$32$2$60
+C$dbglnkrx.c$41$1$62
+C$dbglnkrx.c$33$2$60
+C$dbglnkrx.c$42$1$62
+
+
+
+dbglnkwrhexu16 314691
+.__.ABS.
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+A$dbglnkwrhexu16$141
+A$dbglnkwrhexu16$132
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+A$dbglnkwrhexu16$129
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+A$dbglnkwrhexu16$158
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+A$dbglnkwrhexu16$159
+C$dbglnkwrhexu16.c$23$1$59
+C$dbglnkwrhexu16.c$21$1$0
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+_dbglink_writehexu16
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+XG$dbglink_writehexu16$0$0
+
+
+
+dbglnkwrhexu32 320750
+.__.ABS.
+_dbglink_writehexu32_PARM_2
+Ldbglnkwrhexu32.dbglink_writehexu32$nrdig$1$58
+A$dbglnkwrhexu32$120
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+A$dbglnkwrhexu32$163
+A$dbglnkwrhexu32$154
+A$dbglnkwrhexu32$145
+A$dbglnkwrhexu32$136
+C$dbglnkwrhexu32.c$25$2$60
+A$dbglnkwrhexu32$182
+A$dbglnkwrhexu32$173
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+
+
+crc8onewire 429391
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+_RADIODATA2
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+_RADIODATA3
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+_RADIOFSTATADDR1
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+_INTCHGA
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+_INTCHGB
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+_WDTCFG
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+.__.ABS.
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+_INTCHGC
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+G$IE$0$0
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+_EA
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+_ACC
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+G$B_3$0$0
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+G$_XPAGE$0$0
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+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
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+
+
+
+crc8onewiremsbb 509354
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
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+
+
+
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+
+
+
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+
+
+
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+
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+
+
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+
+
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+
+
+
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+
+
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+
+
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+
+
+
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+
+
+
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+
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+_OSCFORCERUN
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+G$OV$0$0
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+_fmemset
+C$fmemset.c$60$1$28
+C$fmemset.c$10$0$0
+C$fmemset.c$61$1$28
+XG$fmemset$0$0
+A$fmemset$1210
+A$fmemset$1201
+A$fmemset$1220
+A$fmemset$1211
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+
+
+
+fmemcpy 869804
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
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+_IC1STATUS
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+_PCON
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+_PALTA
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
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+_T1PERIOD0
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+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
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+_T1PERIOD1
+_T2PERIOD0
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+_PINB_1
+_PINC_0
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+_FRCOSCKFILT
+_PINCHGA
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+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINB_2
+_PINC_1
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+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
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+G$T1PERIOD$0$0
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+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$fmemcpy$1320
+A$fmemcpy$1302
+A$fmemcpy$1230
+A$fmemcpy$1221
+A$fmemcpy$1212
+A$fmemcpy$1330
+A$fmemcpy$1321
+A$fmemcpy$1312
+A$fmemcpy$1303
+A$fmemcpy$1240
+A$fmemcpy$1231
+A$fmemcpy$1222
+A$fmemcpy$1340
+A$fmemcpy$1322
+A$fmemcpy$1313
+A$fmemcpy$1304
+A$fmemcpy$1232
+A$fmemcpy$1223
+A$fmemcpy$1214
+A$fmemcpy$1205
+A$fmemcpy$1341
+A$fmemcpy$1332
+A$fmemcpy$1314
+A$fmemcpy$1305
+A$fmemcpy$1260
+A$fmemcpy$1251
+A$fmemcpy$1242
+A$fmemcpy$1224
+A$fmemcpy$1215
+A$fmemcpy$1206
+A$fmemcpy$1342
+A$fmemcpy$1333
+A$fmemcpy$1324
+A$fmemcpy$1306
+A$fmemcpy$1261
+A$fmemcpy$1252
+A$fmemcpy$1243
+A$fmemcpy$1234
+A$fmemcpy$1216
+A$fmemcpy$1207
+G$fmemcpy$0$0
+A$fmemcpy$1343
+A$fmemcpy$1334
+A$fmemcpy$1325
+A$fmemcpy$1316
+A$fmemcpy$1307
+A$fmemcpy$1280
+A$fmemcpy$1271
+A$fmemcpy$1253
+A$fmemcpy$1244
+A$fmemcpy$1235
+A$fmemcpy$1226
+A$fmemcpy$1208
+A$fmemcpy$1190
+A$fmemcpy$1344
+A$fmemcpy$1335
+A$fmemcpy$1326
+A$fmemcpy$1317
+A$fmemcpy$1308
+A$fmemcpy$1281
+A$fmemcpy$1272
+A$fmemcpy$1263
+A$fmemcpy$1245
+A$fmemcpy$1236
+A$fmemcpy$1227
+A$fmemcpy$1218
+A$fmemcpy$1209
+A$fmemcpy$1191
+A$fmemcpy$1345
+A$fmemcpy$1336
+A$fmemcpy$1327
+A$fmemcpy$1318
+A$fmemcpy$1309
+A$fmemcpy$1291
+A$fmemcpy$1282
+A$fmemcpy$1273
+A$fmemcpy$1264
+A$fmemcpy$1255
+A$fmemcpy$1246
+A$fmemcpy$1237
+A$fmemcpy$1228
+A$fmemcpy$1219
+A$fmemcpy$1192
+A$fmemcpy$1183
+A$fmemcpy$1346
+A$fmemcpy$1337
+A$fmemcpy$1328
+A$fmemcpy$1319
+A$fmemcpy$1292
+A$fmemcpy$1283
+A$fmemcpy$1274
+A$fmemcpy$1265
+A$fmemcpy$1256
+A$fmemcpy$1247
+A$fmemcpy$1238
+A$fmemcpy$1229
+A$fmemcpy$1193
+A$fmemcpy$1184
+A$fmemcpy$1347
+A$fmemcpy$1338
+A$fmemcpy$1329
+A$fmemcpy$1293
+A$fmemcpy$1284
+A$fmemcpy$1275
+A$fmemcpy$1266
+A$fmemcpy$1257
+A$fmemcpy$1248
+A$fmemcpy$1239
+A$fmemcpy$1194
+A$fmemcpy$1185
+A$fmemcpy$1294
+A$fmemcpy$1285
+A$fmemcpy$1276
+A$fmemcpy$1267
+A$fmemcpy$1258
+A$fmemcpy$1249
+A$fmemcpy$1195
+A$fmemcpy$1186
+A$fmemcpy$1295
+A$fmemcpy$1286
+A$fmemcpy$1268
+A$fmemcpy$1259
+A$fmemcpy$1196
+A$fmemcpy$1187
+A$fmemcpy$1296
+A$fmemcpy$1287
+A$fmemcpy$1278
+A$fmemcpy$1269
+A$fmemcpy$1197
+A$fmemcpy$1188
+A$fmemcpy$1288
+A$fmemcpy$1279
+A$fmemcpy$1198
+A$fmemcpy$1189
+C$fmemcpy.c$184$1$28
+A$fmemcpy$1298
+A$fmemcpy$1289
+C$fmemcpy.c$185$1$28
+A$fmemcpy$1299
+_fmemcpy
+C$fmemcpy.c$10$0$0
+XG$fmemcpy$0$0
+A$fmemcpy$1200
+A$fmemcpy$1300
+A$fmemcpy$1210
+A$fmemcpy$1310
+A$fmemcpy$1301
+A$fmemcpy$1220
+A$fmemcpy$1211
+A$fmemcpy$1202
+
+
+
+delay 905563
+.__.ABS.
+C$delay.c$9$0$0
+G$delay$0$0
+A$delay$110
+A$delay$112
+A$delay$114
+A$delay$105
+_delay
+A$delay$115
+A$delay$106
+A$delay$116
+A$delay$107
+A$delay$117
+A$delay$109
+C$delay.c$23$1$28
+C$delay.c$24$1$28
+XG$delay$0$0
+
+
+
+random 908346
+.__.ABS.
+G$random_seed$0$0
+_random_seed
+G$random$0$0
+A$random$120
+A$random$130
+A$random$121
+A$random$131
+A$random$122
+A$random$132
+A$random$123
+A$random$114
+_random
+A$random$133
+A$random$124
+A$random$115
+A$random$134
+A$random$125
+A$random$116
+A$random$126
+A$random$117
+A$random$127
+A$random$118
+A$random$137
+A$random$128
+A$random$119
+A$random$129
+C$random.c$11$0$0
+C$random.c$35$1$28
+C$random.c$36$1$28
+XG$random$0$0
+
+
+
+sleep 911638
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$enter_sleep$0$0
+G$enter_sleep$0$0
+A$sleep$1180
+A$sleep$1171
+A$sleep$1190
+A$sleep$1181
+A$sleep$1172
+A$sleep$1182
+A$sleep$1173
+A$sleep$1183
+A$sleep$1174
+A$sleep$1184
+A$sleep$1175
+A$sleep$1185
+A$sleep$1176
+A$sleep$1186
+A$sleep$1177
+A$sleep$1187
+A$sleep$1178
+A$sleep$1188
+A$sleep$1179
+A$sleep$1189
+_enter_sleep
+C$sleep.c$33$1$28
+C$sleep.c$10$0$0
+C$sleep.c$34$1$28
+
+
+
+deepsleep 942230
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$enter_deepsleep$0$0
+A$deepsleep$1180
+A$deepsleep$1171
+A$deepsleep$1181
+A$deepsleep$1172
+A$deepsleep$1182
+A$deepsleep$1173
+A$deepsleep$1183
+A$deepsleep$1174
+A$deepsleep$1184
+A$deepsleep$1175
+A$deepsleep$1185
+A$deepsleep$1176
+A$deepsleep$1177
+A$deepsleep$1178
+A$deepsleep$1179
+_enter_deepsleep
+C$deepsleep.c$10$0$0
+XG$enter_deepsleep$0$0
+C$deepsleep.c$28$1$28
+C$deepsleep.c$29$1$28
+
+
+
+sleepcont 972770
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$sleepcont$1220
+A$sleepcont$1230
+A$sleepcont$1221
+A$sleepcont$1231
+A$sleepcont$1222
+A$sleepcont$1232
+A$sleepcont$1223
+A$sleepcont$1233
+A$sleepcont$1224
+A$sleepcont$1225
+A$sleepcont$1226
+A$sleepcont$1228
+A$sleepcont$1219
+XFsleepcont$dummy$0$0
+A$sleepcont$1229
+C$sleepcont.c$72$1$30
+_enter_sleep_cont
+Fsleepcont$dummy$0$0
+XG$enter_sleep_cont$0$0
+A$sleepcont$1180
+A$sleepcont$1171
+A$sleepcont$1190
+A$sleepcont$1181
+A$sleepcont$1172
+A$sleepcont$1191
+A$sleepcont$1182
+A$sleepcont$1173
+A$sleepcont$1192
+A$sleepcont$1183
+A$sleepcont$1174
+A$sleepcont$1184
+A$sleepcont$1175
+A$sleepcont$1185
+A$sleepcont$1176
+A$sleepcont$1186
+A$sleepcont$1177
+A$sleepcont$1187
+A$sleepcont$1178
+A$sleepcont$1188
+A$sleepcont$1179
+A$sleepcont$1189
+C$sleepcont.c$71$1$30
+C$sleepcont.c$41$1$28
+C$sleepcont.c$13$0$0
+C$sleepcont.c$38$1$28
+C$sleepcont.c$39$1$28
+G$enter_sleep_cont$0$0
+
+
+
+standby 1004498
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
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+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$enter_standby$0$0
+A$standby$1180
+A$standby$1171
+A$standby$1181
+A$standby$1172
+A$standby$1173
+A$standby$1174
+A$standby$1175
+A$standby$1176
+A$standby$1177
+A$standby$1178
+A$standby$1179
+_enter_standby
+C$standby.c$24$1$28
+C$standby.c$10$0$0
+C$standby.c$25$1$28
+XG$enter_standby$0$0
+
+
+
+resetcpu 1034815
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
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+_IE_3
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+A$resetcpu$1192
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+A$resetcpu$1189
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+C$resetcpu.c$13$1$28
+C$resetcpu.c$14$1$28
+C$resetcpu.c$10$0$0
+C$resetcpu.c$17$1$28
+C$resetcpu.c$18$1$28
+G$reset_cpu$0$0
+_reset_cpu
+XG$reset_cpu$0$0
+A$resetcpu$1181
+
+
+
+flashunlock 1065122
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+G$EIP_0$0$0
+_MISCCTRL
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+_DIRB
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+_OV
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+_RADIODATA1
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+_U0CTRL
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+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINB_3
+_PINC_2
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+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINB_4
+_PINC_3
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+G$T2PERIOD$0$0
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+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
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+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+G$IE$0$0
+_B
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+_PORTA
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+_EA
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+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
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+_OSCFORCERUN
+_RADIODATA
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+G$CLKSTAT$0$0
+_ADCCLKSRC
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+G$ADCCH0VAL1$0$0
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+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
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+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
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+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
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+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$flash_unlock$0$0
+C$flashunlock.c$6$1$35
+C$flashunlock.c$7$1$35
+C$flashunlock.c$8$1$35
+C$flashunlock.c$9$1$35
+C$flashunlock.c$4$0$0
+_flash_unlock
+XG$flash_unlock$0$0
+A$flashunlock$1201
+A$flashunlock$1191
+A$flashunlock$1183
+A$flashunlock$1184
+A$flashunlock$1194
+A$flashunlock$1185
+A$flashunlock$1197
+A$flashunlock$1188
+A$flashunlock$1198
+C$flashunlock.c$10$1$35
+C$flashunlock.c$11$1$35
+
+
+
+flashlock 1095999
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+Fflashlock$flash_deviceid$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$flash_lock$0$0
+A$flashlock$1180
+A$flashlock$1183
+G$flash_lock$0$0
+C$flashlock.c$6$1$35
+C$flashlock.c$7$1$35
+C$flashlock.c$4$0$0
+_flash_lock
+
+
+
+flashwait 1126395
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+Fflashwait$flash_deviceid$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$flashwait.c$8$1$0
+_flash_wait
+XG$flash_wait$0$0
+A$flashwait$1220
+A$flashwait$1211
+A$flashwait$1230
+A$flashwait$1221
+A$flashwait$1212
+A$flashwait$1206
+A$flashwait$1216
+A$flashwait$1207
+A$flashwait$1235
+A$flashwait$1217
+A$flashwait$1208
+A$flashwait$1227
+A$flashwait$1193
+A$flashwait$1184
+A$flashwait$1239
+A$flashwait$1194
+A$flashwait$1185
+A$flashwait$1195
+A$flashwait$1188
+A$flashwait$1198
+C$flashwait.c$10$1$35
+C$flashwait.c$21$1$35
+C$flashwait.c$22$1$35
+C$flashwait.c$20$2$36
+C$flashwait.c$23$1$35
+C$flashwait.c$12$2$36
+C$flashwait.c$13$3$37
+C$flashwait.c$14$3$37
+C$flashwait.c$15$3$37
+C$flashwait.c$16$3$37
+C$flashwait.c$19$2$36
+C$flashwait.c$17$3$37
+C$flashwait.c$18$3$37
+G$flash_wait$0$0
+C$flashwait.c$9$1$35
+C$flashwait.c$4$0$0
+C$flashwait.c$7$1$0
+
+
+
+flashpgerase 1158118
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+Fflashpgerase$flash_deviceid$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
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+_flash_pageerase
+
+
+
+flashwrite 1189034
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+__XPAGE
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+_IC0CAPT1
+_IC1CAPT0
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+_RS0
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+Fflashwrite$flash_deviceid$0$0
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+_ADCCH0VAL0
+_GPIOENABLE
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+_E2IE_2
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+_ADCCH1VAL1
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+_FRCOSCFREQ1
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+
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+flashread 1220287
+.__.ABS.
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+flashcal 1223539
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+__XPAGE
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+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+_ADCCH0VAL1
+_ADCCH1VAL0
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+_PORTA_2
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+_PORTC_0
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+_CY
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+_DMA0ADDR
+_FRCOSCREF
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+_REF
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+_WTEVTC
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+Fflashcal$flash_calsector$0$0
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+_DMA1ADDR
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+_LPOSCREF
+_XTALOSC
+_ADCCALTEMPGAIN1
+_EIP
+_WTEVTD
+_IE_1
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+
+
+
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+
+
+
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+.__.ABS.
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+G$T0CNT1$0$0
+_DMA0ADDR1
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+_FRCOSCREF1
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+_IE
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+G$T2CNT0$0$0
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+_DMA1ADDR1
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+_DBGLNKBUF
+_WTEVTD1
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+_E2IP
+_P
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+_DPL1
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+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
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+_ADCCH0VAL0
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+_E2IE_2
+_RS1
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+_ADCCH0VAL1
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+_B_6
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+_PORTC_0
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+_ADCCH1VAL1
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+_ACC_2
+_B_7
+_E2IE_4
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+_PORTC_1
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+_ADCCH2VAL1
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+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
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+_ADCCH3VAL1
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+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
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+_RADIOFDATAADDR1
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+_WTEVTA
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+_DPH
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+_T2CNT1
+_WTEVTB
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+_CY
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+_PORTC_5
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
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+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
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+_FRCOSCFREQ1
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart_timer0_baud
+C$uarttimer0.c$9$0$0
+XG$uart_timer0_baud$0$0
+A$uarttimer0$1200
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+A$uarttimer0$1441
+A$uarttimer0$1432
+A$uarttimer0$1423
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+A$uarttimer0$1342
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+A$uarttimer0$1187
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+A$uarttimer0$1378
+A$uarttimer0$1369
+A$uarttimer0$1288
+A$uarttimer0$1279
+A$uarttimer0$1198
+C$uarttimer0.c$12$1$31
+A$uarttimer0$1496
+A$uarttimer0$1478
+A$uarttimer0$1469
+A$uarttimer0$1379
+A$uarttimer0$1289
+A$uarttimer0$1199
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+A$uarttimer0$1479
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+A$uarttimer0$1299
+C$uarttimer0.c$13$2$31
+A$uarttimer0$1498
+A$uarttimer0$1489
+A$uarttimer0$1399
+A$uarttimer0$1499
+C$uarttimer0.c$43$1$31
+C$uarttimer0.c$34$1$31
+C$uarttimer0.c$20$3$34
+C$uarttimer0.c$14$2$32
+C$uarttimer0.c$44$1$31
+C$uarttimer0.c$24$2$32
+C$uarttimer0.c$21$3$34
+C$uarttimer0.c$45$1$31
+C$uarttimer0.c$36$1$31
+C$uarttimer0.c$22$3$34
+C$uarttimer0.c$46$1$31
+C$uarttimer0.c$37$1$31
+C$uarttimer0.c$30$3$36
+C$uarttimer0.c$15$3$33
+C$uarttimer0.c$40$2$37
+C$uarttimer0.c$31$3$36
+C$uarttimer0.c$16$3$33
+C$uarttimer0.c$41$2$37
+C$uarttimer0.c$39$1$31
+C$uarttimer0.c$32$3$36
+C$uarttimer0.c$19$2$32
+C$uarttimer0.c$17$3$33
+C$uarttimer0.c$29$2$32
+C$uarttimer0.c$25$3$35
+C$uarttimer0.c$26$3$35
+C$uarttimer0.c$11$1$0
+C$uarttimer0.c$27$3$35
+G$uart_timer0_baud$0$0
+
+
+
+uarttimer1 1316699
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$PINA_1$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+_LPXOSCGM
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+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
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+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
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+G$PINC_4$0$0
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+_DIRR
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+_PALTA
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+G$NVADDR$0$0
+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
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+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
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+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$FRCOSCREF1$0$0
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+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+_WTCNTB1
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+_AC
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+_EA
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+_ACC
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+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$CLKSTAT$0$0
+_ADCCLKSRC
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+G$ADCCH0VAL1$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
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+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart_timer1_baud
+C$uarttimer1.c$9$0$0
+XG$uart_timer1_baud$0$0
+A$uarttimer1$1200
+A$uarttimer1$1300
+A$uarttimer1$1210
+A$uarttimer1$1201
+A$uarttimer1$1400
+A$uarttimer1$1310
+A$uarttimer1$1301
+A$uarttimer1$1220
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+A$uarttimer1$1500
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+A$uarttimer1$1302
+A$uarttimer1$1230
+A$uarttimer1$1221
+A$uarttimer1$1501
+A$uarttimer1$1420
+A$uarttimer1$1411
+A$uarttimer1$1402
+A$uarttimer1$1330
+A$uarttimer1$1321
+A$uarttimer1$1312
+A$uarttimer1$1240
+A$uarttimer1$1231
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+A$uarttimer1$1213
+A$uarttimer1$1520
+A$uarttimer1$1502
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+A$uarttimer1$1412
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+A$uarttimer1$1369
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+C$uarttimer1.c$12$1$31
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+C$uarttimer1.c$13$2$31
+A$uarttimer1$1498
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+A$uarttimer1$1399
+A$uarttimer1$1499
+C$uarttimer1.c$43$1$31
+C$uarttimer1.c$34$1$31
+C$uarttimer1.c$20$3$34
+C$uarttimer1.c$14$2$32
+C$uarttimer1.c$44$1$31
+C$uarttimer1.c$24$2$32
+C$uarttimer1.c$21$3$34
+C$uarttimer1.c$45$1$31
+C$uarttimer1.c$36$1$31
+C$uarttimer1.c$22$3$34
+C$uarttimer1.c$46$1$31
+C$uarttimer1.c$37$1$31
+C$uarttimer1.c$30$3$36
+C$uarttimer1.c$15$3$33
+C$uarttimer1.c$40$2$37
+C$uarttimer1.c$31$3$36
+C$uarttimer1.c$16$3$33
+C$uarttimer1.c$41$2$37
+C$uarttimer1.c$39$1$31
+C$uarttimer1.c$32$3$36
+C$uarttimer1.c$19$2$32
+C$uarttimer1.c$17$3$33
+C$uarttimer1.c$29$2$32
+C$uarttimer1.c$25$3$35
+C$uarttimer1.c$26$3$35
+C$uarttimer1.c$11$1$0
+C$uarttimer1.c$27$3$35
+G$uart_timer1_baud$0$0
+
+
+
+uarttimer2 1359617
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
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+_IE_4
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+_DIRC
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+G$NVADDR0$0$0
+_XTALAMPL
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+_IC1CAPT
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+_OV
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+_ADCCH1VAL
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+_ADCCH2VAL
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+_ADCCH3VAL
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+_T1MODE
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_RADIODATA2
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+_PINC_2
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+_ADCCH3CONFIG
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+_RADIOFSTATADDR1
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+_INTCHGB
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+.__.ABS.
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+_EA
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+_ACC
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+G$_XPAGE$0$0
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+G$RS0$0$0
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+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
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+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
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+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
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+G$E2IE_7$0$0
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+G$WTEVTA$0$0
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+G$T1CNT1$0$0
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+_DMA1ADDR1
+_LPOSCREF1
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+_WTEVTD1
+G$PORTC_5$0$0
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+G$PORTA_7$0$0
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+_E2IP
+_P
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+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
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+G$DMA1ADDR$0$0
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+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
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+_EIE
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+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+G$ADCCH1VAL$0$0
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+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
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+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
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+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
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+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
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+G$IP_3$0$0
+G$U1MODE$0$0
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+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart_timer2_baud
+C$uarttimer2.c$9$0$0
+XG$uart_timer2_baud$0$0
+A$uarttimer2$1200
+A$uarttimer2$1300
+A$uarttimer2$1210
+A$uarttimer2$1201
+A$uarttimer2$1400
+A$uarttimer2$1310
+A$uarttimer2$1301
+A$uarttimer2$1220
+A$uarttimer2$1202
+A$uarttimer2$1500
+A$uarttimer2$1410
+A$uarttimer2$1401
+A$uarttimer2$1320
+A$uarttimer2$1311
+A$uarttimer2$1302
+A$uarttimer2$1230
+A$uarttimer2$1221
+A$uarttimer2$1501
+A$uarttimer2$1420
+A$uarttimer2$1411
+A$uarttimer2$1402
+A$uarttimer2$1330
+A$uarttimer2$1321
+A$uarttimer2$1312
+A$uarttimer2$1240
+A$uarttimer2$1231
+A$uarttimer2$1222
+A$uarttimer2$1213
+A$uarttimer2$1520
+A$uarttimer2$1502
+A$uarttimer2$1430
+A$uarttimer2$1421
+A$uarttimer2$1412
+A$uarttimer2$1403
+A$uarttimer2$1340
+A$uarttimer2$1331
+A$uarttimer2$1322
+A$uarttimer2$1232
+A$uarttimer2$1223
+A$uarttimer2$1214
+A$uarttimer2$1205
+A$uarttimer2$1530
+A$uarttimer2$1521
+A$uarttimer2$1512
+A$uarttimer2$1503
+A$uarttimer2$1440
+A$uarttimer2$1431
+A$uarttimer2$1422
+A$uarttimer2$1413
+A$uarttimer2$1350
+A$uarttimer2$1341
+A$uarttimer2$1332
+A$uarttimer2$1323
+A$uarttimer2$1314
+A$uarttimer2$1305
+A$uarttimer2$1260
+A$uarttimer2$1251
+A$uarttimer2$1224
+A$uarttimer2$1215
+A$uarttimer2$1206
+A$uarttimer2$1531
+A$uarttimer2$1522
+A$uarttimer2$1513
+A$uarttimer2$1504
+A$uarttimer2$1450
+A$uarttimer2$1441
+A$uarttimer2$1432
+A$uarttimer2$1423
+A$uarttimer2$1414
+A$uarttimer2$1405
+A$uarttimer2$1351
+A$uarttimer2$1342
+A$uarttimer2$1333
+A$uarttimer2$1324
+A$uarttimer2$1270
+A$uarttimer2$1261
+A$uarttimer2$1225
+A$uarttimer2$1216
+A$uarttimer2$1207
+A$uarttimer2$1532
+A$uarttimer2$1514
+A$uarttimer2$1505
+A$uarttimer2$1460
+A$uarttimer2$1451
+A$uarttimer2$1442
+A$uarttimer2$1433
+A$uarttimer2$1415
+A$uarttimer2$1406
+A$uarttimer2$1370
+A$uarttimer2$1361
+A$uarttimer2$1352
+A$uarttimer2$1343
+A$uarttimer2$1334
+A$uarttimer2$1325
+A$uarttimer2$1316
+A$uarttimer2$1280
+A$uarttimer2$1271
+A$uarttimer2$1262
+A$uarttimer2$1244
+A$uarttimer2$1235
+A$uarttimer2$1226
+A$uarttimer2$1217
+A$uarttimer2$1208
+A$uarttimer2$1533
+A$uarttimer2$1515
+A$uarttimer2$1506
+A$uarttimer2$1470
+A$uarttimer2$1461
+A$uarttimer2$1452
+A$uarttimer2$1443
+A$uarttimer2$1434
+A$uarttimer2$1425
+A$uarttimer2$1416
+A$uarttimer2$1407
+A$uarttimer2$1380
+A$uarttimer2$1371
+A$uarttimer2$1353
+A$uarttimer2$1344
+A$uarttimer2$1335
+A$uarttimer2$1326
+A$uarttimer2$1290
+A$uarttimer2$1281
+A$uarttimer2$1272
+A$uarttimer2$1263
+A$uarttimer2$1254
+A$uarttimer2$1245
+A$uarttimer2$1236
+A$uarttimer2$1227
+A$uarttimer2$1218
+A$uarttimer2$1191
+A$uarttimer2$1182
+A$uarttimer2$1534
+A$uarttimer2$1525
+A$uarttimer2$1507
+A$uarttimer2$1480
+A$uarttimer2$1471
+A$uarttimer2$1462
+A$uarttimer2$1453
+A$uarttimer2$1444
+A$uarttimer2$1435
+A$uarttimer2$1417
+A$uarttimer2$1408
+A$uarttimer2$1381
+A$uarttimer2$1372
+A$uarttimer2$1354
+A$uarttimer2$1345
+A$uarttimer2$1336
+A$uarttimer2$1327
+A$uarttimer2$1309
+A$uarttimer2$1291
+A$uarttimer2$1282
+A$uarttimer2$1273
+A$uarttimer2$1264
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+A$uarttimer2$1246
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+A$uarttimer2$1219
+A$uarttimer2$1192
+A$uarttimer2$1183
+A$uarttimer2$1508
+A$uarttimer2$1490
+A$uarttimer2$1481
+A$uarttimer2$1472
+A$uarttimer2$1463
+A$uarttimer2$1454
+A$uarttimer2$1445
+A$uarttimer2$1436
+A$uarttimer2$1418
+A$uarttimer2$1409
+A$uarttimer2$1382
+A$uarttimer2$1373
+A$uarttimer2$1346
+A$uarttimer2$1337
+A$uarttimer2$1328
+A$uarttimer2$1319
+A$uarttimer2$1292
+A$uarttimer2$1283
+A$uarttimer2$1274
+A$uarttimer2$1265
+A$uarttimer2$1256
+A$uarttimer2$1247
+A$uarttimer2$1229
+A$uarttimer2$1193
+A$uarttimer2$1184
+A$uarttimer2$1509
+A$uarttimer2$1491
+A$uarttimer2$1482
+A$uarttimer2$1473
+A$uarttimer2$1464
+A$uarttimer2$1455
+A$uarttimer2$1446
+A$uarttimer2$1437
+A$uarttimer2$1428
+A$uarttimer2$1419
+A$uarttimer2$1392
+A$uarttimer2$1383
+A$uarttimer2$1374
+A$uarttimer2$1365
+A$uarttimer2$1347
+A$uarttimer2$1338
+A$uarttimer2$1329
+A$uarttimer2$1293
+A$uarttimer2$1284
+A$uarttimer2$1275
+A$uarttimer2$1266
+A$uarttimer2$1257
+A$uarttimer2$1537
+A$uarttimer2$1528
+A$uarttimer2$1519
+A$uarttimer2$1492
+A$uarttimer2$1483
+A$uarttimer2$1474
+A$uarttimer2$1456
+A$uarttimer2$1447
+A$uarttimer2$1438
+A$uarttimer2$1429
+A$uarttimer2$1384
+A$uarttimer2$1375
+A$uarttimer2$1366
+A$uarttimer2$1357
+A$uarttimer2$1348
+A$uarttimer2$1339
+A$uarttimer2$1294
+A$uarttimer2$1285
+A$uarttimer2$1276
+A$uarttimer2$1267
+A$uarttimer2$1258
+A$uarttimer2$1249
+A$uarttimer2$1529
+A$uarttimer2$1493
+A$uarttimer2$1484
+A$uarttimer2$1475
+A$uarttimer2$1457
+A$uarttimer2$1448
+A$uarttimer2$1439
+A$uarttimer2$1385
+A$uarttimer2$1376
+A$uarttimer2$1358
+A$uarttimer2$1349
+A$uarttimer2$1295
+A$uarttimer2$1286
+A$uarttimer2$1277
+A$uarttimer2$1268
+A$uarttimer2$1259
+A$uarttimer2$1187
+A$uarttimer2$1494
+A$uarttimer2$1485
+A$uarttimer2$1476
+A$uarttimer2$1467
+A$uarttimer2$1458
+A$uarttimer2$1449
+A$uarttimer2$1386
+A$uarttimer2$1377
+A$uarttimer2$1296
+A$uarttimer2$1287
+A$uarttimer2$1278
+A$uarttimer2$1269
+A$uarttimer2$1197
+A$uarttimer2$1495
+A$uarttimer2$1477
+A$uarttimer2$1459
+A$uarttimer2$1378
+A$uarttimer2$1369
+A$uarttimer2$1288
+A$uarttimer2$1279
+A$uarttimer2$1198
+C$uarttimer2.c$12$1$31
+A$uarttimer2$1496
+A$uarttimer2$1478
+A$uarttimer2$1469
+A$uarttimer2$1379
+A$uarttimer2$1289
+A$uarttimer2$1199
+A$uarttimer2$1497
+A$uarttimer2$1488
+A$uarttimer2$1479
+A$uarttimer2$1398
+A$uarttimer2$1389
+A$uarttimer2$1299
+C$uarttimer2.c$13$2$31
+A$uarttimer2$1498
+A$uarttimer2$1489
+A$uarttimer2$1399
+A$uarttimer2$1499
+C$uarttimer2.c$43$1$31
+C$uarttimer2.c$34$1$31
+C$uarttimer2.c$20$3$34
+C$uarttimer2.c$14$2$32
+C$uarttimer2.c$44$1$31
+C$uarttimer2.c$24$2$32
+C$uarttimer2.c$21$3$34
+C$uarttimer2.c$45$1$31
+C$uarttimer2.c$36$1$31
+C$uarttimer2.c$22$3$34
+C$uarttimer2.c$46$1$31
+C$uarttimer2.c$37$1$31
+C$uarttimer2.c$30$3$36
+C$uarttimer2.c$15$3$33
+C$uarttimer2.c$40$2$37
+C$uarttimer2.c$31$3$36
+C$uarttimer2.c$16$3$33
+C$uarttimer2.c$41$2$37
+C$uarttimer2.c$39$1$31
+C$uarttimer2.c$32$3$36
+C$uarttimer2.c$19$2$32
+C$uarttimer2.c$17$3$33
+C$uarttimer2.c$29$2$32
+C$uarttimer2.c$25$3$35
+C$uarttimer2.c$26$3$35
+C$uarttimer2.c$11$1$0
+C$uarttimer2.c$27$3$35
+G$uart_timer2_baud$0$0
+
+
+
+uart0init 1402535
+G$LPXOSCGM$0$0
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+G$EIP_0$0$0
+_MISCCTRL
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+_ADCCH1VAL
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+_FRCOSCKFILT0
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+_IP_2
+G$LPOSCCONFIG$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
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+_LPOSCKFILT1
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+_LPXOSCGM
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+_FRCOSCFREQ
+_XTALREADY
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+_LPOSCFREQ
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+_PCON
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+_PALTA
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+_ANALOGA
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+_PINA_1
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+G$E2IE$0$0
+_DMA1CONFIG
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+_ADCCH0CONFIG
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+_T1PERIOD1
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+_PINC_0
+G$EA$0$0
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+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
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+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
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+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
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+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
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+G$IE$0$0
+_B
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+_WTCNTB0
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+_WTCNTB1
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+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
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+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
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+_DPL1
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+__XPAGE
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+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+_PORTB_0
+G$XTALAMPL$0$0
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+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
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+_PORTC_1
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+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
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+_RADIOFDATAADDR1
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+_DPH
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
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+_PORTC_6
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+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
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+G$T2CNT$0$0
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+_FRCOSCFREQ1
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+_IE_2
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Fuart0init$uart0_fiforxrd$0$0
+Fuart0init$uart0_fifotxrd$0$0
+Fuart0init$uart0_fiforxwr$0$0
+Fuart0init$uart0_fifotxwr$0$0
+Luart0init.uart0_init$stop$1$101
+Luart0init.uart0_init$wl$1$101
+_uart0_init_PARM_2
+_uart0_init_PARM_3
+C$uart0init.c$148$1$68
+XG$uart0_irq$0$0
+C$uart0init.c$97$1$63
+G$uart0_poll$0$0
+_uart0_poll
+XFuart0init$dummy0$0$0
+G$uart0_irq$0$0
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+A$uart0init$1241
+A$uart0init$1242
+A$uart0init$1270
+A$uart0init$1243
+A$uart0init$1234
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+A$uart0init$1272
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+C$uart0init.c$121$1$66
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+A$uart0init$1237
+_uart0_irq
+A$uart0init$1274
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+A$uart0init$1275
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+C$uart0init.c$449$1$96
+XG$uart0_rxpeek$0$0
+_uart0_txpoke
+C$uart0init.c$466$1$98
+C$uart0init.c$467$1$98
+C$uart0init.c$469$1$98
+_uart0_txpokehex
+C$uart0init.c$1033$1$100
+C$uart0init.c$96$1$63
+Fuart0init$dummy0$0$0
+C$uart0init.c$84$0$0
+C$uart0init.c$1035$1$102
+XG$uart0_txpoke$0$0
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+G$uart0_init$0$0
+C$uart0init.c$1037$1$102
+C$uart0init.c$1038$1$102
+C$uart0init.c$1039$1$102
+XG$uart0_rxbuffersize$0$0
+XG$uart0_txpokehex$0$0
+XFuart0init$wtimer_cansleep_dummy$0$0
+_uart0_init
+C$uart0init.c$484$1$100
+C$uart0init.c$485$1$100
+G$uart0_txidle$0$0
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+_uart0_txidle
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+Fuart0init$wtimer_cansleep_dummy$0$0
+C$uart0init.c$452$1$96
+C$uart0init.c$309$1$78
+C$uart0init.c$284$1$76
+C$uart0init.c$259$1$74
+C$uart0init.c$149$1$68
+XFuart0init$uart0_iocore$0$0
+G$uart0_rxadvance$0$0
+G$uart0_rxbufptr$0$0
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+_uart0_rxadvance
+_uart0_rxbufptr
+_uart0_txadvance
+_uart0_txbufptr
+XG$uart0_poll$0$0
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+A$uart0init$1518
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+A$uart0init$1476
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+A$uart0init$1396
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+C$uart0init.c$256$1$74
+A$uart0init$1479
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+A$uart0init$1389
+C$uart0init.c$282$1$76
+C$uart0init.c$257$1$74
+Fuart0init$uart0_iocore$0$0
+A$uart0init$1399
+A$uart0init$1688
+C$uart0init.c$375$1$86
+C$uart0init.c$359$1$84
+C$uart0init.c$376$1$86
+XG$uart0_rxcountlinear$0$0
+XG$uart0_txfree$0$0
+C$uart0init.c$378$1$86
+C$uart0init.c$386$1$88
+C$uart0init.c$387$1$88
+C$uart0init.c$389$1$88
+XG$uart0_rxcount$0$0
+_uart0_rxbuffersize
+_uart0_txbuffersize
+XG$uart0_txbuffersize$0$0
+G$uart0_txfreelinear$0$0
+G$uart0_rxcountlinear$0$0
+G$uart0_txfree$0$0
+A$uart0init$1610
+G$uart0_rxcount$0$0
+A$uart0init$1602
+C$uart0init.c$400$1$90
+A$uart0init$1612
+A$uart0init$1603
+C$uart0init.c$330$1$80
+_uart0_txfreelinear
+A$uart0init$1640
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+C$uart0init.c$310$1$78
+_uart0_rxcountlinear
+_uart0_txfree
+A$uart0init$1663
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+A$uart0init$1609
+A$uart0init$1582
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+_uart0_rxcount
+A$uart0init$1686
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+A$uart0init$1830
+A$uart0init$1831
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+A$uart0init$1829
+
+
+
+uart1init 1453299
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
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+
+
+
+uart0stop 1504063
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+_RADIODATA2
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+.__.ABS.
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+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Fuart0stop$fiforxrd$0$0
+Fuart0stop$fifotxrd$0$0
+Fuart0stop$fiforxwr$0$0
+Fuart0stop$fifotxwr$0$0
+A$uart0stop$1190
+A$uart0stop$1193
+A$uart0stop$1196
+A$uart0stop$1199
+C$uart0stop.c$76$1$63
+C$uart0stop.c$77$1$63
+C$uart0stop.c$78$1$63
+C$uart0stop.c$79$1$63
+C$uart0stop.c$74$0$0
+G$uart0_stop$0$0
+_uart0_stop
+XG$uart0_stop$0$0
+
+
+
+uart1stop 1536276
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Fuart1stop$fiforxrd$0$0
+Fuart1stop$fifotxrd$0$0
+Fuart1stop$fiforxwr$0$0
+Fuart1stop$fifotxwr$0$0
+A$uart1stop$1190
+A$uart1stop$1193
+A$uart1stop$1196
+A$uart1stop$1199
+C$uart1stop.c$76$1$63
+C$uart1stop.c$77$1$63
+C$uart1stop.c$78$1$63
+C$uart1stop.c$79$1$63
+C$uart1stop.c$74$0$0
+G$uart1_stop$0$0
+_uart1_stop
+XG$uart1_stop$0$0
+
+
+
+uart0txbuf 1568489
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart0_txbuffer
+C$uart0txbuf.c$5$1$60
+C$uart0txbuf.c$5$0$0
+Fuart0txbuf$uart0_define_txbuffer$0$0
+XFuart0txbuf$uart0_define_txbuffer$0$0
+
+
+
+uart1txbuf 1600155
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart1_txbuffer
+C$uart1txbuf.c$5$1$60
+C$uart1txbuf.c$5$0$0
+Fuart1txbuf$uart1_define_txbuffer$0$0
+XFuart1txbuf$uart1_define_txbuffer$0$0
+
+
+
+uart0rxbuf 1631821
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart0_rxbuffer
+C$uart0rxbuf.c$5$1$60
+C$uart0rxbuf.c$5$0$0
+Fuart0rxbuf$uart0_define_rxbuffer$0$0
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+
+
+
+uart1rxbuf 1663487
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+_PORTC_1
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+_ADCCH2VAL1
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+_RADIOFDATAADDR1
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+_T2CNT0
+_WTEVTA
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+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
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+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
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+G$PINC$0$0
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+_DMA1ADDR
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+_LPOSCREF
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+_WTEVTD
+_IE_1
+_PORTC_7
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+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart1_rxbuffer
+C$uart1rxbuf.c$5$1$60
+C$uart1rxbuf.c$5$0$0
+Fuart1rxbuf$uart1_define_rxbuffer$0$0
+XFuart1rxbuf$uart1_define_rxbuffer$0$0
+
+
+
+uart0tx 1695153
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
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+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
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+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$F0$0$0
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+_FRCOSCKFILT0
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+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
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+_U0MODE
+_U1STATUS
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+G$PINA_0$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
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+_LPOSCKFILT1
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+_EXTIRQ
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
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+_E2IP_1
+_IE_3
+C$uart0tx.c$29$2$61
+G$uart0_wait_txfree$0$0
+C$uart0tx.c$45$2$64
+C$uart0tx.c$54$1$66
+C$uart0tx.c$46$2$64
+C$uart0tx.c$24$0$0
+C$uart0tx.c$55$1$66
+C$uart0tx.c$47$2$64
+C$uart0tx.c$49$1$63
+C$uart0tx.c$56$1$66
+G$uart0_wait_txdone$0$0
+C$uart0tx.c$57$1$66
+G$uart0_tx$0$0
+_uart0_wait_txfree
+_uart0_wait_txdone
+_uart0_tx
+XG$uart0_wait_txfree$0$0
+XG$uart0_wait_txdone$0$0
+XG$uart0_tx$0$0
+A$uart0tx$1300
+A$uart0tx$1201
+A$uart0tx$1310
+A$uart0tx$1230
+A$uart0tx$1221
+A$uart0tx$1212
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+A$uart0tx$1213
+A$uart0tx$1204
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+A$uart0tx$1304
+A$uart0tx$1223
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+A$uart0tx$1206
+A$uart0tx$1315
+A$uart0tx$1252
+A$uart0tx$1234
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+A$uart0tx$1307
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+A$uart0tx$1194
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+A$uart0tx$1277
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+A$uart0tx$1278
+A$uart0tx$1269
+A$uart0tx$1188
+A$uart0tx$1189
+A$uart0tx$1299
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+C$uart0tx.c$40$1$63
+C$uart0tx.c$32$2$61
+C$uart0tx.c$50$1$63
+C$uart0tx.c$33$2$61
+C$uart0tx.c$35$1$60
+C$uart0tx.c$26$1$60
+C$uart0tx.c$36$1$60
+C$uart0tx.c$52$1$63
+C$uart0tx.c$42$2$64
+C$uart0tx.c$38$1$60
+C$uart0tx.c$43$2$64
+C$uart0tx.c$28$2$61
+
+
+
+uart1tx 1730113
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
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+_DIRC
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+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
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+G$PINA_3$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
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+G$PINA_5$0$0
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+G$ADCCONV$0$0
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+G$PINC_7$0$0
+_ADCTUNE0
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+_EIP_7
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+_ADCTUNE1
+_FRCOSCCTRL
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+G$B$0$0
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+_FRCOSCKFILT
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+_CLKCON
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+_T2PERIOD1
+_U0CTRL
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+_PINB_2
+_PINC_1
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+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
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+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
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+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
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+_PINB_5
+_PINC_4
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+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
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+_PINC_5
+G$PINSEL$0$0
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+_INTCHGB
+_NVADDR
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+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
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+G$NVKEY$0$0
+G$DPH1$0$0
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+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+_WTCNTB0
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+G$B_3$0$0
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+G$PORTA_4$0$0
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+G$ACC_3$0$0
+G$T0CNT0$0$0
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+G$T1CNT1$0$0
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+G$PORTC_5$0$0
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+G$PORTA_7$0$0
+G$CY$0$0
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+G$T2CNT1$0$0
+G$SPSHREG$0$0
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+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
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+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_DPL1
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+__XPAGE
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+_IC0CAPT1
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+_ADCCH0VAL0
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+_E2IE_2
+_RS1
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+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
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+_PORTR
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+_B_6
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+_PORTB_1
+_PORTC_0
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+_ADCCH1VAL1
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+_ACC_2
+_B_7
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+_PORTC_1
+G$OV$0$0
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+_ADCCH2VAL1
+_ADCCH3VAL0
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+_IP
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+_ADCCH3VAL1
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+_OSCRUN
+_RADIOFDATAADDR0
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+_T1CNT0
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+_RADIOFDATAADDR1
+_RADIOSTAT0
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+_WTEVTA
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+_PORTC_4
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+_DPH
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+_T2CNT1
+_WTEVTB
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+_CY
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+_PORTC_5
+G$RADIOMUX$0$0
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+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_IE_0
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+_DMA1ADDR
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+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$uart1tx.c$43$2$64
+C$uart1tx.c$28$2$61
+C$uart1tx.c$29$2$61
+G$uart1_wait_txfree$0$0
+C$uart1tx.c$45$2$64
+C$uart1tx.c$54$1$66
+C$uart1tx.c$46$2$64
+C$uart1tx.c$24$0$0
+C$uart1tx.c$55$1$66
+C$uart1tx.c$47$2$64
+C$uart1tx.c$49$1$63
+C$uart1tx.c$56$1$66
+G$uart1_wait_txdone$0$0
+C$uart1tx.c$57$1$66
+G$uart1_tx$0$0
+_uart1_wait_txfree
+_uart1_wait_txdone
+_uart1_tx
+XG$uart1_wait_txfree$0$0
+XG$uart1_wait_txdone$0$0
+XG$uart1_tx$0$0
+A$uart1tx$1300
+A$uart1tx$1201
+A$uart1tx$1310
+A$uart1tx$1230
+A$uart1tx$1221
+A$uart1tx$1212
+A$uart1tx$1303
+A$uart1tx$1231
+A$uart1tx$1222
+A$uart1tx$1213
+A$uart1tx$1204
+A$uart1tx$1313
+A$uart1tx$1304
+A$uart1tx$1223
+A$uart1tx$1214
+A$uart1tx$1205
+A$uart1tx$1314
+A$uart1tx$1251
+A$uart1tx$1206
+A$uart1tx$1315
+A$uart1tx$1252
+A$uart1tx$1234
+A$uart1tx$1207
+A$uart1tx$1307
+A$uart1tx$1262
+A$uart1tx$1253
+A$uart1tx$1217
+A$uart1tx$1208
+A$uart1tx$1190
+A$uart1tx$1308
+A$uart1tx$1272
+A$uart1tx$1263
+A$uart1tx$1227
+A$uart1tx$1209
+A$uart1tx$1318
+A$uart1tx$1309
+A$uart1tx$1282
+A$uart1tx$1264
+A$uart1tx$1228
+A$uart1tx$1283
+A$uart1tx$1229
+A$uart1tx$1193
+A$uart1tx$1194
+A$uart1tx$1276
+A$uart1tx$1267
+A$uart1tx$1195
+A$uart1tx$1286
+A$uart1tx$1277
+A$uart1tx$1268
+A$uart1tx$1259
+A$uart1tx$1187
+A$uart1tx$1278
+A$uart1tx$1269
+A$uart1tx$1188
+A$uart1tx$1189
+A$uart1tx$1299
+C$uart1tx.c$31$2$61
+C$uart1tx.c$40$1$63
+C$uart1tx.c$32$2$61
+C$uart1tx.c$50$1$63
+C$uart1tx.c$33$2$61
+C$uart1tx.c$35$1$60
+C$uart1tx.c$26$1$60
+C$uart1tx.c$36$1$60
+C$uart1tx.c$52$1$63
+C$uart1tx.c$42$2$64
+C$uart1tx.c$38$1$60
+
+
+
+uart0rx 1765073
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$uart0rx.c$24$0$0
+G$uart0_wait_rxcount$0$0
+G$uart0_rx$0$0
+_uart0_wait_rxcount
+_uart0_rx
+XG$uart0_wait_rxcount$0$0
+XG$uart0_rx$0$0
+A$uart0rx$1210
+A$uart0rx$1220
+A$uart0rx$1211
+A$uart0rx$1202
+A$uart0rx$1221
+A$uart0rx$1212
+A$uart0rx$1203
+A$uart0rx$1204
+A$uart0rx$1250
+A$uart0rx$1232
+A$uart0rx$1205
+A$uart0rx$1260
+A$uart0rx$1251
+A$uart0rx$1215
+A$uart0rx$1206
+A$uart0rx$1225
+A$uart0rx$1207
+A$uart0rx$1226
+A$uart0rx$1263
+A$uart0rx$1254
+A$uart0rx$1227
+A$uart0rx$1191
+A$uart0rx$1264
+A$uart0rx$1255
+A$uart0rx$1228
+A$uart0rx$1219
+A$uart0rx$1192
+A$uart0rx$1256
+A$uart0rx$1247
+A$uart0rx$1229
+A$uart0rx$1193
+A$uart0rx$1185
+A$uart0rx$1267
+A$uart0rx$1186
+A$uart0rx$1259
+A$uart0rx$1187
+A$uart0rx$1188
+A$uart0rx$1199
+C$uart0rx.c$31$2$61
+C$uart0rx.c$32$2$61
+C$uart0rx.c$41$1$63
+C$uart0rx.c$33$2$61
+C$uart0rx.c$35$1$60
+C$uart0rx.c$26$1$60
+C$uart0rx.c$42$1$63
+C$uart0rx.c$36$1$60
+C$uart0rx.c$43$1$63
+C$uart0rx.c$44$1$63
+C$uart0rx.c$38$1$60
+C$uart0rx.c$45$1$63
+C$uart0rx.c$28$2$61
+C$uart0rx.c$29$2$61
+
+
+
+uart1rx 1798734
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
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+_IC1STATUS
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+_E2IP_2
+_IE_4
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+_DIRC
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+G$NVADDR0$0$0
+_XTALAMPL
+_SP
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+_EIE_1
+_IE_6
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+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
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+_IE_7
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+G$OC0COMP$0$0
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+_IC1CAPT
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+_E2IP_6
+_EIE_3
+_OV
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+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
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+_ADCCH1VAL
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+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$ADCTUNE0$0$0
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+_ADCCH2VAL
+_LPOSCPER
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+G$XPAGE$0$0
+_ADCCH3VAL
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+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$F0$0$0
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+_FRCOSCKFILT0
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+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
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+G$PINA_0$0$0
+G$F1$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$uart1rx.c$24$0$0
+G$uart1_wait_rxcount$0$0
+G$uart1_rx$0$0
+_uart1_wait_rxcount
+_uart1_rx
+XG$uart1_wait_rxcount$0$0
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+A$uart1rx$1210
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+C$uart1rx.c$32$2$61
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+C$uart1rx.c$33$2$61
+C$uart1rx.c$35$1$60
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+C$uart1rx.c$44$1$63
+C$uart1rx.c$38$1$60
+C$uart1rx.c$45$1$63
+C$uart1rx.c$28$2$61
+C$uart1rx.c$29$2$61
+
+
+
+uart0wrhexu16 1832395
+.__.ABS.
+XG$uart0_writehexu16$0$0
+A$uart0wrhexu16$122
+C$uart0wrhexu16.c$30$1$60
+A$uart0wrhexu16$150
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+G$uart0_writehexu16$0$0
+_uart0_writehexu16
+
+
+
+uart1wrhexu16 1838356
+.__.ABS.
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+G$uart1_writehexu16$0$0
+_uart1_writehexu16
+
+
+
+uart0wrhexu32 1844317
+.__.ABS.
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+Luart0wrhexu32.uart0_writehexu32$nrdig$1$59
+XG$uart0_writehexu32$0$0
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+G$uart0_writehexu32$0$0
+_uart0_writehexu32
+
+
+
+uart1wrhexu32 1850797
+.__.ABS.
+_uart1_writehexu32_PARM_2
+Luart1wrhexu32.uart1_writehexu32$nrdig$1$59
+XG$uart1_writehexu32$0$0
+A$uart1wrhexu32$120
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+C$uart1wrhexu32.c$30$1$60
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+C$uart1wrhexu32.c$19$0$0
+G$uart1_writehexu32$0$0
+_uart1_writehexu32
+
+
+
+uart0wrstr 1857277
+.__.ABS.
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+G$uart0_writestr$0$0
+_uart0_writestr
+XG$uart0_writestr$0$0
+C$uart0wrstr.c$102$1$60
+C$uart0wrstr.c$103$1$60
+
+
+
+uart1wrstr 1864222
+.__.ABS.
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+G$uart1_writestr$0$0
+_uart1_writestr
+XG$uart1_writestr$0$0
+C$uart1wrstr.c$102$1$60
+C$uart1wrstr.c$103$1$60
+
+
+
+uart0wru16 1871167
+.__.ABS.
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+G$uart0_writeu16$0$0
+_uart0_writeu16
+XG$uart0_writeu16$0$0
+
+
+
+uart1wru16 1877722
+.__.ABS.
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+G$uart1_writeu16$0$0
+_uart1_writeu16
+XG$uart1_writeu16$0$0
+
+
+
+uart0wru32 1884277
+.__.ABS.
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+_uart0_writeu32
+XG$uart0_writeu32$0$0
+
+
+
+uart1wru32 1890995
+.__.ABS.
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+
+
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+
+
+
+uart0wrnum32 1907935
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+
+
+
+uart0wrhex16 1919525
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+
+
+
+uart1wrnum16 1942389
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+C$uart1wrnum16.c$241$1$62
+A$uart1wrnum16$200
+A$uart1wrnum16$300
+A$uart1wrnum16$210
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+A$uart1wrnum16$302
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+A$uart1wrnum16$314
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+A$uart1wrnum16$233
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+A$uart1wrnum16$215
+A$uart1wrnum16$152
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+A$uart1wrnum16$153
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+A$uart1wrnum16$117
+A$uart1wrnum16$316
+A$uart1wrnum16$307
+A$uart1wrnum16$280
+A$uart1wrnum16$244
+A$uart1wrnum16$235
+A$uart1wrnum16$226
+A$uart1wrnum16$217
+A$uart1wrnum16$208
+A$uart1wrnum16$163
+A$uart1wrnum16$154
+A$uart1wrnum16$145
+A$uart1wrnum16$118
+A$uart1wrnum16$308
+A$uart1wrnum16$290
+A$uart1wrnum16$281
+A$uart1wrnum16$272
+A$uart1wrnum16$263
+A$uart1wrnum16$245
+A$uart1wrnum16$236
+A$uart1wrnum16$227
+A$uart1wrnum16$218
+A$uart1wrnum16$209
+A$uart1wrnum16$182
+A$uart1wrnum16$173
+A$uart1wrnum16$164
+A$uart1wrnum16$155
+A$uart1wrnum16$146
+A$uart1wrnum16$128
+A$uart1wrnum16$119
+A$uart1wrnum16$309
+A$uart1wrnum16$291
+A$uart1wrnum16$282
+A$uart1wrnum16$273
+A$uart1wrnum16$255
+A$uart1wrnum16$228
+A$uart1wrnum16$192
+A$uart1wrnum16$183
+A$uart1wrnum16$174
+A$uart1wrnum16$165
+A$uart1wrnum16$156
+A$uart1wrnum16$147
+A$uart1wrnum16$292
+A$uart1wrnum16$265
+A$uart1wrnum16$247
+A$uart1wrnum16$238
+A$uart1wrnum16$229
+A$uart1wrnum16$193
+A$uart1wrnum16$184
+A$uart1wrnum16$175
+A$uart1wrnum16$166
+A$uart1wrnum16$148
+A$uart1wrnum16$139
+A$uart1wrnum16$293
+A$uart1wrnum16$284
+A$uart1wrnum16$275
+A$uart1wrnum16$266
+A$uart1wrnum16$257
+A$uart1wrnum16$239
+A$uart1wrnum16$185
+A$uart1wrnum16$176
+A$uart1wrnum16$167
+A$uart1wrnum16$158
+A$uart1wrnum16$149
+A$uart1wrnum16$294
+A$uart1wrnum16$276
+A$uart1wrnum16$258
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+A$uart1wrnum16$186
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+A$uart1wrnum16$295
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+A$uart1wrnum16$187
+A$uart1wrnum16$296
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+A$uart1wrnum16$269
+A$uart1wrnum16$197
+A$uart1wrnum16$297
+A$uart1wrnum16$279
+A$uart1wrnum16$198
+C$uart1wrnum16.c$25$0$0
+A$uart1wrnum16$298
+A$uart1wrnum16$289
+
+
+
+uart1wrnum32 1952611
+.__.ABS.
+_uart1_writenum32
+XG$uart1_writenum32$0$0
+A$uart1wrnum32$200
+A$uart1wrnum32$300
+A$uart1wrnum32$210
+A$uart1wrnum32$201
+A$uart1wrnum32$120
+C$uart1wrnum32.c$276$1$62
+A$uart1wrnum32$310
+A$uart1wrnum32$301
+A$uart1wrnum32$220
+A$uart1wrnum32$211
+A$uart1wrnum32$130
+A$uart1wrnum32$121
+C$uart1wrnum32.c$277$1$62
+A$uart1wrnum32$311
+A$uart1wrnum32$230
+A$uart1wrnum32$221
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+A$uart1wrnum32$330
+A$uart1wrnum32$312
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+A$uart1wrnum32$231
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+A$uart1wrnum32$150
+A$uart1wrnum32$141
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+A$uart1wrnum32$313
+A$uart1wrnum32$304
+A$uart1wrnum32$250
+A$uart1wrnum32$241
+A$uart1wrnum32$232
+A$uart1wrnum32$223
+A$uart1wrnum32$160
+A$uart1wrnum32$151
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+A$uart1wrnum32$124
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+A$uart1wrnum32$341
+A$uart1wrnum32$332
+A$uart1wrnum32$314
+A$uart1wrnum32$305
+A$uart1wrnum32$260
+A$uart1wrnum32$233
+A$uart1wrnum32$224
+A$uart1wrnum32$206
+A$uart1wrnum32$161
+A$uart1wrnum32$152
+A$uart1wrnum32$143
+A$uart1wrnum32$134
+A$uart1wrnum32$125
+A$uart1wrnum32$116
+A$uart1wrnum32$351
+A$uart1wrnum32$342
+A$uart1wrnum32$333
+A$uart1wrnum32$324
+A$uart1wrnum32$315
+A$uart1wrnum32$270
+A$uart1wrnum32$261
+A$uart1wrnum32$243
+A$uart1wrnum32$234
+A$uart1wrnum32$225
+A$uart1wrnum32$216
+A$uart1wrnum32$207
+A$uart1wrnum32$162
+A$uart1wrnum32$153
+A$uart1wrnum32$144
+A$uart1wrnum32$117
+A$uart1wrnum32$352
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+A$uart1wrnum32$316
+A$uart1wrnum32$307
+A$uart1wrnum32$280
+A$uart1wrnum32$235
+A$uart1wrnum32$226
+A$uart1wrnum32$208
+A$uart1wrnum32$190
+A$uart1wrnum32$172
+A$uart1wrnum32$163
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+A$uart1wrnum32$145
+A$uart1wrnum32$127
+A$uart1wrnum32$335
+A$uart1wrnum32$326
+A$uart1wrnum32$317
+A$uart1wrnum32$308
+A$uart1wrnum32$290
+A$uart1wrnum32$263
+A$uart1wrnum32$254
+A$uart1wrnum32$245
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+A$uart1wrnum32$218
+A$uart1wrnum32$209
+A$uart1wrnum32$191
+A$uart1wrnum32$173
+A$uart1wrnum32$164
+A$uart1wrnum32$155
+A$uart1wrnum32$146
+A$uart1wrnum32$128
+A$uart1wrnum32$119
+A$uart1wrnum32$354
+A$uart1wrnum32$345
+A$uart1wrnum32$336
+A$uart1wrnum32$327
+A$uart1wrnum32$282
+A$uart1wrnum32$273
+A$uart1wrnum32$264
+A$uart1wrnum32$255
+A$uart1wrnum32$228
+A$uart1wrnum32$219
+A$uart1wrnum32$174
+A$uart1wrnum32$165
+A$uart1wrnum32$156
+A$uart1wrnum32$147
+A$uart1wrnum32$346
+A$uart1wrnum32$337
+A$uart1wrnum32$328
+A$uart1wrnum32$319
+A$uart1wrnum32$292
+A$uart1wrnum32$274
+A$uart1wrnum32$265
+A$uart1wrnum32$256
+A$uart1wrnum32$247
+A$uart1wrnum32$238
+A$uart1wrnum32$193
+A$uart1wrnum32$175
+A$uart1wrnum32$166
+A$uart1wrnum32$157
+A$uart1wrnum32$148
+A$uart1wrnum32$356
+A$uart1wrnum32$347
+A$uart1wrnum32$338
+A$uart1wrnum32$329
+A$uart1wrnum32$293
+A$uart1wrnum32$275
+A$uart1wrnum32$266
+A$uart1wrnum32$257
+A$uart1wrnum32$248
+A$uart1wrnum32$239
+A$uart1wrnum32$194
+A$uart1wrnum32$176
+A$uart1wrnum32$158
+A$uart1wrnum32$149
+A$uart1wrnum32$348
+A$uart1wrnum32$339
+A$uart1wrnum32$276
+A$uart1wrnum32$267
+A$uart1wrnum32$258
+A$uart1wrnum32$195
+A$uart1wrnum32$177
+A$uart1wrnum32$168
+A$uart1wrnum32$349
+A$uart1wrnum32$277
+A$uart1wrnum32$268
+A$uart1wrnum32$259
+A$uart1wrnum32$196
+A$uart1wrnum32$187
+A$uart1wrnum32$296
+A$uart1wrnum32$278
+A$uart1wrnum32$269
+A$uart1wrnum32$188
+A$uart1wrnum32$279
+A$uart1wrnum32$198
+A$uart1wrnum32$189
+C$uart1wrnum32.c$25$0$0
+A$uart1wrnum32$298
+A$uart1wrnum32$199
+G$uart1_writenum32$0$0
+
+
+
+uart1wrhex16 1964201
+.__.ABS.
+_uart1_writehex16
+XG$uart1_writehex16$0$0
+C$uart1wrhex16.c$264$1$62
+C$uart1wrhex16.c$265$1$62
+A$uart1wrhex16$200
+A$uart1wrhex16$201
+A$uart1wrhex16$120
+A$uart1wrhex16$310
+A$uart1wrhex16$301
+A$uart1wrhex16$220
+A$uart1wrhex16$211
+A$uart1wrhex16$202
+A$uart1wrhex16$121
+A$uart1wrhex16$320
+A$uart1wrhex16$311
+A$uart1wrhex16$302
+A$uart1wrhex16$230
+A$uart1wrhex16$221
+A$uart1wrhex16$203
+A$uart1wrhex16$140
+A$uart1wrhex16$122
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+A$uart1wrhex16$321
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+A$uart1wrhex16$331
+A$uart1wrhex16$322
+A$uart1wrhex16$313
+A$uart1wrhex16$304
+A$uart1wrhex16$232
+A$uart1wrhex16$223
+A$uart1wrhex16$205
+A$uart1wrhex16$142
+A$uart1wrhex16$341
+A$uart1wrhex16$332
+A$uart1wrhex16$323
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+A$uart1wrhex16$260
+A$uart1wrhex16$242
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+A$uart1wrhex16$306
+A$uart1wrhex16$270
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+A$uart1wrhex16$207
+A$uart1wrhex16$162
+A$uart1wrhex16$153
+A$uart1wrhex16$144
+A$uart1wrhex16$126
+A$uart1wrhex16$117
+A$uart1wrhex16$343
+A$uart1wrhex16$334
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+A$uart1wrhex16$271
+A$uart1wrhex16$262
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+A$uart1wrhex16$244
+A$uart1wrhex16$208
+A$uart1wrhex16$163
+A$uart1wrhex16$154
+A$uart1wrhex16$145
+A$uart1wrhex16$118
+A$uart1wrhex16$335
+A$uart1wrhex16$326
+A$uart1wrhex16$308
+A$uart1wrhex16$290
+A$uart1wrhex16$272
+A$uart1wrhex16$263
+A$uart1wrhex16$254
+A$uart1wrhex16$227
+A$uart1wrhex16$218
+A$uart1wrhex16$182
+A$uart1wrhex16$173
+A$uart1wrhex16$164
+A$uart1wrhex16$155
+A$uart1wrhex16$146
+A$uart1wrhex16$128
+A$uart1wrhex16$119
+A$uart1wrhex16$345
+A$uart1wrhex16$336
+A$uart1wrhex16$327
+A$uart1wrhex16$318
+A$uart1wrhex16$309
+A$uart1wrhex16$273
+A$uart1wrhex16$264
+A$uart1wrhex16$255
+A$uart1wrhex16$246
+A$uart1wrhex16$237
+A$uart1wrhex16$219
+A$uart1wrhex16$192
+A$uart1wrhex16$183
+A$uart1wrhex16$174
+A$uart1wrhex16$165
+A$uart1wrhex16$156
+A$uart1wrhex16$147
+A$uart1wrhex16$337
+A$uart1wrhex16$319
+A$uart1wrhex16$292
+A$uart1wrhex16$274
+A$uart1wrhex16$265
+A$uart1wrhex16$256
+A$uart1wrhex16$247
+A$uart1wrhex16$238
+A$uart1wrhex16$193
+A$uart1wrhex16$184
+A$uart1wrhex16$175
+A$uart1wrhex16$166
+A$uart1wrhex16$148
+A$uart1wrhex16$139
+A$uart1wrhex16$338
+A$uart1wrhex16$329
+A$uart1wrhex16$284
+A$uart1wrhex16$257
+A$uart1wrhex16$239
+A$uart1wrhex16$194
+A$uart1wrhex16$185
+A$uart1wrhex16$176
+A$uart1wrhex16$167
+A$uart1wrhex16$158
+A$uart1wrhex16$149
+A$uart1wrhex16$339
+A$uart1wrhex16$294
+A$uart1wrhex16$276
+A$uart1wrhex16$267
+A$uart1wrhex16$258
+A$uart1wrhex16$249
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+A$uart1wrhex16$186
+A$uart1wrhex16$177
+A$uart1wrhex16$295
+A$uart1wrhex16$286
+A$uart1wrhex16$268
+A$uart1wrhex16$259
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+A$uart1wrhex16$187
+A$uart1wrhex16$287
+A$uart1wrhex16$269
+A$uart1wrhex16$197
+A$uart1wrhex16$198
+C$uart1wrhex16.c$25$0$0
+A$uart1wrhex16$298
+A$uart1wrhex16$299
+G$uart1_writehex16$0$0
+
+
+
+uart1wrhex32 1975271
+.__.ABS.
+_uart1_writehex32
+XG$uart1_writehex32$0$0
+C$uart1wrhex32.c$282$1$62
+C$uart1wrhex32.c$283$1$62
+A$uart1wrhex32$210
+A$uart1wrhex32$120
+A$uart1wrhex32$310
+A$uart1wrhex32$220
+A$uart1wrhex32$211
+A$uart1wrhex32$202
+A$uart1wrhex32$130
+A$uart1wrhex32$121
+A$uart1wrhex32$221
+A$uart1wrhex32$212
+A$uart1wrhex32$203
+A$uart1wrhex32$122
+A$uart1wrhex32$330
+A$uart1wrhex32$321
+A$uart1wrhex32$312
+A$uart1wrhex32$240
+A$uart1wrhex32$231
+A$uart1wrhex32$222
+A$uart1wrhex32$213
+A$uart1wrhex32$204
+A$uart1wrhex32$150
+A$uart1wrhex32$141
+A$uart1wrhex32$123
+A$uart1wrhex32$340
+A$uart1wrhex32$331
+A$uart1wrhex32$322
+A$uart1wrhex32$304
+A$uart1wrhex32$250
+A$uart1wrhex32$241
+A$uart1wrhex32$223
+A$uart1wrhex32$205
+A$uart1wrhex32$160
+A$uart1wrhex32$151
+A$uart1wrhex32$142
+A$uart1wrhex32$124
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+A$uart1wrhex32$341
+A$uart1wrhex32$314
+A$uart1wrhex32$260
+A$uart1wrhex32$251
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+A$uart1wrhex32$206
+A$uart1wrhex32$161
+A$uart1wrhex32$152
+A$uart1wrhex32$143
+A$uart1wrhex32$134
+A$uart1wrhex32$125
+A$uart1wrhex32$116
+A$uart1wrhex32$360
+A$uart1wrhex32$351
+A$uart1wrhex32$342
+A$uart1wrhex32$333
+A$uart1wrhex32$324
+A$uart1wrhex32$315
+A$uart1wrhex32$306
+A$uart1wrhex32$252
+A$uart1wrhex32$243
+A$uart1wrhex32$225
+A$uart1wrhex32$216
+A$uart1wrhex32$207
+A$uart1wrhex32$162
+A$uart1wrhex32$153
+A$uart1wrhex32$144
+A$uart1wrhex32$117
+A$uart1wrhex32$361
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+A$uart1wrhex32$343
+A$uart1wrhex32$325
+A$uart1wrhex32$307
+A$uart1wrhex32$280
+A$uart1wrhex32$262
+A$uart1wrhex32$253
+A$uart1wrhex32$244
+A$uart1wrhex32$217
+A$uart1wrhex32$208
+A$uart1wrhex32$172
+A$uart1wrhex32$163
+A$uart1wrhex32$154
+A$uart1wrhex32$145
+A$uart1wrhex32$127
+A$uart1wrhex32$344
+A$uart1wrhex32$326
+A$uart1wrhex32$290
+A$uart1wrhex32$254
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+A$uart1wrhex32$227
+A$uart1wrhex32$218
+A$uart1wrhex32$173
+A$uart1wrhex32$164
+A$uart1wrhex32$155
+A$uart1wrhex32$146
+A$uart1wrhex32$128
+A$uart1wrhex32$119
+A$uart1wrhex32$363
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+A$uart1wrhex32$345
+A$uart1wrhex32$327
+A$uart1wrhex32$318
+A$uart1wrhex32$291
+A$uart1wrhex32$282
+A$uart1wrhex32$273
+A$uart1wrhex32$264
+A$uart1wrhex32$228
+A$uart1wrhex32$192
+A$uart1wrhex32$183
+A$uart1wrhex32$174
+A$uart1wrhex32$165
+A$uart1wrhex32$156
+A$uart1wrhex32$147
+A$uart1wrhex32$355
+A$uart1wrhex32$346
+A$uart1wrhex32$328
+A$uart1wrhex32$319
+A$uart1wrhex32$292
+A$uart1wrhex32$283
+A$uart1wrhex32$274
+A$uart1wrhex32$247
+A$uart1wrhex32$238
+A$uart1wrhex32$193
+A$uart1wrhex32$184
+A$uart1wrhex32$175
+A$uart1wrhex32$166
+A$uart1wrhex32$157
+A$uart1wrhex32$148
+A$uart1wrhex32$365
+A$uart1wrhex32$356
+A$uart1wrhex32$347
+A$uart1wrhex32$338
+A$uart1wrhex32$329
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+A$uart1wrhex32$284
+A$uart1wrhex32$275
+A$uart1wrhex32$266
+A$uart1wrhex32$257
+A$uart1wrhex32$239
+A$uart1wrhex32$194
+A$uart1wrhex32$185
+A$uart1wrhex32$176
+A$uart1wrhex32$158
+A$uart1wrhex32$149
+A$uart1wrhex32$357
+A$uart1wrhex32$339
+A$uart1wrhex32$294
+A$uart1wrhex32$285
+A$uart1wrhex32$276
+A$uart1wrhex32$267
+A$uart1wrhex32$258
+A$uart1wrhex32$195
+A$uart1wrhex32$186
+A$uart1wrhex32$177
+A$uart1wrhex32$168
+A$uart1wrhex32$358
+A$uart1wrhex32$349
+A$uart1wrhex32$277
+A$uart1wrhex32$259
+A$uart1wrhex32$196
+A$uart1wrhex32$187
+A$uart1wrhex32$359
+A$uart1wrhex32$296
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+A$uart1wrhex32$278
+A$uart1wrhex32$269
+A$uart1wrhex32$197
+A$uart1wrhex32$288
+A$uart1wrhex32$279
+C$uart1wrhex32.c$25$0$0
+A$uart1wrhex32$289
+G$uart1_writehex32$0$0
+
+
+
+adctemp 1987065
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
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+
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+_DPL
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+_IE_3
+_adc_calibrate_gain
+A$adccalg$1300
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+A$adccalg$1228
+A$adccalg$1219
+A$adccalg$1355
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+
+
+
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+
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+
+
+
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+C$bch3121decp.c$9$1$33
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+_bch3121_decode_parity
+XG$bch3121_decode_parity$0$0
+A$bch3121decp$1200
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+A$bch3121decp$1201
+A$bch3121decp$1220
+A$bch3121decp$1211
+A$bch3121decp$1202
+A$bch3121decp$1230
+A$bch3121decp$1221
+A$bch3121decp$1212
+A$bch3121decp$1240
+A$bch3121decp$1231
+A$bch3121decp$1222
+A$bch3121decp$1213
+A$bch3121decp$1241
+A$bch3121decp$1232
+A$bch3121decp$1223
+A$bch3121decp$1205
+A$bch3121decp$1242
+A$bch3121decp$1233
+A$bch3121decp$1224
+A$bch3121decp$1206
+A$bch3121decp$1234
+A$bch3121decp$1225
+A$bch3121decp$1235
+A$bch3121decp$1226
+A$bch3121decp$1217
+A$bch3121decp$1181
+A$bch3121decp$1236
+A$bch3121decp$1227
+A$bch3121decp$1218
+A$bch3121decp$1209
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+A$bch3121decp$1246
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+A$bch3121decp$1183
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+A$bch3121decp$1187
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+A$bch3121decp$1199
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+C$bch3121decp.c$12$1$33
+
+
+
+bch3121enc 2327498
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+_PCON
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+_ANALOGA
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+_ADCTUNE1
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+_T1PERIOD0
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+_T2PERIOD0
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+_PINC_0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
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+_PSW
+_ADCCH1CONFIG
+_CLKCON
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_SCRATCH3
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+_RADIODATA2
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+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINC_3
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+_RADIOFSTATADDR1
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+_INTCHGA
+_SILICONREV
+_ADCCONV
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+_INTCHGB
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+_WDTCFG
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+.__.ABS.
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+_INTCHGC
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+_WTCNTA0
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+G$IE$0$0
+_B
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+_PORTA
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+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
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+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
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+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
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+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$bch3121enc$1219
+A$bch3121enc$1192
+A$bch3121enc$1193
+A$bch3121enc$1184
+A$bch3121enc$1194
+A$bch3121enc$1185
+A$bch3121enc$1195
+A$bch3121enc$1196
+A$bch3121enc$1197
+A$bch3121enc$1188
+A$bch3121enc$1179
+A$bch3121enc$1198
+A$bch3121enc$1189
+A$bch3121enc$1199
+G$bch3121_encode$0$0
+C$bch3121enc.c$6$1$33
+C$bch3121enc.c$7$1$33
+C$bch3121enc.c$8$1$33
+C$bch3121enc.c$9$1$33
+_bch3121_encode
+C$bch3121enc.c$4$0$0
+XG$bch3121_encode$0$0
+A$bch3121enc$1200
+A$bch3121enc$1210
+A$bch3121enc$1201
+A$bch3121enc$1220
+A$bch3121enc$1211
+A$bch3121enc$1202
+A$bch3121enc$1230
+A$bch3121enc$1221
+A$bch3121enc$1212
+A$bch3121enc$1203
+A$bch3121enc$1213
+A$bch3121enc$1204
+A$bch3121enc$1214
+A$bch3121enc$1205
+A$bch3121enc$1224
+A$bch3121enc$1215
+A$bch3121enc$1206
+A$bch3121enc$1225
+A$bch3121enc$1216
+A$bch3121enc$1207
+A$bch3121enc$1180
+A$bch3121enc$1226
+A$bch3121enc$1217
+A$bch3121enc$1208
+A$bch3121enc$1190
+A$bch3121enc$1181
+A$bch3121enc$1227
+A$bch3121enc$1218
+A$bch3121enc$1209
+A$bch3121enc$1191
+
+
+
+bch3121encp 2359590
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
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+
+
+
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+
+
+bch3121syn 2405169
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+
+
+
+wrnum16 2437338
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+
+
+
+wrnum32 2442449
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+
+
+
+offxosc 2449011
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+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
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+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$offxosc$1200
+A$offxosc$1210
+A$offxosc$1201
+A$offxosc$1202
+A$offxosc$1203
+A$offxosc$1240
+A$offxosc$1231
+A$offxosc$1222
+A$offxosc$1213
+A$offxosc$1204
+A$offxosc$1241
+A$offxosc$1223
+A$offxosc$1205
+A$offxosc$1260
+A$offxosc$1242
+A$offxosc$1224
+A$offxosc$1270
+A$offxosc$1261
+A$offxosc$1243
+A$offxosc$1234
+A$offxosc$1216
+A$offxosc$1280
+A$offxosc$1271
+A$offxosc$1244
+A$offxosc$1208
+A$offxosc$1190
+A$offxosc$1272
+A$offxosc$1254
+A$offxosc$1245
+A$offxosc$1227
+A$offxosc$1209
+A$offxosc$1191
+A$offxosc$1264
+A$offxosc$1237
+A$offxosc$1228
+A$offxosc$1219
+A$offxosc$1192
+A$offxosc$1193
+A$offxosc$1184
+A$offxosc$1275
+A$offxosc$1257
+A$offxosc$1248
+A$offxosc$1185
+A$offxosc$1276
+A$offxosc$1267
+A$offxosc$1258
+A$offxosc$1186
+A$offxosc$1259
+A$offxosc$1196
+A$offxosc$1187
+G$turn_off_xosc$0$0
+A$offxosc$1188
+C$offxosc.c$20$1$33
+C$offxosc.c$30$1$33
+C$offxosc.c$21$1$33
+C$offxosc.c$12$1$33
+C$offxosc.c$31$1$33
+C$offxosc.c$22$1$33
+C$offxosc.c$13$1$33
+C$offxosc.c$32$1$33
+C$offxosc.c$23$1$33
+C$offxosc.c$14$1$33
+C$offxosc.c$33$1$33
+C$offxosc.c$24$1$33
+C$offxosc.c$15$1$33
+C$offxosc.c$25$1$33
+C$offxosc.c$16$1$33
+C$offxosc.c$26$1$33
+C$offxosc.c$17$1$33
+C$offxosc.c$18$1$33
+C$offxosc.c$28$1$33
+C$offxosc.c$19$1$33
+C$offxosc.c$29$1$33
+C$offxosc.c$27$2$34
+_turn_off_xosc
+XG$turn_off_xosc$0$0
+C$offxosc.c$8$0$0
+
+
+
+offlpxosc 2481955
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
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+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
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+G$PINA_5$0$0
+G$WTCFGA$0$0
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+G$ADCCH3CONFIG$0$0
+_PCON
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+G$U0SHREG$0$0
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+G$ADCCONV$0$0
+_PALTA
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+_EIP_5
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+G$PINC_6$0$0
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
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+_DMA1CONFIG
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+_ADCCH0CONFIG
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+_T1PERIOD1
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+_FRCOSCKFILT
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+_T2PERIOD1
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+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
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+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
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+_PINC_5
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+_INTCHGB
+_NVADDR
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+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTA1$0$0
+_INTCHGC
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+G$WTEVTC0$0$0
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+G$IE$0$0
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+_EA
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+G$EIE$0$0
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+_T0PERIOD
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
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+_T1PERIOD
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+G$RS0$0$0
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+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
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+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
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+_WTEVTB1
+_WTEVTC0
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+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
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+G$T0CNT1$0$0
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+G$WTEVTA$0$0
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+G$T1CNT1$0$0
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+_DMA1ADDR1
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+G$SPSHREG$0$0
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+_E2IP
+_P
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+_DPL1
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+_EIE
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+__XPAGE
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+_IC0CAPT1
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+_ADCCH0VAL0
+_GPIOENABLE
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+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
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+_PORTR
+_ACC_1
+_B_6
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+_ADCCH1VAL1
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+_ACC_2
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+_PORTB_2
+_PORTC_1
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+G$SPCLKSRC$0$0
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+_ADCCH2VAL1
+_ADCCH3VAL0
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+_E2IE_5
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+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+G$EIE_5$0$0
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
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+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
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+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
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+G$WTIRQEN$0$0
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+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
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+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$turn_off_lpxosc$0$0
+C$offlpxosc.c$8$0$0
+A$offlpxosc$1200
+A$offlpxosc$1210
+A$offlpxosc$1201
+A$offlpxosc$1202
+A$offlpxosc$1203
+A$offlpxosc$1231
+A$offlpxosc$1222
+A$offlpxosc$1213
+A$offlpxosc$1204
+A$offlpxosc$1232
+A$offlpxosc$1205
+A$offlpxosc$1233
+A$offlpxosc$1252
+A$offlpxosc$1234
+A$offlpxosc$1225
+A$offlpxosc$1216
+A$offlpxosc$1280
+A$offlpxosc$1262
+A$offlpxosc$1253
+A$offlpxosc$1235
+A$offlpxosc$1208
+A$offlpxosc$1190
+A$offlpxosc$1272
+A$offlpxosc$1263
+A$offlpxosc$1254
+A$offlpxosc$1245
+A$offlpxosc$1236
+A$offlpxosc$1209
+A$offlpxosc$1191
+A$offlpxosc$1264
+A$offlpxosc$1255
+A$offlpxosc$1228
+A$offlpxosc$1219
+A$offlpxosc$1192
+A$offlpxosc$1265
+A$offlpxosc$1256
+A$offlpxosc$1193
+A$offlpxosc$1184
+A$offlpxosc$1275
+A$offlpxosc$1266
+A$offlpxosc$1239
+A$offlpxosc$1185
+A$offlpxosc$1276
+A$offlpxosc$1249
+A$offlpxosc$1186
+A$offlpxosc$1259
+A$offlpxosc$1196
+A$offlpxosc$1187
+G$turn_off_lpxosc$0$0
+A$offlpxosc$1269
+A$offlpxosc$1188
+C$offlpxosc.c$20$1$33
+C$offlpxosc.c$30$1$33
+C$offlpxosc.c$21$1$33
+C$offlpxosc.c$12$1$33
+C$offlpxosc.c$31$1$33
+C$offlpxosc.c$22$1$33
+C$offlpxosc.c$13$1$33
+C$offlpxosc.c$32$1$33
+C$offlpxosc.c$23$1$33
+C$offlpxosc.c$14$1$33
+C$offlpxosc.c$33$1$33
+C$offlpxosc.c$24$1$33
+C$offlpxosc.c$15$1$33
+C$offlpxosc.c$34$1$33
+C$offlpxosc.c$16$1$33
+C$offlpxosc.c$25$2$33
+C$offlpxosc.c$17$1$33
+C$offlpxosc.c$18$1$33
+C$offlpxosc.c$19$1$33
+_turn_off_lpxosc
+C$offlpxosc.c$28$2$34
+C$offlpxosc.c$29$2$34
+C$offlpxosc.c$27$3$35
+
+
+
+setuplpxosc 2515056
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
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+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
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+_IE_6
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+_IC0CAPT
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+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
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+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
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+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
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+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+G$PINA_5$0$0
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+G$ADCCH3CONFIG$0$0
+_PCON
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+G$PINC_4$0$0
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+_T2PERIOD1
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+_RADIODATA2
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+_RADIODATA3
+_WTCFGA
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+_RADIOFSTATADDR1
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+_INTCHGA
+_SILICONREV
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+_INTCHGB
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+.__.ABS.
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+G$IE$0$0
+_B
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+G$DBGLNKBUF$0$0
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+G$E2IP$0$0
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+G$WTCNTB$0$0
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+_EA
+G$B_2$0$0
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+G$EIE$0$0
+_ACC
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+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
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+_T1PERIOD
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+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
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+G$PORTA_4$0$0
+G$E2IE_5$0$0
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+G$T1CNT0$0$0
+G$T0CNT1$0$0
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+_DMA1ADDR1
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+_E2IP
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+G$WTEVTC$0$0
+_DPL1
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+_EIE
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+__XPAGE
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+_ADCCH0VAL0
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+_E2IE_2
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+_ADCCH2VAL1
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+_RADIOFDATAADDR1
+_RADIOSTAT0
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+_WTEVTA
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+_DPH
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_IE_0
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+G$OC1PIN$0$0
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+_DMA1ADDR
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+_LPOSCREF
+_XTALOSC
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+_IE_1
+_PORTC_7
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+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$setuplpxosc.c$8$0$0
+_setup_lpxosc
+XG$setup_lpxosc$0$0
+A$setuplpxosc$1202
+A$setuplpxosc$1180
+A$setuplpxosc$1190
+A$setuplpxosc$1181
+A$setuplpxosc$1182
+A$setuplpxosc$1183
+A$setuplpxosc$1193
+A$setuplpxosc$1184
+A$setuplpxosc$1194
+A$setuplpxosc$1176
+A$setuplpxosc$1195
+A$setuplpxosc$1196
+A$setuplpxosc$1187
+A$setuplpxosc$1197
+A$setuplpxosc$1179
+A$setuplpxosc$1198
+C$setuplpxosc.c$10$1$33
+A$setuplpxosc$1199
+C$setuplpxosc.c$11$1$33
+C$setuplpxosc.c$12$1$33
+C$setuplpxosc.c$13$1$33
+C$setuplpxosc.c$14$1$33
+G$setup_lpxosc$0$0
+
+
+
+setupxosc 2545927
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+_DIRC
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+_OC1COMP0
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+G$NVADDR0$0$0
+_XTALAMPL
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+_IE_6
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+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
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+_IE_7
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+_IC1CAPT
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+_E2IP_6
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+_ADCCH2VAL
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+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
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+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
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+G$F0$0$0
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
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+G$F1$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
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+G$PINB_1$0$0
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+G$T1PERIOD1$0$0
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+_LPXOSCGM
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+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
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+
+
+
+setupcal 2576738
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+
+
+
+wtcbadd 2729743
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+_RADIODATA2
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+.__.ABS.
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+_EA
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+_OSCFORCERUN
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+_ADCCLKSRC
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+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
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+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
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+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
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+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
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+_B_2
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+G$IE_3$0$0
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+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
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+_B_3
+_E2IE_0
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+G$E2IP_2$0$0
+G$OC0COMP0$0$0
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+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$EIE_0$0$0
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+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
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+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_wtimer_add_callback
+C$wtcbadd.c$4$0$0
+C$wtcbadd.c$6$1$59
+C$wtcbadd.c$7$1$59
+C$wtcbadd.c$8$1$59
+C$wtcbadd.c$9$1$59
+XG$wtimer_add_callback$0$0
+A$wtcbadd$1200
+A$wtcbadd$1203
+A$wtcbadd$1180
+A$wtcbadd$1181
+A$wtcbadd$1192
+A$wtcbadd$1193
+A$wtcbadd$1184
+A$wtcbadd$1194
+A$wtcbadd$1185
+A$wtcbadd$1195
+A$wtcbadd$1186
+A$wtcbadd$1196
+A$wtcbadd$1189
+A$wtcbadd$1199
+C$wtcbadd.c$10$1$59
+G$wtimer_add_callback$0$0
+
+
+
+wtcbrem 2762318
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
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+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
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+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
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+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
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+G$PINCHGC$0$0
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+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
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+_PCON
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+G$PINB_5$0$0
+G$PINA_6$0$0
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+_DIRR
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+G$ADCCONV$0$0
+_PALTA
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+_WDTRESET
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+_ANALOGA
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+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
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+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$wtcbrem$1202
+A$wtcbrem$1203
+A$wtcbrem$1206
+A$wtcbrem$1209
+A$wtcbrem$1191
+A$wtcbrem$1182
+A$wtcbrem$1183
+A$wtcbrem$1194
+A$wtcbrem$1195
+A$wtcbrem$1186
+A$wtcbrem$1196
+A$wtcbrem$1187
+A$wtcbrem$1197
+A$wtcbrem$1188
+A$wtcbrem$1198
+A$wtcbrem$1199
+C$wtcbrem.c$10$1$59
+C$wtcbrem.c$11$1$59
+C$wtcbrem.c$12$1$59
+C$wtcbrem.c$13$1$59
+G$wtimer_remove_callback$0$0
+C$wtcbrem.c$4$0$0
+C$wtcbrem.c$8$1$59
+C$wtcbrem.c$9$1$59
+_wtimer_remove_callback
+XG$wtimer_remove_callback$0$0
+
+
+
+wt0setcfg 2795169
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_wtimer0_setconfig
+C$wt0setcfg.c$4$0$0
+C$wt0setcfg.c$6$1$59
+C$wt0setcfg.c$7$1$59
+C$wt0setcfg.c$8$1$59
+C$wt0setcfg.c$9$1$59
+XG$wtimer0_setconfig$0$0
+A$wt0setcfg$1211
+A$wt0setcfg$1202
+A$wt0setcfg$1203
+A$wt0setcfg$1204
+A$wt0setcfg$1207
+A$wt0setcfg$1180
+A$wt0setcfg$1181
+A$wt0setcfg$1182
+A$wt0setcfg$1183
+A$wt0setcfg$1193
+A$wt0setcfg$1184
+A$wt0setcfg$1185
+A$wt0setcfg$1196
+A$wt0setcfg$1189
+A$wt0setcfg$1199
+C$wt0setcfg.c$10$1$59
+C$wt0setcfg.c$11$1$59
+G$wtimer0_setconfig$0$0
+C$wt0setcfg.c$12$1$59
+C$wt0setcfg.c$13$1$59
+
+
+
+wt1setcfg 2827959
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
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+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_wtimer1_setconfig
+C$wt1setcfg.c$4$0$0
+C$wt1setcfg.c$6$1$59
+C$wt1setcfg.c$7$1$59
+C$wt1setcfg.c$8$1$59
+C$wt1setcfg.c$9$1$59
+XG$wtimer1_setconfig$0$0
+A$wt1setcfg$1211
+A$wt1setcfg$1202
+A$wt1setcfg$1203
+A$wt1setcfg$1204
+A$wt1setcfg$1207
+A$wt1setcfg$1180
+A$wt1setcfg$1181
+A$wt1setcfg$1182
+A$wt1setcfg$1183
+A$wt1setcfg$1193
+A$wt1setcfg$1184
+A$wt1setcfg$1185
+A$wt1setcfg$1196
+A$wt1setcfg$1189
+A$wt1setcfg$1199
+C$wt1setcfg.c$10$1$59
+C$wt1setcfg.c$11$1$59
+G$wtimer1_setconfig$0$0
+C$wt1setcfg.c$12$1$59
+C$wt1setcfg.c$13$1$59
+
+
+
+wtstdby 2860749
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
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+
+
+
+wt0adda 2890996
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+_CY
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+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
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+
+
+
+wt0addr 2957062
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+
+
+
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+_wtimer1_curtime
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+
+
+
+wt0rem 3090532
+G$LPXOSCGM$0$0
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+_OV
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+
+
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+
+
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+_LPOSCKFILT1
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+
+
+
+radiord24 3223512
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+_MISCCTRL
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+_DIRB
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+_FRCOSCFREQ
+_XTALREADY
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+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
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+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+G$ADCCH3CONFIG$0$0
+_PCON
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+_T2PERIOD1
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+_OSCFORCERUN
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+_PALTRADIO
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+
+
+
+radiord32 3255826
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
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+_OC0COMP0
+_E2IP_2
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+_IE_7
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+_U1STATUS
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+G$CLKCON$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+_IP_6
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+_LPOSCFREQ
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+_PCON
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+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
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+G$INTCHGC$0$0
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+_ADCTUNE0
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+_ADCTUNE1
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+_ADCTUNE2
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+_F1
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+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
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+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
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+_FRCOSCKFILT
+_PINCHGA
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+_PSW
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+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINB_2
+_PINC_1
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+G$ACC$0$0
+_PINCHGB
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+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
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+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINC_3
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+_RADIOFSTATADDR1
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+_EA
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+_ACC
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+_OSCFORCERUN
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+__XPAGE
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+_EXTIRQ
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+G$DPTR0$0$0
+_DMA1ADDR
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+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
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+_FRCOSCFREQ1
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+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
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+_IE_3
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+_radio_read32
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+A$radiord32$1180
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+
+
+
+radiowr16 3288111
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$IP_7$0$0
+G$EIP_2$0$0
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+G$NVADDR0$0$0
+_XTALAMPL
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+_EIE_1
+_IE_6
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+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
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+_EIE_2
+_IE_7
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+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
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+_OV
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+_ADCCH0VAL
+_OC0STATUS
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+_ADCCH1VAL
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+_ADCCH2VAL
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+G$XPAGE$0$0
+_ADCCH3VAL
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+_EIE_7
+_IP_1
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+_FRCOSCKFILT0
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+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
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+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
+_U1MODE
+_IP_3
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+_LPOSCKFILT1
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+_LPXOSCGM
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+G$RADIOADDR0$0$0
+G$CLKCON$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
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+_IP_6
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
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+_IP_7
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+_PCON
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+_PALTA
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+_ADCTUNE0
+_PALTC
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
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+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+_FRCOSCKFILT
+_PINCHGA
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+_CLKCON
+_RADIOADDR0
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+_T2PERIOD1
+_U0CTRL
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+_PINC_1
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+_RADIOADDR1
+_RADIODATA2
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+.__.ABS.
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+_OSCFORCERUN
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+_DPL1
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+__XPAGE
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+_ADCCH0VAL0
+_GPIOENABLE
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+_E2IP_0
+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$radiowr16.c$45$1$64
+C$radiowr16.c$46$1$64
+G$radio_write16$0$0
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+_radio_write16
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+A$radiowr16$1189
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+
+
+
+radiowr24 3320632
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
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+_IE_4
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+_ADCCH2VAL
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$B$0$0
+_ADCTUNE2
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+_F1
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+_T1PERIOD0
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+_DMA1CONFIG
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+_ADCCH0CONFIG
+_PINR
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+_T2PERIOD0
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+_PINC_0
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+_FRCOSCKFILT
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+_SCRATCH2
+_PSW
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+_CLKCON
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINB_2
+_PINC_1
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+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
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+
+
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+_RADIODATA3
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+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+
+
+
+radiodswakecore 3385875
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+_AX5043_BBOFFSRES1NB
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+_AX5043_0xF00NB
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+_DIRC
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+_AX5043_FREQUENCYLEAKNB
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+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
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+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
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+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
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+_ADCCH2VAL
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+G$XWTEVTC$0$0
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+G$XPAGE$0$0
+_ADCCH3VAL
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+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
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+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
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+
+
+
+ax5031comminit 3491247
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+_AX5031_TXBITRATEMIDNB
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+_WTSTAT
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+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
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+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
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+_DPTR1
+_RADIOSTAT
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+G$PSW$0$0
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+G$RADIOADDR1$0$0
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+_LPOSCFREQ
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+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
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+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
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+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
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+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
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+G$INTCHGB$0$0
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+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
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+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
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+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
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+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
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+_AX5031_TXPWRNB
+_RADIOACC
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+G$AC$0$0
+_DMA0CONFIG
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+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
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+G$EA$0$0
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+G$PORTA$0$0
+_FRCOSCKFILT
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+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
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+G$AX5031_ENCODING$0$0
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+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
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+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
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+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
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+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
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+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
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+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
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+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
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+_WTEVTB
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+_CY
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+
+
+
+ax5031commslpexit 3533950
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
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+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
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+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
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+_AX5031_MODULATORMISC
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+G$PALTA$0$0
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+G$WDTRESET$0$0
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+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
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+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5031_FSKDEV0$0$0
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+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
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+_WTIRQEN
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+G$T0PERIOD0$0$0
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+_LPOSCKFILT0
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+_RADIOSTAT
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+_T2MODE
+_U1MODE
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+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+_DBGLNKSTAT
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
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+G$WTCFGA$0$0
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+_AX5031_FREQA0NB
+_PCON
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+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
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+G$AX5031_CRCINIT1$0$0
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+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
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+G$AC$0$0
+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
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+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
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+_PINR
+_RADIODATA0
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+_T2PERIOD0
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+G$EA$0$0
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+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
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+_RADIODATA1
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+G$PORTB$0$0
+G$ACC$0$0
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+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
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+G$AX5031_ENCODING$0$0
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+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
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+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
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+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031commslpexit.c$8$0$0
+G$ax5031_commsleepexit$0$0
+_ax5031_commsleepexit
+XG$ax5031_commsleepexit$0$0
+A$ax5031commslpexit$1470
+A$ax5031commslpexit$1461
+A$ax5031commslpexit$1480
+A$ax5031commslpexit$1471
+A$ax5031commslpexit$1490
+A$ax5031commslpexit$1481
+A$ax5031commslpexit$1472
+A$ax5031commslpexit$1491
+A$ax5031commslpexit$1482
+A$ax5031commslpexit$1464
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+A$ax5031commslpexit$1475
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+A$ax5031commslpexit$1467
+A$ax5031commslpexit$1486
+A$ax5031commslpexit$1468
+A$ax5031commslpexit$1487
+A$ax5031commslpexit$1478
+A$ax5031commslpexit$1469
+A$ax5031commslpexit$1497
+A$ax5031commslpexit$1488
+A$ax5031commslpexit$1479
+A$ax5031commslpexit$1489
+C$ax5031commslpexit.c$10$1$66
+C$ax5031commslpexit.c$11$1$66
+C$ax5031commslpexit.c$12$1$66
+C$ax5031commslpexit.c$13$1$66
+C$ax5031commslpexit.c$24$1$66
+C$ax5031commslpexit.c$15$1$66
+C$ax5031commslpexit.c$25$1$66
+C$ax5031commslpexit.c$16$1$66
+
+
+
+ax5031reset 3576854
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031reset.c$8$0$0
+_ax5031_reset
+_ax5031_probeirq
+XG$ax5031_reset$0$0
+XG$ax5031_probeirq$0$0
+A$ax5031reset$1500
+A$ax5031reset$1501
+A$ax5031reset$1700
+A$ax5031reset$1610
+A$ax5031reset$1601
+A$ax5031reset$1520
+A$ax5031reset$1620
+A$ax5031reset$1611
+A$ax5031reset$1530
+A$ax5031reset$1521
+A$ax5031reset$1512
+A$ax5031reset$1630
+A$ax5031reset$1621
+A$ax5031reset$1612
+A$ax5031reset$1531
+A$ax5031reset$1513
+A$ax5031reset$1504
+A$ax5031reset$1703
+A$ax5031reset$1640
+A$ax5031reset$1631
+A$ax5031reset$1622
+A$ax5031reset$1604
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+
+
+
+ax5031deepsleep 3625777
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
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+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
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+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
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+G$NVDATA1$0$0
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+_XTALAMPL
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+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
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+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
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+_OV
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+_ADCCH0VAL
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+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
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+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5031_FSKDEV0$0$0
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+G$ADCTUNE0$0$0
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+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
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+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
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+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+G$SCRATCH1$0$0
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+_LPXOSCGM
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+G$PINA_3$0$0
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+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
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+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
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+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5031rclkena 3667007
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
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+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+_PINC_7
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+G$FRCOSCREF0$0$0
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+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
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+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
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+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
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+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
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+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
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+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
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+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
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+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
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+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$CLKSTAT$0$0
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+G$ADCCH0VAL1$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
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+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$PORTA_4$0$0
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+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
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+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
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+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
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+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
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+G$T2CNT1$0$0
+G$SPSHREG$0$0
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+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
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+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
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+G$PORTC_7$0$0
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+_AX5031_TXBITRATEMID
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+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
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+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
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+G$IE_4$0$0
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+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
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+G$DIRB$0$0
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+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
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+G$AX5031_FREQA2$0$0
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+G$OC0COMP1$0$0
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+_ADCCH0VAL0
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+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+G$AX5031_PLLLOOP$0$0
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+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
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+G$EIE_1$0$0
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+G$SP$0$0
+_ADCCH0VAL1
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+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
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+_PORTB_2
+_PORTC_1
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+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
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+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
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+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
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+_E2IE_6
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
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+_DPH
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+_CY
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+G$OC0PIN$0$0
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+_EXTIRQ
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+_AX5031_XTALOSC
+_AX5031_FECNB
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+_IE_2
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+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5031_rclk_enable$0$0
+A$ax5031rclkena$1500
+A$ax5031rclkena$1501
+_ax5031_rclk_enable
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+A$ax5031rclkena$1479
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+C$ax5031rclkena.c$11$1$64
+C$ax5031rclkena.c$12$1$64
+C$ax5031rclkena.c$13$1$64
+C$ax5031rclkena.c$14$1$64
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+C$ax5031rclkena.c$16$1$64
+C$ax5031rclkena.c$17$1$64
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+C$ax5031rclkena.c$19$1$64
+C$ax5031rclkena.c$8$1$64
+C$ax5031rclkena.c$9$1$64
+C$ax5031rclkena.c$5$0$0
+
+
+
+ax5031rclkdis 3710594
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+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$XTALREADY$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
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+_XTALAMPL
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+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
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+_EIE_1
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+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031rclkdis.c$8$1$64
+C$ax5031rclkdis.c$9$1$64
+C$ax5031rclkdis.c$5$0$0
+XG$ax5031_rclk_disable$0$0
+A$ax5031rclkdis$1501
+A$ax5031rclkdis$1502
+A$ax5031rclkdis$1505
+A$ax5031rclkdis$1480
+A$ax5031rclkdis$1471
+A$ax5031rclkdis$1490
+A$ax5031rclkdis$1463
+A$ax5031rclkdis$1491
+A$ax5031rclkdis$1464
+A$ax5031rclkdis$1483
+A$ax5031rclkdis$1474
+A$ax5031rclkdis$1465
+A$ax5031rclkdis$1484
+A$ax5031rclkdis$1475
+A$ax5031rclkdis$1494
+A$ax5031rclkdis$1485
+A$ax5031rclkdis$1476
+A$ax5031rclkdis$1495
+A$ax5031rclkdis$1477
+A$ax5031rclkdis$1468
+A$ax5031rclkdis$1496
+A$ax5031rclkdis$1478
+A$ax5031rclkdis$1497
+A$ax5031rclkdis$1488
+A$ax5031rclkdis$1479
+A$ax5031rclkdis$1489
+C$ax5031rclkdis.c$10$1$64
+C$ax5031rclkdis.c$11$1$64
+C$ax5031rclkdis.c$12$1$64
+C$ax5031rclkdis.c$13$1$64
+C$ax5031rclkdis.c$14$1$64
+C$ax5031rclkdis.c$15$1$64
+G$ax5031_rclk_disable$0$0
+C$ax5031rclkdis.c$16$1$64
+_ax5031_rclk_disable
+
+
+
+ax5031rdfifo 3753542
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
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+G$SPSHREG$0$0
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+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
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+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
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+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
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+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
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+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
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+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
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+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031rdfifo.c$10$0$0
+C$ax5031rdfifo.c$74$1$66
+C$ax5031rdfifo.c$75$1$66
+G$ax5031_readfifo$0$0
+_ax5031_readfifo
+A$ax5031rdfifo$1500
+A$ax5031rdfifo$1510
+A$ax5031rdfifo$1501
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+
+
+
+ax5031wrfifo 3797479
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5031wrfifo$1511
+A$ax5031wrfifo$1502
+A$ax5031wrfifo$1512
+A$ax5031wrfifo$1503
+A$ax5031wrfifo$1513
+A$ax5031wrfifo$1504
+A$ax5031wrfifo$1514
+A$ax5031wrfifo$1505
+A$ax5031wrfifo$1460
+A$ax5031wrfifo$1515
+A$ax5031wrfifo$1506
+A$ax5031wrfifo$1470
+A$ax5031wrfifo$1461
+A$ax5031wrfifo$1516
+A$ax5031wrfifo$1480
+A$ax5031wrfifo$1471
+A$ax5031wrfifo$1462
+A$ax5031wrfifo$1508
+A$ax5031wrfifo$1481
+A$ax5031wrfifo$1472
+A$ax5031wrfifo$1463
+A$ax5031wrfifo$1509
+A$ax5031wrfifo$1491
+A$ax5031wrfifo$1464
+A$ax5031wrfifo$1492
+A$ax5031wrfifo$1483
+A$ax5031wrfifo$1474
+A$ax5031wrfifo$1465
+A$ax5031wrfifo$1493
+A$ax5031wrfifo$1484
+A$ax5031wrfifo$1466
+A$ax5031wrfifo$1457
+A$ax5031wrfifo$1494
+A$ax5031wrfifo$1485
+A$ax5031wrfifo$1467
+A$ax5031wrfifo$1458
+A$ax5031wrfifo$1495
+A$ax5031wrfifo$1486
+A$ax5031wrfifo$1477
+A$ax5031wrfifo$1459
+A$ax5031wrfifo$1496
+A$ax5031wrfifo$1487
+A$ax5031wrfifo$1478
+A$ax5031wrfifo$1469
+A$ax5031wrfifo$1497
+A$ax5031wrfifo$1488
+A$ax5031wrfifo$1479
+A$ax5031wrfifo$1498
+A$ax5031wrfifo$1489
+C$ax5031wrfifo.c$10$0$0
+C$ax5031wrfifo.c$75$1$66
+C$ax5031wrfifo.c$76$1$66
+G$ax5031_writefifo$0$0
+_ax5031_writefifo
+XG$ax5031_writefifo$0$0
+A$ax5031wrfifo$1500
+A$ax5031wrfifo$1510
+A$ax5031wrfifo$1501
+
+
+
+ax5031regs 3841491
+.__.ABS.
+
+
+
+ax5042comminit 3842529
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
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+_RADIODATA1
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+_U0CTRL
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+G$PORTB$0$0
+G$ACC$0$0
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+_SCRATCH3
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+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
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+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
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+G$ADCCLKSRC$0$0
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+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
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+_AX5042_CICDECHINB
+_NVADDR
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+_WDTCFG
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+.__.ABS.
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+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042commslpexit.c$24$1$66
+C$ax5042commslpexit.c$15$1$66
+C$ax5042commslpexit.c$25$1$66
+C$ax5042commslpexit.c$16$1$66
+C$ax5042commslpexit.c$8$0$0
+G$ax5042_commsleepexit$0$0
+_ax5042_commsleepexit
+A$ax5042commslpexit$1600
+A$ax5042commslpexit$1610
+A$ax5042commslpexit$1601
+A$ax5042commslpexit$1620
+A$ax5042commslpexit$1611
+A$ax5042commslpexit$1602
+A$ax5042commslpexit$1621
+A$ax5042commslpexit$1612
+A$ax5042commslpexit$1603
+A$ax5042commslpexit$1622
+A$ax5042commslpexit$1613
+A$ax5042commslpexit$1604
+XG$ax5042_commsleepexit$0$0
+A$ax5042commslpexit$1623
+A$ax5042commslpexit$1614
+A$ax5042commslpexit$1615
+A$ax5042commslpexit$1607
+A$ax5042commslpexit$1626
+A$ax5042commslpexit$1618
+A$ax5042commslpexit$1619
+A$ax5042commslpexit$1629
+A$ax5042commslpexit$1593
+A$ax5042commslpexit$1596
+A$ax5042commslpexit$1599
+C$ax5042commslpexit.c$10$1$66
+C$ax5042commslpexit.c$11$1$66
+C$ax5042commslpexit.c$12$1$66
+C$ax5042commslpexit.c$13$1$66
+
+
+
+ax5042reset 3937952
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
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+G$AX5042_FREQUENCYGAINNB$0$0
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+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
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+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
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+_PORTC_3
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+G$WTSTAT$0$0
+G$OC1STATUS$0$0
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+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
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+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
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+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
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+_PORTB_7
+_PORTC_6
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+G$AX5042_TRKAMPLITUDEHI$0$0
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+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
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+_DMA1ADDR
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+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
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+G$AX5042_IRQMASKNB$0$0
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+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
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+G$T2CNT$0$0
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+_FRCOSCFREQ1
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+_AX5042_DSPMODENB
+_E2IP_0
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+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
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+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042reset.c$8$0$0
+_ax5042_reset
+_ax5042_probeirq
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+C$ax5042reset.c$20$1$66
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+C$ax5042reset.c$94$2$69
+C$ax5042reset.c$78$1$68
+G$ax5042_reset$0$0
+C$ax5042reset.c$97$1$68
+C$ax5042reset.c$86$2$69
+C$ax5042reset.c$79$1$68
+G$ax5042_probeirq$0$0
+C$ax5042reset.c$98$1$68
+C$ax5042reset.c$87$2$69
+C$ax5042reset.c$99$1$68
+C$ax5042reset.c$88$2$69
+
+
+
+ax5042deepsleep 3992336
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
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+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5042rclkena 4038474
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5042_rclk_enable$0$0
+_ax5042_rclk_enable
+A$ax5042rclkena$1620
+A$ax5042rclkena$1611
+A$ax5042rclkena$1602
+A$ax5042rclkena$1621
+A$ax5042rclkena$1612
+A$ax5042rclkena$1622
+A$ax5042rclkena$1613
+A$ax5042rclkena$1650
+A$ax5042rclkena$1632
+A$ax5042rclkena$1623
+A$ax5042rclkena$1633
+A$ax5042rclkena$1624
+A$ax5042rclkena$1606
+A$ax5042rclkena$1643
+A$ax5042rclkena$1625
+A$ax5042rclkena$1616
+A$ax5042rclkena$1607
+A$ax5042rclkena$1653
+A$ax5042rclkena$1644
+A$ax5042rclkena$1626
+A$ax5042rclkena$1608
+A$ax5042rclkena$1645
+A$ax5042rclkena$1636
+A$ax5042rclkena$1637
+A$ax5042rclkena$1619
+A$ax5042rclkena$1638
+A$ax5042rclkena$1629
+A$ax5042rclkena$1639
+A$ax5042rclkena$1594
+XG$ax5042_rclk_enable$0$0
+A$ax5042rclkena$1649
+A$ax5042rclkena$1597
+C$ax5042rclkena.c$10$1$64
+A$ax5042rclkena$1599
+C$ax5042rclkena.c$11$1$64
+C$ax5042rclkena.c$12$1$64
+C$ax5042rclkena.c$13$1$64
+C$ax5042rclkena.c$14$1$64
+C$ax5042rclkena.c$15$1$64
+C$ax5042rclkena.c$16$1$64
+C$ax5042rclkena.c$17$1$64
+C$ax5042rclkena.c$18$1$64
+C$ax5042rclkena.c$19$1$64
+C$ax5042rclkena.c$8$1$64
+C$ax5042rclkena.c$9$1$64
+C$ax5042rclkena.c$5$0$0
+
+
+
+ax5042rclkdis 4086891
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5042_rclk_disable
+C$ax5042rclkdis.c$8$1$64
+C$ax5042rclkdis.c$9$1$64
+C$ax5042rclkdis.c$5$0$0
+XG$ax5042_rclk_disable$0$0
+A$ax5042rclkdis$1600
+A$ax5042rclkdis$1610
+A$ax5042rclkdis$1620
+A$ax5042rclkdis$1611
+A$ax5042rclkdis$1621
+A$ax5042rclkdis$1612
+A$ax5042rclkdis$1603
+A$ax5042rclkdis$1622
+A$ax5042rclkdis$1632
+A$ax5042rclkdis$1633
+A$ax5042rclkdis$1615
+A$ax5042rclkdis$1606
+A$ax5042rclkdis$1616
+A$ax5042rclkdis$1607
+A$ax5042rclkdis$1626
+A$ax5042rclkdis$1608
+A$ax5042rclkdis$1636
+A$ax5042rclkdis$1627
+A$ax5042rclkdis$1609
+A$ax5042rclkdis$1628
+A$ax5042rclkdis$1619
+A$ax5042rclkdis$1595
+A$ax5042rclkdis$1596
+A$ax5042rclkdis$1597
+C$ax5042rclkdis.c$10$1$64
+C$ax5042rclkdis.c$11$1$64
+C$ax5042rclkdis.c$12$1$64
+C$ax5042rclkdis.c$13$1$64
+C$ax5042rclkdis.c$14$1$64
+C$ax5042rclkdis.c$15$1$64
+G$ax5042_rclk_disable$0$0
+C$ax5042rclkdis.c$16$1$64
+
+
+
+ax5042rdfifo 4134700
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042rdfifo.c$10$0$0
+C$ax5042rdfifo.c$74$1$66
+C$ax5042rdfifo.c$75$1$66
+G$ax5042_readfifo$0$0
+_ax5042_readfifo
+XG$ax5042_readfifo$0$0
+A$ax5042rdfifo$1610
+A$ax5042rdfifo$1601
+A$ax5042rdfifo$1620
+A$ax5042rdfifo$1611
+A$ax5042rdfifo$1602
+A$ax5042rdfifo$1630
+A$ax5042rdfifo$1621
+A$ax5042rdfifo$1612
+A$ax5042rdfifo$1603
+A$ax5042rdfifo$1640
+A$ax5042rdfifo$1613
+A$ax5042rdfifo$1604
+A$ax5042rdfifo$1632
+A$ax5042rdfifo$1623
+A$ax5042rdfifo$1642
+A$ax5042rdfifo$1633
+A$ax5042rdfifo$1624
+A$ax5042rdfifo$1615
+A$ax5042rdfifo$1606
+A$ax5042rdfifo$1643
+A$ax5042rdfifo$1634
+A$ax5042rdfifo$1625
+A$ax5042rdfifo$1616
+A$ax5042rdfifo$1644
+A$ax5042rdfifo$1635
+A$ax5042rdfifo$1626
+A$ax5042rdfifo$1617
+A$ax5042rdfifo$1590
+A$ax5042rdfifo$1645
+A$ax5042rdfifo$1636
+A$ax5042rdfifo$1627
+A$ax5042rdfifo$1618
+A$ax5042rdfifo$1609
+A$ax5042rdfifo$1591
+A$ax5042rdfifo$1646
+A$ax5042rdfifo$1637
+A$ax5042rdfifo$1628
+A$ax5042rdfifo$1619
+A$ax5042rdfifo$1592
+A$ax5042rdfifo$1647
+A$ax5042rdfifo$1638
+A$ax5042rdfifo$1629
+A$ax5042rdfifo$1593
+A$ax5042rdfifo$1594
+A$ax5042rdfifo$1595
+A$ax5042rdfifo$1596
+A$ax5042rdfifo$1597
+A$ax5042rdfifo$1598
+A$ax5042rdfifo$1589
+A$ax5042rdfifo$1599
+
+
+
+ax5042wrfifo 4183545
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
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+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
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+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
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+G$OSCRUN$0$0
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+G$PORTC_3$0$0
+G$PORTB_4$0$0
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+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
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+_AX5042_PLLRNGMISCNB
+_IE
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+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
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+G$SPSHREG$0$0
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+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
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+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
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+G$XTALOSC$0$0
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+G$IE_1$0$0
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+G$EIP$0$0
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+_WTCNTB
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+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
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+G$AX5042_REF$0$0
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+G$DIRA$0$0
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+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
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+_ADCCH0VAL0
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+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+G$AX5042_FREQ2$0$0
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+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
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+_ADCCH1VAL0
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+_AX5042_FRAMINGNB
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+_B_6
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+G$EIE_2$0$0
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+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
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+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
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+_AX5042_RXMISC
+_IP
+_T0CNT0
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+_T1CNT0
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+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
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+_RADIOSTAT1
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+_T2CNT1
+_WTEVTB
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+_CY
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+G$OC0PIN$0$0
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+C$ax5042wrfifo.c$75$1$66
+C$ax5042wrfifo.c$76$1$66
+G$ax5042_writefifo$0$0
+_ax5042_writefifo
+XG$ax5042_writefifo$0$0
+
+
+
+ax5042regs 4232465
+.__.ABS.
+
+
+
+ax5043comminit 4233503
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
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+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
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+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
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+_AX5043_0xF35
+_AX5043_0xF44
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+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
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+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
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+G$AX5043_XTALAMPL$0$0
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+G$OC1STATUS$0$0
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+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
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+G$LPOSCPER$0$0
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+G$EIE_6$0$0
+G$T0STATUS$0$0
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+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
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+G$AX5043_TMGRXOFFSACQNB$0$0
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+G$AX5043_TMGTXSETTLE$0$0
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+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
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+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
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+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
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+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
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+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
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+
+
+
+ax5043commslpexit 4339608
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
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+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
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+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
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+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
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+G$EIP_3$0$0
+G$NVADDR1$0$0
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+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+_XWTEVTC0
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+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$AX5043_FREQDEV01$0$0
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+G$AX5043_IFFREQ1$0$0
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+G$OC1COMP$0$0
+_ADCCH0VAL
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+_XWTEVTD0
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+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
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+G$AX5043_FREQA0NB$0$0
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+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
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+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
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+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043commslpexit.c$24$1$66
+C$ax5043commslpexit.c$15$1$66
+C$ax5043commslpexit.c$25$1$66
+C$ax5043commslpexit.c$16$1$66
+C$ax5043commslpexit.c$8$0$0
+G$ax5043_commsleepexit$0$0
+_ax5043_commsleepexit
+A$ax5043commslpexit$3301
+A$ax5043commslpexit$3302
+A$ax5043commslpexit$3312
+A$ax5043commslpexit$3303
+A$ax5043commslpexit$3304
+A$ax5043commslpexit$3305
+XG$ax5043_commsleepexit$0$0
+A$ax5043commslpexit$3306
+A$ax5043commslpexit$3290
+A$ax5043commslpexit$3309
+A$ax5043commslpexit$3282
+A$ax5043commslpexit$3283
+A$ax5043commslpexit$3293
+A$ax5043commslpexit$3284
+A$ax5043commslpexit$3294
+A$ax5043commslpexit$3285
+A$ax5043commslpexit$3276
+A$ax5043commslpexit$3295
+A$ax5043commslpexit$3286
+A$ax5043commslpexit$3296
+A$ax5043commslpexit$3287
+A$ax5043commslpexit$3297
+A$ax5043commslpexit$3279
+A$ax5043commslpexit$3298
+C$ax5043commslpexit.c$10$1$66
+C$ax5043commslpexit.c$11$1$66
+C$ax5043commslpexit.c$12$1$66
+C$ax5043commslpexit.c$13$1$66
+
+
+
+ax5043reset 4445914
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIODRV$0$0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIODRV
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043reset.c$8$0$0
+_ax5043_reset
+_ax5043_probeirq
+XG$ax5043_reset$0$0
+XG$ax5043_probeirq$0$0
+A$ax5043reset$3400
+A$ax5043reset$3310
+A$ax5043reset$3311
+A$ax5043reset$3302
+A$ax5043reset$3330
+A$ax5043reset$3321
+A$ax5043reset$3312
+A$ax5043reset$3303
+A$ax5043reset$3502
+A$ax5043reset$3430
+A$ax5043reset$3331
+A$ax5043reset$3322
+A$ax5043reset$3313
+A$ax5043reset$3304
+A$ax5043reset$3512
+A$ax5043reset$3422
+A$ax5043reset$3323
+A$ax5043reset$3314
+A$ax5043reset$3305
+A$ax5043reset$3450
+A$ax5043reset$3360
+A$ax5043reset$3342
+A$ax5043reset$3315
+A$ax5043reset$3306
+A$ax5043reset$3442
+A$ax5043reset$3433
+A$ax5043reset$3370
+A$ax5043reset$3352
+A$ax5043reset$3343
+A$ax5043reset$3334
+A$ax5043reset$3307
+A$ax5043reset$3515
+A$ax5043reset$3506
+A$ax5043reset$3443
+A$ax5043reset$3434
+A$ax5043reset$3425
+A$ax5043reset$3416
+A$ax5043reset$3371
+A$ax5043reset$3353
+A$ax5043reset$3335
+A$ax5043reset$3326
+A$ax5043reset$3290
+A$ax5043reset$3507
+A$ax5043reset$3480
+A$ax5043reset$3453
+A$ax5043reset$3444
+A$ax5043reset$3435
+A$ax5043reset$3381
+A$ax5043reset$3354
+A$ax5043reset$3327
+A$ax5043reset$3318
+A$ax5043reset$3291
+A$ax5043reset$3508
+A$ax5043reset$3481
+A$ax5043reset$3463
+A$ax5043reset$3454
+A$ax5043reset$3445
+A$ax5043reset$3391
+A$ax5043reset$3382
+A$ax5043reset$3364
+A$ax5043reset$3283
+A$ax5043reset$3509
+A$ax5043reset$3491
+A$ax5043reset$3482
+A$ax5043reset$3473
+A$ax5043reset$3464
+A$ax5043reset$3428
+A$ax5043reset$3419
+A$ax5043reset$3392
+A$ax5043reset$3374
+A$ax5043reset$3365
+A$ax5043reset$3347
+A$ax5043reset$3338
+A$ax5043reset$3519
+A$ax5043reset$3492
+A$ax5043reset$3465
+A$ax5043reset$3438
+A$ax5043reset$3429
+A$ax5043reset$3375
+A$ax5043reset$3357
+A$ax5043reset$3348
+A$ax5043reset$3339
+A$ax5043reset$3294
+A$ax5043reset$3493
+A$ax5043reset$3466
+A$ax5043reset$3448
+A$ax5043reset$3439
+A$ax5043reset$3376
+A$ax5043reset$3358
+A$ax5043reset$3286
+A$ax5043reset$3467
+A$ax5043reset$3458
+A$ax5043reset$3449
+A$ax5043reset$3386
+A$ax5043reset$3377
+A$ax5043reset$3359
+A$ax5043reset$3477
+A$ax5043reset$3468
+A$ax5043reset$3459
+A$ax5043reset$3396
+A$ax5043reset$3387
+A$ax5043reset$3369
+A$ax5043reset$3297
+A$ax5043reset$3496
+A$ax5043reset$3487
+A$ax5043reset$3478
+A$ax5043reset$3388
+A$ax5043reset$3298
+A$ax5043reset$3289
+A$ax5043reset$3479
+A$ax5043reset$3299
+A$ax5043reset$3499
+C$ax5043reset.c$20$1$66
+C$ax5043reset.c$12$1$66
+C$ax5043reset.c$22$1$66
+C$ax5043reset.c$13$1$66
+C$ax5043reset.c$32$1$66
+C$ax5043reset.c$23$1$66
+C$ax5043reset.c$60$1$66
+C$ax5043reset.c$51$1$66
+C$ax5043reset.c$42$1$66
+C$ax5043reset.c$15$1$66
+C$ax5043reset.c$61$1$66
+C$ax5043reset.c$52$1$66
+C$ax5043reset.c$43$1$66
+C$ax5043reset.c$53$1$66
+C$ax5043reset.c$35$1$66
+C$ax5043reset.c$70$1$68
+C$ax5043reset.c$54$1$66
+C$ax5043reset.c$36$1$66
+C$ax5043reset.c$71$1$68
+C$ax5043reset.c$55$1$66
+C$ax5043reset.c$19$1$66
+C$ax5043reset.c$72$1$68
+C$ax5043reset.c$56$1$66
+C$ax5043reset.c$80$2$69
+C$ax5043reset.c$73$1$68
+C$ax5043reset.c$66$1$66
+C$ax5043reset.c$48$1$66
+C$ax5043reset.c$39$1$66
+C$ax5043reset.c$92$1$68
+C$ax5043reset.c$90$2$69
+C$ax5043reset.c$81$2$69
+C$ax5043reset.c$74$1$68
+C$ax5043reset.c$58$1$66
+C$ax5043reset.c$49$1$66
+C$ax5043reset.c$93$1$68
+C$ax5043reset.c$91$2$69
+C$ax5043reset.c$75$1$68
+C$ax5043reset.c$59$1$66
+C$ax5043reset.c$94$1$68
+C$ax5043reset.c$83$2$69
+C$ax5043reset.c$76$1$68
+C$ax5043reset.c$69$1$66
+C$ax5043reset.c$95$1$68
+C$ax5043reset.c$84$2$69
+C$ax5043reset.c$77$1$68
+C$ax5043reset.c$96$1$68
+C$ax5043reset.c$85$2$69
+C$ax5043reset.c$78$1$68
+G$ax5043_reset$0$0
+G$ax5043_probeirq$0$0
+C$ax5043reset.c$87$2$69
+C$ax5043reset.c$79$2$69
+C$ax5043reset.c$89$2$69
+
+
+
+ax5043deepsleep 4558103
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043deepsleep.c$21$1$66
+C$ax5043deepsleep.c$12$1$66
+C$ax5043deepsleep.c$22$1$66
+C$ax5043deepsleep.c$13$1$66
+C$ax5043deepsleep.c$10$0$0
+C$ax5043deepsleep.c$31$1$68
+C$ax5043deepsleep.c$24$1$66
+C$ax5043deepsleep.c$32$1$68
+C$ax5043deepsleep.c$17$1$66
+C$ax5043deepsleep.c$41$2$69
+C$ax5043deepsleep.c$18$1$66
+_ax5043_wakeup_deepsleep
+C$ax5043deepsleep.c$42$2$69
+C$ax5043deepsleep.c$26$1$68
+C$ax5043deepsleep.c$19$1$66
+C$ax5043deepsleep.c$45$1$68
+C$ax5043deepsleep.c$43$2$69
+C$ax5043deepsleep.c$27$1$68
+C$ax5043deepsleep.c$46$1$68
+C$ax5043deepsleep.c$28$1$68
+C$ax5043deepsleep.c$47$1$68
+C$ax5043deepsleep.c$29$1$68
+C$ax5043deepsleep.c$48$1$68
+C$ax5043deepsleep.c$39$1$68
+G$ax5043_enter_deepsleep$0$0
+XG$ax5043_wakeup_deepsleep$0$0
+_ax5043_enter_deepsleep
+XG$ax5043_enter_deepsleep$0$0
+A$ax5043deepsleep$3300
+A$ax5043deepsleep$3330
+A$ax5043deepsleep$3303
+A$ax5043deepsleep$3340
+A$ax5043deepsleep$3331
+A$ax5043deepsleep$3304
+A$ax5043deepsleep$3350
+A$ax5043deepsleep$3341
+A$ax5043deepsleep$3323
+A$ax5043deepsleep$3305
+A$ax5043deepsleep$3342
+A$ax5043deepsleep$3361
+A$ax5043deepsleep$3334
+A$ax5043deepsleep$3362
+A$ax5043deepsleep$3353
+A$ax5043deepsleep$3326
+A$ax5043deepsleep$3308
+A$ax5043deepsleep$3281
+A$ax5043deepsleep$3372
+A$ax5043deepsleep$3363
+A$ax5043deepsleep$3354
+A$ax5043deepsleep$3345
+A$ax5043deepsleep$3291
+A$ax5043deepsleep$3282
+A$ax5043deepsleep$3382
+A$ax5043deepsleep$3373
+A$ax5043deepsleep$3364
+A$ax5043deepsleep$3355
+A$ax5043deepsleep$3346
+A$ax5043deepsleep$3337
+A$ax5043deepsleep$3292
+A$ax5043deepsleep$3283
+A$ax5043deepsleep$3374
+A$ax5043deepsleep$3347
+A$ax5043deepsleep$3338
+A$ax5043deepsleep$3329
+A$ax5043deepsleep$3348
+A$ax5043deepsleep$3339
+A$ax5043deepsleep$3367
+A$ax5043deepsleep$3358
+A$ax5043deepsleep$3349
+A$ax5043deepsleep$3295
+A$ax5043deepsleep$3286
+A$ax5043deepsleep$3386
+A$ax5043deepsleep$3377
+A$ax5043deepsleep$3368
+A$ax5043deepsleep$3296
+A$ax5043deepsleep$3287
+A$ax5043deepsleep$3278
+A$ax5043deepsleep$3378
+A$ax5043deepsleep$3297
+A$ax5043deepsleep$3288
+G$ax5043_wakeup_deepsleep$0$0
+A$ax5043deepsleep$3298
+A$ax5043deepsleep$3299
+
+
+
+ax5043rclkena 4666667
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5043_rclk_enable$0$0
+A$ax5043rclkena$3310
+_ax5043_rclk_enable
+A$ax5043rclkena$3311
+A$ax5043rclkena$3302
+A$ax5043rclkena$3330
+A$ax5043rclkena$3321
+A$ax5043rclkena$3303
+A$ax5043rclkena$3322
+A$ax5043rclkena$3304
+A$ax5043rclkena$3323
+A$ax5043rclkena$3314
+A$ax5043rclkena$3333
+A$ax5043rclkena$3324
+A$ax5043rclkena$3315
+A$ax5043rclkena$3325
+A$ax5043rclkena$3316
+A$ax5043rclkena$3307
+A$ax5043rclkena$3280
+A$ax5043rclkena$3317
+A$ax5043rclkena$3290
+A$ax5043rclkena$3291
+A$ax5043rclkena$3282
+A$ax5043rclkena$3329
+A$ax5043rclkena$3294
+A$ax5043rclkena$3285
+A$ax5043rclkena$3295
+A$ax5043rclkena$3277
+XG$ax5043_rclk_enable$0$0
+A$ax5043rclkena$3296
+A$ax5043rclkena$3289
+A$ax5043rclkena$3299
+C$ax5043rclkena.c$10$1$64
+C$ax5043rclkena.c$11$1$64
+C$ax5043rclkena.c$12$1$64
+C$ax5043rclkena.c$13$1$64
+C$ax5043rclkena.c$14$1$64
+C$ax5043rclkena.c$15$1$64
+C$ax5043rclkena.c$16$1$64
+C$ax5043rclkena.c$17$1$64
+C$ax5043rclkena.c$18$1$64
+C$ax5043rclkena.c$19$1$64
+C$ax5043rclkena.c$8$1$64
+C$ax5043rclkena.c$9$1$64
+C$ax5043rclkena.c$5$0$0
+
+
+
+ax5043rclkdis 4773439
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5043_rclk_disable
+C$ax5043rclkdis.c$8$1$64
+C$ax5043rclkdis.c$9$1$64
+C$ax5043rclkdis.c$5$0$0
+XG$ax5043_rclk_disable$0$0
+A$ax5043rclkdis$3300
+A$ax5043rclkdis$3301
+A$ax5043rclkdis$3302
+A$ax5043rclkdis$3312
+A$ax5043rclkdis$3313
+A$ax5043rclkdis$3305
+A$ax5043rclkdis$3306
+A$ax5043rclkdis$3316
+A$ax5043rclkdis$3307
+A$ax5043rclkdis$3280
+A$ax5043rclkdis$3308
+A$ax5043rclkdis$3290
+A$ax5043rclkdis$3291
+A$ax5043rclkdis$3283
+A$ax5043rclkdis$3294
+A$ax5043rclkdis$3295
+A$ax5043rclkdis$3286
+A$ax5043rclkdis$3296
+A$ax5043rclkdis$3278
+A$ax5043rclkdis$3279
+A$ax5043rclkdis$3289
+A$ax5043rclkdis$3299
+C$ax5043rclkdis.c$10$1$64
+C$ax5043rclkdis.c$11$1$64
+C$ax5043rclkdis.c$12$1$64
+C$ax5043rclkdis.c$13$1$64
+C$ax5043rclkdis.c$14$1$64
+C$ax5043rclkdis.c$15$1$64
+G$ax5043_rclk_disable$0$0
+C$ax5043rclkdis.c$16$1$64
+
+
+
+ax5043rdfifo 4879617
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043rdfifo.c$10$0$0
+C$ax5043rdfifo.c$74$1$66
+C$ax5043rdfifo.c$75$1$66
+G$ax5043_readfifo$0$0
+_ax5043_readfifo
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+A$ax5043rdfifo$3310
+A$ax5043rdfifo$3301
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+A$ax5043rdfifo$3311
+A$ax5043rdfifo$3302
+A$ax5043rdfifo$3330
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+A$ax5043rdfifo$3312
+A$ax5043rdfifo$3303
+A$ax5043rdfifo$3313
+A$ax5043rdfifo$3304
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+A$ax5043rdfifo$3315
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+A$ax5043rdfifo$3325
+A$ax5043rdfifo$3316
+A$ax5043rdfifo$3307
+A$ax5043rdfifo$3280
+A$ax5043rdfifo$3326
+A$ax5043rdfifo$3317
+A$ax5043rdfifo$3308
+A$ax5043rdfifo$3281
+A$ax5043rdfifo$3272
+A$ax5043rdfifo$3327
+A$ax5043rdfifo$3318
+A$ax5043rdfifo$3309
+A$ax5043rdfifo$3282
+A$ax5043rdfifo$3273
+A$ax5043rdfifo$3328
+A$ax5043rdfifo$3319
+A$ax5043rdfifo$3292
+A$ax5043rdfifo$3274
+A$ax5043rdfifo$3329
+A$ax5043rdfifo$3293
+A$ax5043rdfifo$3284
+A$ax5043rdfifo$3275
+A$ax5043rdfifo$3294
+A$ax5043rdfifo$3285
+A$ax5043rdfifo$3276
+A$ax5043rdfifo$3295
+A$ax5043rdfifo$3286
+A$ax5043rdfifo$3277
+A$ax5043rdfifo$3296
+A$ax5043rdfifo$3287
+A$ax5043rdfifo$3278
+A$ax5043rdfifo$3279
+A$ax5043rdfifo$3298
+A$ax5043rdfifo$3289
+A$ax5043rdfifo$3299
+
+
+
+ax5043wrfifo 4986956
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5043wrfifo$3300
+A$ax5043wrfifo$3310
+A$ax5043wrfifo$3301
+A$ax5043wrfifo$3320
+A$ax5043wrfifo$3311
+A$ax5043wrfifo$3302
+A$ax5043wrfifo$3330
+A$ax5043wrfifo$3321
+A$ax5043wrfifo$3312
+A$ax5043wrfifo$3303
+A$ax5043wrfifo$3331
+A$ax5043wrfifo$3313
+A$ax5043wrfifo$3304
+A$ax5043wrfifo$3323
+A$ax5043wrfifo$3324
+A$ax5043wrfifo$3315
+A$ax5043wrfifo$3306
+A$ax5043wrfifo$3325
+A$ax5043wrfifo$3316
+A$ax5043wrfifo$3307
+A$ax5043wrfifo$3280
+A$ax5043wrfifo$3326
+A$ax5043wrfifo$3317
+A$ax5043wrfifo$3308
+A$ax5043wrfifo$3281
+A$ax5043wrfifo$3272
+A$ax5043wrfifo$3327
+A$ax5043wrfifo$3318
+A$ax5043wrfifo$3309
+A$ax5043wrfifo$3282
+A$ax5043wrfifo$3273
+A$ax5043wrfifo$3328
+A$ax5043wrfifo$3319
+A$ax5043wrfifo$3292
+A$ax5043wrfifo$3274
+A$ax5043wrfifo$3329
+A$ax5043wrfifo$3293
+A$ax5043wrfifo$3284
+A$ax5043wrfifo$3275
+A$ax5043wrfifo$3294
+A$ax5043wrfifo$3285
+A$ax5043wrfifo$3276
+A$ax5043wrfifo$3295
+A$ax5043wrfifo$3286
+A$ax5043wrfifo$3277
+A$ax5043wrfifo$3296
+A$ax5043wrfifo$3287
+A$ax5043wrfifo$3278
+A$ax5043wrfifo$3279
+A$ax5043wrfifo$3298
+A$ax5043wrfifo$3289
+A$ax5043wrfifo$3299
+C$ax5043wrfifo.c$10$0$0
+C$ax5043wrfifo.c$75$1$66
+C$ax5043wrfifo.c$76$1$66
+G$ax5043_writefifo$0$0
+_ax5043_writefifo
+XG$ax5043_writefifo$0$0
+
+
+
+ax5043regs 5094370
+.__.ABS.
+
+
+
+ax5051comminit 5095408
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
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+G$U1CTRL$0$0
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+G$RADIOADDR1$0$0
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+_LPOSCFREQ
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+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
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+_AX5051_FREQA0NB
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+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
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+_AX5051_PLLLOOPNB
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+_AX5051_MODULATORMISCNB
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+_AX5051_IFMODE
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+G$AC$0$0
+_DMA0CONFIG
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+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
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+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
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+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
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+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
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+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
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+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
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+_ADCCONV
+_NVDATA
+_U0SHREG
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+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
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+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5051commslpexit.c$24$1$66
+C$ax5051commslpexit.c$15$1$66
+C$ax5051commslpexit.c$25$1$66
+C$ax5051commslpexit.c$16$1$66
+C$ax5051commslpexit.c$8$0$0
+G$ax5051_commsleepexit$0$0
+_ax5051_commsleepexit
+XG$ax5051_commsleepexit$0$0
+A$ax5051commslpexit$1650
+A$ax5051commslpexit$1661
+A$ax5051commslpexit$1680
+A$ax5051commslpexit$1653
+A$ax5051commslpexit$1672
+A$ax5051commslpexit$1654
+A$ax5051commslpexit$1673
+A$ax5051commslpexit$1664
+A$ax5051commslpexit$1655
+A$ax5051commslpexit$1683
+A$ax5051commslpexit$1674
+A$ax5051commslpexit$1665
+A$ax5051commslpexit$1656
+A$ax5051commslpexit$1647
+A$ax5051commslpexit$1675
+A$ax5051commslpexit$1666
+A$ax5051commslpexit$1657
+A$ax5051commslpexit$1676
+A$ax5051commslpexit$1667
+A$ax5051commslpexit$1658
+A$ax5051commslpexit$1677
+A$ax5051commslpexit$1668
+A$ax5051commslpexit$1669
+C$ax5051commslpexit.c$10$1$66
+C$ax5051commslpexit.c$11$1$66
+C$ax5051commslpexit.c$12$1$66
+C$ax5051commslpexit.c$13$1$66
+
+
+
+ax5051reset 5194431
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
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+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
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+_PORTC_3
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+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
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+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
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+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_ACC_7
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+G$IP_2$0$0
+G$WTIRQEN$0$0
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+G$U0MODE$0$0
+G$T2STATUS$0$0
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+G$T1CNT$0$0
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+_AX5051_FECSYNCNB
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+G$T2CNT$0$0
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+_E2IP_0
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+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
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+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
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+_E2IP_1
+_IE_3
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+G$ax5051_reset$0$0
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+G$ax5051_probeirq$0$0
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+
+
+
+ax5051deepsleep 5252600
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
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+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$EIP_2$0$0
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+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5051rclkena 5300538
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5051_rclk_enable$0$0
+_ax5051_rclk_enable
+A$ax5051rclkena$1700
+A$ax5051rclkena$1701
+A$ax5051rclkena$1705
+A$ax5051rclkena$1660
+A$ax5051rclkena$1651
+A$ax5051rclkena$1706
+A$ax5051rclkena$1670
+A$ax5051rclkena$1661
+A$ax5051rclkena$1680
+A$ax5051rclkena$1662
+A$ax5051rclkena$1653
+A$ax5051rclkena$1690
+A$ax5051rclkena$1709
+A$ax5051rclkena$1691
+A$ax5051rclkena$1673
+A$ax5051rclkena$1692
+A$ax5051rclkena$1683
+A$ax5051rclkena$1674
+A$ax5051rclkena$1665
+A$ax5051rclkena$1656
+A$ax5051rclkena$1693
+A$ax5051rclkena$1675
+A$ax5051rclkena$1666
+A$ax5051rclkena$1648
+XG$ax5051_rclk_enable$0$0
+A$ax5051rclkena$1676
+A$ax5051rclkena$1667
+A$ax5051rclkena$1686
+A$ax5051rclkena$1677
+A$ax5051rclkena$1687
+A$ax5051rclkena$1678
+A$ax5051rclkena$1697
+A$ax5051rclkena$1679
+C$ax5051rclkena.c$10$1$64
+A$ax5051rclkena$1698
+C$ax5051rclkena.c$11$1$64
+A$ax5051rclkena$1699
+C$ax5051rclkena.c$12$1$64
+C$ax5051rclkena.c$13$1$64
+C$ax5051rclkena.c$14$1$64
+C$ax5051rclkena.c$15$1$64
+C$ax5051rclkena.c$16$1$64
+C$ax5051rclkena.c$17$1$64
+C$ax5051rclkena.c$18$1$64
+C$ax5051rclkena.c$19$1$64
+C$ax5051rclkena.c$8$1$64
+C$ax5051rclkena.c$9$1$64
+C$ax5051rclkena.c$5$0$0
+
+
+
+ax5051rclkdis 5350833
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
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+G$EIE_7$0$0
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+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5051_rclk_disable
+C$ax5051rclkdis.c$8$1$64
+C$ax5051rclkdis.c$9$1$64
+C$ax5051rclkdis.c$5$0$0
+XG$ax5051_rclk_disable$0$0
+A$ax5051rclkdis$1650
+A$ax5051rclkdis$1660
+A$ax5051rclkdis$1651
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+A$ax5051rclkdis$1677
+A$ax5051rclkdis$1687
+A$ax5051rclkdis$1669
+A$ax5051rclkdis$1688
+C$ax5051rclkdis.c$10$1$64
+C$ax5051rclkdis.c$11$1$64
+C$ax5051rclkdis.c$12$1$64
+C$ax5051rclkdis.c$13$1$64
+C$ax5051rclkdis.c$14$1$64
+C$ax5051rclkdis.c$15$1$64
+G$ax5051_rclk_disable$0$0
+C$ax5051rclkdis.c$16$1$64
+
+
+
+ax5051rdfifo 5400489
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5051rdfifo$1699
+C$ax5051rdfifo.c$10$0$0
+C$ax5051rdfifo.c$74$1$66
+C$ax5051rdfifo.c$75$1$66
+G$ax5051_readfifo$0$0
+_ax5051_readfifo
+XG$ax5051_readfifo$0$0
+A$ax5051rdfifo$1700
+A$ax5051rdfifo$1701
+A$ax5051rdfifo$1650
+A$ax5051rdfifo$1660
+A$ax5051rdfifo$1651
+A$ax5051rdfifo$1670
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+A$ax5051rdfifo$1680
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+A$ax5051rdfifo$1672
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+A$ax5051rdfifo$1645
+A$ax5051rdfifo$1691
+A$ax5051rdfifo$1682
+A$ax5051rdfifo$1673
+A$ax5051rdfifo$1664
+A$ax5051rdfifo$1655
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+A$ax5051rdfifo$1683
+A$ax5051rdfifo$1674
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+A$ax5051rdfifo$1675
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+A$ax5051rdfifo$1677
+A$ax5051rdfifo$1696
+A$ax5051rdfifo$1687
+A$ax5051rdfifo$1678
+A$ax5051rdfifo$1669
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+A$ax5051rdfifo$1688
+A$ax5051rdfifo$1679
+A$ax5051rdfifo$1698
+A$ax5051rdfifo$1689
+
+
+
+ax5051wrfifo 5451134
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5051wrfifo$1700
+A$ax5051wrfifo$1701
+A$ax5051wrfifo$1702
+A$ax5051wrfifo$1650
+A$ax5051wrfifo$1660
+A$ax5051wrfifo$1651
+A$ax5051wrfifo$1670
+A$ax5051wrfifo$1652
+A$ax5051wrfifo$1643
+A$ax5051wrfifo$1680
+A$ax5051wrfifo$1671
+A$ax5051wrfifo$1653
+A$ax5051wrfifo$1644
+A$ax5051wrfifo$1690
+A$ax5051wrfifo$1681
+A$ax5051wrfifo$1672
+A$ax5051wrfifo$1663
+A$ax5051wrfifo$1645
+A$ax5051wrfifo$1691
+A$ax5051wrfifo$1682
+A$ax5051wrfifo$1673
+A$ax5051wrfifo$1664
+A$ax5051wrfifo$1655
+A$ax5051wrfifo$1646
+A$ax5051wrfifo$1692
+A$ax5051wrfifo$1683
+A$ax5051wrfifo$1674
+A$ax5051wrfifo$1665
+A$ax5051wrfifo$1656
+A$ax5051wrfifo$1647
+A$ax5051wrfifo$1684
+A$ax5051wrfifo$1675
+A$ax5051wrfifo$1666
+A$ax5051wrfifo$1657
+A$ax5051wrfifo$1648
+A$ax5051wrfifo$1694
+A$ax5051wrfifo$1667
+A$ax5051wrfifo$1658
+A$ax5051wrfifo$1649
+A$ax5051wrfifo$1695
+A$ax5051wrfifo$1686
+A$ax5051wrfifo$1677
+A$ax5051wrfifo$1696
+A$ax5051wrfifo$1687
+A$ax5051wrfifo$1678
+A$ax5051wrfifo$1669
+A$ax5051wrfifo$1697
+A$ax5051wrfifo$1688
+A$ax5051wrfifo$1679
+A$ax5051wrfifo$1698
+A$ax5051wrfifo$1689
+A$ax5051wrfifo$1699
+C$ax5051wrfifo.c$10$0$0
+C$ax5051wrfifo.c$75$1$66
+C$ax5051wrfifo.c$76$1$66
+G$ax5051_writefifo$0$0
+_ax5051_writefifo
+XG$ax5051_writefifo$0$0
+
+
+
+ax5051regs 5501854
+.__.ABS.
+
+
+
+ax8052regs 5502892
+.__.ABS.
+
+
+
+
+
+
+
+lcdinit
+
+;!FILE libmf/lcdinit.asm
+XH3
+H 1B areas 39E global symbols
+M lcdinit
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F5 flags 20 addr 0
+S A$lcdinit$1519 Def0000E5
+S A$lcdinit$1483 Def0000B5
+S A$lcdinit$1456 Def000094
+S A$lcdinit$1294 Def00003C
+S A$lcdinit$1276 Def00002E
+S A$lcdinit$1258 Def000029
+S A$lcdinit$1195 Def000006
+S C$lcdinit.c$116$1$66 Def0000EB
+S C$lcdinit.c$107$1$66 Def0000D0
+S A$lcdinit$1529 Def0000F1
+S A$lcdinit$1484 Def0000B8
+S A$lcdinit$1466 Def0000A0
+S A$lcdinit$1277 Def000030
+S A$lcdinit$1259 Def00002B
+S C$lcdinit.c$117$1$66 Def0000F1
+S C$lcdinit.c$108$1$66 Def0000D6
+S A$lcdinit$1494 Def0000C4
+S A$lcdinit$1476 Def0000AC
+S A$lcdinit$1449 Def00008C
+S A$lcdinit$1395 Def000067
+S A$lcdinit$1386 Def00005E
+S A$lcdinit$1377 Def000056
+S A$lcdinit$1359 Def000052
+S XG$lcd_writedata$0$0 Def00004E
+S A$lcdinit$1477 Def0000AF
+S A$lcdinit$1459 Def000097
+S A$lcdinit$1297 Def00003E
+S A$lcdinit$1487 Def0000BB
+S A$lcdinit$1469 Def0000A3
+S A$lcdinit$1298 Def000040
+S A$lcdinit$1289 Def000036
+S G$lcd_writecmd$0$0 Def000043
+S C$lcdinit.c$10$3$50 Def00000A
+S A$lcdinit$1497 Def0000C7
+S A$lcdinit$1398 Def00006A
+S A$lcdinit$1389 Def000061
+S A$lcdinit$1498 Def0000CA
+S C$lcdinit.c$21$1$52 Def000025
+S C$lcdinit.c$22$1$52 Def00002D
+S C$lcdinit.c$20$2$53 Def000023
+S C$lcdinit.c$24$1$52 Def00002E
+S C$lcdinit.c$51$1$62 Def00004F
+S G$lcd_waitshort$0$0 Def00001D
+S G$lcd_waitlong$0$0 Def000000
+S C$lcdinit.c$52$1$62 Def000052
+S C$lcdinit.c$45$1$60 Def000049
+S C$lcdinit.c$30$2$56 Def000036
+S C$lcdinit.c$60$1$64 Def00005C
+S C$lcdinit.c$53$1$62 Def000055
+S C$lcdinit.c$46$1$60 Def00004B
+S C$lcdinit.c$33$1$55 Def00003C
+S C$lcdinit.c$13$1$48 Def000012
+S C$lcdinit.c$11$2$49 Def00000C
+S C$lcdinit.c$61$1$64 Def00005E
+S C$lcdinit.c$47$1$60 Def00004E
+S C$lcdinit.c$40$1$58 Def000045
+S C$lcdinit.c$34$1$55 Def00003E
+S C$lcdinit.c$19$1$52 Def000023
+S C$lcdinit.c$14$1$48 Def00001C
+S C$lcdinit.c$12$2$49 Def000010
+S C$lcdinit.c$62$1$64 Def000061
+S C$lcdinit.c$55$1$62 Def000056
+S C$lcdinit.c$41$1$58 Def000048
+S C$lcdinit.c$35$1$55 Def000042
+S C$lcdinit.c$26$1$55 Def000032
+S C$lcdinit.c$63$1$64 Def000064
+S C$lcdinit.c$49$1$60 Def00004F
+S C$lcdinit.c$27$1$55 Def000034
+S C$lcdinit.c$16$1$48 Def00001D
+S C$lcdinit.c$80$1$66 Def000087
+S C$lcdinit.c$64$1$64 Def000067
+S C$lcdinit.c$43$1$58 Def000049
+S C$lcdinit.c$37$1$55 Def000043
+S G$lcd_write$0$0 Def00002E
+S _lcd_writecmd Def000043
+S C$lcdinit.c$90$1$66 Def0000A0
+S C$lcdinit.c$81$1$66 Def000089
+S C$lcdinit.c$72$1$66 Def000070
+S C$lcdinit.c$65$1$64 Def00006A
+S C$lcdinit.c$18$1$48 Def000021
+S C$lcdinit.c$82$1$66 Def00008C
+S C$lcdinit.c$73$1$66 Def000073
+S C$lcdinit.c$66$1$64 Def00006D
+S C$lcdinit.c$29$2$55 Def000036
+S C$lcdinit.c$92$1$66 Def0000A3
+S C$lcdinit.c$74$1$66 Def000076
+S C$lcdinit.c$67$1$64 Def00006F
+S C$lcdinit.c$58$1$64 Def000056
+S C$lcdinit.c$93$1$66 Def0000A9
+S C$lcdinit.c$84$1$66 Def00008E
+S C$lcdinit.c$75$1$66 Def000079
+S C$lcdinit.c$59$1$64 Def000059
+S C$lcdinit.c$76$1$66 Def00007C
+S C$lcdinit.c$69$1$64 Def000070
+S C$lcdinit.c$39$1$58 Def000043
+S C$lcdinit.c$95$1$66 Def0000AC
+S C$lcdinit.c$86$1$66 Def000091
+S C$lcdinit.c$77$1$66 Def00007F
+S _lcd_waitshort Def00001D
+S _lcd_waitlong Def000000
+S C$lcdinit.c$96$1$66 Def0000B2
+S C$lcdinit.c$87$1$66 Def000097
+S C$lcdinit.c$78$1$66 Def000082
+S C$lcdinit.c$79$1$66 Def000085
+S C$lcdinit.c$98$1$66 Def0000B5
+S C$lcdinit.c$89$1$66 Def00009A
+S G$lcd_init$0$0 Def000070
+S C$lcdinit.c$99$1$66 Def0000BB
+S XG$lcd_writecmd$0$0 Def000048
+S _lcd_write Def00002E
+S G$lcd_portinit$0$0 Def000056
+S C$lcdinit.c$7$1$48 Def000008
+S C$lcdinit.c$4$0$0 Def000000
+S C$lcdinit.c$8$2$48 Def000008
+S XG$lcd_waitshort$0$0 Def00002D
+S XG$lcd_waitlong$0$0 Def00001C
+S C$lcdinit.c$6$1$0 Def000006
+S C$lcdinit.c$9$2$49 Def00000A
+S G$lcd_portoff$0$0 Def00004F
+S _lcd_init Def000070
+S XG$lcd_write$0$0 Def000042
+S G$lcd_writedata$0$0 Def000049
+S _lcd_portinit Def000056
+S XG$lcd_init$0$0 Def0000F4
+S _lcd_portoff Def00004F
+S A$lcdinit$1201 Def000008
+S A$lcdinit$1301 Def000042
+S A$lcdinit$1220 Def000012
+S A$lcdinit$1211 Def00000C
+S A$lcdinit$1401 Def00006D
+S A$lcdinit$1221 Def000013
+S A$lcdinit$1212 Def00000D
+S XG$lcd_portinit$0$0 Def00006F
+S _lcd_writedata Def000049
+S A$lcdinit$1501 Def0000CD
+S A$lcdinit$1222 Def000014
+S A$lcdinit$1213 Def00000E
+S A$lcdinit$1511 Def0000D9
+S A$lcdinit$1340 Def00004B
+S A$lcdinit$1322 Def000048
+S A$lcdinit$1241 Def00001D
+S A$lcdinit$1223 Def000016
+S A$lcdinit$1512 Def0000DC
+S A$lcdinit$1440 Def000085
+S A$lcdinit$1431 Def00007C
+S A$lcdinit$1422 Def000073
+S A$lcdinit$1404 Def00006F
+S A$lcdinit$1251 Def000023
+S A$lcdinit$1242 Def00001F
+S A$lcdinit$1224 Def000018
+S A$lcdinit$1522 Def0000E8
+S A$lcdinit$1504 Def0000D0
+S A$lcdinit$1252 Def000024
+S A$lcdinit$1225 Def00001A
+S A$lcdinit$1216 Def000010
+S A$lcdinit$1207 Def00000A
+S C$lcdinit.c$110$1$66 Def0000D9
+S C$lcdinit.c$101$1$66 Def0000BE
+S A$lcdinit$1532 Def0000F4
+S A$lcdinit$1505 Def0000D3
+S A$lcdinit$1343 Def00004E
+S A$lcdinit$1316 Def000043
+S A$lcdinit$1280 Def000032
+S A$lcdinit$1262 Def00002D
+S A$lcdinit$1217 Def000011
+S A$lcdinit$1208 Def00000B
+S A$lcdinit$1190 Def000000
+S C$lcdinit.c$111$1$66 Def0000DF
+S C$lcdinit.c$102$1$66 Def0000C4
+S A$lcdinit$1515 Def0000DF
+S A$lcdinit$1470 Def0000A6
+S A$lcdinit$1452 Def00008E
+S A$lcdinit$1443 Def000087
+S A$lcdinit$1434 Def00007F
+S A$lcdinit$1425 Def000076
+S A$lcdinit$1380 Def000059
+S A$lcdinit$1362 Def000055
+S A$lcdinit$1290 Def000038
+S A$lcdinit$1245 Def000021
+S A$lcdinit$1191 Def000002
+S C$lcdinit.c$121$1$66 Def0000F4
+S A$lcdinit$1525 Def0000EB
+S A$lcdinit$1480 Def0000B2
+S A$lcdinit$1462 Def00009A
+S A$lcdinit$1291 Def000039
+S A$lcdinit$1255 Def000025
+S A$lcdinit$1228 Def00001C
+S A$lcdinit$1192 Def000004
+S C$lcdinit.c$113$1$66 Def0000E2
+S C$lcdinit.c$104$1$66 Def0000C7
+S XG$lcd_portoff$0$0 Def000055
+S A$lcdinit$1526 Def0000EE
+S A$lcdinit$1508 Def0000D6
+S A$lcdinit$1490 Def0000BE
+S A$lcdinit$1463 Def00009D
+S A$lcdinit$1337 Def000049
+S A$lcdinit$1319 Def000045
+S A$lcdinit$1283 Def000034
+S A$lcdinit$1256 Def000026
+S C$lcdinit.c$114$1$66 Def0000E8
+S C$lcdinit.c$105$1$66 Def0000CD
+S A$lcdinit$1518 Def0000E2
+S A$lcdinit$1491 Def0000C1
+S A$lcdinit$1473 Def0000A9
+S A$lcdinit$1455 Def000091
+S A$lcdinit$1446 Def000089
+S A$lcdinit$1437 Def000082
+S A$lcdinit$1428 Def000079
+S A$lcdinit$1419 Def000070
+S A$lcdinit$1392 Def000064
+S A$lcdinit$1383 Def00005C
+S A$lcdinit$1356 Def00004F
+S A$lcdinit$1257 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 C0 07 C0 06 C0 05 7F 40
+R 00 00 00 17
+T 00 00 08
+R 00 00 00 17
+T 00 00 08 7E 00
+R 00 00 00 17
+T 00 00 0A
+R 00 00 00 17
+T 00 00 0A EE 14 FD FE 70 FA EF 14 FE FF 70 F2 D0
+R 00 00 00 17
+T 00 00 17 05 D0 06 D0 07 22
+R 00 00 00 17
+T 00 00 1D
+R 00 00 00 17
+T 00 00 1D C0 07 C0 06 7F 00
+R 00 00 00 17
+T 00 00 23
+R 00 00 00 17
+T 00 00 23 EF 14 FE FF 70 FA D0 06 D0 07 22
+R 00 00 00 17
+T 00 00 2E
+R 00 00 00 17
+T 00 00 2E C0 07 AF 82 C2 90 8F DE
+R 00 00 00 17
+T 00 00 36
+R 00 00 00 17
+T 00 00 36 E5 DD FF 30 E0 FA E5 DE D2 90 D0 07 22
+R 00 00 00 17
+T 00 00 43
+R 00 00 00 17
+T 00 00 43 C2 88 12 00 2E 22
+R 00 00 00 17 00 06 00 17
+T 00 00 49
+R 00 00 00 17
+T 00 00 49 D2 88 12 00 2E 22
+R 00 00 00 17 00 06 00 17
+T 00 00 4F
+R 00 00 00 17
+T 00 00 4F 75 DF 07 75 DC 00 22
+R 00 00 00 17
+T 00 00 56
+R 00 00 00 17
+T 00 00 56 43 8A 03 53 88 FE D2 89 43 8B 07 43 90
+R 00 00 00 17
+T 00 00 63 03 53 90 FB 75 DF D8 75 DC 01 E5 DE 22
+R 00 00 00 17
+T 00 00 70
+R 00 00 00 17
+T 00 00 70 43 8A 03 53 88 FC 43 8B 07 43 90 03 53
+R 00 00 00 17
+T 00 00 7D 90 FB 75 DF D8 75 DC 01 E5 DE C2 89 12
+R 00 00 00 17
+T 00 00 8A 00 00 D2 89 12 00 00 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 08 00 17
+T 00 00 95 00 43 12 00 00 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 9E 00 43 12 00 1D 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 A7 00 43 12 00 1D 75 82 39 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 B0 00 43 12 00 1D 75 82 14 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 B9 00 43 12 00 1D 75 82 56 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 C2 00 43 12 00 1D 75 82 6D 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 CB 00 43 12 00 1D 75 82 78 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 D4 00 43 12 00 1D 75 82 0C 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 DD 00 43 12 00 1D 75 82 06 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 E6 00 43 12 00 1D 75 82 01 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 EF 00 43 12 00 00 22
+R 00 00 00 17 00 03 00 17 00 06 00 17
+
+
+M:lcdinit
+F:G$lcd_waitlong$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_waitshort$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_write$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_writecmd$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_writedata$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_portoff$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_portinit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdinit.lcd_writecmd$cmd$1$57({1}SC:U),R,0,0,[]
+S:Llcdinit.lcd_writedata$d$1$59({1}SC:U),R,0,0,[]
+S:Llcdinit.lcd_init$x$1$66({1}SC:U),R,0,0,[]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdsetpos
+
+;!FILE libmf/lcdsetpos.asm
+XH3
+H 1A areas 10 global symbols
+M lcdsetpos
+O -mmcs51 --model-small
+S _lcd_writecmd Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S G$lcd_setpos$0$0 Def000000
+S C$lcdsetpos.c$5$1$48 Def000004
+S C$lcdsetpos.c$6$1$48 Def00000E
+S C$lcdsetpos.c$3$0$0 Def000000
+S _lcd_setpos Def000000
+S XG$lcd_setpos$0$0 Def00000E
+S A$lcdsetpos$111 Def000000
+S A$lcdsetpos$112 Def000002
+S A$lcdsetpos$122 Def00000E
+S A$lcdsetpos$115 Def000004
+S A$lcdsetpos$116 Def000006
+S A$lcdsetpos$117 Def000007
+S A$lcdsetpos$118 Def000009
+S A$lcdsetpos$119 Def00000C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 AF 82 74 80 4F F5 82 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 0D 07 22
+R 00 00 00 16
+
+
+M:lcdsetpos
+F:G$lcd_setpos$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdsetpos.lcd_setpos$v$1$47({1}SC:U),R,0,0,[r7]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrstr
+
+;!FILE libmf/lcdwrstr.asm
+XH3
+H 1A areas 26 global symbols
+M lcdwrstr
+O -mmcs51 --model-small
+S _lcd_writecmd Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+S __gptrget Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2E flags 20 addr 0
+S XG$lcd_writestr$0$0 Def00002D
+S A$lcdwrstr$120 Def000006
+S A$lcdwrstr$130 Def000015
+S A$lcdwrstr$121 Def000008
+S C$lcdwrstr.c$10$3$50 Def00001B
+S A$lcdwrstr$131 Def000016
+S A$lcdwrstr$122 Def00000A
+S A$lcdwrstr$123 Def00000C
+S A$lcdwrstr$114 Def000000
+S A$lcdwrstr$124 Def00000F
+S A$lcdwrstr$115 Def000002
+S C$lcdwrstr.c$12$3$51 Def000023
+S A$lcdwrstr$143 Def000023
+S A$lcdwrstr$134 Def000018
+S A$lcdwrstr$125 Def000010
+S A$lcdwrstr$116 Def000004
+S A$lcdwrstr$153 Def00002D
+S A$lcdwrstr$144 Def000025
+S A$lcdwrstr$126 Def000011
+S A$lcdwrstr$127 Def000013
+S A$lcdwrstr$137 Def00001B
+S A$lcdwrstr$138 Def00001E
+S A$lcdwrstr$148 Def000028
+S A$lcdwrstr$139 Def000021
+S A$lcdwrstr$149 Def00002B
+S C$lcdwrstr.c$16$1$48 Def00002D
+S C$lcdwrstr.c$14$2$49 Def000028
+S G$lcd_writestr$0$0 Def000000
+S C$lcdwrstr.c$3$0$0 Def000000
+S C$lcdwrstr.c$6$2$49 Def000006
+S C$lcdwrstr.c$7$2$49 Def000015
+S C$lcdwrstr.c$9$2$49 Def000018
+S _lcd_writestr Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AD 82 AE 83 AF F0
+R 00 00 00 16
+T 00 00 06
+R 00 00 00 16
+T 00 00 06 8D 82 8E 83 8F F0 12 00 00 FC A3 AD 82
+R 00 00 00 16 02 0A 00 04
+T 00 00 13 AE 83 EC 60 15 BC 0A 08 75 82 C0 12
+R 00 00 00 16
+T 00 00 1F 00 00 80 05
+R 00 00 00 16 02 03 00 00
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 8C 82 12 00 00
+R 00 00 00 16 02 06 00 03
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 12 00 00 80 D9
+R 00 00 00 16 02 04 00 01
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D 22
+R 00 00 00 16
+
+
+M:lcdwrstr
+F:G$lcd_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrstr.lcd_writestr$ch$1$47({3}DG,SC:S),R,0,0,[]
+S:Llcdwrstr.lcd_writestr$c$2$49({1}SC:S),R,0,0,[r4]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdclear
+
+;!FILE libmf/lcdclear.asm
+XH3
+H 1A areas 2F global symbols
+M lcdclear
+O -mmcs51 --model-small
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S Llcdclear.lcd_clear$len$1$47 Def000000
+S _lcd_clear_PARM_2 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2F flags 20 addr 0
+S XG$lcd_clear$0$0 Def00002E
+S A$lcdclear$121 Def000000
+S A$lcdclear$122 Def000002
+S A$lcdclear$150 Def000019
+S A$lcdclear$141 Def000013
+S A$lcdclear$160 Def000021
+S A$lcdclear$151 Def00001A
+S A$lcdclear$133 Def00000B
+S A$lcdclear$152 Def00001B
+S A$lcdclear$125 Def000005
+S A$lcdclear$171 Def00002C
+S A$lcdclear$153 Def00001D
+S A$lcdclear$126 Def000007
+S C$lcdclear.c$10$1$48 Def00000E
+S A$lcdclear$145 Def000015
+S A$lcdclear$136 Def00000E
+S C$lcdclear.c$11$1$48 Def000013
+S A$lcdclear$164 Def000023
+S A$lcdclear$146 Def000017
+S C$lcdclear.c$12$1$48 Def000015
+S A$lcdclear$156 Def00001F
+S A$lcdclear$147 Def000018
+S A$lcdclear$138 Def000011
+S A$lcdclear$129 Def000009
+S C$lcdclear.c$13$1$48 Def000019
+S A$lcdclear$175 Def00002E
+S C$lcdclear.c$14$1$48 Def00001F
+S A$lcdclear$167 Def000026
+S C$lcdclear.c$15$1$48 Def000021
+S A$lcdclear$168 Def000029
+S C$lcdclear.c$18$1$48 Def00002C
+S C$lcdclear.c$16$2$49 Def000023
+S C$lcdclear.c$19$1$48 Def00002E
+S C$lcdclear.c$17$2$49 Def000026
+S G$lcd_clear$0$0 Def000000
+S C$lcdclear.c$6$1$48 Def000000
+S C$lcdclear.c$3$0$0 Def000000
+S C$lcdclear.c$7$1$48 Def000005
+S C$lcdclear.c$8$1$48 Def000009
+S C$lcdclear.c$9$1$48 Def00000B
+S _lcd_clear Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 12 00 00 E5 00 00 00 70 02 80 23
+R 00 00 00 16 02 06 00 00 F1 21 09 00 05
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B 53 07 3F BF 10 00
+R 00 00 00 16
+T 00 00 11
+R 00 00 00 16
+T 00 00 11 40 02 80 19
+R 00 00 00 16
+T 00 00 15
+R 00 00 00 16
+T 00 00 15 74 10 C3 9F FF C3 95 00 00 00 50 02 8F
+R 00 00 00 16 F1 21 0A 00 05
+T 00 00 20 00 00 00
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 AF 00 00 00
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 12 00 00 75 82 20 12 00 00 DF F5
+R 00 00 00 16 02 04 00 01 02 0A 00 03
+T 00 00 2E
+R 00 00 00 16
+T 00 00 2E 22
+R 00 00 00 16
+
+
+M:lcdclear
+F:G$lcd_clear$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdclear.lcd_clear$len$1$47({1}SC:U),E,0,0
+S:Llcdclear.lcd_clear$pos$1$47({1}SC:U),R,0,0,[r7]
+S:Llcdclear.lcd_clear$x$1$48({1}SC:U),R,0,0,[r7]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdclrdisp
+
+;!FILE libmf/lcdclrdisp.asm
+XH3
+H 1A areas B global symbols
+M lcdclrdisp
+O -mmcs51 --model-small
+S _lcd_writecmd Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S A$lcdclrdisp$111 Def000000
+S A$lcdclrdisp$112 Def000003
+S A$lcdclrdisp$115 Def000006
+S C$lcdclrdisp.c$5$1$48 Def000000
+S C$lcdclrdisp.c$6$1$48 Def000006
+S C$lcdclrdisp.c$3$0$0 Def000000
+S G$lcd_cleardisplay$0$0 Def000000
+S _lcd_cleardisplay Def000000
+S XG$lcd_cleardisplay$0$0 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 82 01 12 00 00 22
+R 00 00 00 16 02 07 00 00
+
+
+M:lcdclrdisp
+F:G$lcd_cleardisplay$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwru16
+
+;!FILE libmf/lcdwru16.asm
+XH3
+H 1A areas 41 global symbols
+M lcdwru16
+O -mmcs51 --model-small
+S __divuint Ref000000
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S _lcd_writeu16_PARM_2 Def000000
+S _lcd_writeu16_PARM_3 Def000001
+S Llcdwru16.lcd_writeu16$pos$1$47 Def000001
+S Llcdwru16.lcd_writeu16$nrdig$1$47 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S XG$lcd_writeu16$0$0 Def00004C
+S A$lcdwru16$140 Def000013
+S A$lcdwru16$131 Def000008
+S A$lcdwru16$150 Def000028
+S A$lcdwru16$141 Def000015
+S A$lcdwru16$132 Def000009
+S A$lcdwru16$160 Def000034
+S A$lcdwru16$142 Def000017
+S A$lcdwru16$124 Def000000
+S A$lcdwru16$170 Def00003D
+S A$lcdwru16$143 Def000019
+S A$lcdwru16$125 Def000002
+S A$lcdwru16$171 Def00003F
+S A$lcdwru16$153 Def00002A
+S A$lcdwru16$144 Def00001B
+S A$lcdwru16$135 Def00000B
+S A$lcdwru16$172 Def000040
+S A$lcdwru16$163 Def000035
+S A$lcdwru16$154 Def00002C
+S A$lcdwru16$145 Def00001D
+S A$lcdwru16$182 Def000049
+S A$lcdwru16$173 Def000042
+S A$lcdwru16$164 Def000037
+S A$lcdwru16$155 Def00002D
+S A$lcdwru16$146 Def000020
+S A$lcdwru16$128 Def000004
+S C$lcdwru16.c$10$2$49 Def00003A
+S A$lcdwru16$183 Def00004A
+S A$lcdwru16$156 Def000030
+S A$lcdwru16$147 Def000022
+S A$lcdwru16$138 Def00000D
+S A$lcdwru16$129 Def000006
+S C$lcdwru16.c$11$2$49 Def00003D
+S A$lcdwru16$157 Def000031
+S A$lcdwru16$148 Def000024
+S A$lcdwru16$139 Def000010
+S C$lcdwru16.c$12$2$49 Def000045
+S A$lcdwru16$176 Def000045
+S A$lcdwru16$167 Def00003A
+S A$lcdwru16$158 Def000032
+S A$lcdwru16$149 Def000026
+S C$lcdwru16.c$13$2$49 Def000048
+S A$lcdwru16$159 Def000033
+S C$lcdwru16.c$16$1$48 Def00004C
+S C$lcdwru16.c$14$2$49 Def000049
+S A$lcdwru16$187 Def00004C
+S A$lcdwru16$179 Def000048
+S G$lcd_writeu16$0$0 Def000000
+S C$lcdwru16.c$5$1$48 Def000004
+S C$lcdwru16.c$3$0$0 Def000000
+S C$lcdwru16.c$7$1$48 Def00000D
+S C$lcdwru16.c$6$2$48 Def00000B
+S C$lcdwru16.c$8$2$49 Def00002A
+S C$lcdwru16.c$9$2$49 Def000035
+S _lcd_writeu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 AD 00 00 01 AC 00 00 00
+R 00 00 00 16 F1 21 08 00 05 F1 21 0C 00 05
+T 00 00 08
+R 00 00 00 16
+T 00 00 08 EC 60 41 8E 03 75 00 00 00 0A 75
+R 00 00 00 16 F1 23 09 00 04
+T 00 00 11 00 00 01 00 8E 82 8F 83 C0 05 C0 04 C0
+R 00 00 00 16 F1 23 03 00 04
+T 00 00 1C 03 12 00 00 AE 82 AF 83 D0 03 D0 04 D0
+R 00 00 00 16 02 05 00 00
+T 00 00 29 05 8E 02 EA 75 F0 0A A4 D3 9B F4 FB 8D
+R 00 00 00 16
+T 00 00 36 82 12 00 00 12 00 00 74 30 2B F5 82 12
+R 00 00 00 16 02 05 00 01 02 08 00 02
+T 00 00 43 00 00 12 00 00 1D 1C 80 BC
+R 00 00 00 16 02 03 00 05 02 06 00 02
+T 00 00 4C
+R 00 00 00 16
+T 00 00 4C 22
+R 00 00 00 16
+
+
+M:lcdwru16
+F:G$lcd_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwru16.lcd_writeu16$nrdig$1$47({1}SC:U),E,0,0
+S:Llcdwru16.lcd_writeu16$pos$1$47({1}SC:U),E,0,0
+S:Llcdwru16.lcd_writeu16$val$1$47({2}SI:U),R,0,0,[r6,r7]
+S:Llcdwru16.lcd_writeu16$v1$2$49({1}SC:U),R,0,0,[r3]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwru32
+
+;!FILE libmf/lcdwru32.asm
+XH3
+H 1A areas 4A global symbols
+M lcdwru32
+O -mmcs51 --model-small
+S __divulong_PARM_2 Ref000000
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S _lcd_writeu32_PARM_2 Def000000
+S _lcd_writeu32_PARM_3 Def000001
+S Llcdwru32.lcd_writeu32$pos$1$47 Def000001
+S Llcdwru32.lcd_writeu32$nrdig$1$47 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5A flags 20 addr 0
+S XG$lcd_writeu32$0$0 Def000059
+S A$lcdwru32$130 Def000007
+S A$lcdwru32$140 Def000010
+S A$lcdwru32$131 Def000009
+S A$lcdwru32$150 Def000023
+S A$lcdwru32$141 Def000013
+S A$lcdwru32$151 Def000025
+S A$lcdwru32$142 Def000014
+S A$lcdwru32$133 Def00000B
+S A$lcdwru32$124 Def000000
+S A$lcdwru32$152 Def000027
+S A$lcdwru32$143 Def000016
+S A$lcdwru32$134 Def00000C
+S A$lcdwru32$125 Def000002
+S A$lcdwru32$180 Def00004C
+S A$lcdwru32$162 Def000037
+S A$lcdwru32$153 Def00002A
+S A$lcdwru32$144 Def000018
+S A$lcdwru32$126 Def000004
+S A$lcdwru32$181 Def00004D
+S A$lcdwru32$172 Def000042
+S A$lcdwru32$163 Def000039
+S A$lcdwru32$154 Def00002C
+S A$lcdwru32$145 Def00001A
+S A$lcdwru32$127 Def000006
+S A$lcdwru32$191 Def000056
+S A$lcdwru32$182 Def00004F
+S A$lcdwru32$173 Def000044
+S A$lcdwru32$164 Def00003A
+S A$lcdwru32$155 Def00002E
+S A$lcdwru32$146 Def00001C
+S A$lcdwru32$137 Def00000E
+S C$lcdwru32.c$10$2$49 Def000047
+S A$lcdwru32$192 Def000057
+S A$lcdwru32$165 Def00003D
+S A$lcdwru32$156 Def000030
+S A$lcdwru32$147 Def00001E
+S C$lcdwru32.c$11$2$49 Def00004A
+S A$lcdwru32$166 Def00003E
+S A$lcdwru32$157 Def000031
+S A$lcdwru32$148 Def000020
+S C$lcdwru32.c$12$2$49 Def000052
+S A$lcdwru32$185 Def000052
+S A$lcdwru32$176 Def000047
+S A$lcdwru32$167 Def00003F
+S A$lcdwru32$158 Def000033
+S A$lcdwru32$149 Def000021
+S C$lcdwru32.c$13$2$49 Def000055
+S A$lcdwru32$168 Def000040
+S A$lcdwru32$159 Def000035
+S C$lcdwru32.c$16$1$48 Def000059
+S C$lcdwru32.c$14$2$49 Def000056
+S A$lcdwru32$196 Def000059
+S A$lcdwru32$169 Def000041
+S A$lcdwru32$188 Def000055
+S A$lcdwru32$179 Def00004A
+S G$lcd_writeu32$0$0 Def000000
+S C$lcdwru32.c$5$1$48 Def000007
+S C$lcdwru32.c$3$0$0 Def000000
+S C$lcdwru32.c$7$1$48 Def000010
+S C$lcdwru32.c$6$2$48 Def00000E
+S C$lcdwru32.c$8$2$49 Def000037
+S C$lcdwru32.c$9$2$49 Def000042
+S _lcd_writeu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 01 AA
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0A 00 00 00
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B EA 60 4B 8C 01 75 00 00 00 0A E4 F5
+R 00 00 00 16 F1 23 09 00 00
+T 00 00 15 00 00 01 F5 00 00 02 F5
+R 00 00 00 16 F1 23 03 00 00 F1 23 07 00 00
+T 00 00 19 00 00 03 8C 82 8D 83 8E F0 EF C0 03 C0
+R 00 00 00 16 F1 23 03 00 00
+T 00 00 24 02 C0 01 12 00 00 AC 82 AD 83 AE F0 FF
+R 00 00 00 16 02 07 00 04
+T 00 00 31 D0 01 D0 02 D0 03 8C 00 E8 75 F0 0A A4
+R 00 00 00 16
+T 00 00 3E D3 99 F4 F9 8B 82 12 00 00 12 00 00 74
+R 00 00 00 16 02 0A 00 01 02 0D 00 02
+T 00 00 4B 30 29 F5 82 12 00 00 12 00 00 1B 1A 80
+R 00 00 00 16 02 08 00 05 02 0B 00 02
+T 00 00 58 B2
+R 00 00 00 16
+T 00 00 59
+R 00 00 00 16
+T 00 00 59 22
+R 00 00 00 16
+
+
+M:lcdwru32
+F:G$lcd_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwru32.lcd_writeu32$nrdig$1$47({1}SC:U),E,0,0
+S:Llcdwru32.lcd_writeu32$pos$1$47({1}SC:U),E,0,0
+S:Llcdwru32.lcd_writeu32$val$1$47({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Llcdwru32.lcd_writeu32$v1$2$49({1}SC:U),R,0,0,[r1]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrhexu16
+
+;!FILE libmf/lcdwrhexu16.asm
+XH3
+H 1A areas 3F global symbols
+M lcdwrhexu16
+O -mmcs51 --model-small
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S _lcd_writehexu16_PARM_2 Def000000
+S _lcd_writehexu16_PARM_3 Def000001
+S Llcdwrhexu16.lcd_writehexu16$pos$1$47 Def000001
+S Llcdwrhexu16.lcd_writehexu16$nrdig$1$47 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 41 flags 20 addr 0
+S XG$lcd_writehexu16$0$0 Def000040
+S A$lcdwrhexu16$140 Def00000F
+S A$lcdwrhexu16$131 Def000008
+S A$lcdwrhexu16$141 Def000010
+S A$lcdwrhexu16$132 Def000009
+S A$lcdwrhexu16$160 Def000023
+S A$lcdwrhexu16$142 Def000011
+S A$lcdwrhexu16$124 Def000000
+S A$lcdwrhexu16$161 Def000025
+S A$lcdwrhexu16$152 Def00001B
+S A$lcdwrhexu16$143 Def000013
+S A$lcdwrhexu16$125 Def000002
+S A$lcdwrhexu16$180 Def000039
+S A$lcdwrhexu16$171 Def00002E
+S A$lcdwrhexu16$162 Def000027
+S A$lcdwrhexu16$144 Def000014
+S A$lcdwrhexu16$135 Def00000B
+S A$lcdwrhexu16$163 Def000028
+S A$lcdwrhexu16$145 Def000015
+S A$lcdwrhexu16$191 Def000040
+S A$lcdwrhexu16$155 Def00001E
+S A$lcdwrhexu16$146 Def000017
+S A$lcdwrhexu16$128 Def000004
+S C$lcdwrhexu16.c$10$2$49 Def000023
+S A$lcdwrhexu16$183 Def00003C
+S A$lcdwrhexu16$174 Def000031
+S A$lcdwrhexu16$147 Def000018
+S A$lcdwrhexu16$138 Def00000D
+S A$lcdwrhexu16$129 Def000006
+S C$lcdwrhexu16.c$11$2$49 Def000029
+S A$lcdwrhexu16$175 Def000033
+S A$lcdwrhexu16$157 Def000021
+S A$lcdwrhexu16$148 Def000019
+S A$lcdwrhexu16$139 Def00000E
+S C$lcdwrhexu16.c$12$2$49 Def00002E
+S A$lcdwrhexu16$176 Def000034
+S A$lcdwrhexu16$167 Def000029
+S A$lcdwrhexu16$149 Def00001A
+S C$lcdwrhexu16.c$13$2$49 Def000031
+S A$lcdwrhexu16$186 Def00003D
+S A$lcdwrhexu16$177 Def000036
+S A$lcdwrhexu16$168 Def00002B
+S C$lcdwrhexu16.c$14$2$49 Def000039
+S A$lcdwrhexu16$187 Def00003E
+S C$lcdwrhexu16.c$15$2$49 Def00003C
+S C$lcdwrhexu16.c$18$1$48 Def000040
+S C$lcdwrhexu16.c$16$2$49 Def00003D
+S G$lcd_writehexu16$0$0 Def000000
+S C$lcdwrhexu16.c$5$1$48 Def000004
+S C$lcdwrhexu16.c$3$0$0 Def000000
+S C$lcdwrhexu16.c$6$2$48 Def00000B
+S C$lcdwrhexu16.c$7$2$49 Def00000D
+S C$lcdwrhexu16.c$8$2$49 Def00001B
+S C$lcdwrhexu16.c$9$2$49 Def00001E
+S _lcd_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 AD 00 00 01 AC 00 00 00
+R 00 00 00 16 F1 21 08 00 05 F1 21 0C 00 05
+T 00 00 08
+R 00 00 00 16
+T 00 00 08 EC 60 35 8E 03 EF C4 CE C4 54 0F 6E CE
+R 00 00 00 16
+T 00 00 15 54 0F CE 6E CE FF 53 03 0F BB 0A 00
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 40 06 8B 02 74 07 2A FB
+R 00 00 00 16
+T 00 00 29
+R 00 00 00 16
+T 00 00 29 8D 82 12 00 00 12 00 00 74 30 2B F5 82
+R 00 00 00 16 02 06 00 00 02 09 00 01
+T 00 00 36 12 00 00 12 00 00 1D 1C 80 C8
+R 00 00 00 16 02 04 00 03 02 07 00 01
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 22
+R 00 00 00 16
+
+
+M:lcdwrhexu16
+F:G$lcd_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrhexu16.lcd_writehexu16$nrdig$1$47({1}SC:U),E,0,0
+S:Llcdwrhexu16.lcd_writehexu16$pos$1$47({1}SC:U),E,0,0
+S:Llcdwrhexu16.lcd_writehexu16$val$1$47({2}SI:U),R,0,0,[r6,r7]
+S:Llcdwrhexu16.lcd_writehexu16$v1$2$49({1}SC:U),R,0,0,[r3]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrhexu32
+
+;!FILE libmf/lcdwrhexu32.asm
+XH3
+H 1A areas 52 global symbols
+M lcdwrhexu32
+O -mmcs51 --model-small
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S _lcd_writehexu32_PARM_2 Def000000
+S _lcd_writehexu32_PARM_3 Def000001
+S Llcdwrhexu32.lcd_writehexu32$pos$1$47 Def000001
+S Llcdwrhexu32.lcd_writehexu32$nrdig$1$47 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 58 flags 20 addr 0
+S XG$lcd_writehexu32$0$0 Def000057
+S A$lcdwrhexu32$210 Def000057
+S A$lcdwrhexu32$202 Def000053
+S A$lcdwrhexu32$130 Def000007
+S A$lcdwrhexu32$140 Def000010
+S A$lcdwrhexu32$131 Def000009
+S A$lcdwrhexu32$150 Def00001C
+S A$lcdwrhexu32$141 Def000011
+S A$lcdwrhexu32$205 Def000054
+S A$lcdwrhexu32$160 Def000027
+S A$lcdwrhexu32$151 Def00001D
+S A$lcdwrhexu32$142 Def000012
+S A$lcdwrhexu32$133 Def00000B
+S A$lcdwrhexu32$124 Def000000
+S A$lcdwrhexu32$206 Def000055
+S A$lcdwrhexu32$161 Def000028
+S A$lcdwrhexu32$152 Def00001E
+S A$lcdwrhexu32$143 Def000013
+S A$lcdwrhexu32$134 Def00000C
+S A$lcdwrhexu32$125 Def000002
+S A$lcdwrhexu32$180 Def00003C
+S A$lcdwrhexu32$171 Def000032
+S A$lcdwrhexu32$162 Def00002A
+S A$lcdwrhexu32$153 Def00001F
+S A$lcdwrhexu32$144 Def000014
+S A$lcdwrhexu32$126 Def000004
+S A$lcdwrhexu32$190 Def000045
+S A$lcdwrhexu32$181 Def00003E
+S A$lcdwrhexu32$163 Def00002B
+S A$lcdwrhexu32$154 Def000020
+S A$lcdwrhexu32$145 Def000016
+S A$lcdwrhexu32$127 Def000006
+S A$lcdwrhexu32$182 Def00003F
+S A$lcdwrhexu32$164 Def00002C
+S A$lcdwrhexu32$155 Def000022
+S A$lcdwrhexu32$146 Def000017
+S A$lcdwrhexu32$137 Def00000E
+S C$lcdwrhexu32.c$10$2$49 Def00003A
+S A$lcdwrhexu32$174 Def000035
+S A$lcdwrhexu32$165 Def00002E
+S A$lcdwrhexu32$156 Def000023
+S A$lcdwrhexu32$147 Def000018
+S C$lcdwrhexu32.c$11$2$49 Def000040
+S A$lcdwrhexu32$193 Def000048
+S A$lcdwrhexu32$166 Def00002F
+S A$lcdwrhexu32$157 Def000024
+S A$lcdwrhexu32$148 Def00001A
+S C$lcdwrhexu32.c$12$2$49 Def000045
+S A$lcdwrhexu32$194 Def00004A
+S A$lcdwrhexu32$176 Def000038
+S A$lcdwrhexu32$167 Def000030
+S A$lcdwrhexu32$158 Def000025
+S A$lcdwrhexu32$149 Def00001B
+S C$lcdwrhexu32.c$13$2$49 Def000048
+S A$lcdwrhexu32$195 Def00004B
+S A$lcdwrhexu32$186 Def000040
+S A$lcdwrhexu32$168 Def000031
+S A$lcdwrhexu32$159 Def000026
+S C$lcdwrhexu32.c$14$2$49 Def000050
+S A$lcdwrhexu32$196 Def00004D
+S A$lcdwrhexu32$187 Def000042
+S C$lcdwrhexu32.c$15$2$49 Def000053
+S A$lcdwrhexu32$179 Def00003A
+S C$lcdwrhexu32.c$18$1$48 Def000057
+S C$lcdwrhexu32.c$16$2$49 Def000054
+S A$lcdwrhexu32$199 Def000050
+S G$lcd_writehexu32$0$0 Def000000
+S C$lcdwrhexu32.c$5$1$48 Def000007
+S C$lcdwrhexu32.c$3$0$0 Def000000
+S C$lcdwrhexu32.c$6$2$48 Def00000E
+S C$lcdwrhexu32.c$7$2$49 Def000010
+S C$lcdwrhexu32.c$8$2$49 Def000032
+S C$lcdwrhexu32.c$9$2$49 Def000035
+S _lcd_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 01 AA
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0A 00 00 00
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B EA 60 49 8C 01 ED C4 CC C4 54 0F 6C CC
+R 00 00 00 16
+T 00 00 18 54 0F CC 6C CC FD EE C4 54 F0 4D FD EF
+R 00 00 00 16
+T 00 00 25 C4 CE C4 54 0F 6E CE 54 0F CE 6E CE FF
+R 00 00 00 16
+T 00 00 32 53 01 0F B9 0A 00
+R 00 00 00 16
+T 00 00 38
+R 00 00 00 16
+T 00 00 38 40 06 89 00 74 07 28 F9
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 8B 82 12 00 00 12 00 00 74 30 29 F5 82
+R 00 00 00 16 02 06 00 00 02 09 00 01
+T 00 00 4D 12 00 00 12 00 00 1B 1A 80 B4
+R 00 00 00 16 02 04 00 03 02 07 00 01
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 22
+R 00 00 00 16
+
+
+M:lcdwrhexu32
+F:G$lcd_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrhexu32.lcd_writehexu32$nrdig$1$47({1}SC:U),E,0,0
+S:Llcdwrhexu32.lcd_writehexu32$pos$1$47({1}SC:U),E,0,0
+S:Llcdwrhexu32.lcd_writehexu32$val$1$47({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Llcdwrhexu32.lcd_writehexu32$v1$2$49({1}SC:U),R,0,0,[r1]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrnum16
+
+;!FILE libmf/lcduwrnum16.asm
+XH3
+H 1A areas CD global symbols
+M lcduwrnum16
+O -mmcs51 --model-small
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _bp Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11B flags 20 addr 0
+S C$lcduwrnum16.c$8$0$0 Def000000
+S G$lcd_writenum16$0$0 Def000000
+S _lcd_writenum16 Def000000
+S XG$lcd_writenum16$0$0 Def00011A
+S A$lcduwrnum16$300 Def0000CA
+S A$lcduwrnum16$120 Def000000
+S A$lcduwrnum16$310 Def0000D0
+S A$lcduwrnum16$220 Def000068
+S A$lcduwrnum16$211 Def000061
+S A$lcduwrnum16$202 Def000058
+S A$lcduwrnum16$130 Def00000D
+S A$lcduwrnum16$121 Def000002
+S C$lcduwrnum16.c$30$1$50 Def00006A
+S A$lcduwrnum16$311 Def0000D1
+S A$lcduwrnum16$203 Def000059
+S A$lcduwrnum16$140 Def000018
+S A$lcduwrnum16$122 Def000005
+S C$lcduwrnum16.c$31$1$50 Def00006C
+S C$lcduwrnum16.c$22$1$50 Def000051
+S A$lcduwrnum16$330 Def0000E2
+S A$lcduwrnum16$303 Def0000CD
+S A$lcduwrnum16$240 Def00007A
+S A$lcduwrnum16$231 Def00006E
+S A$lcduwrnum16$150 Def000026
+S A$lcduwrnum16$141 Def00001A
+S A$lcduwrnum16$123 Def000007
+S C$lcduwrnum16.c$23$1$50 Def000057
+S C$lcduwrnum16.c$20$2$52 Def00004F
+S A$lcduwrnum16$340 Def0000ED
+S A$lcduwrnum16$331 Def0000E5
+S A$lcduwrnum16$322 Def0000DA
+S A$lcduwrnum16$250 Def00008C
+S A$lcduwrnum16$241 Def00007C
+S A$lcduwrnum16$232 Def000070
+S A$lcduwrnum16$223 Def00006A
+S A$lcduwrnum16$160 Def000033
+S A$lcduwrnum16$151 Def000028
+S A$lcduwrnum16$142 Def00001B
+S A$lcduwrnum16$133 Def00000F
+S A$lcduwrnum16$124 Def000009
+S C$lcduwrnum16.c$24$1$50 Def000058
+S A$lcduwrnum16$350 Def0000FC
+S A$lcduwrnum16$341 Def0000EE
+S A$lcduwrnum16$314 Def0000D4
+S A$lcduwrnum16$260 Def000099
+S A$lcduwrnum16$251 Def00008D
+S A$lcduwrnum16$242 Def00007E
+S A$lcduwrnum16$233 Def000072
+S A$lcduwrnum16$215 Def000062
+S A$lcduwrnum16$206 Def00005C
+S A$lcduwrnum16$170 Def00003B
+S A$lcduwrnum16$161 Def000034
+S A$lcduwrnum16$152 Def000029
+S A$lcduwrnum16$134 Def000011
+S C$lcduwrnum16.c$16$1$50 Def00001D
+S A$lcduwrnum16$351 Def0000FF
+S A$lcduwrnum16$342 Def0000F0
+S A$lcduwrnum16$315 Def0000D5
+S A$lcduwrnum16$306 Def0000CE
+S A$lcduwrnum16$270 Def0000A5
+S A$lcduwrnum16$261 Def00009C
+S A$lcduwrnum16$252 Def00008F
+S A$lcduwrnum16$243 Def00007F
+S A$lcduwrnum16$234 Def000073
+S A$lcduwrnum16$207 Def00005D
+S A$lcduwrnum16$180 Def000049
+S A$lcduwrnum16$171 Def00003D
+S A$lcduwrnum16$162 Def000035
+S A$lcduwrnum16$153 Def00002A
+S A$lcduwrnum16$135 Def000013
+S A$lcduwrnum16$370 Def000113
+S A$lcduwrnum16$343 Def0000F2
+S A$lcduwrnum16$334 Def0000E8
+S A$lcduwrnum16$325 Def0000DD
+S A$lcduwrnum16$244 Def000081
+S A$lcduwrnum16$208 Def00005F
+S A$lcduwrnum16$181 Def00004A
+S A$lcduwrnum16$163 Def000036
+S A$lcduwrnum16$154 Def00002B
+S A$lcduwrnum16$145 Def00001D
+S A$lcduwrnum16$136 Def000014
+S A$lcduwrnum16$127 Def00000B
+S A$lcduwrnum16$371 Def000115
+S A$lcduwrnum16$344 Def0000F3
+S A$lcduwrnum16$326 Def0000DE
+S A$lcduwrnum16$290 Def0000BA
+S A$lcduwrnum16$281 Def0000AF
+S A$lcduwrnum16$263 Def00009E
+S A$lcduwrnum16$245 Def000082
+S A$lcduwrnum16$227 Def00006C
+S A$lcduwrnum16$218 Def000065
+S A$lcduwrnum16$182 Def00004B
+S A$lcduwrnum16$164 Def000037
+S A$lcduwrnum16$155 Def00002D
+S A$lcduwrnum16$146 Def00001E
+S C$lcduwrnum16.c$64$1$50 Def00010C
+S C$lcduwrnum16.c$51$3$61 Def0000D4
+S C$lcduwrnum16.c$50$2$54 Def0000D0
+S C$lcduwrnum16.c$32$2$54 Def00006E
+S C$lcduwrnum16.c$28$1$50 Def000062
+S C$lcduwrnum16.c$19$1$50 Def00003F
+S C$lcduwrnum16.c$17$2$51 Def000030
+S A$lcduwrnum16$372 Def000118
+S A$lcduwrnum16$363 Def00010C
+S A$lcduwrnum16$354 Def000102
+S A$lcduwrnum16$345 Def0000F5
+S A$lcduwrnum16$318 Def0000D8
+S A$lcduwrnum16$273 Def0000A7
+S A$lcduwrnum16$264 Def00009F
+S A$lcduwrnum16$255 Def000091
+S A$lcduwrnum16$246 Def000084
+S A$lcduwrnum16$237 Def000075
+S A$lcduwrnum16$219 Def000066
+S A$lcduwrnum16$192 Def000051
+S A$lcduwrnum16$183 Def00004C
+S A$lcduwrnum16$165 Def000038
+S A$lcduwrnum16$147 Def000021
+S C$lcduwrnum16.c$65$1$50 Def000113
+S C$lcduwrnum16.c$60$2$54 Def0000FB
+S C$lcduwrnum16.c$52$3$61 Def0000D8
+S C$lcduwrnum16.c$33$2$54 Def000075
+S C$lcduwrnum16.c$29$1$50 Def000065
+S C$lcduwrnum16.c$25$2$53 Def00005C
+S C$lcduwrnum16.c$18$2$51 Def00003B
+S A$lcduwrnum16$364 Def00010E
+S A$lcduwrnum16$355 Def000105
+S A$lcduwrnum16$346 Def0000F8
+S A$lcduwrnum16$274 Def0000A8
+S A$lcduwrnum16$256 Def000093
+S A$lcduwrnum16$247 Def000087
+S A$lcduwrnum16$238 Def000077
+S A$lcduwrnum16$193 Def000052
+S A$lcduwrnum16$184 Def00004D
+S A$lcduwrnum16$175 Def00003F
+S A$lcduwrnum16$166 Def000039
+S A$lcduwrnum16$148 Def000023
+S A$lcduwrnum16$139 Def000016
+S C$lcduwrnum16.c$66$1$50 Def00011A
+S C$lcduwrnum16.c$53$3$61 Def0000DA
+S C$lcduwrnum16.c$34$2$54 Def000091
+S C$lcduwrnum16.c$26$2$53 Def000061
+S C$lcduwrnum16.c$10$1$0 Def00000B
+S A$lcduwrnum16$356 Def000108
+S A$lcduwrnum16$338 Def0000E9
+S A$lcduwrnum16$329 Def0000E0
+S A$lcduwrnum16$293 Def0000BD
+S A$lcduwrnum16$284 Def0000B1
+S A$lcduwrnum16$257 Def000095
+S A$lcduwrnum16$248 Def000089
+S A$lcduwrnum16$239 Def000079
+S A$lcduwrnum16$194 Def000054
+S A$lcduwrnum16$176 Def000040
+S A$lcduwrnum16$167 Def00003A
+S A$lcduwrnum16$158 Def000030
+S A$lcduwrnum16$149 Def000025
+S C$lcduwrnum16.c$54$3$61 Def0000DD
+S A$lcduwrnum16$375 Def00011A
+S A$lcduwrnum16$366 Def000110
+S A$lcduwrnum16$339 Def0000EB
+S A$lcduwrnum16$294 Def0000BE
+S A$lcduwrnum16$267 Def0000A2
+S A$lcduwrnum16$258 Def000096
+S A$lcduwrnum16$249 Def00008A
+S A$lcduwrnum16$195 Def000055
+S A$lcduwrnum16$177 Def000043
+S A$lcduwrnum16$159 Def000032
+S C$lcduwrnum16.c$44$6$60 Def0000C4
+S C$lcduwrnum16.c$12$1$0 Def00000D
+S A$lcduwrnum16$349 Def0000FB
+S A$lcduwrnum16$295 Def0000C1
+S A$lcduwrnum16$277 Def0000AB
+S A$lcduwrnum16$268 Def0000A3
+S A$lcduwrnum16$259 Def000097
+S A$lcduwrnum16$178 Def000044
+S C$lcduwrnum16.c$42$4$56 Def0000B4
+S C$lcduwrnum16.c$40$5$57 Def0000B1
+S C$lcduwrnum16.c$35$3$55 Def0000A2
+S C$lcduwrnum16.c$13$1$0 Def00000F
+S A$lcduwrnum16$359 Def00010B
+S A$lcduwrnum16$278 Def0000AC
+S A$lcduwrnum16$269 Def0000A4
+S A$lcduwrnum16$188 Def00004F
+S A$lcduwrnum16$179 Def000047
+S C$lcduwrnum16.c$62$3$65 Def00010B
+S C$lcduwrnum16.c$43$4$56 Def0000BD
+S C$lcduwrnum16.c$14$1$0 Def000016
+S A$lcduwrnum16$288 Def0000B4
+S A$lcduwrnum16$198 Def000057
+S C$lcduwrnum16.c$61$4$66 Def000102
+S C$lcduwrnum16.c$56$4$62 Def0000E8
+S C$lcduwrnum16.c$37$3$55 Def0000A7
+S A$lcduwrnum16$298 Def0000C4
+S A$lcduwrnum16$289 Def0000B7
+S C$lcduwrnum16.c$55$5$63 Def0000E0
+S A$lcduwrnum16$299 Def0000C7
+S C$lcduwrnum16.c$59$2$54 Def0000E9
+S C$lcduwrnum16.c$47$4$56 Def0000CE
+S C$lcduwrnum16.c$38$4$56 Def0000AB
+S C$lcduwrnum16.c$45$5$59 Def0000CD
+S C$lcduwrnum16.c$39$5$57 Def0000AF
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 C0 82 C0 83
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 03
+T 00 00 09 05 81 7D 00 7C 05 E5 00 00 00 24 FC F8
+R 00 00 00 16 F1 23 0A 00 03
+T 00 00 14 86 03 E5 00 00 00 24 FD F8 86 02 EB 30
+R 00 00 00 16 F1 23 06 00 03
+T 00 00 1F E0 1E C0 04 A8 00 00 00 08 86 04 08 E6
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 2A FF D0 04 30 E7 0F A8 00 00 00 08 C3 E4
+R 00 00 00 16 F1 23 0A 00 03
+T 00 00 35 96 F6 08 E4 96 F6 7D 2D 80 12
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F EB 20 E2 0C EB 30 E1 0A A8 00 00 00 08
+R 00 00 00 16 F1 23 0C 00 03
+T 00 00 4A E6 08 46 60 02
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F 7D 2B
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 ED 60 04 EA 60 01 1A
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 30 E4 06 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 53 03 3F EA 24 FA 50 02 8A 04
+R 00 00 00 16
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C 8C 07
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E E5 00 00 00 24 03 F8 A6 07 E5 00 00 00
+R 00 00 00 16 F1 23 04 00 03 F1 23 0D 00 03
+T 00 00 77 24 03 FE C0 06 A8 00 00 00 08 86 82 08
+R 00 00 00 16 F1 23 09 00 03
+T 00 00 82 86 83 12 00 00 A8 00 00 00 08 A6 82 08
+R 00 00 00 16 02 06 00 02 F1 23 09 00 03
+T 00 00 8D A6 83 15 81 E5 00 00 00 24 03 F8 E6 70
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 98 37 BF 01 02 80 32
+R 00 00 00 16
+T 00 00 9E
+R 00 00 00 16
+T 00 00 9E EB 20 E7 2E C3 EA 9F 40 65 EB 20 E3 25
+R 00 00 00 16
+T 00 00 AB EB 20 E6 05 8F 02 43 03 40
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 75 82 20 12 00 00 12 00 00 EB 30 E4 4B
+R 00 00 00 16 02 07 00 04 02 0A 00 00
+T 00 00 C1 BF 04 48 75 82 20 12 00 00 12 00 00 0A
+R 00 00 00 16 02 0A 00 04 02 0D 00 00
+T 00 00 CE 80 3C
+R 00 00 00 16
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 EB 20 E7 15 EB 20 E6 02 8F 02
+R 00 00 00 16
+T 00 00 DA
+R 00 00 00 16
+T 00 00 DA 43 03 C8 ED 60 09 8D 82 12 00 00 12
+R 00 00 00 16 02 0C 00 04
+T 00 00 E6 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 E9
+R 00 00 00 16
+T 00 00 E9 E5 00 00 00 24 03 F8 86 06 74 30 2E F5
+R 00 00 00 16 F1 23 04 00 03
+T 00 00 F4 82 12 00 00 12 00 00 EB 30 E4 0D BF 04
+R 00 00 00 16 02 05 00 04 02 08 00 00
+T 00 01 01 0A 75 82 27 12 00 00 12 00 00 0A
+R 00 00 00 16 02 08 00 04 02 0B 00 00
+T 00 01 0C
+R 00 00 00 16
+T 00 01 0C DF 02 80 03
+R 00 00 00 16
+T 00 01 10
+R 00 00 00 16
+T 00 01 10 02 00 6E
+R 00 00 00 16 00 04 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 8A 82 85 00 00 00 81 D0 00 00 00 22
+R 00 00 00 16 F1 23 06 00 03 F1 23 0B 00 03
+
+
+M:lcduwrnum16
+F:G$lcd_writenum16$0$0({2}DF,SC:U),Z,0,3,0,0,0
+S:Llcduwrnum16.lcd_writenum16$nrdig1$1$49({1}SC:U),B,1,-3
+S:Llcduwrnum16.lcd_writenum16$flags1$1$49({1}SC:U),B,1,-4
+S:Llcduwrnum16.lcd_writenum16$val$1$49({2}SI:U),B,1,1
+S:Llcduwrnum16.lcd_writenum16$ch$1$50({1}SC:S),R,0,0,[r5]
+S:Llcduwrnum16.lcd_writenum16$d$1$50({1}SC:U),B,1,3
+S:Llcduwrnum16.lcd_writenum16$cnt$1$50({1}SC:U),R,0,0,[r4]
+S:Llcduwrnum16.lcd_writenum16$flags$1$50({1}SC:U),R,0,0,[r3]
+S:Llcduwrnum16.lcd_writenum16$nrdig$1$50({1}SC:U),R,0,0,[r2]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrnum32
+
+;!FILE libmf/lcduwrnum32.asm
+XH3
+H 1A areas D1 global symbols
+M lcduwrnum32
+O -mmcs51 --model-small
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 8 flags 0 addr 0
+S Llcduwrnum32.lcd_writenum32$nrdig1$1$49 Def000000
+S Llcduwrnum32.lcd_writenum32$d$1$50 Def000006
+S _lcd_writenum32_PARM_2 Def000000
+S _lcd_writenum32_PARM_3 Def000001
+S Llcduwrnum32.lcd_writenum32$cnt$1$50 Def000007
+S Llcduwrnum32.lcd_writenum32$flags1$1$49 Def000001
+S Llcduwrnum32.lcd_writenum32$val$1$49 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 12E flags 20 addr 0
+S C$lcduwrnum32.c$8$0$0 Def000000
+S G$lcd_writenum32$0$0 Def000000
+S _lcd_writenum32 Def000000
+S XG$lcd_writenum32$0$0 Def00012D
+S A$lcduwrnum32$300 Def0000B8
+S A$lcduwrnum32$201 Def000051
+S A$lcduwrnum32$400 Def00012B
+S A$lcduwrnum32$220 Def000061
+S A$lcduwrnum32$211 Def000058
+S A$lcduwrnum32$202 Def000052
+S A$lcduwrnum32$320 Def0000D4
+S A$lcduwrnum32$212 Def000059
+S A$lcduwrnum32$203 Def000054
+S A$lcduwrnum32$140 Def000009
+S C$lcduwrnum32.c$22$1$50 Def000051
+S A$lcduwrnum32$312 Def0000C6
+S A$lcduwrnum32$303 Def0000BA
+S A$lcduwrnum32$204 Def000055
+S C$lcduwrnum32.c$32$1$50 Def00006E
+S C$lcduwrnum32.c$23$1$50 Def000057
+S C$lcduwrnum32.c$20$2$52 Def00004F
+S A$lcduwrnum32$403 Def00012D
+S A$lcduwrnum32$340 Def0000E7
+S A$lcduwrnum32$313 Def0000C7
+S A$lcduwrnum32$250 Def000076
+S A$lcduwrnum32$160 Def00001E
+S C$lcduwrnum32.c$33$1$50 Def000071
+S C$lcduwrnum32.c$24$1$50 Def000058
+S A$lcduwrnum32$341 Def0000E8
+S A$lcduwrnum32$332 Def0000E1
+S A$lcduwrnum32$314 Def0000CA
+S A$lcduwrnum32$242 Def00006E
+S A$lcduwrnum32$233 Def000068
+S A$lcduwrnum32$224 Def000062
+S A$lcduwrnum32$215 Def00005C
+S A$lcduwrnum32$170 Def00002B
+S A$lcduwrnum32$161 Def000020
+S A$lcduwrnum32$152 Def000012
+S A$lcduwrnum32$143 Def00000B
+S C$lcduwrnum32.c$70$1$50 Def00012D
+S C$lcduwrnum32.c$34$1$50 Def000076
+S C$lcduwrnum32.c$30$2$53 Def00006D
+S C$lcduwrnum32.c$16$1$50 Def000014
+S A$lcduwrnum32$360 Def0000FB
+S A$lcduwrnum32$351 Def0000F0
+S A$lcduwrnum32$324 Def0000D7
+S A$lcduwrnum32$315 Def0000CD
+S A$lcduwrnum32$270 Def000094
+S A$lcduwrnum32$261 Def00007C
+S A$lcduwrnum32$234 Def000069
+S A$lcduwrnum32$225 Def000063
+S A$lcduwrnum32$216 Def00005D
+S A$lcduwrnum32$207 Def000057
+S A$lcduwrnum32$180 Def000039
+S A$lcduwrnum32$171 Def00002D
+S A$lcduwrnum32$162 Def000021
+S C$lcduwrnum32.c$35$1$50 Def000078
+S A$lcduwrnum32$352 Def0000F1
+S A$lcduwrnum32$325 Def0000DA
+S A$lcduwrnum32$307 Def0000BD
+S A$lcduwrnum32$280 Def0000A4
+S A$lcduwrnum32$271 Def000097
+S A$lcduwrnum32$262 Def00007E
+S A$lcduwrnum32$235 Def00006B
+S A$lcduwrnum32$226 Def000065
+S A$lcduwrnum32$217 Def00005F
+S A$lcduwrnum32$190 Def000047
+S A$lcduwrnum32$181 Def00003B
+S A$lcduwrnum32$172 Def00002F
+S A$lcduwrnum32$380 Def000117
+S A$lcduwrnum32$344 Def0000EB
+S A$lcduwrnum32$326 Def0000DD
+S A$lcduwrnum32$317 Def0000CF
+S A$lcduwrnum32$308 Def0000C0
+S A$lcduwrnum32$281 Def0000A5
+S A$lcduwrnum32$272 Def000099
+S A$lcduwrnum32$263 Def000080
+S A$lcduwrnum32$254 Def000078
+S A$lcduwrnum32$245 Def000071
+S A$lcduwrnum32$191 Def000049
+S A$lcduwrnum32$173 Def000030
+S A$lcduwrnum32$155 Def000014
+S A$lcduwrnum32$146 Def00000D
+S A$lcduwrnum32$137 Def000000
+S C$lcduwrnum32.c$19$1$50 Def00003D
+S C$lcduwrnum32.c$17$2$51 Def000024
+S A$lcduwrnum32$372 Def000109
+S A$lcduwrnum32$336 Def0000E3
+S A$lcduwrnum32$318 Def0000D2
+S A$lcduwrnum32$309 Def0000C3
+S A$lcduwrnum32$264 Def000083
+S A$lcduwrnum32$246 Def000072
+S A$lcduwrnum32$192 Def00004B
+S A$lcduwrnum32$174 Def000032
+S A$lcduwrnum32$165 Def000024
+S A$lcduwrnum32$156 Def000015
+S A$lcduwrnum32$138 Def000003
+S C$lcduwrnum32.c$25$2$53 Def00005C
+S C$lcduwrnum32.c$18$2$51 Def000039
+S A$lcduwrnum32$373 Def00010A
+S A$lcduwrnum32$364 Def0000FC
+S A$lcduwrnum32$355 Def0000F3
+S A$lcduwrnum32$337 Def0000E4
+S A$lcduwrnum32$292 Def0000B0
+S A$lcduwrnum32$265 Def000086
+S A$lcduwrnum32$247 Def000074
+S A$lcduwrnum32$238 Def00006D
+S A$lcduwrnum32$229 Def000067
+S A$lcduwrnum32$193 Def00004D
+S A$lcduwrnum32$175 Def000034
+S A$lcduwrnum32$166 Def000025
+S A$lcduwrnum32$157 Def000018
+S A$lcduwrnum32$139 Def000006
+S C$lcduwrnum32.c$60$4$62 Def0000FB
+S C$lcduwrnum32.c$41$3$55 Def0000B0
+S C$lcduwrnum32.c$26$2$53 Def000061
+S C$lcduwrnum32.c$10$1$0 Def00000B
+S A$lcduwrnum32$374 Def00010D
+S A$lcduwrnum32$365 Def0000FE
+S A$lcduwrnum32$356 Def0000F5
+S A$lcduwrnum32$329 Def0000E0
+S A$lcduwrnum32$293 Def0000B1
+S A$lcduwrnum32$284 Def0000A8
+S A$lcduwrnum32$275 Def00009B
+S A$lcduwrnum32$266 Def000089
+S A$lcduwrnum32$185 Def00003D
+S A$lcduwrnum32$176 Def000035
+S A$lcduwrnum32$167 Def000026
+S A$lcduwrnum32$158 Def00001A
+S A$lcduwrnum32$149 Def000010
+S C$lcduwrnum32.c$27$2$53 Def000062
+S A$lcduwrnum32$393 Def000124
+S A$lcduwrnum32$384 Def00011A
+S A$lcduwrnum32$375 Def000110
+S A$lcduwrnum32$366 Def000100
+S A$lcduwrnum32$357 Def0000F8
+S A$lcduwrnum32$348 Def0000ED
+S A$lcduwrnum32$285 Def0000A9
+S A$lcduwrnum32$276 Def00009D
+S A$lcduwrnum32$267 Def00008B
+S A$lcduwrnum32$258 Def00007A
+S A$lcduwrnum32$186 Def00003E
+S A$lcduwrnum32$177 Def000037
+S A$lcduwrnum32$168 Def000028
+S A$lcduwrnum32$159 Def00001C
+S C$lcduwrnum32.c$68$1$50 Def000124
+S C$lcduwrnum32.c$63$2$54 Def0000FC
+S C$lcduwrnum32.c$55$3$61 Def0000E7
+S C$lcduwrnum32.c$54$2$54 Def0000E3
+S C$lcduwrnum32.c$36$2$54 Def00007A
+S C$lcduwrnum32.c$28$2$53 Def000067
+S C$lcduwrnum32.c$12$1$0 Def00000D
+S A$lcduwrnum32$394 Def000126
+S A$lcduwrnum32$385 Def00011D
+S A$lcduwrnum32$367 Def000101
+S A$lcduwrnum32$286 Def0000AA
+S A$lcduwrnum32$277 Def00009F
+S A$lcduwrnum32$268 Def00008E
+S A$lcduwrnum32$187 Def000041
+S A$lcduwrnum32$169 Def00002A
+S C$lcduwrnum32.c$69$1$50 Def00012B
+S C$lcduwrnum32.c$64$2$54 Def000109
+S C$lcduwrnum32.c$56$3$61 Def0000EB
+S C$lcduwrnum32.c$51$4$56 Def0000E1
+S C$lcduwrnum32.c$42$4$56 Def0000B4
+S C$lcduwrnum32.c$37$2$54 Def00007C
+S C$lcduwrnum32.c$29$2$53 Def000068
+S C$lcduwrnum32.c$13$1$0 Def000010
+S A$lcduwrnum32$386 Def000120
+S A$lcduwrnum32$377 Def000112
+S A$lcduwrnum32$368 Def000103
+S A$lcduwrnum32$296 Def0000B4
+S A$lcduwrnum32$287 Def0000AB
+S A$lcduwrnum32$278 Def0000A2
+S A$lcduwrnum32$269 Def000091
+S A$lcduwrnum32$197 Def00004F
+S A$lcduwrnum32$188 Def000042
+S C$lcduwrnum32.c$57$3$61 Def0000ED
+S C$lcduwrnum32.c$38$2$54 Def00009B
+S C$lcduwrnum32.c$14$1$0 Def000012
+S A$lcduwrnum32$396 Def000128
+S A$lcduwrnum32$378 Def000115
+S A$lcduwrnum32$369 Def000106
+S A$lcduwrnum32$297 Def0000B5
+S A$lcduwrnum32$288 Def0000AD
+S A$lcduwrnum32$189 Def000045
+S C$lcduwrnum32.c$58$3$61 Def0000F0
+S C$lcduwrnum32.c$43$5$57 Def0000B8
+S A$lcduwrnum32$389 Def000123
+S C$lcduwrnum32.c$65$3$65 Def00011A
+S C$lcduwrnum32.c$46$4$56 Def0000BD
+S C$lcduwrnum32.c$44$5$57 Def0000BA
+S C$lcduwrnum32.c$39$3$55 Def0000A8
+S C$lcduwrnum32.c$66$3$65 Def000123
+S C$lcduwrnum32.c$47$4$56 Def0000C6
+S C$lcduwrnum32.c$59$5$63 Def0000F3
+S C$lcduwrnum32.c$48$5$59 Def0000D7
+S C$lcduwrnum32.c$49$5$59 Def0000E0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 06
+R 00 00 00 05
+T 00 00 06
+R 00 00 00 05
+T 00 00 07
+R 00 00 00 05
+T 00 00 07
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 85 82 00 00 02 85 83 00 00 03 85 F0
+R 00 00 00 16 F1 21 05 00 05 F1 21 0A 00 05
+T 00 00 08 00 00 04 F5 00 00 05 7B 00 75
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 0E 00 00 07 0A A9 00 00 01 A8
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 13 00 00 00 E9 30 E0 25 AA 00 00 02 AD
+R 00 00 00 16 F1 21 03 00 05 F1 21 0B 00 05
+T 00 00 1B 00 00 03 AE 00 00 04 E5
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 1F 00 00 05 FF 30 E7 19 C3 E4 95 00 00 02
+R 00 00 00 16 F1 21 03 00 05 F1 21 0D 00 05
+T 00 00 28 F5 00 00 02 E4 95 00 00 03 F5
+R 00 00 00 16 F1 21 04 00 05 F1 21 09 00 05
+T 00 00 2E 00 00 03 E4 95 00 00 04 F5
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 33 00 00 04 E4 95 00 00 05 F5
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 38 00 00 05 7B 2D 80 14
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D E9 20 E2 0E E9 30 E1 0C E5 00 00 02 45
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 48 00 00 03 45 00 00 04 45
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 4C 00 00 05 60 02
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F 7B 2B
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EB 60 04 E8 60 01 18
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 E9 30 E4 12 E8 24 F6 50 01 18
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 E8 24 F9 50 01 18
+R 00 00 00 16
+T 00 00 68
+R 00 00 00 16
+T 00 00 68 E8 24 FC 50 01 18
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E 53 01 3F E8 24 F5 50 02 88 00 00 07
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 78
+R 00 00 00 16
+T 00 00 78 AF 00 00 07
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 7A
+R 00 00 00 16
+T 00 00 7A 8F 00 00 06 74 00 00 06 C0 E0 85
+R 00 00 00 16 F1 21 04 00 05 F1 01 08 00 05
+T 00 00 81 00 00 02 82 85 00 00 03 83 85
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 87 00 00 04 F0 E5 00 00 05 12
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 8C 00 00 85 82 00 00 02 85 83
+R 00 00 00 16 02 03 00 02 F1 21 07 00 05
+T 00 00 93 00 00 03 85 F0 00 00 04 F5
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 98 00 00 05 15 81 E5 00 00 06 70 44 BF 01
+R 00 00 00 16 F1 21 03 00 05 F1 21 09 00 05
+T 00 00 A1 02 80 3F
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 E9 20 E7 3B C3 E8 9F 50 03 02 01 24
+R 00 00 00 16 00 0D 00 16
+T 00 00 B0
+R 00 00 00 16
+T 00 00 B0 E9 20 E3 2F E9 20 E6 05 8F 00 43 01 40
+R 00 00 00 16
+T 00 00 BD
+R 00 00 00 16
+T 00 00 BD 75 82 20 12 00 00 12 00 00 E9 30 E4 5A
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 00 CA BF 04 02 80 08
+R 00 00 00 16
+T 00 00 CF
+R 00 00 00 16
+T 00 00 CF BF 07 02 80 03
+R 00 00 00 16
+T 00 00 D4
+R 00 00 00 16
+T 00 00 D4 BF 0A 4D
+R 00 00 00 16
+T 00 00 D7
+R 00 00 00 16
+T 00 00 D7 75 82 20 12 00 00 12 00 00 08 80 41
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 E9 20 E7 15 E9 20 E6 02 8F 00
+R 00 00 00 16
+T 00 00 ED
+R 00 00 00 16
+T 00 00 ED 43 01 C8 EB 60 09 8B 82 12 00 00 12
+R 00 00 00 16 02 0C 00 03
+T 00 00 F9 00 00 08
+R 00 00 00 16 02 03 00 00
+T 00 00 FC
+R 00 00 00 16
+T 00 00 FC AE 00 00 06 74 30 2E F5 82 12 00 00 12
+R 00 00 00 16 F1 21 04 00 05 02 0D 00 03
+T 00 01 07 00 00 E9 30 E4 17 BF 04 02 80 08
+R 00 00 00 16 02 03 00 00
+T 00 01 12
+R 00 00 00 16
+T 00 01 12 BF 07 02 80 03
+R 00 00 00 16
+T 00 01 17
+R 00 00 00 16
+T 00 01 17 BF 0A 0A
+R 00 00 00 16
+T 00 01 1A
+R 00 00 00 16
+T 00 01 1A 75 82 27 12 00 00 12 00 00 08
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 01 24
+R 00 00 00 16
+T 00 01 24 DF 02 80 03
+R 00 00 00 16
+T 00 01 28
+R 00 00 00 16
+T 00 01 28 02 00 7A
+R 00 00 00 16 00 04 00 16
+T 00 01 2B
+R 00 00 00 16
+T 00 01 2B 88 82 22
+R 00 00 00 16
+
+
+M:lcduwrnum32
+F:G$lcd_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$nrdig1$1$49({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$flags1$1$49({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$val$1$49({4}SL:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$ch$1$50({1}SC:S),R,0,0,[r3]
+S:Llcduwrnum32.lcd_writenum32$d$1$50({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$cnt$1$50({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$flags$1$50({1}SC:U),R,0,0,[r1]
+S:Llcduwrnum32.lcd_writenum32$nrdig$1$50({1}SC:U),R,0,0,[r0]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrhex16
+
+;!FILE libmf/lcduwrhex16.asm
+XH3
+H 1A areas F5 global symbols
+M lcduwrhex16
+O -mmcs51 --model-small
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _bp Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 153 flags 20 addr 0
+S _lcd_writehex16 Def000000
+S XG$lcd_writehex16$0$0 Def000152
+S A$lcduwrhex16$300 Def0000C7
+S A$lcduwrhex16$120 Def000002
+S A$lcduwrhex16$400 Def000134
+S A$lcduwrhex16$301 Def0000C9
+S A$lcduwrhex16$220 Def000074
+S A$lcduwrhex16$211 Def00006E
+S A$lcduwrhex16$202 Def000063
+S A$lcduwrhex16$121 Def000005
+S C$lcduwrhex16.c$30$1$50 Def000081
+S A$lcduwrhex16$401 Def000137
+S A$lcduwrhex16$311 Def0000D3
+S A$lcduwrhex16$302 Def0000CA
+S A$lcduwrhex16$221 Def000076
+S A$lcduwrhex16$203 Def000065
+S A$lcduwrhex16$122 Def000007
+S C$lcduwrhex16.c$31$1$50 Def000083
+S C$lcduwrhex16.c$22$1$50 Def000063
+S A$lcduwrhex16$420 Def00014B
+S A$lcduwrhex16$321 Def0000DC
+S A$lcduwrhex16$312 Def0000D4
+S A$lcduwrhex16$240 Def000083
+S A$lcduwrhex16$231 Def00007C
+S A$lcduwrhex16$204 Def000067
+S A$lcduwrhex16$150 Def000028
+S A$lcduwrhex16$141 Def00001B
+S A$lcduwrhex16$132 Def000012
+S A$lcduwrhex16$123 Def000009
+S C$lcduwrhex16.c$23$1$50 Def00006E
+S C$lcduwrhex16.c$20$2$52 Def00005C
+S A$lcduwrhex16$421 Def00014D
+S A$lcduwrhex16$322 Def0000DD
+S A$lcduwrhex16$250 Def00008E
+S A$lcduwrhex16$232 Def00007D
+S A$lcduwrhex16$205 Def000068
+S A$lcduwrhex16$151 Def00002A
+S A$lcduwrhex16$142 Def00001D
+S C$lcduwrhex16.c$24$1$50 Def00006F
+S A$lcduwrhex16$422 Def000150
+S A$lcduwrhex16$413 Def000144
+S A$lcduwrhex16$404 Def00013A
+S A$lcduwrhex16$341 Def0000F2
+S A$lcduwrhex16$332 Def0000E6
+S A$lcduwrhex16$260 Def00009B
+S A$lcduwrhex16$251 Def00008F
+S A$lcduwrhex16$233 Def00007F
+S A$lcduwrhex16$224 Def000078
+S A$lcduwrhex16$215 Def00006F
+S A$lcduwrhex16$206 Def000069
+S A$lcduwrhex16$170 Def000041
+S A$lcduwrhex16$152 Def00002B
+S A$lcduwrhex16$143 Def00001F
+S C$lcduwrhex16.c$70$1$50 Def000144
+S C$lcduwrhex16.c$16$1$50 Def000022
+S A$lcduwrhex16$414 Def000146
+S A$lcduwrhex16$405 Def00013D
+S A$lcduwrhex16$351 Def000102
+S A$lcduwrhex16$342 Def0000F3
+S A$lcduwrhex16$315 Def0000D7
+S A$lcduwrhex16$306 Def0000CB
+S A$lcduwrhex16$270 Def0000A9
+S A$lcduwrhex16$261 Def00009D
+S A$lcduwrhex16$252 Def000090
+S A$lcduwrhex16$216 Def000070
+S A$lcduwrhex16$207 Def00006B
+S A$lcduwrhex16$171 Def000042
+S A$lcduwrhex16$162 Def000038
+S A$lcduwrhex16$153 Def00002D
+S A$lcduwrhex16$144 Def000020
+S A$lcduwrhex16$135 Def000014
+S A$lcduwrhex16$126 Def00000B
+S C$lcduwrhex16.c$71$1$50 Def00014B
+S A$lcduwrhex16$406 Def000140
+S A$lcduwrhex16$370 Def00010F
+S A$lcduwrhex16$343 Def0000F6
+S A$lcduwrhex16$325 Def0000E0
+S A$lcduwrhex16$316 Def0000D8
+S A$lcduwrhex16$307 Def0000CC
+S A$lcduwrhex16$271 Def0000AA
+S A$lcduwrhex16$262 Def00009F
+S A$lcduwrhex16$253 Def000092
+S A$lcduwrhex16$244 Def000085
+S A$lcduwrhex16$208 Def00006C
+S A$lcduwrhex16$190 Def000059
+S A$lcduwrhex16$163 Def00003A
+S A$lcduwrhex16$154 Def00002E
+S A$lcduwrhex16$136 Def000016
+S A$lcduwrhex16$127 Def00000D
+S C$lcduwrhex16.c$72$1$50 Def000152
+S C$lcduwrhex16.c$40$2$54 Def0000CB
+S A$lcduwrhex16$425 Def000152
+S A$lcduwrhex16$416 Def000148
+S A$lcduwrhex16$380 Def00011A
+S A$lcduwrhex16$362 Def000109
+S A$lcduwrhex16$326 Def0000E1
+S A$lcduwrhex16$317 Def0000D9
+S A$lcduwrhex16$308 Def0000CE
+S A$lcduwrhex16$272 Def0000AB
+S A$lcduwrhex16$263 Def0000A0
+S A$lcduwrhex16$254 Def000093
+S A$lcduwrhex16$245 Def000087
+S A$lcduwrhex16$236 Def000081
+S A$lcduwrhex16$191 Def00005A
+S A$lcduwrhex16$182 Def00004C
+S A$lcduwrhex16$164 Def00003B
+S A$lcduwrhex16$155 Def000030
+S A$lcduwrhex16$137 Def000018
+S A$lcduwrhex16$128 Def00000F
+S A$lcduwrhex16$119 Def000000
+S C$lcduwrhex16.c$32$2$54 Def000085
+S C$lcduwrhex16.c$28$1$50 Def000079
+S C$lcduwrhex16.c$19$1$50 Def00004C
+S C$lcduwrhex16.c$17$2$51 Def000038
+S A$lcduwrhex16$381 Def00011C
+S A$lcduwrhex16$363 Def00010A
+S A$lcduwrhex16$354 Def000103
+S A$lcduwrhex16$336 Def0000E9
+S A$lcduwrhex16$318 Def0000DA
+S A$lcduwrhex16$309 Def0000D1
+S A$lcduwrhex16$291 Def0000BD
+S A$lcduwrhex16$282 Def0000B4
+S A$lcduwrhex16$273 Def0000AC
+S A$lcduwrhex16$264 Def0000A2
+S A$lcduwrhex16$255 Def000094
+S A$lcduwrhex16$246 Def000089
+S A$lcduwrhex16$228 Def000079
+S A$lcduwrhex16$219 Def000073
+S A$lcduwrhex16$183 Def00004D
+S A$lcduwrhex16$174 Def000043
+S A$lcduwrhex16$165 Def00003C
+S A$lcduwrhex16$156 Def000031
+S A$lcduwrhex16$147 Def000022
+S A$lcduwrhex16$138 Def000019
+S A$lcduwrhex16$129 Def000010
+S C$lcduwrhex16.c$60$3$62 Def000112
+S C$lcduwrhex16.c$51$5$60 Def000102
+S C$lcduwrhex16.c$33$2$54 Def0000B1
+S C$lcduwrhex16.c$29$1$50 Def00007C
+S C$lcduwrhex16.c$25$2$53 Def000073
+S C$lcduwrhex16.c$18$2$51 Def000043
+S A$lcduwrhex16$409 Def000143
+S A$lcduwrhex16$382 Def00011E
+S A$lcduwrhex16$373 Def000112
+S A$lcduwrhex16$346 Def0000F9
+S A$lcduwrhex16$337 Def0000EC
+S A$lcduwrhex16$292 Def0000BF
+S A$lcduwrhex16$274 Def0000AD
+S A$lcduwrhex16$265 Def0000A3
+S A$lcduwrhex16$256 Def000095
+S A$lcduwrhex16$247 Def00008A
+S A$lcduwrhex16$184 Def000050
+S A$lcduwrhex16$175 Def000045
+S A$lcduwrhex16$166 Def00003D
+S A$lcduwrhex16$157 Def000032
+S A$lcduwrhex16$148 Def000023
+S C$lcduwrhex16.c$50$6$61 Def0000F9
+S C$lcduwrhex16.c$34$2$54 Def0000B4
+S C$lcduwrhex16.c$26$2$53 Def000078
+S C$lcduwrhex16.c$10$1$0 Def00000B
+S A$lcduwrhex16$392 Def000128
+S A$lcduwrhex16$383 Def00011F
+S A$lcduwrhex16$374 Def000114
+S A$lcduwrhex16$347 Def0000FC
+S A$lcduwrhex16$338 Def0000EF
+S A$lcduwrhex16$329 Def0000E4
+S A$lcduwrhex16$293 Def0000C1
+S A$lcduwrhex16$284 Def0000B7
+S A$lcduwrhex16$266 Def0000A5
+S A$lcduwrhex16$257 Def000097
+S A$lcduwrhex16$248 Def00008D
+S A$lcduwrhex16$185 Def000051
+S A$lcduwrhex16$176 Def000047
+S A$lcduwrhex16$167 Def00003E
+S A$lcduwrhex16$158 Def000033
+S A$lcduwrhex16$149 Def000026
+S C$lcduwrhex16.c$41$3$56 Def0000D7
+S A$lcduwrhex16$393 Def00012A
+S A$lcduwrhex16$384 Def000121
+S A$lcduwrhex16$375 Def000116
+S A$lcduwrhex16$366 Def00010D
+S A$lcduwrhex16$348 Def0000FF
+S A$lcduwrhex16$294 Def0000C2
+S A$lcduwrhex16$276 Def0000AE
+S A$lcduwrhex16$258 Def000098
+S A$lcduwrhex16$195 Def00005C
+S A$lcduwrhex16$186 Def000054
+S A$lcduwrhex16$177 Def000048
+S A$lcduwrhex16$168 Def00003F
+S A$lcduwrhex16$159 Def000035
+S C$lcduwrhex16.c$12$1$0 Def000012
+S A$lcduwrhex16$394 Def00012B
+S A$lcduwrhex16$385 Def000124
+S A$lcduwrhex16$376 Def000117
+S A$lcduwrhex16$358 Def000105
+S A$lcduwrhex16$295 Def0000C3
+S A$lcduwrhex16$268 Def0000A7
+S A$lcduwrhex16$259 Def000099
+S A$lcduwrhex16$196 Def00005E
+S A$lcduwrhex16$187 Def000056
+S A$lcduwrhex16$178 Def00004A
+S A$lcduwrhex16$169 Def000040
+S C$lcduwrhex16.c$62$4$63 Def000127
+S C$lcduwrhex16.c$43$3$56 Def0000DC
+S C$lcduwrhex16.c$35$3$55 Def0000B9
+S C$lcduwrhex16.c$13$1$0 Def000014
+S A$lcduwrhex16$395 Def00012D
+S A$lcduwrhex16$377 Def000118
+S A$lcduwrhex16$359 Def000106
+S A$lcduwrhex16$287 Def0000B9
+S A$lcduwrhex16$269 Def0000A8
+S A$lcduwrhex16$197 Def000060
+S A$lcduwrhex16$188 Def000057
+S C$lcduwrhex16.c$65$2$54 Def000128
+S C$lcduwrhex16.c$61$5$64 Def00011A
+S C$lcduwrhex16.c$56$2$54 Def000105
+S C$lcduwrhex16.c$36$3$55 Def0000BD
+S C$lcduwrhex16.c$14$1$0 Def00001B
+S A$lcduwrhex16$396 Def000130
+S A$lcduwrhex16$288 Def0000BA
+S A$lcduwrhex16$279 Def0000B1
+S A$lcduwrhex16$198 Def000061
+S A$lcduwrhex16$189 Def000058
+S C$lcduwrhex16.c$66$2$54 Def000133
+S C$lcduwrhex16.c$57$3$62 Def000109
+S A$lcduwrhex16$388 Def000127
+S C$lcduwrhex16.c$58$3$62 Def00010D
+S C$lcduwrhex16.c$53$4$57 Def000103
+S C$lcduwrhex16.c$44$4$57 Def0000E0
+S C$lcduwrhex16.c$38$3$55 Def0000C5
+S A$lcduwrhex16$299 Def0000C5
+S C$lcduwrhex16.c$59$3$62 Def00010F
+S A$lcduwrhex16$399 Def000133
+S C$lcduwrhex16.c$45$5$58 Def0000E4
+S C$lcduwrhex16.c$48$4$57 Def0000E9
+S C$lcduwrhex16.c$46$5$58 Def0000E6
+S C$lcduwrhex16.c$68$3$66 Def000143
+S C$lcduwrhex16.c$49$4$57 Def0000F2
+S C$lcduwrhex16.c$67$4$67 Def00013A
+S C$lcduwrhex16.c$8$0$0 Def000000
+S G$lcd_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 C0 82 C0 83
+R 00 00 00 16 F1 23 04 00 02 F1 23 09 00 02
+T 00 00 09 05 81 E5 00 00 00 24 03 F8 76 00 7C 04
+R 00 00 00 16 F1 23 06 00 02
+T 00 00 14 E5 00 00 00 24 FC F8 86 03 E5 00 00 00
+R 00 00 00 16 F1 23 04 00 02 F1 23 0D 00 02
+T 00 00 1D 24 FD F8 86 02 EB 30 E0 26 C0 04 A8
+R 00 00 00 16
+T 00 00 29 00 00 00 08 86 04 08 86 05 E4 FE FF D0
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 34 04 30 E7 14 A8 00 00 00 08 C3 E4 96 F6
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 3F 08 E4 96 F6 E5 00 00 00 24 03 F8 76 2D
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 4A 80 17
+R 00 00 00 16
+T 00 00 4C
+R 00 00 00 16
+T 00 00 4C EB 20 E2 0C EB 30 E1 0F A8 00 00 00 08
+R 00 00 00 16 F1 23 0C 00 02
+T 00 00 57 E6 08 46 60 07
+R 00 00 00 16
+T 00 00 5C
+R 00 00 00 16
+T 00 00 5C E5 00 00 00 24 03 F8 76 2B
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 E5 00 00 00 24 03 F8 E6 60 04 EA 60 01
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 6E 1A
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F EB 30 E4 06 EA 24 FB 50 01 1A
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 53 03 3F EA 24 FB 50 02 8A 04
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 8C 07
+R 00 00 00 16
+T 00 00 85
+R 00 00 00 16
+T 00 00 85 8F 05 7E 00 1D BD FF 01 1E
+R 00 00 00 16
+T 00 00 8E
+R 00 00 00 16
+T 00 00 8E EE CD 25 E0 CD 33 CD 25 E0 CD 33 8D F0
+R 00 00 00 16
+T 00 00 9B 05 F0 A8 00 00 00 08 86 05 08 86 06 80
+R 00 00 00 16 F1 23 06 00 02
+T 00 00 A6 07
+R 00 00 00 16
+T 00 00 A7
+R 00 00 00 16
+T 00 00 A7 C3 EE 13 FE ED 13 FD
+R 00 00 00 16
+T 00 00 AE
+R 00 00 00 16
+T 00 00 AE D5 F0 F6 53 05 0F BD 0A 00
+R 00 00 00 16
+T 00 00 B7
+R 00 00 00 16
+T 00 00 B7 40 12 EB 30 E5 08 8D 06 74 27 2E FD 80
+R 00 00 00 16
+T 00 00 C4 06
+R 00 00 00 16
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 8D 06 74 07 2E FD
+R 00 00 00 16
+T 00 00 CB
+R 00 00 00 16
+T 00 00 CB ED 70 37 BF 01 02 80 32
+R 00 00 00 16
+T 00 00 D3
+R 00 00 00 16
+T 00 00 D3 EB 20 E7 2E C3 EA 9F 40 68 EB 20 E3 25
+R 00 00 00 16
+T 00 00 E0 EB 20 E6 05 8F 02 43 03 40
+R 00 00 00 16
+T 00 00 E9
+R 00 00 00 16
+T 00 00 E9 75 82 20 12 00 00 12 00 00 EB 30 E4 4E
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 00 F6 BF 05 4B 75 82 20 12 00 00 12 00 00 0A
+R 00 00 00 16 02 0A 00 03 02 0D 00 00
+T 00 01 03 80 3F
+R 00 00 00 16
+T 00 01 05
+R 00 00 00 16
+T 00 01 05 EB 20 E7 1F EB 20 E6 02 8F 02
+R 00 00 00 16
+T 00 01 0F
+R 00 00 00 16
+T 00 01 0F 43 03 C8 E5 00 00 00 24 03 F8 E6 60 0E
+R 00 00 00 16 F1 23 07 00 02
+T 00 01 1A E5 00 00 00 24 03 F8 86 82 12 00 00 12
+R 00 00 00 16 F1 23 04 00 02 02 0D 00 03
+T 00 01 25 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 01 28
+R 00 00 00 16
+T 00 01 28 74 30 2D F5 82 12 00 00 12 00 00 EB 30
+R 00 00 00 16 02 09 00 03 02 0C 00 00
+T 00 01 35 E4 0D BF 05 0A 75 82 27 12 00 00 12
+R 00 00 00 16 02 0C 00 03
+T 00 01 41 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 01 44
+R 00 00 00 16
+T 00 01 44 DF 02 80 03
+R 00 00 00 16
+T 00 01 48
+R 00 00 00 16
+T 00 01 48 02 00 85
+R 00 00 00 16 00 04 00 16
+T 00 01 4B
+R 00 00 00 16
+T 00 01 4B 8A 82 85 00 00 00 81 D0 00 00 00 22
+R 00 00 00 16 F1 23 06 00 02 F1 23 0B 00 02
+
+
+M:lcduwrhex16
+F:G$lcd_writehex16$0$0({2}DF,SC:U),Z,0,3,0,0,0
+S:Llcduwrhex16.lcd_writehex16$nrdig1$1$49({1}SC:U),B,1,-3
+S:Llcduwrhex16.lcd_writehex16$flags1$1$49({1}SC:U),B,1,-4
+S:Llcduwrhex16.lcd_writehex16$val$1$49({2}SI:U),B,1,1
+S:Llcduwrhex16.lcd_writehex16$ch$1$50({1}SC:S),B,1,3
+S:Llcduwrhex16.lcd_writehex16$d$1$50({1}SC:U),R,0,0,[r5]
+S:Llcduwrhex16.lcd_writehex16$cnt$1$50({1}SC:U),R,0,0,[r4]
+S:Llcduwrhex16.lcd_writehex16$flags$1$50({1}SC:U),R,0,0,[r3]
+S:Llcduwrhex16.lcd_writehex16$nrdig$1$50({1}SC:U),R,0,0,[r2]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrhex32
+
+;!FILE libmf/lcduwrhex32.asm
+XH3
+H 1A areas E1 global symbols
+M lcduwrhex32
+O -mmcs51 --model-small
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 7 flags 0 addr 0
+S Llcduwrhex32.lcd_writehex32$cnt$1$50 Def000006
+S Llcduwrhex32.lcd_writehex32$flags1$1$49 Def000001
+S _lcd_writehex32_PARM_2 Def000000
+S _lcd_writehex32_PARM_3 Def000001
+S Llcduwrhex32.lcd_writehex32$val$1$49 Def000002
+S Llcduwrhex32.lcd_writehex32$nrdig1$1$49 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 133 flags 20 addr 0
+S _lcd_writehex32 Def000000
+S XG$lcd_writehex32$0$0 Def000132
+S A$lcduwrhex32$200 Def000055
+S A$lcduwrhex32$400 Def000128
+S A$lcduwrhex32$220 Def000062
+S A$lcduwrhex32$211 Def00005C
+S C$lcduwrhex32.c$30$1$50 Def00006A
+S A$lcduwrhex32$212 Def00005D
+S A$lcduwrhex32$203 Def000057
+S C$lcduwrhex32.c$31$1$50 Def00006C
+S C$lcduwrhex32.c$22$1$50 Def000051
+S A$lcduwrhex32$411 Def000130
+S A$lcduwrhex32$312 Def0000C6
+S A$lcduwrhex32$303 Def0000BA
+S A$lcduwrhex32$240 Def000076
+S A$lcduwrhex32$213 Def00005F
+S C$lcduwrhex32.c$23$1$50 Def000057
+S C$lcduwrhex32.c$20$2$52 Def00004F
+S A$lcduwrhex32$340 Def0000E5
+S A$lcduwrhex32$322 Def0000CF
+S A$lcduwrhex32$313 Def0000C7
+S A$lcduwrhex32$304 Def0000BB
+S A$lcduwrhex32$250 Def000081
+S A$lcduwrhex32$232 Def00006C
+S A$lcduwrhex32$223 Def000065
+S A$lcduwrhex32$151 Def000014
+S A$lcduwrhex32$142 Def00000D
+S A$lcduwrhex32$133 Def000000
+S C$lcduwrhex32.c$24$1$50 Def000058
+S A$lcduwrhex32$404 Def000129
+S A$lcduwrhex32$323 Def0000D0
+S A$lcduwrhex32$314 Def0000C8
+S A$lcduwrhex32$305 Def0000BD
+S A$lcduwrhex32$260 Def000091
+S A$lcduwrhex32$251 Def000082
+S A$lcduwrhex32$242 Def000077
+S A$lcduwrhex32$224 Def000066
+S A$lcduwrhex32$170 Def000032
+S A$lcduwrhex32$161 Def000024
+S A$lcduwrhex32$152 Def000015
+S A$lcduwrhex32$134 Def000003
+S C$lcduwrhex32.c$70$1$50 Def000129
+S C$lcduwrhex32.c$16$1$50 Def000014
+S A$lcduwrhex32$414 Def000132
+S A$lcduwrhex32$405 Def00012B
+S A$lcduwrhex32$360 Def0000F9
+S A$lcduwrhex32$351 Def0000F2
+S A$lcduwrhex32$333 Def0000D8
+S A$lcduwrhex32$315 Def0000C9
+S A$lcduwrhex32$306 Def0000C0
+S A$lcduwrhex32$270 Def00009B
+S A$lcduwrhex32$261 Def000092
+S A$lcduwrhex32$252 Def000084
+S A$lcduwrhex32$243 Def000078
+S A$lcduwrhex32$225 Def000068
+S A$lcduwrhex32$216 Def000061
+S A$lcduwrhex32$207 Def000058
+S A$lcduwrhex32$171 Def000034
+S A$lcduwrhex32$162 Def000025
+S A$lcduwrhex32$153 Def000018
+S A$lcduwrhex32$135 Def000006
+S C$lcduwrhex32.c$71$1$50 Def000130
+S A$lcduwrhex32$370 Def000101
+S A$lcduwrhex32$343 Def0000E8
+S A$lcduwrhex32$334 Def0000DB
+S A$lcduwrhex32$271 Def00009C
+S A$lcduwrhex32$262 Def000093
+S A$lcduwrhex32$253 Def000086
+S A$lcduwrhex32$244 Def000079
+S A$lcduwrhex32$208 Def000059
+S A$lcduwrhex32$181 Def00003D
+S A$lcduwrhex32$172 Def000035
+S A$lcduwrhex32$163 Def000026
+S A$lcduwrhex32$154 Def00001A
+S A$lcduwrhex32$145 Def000010
+S A$lcduwrhex32$136 Def000009
+S C$lcduwrhex32.c$72$1$50 Def000132
+S C$lcduwrhex32.c$40$2$54 Def0000BA
+S A$lcduwrhex32$407 Def00012D
+S A$lcduwrhex32$371 Def000102
+S A$lcduwrhex32$344 Def0000EB
+S A$lcduwrhex32$335 Def0000DE
+S A$lcduwrhex32$326 Def0000D3
+S A$lcduwrhex32$308 Def0000C2
+S A$lcduwrhex32$290 Def0000B0
+S A$lcduwrhex32$281 Def0000A6
+S A$lcduwrhex32$263 Def000094
+S A$lcduwrhex32$254 Def000088
+S A$lcduwrhex32$245 Def00007B
+S A$lcduwrhex32$236 Def00006E
+S A$lcduwrhex32$182 Def00003E
+S A$lcduwrhex32$173 Def000037
+S A$lcduwrhex32$164 Def000028
+S A$lcduwrhex32$155 Def00001C
+S C$lcduwrhex32.c$32$2$54 Def00006E
+S C$lcduwrhex32.c$28$1$50 Def000062
+S C$lcduwrhex32.c$19$1$50 Def00003D
+S C$lcduwrhex32.c$17$2$51 Def000024
+S A$lcduwrhex32$390 Def000118
+S A$lcduwrhex32$363 Def0000FC
+S A$lcduwrhex32$345 Def0000EE
+S A$lcduwrhex32$318 Def0000CB
+S A$lcduwrhex32$309 Def0000C3
+S A$lcduwrhex32$291 Def0000B1
+S A$lcduwrhex32$273 Def00009D
+S A$lcduwrhex32$264 Def000095
+S A$lcduwrhex32$255 Def00008A
+S A$lcduwrhex32$246 Def00007C
+S A$lcduwrhex32$237 Def000070
+S A$lcduwrhex32$228 Def00006A
+S A$lcduwrhex32$183 Def000041
+S A$lcduwrhex32$165 Def00002A
+S A$lcduwrhex32$156 Def00001E
+S C$lcduwrhex32.c$60$3$62 Def000101
+S C$lcduwrhex32.c$51$5$60 Def0000F1
+S C$lcduwrhex32.c$33$2$54 Def0000A0
+S C$lcduwrhex32.c$29$1$50 Def000065
+S C$lcduwrhex32.c$25$2$53 Def00005C
+S C$lcduwrhex32.c$18$2$51 Def000039
+S A$lcduwrhex32$391 Def000119
+S A$lcduwrhex32$355 Def0000F4
+S A$lcduwrhex32$319 Def0000CC
+S A$lcduwrhex32$292 Def0000B2
+S A$lcduwrhex32$265 Def000096
+S A$lcduwrhex32$256 Def00008C
+S A$lcduwrhex32$247 Def00007D
+S A$lcduwrhex32$238 Def000072
+S A$lcduwrhex32$193 Def00004F
+S A$lcduwrhex32$184 Def000042
+S A$lcduwrhex32$166 Def00002B
+S A$lcduwrhex32$157 Def000020
+S A$lcduwrhex32$148 Def000012
+S A$lcduwrhex32$139 Def00000B
+S C$lcduwrhex32.c$50$6$61 Def0000E8
+S C$lcduwrhex32.c$34$2$54 Def0000A3
+S C$lcduwrhex32.c$26$2$53 Def000061
+S C$lcduwrhex32.c$10$1$0 Def00000B
+S A$lcduwrhex32$392 Def00011C
+S A$lcduwrhex32$383 Def00010D
+S A$lcduwrhex32$374 Def000104
+S A$lcduwrhex32$356 Def0000F5
+S A$lcduwrhex32$338 Def0000E1
+S A$lcduwrhex32$329 Def0000D5
+S A$lcduwrhex32$284 Def0000A8
+S A$lcduwrhex32$266 Def000097
+S A$lcduwrhex32$257 Def00008E
+S A$lcduwrhex32$248 Def00007E
+S A$lcduwrhex32$239 Def000073
+S A$lcduwrhex32$185 Def000045
+S A$lcduwrhex32$176 Def000039
+S A$lcduwrhex32$167 Def00002D
+S A$lcduwrhex32$158 Def000021
+S C$lcduwrhex32.c$41$3$56 Def0000C6
+S A$lcduwrhex32$384 Def00010F
+S A$lcduwrhex32$375 Def000106
+S A$lcduwrhex32$348 Def0000F1
+S A$lcduwrhex32$339 Def0000E2
+S A$lcduwrhex32$285 Def0000A9
+S A$lcduwrhex32$276 Def0000A0
+S A$lcduwrhex32$267 Def000098
+S A$lcduwrhex32$249 Def000080
+S A$lcduwrhex32$186 Def000047
+S A$lcduwrhex32$177 Def00003B
+S A$lcduwrhex32$168 Def00002F
+S C$lcduwrhex32.c$12$1$0 Def00000D
+S A$lcduwrhex32$385 Def000110
+S A$lcduwrhex32$376 Def000109
+S A$lcduwrhex32$367 Def0000FE
+S A$lcduwrhex32$268 Def000099
+S A$lcduwrhex32$259 Def000090
+S A$lcduwrhex32$187 Def000049
+S A$lcduwrhex32$169 Def000030
+S C$lcduwrhex32.c$62$4$63 Def00010C
+S C$lcduwrhex32.c$43$3$56 Def0000CB
+S C$lcduwrhex32.c$35$3$55 Def0000A8
+S C$lcduwrhex32.c$13$1$0 Def000010
+S A$lcduwrhex32$395 Def00011F
+S A$lcduwrhex32$386 Def000112
+S A$lcduwrhex32$359 Def0000F8
+S A$lcduwrhex32$296 Def0000B4
+S A$lcduwrhex32$269 Def00009A
+S A$lcduwrhex32$197 Def000051
+S A$lcduwrhex32$188 Def00004B
+S C$lcduwrhex32.c$65$2$54 Def00010D
+S C$lcduwrhex32.c$61$5$64 Def000104
+S C$lcduwrhex32.c$56$2$54 Def0000F4
+S C$lcduwrhex32.c$36$3$55 Def0000AC
+S C$lcduwrhex32.c$14$1$0 Def000012
+S A$lcduwrhex32$396 Def000122
+S A$lcduwrhex32$387 Def000115
+S A$lcduwrhex32$297 Def0000B6
+S A$lcduwrhex32$288 Def0000AC
+S A$lcduwrhex32$279 Def0000A3
+S A$lcduwrhex32$198 Def000052
+S A$lcduwrhex32$189 Def00004D
+S C$lcduwrhex32.c$66$2$54 Def000118
+S C$lcduwrhex32.c$57$3$62 Def0000F8
+S A$lcduwrhex32$397 Def000125
+S A$lcduwrhex32$379 Def00010C
+S A$lcduwrhex32$298 Def0000B8
+S A$lcduwrhex32$289 Def0000AE
+S A$lcduwrhex32$199 Def000054
+S C$lcduwrhex32.c$58$3$62 Def0000FC
+S C$lcduwrhex32.c$53$4$57 Def0000F2
+S C$lcduwrhex32.c$44$4$57 Def0000CF
+S C$lcduwrhex32.c$38$3$55 Def0000B4
+S A$lcduwrhex32$299 Def0000B9
+S C$lcduwrhex32.c$59$3$62 Def0000FE
+S C$lcduwrhex32.c$45$5$58 Def0000D3
+S C$lcduwrhex32.c$48$4$57 Def0000D8
+S C$lcduwrhex32.c$46$5$58 Def0000D5
+S C$lcduwrhex32.c$68$3$66 Def000128
+S C$lcduwrhex32.c$49$4$57 Def0000E1
+S C$lcduwrhex32.c$67$4$67 Def00011F
+S C$lcduwrhex32.c$8$0$0 Def000000
+S G$lcd_writehex32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 06
+R 00 00 00 05
+T 00 00 06
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 85 82 00 00 02 85 83 00 00 03 85 F0
+R 00 00 00 16 F1 21 05 00 05 F1 21 0A 00 05
+T 00 00 08 00 00 04 F5 00 00 05 7B 00 75
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 0E 00 00 06 08 A9 00 00 01 A8
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 13 00 00 00 E9 30 E0 25 AA 00 00 02 AD
+R 00 00 00 16 F1 21 03 00 05 F1 21 0B 00 05
+T 00 00 1B 00 00 03 AE 00 00 04 E5
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 1F 00 00 05 FF 30 E7 19 C3 E4 95 00 00 02
+R 00 00 00 16 F1 21 03 00 05 F1 21 0D 00 05
+T 00 00 28 F5 00 00 02 E4 95 00 00 03 F5
+R 00 00 00 16 F1 21 04 00 05 F1 21 09 00 05
+T 00 00 2E 00 00 03 E4 95 00 00 04 F5
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 33 00 00 04 E4 95 00 00 05 F5
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 38 00 00 05 7B 2D 80 14
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D E9 20 E2 0E E9 30 E1 0C E5 00 00 02 45
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 48 00 00 03 45 00 00 04 45
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 4C 00 00 05 60 02
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F 7B 2B
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EB 60 04 E8 60 01 18
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 E9 30 E4 06 E8 24 FB 50 01 18
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 53 01 3F E8 24 F7 50 02 88 00 00 06
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C AF 00 00 06
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E 8F 05 7E 00 1D BD FF 01 1E
+R 00 00 00 16
+T 00 00 77
+R 00 00 00 16
+T 00 00 77 EE CD 25 E0 CD 33 CD 25 E0 CD 33 8D F0
+R 00 00 00 16
+T 00 00 84 05 F0 AD 00 00 02 AE 00 00 03 AC
+R 00 00 00 16 F1 21 06 00 05 F1 21 0A 00 05
+T 00 00 8B 00 00 04 AA 00 00 05 80 0D
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 90
+R 00 00 00 16
+T 00 00 90 C3 EA 13 FA EC 13 FC EE 13 FE ED 13 FD
+R 00 00 00 16
+T 00 00 9D
+R 00 00 00 16
+T 00 00 9D D5 F0 F0 53 05 0F BD 0A 00
+R 00 00 00 16
+T 00 00 A6
+R 00 00 00 16
+T 00 00 A6 40 12 E9 30 E5 08 8D 06 74 27 2E FD 80
+R 00 00 00 16
+T 00 00 B3 06
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 8D 06 74 07 2E FD
+R 00 00 00 16
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA ED 70 37 BF 01 02 80 32
+R 00 00 00 16
+T 00 00 C2
+R 00 00 00 16
+T 00 00 C2 E9 20 E7 2E C3 E8 9F 40 5E E9 20 E3 25
+R 00 00 00 16
+T 00 00 CF E9 20 E6 05 8F 00 43 01 40
+R 00 00 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 75 82 20 12 00 00 12 00 00 E9 30 E4 44
+R 00 00 00 16 02 07 00 02 02 0A 00 00
+T 00 00 E5 BF 05 41 75 82 20 12 00 00 12 00 00 08
+R 00 00 00 16 02 0A 00 02 02 0D 00 00
+T 00 00 F2 80 35
+R 00 00 00 16
+T 00 00 F4
+R 00 00 00 16
+T 00 00 F4 E9 20 E7 15 E9 20 E6 02 8F 00
+R 00 00 00 16
+T 00 00 FE
+R 00 00 00 16
+T 00 00 FE 43 01 C8 EB 60 09 8B 82 12 00 00 12
+R 00 00 00 16 02 0C 00 02
+T 00 01 0A 00 00 08
+R 00 00 00 16 02 03 00 00
+T 00 01 0D
+R 00 00 00 16
+T 00 01 0D 74 30 2D F5 82 12 00 00 12 00 00 E9 30
+R 00 00 00 16 02 09 00 02 02 0C 00 00
+T 00 01 1A E4 0D BF 05 0A 75 82 27 12 00 00 12
+R 00 00 00 16 02 0C 00 02
+T 00 01 26 00 00 08
+R 00 00 00 16 02 03 00 00
+T 00 01 29
+R 00 00 00 16
+T 00 01 29 DF 02 80 03
+R 00 00 00 16
+T 00 01 2D
+R 00 00 00 16
+T 00 01 2D 02 00 6E
+R 00 00 00 16 00 04 00 16
+T 00 01 30
+R 00 00 00 16
+T 00 01 30 88 82 22
+R 00 00 00 16
+
+
+M:lcduwrhex32
+F:G$lcd_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$nrdig1$1$49({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$flags1$1$49({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$val$1$49({4}SL:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$ch$1$50({1}SC:S),R,0,0,[r3]
+S:Llcduwrhex32.lcd_writehex32$d$1$50({1}SC:U),R,0,0,[r5]
+S:Llcduwrhex32.lcd_writehex32$cnt$1$50({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$flags$1$50({1}SC:U),R,0,0,[r1]
+S:Llcduwrhex32.lcd_writehex32$nrdig$1$50({1}SC:U),R,0,0,[r0]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglink
+
+;!FILE libmf/dbglink.asm
+XH3
+H 23 areas 432 global symbols
+M dbglink
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S _dbglink_rxbuffer Ref000000
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _dbglink_txbuffer Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fdbglink$dbglink_fiforxrd$0$0 Def000001
+S Fdbglink$dbglink_fifotxrd$0$0 Def000003
+S Fdbglink$dbglink_fiforxwr$0$0 Def000000
+S Fdbglink$dbglink_fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$dbglink.c$55$1$62 Def000000
+S C$dbglink.c$56$1$62 Def000022
+S C$dbglink.c$32$1$59 Def000000
+S G$dbglink_poll$0$0 Def000022
+S C$dbglink.c$83$1$64 Def000022
+S C$dbglink.c$58$1$62 Def000022
+S C$dbglink.c$36$1$59 Def000000
+S _dbglink_poll Def000022
+S G$dbglink_irq$0$0 Def000000
+S XFdbglink$dummy0$0$0 Def000000
+S _dbglink_irq Def000000
+S A$dbglink$1230 Def00000A
+S A$dbglink$1240 Def000021
+S A$dbglink$1231 Def00000C
+S A$dbglink$1232 Def00000F
+S A$dbglink$1260 Def000026
+S A$dbglink$1233 Def000012
+S A$dbglink$1261 Def000027
+S A$dbglink$1234 Def000015
+S A$dbglink$1225 Def000000
+S A$dbglink$1262 Def000029
+S A$dbglink$1235 Def000017
+S A$dbglink$1226 Def000002
+S A$dbglink$1263 Def00002B
+S A$dbglink$1236 Def000019
+S A$dbglink$1227 Def000004
+S A$dbglink$1264 Def00002E
+S A$dbglink$1237 Def00001B
+S A$dbglink$1228 Def000006
+S XG$dbglink_irq$0$0 Def000022
+S A$dbglink$1265 Def000030
+S A$dbglink$1238 Def00001D
+S A$dbglink$1229 Def000008
+S A$dbglink$1266 Def000031
+S A$dbglink$1239 Def00001F
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+
+
+M:dbglink
+F:Fdbglink$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$dbglink_irq$0$0({2}DF,SV:S),Z,0,0,1,21,0
+F:G$dbglink_poll$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fdbglink$dbglink_iocore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$dbglink_rxadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglink.dbglink_rxadvance$idx$1$67({1}SC:U),R,0,0,[]
+F:G$dbglink_txadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglink.dbglink_txadvance$idx$1$69({1}SC:U),R,0,0,[]
+F:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Ldbglink.dbglink_rxbufptr$idx$1$71({1}SC:U),R,0,0,[]
+F:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Ldbglink.dbglink_txbufptr$idx$1$73({1}SC:U),R,0,0,[]
+F:G$dbglink_txfreelinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_txfree$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_rxcount$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_txbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$dbglink_rxpeek$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglink.dbglink_rxpeek$idx$1$87({1}SC:U),R,0,0,[]
+F:G$dbglink_txpoke$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglink.dbglink_txpoke$ch$1$89({1}SC:U),B,1,-3
+S:Ldbglink.dbglink_txpoke$idx$1$89({1}SC:U),R,0,0,[]
+F:G$dbglink_txpokehex$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglink.dbglink_txpokehex$ch$1$91({1}SC:U),B,1,-3
+S:Ldbglink.dbglink_txpokehex$idx$1$91({1}SC:U),R,0,0,[]
+F:G$dbglink_txidle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fdbglink$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$dbglink_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fdbglink$dbglink_fiforxwr$0$0({1}SC:U),E,0,0
+S:Fdbglink$dbglink_fiforxrd$0$0({1}SC:U),E,0,0
+S:Fdbglink$dbglink_fifotxwr$0$0({1}SC:U),E,0,0
+S:Fdbglink$dbglink_fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$dbglink_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$dbglink_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglink$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fdbglink$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnktxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M dbglnktxbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _dbglink_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$dbglnktxbuf.c$5$1$59 Def000000
+S C$dbglnktxbuf.c$5$0$0 Def000000
+S Fdbglnktxbuf$dbglink_define_txbuffer$0$0 Def000000
+S XFdbglnktxbuf$dbglink_define_txbuffer$0$0 Def000000
+A DBGLINK0 size 0 flags 20 addr 0
+A DBGLINK1 size 2 flags 20 addr 0
+A DBGLINK2 size 0 flags 20 addr 0
+A DBGLINK3 size 0 flags 20 addr 0
+A DBGLINK4 size 1 flags 20 addr 0
+A DBGLINK5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:dbglnktxbuf
+F:Fdbglnktxbuf$dbglink_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglnktxbuf$dbglink_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkrxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M dbglnkrxbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _dbglink_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$dbglnkrxbuf.c$5$1$59 Def000000
+S C$dbglnkrxbuf.c$5$0$0 Def000000
+S Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0 Def000000
+S XFdbglnkrxbuf$dbglink_define_rxbuffer$0$0 Def000000
+A DBGLINK0 size 0 flags 20 addr 0
+A DBGLINK1 size 0 flags 20 addr 0
+A DBGLINK2 size 2 flags 20 addr 0
+A DBGLINK3 size 0 flags 20 addr 0
+A DBGLINK4 size 0 flags 20 addr 0
+A DBGLINK5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:dbglnkrxbuf
+F:Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
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+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnktx
+
+;!FILE libmf/dbglnktx.asm
+XH3
+H 1A areas 327 global symbols
+M dbglnktx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _dbglink_poll Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S _dbglink_txadvance Ref000000
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _dbglink_txidle Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S _dbglink_txfree Ref000000
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _dbglink_txpoke Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$dbglnktx.c$50$1$62 Def000052
+S C$dbglnktx.c$33$2$60 Def000023
+S C$dbglnktx.c$52$1$62 Def000053
+S C$dbglnktx.c$42$2$63 Def000037
+S C$dbglnktx.c$43$2$63 Def000039
+S C$dbglnktx.c$28$2$60 Def00000D
+S C$dbglnktx.c$29$2$60 Def00000F
+S _dbglink_tx Def000053
+S C$dbglnktx.c$45$2$63 Def000040
+S C$dbglnktx.c$54$1$65 Def000057
+S C$dbglnktx.c$46$2$63 Def000047
+S XG$dbglink_wait_txfree$0$0 Def000031
+S C$dbglnktx.c$55$1$65 Def00005D
+S C$dbglnktx.c$47$2$63 Def00004A
+S C$dbglnktx.c$49$1$62 Def00004F
+S C$dbglnktx.c$24$0$0 Def000000
+S C$dbglnktx.c$56$1$65 Def000067
+S C$dbglnktx.c$35$1$59 Def000028
+S C$dbglnktx.c$26$1$59 Def000008
+S C$dbglnktx.c$57$1$65 Def00006F
+S C$dbglnktx.c$36$1$59 Def000031
+S XG$dbglink_wait_txdone$0$0 Def000052
+S C$dbglnktx.c$38$1$59 Def000032
+S XG$dbglink_tx$0$0 Def00006F
+S A$dbglnktx$1300 Def000055
+S A$dbglnktx$1201 Def00000D
+S A$dbglnktx$1310 Def000065
+S A$dbglnktx$1230 Def00002D
+S A$dbglnktx$1221 Def000023
+S A$dbglnktx$1212 Def000019
+S A$dbglnktx$1303 Def000057
+S A$dbglnktx$1231 Def00002F
+S A$dbglnktx$1222 Def000024
+S A$dbglnktx$1213 Def00001C
+S A$dbglnktx$1204 Def00000F
+S A$dbglnktx$1313 Def000067
+S A$dbglnktx$1304 Def00005A
+S A$dbglnktx$1223 Def000026
+S A$dbglnktx$1214 Def00001E
+S A$dbglnktx$1205 Def000012
+S G$dbglink_wait_txfree$0$0 Def000000
+S A$dbglnktx$1314 Def00006A
+S A$dbglnktx$1251 Def000032
+S A$dbglnktx$1206 Def000014
+S A$dbglnktx$1315 Def00006D
+S A$dbglnktx$1252 Def000034
+S A$dbglnktx$1234 Def000031
+S A$dbglnktx$1207 Def000015
+S A$dbglnktx$1307 Def00005D
+S A$dbglnktx$1262 Def000039
+S A$dbglnktx$1253 Def000036
+S A$dbglnktx$1217 Def000020
+S A$dbglnktx$1208 Def000016
+S A$dbglnktx$1190 Def000006
+S A$dbglnktx$1308 Def00005F
+S A$dbglnktx$1272 Def000047
+S A$dbglnktx$1263 Def00003C
+S A$dbglnktx$1227 Def000028
+S A$dbglnktx$1209 Def000017
+S G$dbglink_wait_txdone$0$0 Def000032
+S A$dbglnktx$1318 Def00006F
+S A$dbglnktx$1309 Def000062
+S A$dbglnktx$1282 Def00004F
+S A$dbglnktx$1264 Def00003E
+S A$dbglnktx$1228 Def000029
+S A$dbglnktx$1283 Def000050
+S A$dbglnktx$1229 Def00002B
+S A$dbglnktx$1193 Def000008
+S A$dbglnktx$1194 Def00000A
+S A$dbglnktx$1276 Def00004A
+S A$dbglnktx$1267 Def000040
+S A$dbglnktx$1195 Def00000C
+S A$dbglnktx$1286 Def000052
+S A$dbglnktx$1277 Def00004B
+S A$dbglnktx$1268 Def000043
+S A$dbglnktx$1259 Def000037
+S A$dbglnktx$1187 Def000000
+S A$dbglnktx$1278 Def00004D
+S A$dbglnktx$1269 Def000045
+S A$dbglnktx$1188 Def000002
+S G$dbglink_tx$0$0 Def000053
+S A$dbglnktx$1189 Def000004
+S _dbglink_wait_txfree Def000000
+S A$dbglnktx$1299 Def000053
+S C$dbglnktx.c$31$2$60 Def000019
+S C$dbglnktx.c$40$1$62 Def000032
+S C$dbglnktx.c$32$2$60 Def000020
+S _dbglink_wait_txdone Def000032
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
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+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
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+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 01 83
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 00 C2 02 0A 00 7F
+T 00 00 23
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+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
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+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
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+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 01 67 02 0D 00 C2
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 7F
+T 00 00 4A
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+R 00 00 00 16
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+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
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+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 02 24 02 0E 00 F5
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:dbglnktx
+F:G$dbglink_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_wait_txfree$v$1$58({1}SC:U),R,0,0,[r7]
+S:Ldbglnktx.dbglink_wait_txfree$iesave$1$59({1}SC:U),R,0,0,[r6]
+F:G$dbglink_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_wait_txdone$iesave$1$62({1}SC:U),R,0,0,[r7]
+F:G$dbglink_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_tx$v$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkrx
+
+;!FILE libmf/dbglnkrx.asm
+XH3
+H 1A areas 309 global symbols
+M dbglnkrx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _dbglink_poll Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S _dbglink_rxadvance Ref000000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S _dbglink_rxpeek Ref000000
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S _dbglink_rxcount Ref000000
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$dbglnkrx.c$43$1$62 Def000042
+S _dbglink_wait_rxcount Def000000
+S C$dbglnkrx.c$44$1$62 Def000048
+S C$dbglnkrx.c$45$1$62 Def00004C
+S C$dbglnkrx.c$28$2$60 Def00000D
+S C$dbglnkrx.c$29$2$60 Def00000F
+S _dbglink_rx Def000032
+S C$dbglnkrx.c$24$0$0 Def000000
+S C$dbglnkrx.c$35$1$59 Def000028
+S C$dbglnkrx.c$26$1$59 Def000008
+S C$dbglnkrx.c$36$1$59 Def000031
+S C$dbglnkrx.c$38$1$59 Def000032
+S XG$dbglink_wait_rxcount$0$0 Def000031
+S XG$dbglink_rx$0$0 Def00004C
+S A$dbglnkrx$1210 Def000019
+S A$dbglnkrx$1220 Def000024
+S A$dbglnkrx$1211 Def00001C
+S A$dbglnkrx$1202 Def00000F
+S A$dbglnkrx$1221 Def000026
+S A$dbglnkrx$1212 Def00001E
+S A$dbglnkrx$1203 Def000012
+S A$dbglnkrx$1204 Def000014
+S A$dbglnkrx$1250 Def000034
+S A$dbglnkrx$1232 Def000031
+S A$dbglnkrx$1205 Def000015
+S A$dbglnkrx$1260 Def000045
+S A$dbglnkrx$1251 Def000037
+S A$dbglnkrx$1215 Def000020
+S A$dbglnkrx$1206 Def000016
+S A$dbglnkrx$1225 Def000028
+S A$dbglnkrx$1207 Def000017
+S A$dbglnkrx$1226 Def000029
+S A$dbglnkrx$1263 Def000048
+S A$dbglnkrx$1254 Def00003A
+S A$dbglnkrx$1227 Def00002B
+S A$dbglnkrx$1191 Def000008
+S A$dbglnkrx$1264 Def00004A
+S A$dbglnkrx$1255 Def00003D
+S A$dbglnkrx$1228 Def00002D
+S A$dbglnkrx$1219 Def000023
+S A$dbglnkrx$1192 Def00000A
+S A$dbglnkrx$1256 Def000040
+S A$dbglnkrx$1247 Def000032
+S A$dbglnkrx$1229 Def00002F
+S A$dbglnkrx$1193 Def00000C
+S A$dbglnkrx$1185 Def000000
+S G$dbglink_wait_rxcount$0$0 Def000000
+S A$dbglnkrx$1267 Def00004C
+S A$dbglnkrx$1186 Def000002
+S A$dbglnkrx$1259 Def000042
+S A$dbglnkrx$1187 Def000004
+S A$dbglnkrx$1188 Def000006
+S G$dbglink_rx$0$0 Def000032
+S A$dbglnkrx$1199 Def00000D
+S C$dbglnkrx.c$31$2$60 Def000019
+S C$dbglnkrx.c$32$2$60 Def000020
+S C$dbglnkrx.c$41$1$62 Def000034
+S C$dbglnkrx.c$33$2$60 Def000023
+S C$dbglnkrx.c$42$1$62 Def00003A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 01 C1
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 00 C2 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 01 8B 02 0B 00 E9
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:dbglnkrx
+F:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkrx.dbglink_wait_rxcount$v$1$58({1}SC:U),R,0,0,[r7]
+S:Ldbglnkrx.dbglink_wait_rxcount$iesave$1$59({1}SC:U),R,0,0,[r6]
+F:G$dbglink_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkrx.dbglink_rx$x$1$62({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$DPL$0$0({1}SC:U),I,0,0
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+S:G$DPS$0$0({1}SC:U),I,0,0
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+S:G$EIE$0$0({1}SC:U),I,0,0
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+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
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+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
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+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
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+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PORTR$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
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+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
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+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
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+S:G$EIE_2$0$0({1}SX:U),J,0,0
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+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
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+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhexu16
+
+;!FILE libmf/dbglnkwrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M dbglnkwrhexu16
+O -mmcs51 --model-small
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S _bp Ref000000
+S _dbglink_txpokehex Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S G$dbglink_writehexu16$0$0 Def000000
+S A$dbglnkwrhexu16$122 Def000009
+S A$dbglnkwrhexu16$150 Def000028
+S A$dbglnkwrhexu16$141 Def00001B
+S A$dbglnkwrhexu16$132 Def000015
+S A$dbglnkwrhexu16$123 Def00000B
+S A$dbglnkwrhexu16$160 Def000034
+S A$dbglnkwrhexu16$151 Def000029
+S A$dbglnkwrhexu16$142 Def00001D
+S A$dbglnkwrhexu16$124 Def00000D
+S A$dbglnkwrhexu16$152 Def00002A
+S A$dbglnkwrhexu16$143 Def00001F
+S A$dbglnkwrhexu16$134 Def000017
+S A$dbglnkwrhexu16$125 Def00000E
+S A$dbglnkwrhexu16$116 Def000000
+S A$dbglnkwrhexu16$153 Def00002C
+S A$dbglnkwrhexu16$144 Def000021
+S A$dbglnkwrhexu16$135 Def000018
+S A$dbglnkwrhexu16$117 Def000002
+S A$dbglnkwrhexu16$154 Def00002D
+S A$dbglnkwrhexu16$145 Def000024
+S A$dbglnkwrhexu16$118 Def000005
+S C$dbglnkwrhexu16.c$25$2$60 Def00001A
+S A$dbglnkwrhexu16$164 Def000036
+S A$dbglnkwrhexu16$155 Def00002E
+S A$dbglnkwrhexu16$128 Def000010
+S A$dbglnkwrhexu16$119 Def000007
+S C$dbglnkwrhexu16.c$26$2$60 Def00001B
+S A$dbglnkwrhexu16$165 Def000038
+S A$dbglnkwrhexu16$156 Def000030
+S A$dbglnkwrhexu16$138 Def00001A
+S A$dbglnkwrhexu16$129 Def000012
+S C$dbglnkwrhexu16.c$27$2$60 Def000026
+S A$dbglnkwrhexu16$166 Def00003B
+S A$dbglnkwrhexu16$157 Def000031
+S A$dbglnkwrhexu16$148 Def000026
+S C$dbglnkwrhexu16.c$30$1$59 Def00003D
+S A$dbglnkwrhexu16$158 Def000032
+S A$dbglnkwrhexu16$149 Def000027
+S A$dbglnkwrhexu16$159 Def000033
+S C$dbglnkwrhexu16.c$23$1$59 Def000010
+S C$dbglnkwrhexu16.c$21$1$0 Def000009
+S A$dbglnkwrhexu16$169 Def00003D
+S C$dbglnkwrhexu16.c$24$1$59 Def000015
+S _dbglink_writehexu16 Def000000
+S C$dbglnkwrhexu16.c$29$1$59 Def000036
+S C$dbglnkwrhexu16.c$19$0$0 Def000000
+S XG$dbglink_writehexu16$0$0 Def00003D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 02 F1 23 09 00 02
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 04
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 03
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 00 F1 23 09 00 02
+
+
+M:dbglnkwrhexu16
+F:G$dbglink_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwrhexu16.dbglink_writehexu16$nrdig$1$58({1}SC:U),B,1,-3
+S:Ldbglnkwrhexu16.dbglink_writehexu16$val$1$58({2}SI:U),R,0,0,[r6,r7]
+S:Ldbglnkwrhexu16.dbglink_writehexu16$nrdig1$1$59({1}SC:U),R,0,0,[r5]
+S:Ldbglnkwrhexu16.dbglink_writehexu16$digit$1$59({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhexu32
+
+;!FILE libmf/dbglnkwrhexu32.asm
+XH3
+H 1A areas 43 global symbols
+M dbglnkwrhexu32
+O -mmcs51 --model-small
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S _dbglink_txpokehex Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S _dbglink_writehexu32_PARM_2 Def000000
+S Ldbglnkwrhexu32.dbglink_writehexu32$nrdig$1$58 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 49 flags 20 addr 0
+S A$dbglnkwrhexu32$120 Def000000
+S A$dbglnkwrhexu32$130 Def00000B
+S A$dbglnkwrhexu32$121 Def000002
+S G$dbglink_writehexu32$0$0 Def000000
+S A$dbglnkwrhexu32$122 Def000004
+S A$dbglnkwrhexu32$150 Def000020
+S A$dbglnkwrhexu32$123 Def000006
+S A$dbglnkwrhexu32$160 Def00002C
+S A$dbglnkwrhexu32$151 Def000021
+S A$dbglnkwrhexu32$142 Def000014
+S A$dbglnkwrhexu32$133 Def00000E
+S A$dbglnkwrhexu32$170 Def000037
+S A$dbglnkwrhexu32$161 Def00002D
+S A$dbglnkwrhexu32$152 Def000022
+S A$dbglnkwrhexu32$143 Def000016
+S A$dbglnkwrhexu32$171 Def000039
+S A$dbglnkwrhexu32$162 Def00002E
+S A$dbglnkwrhexu32$153 Def000023
+S A$dbglnkwrhexu32$144 Def000018
+S A$dbglnkwrhexu32$135 Def000010
+S A$dbglnkwrhexu32$126 Def000007
+S A$dbglnkwrhexu32$172 Def00003A
+S A$dbglnkwrhexu32$163 Def00002F
+S A$dbglnkwrhexu32$154 Def000025
+S A$dbglnkwrhexu32$145 Def00001A
+S A$dbglnkwrhexu32$136 Def000011
+S C$dbglnkwrhexu32.c$25$2$60 Def000013
+S A$dbglnkwrhexu32$182 Def000043
+S A$dbglnkwrhexu32$173 Def00003B
+S A$dbglnkwrhexu32$164 Def000031
+S A$dbglnkwrhexu32$155 Def000026
+S A$dbglnkwrhexu32$146 Def00001D
+S C$dbglnkwrhexu32.c$26$2$60 Def000014
+S A$dbglnkwrhexu32$183 Def000045
+S A$dbglnkwrhexu32$174 Def00003D
+S A$dbglnkwrhexu32$165 Def000032
+S A$dbglnkwrhexu32$156 Def000027
+S A$dbglnkwrhexu32$129 Def000009
+S C$dbglnkwrhexu32.c$27$2$60 Def00001F
+S A$dbglnkwrhexu32$175 Def00003E
+S A$dbglnkwrhexu32$166 Def000033
+S A$dbglnkwrhexu32$157 Def000029
+S A$dbglnkwrhexu32$139 Def000013
+S C$dbglnkwrhexu32.c$30$1$59 Def000048
+S A$dbglnkwrhexu32$176 Def00003F
+S A$dbglnkwrhexu32$167 Def000034
+S A$dbglnkwrhexu32$158 Def00002A
+S A$dbglnkwrhexu32$149 Def00001F
+S A$dbglnkwrhexu32$186 Def000048
+S A$dbglnkwrhexu32$177 Def000040
+S A$dbglnkwrhexu32$168 Def000035
+S A$dbglnkwrhexu32$159 Def00002B
+S C$dbglnkwrhexu32.c$23$1$59 Def000009
+S C$dbglnkwrhexu32.c$21$1$0 Def000007
+S A$dbglnkwrhexu32$178 Def000041
+S A$dbglnkwrhexu32$169 Def000036
+S C$dbglnkwrhexu32.c$24$1$59 Def00000E
+S _dbglink_writehexu32 Def000000
+S C$dbglnkwrhexu32.c$29$1$59 Def000043
+S C$dbglnkwrhexu32.c$19$0$0 Def000000
+S XG$dbglink_writehexu32$0$0 Def000048
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 03
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 30 1A 8C 01 C0 01 8A 82 12 00 00
+R 00 00 00 16 02 0E 00 02
+T 00 00 1D 15 81 ED C4 CC C4 54 0F 6C CC 54 0F CC
+R 00 00 00 16
+T 00 00 2A 6C CC FD EE C4 54 F0 4D FD EF C4 CE C4
+R 00 00 00 16
+T 00 00 37 54 0F 6E CE 54 0F CE 6E CE FF 80 CD
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 00
+
+
+M:dbglnkwrhexu32
+F:G$dbglink_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Ldbglnkwrhexu32.dbglink_writehexu32$nrdig$1$58({1}SC:U),E,0,0
+S:Ldbglnkwrhexu32.dbglink_writehexu32$val$1$58({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Ldbglnkwrhexu32.dbglink_writehexu32$nrdig1$1$59({1}SC:U),R,0,0,[r3]
+S:Ldbglnkwrhexu32.dbglink_writehexu32$digit$1$59({1}SC:U),R,0,0,[r2]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrstr
+
+;!FILE libmf/dbglnkwrstr.asm
+XH3
+H 1A areas 51 global symbols
+M dbglnkwrstr
+O -mmcs51 --model-small
+S _dbglink_txadvance Ref000000
+S _dbglink_txbufptr Ref000000
+S .__.ABS. Def000000
+S _dbglink_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S C$dbglnkwrstr.c$102$1$59 Def000000
+S C$dbglnkwrstr.c$103$1$59 Def000076
+S A$dbglnkwrstr$120 Def00000A
+S A$dbglnkwrstr$130 Def000018
+S A$dbglnkwrstr$121 Def00000D
+S G$dbglink_writestr$0$0 Def000000
+S A$dbglnkwrstr$140 Def000025
+S A$dbglnkwrstr$131 Def000019
+S A$dbglnkwrstr$113 Def000000
+S A$dbglnkwrstr$150 Def00002F
+S A$dbglnkwrstr$141 Def000026
+S A$dbglnkwrstr$132 Def00001A
+S A$dbglnkwrstr$123 Def000010
+S A$dbglnkwrstr$114 Def000002
+S A$dbglnkwrstr$160 Def000040
+S A$dbglnkwrstr$151 Def000031
+S A$dbglnkwrstr$142 Def000027
+S A$dbglnkwrstr$133 Def00001B
+S A$dbglnkwrstr$124 Def000011
+S A$dbglnkwrstr$115 Def000004
+S A$dbglnkwrstr$170 Def000054
+S A$dbglnkwrstr$161 Def000042
+S A$dbglnkwrstr$152 Def000032
+S A$dbglnkwrstr$143 Def000029
+S A$dbglnkwrstr$134 Def00001D
+S A$dbglnkwrstr$125 Def000012
+S A$dbglnkwrstr$116 Def000005
+S A$dbglnkwrstr$180 Def000064
+S A$dbglnkwrstr$171 Def000055
+S A$dbglnkwrstr$162 Def000044
+S A$dbglnkwrstr$153 Def000033
+S A$dbglnkwrstr$144 Def00002B
+S A$dbglnkwrstr$135 Def00001F
+S A$dbglnkwrstr$117 Def000006
+S A$dbglnkwrstr$190 Def000071
+S A$dbglnkwrstr$181 Def000065
+S A$dbglnkwrstr$172 Def000056
+S A$dbglnkwrstr$163 Def000046
+S A$dbglnkwrstr$154 Def000035
+S A$dbglnkwrstr$191 Def000073
+S A$dbglnkwrstr$182 Def000066
+S A$dbglnkwrstr$173 Def000058
+S A$dbglnkwrstr$164 Def000049
+S A$dbglnkwrstr$155 Def000036
+S A$dbglnkwrstr$128 Def000014
+S A$dbglnkwrstr$119 Def000007
+S A$dbglnkwrstr$183 Def000068
+S A$dbglnkwrstr$174 Def00005B
+S A$dbglnkwrstr$165 Def00004C
+S A$dbglnkwrstr$156 Def000038
+S A$dbglnkwrstr$147 Def00002D
+S A$dbglnkwrstr$138 Def000021
+S A$dbglnkwrstr$129 Def000016
+S A$dbglnkwrstr$184 Def00006A
+S A$dbglnkwrstr$175 Def00005D
+S A$dbglnkwrstr$166 Def00004E
+S A$dbglnkwrstr$157 Def00003A
+S A$dbglnkwrstr$148 Def00002E
+S A$dbglnkwrstr$139 Def000023
+S A$dbglnkwrstr$185 Def00006B
+S A$dbglnkwrstr$167 Def000051
+S A$dbglnkwrstr$195 Def000076
+S A$dbglnkwrstr$186 Def00006C
+S A$dbglnkwrstr$177 Def00005F
+S A$dbglnkwrstr$159 Def00003D
+S A$dbglnkwrstr$178 Def000061
+S A$dbglnkwrstr$169 Def000053
+S _dbglink_writestr Def000000
+S A$dbglnkwrstr$188 Def00006E
+S A$dbglnkwrstr$179 Def000063
+S A$dbglnkwrstr$189 Def00006F
+S C$dbglnkwrstr.c$27$0$0 Def000000
+S XG$dbglink_writestr$0$0 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 05
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 04
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 00
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 03
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 07 02 08 00 03
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 01
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 00
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:dbglnkwrstr
+F:G$dbglink_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwrstr.dbglink_writestr$ch$1$58({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwru16
+
+;!FILE libmf/dbglnkwru16.asm
+XH3
+H 1A areas 46 global symbols
+M dbglnkwru16
+O -mmcs51 --model-small
+S __divuint Ref000000
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _bp Ref000000
+S _dbglink_txpoke Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$dbglnkwru16$120 Def000007
+S A$dbglnkwru16$130 Def000012
+S G$dbglink_writeu16$0$0 Def000000
+S A$dbglnkwru16$150 Def00002F
+S A$dbglnkwru16$123 Def000009
+S A$dbglnkwru16$160 Def00003F
+S A$dbglnkwru16$151 Def000031
+S A$dbglnkwru16$142 Def00001C
+S A$dbglnkwru16$133 Def000015
+S A$dbglnkwru16$124 Def00000B
+S A$dbglnkwru16$161 Def000040
+S A$dbglnkwru16$152 Def000033
+S A$dbglnkwru16$143 Def00001F
+S A$dbglnkwru16$125 Def00000D
+S A$dbglnkwru16$171 Def000046
+S A$dbglnkwru16$162 Def000041
+S A$dbglnkwru16$153 Def000035
+S A$dbglnkwru16$144 Def000022
+S A$dbglnkwru16$135 Def000017
+S A$dbglnkwru16$126 Def00000E
+S A$dbglnkwru16$117 Def000000
+S A$dbglnkwru16$172 Def000048
+S A$dbglnkwru16$163 Def000042
+S A$dbglnkwru16$154 Def000037
+S A$dbglnkwru16$145 Def000024
+S A$dbglnkwru16$136 Def000018
+S A$dbglnkwru16$118 Def000002
+S A$dbglnkwru16$182 Def000055
+S A$dbglnkwru16$173 Def000049
+S A$dbglnkwru16$164 Def000043
+S A$dbglnkwru16$146 Def000026
+S A$dbglnkwru16$119 Def000005
+S A$dbglnkwru16$183 Def000057
+S A$dbglnkwru16$174 Def00004A
+S A$dbglnkwru16$165 Def000044
+S A$dbglnkwru16$147 Def000028
+S A$dbglnkwru16$129 Def000010
+S C$dbglnkwru16.c$27$2$60 Def000039
+S A$dbglnkwru16$184 Def00005A
+S A$dbglnkwru16$175 Def00004C
+S A$dbglnkwru16$157 Def000039
+S A$dbglnkwru16$148 Def00002A
+S A$dbglnkwru16$139 Def00001A
+S C$dbglnkwru16.c$28$2$60 Def000045
+S A$dbglnkwru16$176 Def00004E
+S A$dbglnkwru16$158 Def00003B
+S A$dbglnkwru16$149 Def00002C
+S C$dbglnkwru16.c$31$1$59 Def000055
+S C$dbglnkwru16.c$29$2$60 Def000046
+S A$dbglnkwru16$177 Def000051
+S A$dbglnkwru16$168 Def000045
+S A$dbglnkwru16$159 Def00003C
+S C$dbglnkwru16.c$32$1$59 Def00005C
+S C$dbglnkwru16.c$23$1$59 Def000010
+S C$dbglnkwru16.c$21$1$0 Def000009
+S A$dbglnkwru16$187 Def00005C
+S A$dbglnkwru16$178 Def000053
+S C$dbglnkwru16.c$24$1$59 Def000015
+S _dbglink_writeu16 Def000000
+S C$dbglnkwru16.c$26$1$59 Def00001C
+S C$dbglnkwru16.c$25$2$59 Def00001A
+S C$dbglnkwru16.c$19$0$0 Def000000
+S XG$dbglink_writeu16$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 06
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3B 8E 03 75 00 00 00 0A 75
+R 00 00 00 16 F1 23 09 00 03
+T 00 00 20 00 00 01 00 8E 82 8F 83 C0 05 C0 04 C0
+R 00 00 00 16 F1 23 03 00 03
+T 00 00 2B 03 12 00 00 AE 82 AF 83 D0 03 D0 04 D0
+R 00 00 00 16 02 05 00 00
+T 00 00 38 05 8E 02 EA 75 F0 0A A4 FA EB C3 9A FB
+R 00 00 00 16
+T 00 00 45 1C 74 30 2B FB C0 03 8C 82 12 00 00 15
+R 00 00 00 16 02 0D 00 05
+T 00 00 52 81 80 C2
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 01 F1 23 09 00 04
+
+
+M:dbglnkwru16
+F:G$dbglink_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwru16.dbglink_writeu16$nrdig$1$58({1}SC:U),B,1,-3
+S:Ldbglnkwru16.dbglink_writeu16$val$1$58({2}SI:U),R,0,0,[r6,r7]
+S:Ldbglnkwru16.dbglink_writeu16$nrdig1$1$59({1}SC:U),R,0,0,[r5]
+S:Ldbglnkwru16.dbglink_writeu16$digit$1$59({1}SC:U),R,0,0,[r4]
+S:Ldbglnkwru16.dbglink_writeu16$v1$2$60({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwru32
+
+;!FILE libmf/dbglnkwru32.asm
+XH3
+H 1A areas 49 global symbols
+M dbglnkwru32
+O -mmcs51 --model-small
+S __divulong_PARM_2 Ref000000
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _dbglink_txpoke Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S Ldbglnkwru32.dbglink_writeu32$nrdig$1$58 Def000000
+S _dbglink_writeu32_PARM_2 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$dbglnkwru32$130 Def000009
+S A$dbglnkwru32$121 Def000000
+S G$dbglink_writeu32$0$0 Def000000
+S A$dbglnkwru32$140 Def000013
+S A$dbglnkwru32$131 Def00000B
+S A$dbglnkwru32$122 Def000002
+S A$dbglnkwru32$150 Def000023
+S A$dbglnkwru32$123 Def000004
+S A$dbglnkwru32$160 Def000036
+S A$dbglnkwru32$151 Def000025
+S A$dbglnkwru32$124 Def000006
+S A$dbglnkwru32$170 Def000044
+S A$dbglnkwru32$161 Def000038
+S A$dbglnkwru32$152 Def000026
+S A$dbglnkwru32$143 Def000015
+S A$dbglnkwru32$134 Def00000E
+S A$dbglnkwru32$180 Def00004B
+S A$dbglnkwru32$171 Def000045
+S A$dbglnkwru32$162 Def00003A
+S A$dbglnkwru32$153 Def000028
+S A$dbglnkwru32$144 Def000018
+S A$dbglnkwru32$190 Def000059
+S A$dbglnkwru32$181 Def00004C
+S A$dbglnkwru32$172 Def000046
+S A$dbglnkwru32$154 Def00002A
+S A$dbglnkwru32$145 Def000019
+S A$dbglnkwru32$136 Def000010
+S A$dbglnkwru32$127 Def000007
+S A$dbglnkwru32$182 Def00004E
+S A$dbglnkwru32$155 Def00002C
+S A$dbglnkwru32$146 Def00001B
+S A$dbglnkwru32$137 Def000011
+S A$dbglnkwru32$183 Def000050
+S A$dbglnkwru32$165 Def00003C
+S A$dbglnkwru32$156 Def00002F
+S A$dbglnkwru32$147 Def00001D
+S C$dbglnkwru32.c$27$2$60 Def00003C
+S A$dbglnkwru32$193 Def00005C
+S A$dbglnkwru32$184 Def000053
+S A$dbglnkwru32$175 Def000047
+S A$dbglnkwru32$166 Def00003E
+S A$dbglnkwru32$157 Def000031
+S A$dbglnkwru32$148 Def00001F
+S C$dbglnkwru32.c$28$2$60 Def000047
+S A$dbglnkwru32$185 Def000055
+S A$dbglnkwru32$167 Def00003F
+S A$dbglnkwru32$158 Def000033
+S A$dbglnkwru32$149 Def000021
+S C$dbglnkwru32.c$31$1$59 Def000057
+S C$dbglnkwru32.c$29$2$60 Def000048
+S A$dbglnkwru32$168 Def000042
+S A$dbglnkwru32$159 Def000035
+S C$dbglnkwru32.c$32$1$59 Def00005C
+S C$dbglnkwru32.c$23$1$59 Def000009
+S C$dbglnkwru32.c$21$1$0 Def000007
+S A$dbglnkwru32$178 Def000048
+S A$dbglnkwru32$169 Def000043
+S C$dbglnkwru32.c$24$1$59 Def00000E
+S _dbglink_writeu32 Def000000
+S A$dbglnkwru32$179 Def00004A
+S A$dbglnkwru32$189 Def000057
+S C$dbglnkwru32.c$26$1$59 Def000015
+S C$dbglnkwru32.c$25$2$59 Def000013
+S C$dbglnkwru32.c$19$0$0 Def000000
+S XG$dbglink_writeu32$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 05
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 44 8C 01 75 00 00 00 0A E4 F5
+R 00 00 00 16 F1 23 09 00 00
+T 00 00 1A 00 00 01 F5 00 00 02 F5
+R 00 00 00 16 F1 23 03 00 00 F1 23 07 00 00
+T 00 00 1E 00 00 03 8C 82 8D 83 8E F0 EF C0 03 C0
+R 00 00 00 16 F1 23 03 00 00
+T 00 00 29 02 C0 01 12 00 00 AC 82 AD 83 AE F0 FF
+R 00 00 00 16 02 07 00 03
+T 00 00 36 D0 01 D0 02 D0 03 8C 00 E8 75 F0 0A A4
+R 00 00 00 16
+T 00 00 43 D3 99 F4 F9 1A 74 30 29 F9 C0 01 8A 82
+R 00 00 00 16
+T 00 00 50 12 00 00 15 81 80 B9
+R 00 00 00 16 02 04 00 04
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 01
+
+
+M:dbglnkwru32
+F:G$dbglink_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Ldbglnkwru32.dbglink_writeu32$nrdig$1$58({1}SC:U),E,0,0
+S:Ldbglnkwru32.dbglink_writeu32$val$1$58({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Ldbglnkwru32.dbglink_writeu32$nrdig1$1$59({1}SC:U),R,0,0,[r3]
+S:Ldbglnkwru32.dbglink_writeu32$digit$1$59({1}SC:U),R,0,0,[r2]
+S:Ldbglnkwru32.dbglink_writeu32$v1$2$60({1}SC:U),R,0,0,[r1]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrnum16
+
+;!FILE libmf/dbglnkwrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M dbglnkwrnum16
+O -mmcs51 --model-small
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S XG$dbglink_writenum16$0$0 Def0000F6
+S C$dbglnkwrnum16.c$240$1$61 Def000000
+S C$dbglnkwrnum16.c$241$1$61 Def0000F6
+S A$dbglnkwrnum16$200 Def000059
+S A$dbglnkwrnum16$300 Def0000D9
+S A$dbglnkwrnum16$210 Def000065
+S A$dbglnkwrnum16$201 Def00005A
+S A$dbglnkwrnum16$120 Def000005
+S A$dbglnkwrnum16$310 Def0000ED
+S A$dbglnkwrnum16$301 Def0000DC
+S A$dbglnkwrnum16$220 Def000070
+S A$dbglnkwrnum16$211 Def000066
+S A$dbglnkwrnum16$202 Def00005C
+S A$dbglnkwrnum16$121 Def000006
+S G$dbglink_writenum16$0$0 Def000000
+S A$dbglnkwrnum16$311 Def0000EF
+S A$dbglnkwrnum16$302 Def0000DD
+S A$dbglnkwrnum16$230 Def000080
+S A$dbglnkwrnum16$203 Def00005D
+S A$dbglnkwrnum16$140 Def000014
+S A$dbglnkwrnum16$122 Def000007
+S A$dbglnkwrnum16$312 Def0000F1
+S A$dbglnkwrnum16$303 Def0000DF
+S A$dbglnkwrnum16$240 Def000090
+S A$dbglnkwrnum16$231 Def000082
+S A$dbglnkwrnum16$213 Def000068
+S A$dbglnkwrnum16$204 Def00005E
+S A$dbglnkwrnum16$150 Def000026
+S A$dbglnkwrnum16$141 Def000016
+S A$dbglnkwrnum16$132 Def00000F
+S A$dbglnkwrnum16$123 Def000009
+S A$dbglnkwrnum16$241 Def000092
+S A$dbglnkwrnum16$205 Def000060
+S A$dbglnkwrnum16$142 Def000019
+S A$dbglnkwrnum16$314 Def0000F3
+S A$dbglnkwrnum16$305 Def0000E1
+S A$dbglnkwrnum16$242 Def000095
+S A$dbglnkwrnum16$233 Def000084
+S A$dbglnkwrnum16$224 Def000072
+S A$dbglnkwrnum16$215 Def00006B
+S A$dbglnkwrnum16$152 Def000028
+S A$dbglnkwrnum16$143 Def00001A
+S A$dbglnkwrnum16$125 Def00000B
+S A$dbglnkwrnum16$306 Def0000E3
+S A$dbglnkwrnum16$270 Def0000AE
+S A$dbglnkwrnum16$261 Def0000A4
+S A$dbglnkwrnum16$243 Def000098
+S A$dbglnkwrnum16$234 Def000087
+S A$dbglnkwrnum16$225 Def000074
+S A$dbglnkwrnum16$162 Def000036
+S A$dbglnkwrnum16$153 Def00002B
+S A$dbglnkwrnum16$144 Def00001B
+S A$dbglnkwrnum16$126 Def00000C
+S A$dbglnkwrnum16$117 Def000000
+S A$dbglnkwrnum16$316 Def0000F4
+S A$dbglnkwrnum16$307 Def0000E5
+S A$dbglnkwrnum16$280 Def0000BE
+S A$dbglnkwrnum16$244 Def00009A
+S A$dbglnkwrnum16$235 Def000088
+S A$dbglnkwrnum16$226 Def000076
+S A$dbglnkwrnum16$217 Def00006E
+S A$dbglnkwrnum16$208 Def000063
+S A$dbglnkwrnum16$163 Def000037
+S A$dbglnkwrnum16$154 Def00002E
+S A$dbglnkwrnum16$145 Def00001D
+S A$dbglnkwrnum16$118 Def000002
+S A$dbglnkwrnum16$308 Def0000E7
+S A$dbglnkwrnum16$290 Def0000C7
+S A$dbglnkwrnum16$281 Def0000C0
+S A$dbglnkwrnum16$272 Def0000B0
+S A$dbglnkwrnum16$263 Def0000A7
+S A$dbglnkwrnum16$245 Def00009C
+S A$dbglnkwrnum16$236 Def00008A
+S A$dbglnkwrnum16$227 Def000078
+S A$dbglnkwrnum16$218 Def00006F
+S A$dbglnkwrnum16$209 Def000064
+S A$dbglnkwrnum16$182 Def000047
+S A$dbglnkwrnum16$173 Def00003E
+S A$dbglnkwrnum16$164 Def000039
+S A$dbglnkwrnum16$155 Def000030
+S A$dbglnkwrnum16$146 Def00001F
+S A$dbglnkwrnum16$128 Def00000D
+S A$dbglnkwrnum16$119 Def000004
+S A$dbglnkwrnum16$309 Def0000EA
+S A$dbglnkwrnum16$291 Def0000C9
+S A$dbglnkwrnum16$282 Def0000C2
+S A$dbglnkwrnum16$273 Def0000B1
+S A$dbglnkwrnum16$255 Def00009F
+S A$dbglnkwrnum16$228 Def00007B
+S A$dbglnkwrnum16$192 Def00004E
+S A$dbglnkwrnum16$183 Def000048
+S A$dbglnkwrnum16$174 Def000041
+S A$dbglnkwrnum16$165 Def00003A
+S A$dbglnkwrnum16$156 Def000032
+S A$dbglnkwrnum16$147 Def000020
+S A$dbglnkwrnum16$292 Def0000CB
+S A$dbglnkwrnum16$265 Def0000AA
+S A$dbglnkwrnum16$247 Def00009E
+S A$dbglnkwrnum16$238 Def00008C
+S A$dbglnkwrnum16$229 Def00007E
+S A$dbglnkwrnum16$193 Def00004F
+S A$dbglnkwrnum16$184 Def000049
+S A$dbglnkwrnum16$175 Def000042
+S A$dbglnkwrnum16$166 Def00003C
+S A$dbglnkwrnum16$148 Def000022
+S A$dbglnkwrnum16$139 Def000011
+S A$dbglnkwrnum16$293 Def0000CC
+S A$dbglnkwrnum16$284 Def0000C4
+S A$dbglnkwrnum16$275 Def0000B3
+S A$dbglnkwrnum16$266 Def0000AB
+S A$dbglnkwrnum16$257 Def0000A1
+S A$dbglnkwrnum16$239 Def00008E
+S A$dbglnkwrnum16$185 Def00004A
+S A$dbglnkwrnum16$176 Def000044
+S A$dbglnkwrnum16$167 Def00003D
+S A$dbglnkwrnum16$158 Def000034
+S A$dbglnkwrnum16$149 Def000024
+S A$dbglnkwrnum16$294 Def0000CE
+S A$dbglnkwrnum16$276 Def0000B5
+S A$dbglnkwrnum16$258 Def0000A3
+S A$dbglnkwrnum16$195 Def000050
+S A$dbglnkwrnum16$186 Def00004C
+S A$dbglnkwrnum16$177 Def000046
+S A$dbglnkwrnum16$295 Def0000D0
+S A$dbglnkwrnum16$277 Def0000B7
+S A$dbglnkwrnum16$196 Def000052
+S A$dbglnkwrnum16$187 Def00004D
+S _dbglink_writenum16 Def000000
+S A$dbglnkwrnum16$296 Def0000D3
+S A$dbglnkwrnum16$278 Def0000B9
+S A$dbglnkwrnum16$269 Def0000AC
+S A$dbglnkwrnum16$197 Def000054
+S A$dbglnkwrnum16$297 Def0000D5
+S A$dbglnkwrnum16$279 Def0000BB
+S A$dbglnkwrnum16$198 Def000057
+S C$dbglnkwrnum16.c$25$0$0 Def000000
+S A$dbglnkwrnum16$298 Def0000D7
+S A$dbglnkwrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrnum16
+F:G$dbglink_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrnum16.dbglink_writenum16$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrnum16.dbglink_writenum16$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrnum16.dbglink_writenum16$val$1$60({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrnum32
+
+;!FILE libmf/dbglnkwrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M dbglnkwrnum32
+O -mmcs51 --model-small
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S XG$dbglink_writenum32$0$0 Def000128
+S A$dbglnkwrnum32$200 Def00005A
+S C$dbglnkwrnum32.c$276$1$61 Def000000
+S A$dbglnkwrnum32$300 Def0000D4
+S A$dbglnkwrnum32$210 Def000062
+S A$dbglnkwrnum32$201 Def00005C
+S A$dbglnkwrnum32$120 Def000005
+S C$dbglnkwrnum32.c$277$1$61 Def000128
+S A$dbglnkwrnum32$310 Def0000DD
+S A$dbglnkwrnum32$301 Def0000D5
+S A$dbglnkwrnum32$220 Def00006A
+S A$dbglnkwrnum32$211 Def000063
+S A$dbglnkwrnum32$130 Def000010
+S A$dbglnkwrnum32$121 Def000007
+S G$dbglink_writenum32$0$0 Def000000
+S A$dbglnkwrnum32$311 Def0000DF
+S A$dbglnkwrnum32$230 Def00007B
+S A$dbglnkwrnum32$221 Def00006C
+S A$dbglnkwrnum32$122 Def000008
+S A$dbglnkwrnum32$330 Def0000FA
+S A$dbglnkwrnum32$312 Def0000E1
+S A$dbglnkwrnum32$240 Def000087
+S A$dbglnkwrnum32$231 Def00007C
+S A$dbglnkwrnum32$222 Def00006E
+S A$dbglnkwrnum32$150 Def000024
+S A$dbglnkwrnum32$141 Def000014
+S A$dbglnkwrnum32$123 Def000009
+S A$dbglnkwrnum32$340 Def00010D
+S A$dbglnkwrnum32$331 Def0000FD
+S A$dbglnkwrnum32$313 Def0000E3
+S A$dbglnkwrnum32$304 Def0000D6
+S A$dbglnkwrnum32$250 Def000092
+S A$dbglnkwrnum32$241 Def000088
+S A$dbglnkwrnum32$232 Def00007E
+S A$dbglnkwrnum32$223 Def00006F
+S A$dbglnkwrnum32$160 Def000030
+S A$dbglnkwrnum32$151 Def000026
+S A$dbglnkwrnum32$142 Def000017
+S A$dbglnkwrnum32$124 Def00000A
+S A$dbglnkwrnum32$350 Def00011F
+S A$dbglnkwrnum32$341 Def00010F
+S A$dbglnkwrnum32$332 Def0000FF
+S A$dbglnkwrnum32$314 Def0000E5
+S A$dbglnkwrnum32$305 Def0000D8
+S A$dbglnkwrnum32$260 Def0000A2
+S A$dbglnkwrnum32$233 Def00007F
+S A$dbglnkwrnum32$224 Def000072
+S A$dbglnkwrnum32$206 Def00005D
+S A$dbglnkwrnum32$161 Def000033
+S A$dbglnkwrnum32$152 Def000027
+S A$dbglnkwrnum32$143 Def000018
+S A$dbglnkwrnum32$134 Def000012
+S A$dbglnkwrnum32$125 Def00000C
+S A$dbglnkwrnum32$116 Def000000
+S A$dbglnkwrnum32$351 Def000121
+S A$dbglnkwrnum32$342 Def000111
+S A$dbglnkwrnum32$333 Def000101
+S A$dbglnkwrnum32$324 Def0000EF
+S A$dbglnkwrnum32$315 Def0000E8
+S A$dbglnkwrnum32$270 Def0000B4
+S A$dbglnkwrnum32$261 Def0000A4
+S A$dbglnkwrnum32$243 Def00008A
+S A$dbglnkwrnum32$234 Def000080
+S A$dbglnkwrnum32$225 Def000073
+S A$dbglnkwrnum32$216 Def000064
+S A$dbglnkwrnum32$207 Def00005E
+S A$dbglnkwrnum32$162 Def000036
+S A$dbglnkwrnum32$153 Def000028
+S A$dbglnkwrnum32$144 Def00001B
+S A$dbglnkwrnum32$117 Def000001
+S A$dbglnkwrnum32$352 Def000123
+S A$dbglnkwrnum32$325 Def0000F1
+S A$dbglnkwrnum32$316 Def0000EA
+S A$dbglnkwrnum32$307 Def0000DA
+S A$dbglnkwrnum32$280 Def0000C6
+S A$dbglnkwrnum32$235 Def000082
+S A$dbglnkwrnum32$226 Def000075
+S A$dbglnkwrnum32$208 Def00005F
+S A$dbglnkwrnum32$190 Def00004E
+S A$dbglnkwrnum32$172 Def000040
+S A$dbglnkwrnum32$163 Def000038
+S A$dbglnkwrnum32$154 Def000029
+S A$dbglnkwrnum32$145 Def00001C
+S A$dbglnkwrnum32$127 Def00000E
+S A$dbglnkwrnum32$335 Def000103
+S A$dbglnkwrnum32$326 Def0000F3
+S A$dbglnkwrnum32$317 Def0000EC
+S A$dbglnkwrnum32$308 Def0000DB
+S A$dbglnkwrnum32$290 Def0000C9
+S A$dbglnkwrnum32$263 Def0000A6
+S A$dbglnkwrnum32$254 Def000094
+S A$dbglnkwrnum32$245 Def00008D
+S A$dbglnkwrnum32$227 Def000077
+S A$dbglnkwrnum32$218 Def000066
+S A$dbglnkwrnum32$209 Def000060
+S A$dbglnkwrnum32$191 Def000050
+S A$dbglnkwrnum32$173 Def000041
+S A$dbglnkwrnum32$164 Def00003A
+S A$dbglnkwrnum32$155 Def00002A
+S A$dbglnkwrnum32$146 Def00001D
+S A$dbglnkwrnum32$128 Def00000F
+S A$dbglnkwrnum32$119 Def000003
+S A$dbglnkwrnum32$354 Def000125
+S A$dbglnkwrnum32$345 Def000113
+S A$dbglnkwrnum32$336 Def000106
+S A$dbglnkwrnum32$327 Def0000F5
+S A$dbglnkwrnum32$282 Def0000C8
+S A$dbglnkwrnum32$273 Def0000B6
+S A$dbglnkwrnum32$264 Def0000A9
+S A$dbglnkwrnum32$255 Def000096
+S A$dbglnkwrnum32$228 Def000079
+S A$dbglnkwrnum32$219 Def000068
+S A$dbglnkwrnum32$174 Def000043
+S A$dbglnkwrnum32$165 Def00003B
+S A$dbglnkwrnum32$156 Def00002B
+S A$dbglnkwrnum32$147 Def00001F
+S A$dbglnkwrnum32$346 Def000115
+S A$dbglnkwrnum32$337 Def000107
+S A$dbglnkwrnum32$328 Def0000F6
+S A$dbglnkwrnum32$319 Def0000EE
+S A$dbglnkwrnum32$292 Def0000CB
+S A$dbglnkwrnum32$274 Def0000B8
+S A$dbglnkwrnum32$265 Def0000AA
+S A$dbglnkwrnum32$256 Def000098
+S A$dbglnkwrnum32$247 Def000090
+S A$dbglnkwrnum32$238 Def000085
+S A$dbglnkwrnum32$193 Def000051
+S A$dbglnkwrnum32$175 Def000044
+S A$dbglnkwrnum32$166 Def00003C
+S A$dbglnkwrnum32$157 Def00002C
+S A$dbglnkwrnum32$148 Def000021
+S A$dbglnkwrnum32$356 Def000126
+S A$dbglnkwrnum32$347 Def000117
+S A$dbglnkwrnum32$338 Def000109
+S A$dbglnkwrnum32$329 Def0000F8
+S A$dbglnkwrnum32$293 Def0000CD
+S A$dbglnkwrnum32$275 Def0000BA
+S A$dbglnkwrnum32$266 Def0000AC
+S A$dbglnkwrnum32$257 Def00009A
+S A$dbglnkwrnum32$248 Def000091
+S A$dbglnkwrnum32$239 Def000086
+S A$dbglnkwrnum32$194 Def000052
+S A$dbglnkwrnum32$176 Def000046
+S A$dbglnkwrnum32$158 Def00002E
+S A$dbglnkwrnum32$149 Def000022
+S A$dbglnkwrnum32$348 Def000119
+S A$dbglnkwrnum32$339 Def00010B
+S A$dbglnkwrnum32$276 Def0000BC
+S A$dbglnkwrnum32$267 Def0000AE
+S A$dbglnkwrnum32$258 Def00009D
+S A$dbglnkwrnum32$195 Def000054
+S A$dbglnkwrnum32$177 Def000047
+S A$dbglnkwrnum32$168 Def00003E
+S A$dbglnkwrnum32$349 Def00011C
+S A$dbglnkwrnum32$277 Def0000BF
+S A$dbglnkwrnum32$268 Def0000B0
+S A$dbglnkwrnum32$259 Def0000A0
+S A$dbglnkwrnum32$196 Def000056
+S A$dbglnkwrnum32$187 Def000048
+S _dbglink_writenum32 Def000000
+S A$dbglnkwrnum32$296 Def0000CE
+S A$dbglnkwrnum32$278 Def0000C2
+S A$dbglnkwrnum32$269 Def0000B2
+S A$dbglnkwrnum32$188 Def00004B
+S A$dbglnkwrnum32$279 Def0000C4
+S A$dbglnkwrnum32$198 Def000057
+S A$dbglnkwrnum32$189 Def00004C
+S C$dbglnkwrnum32.c$25$0$0 Def000000
+S A$dbglnkwrnum32$298 Def0000D1
+S A$dbglnkwrnum32$199 Def000058
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:dbglnkwrnum32
+F:G$dbglink_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrnum32.dbglink_writenum32$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrnum32.dbglink_writenum32$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrnum32.dbglink_writenum32$val$1$60({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhex16
+
+;!FILE libmf/dbglnkwrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M dbglnkwrhex16
+O -mmcs51 --model-small
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S C$dbglnkwrhex16.c$264$1$61 Def000000
+S C$dbglnkwrhex16.c$265$1$61 Def000111
+S A$dbglnkwrhex16$200 Def000058
+S A$dbglnkwrhex16$201 Def000059
+S A$dbglnkwrhex16$120 Def000005
+S A$dbglnkwrhex16$310 Def0000DB
+S A$dbglnkwrhex16$301 Def0000CB
+S A$dbglnkwrhex16$220 Def000069
+S A$dbglnkwrhex16$211 Def000063
+S A$dbglnkwrhex16$202 Def00005B
+S A$dbglnkwrhex16$121 Def000006
+S G$dbglink_writehex16$0$0 Def000000
+S A$dbglnkwrhex16$320 Def0000E4
+S A$dbglnkwrhex16$311 Def0000DD
+S A$dbglnkwrhex16$302 Def0000CC
+S A$dbglnkwrhex16$230 Def000075
+S A$dbglnkwrhex16$221 Def00006B
+S A$dbglnkwrhex16$203 Def00005D
+S A$dbglnkwrhex16$140 Def000014
+S A$dbglnkwrhex16$122 Def000007
+S A$dbglnkwrhex16$330 Def0000F7
+S A$dbglnkwrhex16$321 Def0000E6
+S A$dbglnkwrhex16$240 Def000081
+S A$dbglnkwrhex16$231 Def000077
+S A$dbglnkwrhex16$150 Def000026
+S A$dbglnkwrhex16$141 Def000016
+S A$dbglnkwrhex16$132 Def00000F
+S A$dbglnkwrhex16$123 Def000009
+S A$dbglnkwrhex16$340 Def00010A
+S A$dbglnkwrhex16$331 Def0000F8
+S A$dbglnkwrhex16$322 Def0000E7
+S A$dbglnkwrhex16$313 Def0000DF
+S A$dbglnkwrhex16$304 Def0000CE
+S A$dbglnkwrhex16$232 Def000078
+S A$dbglnkwrhex16$223 Def00006D
+S A$dbglnkwrhex16$205 Def00005F
+S A$dbglnkwrhex16$142 Def000019
+S A$dbglnkwrhex16$341 Def00010C
+S A$dbglnkwrhex16$332 Def0000FA
+S A$dbglnkwrhex16$323 Def0000E9
+S A$dbglnkwrhex16$305 Def0000D0
+S A$dbglnkwrhex16$260 Def00009D
+S A$dbglnkwrhex16$242 Def000083
+S A$dbglnkwrhex16$233 Def000079
+S A$dbglnkwrhex16$224 Def00006F
+S A$dbglnkwrhex16$152 Def000028
+S A$dbglnkwrhex16$143 Def00001A
+S A$dbglnkwrhex16$125 Def00000B
+S A$dbglnkwrhex16$324 Def0000EB
+S A$dbglnkwrhex16$306 Def0000D2
+S A$dbglnkwrhex16$270 Def0000AD
+S A$dbglnkwrhex16$234 Def00007B
+S A$dbglnkwrhex16$225 Def000072
+S A$dbglnkwrhex16$207 Def000060
+S A$dbglnkwrhex16$162 Def000036
+S A$dbglnkwrhex16$153 Def00002B
+S A$dbglnkwrhex16$144 Def00001B
+S A$dbglnkwrhex16$126 Def00000C
+S A$dbglnkwrhex16$117 Def000000
+S A$dbglnkwrhex16$343 Def00010E
+S A$dbglnkwrhex16$334 Def0000FC
+S A$dbglnkwrhex16$325 Def0000EE
+S A$dbglnkwrhex16$307 Def0000D4
+S A$dbglnkwrhex16$271 Def0000B0
+S A$dbglnkwrhex16$262 Def00009F
+S A$dbglnkwrhex16$253 Def00008D
+S A$dbglnkwrhex16$244 Def000086
+S A$dbglnkwrhex16$208 Def000062
+S A$dbglnkwrhex16$163 Def000037
+S A$dbglnkwrhex16$154 Def00002E
+S A$dbglnkwrhex16$145 Def00001D
+S A$dbglnkwrhex16$118 Def000002
+S A$dbglnkwrhex16$335 Def0000FE
+S A$dbglnkwrhex16$326 Def0000F0
+S A$dbglnkwrhex16$308 Def0000D6
+S A$dbglnkwrhex16$290 Def0000BF
+S A$dbglnkwrhex16$272 Def0000B3
+S A$dbglnkwrhex16$263 Def0000A2
+S A$dbglnkwrhex16$254 Def00008F
+S A$dbglnkwrhex16$227 Def000074
+S A$dbglnkwrhex16$218 Def000065
+S A$dbglnkwrhex16$182 Def000047
+S A$dbglnkwrhex16$173 Def00003E
+S A$dbglnkwrhex16$164 Def000039
+S A$dbglnkwrhex16$155 Def000030
+S A$dbglnkwrhex16$146 Def00001F
+S A$dbglnkwrhex16$128 Def00000D
+S A$dbglnkwrhex16$119 Def000004
+S A$dbglnkwrhex16$345 Def00010F
+S A$dbglnkwrhex16$336 Def000100
+S A$dbglnkwrhex16$327 Def0000F2
+S A$dbglnkwrhex16$318 Def0000E0
+S A$dbglnkwrhex16$309 Def0000D9
+S A$dbglnkwrhex16$273 Def0000B5
+S A$dbglnkwrhex16$264 Def0000A3
+S A$dbglnkwrhex16$255 Def000091
+S A$dbglnkwrhex16$246 Def000089
+S A$dbglnkwrhex16$237 Def00007E
+S A$dbglnkwrhex16$219 Def000067
+S A$dbglnkwrhex16$192 Def00004E
+S A$dbglnkwrhex16$183 Def000048
+S A$dbglnkwrhex16$174 Def000041
+S A$dbglnkwrhex16$165 Def00003A
+S A$dbglnkwrhex16$156 Def000032
+S A$dbglnkwrhex16$147 Def000020
+S A$dbglnkwrhex16$337 Def000102
+S A$dbglnkwrhex16$319 Def0000E2
+S A$dbglnkwrhex16$292 Def0000C2
+S A$dbglnkwrhex16$274 Def0000B7
+S A$dbglnkwrhex16$265 Def0000A5
+S A$dbglnkwrhex16$256 Def000093
+S A$dbglnkwrhex16$247 Def00008A
+S A$dbglnkwrhex16$238 Def00007F
+S A$dbglnkwrhex16$193 Def00004F
+S A$dbglnkwrhex16$184 Def000049
+S A$dbglnkwrhex16$175 Def000042
+S A$dbglnkwrhex16$166 Def00003C
+S A$dbglnkwrhex16$148 Def000022
+S A$dbglnkwrhex16$139 Def000011
+S A$dbglnkwrhex16$338 Def000105
+S A$dbglnkwrhex16$329 Def0000F4
+S A$dbglnkwrhex16$284 Def0000BA
+S A$dbglnkwrhex16$257 Def000096
+S A$dbglnkwrhex16$239 Def000080
+S A$dbglnkwrhex16$194 Def000050
+S A$dbglnkwrhex16$185 Def00004A
+S A$dbglnkwrhex16$176 Def000044
+S A$dbglnkwrhex16$167 Def00003D
+S A$dbglnkwrhex16$158 Def000034
+S A$dbglnkwrhex16$149 Def000024
+S A$dbglnkwrhex16$339 Def000108
+S A$dbglnkwrhex16$294 Def0000C5
+S A$dbglnkwrhex16$276 Def0000B9
+S A$dbglnkwrhex16$267 Def0000A7
+S A$dbglnkwrhex16$258 Def000099
+S A$dbglnkwrhex16$249 Def00008B
+S A$dbglnkwrhex16$195 Def000051
+S A$dbglnkwrhex16$186 Def00004C
+S A$dbglnkwrhex16$177 Def000046
+S A$dbglnkwrhex16$295 Def0000C6
+S A$dbglnkwrhex16$286 Def0000BC
+S A$dbglnkwrhex16$268 Def0000A9
+S A$dbglnkwrhex16$259 Def00009B
+S A$dbglnkwrhex16$196 Def000052
+S A$dbglnkwrhex16$187 Def00004D
+S _dbglink_writehex16 Def000000
+S A$dbglnkwrhex16$287 Def0000BE
+S A$dbglnkwrhex16$269 Def0000AB
+S A$dbglnkwrhex16$197 Def000054
+S A$dbglnkwrhex16$198 Def000056
+S C$dbglnkwrhex16.c$25$0$0 Def000000
+S A$dbglnkwrhex16$298 Def0000C7
+S A$dbglnkwrhex16$299 Def0000C9
+S XG$dbglink_writehex16$0$0 Def000111
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrhex16
+F:G$dbglink_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrhex16.dbglink_writehex16$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrhex16.dbglink_writehex16$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrhex16.dbglink_writehex16$val$1$60({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhex32
+
+;!FILE libmf/dbglnkwrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M dbglnkwrhex32
+O -mmcs51 --model-small
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S C$dbglnkwrhex32.c$282$1$61 Def000000
+S C$dbglnkwrhex32.c$283$1$61 Def000127
+S A$dbglnkwrhex32$210 Def000062
+S A$dbglnkwrhex32$120 Def000005
+S A$dbglnkwrhex32$310 Def0000D5
+S A$dbglnkwrhex32$220 Def00006F
+S A$dbglnkwrhex32$211 Def000063
+S A$dbglnkwrhex32$202 Def000058
+S A$dbglnkwrhex32$130 Def000010
+S A$dbglnkwrhex32$121 Def000007
+S G$dbglink_writehex32$0$0 Def000000
+S A$dbglnkwrhex32$221 Def000070
+S A$dbglnkwrhex32$212 Def000065
+S A$dbglnkwrhex32$203 Def000059
+S A$dbglnkwrhex32$122 Def000008
+S A$dbglnkwrhex32$330 Def0000F1
+S A$dbglnkwrhex32$321 Def0000E1
+S A$dbglnkwrhex32$312 Def0000D8
+S A$dbglnkwrhex32$240 Def00007F
+S A$dbglnkwrhex32$231 Def000079
+S A$dbglnkwrhex32$222 Def000072
+S A$dbglnkwrhex32$213 Def000067
+S A$dbglnkwrhex32$204 Def00005A
+S A$dbglnkwrhex32$150 Def000024
+S A$dbglnkwrhex32$141 Def000014
+S A$dbglnkwrhex32$123 Def000009
+S A$dbglnkwrhex32$340 Def0000FA
+S A$dbglnkwrhex32$331 Def0000F3
+S A$dbglnkwrhex32$322 Def0000E2
+S A$dbglnkwrhex32$304 Def0000D0
+S A$dbglnkwrhex32$250 Def00008B
+S A$dbglnkwrhex32$241 Def000081
+S A$dbglnkwrhex32$223 Def000073
+S A$dbglnkwrhex32$205 Def00005B
+S A$dbglnkwrhex32$160 Def000030
+S A$dbglnkwrhex32$151 Def000026
+S A$dbglnkwrhex32$142 Def000017
+S A$dbglnkwrhex32$124 Def00000A
+S A$dbglnkwrhex32$350 Def00010D
+S A$dbglnkwrhex32$341 Def0000FC
+S A$dbglnkwrhex32$314 Def0000DB
+S A$dbglnkwrhex32$260 Def000097
+S A$dbglnkwrhex32$251 Def00008D
+S A$dbglnkwrhex32$215 Def000069
+S A$dbglnkwrhex32$206 Def00005C
+S A$dbglnkwrhex32$161 Def000033
+S A$dbglnkwrhex32$152 Def000027
+S A$dbglnkwrhex32$143 Def000018
+S A$dbglnkwrhex32$134 Def000012
+S A$dbglnkwrhex32$125 Def00000C
+S A$dbglnkwrhex32$116 Def000000
+S A$dbglnkwrhex32$360 Def000120
+S A$dbglnkwrhex32$351 Def00010E
+S A$dbglnkwrhex32$342 Def0000FD
+S A$dbglnkwrhex32$333 Def0000F5
+S A$dbglnkwrhex32$324 Def0000E4
+S A$dbglnkwrhex32$315 Def0000DC
+S A$dbglnkwrhex32$306 Def0000D2
+S A$dbglnkwrhex32$252 Def00008E
+S A$dbglnkwrhex32$243 Def000083
+S A$dbglnkwrhex32$225 Def000075
+S A$dbglnkwrhex32$216 Def00006A
+S A$dbglnkwrhex32$207 Def00005E
+S A$dbglnkwrhex32$162 Def000036
+S A$dbglnkwrhex32$153 Def000028
+S A$dbglnkwrhex32$144 Def00001B
+S A$dbglnkwrhex32$117 Def000001
+S A$dbglnkwrhex32$361 Def000122
+S A$dbglnkwrhex32$352 Def000110
+S A$dbglnkwrhex32$343 Def0000FF
+S A$dbglnkwrhex32$325 Def0000E6
+S A$dbglnkwrhex32$307 Def0000D4
+S A$dbglnkwrhex32$280 Def0000B3
+S A$dbglnkwrhex32$262 Def000099
+S A$dbglnkwrhex32$253 Def00008F
+S A$dbglnkwrhex32$244 Def000085
+S A$dbglnkwrhex32$217 Def00006C
+S A$dbglnkwrhex32$208 Def000060
+S A$dbglnkwrhex32$172 Def000040
+S A$dbglnkwrhex32$163 Def000038
+S A$dbglnkwrhex32$154 Def000029
+S A$dbglnkwrhex32$145 Def00001C
+S A$dbglnkwrhex32$127 Def00000E
+S A$dbglnkwrhex32$344 Def000101
+S A$dbglnkwrhex32$326 Def0000E8
+S A$dbglnkwrhex32$290 Def0000C3
+S A$dbglnkwrhex32$254 Def000091
+S A$dbglnkwrhex32$245 Def000088
+S A$dbglnkwrhex32$227 Def000076
+S A$dbglnkwrhex32$218 Def00006D
+S A$dbglnkwrhex32$173 Def000041
+S A$dbglnkwrhex32$164 Def00003A
+S A$dbglnkwrhex32$155 Def00002A
+S A$dbglnkwrhex32$146 Def00001D
+S A$dbglnkwrhex32$128 Def00000F
+S A$dbglnkwrhex32$119 Def000003
+S A$dbglnkwrhex32$363 Def000124
+S A$dbglnkwrhex32$354 Def000112
+S A$dbglnkwrhex32$345 Def000104
+S A$dbglnkwrhex32$327 Def0000EA
+S A$dbglnkwrhex32$318 Def0000DD
+S A$dbglnkwrhex32$291 Def0000C6
+S A$dbglnkwrhex32$282 Def0000B5
+S A$dbglnkwrhex32$273 Def0000A3
+S A$dbglnkwrhex32$264 Def00009C
+S A$dbglnkwrhex32$228 Def000078
+S A$dbglnkwrhex32$192 Def000051
+S A$dbglnkwrhex32$183 Def000048
+S A$dbglnkwrhex32$174 Def000043
+S A$dbglnkwrhex32$165 Def00003B
+S A$dbglnkwrhex32$156 Def00002B
+S A$dbglnkwrhex32$147 Def00001F
+S A$dbglnkwrhex32$355 Def000114
+S A$dbglnkwrhex32$346 Def000106
+S A$dbglnkwrhex32$328 Def0000EC
+S A$dbglnkwrhex32$319 Def0000DF
+S A$dbglnkwrhex32$292 Def0000C9
+S A$dbglnkwrhex32$283 Def0000B8
+S A$dbglnkwrhex32$274 Def0000A5
+S A$dbglnkwrhex32$247 Def00008A
+S A$dbglnkwrhex32$238 Def00007B
+S A$dbglnkwrhex32$193 Def000052
+S A$dbglnkwrhex32$184 Def00004B
+S A$dbglnkwrhex32$175 Def000044
+S A$dbglnkwrhex32$166 Def00003C
+S A$dbglnkwrhex32$157 Def00002C
+S A$dbglnkwrhex32$148 Def000021
+S A$dbglnkwrhex32$365 Def000125
+S A$dbglnkwrhex32$356 Def000116
+S A$dbglnkwrhex32$347 Def000108
+S A$dbglnkwrhex32$338 Def0000F6
+S A$dbglnkwrhex32$329 Def0000EF
+S A$dbglnkwrhex32$293 Def0000CB
+S A$dbglnkwrhex32$284 Def0000B9
+S A$dbglnkwrhex32$275 Def0000A7
+S A$dbglnkwrhex32$266 Def00009F
+S A$dbglnkwrhex32$257 Def000094
+S A$dbglnkwrhex32$239 Def00007D
+S A$dbglnkwrhex32$194 Def000053
+S A$dbglnkwrhex32$185 Def00004C
+S A$dbglnkwrhex32$176 Def000046
+S A$dbglnkwrhex32$158 Def00002E
+S A$dbglnkwrhex32$149 Def000022
+S A$dbglnkwrhex32$357 Def000118
+S A$dbglnkwrhex32$339 Def0000F8
+S A$dbglnkwrhex32$294 Def0000CD
+S A$dbglnkwrhex32$285 Def0000BB
+S A$dbglnkwrhex32$276 Def0000A9
+S A$dbglnkwrhex32$267 Def0000A0
+S A$dbglnkwrhex32$258 Def000095
+S A$dbglnkwrhex32$195 Def000054
+S A$dbglnkwrhex32$186 Def00004E
+S A$dbglnkwrhex32$177 Def000047
+S A$dbglnkwrhex32$168 Def00003E
+S A$dbglnkwrhex32$358 Def00011B
+S A$dbglnkwrhex32$349 Def00010A
+S A$dbglnkwrhex32$277 Def0000AC
+S A$dbglnkwrhex32$259 Def000096
+S A$dbglnkwrhex32$196 Def000056
+S A$dbglnkwrhex32$187 Def000050
+S _dbglink_writehex32 Def000000
+S A$dbglnkwrhex32$359 Def00011E
+S A$dbglnkwrhex32$296 Def0000CF
+S A$dbglnkwrhex32$287 Def0000BD
+S A$dbglnkwrhex32$278 Def0000AF
+S A$dbglnkwrhex32$269 Def0000A1
+S A$dbglnkwrhex32$197 Def000057
+S A$dbglnkwrhex32$288 Def0000BF
+S A$dbglnkwrhex32$279 Def0000B1
+S C$dbglnkwrhex32.c$25$0$0 Def000000
+S A$dbglnkwrhex32$289 Def0000C1
+S XG$dbglink_writehex32$0$0 Def000127
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrhex32
+F:G$dbglink_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrhex32.dbglink_writehex32$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrhex32.dbglink_writehex32$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrhex32.dbglink_writehex32$val$1$60({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+crc8ccitt
+
+;!FILE libmf/crc8ccitt.asm
+XH3
+H 1A areas 320 global symbols
+M crc8ccitt
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 72 flags 20 addr 0
+S C$crc8ccitt.c$7$0$0 Def000000
+S _crc8_ccitt Def000014
+S G$crc8_ccitt_byte$0$0 Def000000
+S XG$crc8_ccitt$0$0 Def000072
+S A$crc8ccitt$1220 Def00001D
+S A$crc8ccitt$1221 Def000020
+S A$crc8ccitt$1212 Def000014
+S A$crc8ccitt$1231 Def00002D
+S A$crc8ccitt$1222 Def000023
+S A$crc8ccitt$1213 Def000016
+S A$crc8ccitt$1250 Def000042
+S A$crc8ccitt$1232 Def00002E
+S A$crc8ccitt$1223 Def000025
+S A$crc8ccitt$1214 Def000017
+S _crc8_ccitt_byte Def000000
+S A$crc8ccitt$1260 Def00004E
+S A$crc8ccitt$1251 Def000044
+S A$crc8ccitt$1242 Def00003A
+S A$crc8ccitt$1233 Def00002F
+S A$crc8ccitt$1215 Def000018
+S A$crc8ccitt$1270 Def00005A
+S A$crc8ccitt$1261 Def00004F
+S A$crc8ccitt$1243 Def00003B
+S A$crc8ccitt$1234 Def000031
+S A$crc8ccitt$1216 Def000019
+S A$crc8ccitt$1180 Def000005
+S A$crc8ccitt$1280 Def000064
+S A$crc8ccitt$1271 Def00005B
+S A$crc8ccitt$1262 Def000050
+S A$crc8ccitt$1253 Def000046
+S A$crc8ccitt$1244 Def00003C
+S A$crc8ccitt$1226 Def000028
+S A$crc8ccitt$1217 Def00001A
+S A$crc8ccitt$1190 Def000013
+S A$crc8ccitt$1181 Def000007
+S A$crc8ccitt$1290 Def00006F
+S A$crc8ccitt$1281 Def000065
+S A$crc8ccitt$1272 Def00005D
+S A$crc8ccitt$1254 Def000048
+S A$crc8ccitt$1245 Def00003D
+S A$crc8ccitt$1236 Def000033
+S A$crc8ccitt$1227 Def000029
+S A$crc8ccitt$1218 Def00001B
+S A$crc8ccitt$1291 Def000071
+S A$crc8ccitt$1282 Def000066
+S A$crc8ccitt$1264 Def000052
+S A$crc8ccitt$1255 Def000049
+S A$crc8ccitt$1246 Def00003E
+S A$crc8ccitt$1237 Def000035
+S A$crc8ccitt$1228 Def00002A
+S A$crc8ccitt$1219 Def00001C
+S A$crc8ccitt$1183 Def000009
+S C$crc8ccitt.c$105$1$65 Def000014
+S A$crc8ccitt$1283 Def000068
+S A$crc8ccitt$1265 Def000053
+S A$crc8ccitt$1256 Def00004B
+S A$crc8ccitt$1238 Def000036
+S A$crc8ccitt$1229 Def00002B
+S A$crc8ccitt$1184 Def00000A
+S C$crc8ccitt.c$106$1$65 Def000072
+S A$crc8ccitt$1275 Def00005F
+S A$crc8ccitt$1266 Def000054
+S A$crc8ccitt$1248 Def000040
+S A$crc8ccitt$1239 Def000038
+S A$crc8ccitt$1185 Def00000B
+S A$crc8ccitt$1176 Def000000
+S A$crc8ccitt$1285 Def00006A
+S A$crc8ccitt$1276 Def000060
+S A$crc8ccitt$1267 Def000056
+S A$crc8ccitt$1249 Def000041
+S A$crc8ccitt$1186 Def00000D
+S A$crc8ccitt$1177 Def000002
+S A$crc8ccitt$1286 Def00006C
+S A$crc8ccitt$1277 Def000061
+S A$crc8ccitt$1259 Def00004D
+S A$crc8ccitt$1178 Def000003
+S A$crc8ccitt$1287 Def00006D
+S A$crc8ccitt$1278 Def000062
+S A$crc8ccitt$1269 Def000058
+S A$crc8ccitt$1188 Def00000F
+S A$crc8ccitt$1179 Def000004
+S A$crc8ccitt$1189 Def000011
+S XG$crc8_ccitt_byte$0$0 Def000014
+S C$crc8ccitt.c$25$1$63 Def000000
+S C$crc8ccitt.c$26$1$63 Def000014
+S C$crc8ccitt.c$28$1$63 Def000014
+S G$crc8_ccitt$0$0 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 E6 65 82 78 08
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F D8 F8 F5 82 22
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 A8 81 18 18 E6 FA 18 E6 FB 20 F7 1A 30
+R 00 00 00 16
+T 00 00 21 F6 2A A8 82 20 F5 37
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6B 7C 08
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 33
+R 00 00 00 16
+T 00 00 33 DC F8 FB DA F0 80 35
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A E4 93 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 46
+R 00 00 00 16
+T 00 00 46 DC F8 FB DA EF 80 22
+R 00 00 00 16
+T 00 00 4D
+R 00 00 00 16
+T 00 00 4D E0 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 DC F8 FB DA F0 80 10
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E2 08 6B 7C 08
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 6A
+R 00 00 00 16
+T 00 00 6A DC F8 FB DA F0
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 8B 82 22
+R 00 00 00 16
+
+
+M:crc8ccitt
+F:G$crc8_ccitt_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccitt.crc8_ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8ccitt.crc8_ccitt_byte$crc$1$62({1}SC:U),R,0,0,[]
+F:G$crc8_ccitt$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccitt.crc8_ccitt$len$1$64({1}SC:U),B,1,-3
+S:Lcrc8ccitt.crc8_ccitt$init$1$64({1}SC:U),B,1,-4
+S:Lcrc8ccitt.crc8_ccitt$buf$1$64({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
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+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewire
+
+;!FILE libmf/crc8onewire.asm
+XH3
+H 1A areas 320 global symbols
+M crc8onewire
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 72 flags 20 addr 0
+S A$crc8onewire$1283 Def000068
+S A$crc8onewire$1265 Def000053
+S A$crc8onewire$1256 Def00004B
+S A$crc8onewire$1238 Def000036
+S A$crc8onewire$1229 Def00002B
+S A$crc8onewire$1184 Def00000A
+S C$crc8onewire.c$106$1$65 Def000072
+S A$crc8onewire$1275 Def00005F
+S A$crc8onewire$1266 Def000054
+S A$crc8onewire$1248 Def000040
+S A$crc8onewire$1239 Def000038
+S A$crc8onewire$1185 Def00000B
+S A$crc8onewire$1176 Def000000
+S A$crc8onewire$1285 Def00006A
+S A$crc8onewire$1276 Def000060
+S A$crc8onewire$1267 Def000056
+S A$crc8onewire$1249 Def000041
+S A$crc8onewire$1186 Def00000D
+S A$crc8onewire$1177 Def000002
+S A$crc8onewire$1286 Def00006C
+S A$crc8onewire$1277 Def000061
+S A$crc8onewire$1259 Def00004D
+S A$crc8onewire$1178 Def000003
+S A$crc8onewire$1287 Def00006D
+S A$crc8onewire$1278 Def000062
+S A$crc8onewire$1269 Def000058
+S A$crc8onewire$1188 Def00000F
+S A$crc8onewire$1179 Def000004
+S A$crc8onewire$1189 Def000011
+S XG$crc8_onewire_byte$0$0 Def000014
+S C$crc8onewire.c$25$1$63 Def000000
+S C$crc8onewire.c$26$1$63 Def000014
+S C$crc8onewire.c$28$1$63 Def000014
+S G$crc8_onewire$0$0 Def000014
+S C$crc8onewire.c$7$0$0 Def000000
+S _crc8_onewire Def000014
+S G$crc8_onewire_byte$0$0 Def000000
+S XG$crc8_onewire$0$0 Def000072
+S A$crc8onewire$1220 Def00001D
+S A$crc8onewire$1221 Def000020
+S A$crc8onewire$1212 Def000014
+S A$crc8onewire$1231 Def00002D
+S A$crc8onewire$1222 Def000023
+S A$crc8onewire$1213 Def000016
+S A$crc8onewire$1250 Def000042
+S A$crc8onewire$1232 Def00002E
+S A$crc8onewire$1223 Def000025
+S A$crc8onewire$1214 Def000017
+S _crc8_onewire_byte Def000000
+S A$crc8onewire$1260 Def00004E
+S A$crc8onewire$1251 Def000044
+S A$crc8onewire$1242 Def00003A
+S A$crc8onewire$1233 Def00002F
+S A$crc8onewire$1215 Def000018
+S A$crc8onewire$1270 Def00005A
+S A$crc8onewire$1261 Def00004F
+S A$crc8onewire$1243 Def00003B
+S A$crc8onewire$1234 Def000031
+S A$crc8onewire$1216 Def000019
+S A$crc8onewire$1180 Def000005
+S A$crc8onewire$1280 Def000064
+S A$crc8onewire$1271 Def00005B
+S A$crc8onewire$1262 Def000050
+S A$crc8onewire$1253 Def000046
+S A$crc8onewire$1244 Def00003C
+S A$crc8onewire$1226 Def000028
+S A$crc8onewire$1217 Def00001A
+S A$crc8onewire$1190 Def000013
+S A$crc8onewire$1181 Def000007
+S A$crc8onewire$1290 Def00006F
+S A$crc8onewire$1281 Def000065
+S A$crc8onewire$1272 Def00005D
+S A$crc8onewire$1254 Def000048
+S A$crc8onewire$1245 Def00003D
+S A$crc8onewire$1236 Def000033
+S A$crc8onewire$1227 Def000029
+S A$crc8onewire$1218 Def00001B
+S A$crc8onewire$1291 Def000071
+S A$crc8onewire$1282 Def000066
+S A$crc8onewire$1264 Def000052
+S A$crc8onewire$1255 Def000049
+S A$crc8onewire$1246 Def00003E
+S A$crc8onewire$1237 Def000035
+S A$crc8onewire$1228 Def00002A
+S A$crc8onewire$1219 Def00001C
+S A$crc8onewire$1183 Def000009
+S C$crc8onewire.c$105$1$65 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 E6 65 82 78 08
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 C3 33 50 02 64 31
+R 00 00 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F D8 F8 F5 82 22
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 A8 81 18 18 E6 FA 18 E6 FB 20 F7 1A 30
+R 00 00 00 16
+T 00 00 21 F6 2A A8 82 20 F5 37
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6B 7C 08
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D C3 33 50 02 64 31
+R 00 00 00 16
+T 00 00 33
+R 00 00 00 16
+T 00 00 33 DC F8 FB DA F0 80 35
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A E4 93 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 C3 33 50 02 64 31
+R 00 00 00 16
+T 00 00 46
+R 00 00 00 16
+T 00 00 46 DC F8 FB DA EF 80 22
+R 00 00 00 16
+T 00 00 4D
+R 00 00 00 16
+T 00 00 4D E0 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 C3 33 50 02 64 31
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 DC F8 FB DA F0 80 10
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E2 08 6B 7C 08
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C3 33 50 02 64 31
+R 00 00 00 16
+T 00 00 6A
+R 00 00 00 16
+T 00 00 6A DC F8 FB DA F0
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 8B 82 22
+R 00 00 00 16
+
+
+M:crc8onewire
+F:G$crc8_onewire_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewire.crc8_onewire_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8onewire.crc8_onewire_byte$crc$1$62({1}SC:U),R,0,0,[]
+F:G$crc8_onewire$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewire.crc8_onewire$len$1$64({1}SC:U),B,1,-3
+S:Lcrc8onewire.crc8_onewire$init$1$64({1}SC:U),B,1,-4
+S:Lcrc8onewire.crc8_onewire$buf$1$64({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
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+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tccitt
+
+;!FILE libmf/crc8tccitt.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tccitt
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc8ccitt_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S G$crc_crc8ccitt_byte$0$0 Def000000
+S _crc_crc8ccitt_byte Def000000
+S A$crc8tccitt$110 Def000005
+S A$crc8tccitt$111 Def000006
+S A$crc8tccitt$112 Def000008
+S A$crc8tccitt$113 Def00000B
+S A$crc8tccitt$114 Def00000C
+S A$crc8tccitt$115 Def00000E
+S A$crc8tccitt$107 Def000000
+S XG$crc_crc8ccitt_byte$0$0 Def00000F
+S A$crc8tccitt$108 Def000002
+S A$crc8tccitt$109 Def000004
+S C$crc8tccitt.c$23$1$63 Def000000
+S C$crc8tccitt.c$24$1$63 Def00000F
+S C$crc8tccitt.c$9$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 01
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tccitt
+F:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tccitt.crc_crc8ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tccitt.crc_crc8ccitt_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tccittmsb
+
+;!FILE libmf/crc8tccittmsb.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tccittmsb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc8ccitt_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tccittmsb$110 Def000005
+S A$crc8tccittmsb$111 Def000006
+S A$crc8tccittmsb$112 Def000008
+S A$crc8tccittmsb$113 Def00000B
+S A$crc8tccittmsb$114 Def00000C
+S A$crc8tccittmsb$115 Def00000E
+S A$crc8tccittmsb$107 Def000000
+S A$crc8tccittmsb$108 Def000002
+S A$crc8tccittmsb$109 Def000004
+S C$crc8tccittmsb.c$23$1$63 Def000000
+S C$crc8tccittmsb.c$24$1$63 Def00000F
+S G$crc_crc8ccitt_msb_byte$0$0 Def000000
+S _crc_crc8ccitt_msb_byte Def000000
+S C$crc8tccittmsb.c$9$0$0 Def000000
+S XG$crc_crc8ccitt_msb_byte$0$0 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 01
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tccittmsb
+F:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tccittmsb.crc_crc8ccitt_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tccittmsb.crc_crc8ccitt_msb_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tonewire
+
+;!FILE libmf/crc8tonewire.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tonewire
+O -mmcs51 --model-small
+S _crc_crc8onewire_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tonewire$109 Def000004
+S C$crc8tonewire.c$23$1$63 Def000000
+S C$crc8tonewire.c$24$1$63 Def00000F
+S C$crc8tonewire.c$9$0$0 Def000000
+S G$crc_crc8onewire_byte$0$0 Def000000
+S _crc_crc8onewire_byte Def000000
+S A$crc8tonewire$110 Def000005
+S A$crc8tonewire$111 Def000006
+S A$crc8tonewire$112 Def000008
+S A$crc8tonewire$113 Def00000B
+S A$crc8tonewire$114 Def00000C
+S A$crc8tonewire$115 Def00000E
+S A$crc8tonewire$107 Def000000
+S XG$crc_crc8onewire_byte$0$0 Def00000F
+S A$crc8tonewire$108 Def000002
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 00
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tonewire
+F:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tonewire.crc_crc8onewire_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tonewire.crc_crc8onewire_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tonewiremsb
+
+;!FILE libmf/crc8tonewiremsb.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tonewiremsb
+O -mmcs51 --model-small
+S _crc_crc8onewire_msbtable Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tonewiremsb$107 Def000000
+S A$crc8tonewiremsb$108 Def000002
+S A$crc8tonewiremsb$109 Def000004
+S C$crc8tonewiremsb.c$23$1$63 Def000000
+S C$crc8tonewiremsb.c$24$1$63 Def00000F
+S G$crc_crc8onewire_msb_byte$0$0 Def000000
+S _crc_crc8onewire_msb_byte Def000000
+S C$crc8tonewiremsb.c$9$0$0 Def000000
+S XG$crc_crc8onewire_msb_byte$0$0 Def00000F
+S A$crc8tonewiremsb$110 Def000005
+S A$crc8tonewiremsb$111 Def000006
+S A$crc8tonewiremsb$112 Def000008
+S A$crc8tonewiremsb$113 Def00000B
+S A$crc8tonewiremsb$114 Def00000C
+S A$crc8tonewiremsb$115 Def00000E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 00
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tonewiremsb
+F:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tonewiremsb.crc_crc8onewire_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tonewiremsb.crc_crc8onewire_msb_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittb
+
+;!FILE libmf/crc8ccittb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8ccittb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc8ccitt_table Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S A$crc8ccittb$110 Def000004
+S A$crc8ccittb$120 Def00000E
+S A$crc8ccittb$111 Def000005
+S A$crc8ccittb$121 Def000010
+S A$crc8ccittb$112 Def000006
+S A$crc8ccittb$140 Def000029
+S A$crc8ccittb$131 Def00001F
+S A$crc8ccittb$122 Def000011
+S A$crc8ccittb$113 Def000007
+S A$crc8ccittb$141 Def00002B
+S A$crc8ccittb$132 Def000020
+S A$crc8ccittb$123 Def000013
+S A$crc8ccittb$114 Def000008
+S A$crc8ccittb$160 Def000040
+S A$crc8ccittb$151 Def000035
+S A$crc8ccittb$115 Def000009
+S XG$crc_crc8ccitt$0$0 Def000069
+S A$crc8ccittb$170 Def00004E
+S A$crc8ccittb$152 Def000037
+S A$crc8ccittb$143 Def00002D
+S A$crc8ccittb$134 Def000021
+S A$crc8ccittb$125 Def000014
+S A$crc8ccittb$116 Def00000A
+S A$crc8ccittb$180 Def00005A
+S A$crc8ccittb$171 Def000050
+S A$crc8ccittb$162 Def000042
+S A$crc8ccittb$144 Def00002E
+S A$crc8ccittb$135 Def000022
+S A$crc8ccittb$126 Def000017
+S A$crc8ccittb$117 Def00000B
+S A$crc8ccittb$108 Def000000
+S A$crc8ccittb$181 Def00005D
+S A$crc8ccittb$163 Def000043
+S A$crc8ccittb$154 Def000039
+S A$crc8ccittb$136 Def000025
+S A$crc8ccittb$127 Def00001A
+S A$crc8ccittb$118 Def00000C
+S A$crc8ccittb$109 Def000002
+S A$crc8ccittb$182 Def00005E
+S A$crc8ccittb$173 Def000052
+S A$crc8ccittb$164 Def000046
+S A$crc8ccittb$155 Def00003B
+S A$crc8ccittb$146 Def00002F
+S A$crc8ccittb$137 Def000026
+S A$crc8ccittb$128 Def00001C
+S A$crc8ccittb$119 Def00000D
+S A$crc8ccittb$174 Def000053
+S A$crc8ccittb$165 Def000047
+S A$crc8ccittb$147 Def000030
+S C$crc8ccittb.c$10$0$0 Def000000
+S A$crc8ccittb$184 Def00005F
+S A$crc8ccittb$175 Def000054
+S A$crc8ccittb$157 Def00003C
+S A$crc8ccittb$148 Def000033
+S A$crc8ccittb$139 Def000027
+S A$crc8ccittb$185 Def000061
+S A$crc8ccittb$176 Def000055
+S A$crc8ccittb$167 Def000048
+S A$crc8ccittb$158 Def00003D
+S A$crc8ccittb$149 Def000034
+S A$crc8ccittb$186 Def000063
+S A$crc8ccittb$177 Def000057
+S A$crc8ccittb$168 Def00004A
+S A$crc8ccittb$159 Def00003E
+S A$crc8ccittb$187 Def000065
+S A$crc8ccittb$169 Def00004C
+S A$crc8ccittb$188 Def000067
+S A$crc8ccittb$179 Def000059
+S C$crc8ccittb.c$96$1$63 Def000000
+S C$crc8ccittb.c$97$1$63 Def000069
+S G$crc_crc8ccitt$0$0 Def000000
+S _crc_crc8ccitt Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 01
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 01
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 01
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 01
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8ccittb
+F:G$crc_crc8ccitt$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccittb.crc_crc8ccitt$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8ccittb.crc_crc8ccitt$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8ccittb.crc_crc8ccitt$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittmsbb
+
+;!FILE libmf/crc8ccittmsbb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8ccittmsbb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc8ccitt_msbtable Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S A$crc8ccittmsbb$110 Def000004
+S A$crc8ccittmsbb$120 Def00000E
+S A$crc8ccittmsbb$111 Def000005
+S A$crc8ccittmsbb$121 Def000010
+S A$crc8ccittmsbb$112 Def000006
+S A$crc8ccittmsbb$140 Def000029
+S A$crc8ccittmsbb$131 Def00001F
+S A$crc8ccittmsbb$122 Def000011
+S A$crc8ccittmsbb$113 Def000007
+S A$crc8ccittmsbb$141 Def00002B
+S A$crc8ccittmsbb$132 Def000020
+S A$crc8ccittmsbb$123 Def000013
+S A$crc8ccittmsbb$114 Def000008
+S A$crc8ccittmsbb$160 Def000040
+S A$crc8ccittmsbb$151 Def000035
+S A$crc8ccittmsbb$115 Def000009
+S A$crc8ccittmsbb$170 Def00004E
+S A$crc8ccittmsbb$152 Def000037
+S A$crc8ccittmsbb$143 Def00002D
+S A$crc8ccittmsbb$134 Def000021
+S A$crc8ccittmsbb$125 Def000014
+S A$crc8ccittmsbb$116 Def00000A
+S A$crc8ccittmsbb$180 Def00005A
+S A$crc8ccittmsbb$171 Def000050
+S A$crc8ccittmsbb$162 Def000042
+S A$crc8ccittmsbb$144 Def00002E
+S A$crc8ccittmsbb$135 Def000022
+S A$crc8ccittmsbb$126 Def000017
+S A$crc8ccittmsbb$117 Def00000B
+S A$crc8ccittmsbb$108 Def000000
+S A$crc8ccittmsbb$181 Def00005D
+S A$crc8ccittmsbb$163 Def000043
+S A$crc8ccittmsbb$154 Def000039
+S A$crc8ccittmsbb$136 Def000025
+S A$crc8ccittmsbb$127 Def00001A
+S A$crc8ccittmsbb$118 Def00000C
+S A$crc8ccittmsbb$109 Def000002
+S A$crc8ccittmsbb$182 Def00005E
+S A$crc8ccittmsbb$173 Def000052
+S A$crc8ccittmsbb$164 Def000046
+S A$crc8ccittmsbb$155 Def00003B
+S A$crc8ccittmsbb$146 Def00002F
+S A$crc8ccittmsbb$137 Def000026
+S A$crc8ccittmsbb$128 Def00001C
+S A$crc8ccittmsbb$119 Def00000D
+S A$crc8ccittmsbb$174 Def000053
+S A$crc8ccittmsbb$165 Def000047
+S A$crc8ccittmsbb$147 Def000030
+S C$crc8ccittmsbb.c$10$0$0 Def000000
+S A$crc8ccittmsbb$184 Def00005F
+S A$crc8ccittmsbb$175 Def000054
+S A$crc8ccittmsbb$157 Def00003C
+S A$crc8ccittmsbb$148 Def000033
+S A$crc8ccittmsbb$139 Def000027
+S A$crc8ccittmsbb$185 Def000061
+S A$crc8ccittmsbb$176 Def000055
+S A$crc8ccittmsbb$167 Def000048
+S A$crc8ccittmsbb$158 Def00003D
+S A$crc8ccittmsbb$149 Def000034
+S G$crc_crc8ccitt_msb$0$0 Def000000
+S A$crc8ccittmsbb$186 Def000063
+S A$crc8ccittmsbb$177 Def000057
+S A$crc8ccittmsbb$168 Def00004A
+S A$crc8ccittmsbb$159 Def00003E
+S A$crc8ccittmsbb$187 Def000065
+S A$crc8ccittmsbb$169 Def00004C
+S A$crc8ccittmsbb$188 Def000067
+S A$crc8ccittmsbb$179 Def000059
+S C$crc8ccittmsbb.c$96$1$63 Def000000
+S C$crc8ccittmsbb.c$97$1$63 Def000069
+S _crc_crc8ccitt_msb Def000000
+S XG$crc_crc8ccitt_msb$0$0 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 01
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 01
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 01
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 01
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8ccittmsbb
+F:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewireb
+
+;!FILE libmf/crc8onewireb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8onewireb
+O -mmcs51 --model-small
+S _crc_crc8onewire_table Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S G$crc_crc8onewire$0$0 Def000000
+S _crc_crc8onewire Def000000
+S A$crc8onewireb$110 Def000004
+S A$crc8onewireb$120 Def00000E
+S A$crc8onewireb$111 Def000005
+S A$crc8onewireb$121 Def000010
+S A$crc8onewireb$112 Def000006
+S A$crc8onewireb$140 Def000029
+S A$crc8onewireb$131 Def00001F
+S A$crc8onewireb$122 Def000011
+S A$crc8onewireb$113 Def000007
+S A$crc8onewireb$141 Def00002B
+S A$crc8onewireb$132 Def000020
+S A$crc8onewireb$123 Def000013
+S A$crc8onewireb$114 Def000008
+S A$crc8onewireb$160 Def000040
+S A$crc8onewireb$151 Def000035
+S A$crc8onewireb$115 Def000009
+S XG$crc_crc8onewire$0$0 Def000069
+S A$crc8onewireb$170 Def00004E
+S A$crc8onewireb$152 Def000037
+S A$crc8onewireb$143 Def00002D
+S A$crc8onewireb$134 Def000021
+S A$crc8onewireb$125 Def000014
+S A$crc8onewireb$116 Def00000A
+S A$crc8onewireb$180 Def00005A
+S A$crc8onewireb$171 Def000050
+S A$crc8onewireb$162 Def000042
+S A$crc8onewireb$144 Def00002E
+S A$crc8onewireb$135 Def000022
+S A$crc8onewireb$126 Def000017
+S A$crc8onewireb$117 Def00000B
+S A$crc8onewireb$108 Def000000
+S A$crc8onewireb$181 Def00005D
+S A$crc8onewireb$163 Def000043
+S A$crc8onewireb$154 Def000039
+S A$crc8onewireb$136 Def000025
+S A$crc8onewireb$127 Def00001A
+S A$crc8onewireb$118 Def00000C
+S A$crc8onewireb$109 Def000002
+S A$crc8onewireb$182 Def00005E
+S A$crc8onewireb$173 Def000052
+S A$crc8onewireb$164 Def000046
+S A$crc8onewireb$155 Def00003B
+S A$crc8onewireb$146 Def00002F
+S A$crc8onewireb$137 Def000026
+S A$crc8onewireb$128 Def00001C
+S A$crc8onewireb$119 Def00000D
+S A$crc8onewireb$174 Def000053
+S A$crc8onewireb$165 Def000047
+S A$crc8onewireb$147 Def000030
+S C$crc8onewireb.c$10$0$0 Def000000
+S A$crc8onewireb$184 Def00005F
+S A$crc8onewireb$175 Def000054
+S A$crc8onewireb$157 Def00003C
+S A$crc8onewireb$148 Def000033
+S A$crc8onewireb$139 Def000027
+S A$crc8onewireb$185 Def000061
+S A$crc8onewireb$176 Def000055
+S A$crc8onewireb$167 Def000048
+S A$crc8onewireb$158 Def00003D
+S A$crc8onewireb$149 Def000034
+S A$crc8onewireb$186 Def000063
+S A$crc8onewireb$177 Def000057
+S A$crc8onewireb$168 Def00004A
+S A$crc8onewireb$159 Def00003E
+S A$crc8onewireb$187 Def000065
+S A$crc8onewireb$169 Def00004C
+S A$crc8onewireb$188 Def000067
+S A$crc8onewireb$179 Def000059
+S C$crc8onewireb.c$96$1$63 Def000000
+S C$crc8onewireb.c$97$1$63 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 00
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 00
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 00
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 00
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8onewireb
+F:G$crc_crc8onewire$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewireb.crc_crc8onewire$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8onewireb.crc_crc8onewire$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8onewireb.crc_crc8onewire$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiremsbb
+
+;!FILE libmf/crc8onewiremsbb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8onewiremsbb
+O -mmcs51 --model-small
+S _crc_crc8onewire_msbtable Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S _crc_crc8onewire_msb Def000000
+S XG$crc_crc8onewire_msb$0$0 Def000069
+S A$crc8onewiremsbb$110 Def000004
+S A$crc8onewiremsbb$120 Def00000E
+S A$crc8onewiremsbb$111 Def000005
+S A$crc8onewiremsbb$121 Def000010
+S A$crc8onewiremsbb$112 Def000006
+S A$crc8onewiremsbb$140 Def000029
+S A$crc8onewiremsbb$131 Def00001F
+S A$crc8onewiremsbb$122 Def000011
+S A$crc8onewiremsbb$113 Def000007
+S A$crc8onewiremsbb$141 Def00002B
+S A$crc8onewiremsbb$132 Def000020
+S A$crc8onewiremsbb$123 Def000013
+S A$crc8onewiremsbb$114 Def000008
+S A$crc8onewiremsbb$160 Def000040
+S A$crc8onewiremsbb$151 Def000035
+S A$crc8onewiremsbb$115 Def000009
+S A$crc8onewiremsbb$170 Def00004E
+S A$crc8onewiremsbb$152 Def000037
+S A$crc8onewiremsbb$143 Def00002D
+S A$crc8onewiremsbb$134 Def000021
+S A$crc8onewiremsbb$125 Def000014
+S A$crc8onewiremsbb$116 Def00000A
+S A$crc8onewiremsbb$180 Def00005A
+S A$crc8onewiremsbb$171 Def000050
+S A$crc8onewiremsbb$162 Def000042
+S A$crc8onewiremsbb$144 Def00002E
+S A$crc8onewiremsbb$135 Def000022
+S A$crc8onewiremsbb$126 Def000017
+S A$crc8onewiremsbb$117 Def00000B
+S A$crc8onewiremsbb$108 Def000000
+S A$crc8onewiremsbb$181 Def00005D
+S A$crc8onewiremsbb$163 Def000043
+S A$crc8onewiremsbb$154 Def000039
+S A$crc8onewiremsbb$136 Def000025
+S A$crc8onewiremsbb$127 Def00001A
+S A$crc8onewiremsbb$118 Def00000C
+S A$crc8onewiremsbb$109 Def000002
+S A$crc8onewiremsbb$182 Def00005E
+S A$crc8onewiremsbb$173 Def000052
+S A$crc8onewiremsbb$164 Def000046
+S A$crc8onewiremsbb$155 Def00003B
+S A$crc8onewiremsbb$146 Def00002F
+S A$crc8onewiremsbb$137 Def000026
+S A$crc8onewiremsbb$128 Def00001C
+S A$crc8onewiremsbb$119 Def00000D
+S A$crc8onewiremsbb$174 Def000053
+S A$crc8onewiremsbb$165 Def000047
+S A$crc8onewiremsbb$147 Def000030
+S C$crc8onewiremsbb.c$10$0$0 Def000000
+S A$crc8onewiremsbb$184 Def00005F
+S A$crc8onewiremsbb$175 Def000054
+S A$crc8onewiremsbb$157 Def00003C
+S A$crc8onewiremsbb$148 Def000033
+S A$crc8onewiremsbb$139 Def000027
+S A$crc8onewiremsbb$185 Def000061
+S A$crc8onewiremsbb$176 Def000055
+S A$crc8onewiremsbb$167 Def000048
+S A$crc8onewiremsbb$158 Def00003D
+S A$crc8onewiremsbb$149 Def000034
+S G$crc_crc8onewire_msb$0$0 Def000000
+S A$crc8onewiremsbb$186 Def000063
+S A$crc8onewiremsbb$177 Def000057
+S A$crc8onewiremsbb$168 Def00004A
+S A$crc8onewiremsbb$159 Def00003E
+S A$crc8onewiremsbb$187 Def000065
+S A$crc8onewiremsbb$169 Def00004C
+S A$crc8onewiremsbb$188 Def000067
+S A$crc8onewiremsbb$179 Def000059
+S C$crc8onewiremsbb.c$96$1$63 Def000000
+S C$crc8onewiremsbb.c$97$1$63 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 00
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 00
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 00
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 00
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8onewiremsbb
+F:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccitttable
+
+XH3
+H 1A areas 3 global symbols
+M crc8ccitttable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S G$crc_crc8ccitt_table$0$0 Def000000
+S _crc_crc8ccitt_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 91 E3 72 07 96 E4 75 0E 9F ED 7C 09
+R 00 00 00 17
+T 00 00 0D 98 EA 7B 1C 8D FF 6E 1B 8A F8 69 12 83
+R 00 00 00 17
+T 00 00 1A F1 60 15 84 F6 67 38 A9 DB 4A 3F AE DC
+R 00 00 00 17
+T 00 00 27 4D 36 A7 D5 44 31 A0 D2 43 24 B5 C7 56
+R 00 00 00 17
+T 00 00 34 23 B2 C0 51 2A BB C9 58 2D BC CE 5F 70
+R 00 00 00 17
+T 00 00 41 E1 93 02 77 E6 94 05 7E EF 9D 0C 79 E8
+R 00 00 00 17
+T 00 00 4E 9A 0B 6C FD 8F 1E 6B FA 88 19 62 F3 81
+R 00 00 00 17
+T 00 00 5B 10 65 F4 86 17 48 D9 AB 3A 4F DE AC 3D
+R 00 00 00 17
+T 00 00 68 46 D7 A5 34 41 D0 A2 33 54 C5 B7 26 53
+R 00 00 00 17
+T 00 00 75 C2 B0 21 5A CB B9 28 5D CC BE 2F E0 71
+R 00 00 00 17
+T 00 00 82 03 92 E7 76 04 95 EE 7F 0D 9C E9 78 0A
+R 00 00 00 17
+T 00 00 8F 9B FC 6D 1F 8E FB 6A 18 89 F2 63 11 80
+R 00 00 00 17
+T 00 00 9C F5 64 16 87 D8 49 3B AA DF 4E 3C AD D6
+R 00 00 00 17
+T 00 00 A9 47 35 A4 D1 40 32 A3 C4 55 27 B6 C3 52
+R 00 00 00 17
+T 00 00 B6 20 B1 CA 5B 29 B8 CD 5C 2E BF 90 01 73
+R 00 00 00 17
+T 00 00 C3 E2 97 06 74 E5 9E 0F 7D EC 99 08 7A EB
+R 00 00 00 17
+T 00 00 D0 8C 1D 6F FE 8B 1A 68 F9 82 13 61 F0 85
+R 00 00 00 17
+T 00 00 DD 14 66 F7 A8 39 4B DA AF 3E 4C DD A6 37
+R 00 00 00 17
+T 00 00 EA 45 D4 A1 30 42 D3 B4 25 57 C6 B3 22 50
+R 00 00 00 17
+T 00 00 F7 C1 BA 2B 59 C8 BD 2C 5E CF
+R 00 00 00 17
+
+
+M:crc8ccitttable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiretable
+
+XH3
+H 1A areas 3 global symbols
+M crc8onewiretable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _crc_crc8onewire_table Def000000
+S G$crc_crc8onewire_table$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 5E BC E2 61 3F DD 83 C2 9C 7E 20 A3
+R 00 00 00 17
+T 00 00 0D FD 1F 41 9D C3 21 7F FC A2 40 1E 5F 01
+R 00 00 00 17
+T 00 00 1A E3 BD 3E 60 82 DC 23 7D 9F C1 42 1C FE
+R 00 00 00 17
+T 00 00 27 A0 E1 BF 5D 03 80 DE 3C 62 BE E0 02 5C
+R 00 00 00 17
+T 00 00 34 DF 81 63 3D 7C 22 C0 9E 1D 43 A1 FF 46
+R 00 00 00 17
+T 00 00 41 18 FA A4 27 79 9B C5 84 DA 38 66 E5 BB
+R 00 00 00 17
+T 00 00 4E 59 07 DB 85 67 39 BA E4 06 58 19 47 A5
+R 00 00 00 17
+T 00 00 5B FB 78 26 C4 9A 65 3B D9 87 04 5A B8 E6
+R 00 00 00 17
+T 00 00 68 A7 F9 1B 45 C6 98 7A 24 F8 A6 44 1A 99
+R 00 00 00 17
+T 00 00 75 C7 25 7B 3A 64 86 D8 5B 05 E7 B9 8C D2
+R 00 00 00 17
+T 00 00 82 30 6E ED B3 51 0F 4E 10 F2 AC 2F 71 93
+R 00 00 00 17
+T 00 00 8F CD 11 4F AD F3 70 2E CC 92 D3 8D 6F 31
+R 00 00 00 17
+T 00 00 9C B2 EC 0E 50 AF F1 13 4D CE 90 72 2C 6D
+R 00 00 00 17
+T 00 00 A9 33 D1 8F 0C 52 B0 EE 32 6C 8E D0 53 0D
+R 00 00 00 17
+T 00 00 B6 EF B1 F0 AE 4C 12 91 CF 2D 73 CA 94 76
+R 00 00 00 17
+T 00 00 C3 28 AB F5 17 49 08 56 B4 EA 69 37 D5 8B
+R 00 00 00 17
+T 00 00 D0 57 09 EB B5 36 68 8A D4 95 CB 29 77 F4
+R 00 00 00 17
+T 00 00 DD AA 48 16 E9 B7 55 0B 88 D6 34 6A 2B 75
+R 00 00 00 17
+T 00 00 EA 97 C9 4A 14 F6 A8 74 2A C8 96 15 4B A9
+R 00 00 00 17
+T 00 00 F7 F7 B6 E8 0A 54 D7 89 6B 35
+R 00 00 00 17
+
+
+M:crc8onewiretable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc8ccittmsbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S G$crc_crc8ccitt_msbtable$0$0 Def000000
+S _crc_crc8ccitt_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 07 0E 09 1C 1B 12 15 38 3F 36 31 24
+R 00 00 00 17
+T 00 00 0D 23 2A 2D 70 77 7E 79 6C 6B 62 65 48 4F
+R 00 00 00 17
+T 00 00 1A 46 41 54 53 5A 5D E0 E7 EE E9 FC FB F2
+R 00 00 00 17
+T 00 00 27 F5 D8 DF D6 D1 C4 C3 CA CD 90 97 9E 99
+R 00 00 00 17
+T 00 00 34 8C 8B 82 85 A8 AF A6 A1 B4 B3 BA BD C7
+R 00 00 00 17
+T 00 00 41 C0 C9 CE DB DC D5 D2 FF F8 F1 F6 E3 E4
+R 00 00 00 17
+T 00 00 4E ED EA B7 B0 B9 BE AB AC A5 A2 8F 88 81
+R 00 00 00 17
+T 00 00 5B 86 93 94 9D 9A 27 20 29 2E 3B 3C 35 32
+R 00 00 00 17
+T 00 00 68 1F 18 11 16 03 04 0D 0A 57 50 59 5E 4B
+R 00 00 00 17
+T 00 00 75 4C 45 42 6F 68 61 66 73 74 7D 7A 89 8E
+R 00 00 00 17
+T 00 00 82 87 80 95 92 9B 9C B1 B6 BF B8 AD AA A3
+R 00 00 00 17
+T 00 00 8F A4 F9 FE F7 F0 E5 E2 EB EC C1 C6 CF C8
+R 00 00 00 17
+T 00 00 9C DD DA D3 D4 69 6E 67 60 75 72 7B 7C 51
+R 00 00 00 17
+T 00 00 A9 56 5F 58 4D 4A 43 44 19 1E 17 10 05 02
+R 00 00 00 17
+T 00 00 B6 0B 0C 21 26 2F 28 3D 3A 33 34 4E 49 40
+R 00 00 00 17
+T 00 00 C3 47 52 55 5C 5B 76 71 78 7F 6A 6D 64 63
+R 00 00 00 17
+T 00 00 D0 3E 39 30 37 22 25 2C 2B 06 01 08 0F 1A
+R 00 00 00 17
+T 00 00 DD 1D 14 13 AE A9 A0 A7 B2 B5 BC BB 96 91
+R 00 00 00 17
+T 00 00 EA 98 9F 8A 8D 84 83 DE D9 D0 D7 C2 C5 CC
+R 00 00 00 17
+T 00 00 F7 CB E6 E1 E8 EF FA FD F4 F3
+R 00 00 00 17
+
+
+M:crc8ccittmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiremsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc8onewiremsbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _crc_crc8onewire_msbtable Def000000
+S G$crc_crc8onewire_msbtable$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 31 62 53 C4 F5 A6 97 B9 88 DB EA 7D
+R 00 00 00 17
+T 00 00 0D 4C 1F 2E 43 72 21 10 87 B6 E5 D4 FA CB
+R 00 00 00 17
+T 00 00 1A 98 A9 3E 0F 5C 6D 86 B7 E4 D5 42 73 20
+R 00 00 00 17
+T 00 00 27 11 3F 0E 5D 6C FB CA 99 A8 C5 F4 A7 96
+R 00 00 00 17
+T 00 00 34 01 30 63 52 7C 4D 1E 2F B8 89 DA EB 3D
+R 00 00 00 17
+T 00 00 41 0C 5F 6E F9 C8 9B AA 84 B5 E6 D7 40 71
+R 00 00 00 17
+T 00 00 4E 22 13 7E 4F 1C 2D BA 8B D8 E9 C7 F6 A5
+R 00 00 00 17
+T 00 00 5B 94 03 32 61 50 BB 8A D9 E8 7F 4E 1D 2C
+R 00 00 00 17
+T 00 00 68 02 33 60 51 C6 F7 A4 95 F8 C9 9A AB 3C
+R 00 00 00 17
+T 00 00 75 0D 5E 6F 41 70 23 12 85 B4 E7 D6 7A 4B
+R 00 00 00 17
+T 00 00 82 18 29 BE 8F DC ED C3 F2 A1 90 07 36 65
+R 00 00 00 17
+T 00 00 8F 54 39 08 5B 6A FD CC 9F AE 80 B1 E2 D3
+R 00 00 00 17
+T 00 00 9C 44 75 26 17 FC CD 9E AF 38 09 5A 6B 45
+R 00 00 00 17
+T 00 00 A9 74 27 16 81 B0 E3 D2 BF 8E DD EC 7B 4A
+R 00 00 00 17
+T 00 00 B6 19 28 06 37 64 55 C2 F3 A0 91 47 76 25
+R 00 00 00 17
+T 00 00 C3 14 83 B2 E1 D0 FE CF 9C AD 3A 0B 58 69
+R 00 00 00 17
+T 00 00 D0 04 35 66 57 C0 F1 A2 93 BD 8C DF EE 79
+R 00 00 00 17
+T 00 00 DD 48 1B 2A C1 F0 A3 92 05 34 67 56 78 49
+R 00 00 00 17
+T 00 00 EA 1A 2B BC 8D DE EF 82 B3 E0 D1 46 77 24
+R 00 00 00 17
+T 00 00 F7 15 3B 0A 59 68 FF CE 9D AC
+R 00 00 00 17
+
+
+M:crc8onewiremsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccitt
+
+;!FILE libmf/crcccitt.asm
+XH3
+H 1A areas 23 global symbols
+M crcccitt
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_ccitt_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crcccitt.c$9$0$0 Def000000
+S G$crc_ccitt_byte$0$0 Def000000
+S _crc_ccitt_byte Def000000
+S A$crcccitt$110 Def000005
+S A$crcccitt$120 Def000011
+S A$crcccitt$111 Def000006
+S A$crcccitt$130 Def00001F
+S A$crcccitt$121 Def000013
+S A$crcccitt$112 Def000008
+S XG$crc_ccitt_byte$0$0 Def000025
+S A$crcccitt$131 Def000020
+S A$crcccitt$122 Def000015
+S A$crcccitt$113 Def000009
+S A$crcccitt$132 Def000022
+S A$crcccitt$123 Def000016
+S A$crcccitt$114 Def00000A
+S A$crcccitt$133 Def000024
+S A$crcccitt$124 Def000018
+S A$crcccitt$115 Def00000B
+S A$crcccitt$125 Def000019
+S A$crcccitt$116 Def00000C
+S A$crcccitt$107 Def000000
+S A$crcccitt$126 Def00001A
+S A$crcccitt$117 Def00000D
+S A$crcccitt$108 Def000002
+S A$crcccitt$127 Def00001B
+S A$crcccitt$118 Def00000E
+S A$crcccitt$109 Def000004
+S C$crcccitt.c$41$1$63 Def000000
+S A$crcccitt$128 Def00001C
+S A$crcccitt$119 Def000010
+S C$crcccitt.c$42$1$63 Def000025
+S A$crcccitt$129 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crcccitt
+F:G$crc_ccitt_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccitt.crc_ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrcccitt.crc_ccitt_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittmsb
+
+;!FILE libmf/crcccittmsb.asm
+XH3
+H 1A areas 23 global symbols
+M crcccittmsb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_ccitt_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S _crc_ccitt_msb_byte Def000000
+S XG$crc_ccitt_msb_byte$0$0 Def000025
+S C$crcccittmsb.c$9$0$0 Def000000
+S A$crcccittmsb$110 Def000005
+S A$crcccittmsb$120 Def000011
+S A$crcccittmsb$111 Def000006
+S A$crcccittmsb$130 Def00001F
+S A$crcccittmsb$121 Def000013
+S A$crcccittmsb$112 Def000008
+S A$crcccittmsb$131 Def000020
+S A$crcccittmsb$122 Def000014
+S A$crcccittmsb$113 Def000009
+S A$crcccittmsb$132 Def000022
+S A$crcccittmsb$123 Def000016
+S A$crcccittmsb$114 Def00000A
+S A$crcccittmsb$133 Def000024
+S A$crcccittmsb$124 Def000017
+S A$crcccittmsb$115 Def00000B
+S A$crcccittmsb$125 Def000019
+S A$crcccittmsb$116 Def00000C
+S A$crcccittmsb$107 Def000000
+S A$crcccittmsb$126 Def00001B
+S A$crcccittmsb$117 Def00000D
+S A$crcccittmsb$108 Def000002
+S A$crcccittmsb$127 Def00001C
+S A$crcccittmsb$118 Def00000E
+S A$crcccittmsb$109 Def000004
+S C$crcccittmsb.c$41$1$63 Def000000
+S A$crcccittmsb$128 Def00001D
+S A$crcccittmsb$119 Def000010
+S C$crcccittmsb.c$42$1$63 Def000025
+S G$crc_ccitt_msb_byte$0$0 Def000000
+S A$crcccittmsb$129 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 01 F1 83 0D 00 01
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crcccittmsb
+F:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittmsb.crc_ccitt_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrcccittmsb.crc_ccitt_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansi
+
+;!FILE libmf/crc16ansi.asm
+XH3
+H 1A areas 23 global symbols
+M crc16ansi
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc16_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crc16ansi.c$9$0$0 Def000000
+S G$crc_crc16_byte$0$0 Def000000
+S A$crc16ansi$110 Def000005
+S A$crc16ansi$120 Def000011
+S A$crc16ansi$111 Def000006
+S A$crc16ansi$130 Def00001F
+S A$crc16ansi$121 Def000013
+S A$crc16ansi$112 Def000008
+S A$crc16ansi$131 Def000020
+S A$crc16ansi$122 Def000015
+S A$crc16ansi$113 Def000009
+S _crc_crc16_byte Def000000
+S A$crc16ansi$132 Def000022
+S A$crc16ansi$123 Def000016
+S A$crc16ansi$114 Def00000A
+S A$crc16ansi$133 Def000024
+S A$crc16ansi$124 Def000018
+S A$crc16ansi$115 Def00000B
+S A$crc16ansi$125 Def000019
+S A$crc16ansi$116 Def00000C
+S A$crc16ansi$107 Def000000
+S A$crc16ansi$126 Def00001A
+S A$crc16ansi$117 Def00000D
+S A$crc16ansi$108 Def000002
+S A$crc16ansi$127 Def00001B
+S A$crc16ansi$118 Def00000E
+S A$crc16ansi$109 Def000004
+S C$crc16ansi.c$41$1$63 Def000000
+S A$crc16ansi$128 Def00001C
+S A$crc16ansi$119 Def000010
+S C$crc16ansi.c$42$1$63 Def000025
+S A$crc16ansi$129 Def00001D
+S XG$crc_crc16_byte$0$0 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crc16ansi
+F:G$crc_crc16_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansi.crc_crc16_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16ansi.crc_crc16_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansimsb
+
+;!FILE libmf/crc16ansimsb.asm
+XH3
+H 1A areas 23 global symbols
+M crc16ansimsb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc16_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crc16ansimsb.c$9$0$0 Def000000
+S _crc_crc16_msb_byte Def000000
+S XG$crc_crc16_msb_byte$0$0 Def000025
+S A$crc16ansimsb$110 Def000005
+S A$crc16ansimsb$120 Def000011
+S A$crc16ansimsb$111 Def000006
+S A$crc16ansimsb$130 Def00001F
+S A$crc16ansimsb$121 Def000013
+S A$crc16ansimsb$112 Def000008
+S A$crc16ansimsb$131 Def000020
+S A$crc16ansimsb$122 Def000014
+S A$crc16ansimsb$113 Def000009
+S A$crc16ansimsb$132 Def000022
+S A$crc16ansimsb$123 Def000016
+S A$crc16ansimsb$114 Def00000A
+S A$crc16ansimsb$133 Def000024
+S A$crc16ansimsb$124 Def000017
+S A$crc16ansimsb$115 Def00000B
+S A$crc16ansimsb$125 Def000019
+S A$crc16ansimsb$116 Def00000C
+S A$crc16ansimsb$107 Def000000
+S A$crc16ansimsb$126 Def00001B
+S A$crc16ansimsb$117 Def00000D
+S A$crc16ansimsb$108 Def000002
+S A$crc16ansimsb$127 Def00001C
+S A$crc16ansimsb$118 Def00000E
+S A$crc16ansimsb$109 Def000004
+S C$crc16ansimsb.c$41$1$63 Def000000
+S A$crc16ansimsb$128 Def00001D
+S A$crc16ansimsb$119 Def000010
+S C$crc16ansimsb.c$42$1$63 Def000025
+S A$crc16ansimsb$129 Def00001E
+S G$crc_crc16_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 01 F1 83 0D 00 01
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crc16ansimsb
+F:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansimsb.crc_crc16_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16ansimsb.crc_crc16_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnp
+
+;!FILE libmf/crc16dnp.asm
+XH3
+H 1A areas 23 global symbols
+M crc16dnp
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc16dnp_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$crc16dnp$132 Def000022
+S A$crc16dnp$123 Def000016
+S A$crc16dnp$114 Def00000A
+S A$crc16dnp$133 Def000024
+S A$crc16dnp$124 Def000018
+S A$crc16dnp$115 Def00000B
+S A$crc16dnp$125 Def000019
+S A$crc16dnp$116 Def00000C
+S A$crc16dnp$107 Def000000
+S A$crc16dnp$126 Def00001A
+S A$crc16dnp$117 Def00000D
+S A$crc16dnp$108 Def000002
+S A$crc16dnp$127 Def00001B
+S A$crc16dnp$118 Def00000E
+S A$crc16dnp$109 Def000004
+S C$crc16dnp.c$41$1$63 Def000000
+S A$crc16dnp$128 Def00001C
+S A$crc16dnp$119 Def000010
+S C$crc16dnp.c$42$1$63 Def000025
+S A$crc16dnp$129 Def00001D
+S C$crc16dnp.c$9$0$0 Def000000
+S G$crc_crc16dnp_byte$0$0 Def000000
+S _crc_crc16dnp_byte Def000000
+S XG$crc_crc16dnp_byte$0$0 Def000025
+S A$crc16dnp$110 Def000005
+S A$crc16dnp$120 Def000011
+S A$crc16dnp$111 Def000006
+S A$crc16dnp$130 Def00001F
+S A$crc16dnp$121 Def000013
+S A$crc16dnp$112 Def000008
+S A$crc16dnp$131 Def000020
+S A$crc16dnp$122 Def000015
+S A$crc16dnp$113 Def000009
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crc16dnp
+F:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnp.crc_crc16dnp_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16dnp.crc_crc16dnp_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpmsb
+
+;!FILE libmf/crc16dnpmsb.asm
+XH3
+H 1A areas 23 global symbols
+M crc16dnpmsb
+O -mmcs51 --model-small
+S _crc_crc16dnp_msbtable Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$crc16dnpmsb$130 Def00001F
+S A$crc16dnpmsb$121 Def000013
+S A$crc16dnpmsb$112 Def000008
+S A$crc16dnpmsb$131 Def000020
+S A$crc16dnpmsb$122 Def000014
+S A$crc16dnpmsb$113 Def000009
+S A$crc16dnpmsb$132 Def000022
+S A$crc16dnpmsb$123 Def000016
+S A$crc16dnpmsb$114 Def00000A
+S A$crc16dnpmsb$133 Def000024
+S A$crc16dnpmsb$124 Def000017
+S A$crc16dnpmsb$115 Def00000B
+S A$crc16dnpmsb$125 Def000019
+S A$crc16dnpmsb$116 Def00000C
+S A$crc16dnpmsb$107 Def000000
+S A$crc16dnpmsb$126 Def00001B
+S A$crc16dnpmsb$117 Def00000D
+S A$crc16dnpmsb$108 Def000002
+S A$crc16dnpmsb$127 Def00001C
+S A$crc16dnpmsb$118 Def00000E
+S A$crc16dnpmsb$109 Def000004
+S C$crc16dnpmsb.c$41$1$63 Def000000
+S A$crc16dnpmsb$128 Def00001D
+S A$crc16dnpmsb$119 Def000010
+S C$crc16dnpmsb.c$42$1$63 Def000025
+S A$crc16dnpmsb$129 Def00001E
+S _crc_crc16dnp_msb_byte Def000000
+S XG$crc_crc16dnp_msb_byte$0$0 Def000025
+S C$crc16dnpmsb.c$9$0$0 Def000000
+S A$crc16dnpmsb$110 Def000005
+S A$crc16dnpmsb$120 Def000011
+S A$crc16dnpmsb$111 Def000006
+S G$crc_crc16dnp_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 00 F1 83 0D 00 00
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crc16dnpmsb
+F:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpmsb.crc_crc16dnp_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16dnpmsb.crc_crc16dnp_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansi
+
+;!FILE libmf/crc32ansi.asm
+XH3
+H 1A areas 2C global symbols
+M crc32ansi
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc32_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$crc32ansi.c$9$0$0 Def000000
+S G$crc_crc32_byte$0$0 Def000000
+S A$crc32ansi$110 Def000005
+S A$crc32ansi$120 Def000013
+S A$crc32ansi$111 Def000006
+S A$crc32ansi$130 Def000021
+S A$crc32ansi$121 Def000015
+S A$crc32ansi$112 Def000007
+S A$crc32ansi$140 Def000030
+S A$crc32ansi$131 Def000022
+S A$crc32ansi$122 Def000017
+S A$crc32ansi$113 Def000009
+S _crc_crc32_byte Def000000
+S A$crc32ansi$141 Def000032
+S A$crc32ansi$132 Def000023
+S A$crc32ansi$123 Def000019
+S A$crc32ansi$114 Def00000A
+S A$crc32ansi$142 Def000033
+S A$crc32ansi$133 Def000025
+S A$crc32ansi$124 Def00001A
+S A$crc32ansi$115 Def00000B
+S A$crc32ansi$134 Def000026
+S A$crc32ansi$125 Def00001B
+S A$crc32ansi$116 Def00000C
+S A$crc32ansi$107 Def000000
+S A$crc32ansi$135 Def000027
+S A$crc32ansi$126 Def00001C
+S A$crc32ansi$117 Def00000E
+S A$crc32ansi$108 Def000001
+S A$crc32ansi$136 Def000029
+S A$crc32ansi$127 Def00001D
+S A$crc32ansi$118 Def000010
+S A$crc32ansi$109 Def000003
+S C$crc32ansi.c$50$1$63 Def000000
+S A$crc32ansi$137 Def00002A
+S A$crc32ansi$128 Def00001E
+S A$crc32ansi$119 Def000012
+S C$crc32ansi.c$51$1$63 Def000034
+S A$crc32ansi$138 Def00002C
+S A$crc32ansi$129 Def000020
+S A$crc32ansi$139 Def00002E
+S XG$crc_crc32_byte$0$0 Def000034
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FC E5 81 24 FE F8 E6 65 82 23 23 FB 54
+R 00 00 00 16
+T 00 00 0D FC 24 00 00 00 F5 82 EB 54 03 34
+R 00 00 00 16 F1 03 05 00 01
+T 00 00 16 00 00 00 C5 83 FA E4 93 6A FA 74 02 93
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 21 6C FB 74 03 93 FC 74 01 93 65 F0 F5 83
+R 00 00 00 16
+T 00 00 2E 8A 82 8B F0 EC 22
+R 00 00 00 16
+
+
+M:crc32ansi
+F:G$crc_crc32_byte$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansi.crc_crc32_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc32ansi.crc_crc32_byte$crc$1$62({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansimsb
+
+;!FILE libmf/crc32ansimsb.asm
+XH3
+H 1A areas 2D global symbols
+M crc32ansimsb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_crc32_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$crc32ansimsb.c$9$0$0 Def000000
+S _crc_crc32_msb_byte Def000000
+S XG$crc_crc32_msb_byte$0$0 Def000034
+S A$crc32ansimsb$110 Def000005
+S A$crc32ansimsb$120 Def000012
+S A$crc32ansimsb$111 Def000006
+S A$crc32ansimsb$130 Def000021
+S A$crc32ansimsb$121 Def000013
+S A$crc32ansimsb$112 Def000007
+S A$crc32ansimsb$140 Def00002E
+S A$crc32ansimsb$131 Def000022
+S A$crc32ansimsb$122 Def000015
+S A$crc32ansimsb$113 Def000008
+S A$crc32ansimsb$141 Def000030
+S A$crc32ansimsb$132 Def000023
+S A$crc32ansimsb$123 Def000017
+S A$crc32ansimsb$114 Def000009
+S A$crc32ansimsb$142 Def000032
+S A$crc32ansimsb$133 Def000024
+S A$crc32ansimsb$124 Def000019
+S A$crc32ansimsb$115 Def00000A
+S A$crc32ansimsb$143 Def000033
+S A$crc32ansimsb$134 Def000026
+S A$crc32ansimsb$125 Def00001A
+S A$crc32ansimsb$116 Def00000B
+S A$crc32ansimsb$107 Def000000
+S A$crc32ansimsb$135 Def000027
+S A$crc32ansimsb$126 Def00001C
+S A$crc32ansimsb$117 Def00000D
+S A$crc32ansimsb$108 Def000001
+S A$crc32ansimsb$136 Def000029
+S A$crc32ansimsb$127 Def00001D
+S A$crc32ansimsb$118 Def00000F
+S A$crc32ansimsb$109 Def000003
+S A$crc32ansimsb$137 Def00002A
+S A$crc32ansimsb$128 Def00001E
+S A$crc32ansimsb$119 Def000011
+S C$crc32ansimsb.c$51$1$63 Def000000
+S A$crc32ansimsb$138 Def00002B
+S A$crc32ansimsb$129 Def00001F
+S C$crc32ansimsb.c$52$1$63 Def000034
+S A$crc32ansimsb$139 Def00002C
+S G$crc_crc32_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FA E5 81 24 FE F8 E6 6A 23 23 FB 54 FC
+R 00 00 00 16
+T 00 00 0D 24 00 00 00 C5 82 FA EB 54 03 34
+R 00 00 00 16 F1 03 04 00 01
+T 00 00 16 00 00 00 C5 83 FB 74 01 93 6A FA 74 02
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 21 93 6B FB 74 03 93 65 F0 FC E4 93 F5 82
+R 00 00 00 16
+T 00 00 2E 8A 83 8B F0 EC 22
+R 00 00 00 16
+
+
+M:crc32ansimsb
+F:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansimsb.crc_crc32_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc32ansimsb.crc_crc32_msb_byte$crc$1$62({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittb
+
+;!FILE libmf/crcccittb.asm
+XH3
+H 1A areas 81 global symbols
+M crcccittb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _crc_ccitt_table Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S G$crc_ccitt$0$0 Def000000
+S C$crcccittb.c$228$1$63 Def000000
+S A$crcccittb$200 Def00007C
+S A$crcccittb$110 Def000004
+S C$crcccittb.c$229$1$63 Def0000B6
+S A$crcccittb$210 Def000089
+S A$crcccittb$201 Def00007D
+S A$crcccittb$120 Def00000E
+S A$crcccittb$111 Def000005
+S _crc_ccitt Def000000
+S A$crcccittb$220 Def000095
+S A$crcccittb$211 Def00008B
+S A$crcccittb$202 Def00007E
+S A$crcccittb$130 Def00001D
+S A$crcccittb$121 Def00000F
+S A$crcccittb$112 Def000006
+S A$crcccittb$230 Def0000A6
+S A$crcccittb$221 Def000096
+S A$crcccittb$203 Def00007F
+S A$crcccittb$140 Def000028
+S A$crcccittb$131 Def00001F
+S A$crcccittb$122 Def000010
+S A$crcccittb$113 Def000007
+S A$crcccittb$240 Def0000B4
+S A$crcccittb$231 Def0000A7
+S A$crcccittb$222 Def000098
+S A$crcccittb$213 Def00008D
+S A$crcccittb$204 Def000081
+S A$crcccittb$150 Def000038
+S A$crcccittb$141 Def00002A
+S A$crcccittb$123 Def000011
+S A$crcccittb$114 Def000008
+S A$crcccittb$232 Def0000A8
+S A$crcccittb$223 Def00009A
+S A$crcccittb$214 Def00008E
+S A$crcccittb$205 Def000082
+S A$crcccittb$151 Def00003A
+S A$crcccittb$142 Def00002C
+S A$crcccittb$124 Def000013
+S A$crcccittb$115 Def000009
+S A$crcccittb$233 Def0000AA
+S A$crcccittb$224 Def00009C
+S A$crcccittb$215 Def00008F
+S A$crcccittb$170 Def000054
+S A$crcccittb$161 Def000044
+S A$crcccittb$152 Def00003B
+S A$crcccittb$143 Def00002E
+S A$crcccittb$134 Def000022
+S A$crcccittb$125 Def000014
+S A$crcccittb$116 Def00000A
+S A$crcccittb$234 Def0000AB
+S A$crcccittb$225 Def00009E
+S A$crcccittb$216 Def000090
+S A$crcccittb$207 Def000083
+S A$crcccittb$171 Def000055
+S A$crcccittb$162 Def000045
+S A$crcccittb$144 Def000030
+S A$crcccittb$135 Def000023
+S A$crcccittb$126 Def000016
+S A$crcccittb$117 Def00000B
+S A$crcccittb$108 Def000000
+S A$crcccittb$226 Def0000A0
+S A$crcccittb$217 Def000092
+S A$crcccittb$208 Def000085
+S A$crcccittb$190 Def00006B
+S A$crcccittb$181 Def000060
+S A$crcccittb$172 Def000056
+S A$crcccittb$163 Def000046
+S A$crcccittb$154 Def00003C
+S A$crcccittb$145 Def000032
+S A$crcccittb$118 Def00000C
+S A$crcccittb$109 Def000002
+S A$crcccittb$236 Def0000AC
+S A$crcccittb$227 Def0000A2
+S A$crcccittb$209 Def000087
+S A$crcccittb$191 Def00006C
+S A$crcccittb$182 Def000062
+S A$crcccittb$173 Def000057
+S A$crcccittb$164 Def000048
+S A$crcccittb$155 Def00003E
+S A$crcccittb$146 Def000034
+S A$crcccittb$137 Def000024
+S A$crcccittb$128 Def000017
+S A$crcccittb$119 Def00000D
+S A$crcccittb$237 Def0000AE
+S A$crcccittb$228 Def0000A4
+S A$crcccittb$219 Def000094
+S A$crcccittb$192 Def00006D
+S A$crcccittb$183 Def000064
+S A$crcccittb$174 Def000058
+S A$crcccittb$165 Def00004A
+S A$crcccittb$156 Def000040
+S A$crcccittb$147 Def000035
+S A$crcccittb$138 Def000025
+S A$crcccittb$129 Def00001A
+S C$crcccittb.c$10$0$0 Def000000
+S A$crcccittb$238 Def0000B0
+S A$crcccittb$229 Def0000A5
+S A$crcccittb$193 Def00006F
+S A$crcccittb$175 Def00005A
+S A$crcccittb$166 Def00004C
+S A$crcccittb$148 Def000036
+S A$crcccittb$139 Def000026
+S A$crcccittb$239 Def0000B2
+S A$crcccittb$194 Def000071
+S A$crcccittb$185 Def000065
+S A$crcccittb$176 Def00005B
+S A$crcccittb$167 Def00004E
+S A$crcccittb$158 Def000042
+S A$crcccittb$149 Def000037
+S A$crcccittb$195 Def000073
+S A$crcccittb$186 Def000066
+S A$crcccittb$168 Def000050
+S A$crcccittb$159 Def000043
+S XG$crc_ccitt$0$0 Def0000B6
+S A$crcccittb$196 Def000075
+S A$crcccittb$187 Def000067
+S A$crcccittb$178 Def00005C
+S A$crcccittb$169 Def000052
+S A$crcccittb$197 Def000077
+S A$crcccittb$188 Def000069
+S A$crcccittb$179 Def00005E
+S A$crcccittb$198 Def000079
+S A$crcccittb$199 Def00007B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 01
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 01
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 01
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 01
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 01 F1 83 0B 00 01
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 01 F1 83 0C 00 01
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crcccittb
+F:G$crc_ccitt$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittb.crc_ccitt$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrcccittb.crc_ccitt$crc$1$62({2}SI:U),B,1,-6
+S:Lcrcccittb.crc_ccitt$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittmsbb
+
+;!FILE libmf/crcccittmsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crcccittmsbb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _crc_ccitt_msbtable Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S C$crcccittmsbb.c$228$1$63 Def000000
+S A$crcccittmsbb$200 Def00007D
+S A$crcccittmsbb$110 Def000004
+S C$crcccittmsbb.c$229$1$63 Def0000B6
+S A$crcccittmsbb$210 Def000089
+S A$crcccittmsbb$201 Def00007E
+S A$crcccittmsbb$120 Def00000E
+S A$crcccittmsbb$111 Def000005
+S A$crcccittmsbb$220 Def000095
+S A$crcccittmsbb$211 Def00008B
+S A$crcccittmsbb$202 Def00007F
+S A$crcccittmsbb$130 Def00001D
+S A$crcccittmsbb$121 Def00000F
+S A$crcccittmsbb$112 Def000006
+S A$crcccittmsbb$230 Def0000A7
+S A$crcccittmsbb$221 Def000096
+S A$crcccittmsbb$203 Def000080
+S A$crcccittmsbb$140 Def000028
+S A$crcccittmsbb$131 Def00001F
+S A$crcccittmsbb$122 Def000010
+S A$crcccittmsbb$113 Def000007
+S A$crcccittmsbb$240 Def0000B4
+S A$crcccittmsbb$231 Def0000A8
+S A$crcccittmsbb$222 Def000098
+S A$crcccittmsbb$213 Def00008D
+S A$crcccittmsbb$204 Def000081
+S A$crcccittmsbb$150 Def000039
+S A$crcccittmsbb$141 Def00002A
+S A$crcccittmsbb$123 Def000011
+S A$crcccittmsbb$114 Def000008
+S A$crcccittmsbb$232 Def0000A9
+S A$crcccittmsbb$223 Def00009A
+S A$crcccittmsbb$214 Def00008E
+S A$crcccittmsbb$205 Def000082
+S A$crcccittmsbb$151 Def00003A
+S A$crcccittmsbb$142 Def00002C
+S A$crcccittmsbb$124 Def000013
+S A$crcccittmsbb$115 Def000009
+S A$crcccittmsbb$233 Def0000AA
+S A$crcccittmsbb$224 Def00009C
+S A$crcccittmsbb$215 Def00008F
+S A$crcccittmsbb$170 Def000054
+S A$crcccittmsbb$161 Def000044
+S A$crcccittmsbb$152 Def00003B
+S A$crcccittmsbb$143 Def00002E
+S A$crcccittmsbb$134 Def000022
+S A$crcccittmsbb$125 Def000014
+S A$crcccittmsbb$116 Def00000A
+S A$crcccittmsbb$234 Def0000AB
+S A$crcccittmsbb$225 Def00009E
+S A$crcccittmsbb$216 Def000090
+S A$crcccittmsbb$207 Def000083
+S A$crcccittmsbb$171 Def000056
+S A$crcccittmsbb$162 Def000045
+S A$crcccittmsbb$144 Def000030
+S A$crcccittmsbb$135 Def000023
+S A$crcccittmsbb$126 Def000016
+S A$crcccittmsbb$117 Def00000B
+S A$crcccittmsbb$108 Def000000
+S A$crcccittmsbb$226 Def0000A0
+S A$crcccittmsbb$217 Def000092
+S A$crcccittmsbb$208 Def000085
+S A$crcccittmsbb$190 Def00006B
+S A$crcccittmsbb$181 Def000060
+S A$crcccittmsbb$172 Def000057
+S A$crcccittmsbb$163 Def000046
+S A$crcccittmsbb$154 Def00003C
+S A$crcccittmsbb$145 Def000032
+S A$crcccittmsbb$118 Def00000C
+S A$crcccittmsbb$109 Def000002
+S A$crcccittmsbb$236 Def0000AC
+S A$crcccittmsbb$227 Def0000A2
+S A$crcccittmsbb$209 Def000087
+S A$crcccittmsbb$191 Def00006C
+S A$crcccittmsbb$182 Def000062
+S A$crcccittmsbb$173 Def000058
+S A$crcccittmsbb$164 Def000048
+S A$crcccittmsbb$155 Def00003E
+S A$crcccittmsbb$146 Def000034
+S A$crcccittmsbb$137 Def000024
+S A$crcccittmsbb$128 Def000017
+S A$crcccittmsbb$119 Def00000D
+S A$crcccittmsbb$237 Def0000AE
+S A$crcccittmsbb$228 Def0000A4
+S A$crcccittmsbb$219 Def000094
+S A$crcccittmsbb$192 Def00006D
+S A$crcccittmsbb$183 Def000064
+S A$crcccittmsbb$174 Def000059
+S A$crcccittmsbb$165 Def00004A
+S A$crcccittmsbb$156 Def000040
+S A$crcccittmsbb$147 Def000036
+S A$crcccittmsbb$138 Def000025
+S A$crcccittmsbb$129 Def00001A
+S C$crcccittmsbb.c$10$0$0 Def000000
+S A$crcccittmsbb$238 Def0000B0
+S A$crcccittmsbb$229 Def0000A6
+S A$crcccittmsbb$193 Def00006F
+S A$crcccittmsbb$175 Def00005A
+S A$crcccittmsbb$166 Def00004C
+S A$crcccittmsbb$148 Def000037
+S A$crcccittmsbb$139 Def000026
+S A$crcccittmsbb$239 Def0000B2
+S A$crcccittmsbb$194 Def000071
+S A$crcccittmsbb$185 Def000065
+S A$crcccittmsbb$176 Def00005B
+S A$crcccittmsbb$167 Def00004E
+S A$crcccittmsbb$158 Def000042
+S A$crcccittmsbb$149 Def000038
+S A$crcccittmsbb$195 Def000073
+S A$crcccittmsbb$186 Def000066
+S A$crcccittmsbb$168 Def000050
+S A$crcccittmsbb$159 Def000043
+S A$crcccittmsbb$196 Def000075
+S A$crcccittmsbb$187 Def000067
+S A$crcccittmsbb$178 Def00005C
+S A$crcccittmsbb$169 Def000052
+S A$crcccittmsbb$197 Def000077
+S A$crcccittmsbb$188 Def000069
+S A$crcccittmsbb$179 Def00005E
+S A$crcccittmsbb$198 Def000079
+S A$crcccittmsbb$199 Def00007B
+S G$crc_ccitt_msb$0$0 Def000000
+S _crc_ccitt_msb Def000000
+S XG$crc_ccitt_msb$0$0 Def0000B6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 02
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 02
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 02
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 02
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 02 F1 83 0B 00 02
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 02 F1 83 0C 00 02
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crcccittmsbb
+F:G$crc_ccitt_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittmsbb.crc_ccitt_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrcccittmsbb.crc_ccitt_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrcccittmsbb.crc_ccitt_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansib
+
+;!FILE libmf/crc16ansib.asm
+XH3
+H 1A areas 81 global symbols
+M crc16ansib
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S C$crc16ansib.c$228$1$63 Def000000
+S A$crc16ansib$200 Def00007C
+S A$crc16ansib$110 Def000004
+S C$crc16ansib.c$229$1$63 Def0000B6
+S A$crc16ansib$210 Def000089
+S A$crc16ansib$201 Def00007D
+S A$crc16ansib$120 Def00000E
+S A$crc16ansib$111 Def000005
+S A$crc16ansib$220 Def000095
+S A$crc16ansib$211 Def00008B
+S A$crc16ansib$202 Def00007E
+S A$crc16ansib$130 Def00001D
+S A$crc16ansib$121 Def00000F
+S A$crc16ansib$112 Def000006
+S G$crc_crc16$0$0 Def000000
+S A$crc16ansib$230 Def0000A6
+S A$crc16ansib$221 Def000096
+S A$crc16ansib$203 Def00007F
+S A$crc16ansib$140 Def000028
+S A$crc16ansib$131 Def00001F
+S A$crc16ansib$122 Def000010
+S A$crc16ansib$113 Def000007
+S A$crc16ansib$240 Def0000B4
+S A$crc16ansib$231 Def0000A7
+S A$crc16ansib$222 Def000098
+S A$crc16ansib$213 Def00008D
+S A$crc16ansib$204 Def000081
+S A$crc16ansib$150 Def000038
+S A$crc16ansib$141 Def00002A
+S A$crc16ansib$123 Def000011
+S A$crc16ansib$114 Def000008
+S A$crc16ansib$232 Def0000A8
+S A$crc16ansib$223 Def00009A
+S A$crc16ansib$214 Def00008E
+S A$crc16ansib$205 Def000082
+S A$crc16ansib$151 Def00003A
+S A$crc16ansib$142 Def00002C
+S A$crc16ansib$124 Def000013
+S A$crc16ansib$115 Def000009
+S A$crc16ansib$233 Def0000AA
+S A$crc16ansib$224 Def00009C
+S A$crc16ansib$215 Def00008F
+S A$crc16ansib$170 Def000054
+S A$crc16ansib$161 Def000044
+S A$crc16ansib$152 Def00003B
+S A$crc16ansib$143 Def00002E
+S A$crc16ansib$134 Def000022
+S A$crc16ansib$125 Def000014
+S A$crc16ansib$116 Def00000A
+S A$crc16ansib$234 Def0000AB
+S A$crc16ansib$225 Def00009E
+S A$crc16ansib$216 Def000090
+S A$crc16ansib$207 Def000083
+S A$crc16ansib$171 Def000055
+S A$crc16ansib$162 Def000045
+S A$crc16ansib$144 Def000030
+S A$crc16ansib$135 Def000023
+S A$crc16ansib$126 Def000016
+S A$crc16ansib$117 Def00000B
+S A$crc16ansib$108 Def000000
+S A$crc16ansib$226 Def0000A0
+S A$crc16ansib$217 Def000092
+S A$crc16ansib$208 Def000085
+S A$crc16ansib$190 Def00006B
+S A$crc16ansib$181 Def000060
+S A$crc16ansib$172 Def000056
+S A$crc16ansib$163 Def000046
+S A$crc16ansib$154 Def00003C
+S A$crc16ansib$145 Def000032
+S A$crc16ansib$118 Def00000C
+S A$crc16ansib$109 Def000002
+S A$crc16ansib$236 Def0000AC
+S A$crc16ansib$227 Def0000A2
+S A$crc16ansib$209 Def000087
+S A$crc16ansib$191 Def00006C
+S A$crc16ansib$182 Def000062
+S A$crc16ansib$173 Def000057
+S A$crc16ansib$164 Def000048
+S A$crc16ansib$155 Def00003E
+S A$crc16ansib$146 Def000034
+S A$crc16ansib$137 Def000024
+S A$crc16ansib$128 Def000017
+S A$crc16ansib$119 Def00000D
+S A$crc16ansib$237 Def0000AE
+S A$crc16ansib$228 Def0000A4
+S A$crc16ansib$219 Def000094
+S A$crc16ansib$192 Def00006D
+S A$crc16ansib$183 Def000064
+S A$crc16ansib$174 Def000058
+S A$crc16ansib$165 Def00004A
+S A$crc16ansib$156 Def000040
+S A$crc16ansib$147 Def000035
+S A$crc16ansib$138 Def000025
+S A$crc16ansib$129 Def00001A
+S C$crc16ansib.c$10$0$0 Def000000
+S A$crc16ansib$238 Def0000B0
+S A$crc16ansib$229 Def0000A5
+S A$crc16ansib$193 Def00006F
+S A$crc16ansib$175 Def00005A
+S A$crc16ansib$166 Def00004C
+S A$crc16ansib$148 Def000036
+S A$crc16ansib$139 Def000026
+S A$crc16ansib$239 Def0000B2
+S A$crc16ansib$194 Def000071
+S A$crc16ansib$185 Def000065
+S A$crc16ansib$176 Def00005B
+S A$crc16ansib$167 Def00004E
+S A$crc16ansib$158 Def000042
+S A$crc16ansib$149 Def000037
+S A$crc16ansib$195 Def000073
+S A$crc16ansib$186 Def000066
+S A$crc16ansib$168 Def000050
+S A$crc16ansib$159 Def000043
+S A$crc16ansib$196 Def000075
+S A$crc16ansib$187 Def000067
+S A$crc16ansib$178 Def00005C
+S A$crc16ansib$169 Def000052
+S _crc_crc16 Def000000
+S A$crc16ansib$197 Def000077
+S A$crc16ansib$188 Def000069
+S A$crc16ansib$179 Def00005E
+S A$crc16ansib$198 Def000079
+S A$crc16ansib$199 Def00007B
+S XG$crc_crc16$0$0 Def0000B6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16ansib
+F:G$crc_crc16$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansib.crc_crc16$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16ansib.crc_crc16$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16ansib.crc_crc16$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansimsbb
+
+;!FILE libmf/crc16ansimsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16ansimsbb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S XG$crc_crc16_msb$0$0 Def0000B6
+S C$crc16ansimsbb.c$228$1$63 Def000000
+S A$crc16ansimsbb$200 Def00007D
+S A$crc16ansimsbb$110 Def000004
+S C$crc16ansimsbb.c$229$1$63 Def0000B6
+S A$crc16ansimsbb$210 Def000089
+S A$crc16ansimsbb$201 Def00007E
+S A$crc16ansimsbb$120 Def00000E
+S A$crc16ansimsbb$111 Def000005
+S A$crc16ansimsbb$220 Def000095
+S A$crc16ansimsbb$211 Def00008B
+S A$crc16ansimsbb$202 Def00007F
+S A$crc16ansimsbb$130 Def00001D
+S A$crc16ansimsbb$121 Def00000F
+S A$crc16ansimsbb$112 Def000006
+S A$crc16ansimsbb$230 Def0000A7
+S A$crc16ansimsbb$221 Def000096
+S A$crc16ansimsbb$203 Def000080
+S A$crc16ansimsbb$140 Def000028
+S A$crc16ansimsbb$131 Def00001F
+S A$crc16ansimsbb$122 Def000010
+S A$crc16ansimsbb$113 Def000007
+S A$crc16ansimsbb$240 Def0000B4
+S A$crc16ansimsbb$231 Def0000A8
+S A$crc16ansimsbb$222 Def000098
+S A$crc16ansimsbb$213 Def00008D
+S A$crc16ansimsbb$204 Def000081
+S A$crc16ansimsbb$150 Def000039
+S A$crc16ansimsbb$141 Def00002A
+S A$crc16ansimsbb$123 Def000011
+S A$crc16ansimsbb$114 Def000008
+S A$crc16ansimsbb$232 Def0000A9
+S A$crc16ansimsbb$223 Def00009A
+S A$crc16ansimsbb$214 Def00008E
+S A$crc16ansimsbb$205 Def000082
+S A$crc16ansimsbb$151 Def00003A
+S A$crc16ansimsbb$142 Def00002C
+S A$crc16ansimsbb$124 Def000013
+S A$crc16ansimsbb$115 Def000009
+S A$crc16ansimsbb$233 Def0000AA
+S A$crc16ansimsbb$224 Def00009C
+S A$crc16ansimsbb$215 Def00008F
+S A$crc16ansimsbb$170 Def000054
+S A$crc16ansimsbb$161 Def000044
+S A$crc16ansimsbb$152 Def00003B
+S A$crc16ansimsbb$143 Def00002E
+S A$crc16ansimsbb$134 Def000022
+S A$crc16ansimsbb$125 Def000014
+S A$crc16ansimsbb$116 Def00000A
+S A$crc16ansimsbb$234 Def0000AB
+S A$crc16ansimsbb$225 Def00009E
+S A$crc16ansimsbb$216 Def000090
+S A$crc16ansimsbb$207 Def000083
+S A$crc16ansimsbb$171 Def000056
+S A$crc16ansimsbb$162 Def000045
+S A$crc16ansimsbb$144 Def000030
+S A$crc16ansimsbb$135 Def000023
+S A$crc16ansimsbb$126 Def000016
+S A$crc16ansimsbb$117 Def00000B
+S A$crc16ansimsbb$108 Def000000
+S A$crc16ansimsbb$226 Def0000A0
+S A$crc16ansimsbb$217 Def000092
+S A$crc16ansimsbb$208 Def000085
+S A$crc16ansimsbb$190 Def00006B
+S A$crc16ansimsbb$181 Def000060
+S A$crc16ansimsbb$172 Def000057
+S A$crc16ansimsbb$163 Def000046
+S A$crc16ansimsbb$154 Def00003C
+S A$crc16ansimsbb$145 Def000032
+S A$crc16ansimsbb$118 Def00000C
+S A$crc16ansimsbb$109 Def000002
+S A$crc16ansimsbb$236 Def0000AC
+S A$crc16ansimsbb$227 Def0000A2
+S A$crc16ansimsbb$209 Def000087
+S A$crc16ansimsbb$191 Def00006C
+S A$crc16ansimsbb$182 Def000062
+S A$crc16ansimsbb$173 Def000058
+S A$crc16ansimsbb$164 Def000048
+S A$crc16ansimsbb$155 Def00003E
+S A$crc16ansimsbb$146 Def000034
+S A$crc16ansimsbb$137 Def000024
+S A$crc16ansimsbb$128 Def000017
+S A$crc16ansimsbb$119 Def00000D
+S A$crc16ansimsbb$237 Def0000AE
+S A$crc16ansimsbb$228 Def0000A4
+S A$crc16ansimsbb$219 Def000094
+S A$crc16ansimsbb$192 Def00006D
+S A$crc16ansimsbb$183 Def000064
+S A$crc16ansimsbb$174 Def000059
+S A$crc16ansimsbb$165 Def00004A
+S A$crc16ansimsbb$156 Def000040
+S A$crc16ansimsbb$147 Def000036
+S A$crc16ansimsbb$138 Def000025
+S A$crc16ansimsbb$129 Def00001A
+S C$crc16ansimsbb.c$10$0$0 Def000000
+S A$crc16ansimsbb$238 Def0000B0
+S A$crc16ansimsbb$229 Def0000A6
+S A$crc16ansimsbb$193 Def00006F
+S A$crc16ansimsbb$175 Def00005A
+S A$crc16ansimsbb$166 Def00004C
+S A$crc16ansimsbb$148 Def000037
+S A$crc16ansimsbb$139 Def000026
+S A$crc16ansimsbb$239 Def0000B2
+S A$crc16ansimsbb$194 Def000071
+S A$crc16ansimsbb$185 Def000065
+S A$crc16ansimsbb$176 Def00005B
+S A$crc16ansimsbb$167 Def00004E
+S A$crc16ansimsbb$158 Def000042
+S A$crc16ansimsbb$149 Def000038
+S A$crc16ansimsbb$195 Def000073
+S A$crc16ansimsbb$186 Def000066
+S A$crc16ansimsbb$168 Def000050
+S A$crc16ansimsbb$159 Def000043
+S A$crc16ansimsbb$196 Def000075
+S A$crc16ansimsbb$187 Def000067
+S A$crc16ansimsbb$178 Def00005C
+S A$crc16ansimsbb$169 Def000052
+S A$crc16ansimsbb$197 Def000077
+S A$crc16ansimsbb$188 Def000069
+S A$crc16ansimsbb$179 Def00005E
+S A$crc16ansimsbb$198 Def000079
+S A$crc16ansimsbb$199 Def00007B
+S G$crc_crc16_msb$0$0 Def000000
+S _crc_crc16_msb Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16ansimsbb
+F:G$crc_crc16_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansimsbb.crc_crc16_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16ansimsbb.crc_crc16_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16ansimsbb.crc_crc16_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpb
+
+;!FILE libmf/crc16dnpb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16dnpb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16dnp_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S G$crc_crc16dnp$0$0 Def000000
+S _crc_crc16dnp Def000000
+S C$crc16dnpb.c$228$1$63 Def000000
+S A$crc16dnpb$200 Def00007C
+S A$crc16dnpb$110 Def000004
+S C$crc16dnpb.c$229$1$63 Def0000B6
+S A$crc16dnpb$210 Def000089
+S A$crc16dnpb$201 Def00007D
+S A$crc16dnpb$120 Def00000E
+S A$crc16dnpb$111 Def000005
+S A$crc16dnpb$220 Def000095
+S A$crc16dnpb$211 Def00008B
+S A$crc16dnpb$202 Def00007E
+S A$crc16dnpb$130 Def00001D
+S A$crc16dnpb$121 Def00000F
+S A$crc16dnpb$112 Def000006
+S A$crc16dnpb$230 Def0000A6
+S A$crc16dnpb$221 Def000096
+S A$crc16dnpb$203 Def00007F
+S A$crc16dnpb$140 Def000028
+S A$crc16dnpb$131 Def00001F
+S A$crc16dnpb$122 Def000010
+S A$crc16dnpb$113 Def000007
+S A$crc16dnpb$240 Def0000B4
+S A$crc16dnpb$231 Def0000A7
+S A$crc16dnpb$222 Def000098
+S A$crc16dnpb$213 Def00008D
+S A$crc16dnpb$204 Def000081
+S A$crc16dnpb$150 Def000038
+S A$crc16dnpb$141 Def00002A
+S A$crc16dnpb$123 Def000011
+S A$crc16dnpb$114 Def000008
+S A$crc16dnpb$232 Def0000A8
+S A$crc16dnpb$223 Def00009A
+S A$crc16dnpb$214 Def00008E
+S A$crc16dnpb$205 Def000082
+S A$crc16dnpb$151 Def00003A
+S A$crc16dnpb$142 Def00002C
+S A$crc16dnpb$124 Def000013
+S A$crc16dnpb$115 Def000009
+S XG$crc_crc16dnp$0$0 Def0000B6
+S A$crc16dnpb$233 Def0000AA
+S A$crc16dnpb$224 Def00009C
+S A$crc16dnpb$215 Def00008F
+S A$crc16dnpb$170 Def000054
+S A$crc16dnpb$161 Def000044
+S A$crc16dnpb$152 Def00003B
+S A$crc16dnpb$143 Def00002E
+S A$crc16dnpb$134 Def000022
+S A$crc16dnpb$125 Def000014
+S A$crc16dnpb$116 Def00000A
+S A$crc16dnpb$234 Def0000AB
+S A$crc16dnpb$225 Def00009E
+S A$crc16dnpb$216 Def000090
+S A$crc16dnpb$207 Def000083
+S A$crc16dnpb$171 Def000055
+S A$crc16dnpb$162 Def000045
+S A$crc16dnpb$144 Def000030
+S A$crc16dnpb$135 Def000023
+S A$crc16dnpb$126 Def000016
+S A$crc16dnpb$117 Def00000B
+S A$crc16dnpb$108 Def000000
+S A$crc16dnpb$226 Def0000A0
+S A$crc16dnpb$217 Def000092
+S A$crc16dnpb$208 Def000085
+S A$crc16dnpb$190 Def00006B
+S A$crc16dnpb$181 Def000060
+S A$crc16dnpb$172 Def000056
+S A$crc16dnpb$163 Def000046
+S A$crc16dnpb$154 Def00003C
+S A$crc16dnpb$145 Def000032
+S A$crc16dnpb$118 Def00000C
+S A$crc16dnpb$109 Def000002
+S A$crc16dnpb$236 Def0000AC
+S A$crc16dnpb$227 Def0000A2
+S A$crc16dnpb$209 Def000087
+S A$crc16dnpb$191 Def00006C
+S A$crc16dnpb$182 Def000062
+S A$crc16dnpb$173 Def000057
+S A$crc16dnpb$164 Def000048
+S A$crc16dnpb$155 Def00003E
+S A$crc16dnpb$146 Def000034
+S A$crc16dnpb$137 Def000024
+S A$crc16dnpb$128 Def000017
+S A$crc16dnpb$119 Def00000D
+S A$crc16dnpb$237 Def0000AE
+S A$crc16dnpb$228 Def0000A4
+S A$crc16dnpb$219 Def000094
+S A$crc16dnpb$192 Def00006D
+S A$crc16dnpb$183 Def000064
+S A$crc16dnpb$174 Def000058
+S A$crc16dnpb$165 Def00004A
+S A$crc16dnpb$156 Def000040
+S A$crc16dnpb$147 Def000035
+S A$crc16dnpb$138 Def000025
+S A$crc16dnpb$129 Def00001A
+S C$crc16dnpb.c$10$0$0 Def000000
+S A$crc16dnpb$238 Def0000B0
+S A$crc16dnpb$229 Def0000A5
+S A$crc16dnpb$193 Def00006F
+S A$crc16dnpb$175 Def00005A
+S A$crc16dnpb$166 Def00004C
+S A$crc16dnpb$148 Def000036
+S A$crc16dnpb$139 Def000026
+S A$crc16dnpb$239 Def0000B2
+S A$crc16dnpb$194 Def000071
+S A$crc16dnpb$185 Def000065
+S A$crc16dnpb$176 Def00005B
+S A$crc16dnpb$167 Def00004E
+S A$crc16dnpb$158 Def000042
+S A$crc16dnpb$149 Def000037
+S A$crc16dnpb$195 Def000073
+S A$crc16dnpb$186 Def000066
+S A$crc16dnpb$168 Def000050
+S A$crc16dnpb$159 Def000043
+S A$crc16dnpb$196 Def000075
+S A$crc16dnpb$187 Def000067
+S A$crc16dnpb$178 Def00005C
+S A$crc16dnpb$169 Def000052
+S A$crc16dnpb$197 Def000077
+S A$crc16dnpb$188 Def000069
+S A$crc16dnpb$179 Def00005E
+S A$crc16dnpb$198 Def000079
+S A$crc16dnpb$199 Def00007B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16dnpb
+F:G$crc_crc16dnp$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpb.crc_crc16dnp$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16dnpb.crc_crc16dnp$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16dnpb.crc_crc16dnp$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpmsbb
+
+;!FILE libmf/crc16dnpmsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16dnpmsbb
+O -mmcs51 --model-small
+S _crc_crc16dnp_msbtable Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S XG$crc_crc16dnp_msb$0$0 Def0000B6
+S C$crc16dnpmsbb.c$228$1$63 Def000000
+S A$crc16dnpmsbb$200 Def00007D
+S A$crc16dnpmsbb$110 Def000004
+S C$crc16dnpmsbb.c$229$1$63 Def0000B6
+S A$crc16dnpmsbb$210 Def000089
+S A$crc16dnpmsbb$201 Def00007E
+S A$crc16dnpmsbb$120 Def00000E
+S A$crc16dnpmsbb$111 Def000005
+S A$crc16dnpmsbb$220 Def000095
+S A$crc16dnpmsbb$211 Def00008B
+S A$crc16dnpmsbb$202 Def00007F
+S A$crc16dnpmsbb$130 Def00001D
+S A$crc16dnpmsbb$121 Def00000F
+S A$crc16dnpmsbb$112 Def000006
+S A$crc16dnpmsbb$230 Def0000A7
+S A$crc16dnpmsbb$221 Def000096
+S A$crc16dnpmsbb$203 Def000080
+S A$crc16dnpmsbb$140 Def000028
+S A$crc16dnpmsbb$131 Def00001F
+S A$crc16dnpmsbb$122 Def000010
+S A$crc16dnpmsbb$113 Def000007
+S A$crc16dnpmsbb$240 Def0000B4
+S A$crc16dnpmsbb$231 Def0000A8
+S A$crc16dnpmsbb$222 Def000098
+S A$crc16dnpmsbb$213 Def00008D
+S A$crc16dnpmsbb$204 Def000081
+S A$crc16dnpmsbb$150 Def000039
+S A$crc16dnpmsbb$141 Def00002A
+S A$crc16dnpmsbb$123 Def000011
+S A$crc16dnpmsbb$114 Def000008
+S A$crc16dnpmsbb$232 Def0000A9
+S A$crc16dnpmsbb$223 Def00009A
+S A$crc16dnpmsbb$214 Def00008E
+S A$crc16dnpmsbb$205 Def000082
+S A$crc16dnpmsbb$151 Def00003A
+S A$crc16dnpmsbb$142 Def00002C
+S A$crc16dnpmsbb$124 Def000013
+S A$crc16dnpmsbb$115 Def000009
+S A$crc16dnpmsbb$233 Def0000AA
+S A$crc16dnpmsbb$224 Def00009C
+S A$crc16dnpmsbb$215 Def00008F
+S A$crc16dnpmsbb$170 Def000054
+S A$crc16dnpmsbb$161 Def000044
+S A$crc16dnpmsbb$152 Def00003B
+S A$crc16dnpmsbb$143 Def00002E
+S A$crc16dnpmsbb$134 Def000022
+S A$crc16dnpmsbb$125 Def000014
+S A$crc16dnpmsbb$116 Def00000A
+S A$crc16dnpmsbb$234 Def0000AB
+S A$crc16dnpmsbb$225 Def00009E
+S A$crc16dnpmsbb$216 Def000090
+S A$crc16dnpmsbb$207 Def000083
+S A$crc16dnpmsbb$171 Def000056
+S A$crc16dnpmsbb$162 Def000045
+S A$crc16dnpmsbb$144 Def000030
+S A$crc16dnpmsbb$135 Def000023
+S A$crc16dnpmsbb$126 Def000016
+S A$crc16dnpmsbb$117 Def00000B
+S A$crc16dnpmsbb$108 Def000000
+S A$crc16dnpmsbb$226 Def0000A0
+S A$crc16dnpmsbb$217 Def000092
+S A$crc16dnpmsbb$208 Def000085
+S A$crc16dnpmsbb$190 Def00006B
+S A$crc16dnpmsbb$181 Def000060
+S A$crc16dnpmsbb$172 Def000057
+S A$crc16dnpmsbb$163 Def000046
+S A$crc16dnpmsbb$154 Def00003C
+S A$crc16dnpmsbb$145 Def000032
+S A$crc16dnpmsbb$118 Def00000C
+S A$crc16dnpmsbb$109 Def000002
+S A$crc16dnpmsbb$236 Def0000AC
+S A$crc16dnpmsbb$227 Def0000A2
+S A$crc16dnpmsbb$209 Def000087
+S A$crc16dnpmsbb$191 Def00006C
+S A$crc16dnpmsbb$182 Def000062
+S A$crc16dnpmsbb$173 Def000058
+S A$crc16dnpmsbb$164 Def000048
+S A$crc16dnpmsbb$155 Def00003E
+S A$crc16dnpmsbb$146 Def000034
+S A$crc16dnpmsbb$137 Def000024
+S A$crc16dnpmsbb$128 Def000017
+S A$crc16dnpmsbb$119 Def00000D
+S A$crc16dnpmsbb$237 Def0000AE
+S A$crc16dnpmsbb$228 Def0000A4
+S A$crc16dnpmsbb$219 Def000094
+S A$crc16dnpmsbb$192 Def00006D
+S A$crc16dnpmsbb$183 Def000064
+S A$crc16dnpmsbb$174 Def000059
+S A$crc16dnpmsbb$165 Def00004A
+S A$crc16dnpmsbb$156 Def000040
+S A$crc16dnpmsbb$147 Def000036
+S A$crc16dnpmsbb$138 Def000025
+S A$crc16dnpmsbb$129 Def00001A
+S C$crc16dnpmsbb.c$10$0$0 Def000000
+S A$crc16dnpmsbb$238 Def0000B0
+S A$crc16dnpmsbb$229 Def0000A6
+S A$crc16dnpmsbb$193 Def00006F
+S A$crc16dnpmsbb$175 Def00005A
+S A$crc16dnpmsbb$166 Def00004C
+S A$crc16dnpmsbb$148 Def000037
+S A$crc16dnpmsbb$139 Def000026
+S A$crc16dnpmsbb$239 Def0000B2
+S A$crc16dnpmsbb$194 Def000071
+S A$crc16dnpmsbb$185 Def000065
+S A$crc16dnpmsbb$176 Def00005B
+S A$crc16dnpmsbb$167 Def00004E
+S A$crc16dnpmsbb$158 Def000042
+S A$crc16dnpmsbb$149 Def000038
+S G$crc_crc16dnp_msb$0$0 Def000000
+S A$crc16dnpmsbb$195 Def000073
+S A$crc16dnpmsbb$186 Def000066
+S A$crc16dnpmsbb$168 Def000050
+S A$crc16dnpmsbb$159 Def000043
+S A$crc16dnpmsbb$196 Def000075
+S A$crc16dnpmsbb$187 Def000067
+S A$crc16dnpmsbb$178 Def00005C
+S A$crc16dnpmsbb$169 Def000052
+S A$crc16dnpmsbb$197 Def000077
+S A$crc16dnpmsbb$188 Def000069
+S A$crc16dnpmsbb$179 Def00005E
+S A$crc16dnpmsbb$198 Def000079
+S A$crc16dnpmsbb$199 Def00007B
+S _crc_crc16dnp_msb Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 00
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 00
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 00
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 00
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 00 F1 83 0B 00 00
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 00 F1 83 0C 00 00
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16dnpmsbb
+F:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansib
+
+;!FILE libmf/crc32ansib.asm
+XH3
+H 1A areas AE global symbols
+M crc32ansib
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc32_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size ED flags 20 addr 0
+S A$crc32ansib$200 Def000077
+S A$crc32ansib$110 Def000004
+S A$crc32ansib$120 Def00000E
+S A$crc32ansib$111 Def000005
+S A$crc32ansib$220 Def00008E
+S A$crc32ansib$211 Def000084
+S A$crc32ansib$202 Def000078
+S A$crc32ansib$130 Def000019
+S A$crc32ansib$121 Def00000F
+S A$crc32ansib$112 Def000006
+S G$crc_crc32$0$0 Def000000
+S A$crc32ansib$230 Def00009F
+S A$crc32ansib$221 Def00008F
+S A$crc32ansib$203 Def00007A
+S A$crc32ansib$140 Def000028
+S A$crc32ansib$131 Def00001A
+S A$crc32ansib$122 Def000010
+S A$crc32ansib$113 Def000007
+S A$crc32ansib$240 Def0000AB
+S A$crc32ansib$231 Def0000A0
+S A$crc32ansib$222 Def000091
+S A$crc32ansib$213 Def000086
+S A$crc32ansib$150 Def000035
+S A$crc32ansib$141 Def000029
+S A$crc32ansib$132 Def00001C
+S A$crc32ansib$123 Def000011
+S A$crc32ansib$114 Def000008
+S A$crc32ansib$250 Def0000B9
+S A$crc32ansib$241 Def0000AD
+S A$crc32ansib$232 Def0000A1
+S A$crc32ansib$223 Def000093
+S A$crc32ansib$214 Def000087
+S A$crc32ansib$205 Def00007C
+S A$crc32ansib$160 Def000043
+S A$crc32ansib$151 Def000037
+S A$crc32ansib$124 Def000012
+S A$crc32ansib$115 Def000009
+S A$crc32ansib$260 Def0000C5
+S A$crc32ansib$251 Def0000BA
+S A$crc32ansib$242 Def0000AE
+S A$crc32ansib$233 Def0000A3
+S A$crc32ansib$224 Def000095
+S A$crc32ansib$215 Def000088
+S A$crc32ansib$206 Def00007E
+S A$crc32ansib$170 Def00004F
+S A$crc32ansib$161 Def000044
+S A$crc32ansib$152 Def000039
+S A$crc32ansib$143 Def00002A
+S A$crc32ansib$134 Def00001D
+S A$crc32ansib$125 Def000013
+S A$crc32ansib$116 Def00000A
+S A$crc32ansib$270 Def0000D5
+S A$crc32ansib$261 Def0000C7
+S A$crc32ansib$252 Def0000BB
+S A$crc32ansib$234 Def0000A4
+S A$crc32ansib$225 Def000097
+S A$crc32ansib$216 Def00008A
+S A$crc32ansib$207 Def000080
+S A$crc32ansib$180 Def00005A
+S A$crc32ansib$171 Def000051
+S A$crc32ansib$162 Def000046
+S A$crc32ansib$153 Def00003B
+S A$crc32ansib$144 Def00002B
+S A$crc32ansib$135 Def000020
+S A$crc32ansib$126 Def000014
+S A$crc32ansib$117 Def00000B
+S A$crc32ansib$108 Def000000
+S A$crc32ansib$280 Def0000E2
+S A$crc32ansib$271 Def0000D7
+S A$crc32ansib$262 Def0000C9
+S A$crc32ansib$253 Def0000BC
+S A$crc32ansib$244 Def0000AF
+S A$crc32ansib$235 Def0000A5
+S A$crc32ansib$226 Def000099
+S A$crc32ansib$208 Def000082
+S A$crc32ansib$190 Def00006A
+S A$crc32ansib$181 Def00005C
+S A$crc32ansib$163 Def000047
+S A$crc32ansib$154 Def00003C
+S A$crc32ansib$145 Def00002C
+S A$crc32ansib$136 Def000023
+S A$crc32ansib$127 Def000015
+S A$crc32ansib$118 Def00000C
+S A$crc32ansib$109 Def000002
+S A$crc32ansib$272 Def0000D8
+S A$crc32ansib$263 Def0000CB
+S A$crc32ansib$254 Def0000BE
+S A$crc32ansib$245 Def0000B1
+S A$crc32ansib$236 Def0000A6
+S A$crc32ansib$227 Def00009B
+S A$crc32ansib$218 Def00008C
+S A$crc32ansib$209 Def000083
+S A$crc32ansib$191 Def00006C
+S A$crc32ansib$182 Def00005E
+S A$crc32ansib$173 Def000053
+S A$crc32ansib$164 Def000048
+S A$crc32ansib$155 Def00003D
+S A$crc32ansib$146 Def00002D
+S A$crc32ansib$137 Def000025
+S A$crc32ansib$128 Def000016
+S A$crc32ansib$119 Def00000D
+S A$crc32ansib$282 Def0000E3
+S A$crc32ansib$273 Def0000D9
+S A$crc32ansib$264 Def0000CD
+S A$crc32ansib$246 Def0000B3
+S A$crc32ansib$237 Def0000A8
+S A$crc32ansib$228 Def00009D
+S A$crc32ansib$219 Def00008D
+S A$crc32ansib$192 Def00006D
+S A$crc32ansib$183 Def000060
+S A$crc32ansib$174 Def000054
+S A$crc32ansib$165 Def000049
+S A$crc32ansib$156 Def00003E
+S A$crc32ansib$147 Def00002F
+S A$crc32ansib$129 Def000017
+S C$crc32ansib.c$10$0$0 Def000000
+S A$crc32ansib$283 Def0000E5
+S A$crc32ansib$274 Def0000DA
+S A$crc32ansib$265 Def0000CF
+S A$crc32ansib$256 Def0000C0
+S A$crc32ansib$247 Def0000B5
+S A$crc32ansib$238 Def0000A9
+S A$crc32ansib$229 Def00009E
+S A$crc32ansib$193 Def00006E
+S A$crc32ansib$184 Def000062
+S A$crc32ansib$166 Def00004B
+S A$crc32ansib$157 Def00003F
+S A$crc32ansib$148 Def000031
+S A$crc32ansib$284 Def0000E7
+S A$crc32ansib$275 Def0000DC
+S A$crc32ansib$266 Def0000D1
+S A$crc32ansib$257 Def0000C1
+S A$crc32ansib$248 Def0000B7
+S A$crc32ansib$239 Def0000AA
+S A$crc32ansib$194 Def00006F
+S A$crc32ansib$185 Def000064
+S A$crc32ansib$176 Def000055
+S A$crc32ansib$167 Def00004C
+S A$crc32ansib$158 Def000041
+S A$crc32ansib$149 Def000033
+S A$crc32ansib$285 Def0000E9
+S A$crc32ansib$276 Def0000DD
+S A$crc32ansib$267 Def0000D2
+S A$crc32ansib$258 Def0000C2
+S A$crc32ansib$195 Def000071
+S A$crc32ansib$186 Def000066
+S A$crc32ansib$177 Def000056
+S A$crc32ansib$159 Def000042
+S A$crc32ansib$286 Def0000EB
+S A$crc32ansib$277 Def0000DE
+S A$crc32ansib$268 Def0000D3
+S A$crc32ansib$259 Def0000C3
+S A$crc32ansib$196 Def000072
+S A$crc32ansib$187 Def000067
+S A$crc32ansib$178 Def000057
+S A$crc32ansib$169 Def00004D
+S _crc_crc32 Def000000
+S A$crc32ansib$278 Def0000DF
+S A$crc32ansib$269 Def0000D4
+S A$crc32ansib$197 Def000073
+S A$crc32ansib$188 Def000068
+S A$crc32ansib$179 Def000058
+S A$crc32ansib$279 Def0000E1
+S A$crc32ansib$198 Def000074
+S A$crc32ansib$189 Def000069
+S A$crc32ansib$199 Def000076
+S XG$crc_crc32$0$0 Def0000ED
+S C$crc32ansib.c$311$1$63 Def000000
+S C$crc32ansib.c$312$1$63 Def0000ED
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 F9 F8 E6 FC 08 E6 FD 08 E6 FE
+R 00 00 00 16
+T 00 00 0D 08 E6 FF 08 E6 FA 08 E6 FB 4A 60 63 EA
+R 00 00 00 16
+T 00 00 1A 60 01 0B
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 20 00 00 00 64 30 00 00 00 63 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 26 00 00 00 2B
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6C 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 33 C5 82 54 03 34 00 00 00 F5 83 E4 93 6D
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 3E FC 74 01 93 6E FD 74 02 93 6F FE 74 03
+R 00 00 00 16
+T 00 00 4B 93 FF DA D9 DB D7 80 29
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 E2 08 6C 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 5E C5 82 54 03 34 00 00 00 F5 83 E4 93 6D
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 69 FC 74 01 93 6E FD 74 02 93 6F FE 74 03
+R 00 00 00 16
+T 00 00 76 93 FF DA D9 DB D7
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C 8C 82 8D 83 8E F0 EF 22
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 80 33
+R 00 00 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 E0 A3 A8 82 A9 83 6C 23 23 F5 82 54 FC
+R 00 00 00 16
+T 00 00 93 24 00 00 00 C5 82 54 03 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 9C 83 E4 93 6D FC 74 01 93 6E FD 74 02 93
+R 00 00 00 16
+T 00 00 A9 6F FE 74 03 93 FF 89 83 88 82 DA D1 DB
+R 00 00 00 16
+T 00 00 B6 CF 80 C3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 E4 93 A3 A8 82 A9 83 6C 23 23 F5 82 54
+R 00 00 00 16
+T 00 00 C6 FC 24 00 00 00 C5 82 54 03 34 00 00 00
+R 00 00 00 16 F1 03 05 00 04 F1 83 0D 00 04
+T 00 00 CF F5 83 E4 93 6D FC 74 01 93 6E FD 74 02
+R 00 00 00 16
+T 00 00 DC 93 6F FE 74 03 93 FF 89 83 88 82 DA D0
+R 00 00 00 16
+T 00 00 E9 DB CE 80 8F
+R 00 00 00 16
+
+
+M:crc32ansib
+F:G$crc_crc32$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansib.crc_crc32$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc32ansib.crc_crc32$crc$1$62({4}SL:U),B,1,-8
+S:Lcrc32ansib.crc_crc32$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansimsbb
+
+;!FILE libmf/crc32ansimsbb.asm
+XH3
+H 1A areas AE global symbols
+M crc32ansimsbb
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc32_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size ED flags 20 addr 0
+S XG$crc_crc32_msb$0$0 Def0000ED
+S C$crc32ansimsbb.c$312$1$63 Def0000ED
+S A$crc32ansimsbb$200 Def000077
+S A$crc32ansimsbb$110 Def000004
+S A$crc32ansimsbb$120 Def00000E
+S A$crc32ansimsbb$111 Def000005
+S A$crc32ansimsbb$220 Def00008E
+S A$crc32ansimsbb$211 Def000084
+S A$crc32ansimsbb$202 Def000078
+S A$crc32ansimsbb$130 Def000019
+S A$crc32ansimsbb$121 Def00000F
+S A$crc32ansimsbb$112 Def000006
+S A$crc32ansimsbb$230 Def0000A0
+S A$crc32ansimsbb$221 Def00008F
+S A$crc32ansimsbb$203 Def00007A
+S A$crc32ansimsbb$140 Def000028
+S A$crc32ansimsbb$131 Def00001A
+S A$crc32ansimsbb$122 Def000010
+S A$crc32ansimsbb$113 Def000007
+S A$crc32ansimsbb$240 Def0000AC
+S A$crc32ansimsbb$231 Def0000A1
+S A$crc32ansimsbb$222 Def000091
+S A$crc32ansimsbb$213 Def000086
+S A$crc32ansimsbb$150 Def000035
+S A$crc32ansimsbb$141 Def000029
+S A$crc32ansimsbb$132 Def00001C
+S A$crc32ansimsbb$123 Def000011
+S A$crc32ansimsbb$114 Def000008
+S A$crc32ansimsbb$250 Def0000B9
+S A$crc32ansimsbb$241 Def0000AD
+S A$crc32ansimsbb$232 Def0000A2
+S A$crc32ansimsbb$223 Def000093
+S A$crc32ansimsbb$214 Def000087
+S A$crc32ansimsbb$205 Def00007C
+S A$crc32ansimsbb$160 Def000044
+S A$crc32ansimsbb$151 Def000037
+S A$crc32ansimsbb$124 Def000012
+S A$crc32ansimsbb$115 Def000009
+S A$crc32ansimsbb$260 Def0000C5
+S A$crc32ansimsbb$251 Def0000BA
+S A$crc32ansimsbb$242 Def0000AE
+S A$crc32ansimsbb$233 Def0000A4
+S A$crc32ansimsbb$224 Def000095
+S A$crc32ansimsbb$215 Def000088
+S A$crc32ansimsbb$206 Def00007E
+S A$crc32ansimsbb$170 Def00004F
+S A$crc32ansimsbb$161 Def000045
+S A$crc32ansimsbb$152 Def000039
+S A$crc32ansimsbb$143 Def00002A
+S A$crc32ansimsbb$134 Def00001D
+S A$crc32ansimsbb$125 Def000013
+S A$crc32ansimsbb$116 Def00000A
+S A$crc32ansimsbb$270 Def0000D6
+S A$crc32ansimsbb$261 Def0000C7
+S A$crc32ansimsbb$252 Def0000BB
+S A$crc32ansimsbb$234 Def0000A5
+S A$crc32ansimsbb$225 Def000097
+S A$crc32ansimsbb$216 Def00008A
+S A$crc32ansimsbb$207 Def000080
+S A$crc32ansimsbb$180 Def00005A
+S A$crc32ansimsbb$171 Def000051
+S A$crc32ansimsbb$162 Def000047
+S A$crc32ansimsbb$153 Def00003B
+S A$crc32ansimsbb$144 Def00002B
+S A$crc32ansimsbb$135 Def000020
+S A$crc32ansimsbb$126 Def000014
+S A$crc32ansimsbb$117 Def00000B
+S A$crc32ansimsbb$108 Def000000
+S A$crc32ansimsbb$280 Def0000E2
+S A$crc32ansimsbb$271 Def0000D8
+S A$crc32ansimsbb$262 Def0000C9
+S A$crc32ansimsbb$253 Def0000BC
+S A$crc32ansimsbb$244 Def0000AF
+S A$crc32ansimsbb$235 Def0000A6
+S A$crc32ansimsbb$226 Def000099
+S A$crc32ansimsbb$208 Def000082
+S A$crc32ansimsbb$190 Def00006B
+S A$crc32ansimsbb$181 Def00005C
+S A$crc32ansimsbb$163 Def000048
+S A$crc32ansimsbb$154 Def00003D
+S A$crc32ansimsbb$145 Def00002C
+S A$crc32ansimsbb$136 Def000023
+S A$crc32ansimsbb$127 Def000015
+S A$crc32ansimsbb$118 Def00000C
+S A$crc32ansimsbb$109 Def000002
+S A$crc32ansimsbb$272 Def0000D9
+S A$crc32ansimsbb$263 Def0000CB
+S A$crc32ansimsbb$254 Def0000BE
+S A$crc32ansimsbb$245 Def0000B1
+S A$crc32ansimsbb$236 Def0000A7
+S A$crc32ansimsbb$227 Def00009B
+S A$crc32ansimsbb$218 Def00008C
+S A$crc32ansimsbb$209 Def000083
+S A$crc32ansimsbb$191 Def00006D
+S A$crc32ansimsbb$182 Def00005E
+S A$crc32ansimsbb$173 Def000053
+S A$crc32ansimsbb$164 Def000049
+S A$crc32ansimsbb$155 Def00003E
+S A$crc32ansimsbb$146 Def00002D
+S A$crc32ansimsbb$137 Def000025
+S A$crc32ansimsbb$128 Def000016
+S A$crc32ansimsbb$119 Def00000D
+S A$crc32ansimsbb$282 Def0000E3
+S A$crc32ansimsbb$273 Def0000DA
+S A$crc32ansimsbb$264 Def0000CD
+S A$crc32ansimsbb$246 Def0000B3
+S A$crc32ansimsbb$237 Def0000A9
+S A$crc32ansimsbb$228 Def00009D
+S A$crc32ansimsbb$219 Def00008D
+S A$crc32ansimsbb$192 Def00006E
+S A$crc32ansimsbb$183 Def000060
+S A$crc32ansimsbb$174 Def000054
+S A$crc32ansimsbb$165 Def00004A
+S A$crc32ansimsbb$156 Def00003F
+S A$crc32ansimsbb$147 Def00002F
+S A$crc32ansimsbb$129 Def000017
+S C$crc32ansimsbb.c$10$0$0 Def000000
+S A$crc32ansimsbb$283 Def0000E5
+S A$crc32ansimsbb$274 Def0000DB
+S A$crc32ansimsbb$265 Def0000CF
+S A$crc32ansimsbb$256 Def0000C0
+S A$crc32ansimsbb$247 Def0000B5
+S A$crc32ansimsbb$238 Def0000AA
+S A$crc32ansimsbb$229 Def00009F
+S A$crc32ansimsbb$193 Def00006F
+S A$crc32ansimsbb$184 Def000062
+S A$crc32ansimsbb$166 Def00004B
+S A$crc32ansimsbb$157 Def000040
+S A$crc32ansimsbb$148 Def000031
+S A$crc32ansimsbb$284 Def0000E7
+S A$crc32ansimsbb$275 Def0000DD
+S A$crc32ansimsbb$266 Def0000D1
+S A$crc32ansimsbb$257 Def0000C1
+S A$crc32ansimsbb$248 Def0000B7
+S A$crc32ansimsbb$239 Def0000AB
+S A$crc32ansimsbb$194 Def000070
+S A$crc32ansimsbb$185 Def000064
+S A$crc32ansimsbb$176 Def000055
+S A$crc32ansimsbb$167 Def00004C
+S A$crc32ansimsbb$158 Def000042
+S A$crc32ansimsbb$149 Def000033
+S A$crc32ansimsbb$285 Def0000E9
+S A$crc32ansimsbb$276 Def0000DE
+S A$crc32ansimsbb$267 Def0000D3
+S A$crc32ansimsbb$258 Def0000C2
+S A$crc32ansimsbb$195 Def000072
+S A$crc32ansimsbb$186 Def000066
+S A$crc32ansimsbb$177 Def000056
+S A$crc32ansimsbb$159 Def000043
+S A$crc32ansimsbb$286 Def0000EB
+S A$crc32ansimsbb$277 Def0000DF
+S A$crc32ansimsbb$268 Def0000D4
+S A$crc32ansimsbb$259 Def0000C3
+S A$crc32ansimsbb$196 Def000073
+S A$crc32ansimsbb$187 Def000068
+S A$crc32ansimsbb$178 Def000057
+S A$crc32ansimsbb$169 Def00004D
+S A$crc32ansimsbb$278 Def0000E0
+S A$crc32ansimsbb$269 Def0000D5
+S A$crc32ansimsbb$197 Def000074
+S A$crc32ansimsbb$188 Def000069
+S A$crc32ansimsbb$179 Def000058
+S A$crc32ansimsbb$279 Def0000E1
+S A$crc32ansimsbb$198 Def000075
+S A$crc32ansimsbb$189 Def00006A
+S A$crc32ansimsbb$199 Def000076
+S G$crc_crc32_msb$0$0 Def000000
+S _crc_crc32_msb Def000000
+S C$crc32ansimsbb.c$311$1$63 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 F9 F8 E6 FC 08 E6 FD 08 E6 FE
+R 00 00 00 16
+T 00 00 0D 08 E6 FF 08 E6 FA 08 E6 FB 4A 60 63 EA
+R 00 00 00 16
+T 00 00 1A 60 01 0B
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 20 00 00 00 64 30 00 00 00 63 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 26 00 00 00 2B
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6F 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 33 C5 82 54 03 34 00 00 00 F5 83 74 03 93
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 3E 6E FF 74 02 93 6D FE 74 01 93 6C FD E4
+R 00 00 00 16
+T 00 00 4B 93 FC DA D9 DB D7 80 29
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 E2 08 6F 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 5E C5 82 54 03 34 00 00 00 F5 83 74 03 93
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 69 6E FF 74 02 93 6D FE 74 01 93 6C FD E4
+R 00 00 00 16
+T 00 00 76 93 FC DA D9 DB D7
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C 8C 82 8D 83 8E F0 EF 22
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 80 33
+R 00 00 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 E0 A3 A8 82 A9 83 6F 23 23 F5 82 54 FC
+R 00 00 00 16
+T 00 00 93 24 00 00 00 C5 82 54 03 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 9C 83 74 03 93 6E FF 74 02 93 6D FE 74 01
+R 00 00 00 16
+T 00 00 A9 93 6C FD E4 93 FC 89 83 88 82 DA D1 DB
+R 00 00 00 16
+T 00 00 B6 CF 80 C3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 E4 93 A3 A8 82 A9 83 6F 23 23 F5 82 54
+R 00 00 00 16
+T 00 00 C6 FC 24 00 00 00 C5 82 54 03 34 00 00 00
+R 00 00 00 16 F1 03 05 00 04 F1 83 0D 00 04
+T 00 00 CF F5 83 74 03 93 6E FF 74 02 93 6D FE 74
+R 00 00 00 16
+T 00 00 DC 01 93 6C FD E4 93 FC 89 83 88 82 DA D0
+R 00 00 00 16
+T 00 00 E9 DB CE 80 8F
+R 00 00 00 16
+
+
+M:crc32ansimsbb
+F:G$crc_crc32_msb$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansimsbb.crc_crc32_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc32ansimsbb.crc_crc32_msb$crc$1$62({4}SL:U),B,1,-8
+S:Lcrc32ansimsbb.crc_crc32_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccitttable
+
+XH3
+H 1A areas 3 global symbols
+M crcccitttable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_ccitt_table$0$0 Def000000
+S _crc_ccitt_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 89 11 12 23 9B 32 24 46 AD 57 36
+R 00 00 00 17
+T 00 00 0D 65 BF 74 48 8C C1 9D 5A AF D3 BE 6C CA
+R 00 00 00 17
+T 00 00 1A E5 DB 7E E9 F7 F8 81 10 08 01 93 33 1A
+R 00 00 00 17
+T 00 00 27 22 A5 56 2C 47 B7 75 3E 64 C9 9C 40 8D
+R 00 00 00 17
+T 00 00 34 DB BF 52 AE ED DA 64 CB FF F9 76 E8 02
+R 00 00 00 17
+T 00 00 41 21 8B 30 10 02 99 13 26 67 AF 76 34 44
+R 00 00 00 17
+T 00 00 4E BD 55 4A AD C3 BC 58 8E D1 9F 6E EB E7
+R 00 00 00 17
+T 00 00 5B FA 7C C8 F5 D9 83 31 0A 20 91 12 18 03
+R 00 00 00 17
+T 00 00 68 A7 77 2E 66 B5 54 3C 45 CB BD 42 AC D9
+R 00 00 00 17
+T 00 00 75 9E 50 8F EF FB 66 EA FD D8 74 C9 04 42
+R 00 00 00 17
+T 00 00 82 8D 53 16 61 9F 70 20 04 A9 15 32 27 BB
+R 00 00 00 17
+T 00 00 8F 36 4C CE C5 DF 5E ED D7 FC 68 88 E1 99
+R 00 00 00 17
+T 00 00 9C 7A AB F3 BA 85 52 0C 43 97 71 1E 60 A1
+R 00 00 00 17
+T 00 00 A9 14 28 05 B3 37 3A 26 CD DE 44 CF DF FD
+R 00 00 00 17
+T 00 00 B6 56 EC E9 98 60 89 FB BB 72 AA 06 63 8F
+R 00 00 00 17
+T 00 00 C3 72 14 40 9D 51 22 25 AB 34 30 06 B9 17
+R 00 00 00 17
+T 00 00 D0 4E EF C7 FE 5C CC D5 DD 6A A9 E3 B8 78
+R 00 00 00 17
+T 00 00 DD 8A F1 9B 87 73 0E 62 95 50 1C 41 A3 35
+R 00 00 00 17
+T 00 00 EA 2A 24 B1 16 38 07 CF FF 46 EE DD DC 54
+R 00 00 00 17
+T 00 00 F7 CD EB B9 62 A8 F9 9A 70 8B 08 84 81 95
+R 00 00 00 17
+T 00 01 04 1A A7 93 B6 2C C2 A5 D3 3E E1 B7 F0 40
+R 00 00 00 17
+T 00 01 11 08 C9 19 52 2B DB 3A 64 4E ED 5F 76 6D
+R 00 00 00 17
+T 00 01 1E FF 7C 89 94 00 85 9B B7 12 A6 AD D2 24
+R 00 00 00 17
+T 00 01 2B C3 BF F1 36 E0 C1 18 48 09 D3 3B 5A 2A
+R 00 00 00 17
+T 00 01 38 E5 5E 6C 4F F7 7D 7E 6C 0A A5 83 B4 18
+R 00 00 00 17
+T 00 01 45 86 91 97 2E E3 A7 F2 3C C0 B5 D1 42 29
+R 00 00 00 17
+T 00 01 52 CB 38 50 0A D9 1B 66 6F EF 7E 74 4C FD
+R 00 00 00 17
+T 00 01 5F 5D 8B B5 02 A4 99 96 10 87 AF F3 26 E2
+R 00 00 00 17
+T 00 01 6C BD D0 34 C1 C3 39 4A 28 D1 1A 58 0B E7
+R 00 00 00 17
+T 00 01 79 7F 6E 6E F5 5C 7C 4D 0C C6 85 D7 1E E5
+R 00 00 00 17
+T 00 01 86 97 F4 28 80 A1 91 3A A3 B3 B2 44 4A CD
+R 00 00 00 17
+T 00 01 93 5B 56 69 DF 78 60 0C E9 1D 72 2F FB 3E
+R 00 00 00 17
+T 00 01 A0 8D D6 04 C7 9F F5 16 E4 A9 90 20 81 BB
+R 00 00 00 17
+T 00 01 AD B3 32 A2 C5 5A 4C 4B D7 79 5E 68 E1 1C
+R 00 00 00 17
+T 00 01 BA 68 0D F3 3F 7A 2E 0E E7 87 F6 1C C4 95
+R 00 00 00 17
+T 00 01 C7 D5 2A A1 A3 B0 38 82 B1 93 46 6B CF 7A
+R 00 00 00 17
+T 00 01 D4 54 48 DD 59 62 2D EB 3C 70 0E F9 1F 8F
+R 00 00 00 17
+T 00 01 E1 F7 06 E6 9D D4 14 C5 AB B1 22 A0 B9 92
+R 00 00 00 17
+T 00 01 EE 30 83 C7 7B 4E 6A D5 58 5C 49 E3 3D 6A
+R 00 00 00 17
+T 00 01 FB 2C F1 1E 78 0F
+R 00 00 00 17
+
+
+M:crcccitttable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16table
+
+XH3
+H 1A areas 3 global symbols
+M crc16table
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16_table$0$0 Def000000
+S _crc_crc16_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 C1 C0 81 C1 40 01 01 C3 C0 03 80
+R 00 00 00 17
+T 00 00 0D 02 41 C2 01 C6 C0 06 80 07 41 C7 00 05
+R 00 00 00 17
+T 00 00 1A C1 C5 81 C4 40 04 01 CC C0 0C 80 0D 41
+R 00 00 00 17
+T 00 00 27 CD 00 0F C1 CF 81 CE 40 0E 00 0A C1 CA
+R 00 00 00 17
+T 00 00 34 81 CB 40 0B 01 C9 C0 09 80 08 41 C8 01
+R 00 00 00 17
+T 00 00 41 D8 C0 18 80 19 41 D9 00 1B C1 DB 81 DA
+R 00 00 00 17
+T 00 00 4E 40 1A 00 1E C1 DE 81 DF 40 1F 01 DD C0
+R 00 00 00 17
+T 00 00 5B 1D 80 1C 41 DC 00 14 C1 D4 81 D5 40 15
+R 00 00 00 17
+T 00 00 68 01 D7 C0 17 80 16 41 D6 01 D2 C0 12 80
+R 00 00 00 17
+T 00 00 75 13 41 D3 00 11 C1 D1 81 D0 40 10 01 F0
+R 00 00 00 17
+T 00 00 82 C0 30 80 31 41 F1 00 33 C1 F3 81 F2 40
+R 00 00 00 17
+T 00 00 8F 32 00 36 C1 F6 81 F7 40 37 01 F5 C0 35
+R 00 00 00 17
+T 00 00 9C 80 34 41 F4 00 3C C1 FC 81 FD 40 3D 01
+R 00 00 00 17
+T 00 00 A9 FF C0 3F 80 3E 41 FE 01 FA C0 3A 80 3B
+R 00 00 00 17
+T 00 00 B6 41 FB 00 39 C1 F9 81 F8 40 38 00 28 C1
+R 00 00 00 17
+T 00 00 C3 E8 81 E9 40 29 01 EB C0 2B 80 2A 41 EA
+R 00 00 00 17
+T 00 00 D0 01 EE C0 2E 80 2F 41 EF 00 2D C1 ED 81
+R 00 00 00 17
+T 00 00 DD EC 40 2C 01 E4 C0 24 80 25 41 E5 00 27
+R 00 00 00 17
+T 00 00 EA C1 E7 81 E6 40 26 00 22 C1 E2 81 E3 40
+R 00 00 00 17
+T 00 00 F7 23 01 E1 C0 21 80 20 41 E0 01 A0 C0 60
+R 00 00 00 17
+T 00 01 04 80 61 41 A1 00 63 C1 A3 81 A2 40 62 00
+R 00 00 00 17
+T 00 01 11 66 C1 A6 81 A7 40 67 01 A5 C0 65 80 64
+R 00 00 00 17
+T 00 01 1E 41 A4 00 6C C1 AC 81 AD 40 6D 01 AF C0
+R 00 00 00 17
+T 00 01 2B 6F 80 6E 41 AE 01 AA C0 6A 80 6B 41 AB
+R 00 00 00 17
+T 00 01 38 00 69 C1 A9 81 A8 40 68 00 78 C1 B8 81
+R 00 00 00 17
+T 00 01 45 B9 40 79 01 BB C0 7B 80 7A 41 BA 01 BE
+R 00 00 00 17
+T 00 01 52 C0 7E 80 7F 41 BF 00 7D C1 BD 81 BC 40
+R 00 00 00 17
+T 00 01 5F 7C 01 B4 C0 74 80 75 41 B5 00 77 C1 B7
+R 00 00 00 17
+T 00 01 6C 81 B6 40 76 00 72 C1 B2 81 B3 40 73 01
+R 00 00 00 17
+T 00 01 79 B1 C0 71 80 70 41 B0 00 50 C1 90 81 91
+R 00 00 00 17
+T 00 01 86 40 51 01 93 C0 53 80 52 41 92 01 96 C0
+R 00 00 00 17
+T 00 01 93 56 80 57 41 97 00 55 C1 95 81 94 40 54
+R 00 00 00 17
+T 00 01 A0 01 9C C0 5C 80 5D 41 9D 00 5F C1 9F 81
+R 00 00 00 17
+T 00 01 AD 9E 40 5E 00 5A C1 9A 81 9B 40 5B 01 99
+R 00 00 00 17
+T 00 01 BA C0 59 80 58 41 98 01 88 C0 48 80 49 41
+R 00 00 00 17
+T 00 01 C7 89 00 4B C1 8B 81 8A 40 4A 00 4E C1 8E
+R 00 00 00 17
+T 00 01 D4 81 8F 40 4F 01 8D C0 4D 80 4C 41 8C 00
+R 00 00 00 17
+T 00 01 E1 44 C1 84 81 85 40 45 01 87 C0 47 80 46
+R 00 00 00 17
+T 00 01 EE 41 86 01 82 C0 42 80 43 41 83 00 41 C1
+R 00 00 00 17
+T 00 01 FB 81 81 80 40 40
+R 00 00 00 17
+
+
+M:crc16table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16dnptable
+
+XH3
+H 1A areas 3 global symbols
+M crc16dnptable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16dnp_table$0$0 Def000000
+S _crc_crc16dnp_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 5E 36 BC 6C E2 5A 78 D9 26 EF C4
+R 00 00 00 17
+T 00 00 0D B5 9A 83 89 FF D7 C9 35 93 6B A5 F1 26
+R 00 00 00 17
+T 00 00 1A AF 10 4D 4A 13 7C 6B B2 35 84 D7 DE 89
+R 00 00 00 17
+T 00 00 27 E8 13 6B 4D 5D AF 07 F1 31 E2 4D BC 7B
+R 00 00 00 17
+T 00 00 34 5E 21 00 17 9A 94 C4 A2 26 F8 78 CE AF
+R 00 00 00 17
+T 00 00 41 29 F1 1F 13 45 4D 73 D7 F0 89 C6 6B 9C
+R 00 00 00 17
+T 00 00 4E 35 AA 26 D6 78 E0 9A BA C4 8C 5E 0F 00
+R 00 00 00 17
+T 00 00 5B 39 E2 63 BC 55 C4 9B 9A AD 78 F7 26 C1
+R 00 00 00 17
+T 00 00 68 BC 42 E2 74 00 2E 5E 18 4D 64 13 52 F1
+R 00 00 00 17
+T 00 00 75 08 AF 3E 35 BD 6B 8B 89 D1 D7 E7 5E 53
+R 00 00 00 17
+T 00 00 82 00 65 E2 3F BC 09 26 8A 78 BC 9A E6 C4
+R 00 00 00 17
+T 00 00 8F D0 D7 AC 89 9A 6B C0 35 F6 AF 75 F1 43
+R 00 00 00 17
+T 00 00 9C 13 19 4D 2F 35 E1 6B D7 89 8D D7 BB 4D
+R 00 00 00 17
+T 00 00 A9 38 13 0E F1 54 AF 62 BC 1E E2 28 00 72
+R 00 00 00 17
+T 00 00 B6 5E 44 C4 C7 9A F1 78 AB 26 9D F1 7A AF
+R 00 00 00 17
+T 00 00 C3 4C 4D 16 13 20 89 A3 D7 95 35 CF 6B F9
+R 00 00 00 17
+T 00 00 D0 78 85 26 B3 C4 E9 9A DF 00 5C 5E 6A BC
+R 00 00 00 17
+T 00 00 DD 30 E2 06 9A C8 C4 FE 26 A4 78 92 E2 11
+R 00 00 00 17
+T 00 00 EA BC 27 5E 7D 00 4B 13 37 4D 01 AF 5B F1
+R 00 00 00 17
+T 00 00 F7 6D 6B EE 35 D8 D7 82 89 B4 BC A6 E2 90
+R 00 00 00 17
+T 00 01 04 00 CA 5E FC C4 7F 9A 49 78 13 26 25 35
+R 00 00 00 17
+T 00 01 11 59 6B 6F 89 35 D7 03 4D 80 13 B6 F1 EC
+R 00 00 00 17
+T 00 01 1E AF DA D7 14 89 22 6B 78 35 4E AF CD F1
+R 00 00 00 17
+T 00 01 2B FB 13 A1 4D 97 5E EB 00 DD E2 87 BC B1
+R 00 00 00 17
+T 00 01 38 26 32 78 04 9A 5E C4 68 13 8F 4D B9 AF
+R 00 00 00 17
+T 00 01 45 E3 F1 D5 6B 56 35 60 D7 3A 89 0C 9A 70
+R 00 00 00 17
+T 00 01 52 C4 46 26 1C 78 2A E2 A9 BC 9F 5E C5 00
+R 00 00 00 17
+T 00 01 5F F3 78 3D 26 0B C4 51 9A 67 00 E4 5E D2
+R 00 00 00 17
+T 00 01 6C BC 88 E2 BE F1 C2 AF F4 4D AE 13 98 89
+R 00 00 00 17
+T 00 01 79 1B D7 2D 35 77 6B 41 E2 F5 BC C3 5E 99
+R 00 00 00 17
+T 00 01 86 00 AF 9A 2C C4 1A 26 40 78 76 6B 0A 35
+R 00 00 00 17
+T 00 01 93 3C D7 66 89 50 13 D3 4D E5 AF BF F1 89
+R 00 00 00 17
+T 00 01 A0 89 47 D7 71 35 2B 6B 1D F1 9E AF A8 4D
+R 00 00 00 17
+T 00 01 AD F2 13 C4 00 B8 5E 8E BC D4 E2 E2 78 61
+R 00 00 00 17
+T 00 01 BA 26 57 C4 0D 9A 3B 4D DC 13 EA F1 B0 AF
+R 00 00 00 17
+T 00 01 C7 86 35 05 6B 33 89 69 D7 5F C4 23 9A 15
+R 00 00 00 17
+T 00 01 D4 78 4F 26 79 BC FA E2 CC 00 96 5E A0 26
+R 00 00 00 17
+T 00 01 E1 6E 78 58 9A 02 C4 34 5E B7 00 81 E2 DB
+R 00 00 00 17
+T 00 01 EE BC ED AF 91 F1 A7 13 FD 4D CB D7 48 89
+R 00 00 00 17
+T 00 01 FB 7E 6B 24 35 12
+R 00 00 00 17
+
+
+M:crc16dnptable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crcccittmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crcccittmsbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_ccitt_msbtable$0$0 Def000000
+S _crc_ccitt_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 21 10 42 20 63 30 84 40 A5 50 C6
+R 00 00 00 17
+T 00 00 0D 60 E7 70 08 81 29 91 4A A1 6B B1 8C C1
+R 00 00 00 17
+T 00 00 1A AD D1 CE E1 EF F1 31 12 10 02 73 32 52
+R 00 00 00 17
+T 00 00 27 22 B5 52 94 42 F7 72 D6 62 39 93 18 83
+R 00 00 00 17
+T 00 00 34 7B B3 5A A3 BD D3 9C C3 FF F3 DE E3 62
+R 00 00 00 17
+T 00 00 41 24 43 34 20 04 01 14 E6 64 C7 74 A4 44
+R 00 00 00 17
+T 00 00 4E 85 54 6A A5 4B B5 28 85 09 95 EE E5 CF
+R 00 00 00 17
+T 00 00 5B F5 AC C5 8D D5 53 36 72 26 11 16 30 06
+R 00 00 00 17
+T 00 00 68 D7 76 F6 66 95 56 B4 46 5B B7 7A A7 19
+R 00 00 00 17
+T 00 00 75 97 38 87 DF F7 FE E7 9D D7 BC C7 C4 48
+R 00 00 00 17
+T 00 00 82 E5 58 86 68 A7 78 40 08 61 18 02 28 23
+R 00 00 00 17
+T 00 00 8F 38 CC C9 ED D9 8E E9 AF F9 48 89 69 99
+R 00 00 00 17
+T 00 00 9C 0A A9 2B B9 F5 5A D4 4A B7 7A 96 6A 71
+R 00 00 00 17
+T 00 00 A9 1A 50 0A 33 3A 12 2A FD DB DC CB BF FB
+R 00 00 00 17
+T 00 00 B6 9E EB 79 9B 58 8B 3B BB 1A AB A6 6C 87
+R 00 00 00 17
+T 00 00 C3 7C E4 4C C5 5C 22 2C 03 3C 60 0C 41 1C
+R 00 00 00 17
+T 00 00 D0 AE ED 8F FD EC CD CD DD 2A AD 0B BD 68
+R 00 00 00 17
+T 00 00 DD 8D 49 9D 97 7E B6 6E D5 5E F4 4E 13 3E
+R 00 00 00 17
+T 00 00 EA 32 2E 51 1E 70 0E 9F FF BE EF DD DF FC
+R 00 00 00 17
+T 00 00 F7 CF 1B BF 3A AF 59 9F 78 8F 88 91 A9 81
+R 00 00 00 17
+T 00 01 04 CA B1 EB A1 0C D1 2D C1 4E F1 6F E1 80
+R 00 00 00 17
+T 00 01 11 10 A1 00 C2 30 E3 20 04 50 25 40 46 70
+R 00 00 00 17
+T 00 01 1E 67 60 B9 83 98 93 FB A3 DA B3 3D C3 1C
+R 00 00 00 17
+T 00 01 2B D3 7F E3 5E F3 B1 02 90 12 F3 22 D2 32
+R 00 00 00 17
+T 00 01 38 35 42 14 52 77 62 56 72 EA B5 CB A5 A8
+R 00 00 00 17
+T 00 01 45 95 89 85 6E F5 4F E5 2C D5 0D C5 E2 34
+R 00 00 00 17
+T 00 01 52 C3 24 A0 14 81 04 66 74 47 64 24 54 05
+R 00 00 00 17
+T 00 01 5F 44 DB A7 FA B7 99 87 B8 97 5F E7 7E F7
+R 00 00 00 17
+T 00 01 6C 1D C7 3C D7 D3 26 F2 36 91 06 B0 16 57
+R 00 00 00 17
+T 00 01 79 66 76 76 15 46 34 56 4C D9 6D C9 0E F9
+R 00 00 00 17
+T 00 01 86 2F E9 C8 99 E9 89 8A B9 AB A9 44 58 65
+R 00 00 00 17
+T 00 01 93 48 06 78 27 68 C0 18 E1 08 82 38 A3 28
+R 00 00 00 17
+T 00 01 A0 7D CB 5C DB 3F EB 1E FB F9 8B D8 9B BB
+R 00 00 00 17
+T 00 01 AD AB 9A BB 75 4A 54 5A 37 6A 16 7A F1 0A
+R 00 00 00 17
+T 00 01 BA D0 1A B3 2A 92 3A 2E FD 0F ED 6C DD 4D
+R 00 00 00 17
+T 00 01 C7 CD AA BD 8B AD E8 9D C9 8D 26 7C 07 6C
+R 00 00 00 17
+T 00 01 D4 64 5C 45 4C A2 3C 83 2C E0 1C C1 0C 1F
+R 00 00 00 17
+T 00 01 E1 EF 3E FF 5D CF 7C DF 9B AF BA BF D9 8F
+R 00 00 00 17
+T 00 01 EE F8 9F 17 6E 36 7E 55 4E 74 5E 93 2E B2
+R 00 00 00 17
+T 00 01 FB 3E D1 0E F0 1E
+R 00 00 00 17
+
+
+M:crcccittmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16msbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc16msbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16_msbtable$0$0 Def000000
+S _crc_crc16_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 05 80 0F 80 0A 00 1B 80 1E 00 14
+R 00 00 00 17
+T 00 00 0D 00 11 80 33 80 36 00 3C 00 39 80 28 00
+R 00 00 00 17
+T 00 00 1A 2D 80 27 80 22 00 63 80 66 00 6C 00 69
+R 00 00 00 17
+T 00 00 27 80 78 00 7D 80 77 80 72 00 50 00 55 80
+R 00 00 00 17
+T 00 00 34 5F 80 5A 00 4B 80 4E 00 44 00 41 80 C3
+R 00 00 00 17
+T 00 00 41 80 C6 00 CC 00 C9 80 D8 00 DD 80 D7 80
+R 00 00 00 17
+T 00 00 4E D2 00 F0 00 F5 80 FF 80 FA 00 EB 80 EE
+R 00 00 00 17
+T 00 00 5B 00 E4 00 E1 80 A0 00 A5 80 AF 80 AA 00
+R 00 00 00 17
+T 00 00 68 BB 80 BE 00 B4 00 B1 80 93 80 96 00 9C
+R 00 00 00 17
+T 00 00 75 00 99 80 88 00 8D 80 87 80 82 00 83 81
+R 00 00 00 17
+T 00 00 82 86 01 8C 01 89 81 98 01 9D 81 97 81 92
+R 00 00 00 17
+T 00 00 8F 01 B0 01 B5 81 BF 81 BA 01 AB 81 AE 01
+R 00 00 00 17
+T 00 00 9C A4 01 A1 81 E0 01 E5 81 EF 81 EA 01 FB
+R 00 00 00 17
+T 00 00 A9 81 FE 01 F4 01 F1 81 D3 81 D6 01 DC 01
+R 00 00 00 17
+T 00 00 B6 D9 81 C8 01 CD 81 C7 81 C2 01 40 01 45
+R 00 00 00 17
+T 00 00 C3 81 4F 81 4A 01 5B 81 5E 01 54 01 51 81
+R 00 00 00 17
+T 00 00 D0 73 81 76 01 7C 01 79 81 68 01 6D 81 67
+R 00 00 00 17
+T 00 00 DD 81 62 01 23 81 26 01 2C 01 29 81 38 01
+R 00 00 00 17
+T 00 00 EA 3D 81 37 81 32 01 10 01 15 81 1F 81 1A
+R 00 00 00 17
+T 00 00 F7 01 0B 81 0E 01 04 01 01 81 03 83 06 03
+R 00 00 00 17
+T 00 01 04 0C 03 09 83 18 03 1D 83 17 83 12 03 30
+R 00 00 00 17
+T 00 01 11 03 35 83 3F 83 3A 03 2B 83 2E 03 24 03
+R 00 00 00 17
+T 00 01 1E 21 83 60 03 65 83 6F 83 6A 03 7B 83 7E
+R 00 00 00 17
+T 00 01 2B 03 74 03 71 83 53 83 56 03 5C 03 59 83
+R 00 00 00 17
+T 00 01 38 48 03 4D 83 47 83 42 03 C0 03 C5 83 CF
+R 00 00 00 17
+T 00 01 45 83 CA 03 DB 83 DE 03 D4 03 D1 83 F3 83
+R 00 00 00 17
+T 00 01 52 F6 03 FC 03 F9 83 E8 03 ED 83 E7 83 E2
+R 00 00 00 17
+T 00 01 5F 03 A3 83 A6 03 AC 03 A9 83 B8 03 BD 83
+R 00 00 00 17
+T 00 01 6C B7 83 B2 03 90 03 95 83 9F 83 9A 03 8B
+R 00 00 00 17
+T 00 01 79 83 8E 03 84 03 81 83 80 02 85 82 8F 82
+R 00 00 00 17
+T 00 01 86 8A 02 9B 82 9E 02 94 02 91 82 B3 82 B6
+R 00 00 00 17
+T 00 01 93 02 BC 02 B9 82 A8 02 AD 82 A7 82 A2 02
+R 00 00 00 17
+T 00 01 A0 E3 82 E6 02 EC 02 E9 82 F8 02 FD 82 F7
+R 00 00 00 17
+T 00 01 AD 82 F2 02 D0 02 D5 82 DF 82 DA 02 CB 82
+R 00 00 00 17
+T 00 01 BA CE 02 C4 02 C1 82 43 82 46 02 4C 02 49
+R 00 00 00 17
+T 00 01 C7 82 58 02 5D 82 57 82 52 02 70 02 75 82
+R 00 00 00 17
+T 00 01 D4 7F 82 7A 02 6B 82 6E 02 64 02 61 82 20
+R 00 00 00 17
+T 00 01 E1 02 25 82 2F 82 2A 02 3B 82 3E 02 34 02
+R 00 00 00 17
+T 00 01 EE 31 82 13 82 16 02 1C 02 19 82 08 02 0D
+R 00 00 00 17
+T 00 01 FB 82 07 82 02 02
+R 00 00 00 17
+
+
+M:crc16msbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16dnpmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc16dnpmsbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S _crc_crc16dnp_msbtable Def000000
+S G$crc_crc16dnp_msbtable$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 65 3D CA 7A AF 47 94 F5 F1 C8 5E
+R 00 00 00 17
+T 00 00 0D 8F 3B B2 4D D6 28 EB 87 AC E2 91 D9 23
+R 00 00 00 17
+T 00 00 1A BC 1E 13 59 76 64 FF 91 9A AC 35 EB 50
+R 00 00 00 17
+T 00 00 27 D6 6B 64 0E 59 A1 1E C4 23 B2 47 D7 7A
+R 00 00 00 17
+T 00 00 34 78 3D 1D 00 26 B2 43 8F EC C8 89 F5 9B
+R 00 00 00 17
+T 00 00 41 1E FE 23 51 64 34 59 0F EB 6A D6 C5 91
+R 00 00 00 17
+T 00 00 4E A0 AC D6 C8 B3 F5 1C B2 79 8F 42 3D 27
+R 00 00 00 17
+T 00 00 5B 00 88 47 ED 7A 64 8F 01 B2 AE F5 CB C8
+R 00 00 00 17
+T 00 00 68 F0 7A 95 47 3A 00 5F 3D 29 59 4C 64 E3
+R 00 00 00 17
+T 00 00 75 23 86 1E BD AC D8 91 77 D6 12 EB 36 3D
+R 00 00 00 17
+T 00 00 82 53 00 FC 47 99 7A A2 C8 C7 F5 68 B2 0D
+R 00 00 00 17
+T 00 00 8F 8F 7B EB 1E D6 B1 91 D4 AC EF 1E 8A 23
+R 00 00 00 17
+T 00 00 9C 25 64 40 59 C9 AC AC 91 03 D6 66 EB 5D
+R 00 00 00 17
+T 00 00 A9 59 38 64 97 23 F2 1E 84 7A E1 47 4E 00
+R 00 00 00 17
+T 00 00 B6 2B 3D 10 8F 75 B2 DA F5 BF C8 AD 23 C8
+R 00 00 00 17
+T 00 00 C3 1E 67 59 02 64 39 D6 5C EB F3 AC 96 91
+R 00 00 00 17
+T 00 00 D0 E0 F5 85 C8 2A 8F 4F B2 74 00 11 3D BE
+R 00 00 00 17
+T 00 00 DD 7A DB 47 52 B2 37 8F 98 C8 FD F5 C6 47
+R 00 00 00 17
+T 00 00 EA A3 7A 0C 3D 69 00 1F 64 7A 59 D5 1E B0
+R 00 00 00 17
+T 00 00 F7 23 8B 91 EE AC 41 EB 24 D6 6C 7A 09 47
+R 00 00 00 17
+T 00 01 04 A6 00 C3 3D F8 8F 9D B2 32 F5 57 C8 21
+R 00 00 00 17
+T 00 01 11 AC 44 91 EB D6 8E EB B5 59 D0 64 7F 23
+R 00 00 00 17
+T 00 01 1E 1A 1E 93 EB F6 D6 59 91 3C AC 07 1E 62
+R 00 00 00 17
+T 00 01 2B 23 CD 64 A8 59 DE 3D BB 00 14 47 71 7A
+R 00 00 00 17
+T 00 01 38 4A C8 2F F5 80 B2 E5 8F F7 64 92 59 3D
+R 00 00 00 17
+T 00 01 45 1E 58 23 63 91 06 AC A9 EB CC D6 BA B2
+R 00 00 00 17
+T 00 01 52 DF 8F 70 C8 15 F5 2E 47 4B 7A E4 3D 81
+R 00 00 00 17
+T 00 01 5F 00 08 F5 6D C8 C2 8F A7 B2 9C 00 F9 3D
+R 00 00 00 17
+T 00 01 6C 56 7A 33 47 45 23 20 1E 8F 59 EA 64 D1
+R 00 00 00 17
+T 00 01 79 D6 B4 EB 1B AC 7E 91 5A 47 3F 7A 90 3D
+R 00 00 00 17
+T 00 01 86 F5 00 CE B2 AB 8F 04 C8 61 F5 17 91 72
+R 00 00 00 17
+T 00 01 93 AC DD EB B8 D6 83 64 E6 59 49 1E 2C 23
+R 00 00 00 17
+T 00 01 A0 A5 D6 C0 EB 6F AC 0A 91 31 23 54 1E FB
+R 00 00 00 17
+T 00 01 AD 59 9E 64 E8 00 8D 3D 22 7A 47 47 7C F5
+R 00 00 00 17
+T 00 01 BA 19 C8 B6 8F D3 B2 C1 59 A4 64 0B 23 6E
+R 00 00 00 17
+T 00 01 C7 1E 55 AC 30 91 9F D6 FA EB 8C 8F E9 B2
+R 00 00 00 17
+T 00 01 D4 46 F5 23 C8 18 7A 7D 47 D2 00 B7 3D 3E
+R 00 00 00 17
+T 00 01 E1 C8 5B F5 F4 B2 91 8F AA 3D CF 00 60 47
+R 00 00 00 17
+T 00 01 EE 05 7A 73 1E 16 23 B9 64 DC 59 E7 EB 82
+R 00 00 00 17
+T 00 01 FB D6 2D 91 48 AC
+R 00 00 00 17
+
+
+M:crc16dnpmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc32table
+
+XH3
+H 1A areas 3 global symbols
+M crc32table
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 400 flags 20 addr 0
+S G$crc_crc32_table$0$0 Def000000
+S _crc_crc32_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 00 00 96 30 07 77 2C 61 0E EE BA
+R 00 00 00 17
+T 00 00 0D 51 09 99 19 C4 6D 07 8F F4 6A 70 35 A5
+R 00 00 00 17
+T 00 00 1A 63 E9 A3 95 64 9E 32 88 DB 0E A4 B8 DC
+R 00 00 00 17
+T 00 00 27 79 1E E9 D5 E0 88 D9 D2 97 2B 4C B6 09
+R 00 00 00 17
+T 00 00 34 BD 7C B1 7E 07 2D B8 E7 91 1D BF 90 64
+R 00 00 00 17
+T 00 00 41 10 B7 1D F2 20 B0 6A 48 71 B9 F3 DE 41
+R 00 00 00 17
+T 00 00 4E BE 84 7D D4 DA 1A EB E4 DD 6D 51 B5 D4
+R 00 00 00 17
+T 00 00 5B F4 C7 85 D3 83 56 98 6C 13 C0 A8 6B 64
+R 00 00 00 17
+T 00 00 68 7A F9 62 FD EC C9 65 8A 4F 5C 01 14 D9
+R 00 00 00 17
+T 00 00 75 6C 06 63 63 3D 0F FA F5 0D 08 8D C8 20
+R 00 00 00 17
+T 00 00 82 6E 3B 5E 10 69 4C E4 41 60 D5 72 71 67
+R 00 00 00 17
+T 00 00 8F A2 D1 E4 03 3C 47 D4 04 4B FD 85 0D D2
+R 00 00 00 17
+T 00 00 9C 6B B5 0A A5 FA A8 B5 35 6C 98 B2 42 D6
+R 00 00 00 17
+T 00 00 A9 C9 BB DB 40 F9 BC AC E3 6C D8 32 75 5C
+R 00 00 00 17
+T 00 00 B6 DF 45 CF 0D D6 DC 59 3D D1 AB AC 30 D9
+R 00 00 00 17
+T 00 00 C3 26 3A 00 DE 51 80 51 D7 C8 16 61 D0 BF
+R 00 00 00 17
+T 00 00 D0 B5 F4 B4 21 23 C4 B3 56 99 95 BA CF 0F
+R 00 00 00 17
+T 00 00 DD A5 BD B8 9E B8 02 28 08 88 05 5F B2 D9
+R 00 00 00 17
+T 00 00 EA 0C C6 24 E9 0B B1 87 7C 6F 2F 11 4C 68
+R 00 00 00 17
+T 00 00 F7 58 AB 1D 61 C1 3D 2D 66 B6 90 41 DC 76
+R 00 00 00 17
+T 00 01 04 06 71 DB 01 BC 20 D2 98 2A 10 D5 EF 89
+R 00 00 00 17
+T 00 01 11 85 B1 71 1F B5 B6 06 A5 E4 BF 9F 33 D4
+R 00 00 00 17
+T 00 01 1E B8 E8 A2 C9 07 78 34 F9 00 0F 8E A8 09
+R 00 00 00 17
+T 00 01 2B 96 18 98 0E E1 BB 0D 6A 7F 2D 3D 6D 08
+R 00 00 00 17
+T 00 01 38 97 6C 64 91 01 5C 63 E6 F4 51 6B 6B 62
+R 00 00 00 17
+T 00 01 45 61 6C 1C D8 30 65 85 4E 00 62 F2 ED 95
+R 00 00 00 17
+T 00 01 52 06 6C 7B A5 01 1B C1 F4 08 82 57 C4 0F
+R 00 00 00 17
+T 00 01 5F F5 C6 D9 B0 65 50 E9 B7 12 EA B8 BE 8B
+R 00 00 00 17
+T 00 01 6C 7C 88 B9 FC DF 1D DD 62 49 2D DA 15 F3
+R 00 00 00 17
+T 00 01 79 7C D3 8C 65 4C D4 FB 58 61 B2 4D CE 51
+R 00 00 00 17
+T 00 01 86 B5 3A 74 00 BC A3 E2 30 BB D4 41 A5 DF
+R 00 00 00 17
+T 00 01 93 4A D7 95 D8 3D 6D C4 D1 A4 FB F4 D6 D3
+R 00 00 00 17
+T 00 01 A0 6A E9 69 43 FC D9 6E 34 46 88 67 AD D0
+R 00 00 00 17
+T 00 01 AD B8 60 DA 73 2D 04 44 E5 1D 03 33 5F 4C
+R 00 00 00 17
+T 00 01 BA 0A AA C9 7C 0D DD 3C 71 05 50 AA 41 02
+R 00 00 00 17
+T 00 01 C7 27 10 10 0B BE 86 20 0C C9 25 B5 68 57
+R 00 00 00 17
+T 00 01 D4 B3 85 6F 20 09 D4 66 B9 9F E4 61 CE 0E
+R 00 00 00 17
+T 00 01 E1 F9 DE 5E 98 C9 D9 29 22 98 D0 B0 B4 A8
+R 00 00 00 17
+T 00 01 EE D7 C7 17 3D B3 59 81 0D B4 2E 3B 5C BD
+R 00 00 00 17
+T 00 01 FB B7 AD 6C BA C0 20 83 B8 ED B6 B3 BF 9A
+R 00 00 00 17
+T 00 02 08 0C E2 B6 03 9A D2 B1 74 39 47 D5 EA AF
+R 00 00 00 17
+T 00 02 15 77 D2 9D 15 26 DB 04 83 16 DC 73 12 0B
+R 00 00 00 17
+T 00 02 22 63 E3 84 3B 64 94 3E 6A 6D 0D A8 5A 6A
+R 00 00 00 17
+T 00 02 2F 7A 0B CF 0E E4 9D FF 09 93 27 AE 00 0A
+R 00 00 00 17
+T 00 02 3C B1 9E 07 7D 44 93 0F F0 D2 A3 08 87 68
+R 00 00 00 17
+T 00 02 49 F2 01 1E FE C2 06 69 5D 57 62 F7 CB 67
+R 00 00 00 17
+T 00 02 56 65 80 71 36 6C 19 E7 06 6B 6E 76 1B D4
+R 00 00 00 17
+T 00 02 63 FE E0 2B D3 89 5A 7A DA 10 CC 4A DD 67
+R 00 00 00 17
+T 00 02 70 6F DF B9 F9 F9 EF BE 8E 43 BE B7 17 D5
+R 00 00 00 17
+T 00 02 7D 8E B0 60 E8 A3 D6 D6 7E 93 D1 A1 C4 C2
+R 00 00 00 17
+T 00 02 8A D8 38 52 F2 DF 4F F1 67 BB D1 67 57 BC
+R 00 00 00 17
+T 00 02 97 A6 DD 06 B5 3F 4B 36 B2 48 DA 2B 0D D8
+R 00 00 00 17
+T 00 02 A4 4C 1B 0A AF F6 4A 03 36 60 7A 04 41 C3
+R 00 00 00 17
+T 00 02 B1 EF 60 DF 55 DF 67 A8 EF 8E 6E 31 79 BE
+R 00 00 00 17
+T 00 02 BE 69 46 8C B3 61 CB 1A 83 66 BC A0 D2 6F
+R 00 00 00 17
+T 00 02 CB 25 36 E2 68 52 95 77 0C CC 03 47 0B BB
+R 00 00 00 17
+T 00 02 D8 B9 16 02 22 2F 26 05 55 BE 3B BA C5 28
+R 00 00 00 17
+T 00 02 E5 0B BD B2 92 5A B4 2B 04 6A B3 5C A7 FF
+R 00 00 00 17
+T 00 02 F2 D7 C2 31 CF D0 B5 8B 9E D9 2C 1D AE DE
+R 00 00 00 17
+T 00 02 FF 5B B0 C2 64 9B 26 F2 63 EC 9C A3 6A 75
+R 00 00 00 17
+T 00 03 0C 0A 93 6D 02 A9 06 09 9C 3F 36 0E EB 85
+R 00 00 00 17
+T 00 03 19 67 07 72 13 57 00 05 82 4A BF 95 14 7A
+R 00 00 00 17
+T 00 03 26 B8 E2 AE 2B B1 7B 38 1B B6 0C 9B 8E D2
+R 00 00 00 17
+T 00 03 33 92 0D BE D5 E5 B7 EF DC 7C 21 DF DB 0B
+R 00 00 00 17
+T 00 03 40 D4 D2 D3 86 42 E2 D4 F1 F8 B3 DD 68 6E
+R 00 00 00 17
+T 00 03 4D 83 DA 1F CD 16 BE 81 5B 26 B9 F6 E1 77
+R 00 00 00 17
+T 00 03 5A B0 6F 77 47 B7 18 E6 5A 08 88 70 6A 0F
+R 00 00 00 17
+T 00 03 67 FF CA 3B 06 66 5C 0B 01 11 FF 9E 65 8F
+R 00 00 00 17
+T 00 03 74 69 AE 62 F8 D3 FF 6B 61 45 CF 6C 16 78
+R 00 00 00 17
+T 00 03 81 E2 0A A0 EE D2 0D D7 54 83 04 4E C2 B3
+R 00 00 00 17
+T 00 03 8E 03 39 61 26 67 A7 F7 16 60 D0 4D 47 69
+R 00 00 00 17
+T 00 03 9B 49 DB 77 6E 3E 4A 6A D1 AE DC 5A D6 D9
+R 00 00 00 17
+T 00 03 A8 66 0B DF 40 F0 3B D8 37 53 AE BC A9 C5
+R 00 00 00 17
+T 00 03 B5 9E BB DE 7F CF B2 47 E9 FF B5 30 1C F2
+R 00 00 00 17
+T 00 03 C2 BD BD 8A C2 BA CA 30 93 B3 53 A6 A3 B4
+R 00 00 00 17
+T 00 03 CF 24 05 36 D0 BA 93 06 D7 CD 29 57 DE 54
+R 00 00 00 17
+T 00 03 DC BF 67 D9 23 2E 7A 66 B3 B8 4A 61 C4 02
+R 00 00 00 17
+T 00 03 E9 1B 68 5D 94 2B 6F 2A 37 BE 0B B4 A1 8E
+R 00 00 00 17
+T 00 03 F6 0C C3 1B DF 05 5A 8D EF 02 2D
+R 00 00 00 17
+
+
+M:crc32table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+
+
+
+
+crc32msbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc32msbtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 400 flags 20 addr 0
+S G$crc_crc32_msbtable$0$0 Def000000
+S _crc_crc32_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 00 00 B7 1D C1 04 6E 3B 82 09 D9
+R 00 00 00 17
+T 00 00 0D 26 43 0D DC 76 04 13 6B 6B C5 17 B2 4D
+R 00 00 00 17
+T 00 00 1A 86 1A 05 50 47 1E B8 ED 08 26 0F F0 C9
+R 00 00 00 17
+T 00 00 27 22 D6 D6 8A 2F 61 CB 4B 2B 64 9B 0C 35
+R 00 00 00 17
+T 00 00 34 D3 86 CD 31 0A A0 8E 3C BD BD 4F 38 70
+R 00 00 00 17
+T 00 00 41 DB 11 4C C7 C6 D0 48 1E E0 93 45 A9 FD
+R 00 00 00 17
+T 00 00 4E 52 41 AC AD 15 5F 1B B0 D4 5B C2 96 97
+R 00 00 00 17
+T 00 00 5B 56 75 8B 56 52 C8 36 19 6A 7F 2B D8 6E
+R 00 00 00 17
+T 00 00 68 A6 0D 9B 63 11 10 5A 67 14 40 1D 79 A3
+R 00 00 00 17
+T 00 00 75 5D DC 7D 7A 7B 9F 70 CD 66 5E 74 E0 B6
+R 00 00 00 17
+T 00 00 82 23 98 57 AB E2 9C 8E 8D A1 91 39 90 60
+R 00 00 00 17
+T 00 00 8F 95 3C C0 27 8B 8B DD E6 8F 52 FB A5 82
+R 00 00 00 17
+T 00 00 9C E5 E6 64 86 58 5B 2B BE EF 46 EA BA 36
+R 00 00 00 17
+T 00 00 A9 60 A9 B7 81 7D 68 B3 84 2D 2F AD 33 30
+R 00 00 00 17
+T 00 00 B6 EE A9 EA 16 AD A4 5D 0B 6C A0 90 6D 32
+R 00 00 00 17
+T 00 00 C3 D4 27 70 F3 D0 FE 56 B0 DD 49 4B 71 D9
+R 00 00 00 17
+T 00 00 D0 4C 1B 36 C7 FB 06 F7 C3 22 20 B4 CE 95
+R 00 00 00 17
+T 00 00 DD 3D 75 CA 28 80 3A F2 9F 9D FB F6 46 BB
+R 00 00 00 17
+T 00 00 EA B8 FB F1 A6 79 FF F4 F6 3E E1 43 EB FF
+R 00 00 00 17
+T 00 00 F7 E5 9A CD BC E8 2D D0 7D EC 77 70 86 34
+R 00 00 00 17
+T 00 01 04 C0 6D 47 30 19 4B 04 3D AE 56 C5 39 AB
+R 00 00 00 17
+T 00 01 11 06 82 27 1C 1B 43 23 C5 3D 00 2E 72 20
+R 00 00 00 17
+T 00 01 1E C1 2A CF 9D 8E 12 78 80 4F 16 A1 A6 0C
+R 00 00 00 17
+T 00 01 2B 1B 16 BB CD 1F 13 EB 8A 01 A4 F6 4B 05
+R 00 00 00 17
+T 00 01 38 7D D0 08 08 CA CD C9 0C 07 AB 97 78 B0
+R 00 00 00 17
+T 00 01 45 B6 56 7C 69 90 15 71 DE 8D D4 75 DB DD
+R 00 00 00 17
+T 00 01 52 93 6B 6C C0 52 6F B5 E6 11 62 02 FB D0
+R 00 00 00 17
+T 00 01 5F 66 BF 46 9F 5E 08 5B 5E 5A D1 7D 1D 57
+R 00 00 00 17
+T 00 01 6C 66 60 DC 53 63 30 9B 4D D4 2D 5A 49 0D
+R 00 00 00 17
+T 00 01 79 0B 19 44 BA 16 D8 40 97 C6 A5 AC 20 DB
+R 00 00 00 17
+T 00 01 86 64 A8 F9 FD 27 A5 4E E0 E6 A1 4B B0 A1
+R 00 00 00 17
+T 00 01 93 BF FC AD 60 BB 25 8B 23 B6 92 96 E2 B2
+R 00 00 00 17
+T 00 01 A0 2F 2B AD 8A 98 36 6C 8E 41 10 2F 83 F6
+R 00 00 00 17
+T 00 01 AD 0D EE 87 F3 5D A9 99 44 40 68 9D 9D 66
+R 00 00 00 17
+T 00 01 BA 2B 90 2A 7B EA 94 E7 1D B4 E0 50 00 75
+R 00 00 00 17
+T 00 01 C7 E4 89 26 36 E9 3E 3B F7 ED 3B 6B B0 F3
+R 00 00 00 17
+T 00 01 D4 8C 76 71 F7 55 50 32 FA E2 4D F3 FE 5F
+R 00 00 00 17
+T 00 01 E1 F0 BC C6 E8 ED 7D C2 31 CB 3E CF 86 D6
+R 00 00 00 17
+T 00 01 EE FF CB 83 86 B8 D5 34 9B 79 D1 ED BD 3A
+R 00 00 00 17
+T 00 01 FB DC 5A A0 FB D8 EE E0 0C 69 59 FD CD 6D
+R 00 00 00 17
+T 00 02 08 80 DB 8E 60 37 C6 4F 64 32 96 08 7A 85
+R 00 00 00 17
+T 00 02 15 8B C9 7E 5C AD 8A 73 EB B0 4B 77 56 0D
+R 00 00 00 17
+T 00 02 22 04 4F E1 10 C5 4B 38 36 86 46 8F 2B 47
+R 00 00 00 17
+T 00 02 2F 42 8A 7B 00 5C 3D 66 C1 58 E4 40 82 55
+R 00 00 00 17
+T 00 02 3C 53 5D 43 51 9E 3B 1D 25 29 26 DC 21 F0
+R 00 00 00 17
+T 00 02 49 00 9F 2C 47 1D 5E 28 42 4D 19 36 F5 50
+R 00 00 00 17
+T 00 02 56 D8 32 2C 76 9B 3F 9B 6B 5A 3B 26 D6 15
+R 00 00 00 17
+T 00 02 63 03 91 CB D4 07 48 ED 97 0A FF F0 56 0E
+R 00 00 00 17
+T 00 02 70 FA A0 11 10 4D BD D0 14 94 9B 93 19 23
+R 00 00 00 17
+T 00 02 7D 86 52 1D 0E 56 2F F1 B9 4B EE F5 60 6D
+R 00 00 00 17
+T 00 02 8A AD F8 D7 70 6C FC D2 20 2B E2 65 3D EA
+R 00 00 00 17
+T 00 02 97 E6 BC 1B A9 EB 0B 06 68 EF B6 BB 27 D7
+R 00 00 00 17
+T 00 02 A4 01 A6 E6 D3 D8 80 A5 DE 6F 9D 64 DA 6A
+R 00 00 00 17
+T 00 02 B1 CD 23 C4 DD D0 E2 C0 04 F6 A1 CD B3 EB
+R 00 00 00 17
+T 00 02 BE 60 C9 7E 8D 3E BD C9 90 FF B9 10 B6 BC
+R 00 00 00 17
+T 00 02 CB B4 A7 AB 7D B0 A2 FB 3A AE 15 E6 FB AA
+R 00 00 00 17
+T 00 02 D8 CC C0 B8 A7 7B DD 79 A3 C6 60 36 9B 71
+R 00 00 00 17
+T 00 02 E5 7D F7 9F A8 5B B4 92 1F 46 75 96 1A 16
+R 00 00 00 17
+T 00 02 F2 32 88 AD 0B F3 8C 74 2D B0 81 C3 30 71
+R 00 00 00 17
+T 00 02 FF 85 99 90 8A 5D 2E 8D 4B 59 F7 AB 08 54
+R 00 00 00 17
+T 00 03 0C 40 B6 C9 50 45 E6 8E 4E F2 FB 4F 4A 2B
+R 00 00 00 17
+T 00 03 19 DD 0C 47 9C C0 CD 43 21 7D 82 7B 96 60
+R 00 00 00 17
+T 00 03 26 43 7F 4F 46 00 72 F8 5B C1 76 FD 0B 86
+R 00 00 00 17
+T 00 03 33 68 4A 16 47 6C 93 30 04 61 24 2D C5 65
+R 00 00 00 17
+T 00 03 40 E9 4B 9B 11 5E 56 5A 15 87 70 19 18 30
+R 00 00 00 17
+T 00 03 4D 6D D8 1C 35 3D 9F 02 82 20 5E 06 5B 06
+R 00 00 00 17
+T 00 03 5A 1D 0B EC 1B DC 0F 51 A6 93 37 E6 BB 52
+R 00 00 00 17
+T 00 03 67 33 3F 9D 11 3E 88 80 D0 3A 8D D0 97 24
+R 00 00 00 17
+T 00 03 74 3A CD 56 20 E3 EB 15 2D 54 F6 D4 29 79
+R 00 00 00 17
+T 00 03 81 26 A9 C5 CE 3B 68 C1 17 1D 2B CC A0 00
+R 00 00 00 17
+T 00 03 8E EA C8 A5 50 AD D6 12 4D 6C D2 CB 6B 2F
+R 00 00 00 17
+T 00 03 9B DF 7C 76 EE DB C1 CB A1 E3 76 D6 60 E7
+R 00 00 00 17
+T 00 03 A8 AF F0 23 EA 18 ED E2 EE 1D BD A5 F0 AA
+R 00 00 00 17
+T 00 03 B5 A0 64 F4 73 86 27 F9 C4 9B E6 FD 09 FD
+R 00 00 00 17
+T 00 03 C2 B8 89 BE E0 79 8D 67 C6 3A 80 D0 DB FB
+R 00 00 00 17
+T 00 03 CF 84 D5 8B BC 9A 62 96 7D 9E BB B0 3E 93
+R 00 00 00 17
+T 00 03 DC 0C AD FF 97 B1 10 B0 AF 06 0D 71 AB DF
+R 00 00 00 17
+T 00 03 E9 2B 32 A6 68 36 F3 A2 6D 66 B4 BC DA 7B
+R 00 00 00 17
+T 00 03 F6 75 B8 03 5D 36 B5 B4 40 F7 B1
+R 00 00 00 17
+
+
+M:crc32msbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+
+
+
+
+pn9
+
+;!FILE libmf/pn9.asm
+XH3
+H 1A areas 24 global symbols
+M pn9
+O -mmcs51 --model-small
+S _pn9_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$pn9.c$5$1$63 Def000004
+S C$pn9.c$6$1$63 Def000007
+S C$pn9.c$7$1$63 Def000027
+S C$pn9.c$3$0$0 Def000000
+S G$pn9_advance$0$0 Def000000
+S _pn9_advance Def000000
+S A$pn9$110 Def000000
+S A$pn9$120 Def00000C
+S A$pn9$111 Def000002
+S XG$pn9_advance$0$0 Def000027
+S A$pn9$130 Def00001A
+S A$pn9$121 Def00000E
+S A$pn9$131 Def00001C
+S A$pn9$122 Def000010
+S A$pn9$132 Def00001D
+S A$pn9$123 Def000011
+S A$pn9$114 Def000004
+S A$pn9$142 Def000027
+S A$pn9$133 Def00001E
+S A$pn9$124 Def000013
+S A$pn9$134 Def00001F
+S A$pn9$125 Def000015
+S A$pn9$135 Def000020
+S A$pn9$126 Def000016
+S A$pn9$117 Def000007
+S A$pn9$136 Def000021
+S A$pn9$127 Def000017
+S A$pn9$118 Def000009
+S A$pn9$137 Def000023
+S A$pn9$128 Def000018
+S A$pn9$119 Def00000B
+S A$pn9$138 Def000024
+S A$pn9$129 Def000019
+S A$pn9$139 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 53 07 01 8F 04 7D 00 EE 24
+R 00 00 00 16
+T 00 00 0D 00 00 00 F5 82 EF 34 00 00 00 F5 83 E4
+R 00 00 00 16 F1 03 03 00 00 F1 83 0A 00 00
+T 00 00 16 93 FF E4 CF 25 E0 CF 33 FE EF 6C F5 82
+R 00 00 00 16
+T 00 00 23 EE 6D F5 83 22
+R 00 00 00 16
+
+
+M:pn9
+F:G$pn9_advance$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9.pn9_advance$pn9$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9table
+
+XH3
+H 1A areas 3 global symbols
+M pn9table
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$pn9_table$0$0 Def000000
+S _pn9_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 11 22 33 44 55 66 77 88 99 AA BB CC
+R 00 00 00 17
+T 00 00 0D DD EE FF 10 01 32 23 54 45 76 67 98 89
+R 00 00 00 17
+T 00 00 1A BA AB DC CD FE EF 31 20 13 02 75 64 57
+R 00 00 00 17
+T 00 00 27 46 B9 A8 9B 8A FD EC DF CE 21 30 03 12
+R 00 00 00 17
+T 00 00 34 65 74 47 56 A9 B8 8B 9A ED FC CF DE 62
+R 00 00 00 17
+T 00 00 41 73 40 51 26 37 04 15 EA FB C8 D9 AE BF
+R 00 00 00 17
+T 00 00 4E 8C 9D 72 63 50 41 36 27 14 05 FA EB D8
+R 00 00 00 17
+T 00 00 5B C9 BE AF 9C 8D 53 42 71 60 17 06 35 24
+R 00 00 00 17
+T 00 00 68 DB CA F9 E8 9F 8E BD AC 43 52 61 70 07
+R 00 00 00 17
+T 00 00 75 16 25 34 CB DA E9 F8 8F 9E AD BC C4 D5
+R 00 00 00 17
+T 00 00 82 E6 F7 80 91 A2 B3 4C 5D 6E 7F 08 19 2A
+R 00 00 00 17
+T 00 00 8F 3B D4 C5 F6 E7 90 81 B2 A3 5C 4D 7E 6F
+R 00 00 00 17
+T 00 00 9C 18 09 3A 2B F5 E4 D7 C6 B1 A0 93 82 7D
+R 00 00 00 17
+T 00 00 A9 6C 5F 4E 39 28 1B 0A E5 F4 C7 D6 A1 B0
+R 00 00 00 17
+T 00 00 B6 83 92 6D 7C 4F 5E 29 38 0B 1A A6 B7 84
+R 00 00 00 17
+T 00 00 C3 95 E2 F3 C0 D1 2E 3F 0C 1D 6A 7B 48 59
+R 00 00 00 17
+T 00 00 D0 B6 A7 94 85 F2 E3 D0 C1 3E 2F 1C 0D 7A
+R 00 00 00 17
+T 00 00 DD 6B 58 49 97 86 B5 A4 D3 C2 F1 E0 1F 0E
+R 00 00 00 17
+T 00 00 EA 3D 2C 5B 4A 79 68 87 96 A5 B4 C3 D2 E1
+R 00 00 00 17
+T 00 00 F7 F0 0F 1E 2D 3C 4B 5A 69 78 88 99 AA BB
+R 00 00 00 17
+T 00 01 04 CC DD EE FF 00 11 22 33 44 55 66 77 98
+R 00 00 00 17
+T 00 01 11 89 BA AB DC CD FE EF 10 01 32 23 54 45
+R 00 00 00 17
+T 00 01 1E 76 67 B9 A8 9B 8A FD EC DF CE 31 20 13
+R 00 00 00 17
+T 00 01 2B 02 75 64 57 46 A9 B8 8B 9A ED FC CF DE
+R 00 00 00 17
+T 00 01 38 21 30 03 12 65 74 47 56 EA FB C8 D9 AE
+R 00 00 00 17
+T 00 01 45 BF 8C 9D 62 73 40 51 26 37 04 15 FA EB
+R 00 00 00 17
+T 00 01 52 D8 C9 BE AF 9C 8D 72 63 50 41 36 27 14
+R 00 00 00 17
+T 00 01 5F 05 DB CA F9 E8 9F 8E BD AC 53 42 71 60
+R 00 00 00 17
+T 00 01 6C 17 06 35 24 CB DA E9 F8 8F 9E AD BC 43
+R 00 00 00 17
+T 00 01 79 52 61 70 07 16 25 34 4C 5D 6E 7F 08 19
+R 00 00 00 17
+T 00 01 86 2A 3B C4 D5 E6 F7 80 91 A2 B3 5C 4D 7E
+R 00 00 00 17
+T 00 01 93 6F 18 09 3A 2B D4 C5 F6 E7 90 81 B2 A3
+R 00 00 00 17
+T 00 01 A0 7D 6C 5F 4E 39 28 1B 0A F5 E4 D7 C6 B1
+R 00 00 00 17
+T 00 01 AD A0 93 82 6D 7C 4F 5E 29 38 0B 1A E5 F4
+R 00 00 00 17
+T 00 01 BA C7 D6 A1 B0 83 92 2E 3F 0C 1D 6A 7B 48
+R 00 00 00 17
+T 00 01 C7 59 A6 B7 84 95 E2 F3 C0 D1 3E 2F 1C 0D
+R 00 00 00 17
+T 00 01 D4 7A 6B 58 49 B6 A7 94 85 F2 E3 D0 C1 1F
+R 00 00 00 17
+T 00 01 E1 0E 3D 2C 5B 4A 79 68 97 86 B5 A4 D3 C2
+R 00 00 00 17
+T 00 01 EE F1 E0 0F 1E 2D 3C 4B 5A 69 78 87 96 A5
+R 00 00 00 17
+T 00 01 FB B4 C3 D2 E1 F0
+R 00 00 00 17
+
+
+M:pn9table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+
+
+
+
+pn9bit
+
+;!FILE libmf/pn9bit.asm
+XH3
+H 1A areas 12 global symbols
+M pn9bit
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11 flags 20 addr 0
+S _pn9_advance_bit Def000000
+S C$pn9bit.c$5$0$0 Def000000
+S XG$pn9_advance_bit$0$0 Def000011
+S A$pn9bit$110 Def000009
+S A$pn9bit$112 Def00000A
+S A$pn9bit$113 Def00000C
+S A$pn9bit$114 Def00000D
+S A$pn9bit$105 Def000000
+S A$pn9bit$115 Def00000E
+S A$pn9bit$106 Def000002
+S C$pn9bit.c$20$1$63 Def000000
+S A$pn9bit$116 Def000010
+S A$pn9bit$107 Def000003
+S C$pn9bit.c$21$1$63 Def000011
+S A$pn9bit$108 Def000005
+S A$pn9bit$109 Def000006
+S G$pn9_advance_bit$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 13 E5 82 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A F5 82 E4 33 F5 83 22
+R 00 00 00 16
+
+
+M:pn9bit
+F:G$pn9_advance_bit$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9bit.pn9_advance_bit$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9bits
+
+;!FILE libmf/pn9bits.asm
+XH3
+H 1A areas 21 global symbols
+M pn9bits
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 26 flags 20 addr 0
+S C$pn9bits.c$5$0$0 Def000000
+S XG$pn9_advance_bits$0$0 Def000026
+S A$pn9bits$110 Def000006
+S A$pn9bits$120 Def000011
+S A$pn9bits$111 Def000007
+S A$pn9bits$130 Def00001F
+S A$pn9bits$121 Def000013
+S A$pn9bits$112 Def000008
+S A$pn9bits$131 Def000021
+S A$pn9bits$122 Def000014
+S A$pn9bits$113 Def000009
+S A$pn9bits$132 Def000022
+S A$pn9bits$114 Def00000A
+S A$pn9bits$133 Def000023
+S A$pn9bits$124 Def000016
+S A$pn9bits$115 Def00000B
+S A$pn9bits$106 Def000000
+S A$pn9bits$125 Def000017
+S A$pn9bits$116 Def00000D
+S A$pn9bits$107 Def000002
+S A$pn9bits$135 Def000025
+S A$pn9bits$126 Def00001A
+S A$pn9bits$117 Def00000E
+S A$pn9bits$108 Def000004
+S A$pn9bits$118 Def000010
+S A$pn9bits$109 Def000005
+S G$pn9_advance_bits$0$0 Def000000
+S A$pn9bits$128 Def00001B
+S A$pn9bits$129 Def00001D
+S C$pn9bits.c$36$1$63 Def000000
+S C$pn9bits.c$37$1$63 Def000026
+S _pn9_advance_bits Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 FA 08 E6 FB 4A 60 18
+R 00 00 00 16
+T 00 00 0D EA 60 01 0B
+R 00 00 00 16
+T 00 00 11
+R 00 00 00 16
+T 00 00 11 E5 83 13 E5 82
+R 00 00 00 16
+T 00 00 16
+R 00 00 00 16
+T 00 00 16 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 1B
+R 00 00 00 16
+T 00 00 1B DA F9 DB F7 F5 82 E4 33 F5 83
+R 00 00 00 16
+T 00 00 25
+R 00 00 00 16
+T 00 00 25 22
+R 00 00 00 16
+
+
+M:pn9bits
+F:G$pn9_advance_bits$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9bits.pn9_advance_bits$bits$1$62({2}SI:U),B,1,-4
+S:Lpn9bits.pn9_advance_bits$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9byte
+
+;!FILE libmf/pn9byte.asm
+XH3
+H 1A areas 27 global symbols
+M pn9byte
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$pn9byte.c$5$0$0 Def000000
+S XG$pn9_advance_byte$0$0 Def000034
+S A$pn9byte$110 Def000009
+S A$pn9byte$120 Def000014
+S A$pn9byte$130 Def000022
+S A$pn9byte$121 Def000015
+S A$pn9byte$112 Def00000A
+S A$pn9byte$140 Def00002D
+S A$pn9byte$122 Def000018
+S A$pn9byte$113 Def00000B
+S A$pn9byte$141 Def00002F
+S A$pn9byte$132 Def000023
+S A$pn9byte$114 Def00000E
+S A$pn9byte$105 Def000000
+S A$pn9byte$142 Def000030
+S A$pn9byte$133 Def000024
+S A$pn9byte$124 Def000019
+S A$pn9byte$106 Def000002
+S A$pn9byte$143 Def000031
+S A$pn9byte$134 Def000027
+S A$pn9byte$125 Def00001A
+S A$pn9byte$116 Def00000F
+S A$pn9byte$107 Def000003
+S A$pn9byte$144 Def000033
+S A$pn9byte$126 Def00001D
+S A$pn9byte$117 Def000010
+S A$pn9byte$108 Def000005
+S A$pn9byte$136 Def000028
+S A$pn9byte$118 Def000013
+S A$pn9byte$109 Def000006
+S C$pn9byte.c$41$1$63 Def000000
+S G$pn9_advance_byte$0$0 Def000000
+S A$pn9byte$137 Def000029
+S A$pn9byte$128 Def00001E
+S C$pn9byte.c$42$1$63 Def000034
+S A$pn9byte$138 Def00002C
+S A$pn9byte$129 Def00001F
+S _pn9_advance_byte Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 13 E5 82 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D F5 82 E4 33 F5 83 22
+R 00 00 00 16
+
+
+M:pn9byte
+F:G$pn9_advance_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9byte.pn9_advance_byte$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9buf
+
+;!FILE libmf/pn9buf.asm
+XH3
+H 1A areas BF global symbols
+M pn9buf
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 112 flags 20 addr 0
+S A$pn9buf$298 Def0000E8
+S A$pn9buf$289 Def0000DC
+S A$pn9buf$199 Def00006E
+S G$pn9_buffer$0$0 Def000000
+S C$pn9buf.c$5$0$0 Def000000
+S _pn9_buffer Def000000
+S XG$pn9_buffer$0$0 Def000112
+S C$pn9buf.c$203$1$63 Def000000
+S C$pn9buf.c$204$1$63 Def000112
+S A$pn9buf$200 Def00006F
+S A$pn9buf$110 Def000002
+S A$pn9buf$300 Def0000E9
+S A$pn9buf$210 Def00007B
+S A$pn9buf$201 Def000070
+S A$pn9buf$120 Def00000D
+S A$pn9buf$111 Def000004
+S A$pn9buf$310 Def0000F7
+S A$pn9buf$301 Def0000EA
+S A$pn9buf$211 Def00007E
+S A$pn9buf$202 Def000071
+S A$pn9buf$130 Def000019
+S A$pn9buf$121 Def00000E
+S A$pn9buf$112 Def000005
+S A$pn9buf$320 Def000102
+S A$pn9buf$302 Def0000ED
+S A$pn9buf$230 Def000094
+S A$pn9buf$221 Def000089
+S A$pn9buf$203 Def000074
+S A$pn9buf$140 Def000027
+S A$pn9buf$122 Def00000F
+S A$pn9buf$113 Def000006
+S A$pn9buf$330 Def00010F
+S A$pn9buf$321 Def000103
+S A$pn9buf$312 Def0000F8
+S A$pn9buf$231 Def000097
+S A$pn9buf$222 Def00008A
+S A$pn9buf$213 Def00007F
+S A$pn9buf$150 Def000032
+S A$pn9buf$141 Def000028
+S A$pn9buf$132 Def00001A
+S A$pn9buf$123 Def000010
+S A$pn9buf$114 Def000007
+S A$pn9buf$322 Def000106
+S A$pn9buf$313 Def0000F9
+S A$pn9buf$304 Def0000EE
+S A$pn9buf$250 Def0000AB
+S A$pn9buf$241 Def0000A2
+S A$pn9buf$223 Def00008D
+S A$pn9buf$214 Def000080
+S A$pn9buf$205 Def000075
+S A$pn9buf$160 Def000040
+S A$pn9buf$151 Def000033
+S A$pn9buf$142 Def000029
+S A$pn9buf$133 Def00001D
+S A$pn9buf$124 Def000011
+S A$pn9buf$115 Def000008
+S A$pn9buf$314 Def0000FC
+S A$pn9buf$305 Def0000EF
+S A$pn9buf$251 Def0000AE
+S A$pn9buf$242 Def0000A3
+S A$pn9buf$233 Def000098
+S A$pn9buf$215 Def000083
+S A$pn9buf$206 Def000076
+S A$pn9buf$170 Def00004B
+S A$pn9buf$152 Def000036
+S A$pn9buf$143 Def00002A
+S A$pn9buf$134 Def000020
+S A$pn9buf$125 Def000012
+S A$pn9buf$116 Def000009
+S A$pn9buf$324 Def000107
+S A$pn9buf$306 Def0000F2
+S A$pn9buf$270 Def0000C4
+S A$pn9buf$261 Def0000B9
+S A$pn9buf$243 Def0000A4
+S A$pn9buf$234 Def000099
+S A$pn9buf$225 Def00008E
+S A$pn9buf$207 Def000079
+S A$pn9buf$180 Def000057
+S A$pn9buf$171 Def00004C
+S A$pn9buf$162 Def000041
+S A$pn9buf$144 Def00002B
+S A$pn9buf$135 Def000022
+S A$pn9buf$126 Def000013
+S A$pn9buf$117 Def00000A
+S A$pn9buf$325 Def000108
+S A$pn9buf$316 Def0000FD
+S A$pn9buf$271 Def0000C7
+S A$pn9buf$262 Def0000BA
+S A$pn9buf$253 Def0000AF
+S A$pn9buf$244 Def0000A5
+S A$pn9buf$235 Def00009A
+S A$pn9buf$226 Def00008F
+S A$pn9buf$217 Def000084
+S A$pn9buf$181 Def000058
+S A$pn9buf$172 Def00004F
+S A$pn9buf$163 Def000042
+S A$pn9buf$154 Def000037
+S A$pn9buf$145 Def00002C
+S A$pn9buf$127 Def000014
+S A$pn9buf$118 Def00000B
+S A$pn9buf$109 Def000000
+S A$pn9buf$326 Def000109
+S A$pn9buf$317 Def0000FE
+S A$pn9buf$308 Def0000F3
+S A$pn9buf$290 Def0000DD
+S A$pn9buf$281 Def0000D2
+S A$pn9buf$263 Def0000BD
+S A$pn9buf$254 Def0000B0
+S A$pn9buf$245 Def0000A6
+S A$pn9buf$236 Def00009B
+S A$pn9buf$227 Def000092
+S A$pn9buf$218 Def000085
+S A$pn9buf$209 Def00007A
+S A$pn9buf$191 Def000065
+S A$pn9buf$182 Def000059
+S A$pn9buf$164 Def000045
+S A$pn9buf$155 Def000038
+S A$pn9buf$146 Def00002D
+S A$pn9buf$128 Def000016
+S A$pn9buf$119 Def00000C
+S A$pn9buf$327 Def00010A
+S A$pn9buf$318 Def000101
+S A$pn9buf$309 Def0000F4
+S A$pn9buf$291 Def0000DE
+S A$pn9buf$282 Def0000D3
+S A$pn9buf$273 Def0000C8
+S A$pn9buf$255 Def0000B3
+S A$pn9buf$246 Def0000A7
+S A$pn9buf$237 Def00009C
+S A$pn9buf$219 Def000088
+S A$pn9buf$183 Def00005B
+S A$pn9buf$174 Def000050
+S A$pn9buf$156 Def00003B
+S A$pn9buf$147 Def00002E
+S A$pn9buf$138 Def000025
+S A$pn9buf$129 Def000017
+S A$pn9buf$328 Def00010B
+S A$pn9buf$292 Def0000DF
+S A$pn9buf$283 Def0000D4
+S A$pn9buf$274 Def0000C9
+S A$pn9buf$265 Def0000BE
+S A$pn9buf$247 Def0000A8
+S A$pn9buf$238 Def00009E
+S A$pn9buf$229 Def000093
+S A$pn9buf$193 Def000068
+S A$pn9buf$175 Def000051
+S A$pn9buf$166 Def000046
+S A$pn9buf$148 Def000031
+S A$pn9buf$139 Def000026
+S A$pn9buf$329 Def00010D
+S A$pn9buf$293 Def0000E0
+S A$pn9buf$284 Def0000D5
+S A$pn9buf$275 Def0000CC
+S A$pn9buf$266 Def0000BF
+S A$pn9buf$257 Def0000B4
+S A$pn9buf$248 Def0000A9
+S A$pn9buf$239 Def0000A0
+S A$pn9buf$194 Def000069
+S A$pn9buf$185 Def00005D
+S A$pn9buf$176 Def000054
+S A$pn9buf$167 Def000047
+S A$pn9buf$158 Def00003C
+S A$pn9buf$294 Def0000E3
+S A$pn9buf$285 Def0000D6
+S A$pn9buf$267 Def0000C2
+S A$pn9buf$258 Def0000B5
+S A$pn9buf$249 Def0000AA
+S A$pn9buf$195 Def00006A
+S A$pn9buf$186 Def00005F
+S A$pn9buf$168 Def00004A
+S A$pn9buf$159 Def00003D
+S A$pn9buf$286 Def0000D8
+S A$pn9buf$277 Def0000CD
+S A$pn9buf$259 Def0000B8
+S A$pn9buf$196 Def00006B
+S A$pn9buf$187 Def000061
+S A$pn9buf$178 Def000055
+S A$pn9buf$296 Def0000E4
+S A$pn9buf$287 Def0000DA
+S A$pn9buf$278 Def0000CE
+S A$pn9buf$269 Def0000C3
+S A$pn9buf$197 Def00006C
+S A$pn9buf$179 Def000056
+S A$pn9buf$297 Def0000E5
+S A$pn9buf$279 Def0000D1
+S A$pn9buf$198 Def00006D
+S A$pn9buf$189 Def000062
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FA F8 E6 FF 08 E6 FC 08 E6 FD
+R 00 00 00 16
+T 00 00 0D 08 E6 FA 08 E6 FB 4A 60 47 EA 60 01 0B
+R 00 00 00 16
+T 00 00 1A
+R 00 00 00 16
+T 00 00 1A 20 00 00 00 45 30 00 00 00 45 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
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+R 00 00 00 16 F1 23 03 00 01
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+T 00 00 25 E6 6C 6F F6 08 ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
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+T 00 00 5D 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 02 00 DC
+R 00 00 00 16 00 04 00 16
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+T 00 00 65 02 00 A2
+R 00 00 00 16 00 04 00 16
+T 00 00 68
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+R 00 00 00 16
+T 00 00 7A
+R 00 00 00 16
+T 00 00 7A 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 7F
+R 00 00 00 16
+T 00 00 7F 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 8E
+R 00 00 00 16
+T 00 00 8E 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 93
+R 00 00 00 16
+T 00 00 93 13 30 E4 01 B3
+R 00 00 00 16
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+T 00 00 98 FC E4 33 FD DA CA DB C8 80 BB
+R 00 00 00 16
+T 00 00 A2
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+T 00 00 A2 E0 6C 6F F0 A3 ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 AF
+R 00 00 00 16
+T 00 00 AF 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 BE
+R 00 00 00 16
+T 00 00 BE 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 C3
+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 CD 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 D2
+R 00 00 00 16
+T 00 00 D2 FC E4 33 FD DA CA DB C8 80 81
+R 00 00 00 16
+T 00 00 DC
+R 00 00 00 16
+T 00 00 DC ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 E4 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 E9
+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 F3
+R 00 00 00 16
+T 00 00 F3 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 F8
+R 00 00 00 16
+T 00 00 F8 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 FD
+R 00 00 00 16
+T 00 00 FD 13 30 E4 01 B3
+R 00 00 00 16
+T 00 01 02
+R 00 00 00 16
+T 00 01 02 13 30 E4 01 B3
+R 00 00 00 16
+T 00 01 07
+R 00 00 00 16
+T 00 01 07 FC E4 33 FD DA CF DB CD 02 00 5D
+R 00 00 00 16 00 0C 00 16
+
+
+M:pn9buf
+F:G$pn9_buffer$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9buf.pn9_buffer$buflen$1$62({2}SI:U),B,1,-4
+S:Lpn9buf.pn9_buffer$pn9$1$62({2}SI:U),B,1,-6
+S:Lpn9buf.pn9_buffer$xor$1$62({1}SC:U),B,1,-7
+S:Lpn9buf.pn9_buffer$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15advtable
+
+XH3
+H 1A areas 3 global symbols
+M pn15advtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$pn15_adv_table$0$0 Def000000
+S _pn15_adv_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 81 7F 01 7F 80 00 01 7E 80 01 00
+R 00 00 00 17
+T 00 00 0D 01 81 7E 01 7C 80 03 00 03 81 7C 00 02
+R 00 00 00 17
+T 00 00 1A 81 7D 01 7D 80 02 01 78 80 07 00 07 81
+R 00 00 00 17
+T 00 00 27 78 00 06 81 79 01 79 80 06 00 04 81 7B
+R 00 00 00 17
+T 00 00 34 01 7B 80 04 01 7A 80 05 00 05 81 7A 01
+R 00 00 00 17
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+R 00 00 00 17
+T 00 00 4E 80 0E 00 0C 81 73 01 73 80 0C 01 72 80
+R 00 00 00 17
+T 00 00 5B 0D 00 0D 81 72 00 08 81 77 01 77 80 08
+R 00 00 00 17
+T 00 00 68 01 76 80 09 00 09 81 76 01 74 80 0B 00
+R 00 00 00 17
+T 00 00 75 0B 81 74 00 0A 81 75 01 75 80 0A 01 60
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+T 00 00 82 80 1F 00 1F 81 60 00 1E 81 61 01 61 80
+R 00 00 00 17
+T 00 00 8F 1E 00 1C 81 63 01 63 80 1C 01 62 80 1D
+R 00 00 00 17
+T 00 00 9C 00 1D 81 62 00 18 81 67 01 67 80 18 01
+R 00 00 00 17
+T 00 00 A9 66 80 19 00 19 81 66 01 64 80 1B 00 1B
+R 00 00 00 17
+T 00 00 B6 81 64 00 1A 81 65 01 65 80 1A 00 10 81
+R 00 00 00 17
+T 00 00 C3 6F 01 6F 80 10 01 6E 80 11 00 11 81 6E
+R 00 00 00 17
+T 00 00 D0 01 6C 80 13 00 13 81 6C 00 12 81 6D 01
+R 00 00 00 17
+T 00 00 DD 6D 80 12 01 68 80 17 00 17 81 68 00 16
+R 00 00 00 17
+T 00 00 EA 81 69 01 69 80 16 00 14 81 6B 01 6B 80
+R 00 00 00 17
+T 00 00 F7 14 01 6A 80 15 00 15 81 6A 01 40 80 3F
+R 00 00 00 17
+T 00 01 04 00 3F 81 40 00 3E 81 41 01 41 80 3E 00
+R 00 00 00 17
+T 00 01 11 3C 81 43 01 43 80 3C 01 42 80 3D 00 3D
+R 00 00 00 17
+T 00 01 1E 81 42 00 38 81 47 01 47 80 38 01 46 80
+R 00 00 00 17
+T 00 01 2B 39 00 39 81 46 01 44 80 3B 00 3B 81 44
+R 00 00 00 17
+T 00 01 38 00 3A 81 45 01 45 80 3A 00 30 81 4F 01
+R 00 00 00 17
+T 00 01 45 4F 80 30 01 4E 80 31 00 31 81 4E 01 4C
+R 00 00 00 17
+T 00 01 52 80 33 00 33 81 4C 00 32 81 4D 01 4D 80
+R 00 00 00 17
+T 00 01 5F 32 01 48 80 37 00 37 81 48 00 36 81 49
+R 00 00 00 17
+T 00 01 6C 01 49 80 36 00 34 81 4B 01 4B 80 34 01
+R 00 00 00 17
+T 00 01 79 4A 80 35 00 35 81 4A 00 20 81 5F 01 5F
+R 00 00 00 17
+T 00 01 86 80 20 01 5E 80 21 00 21 81 5E 01 5C 80
+R 00 00 00 17
+T 00 01 93 23 00 23 81 5C 00 22 81 5D 01 5D 80 22
+R 00 00 00 17
+T 00 01 A0 01 58 80 27 00 27 81 58 00 26 81 59 01
+R 00 00 00 17
+T 00 01 AD 59 80 26 00 24 81 5B 01 5B 80 24 01 5A
+R 00 00 00 17
+T 00 01 BA 80 25 00 25 81 5A 01 50 80 2F 00 2F 81
+R 00 00 00 17
+T 00 01 C7 50 00 2E 81 51 01 51 80 2E 00 2C 81 53
+R 00 00 00 17
+T 00 01 D4 01 53 80 2C 01 52 80 2D 00 2D 81 52 00
+R 00 00 00 17
+T 00 01 E1 28 81 57 01 57 80 28 01 56 80 29 00 29
+R 00 00 00 17
+T 00 01 EE 81 56 01 54 80 2B 00 2B 81 54 00 2A 81
+R 00 00 00 17
+T 00 01 FB 55 01 55 80 2A
+R 00 00 00 17
+
+
+M:pn15advtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+pn15outtable
+
+XH3
+H 1A areas 3 global symbols
+M pn15outtable
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _pn15_out_table Def000000
+S G$pn15_out_table$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 FF FE 01 FC 03 02 FD F8 07 06 F9 04
+R 00 00 00 17
+T 00 00 0D FB FA 05 F0 0F 0E F1 0C F3 F2 0D 08 F7
+R 00 00 00 17
+T 00 00 1A F6 09 F4 0B 0A F5 E0 1F 1E E1 1C E3 E2
+R 00 00 00 17
+T 00 00 27 1D 18 E7 E6 19 E4 1B 1A E5 10 EF EE 11
+R 00 00 00 17
+T 00 00 34 EC 13 12 ED E8 17 16 E9 14 EB EA 15 C0
+R 00 00 00 17
+T 00 00 41 3F 3E C1 3C C3 C2 3D 38 C7 C6 39 C4 3B
+R 00 00 00 17
+T 00 00 4E 3A C5 30 CF CE 31 CC 33 32 CD C8 37 36
+R 00 00 00 17
+T 00 00 5B C9 34 CB CA 35 20 DF DE 21 DC 23 22 DD
+R 00 00 00 17
+T 00 00 68 D8 27 26 D9 24 DB DA 25 D0 2F 2E D1 2C
+R 00 00 00 17
+T 00 00 75 D3 D2 2D 28 D7 D6 29 D4 2B 2A D5 80 7F
+R 00 00 00 17
+T 00 00 82 7E 81 7C 83 82 7D 78 87 86 79 84 7B 7A
+R 00 00 00 17
+T 00 00 8F 85 70 8F 8E 71 8C 73 72 8D 88 77 76 89
+R 00 00 00 17
+T 00 00 9C 74 8B 8A 75 60 9F 9E 61 9C 63 62 9D 98
+R 00 00 00 17
+T 00 00 A9 67 66 99 64 9B 9A 65 90 6F 6E 91 6C 93
+R 00 00 00 17
+T 00 00 B6 92 6D 68 97 96 69 94 6B 6A 95 40 BF BE
+R 00 00 00 17
+T 00 00 C3 41 BC 43 42 BD B8 47 46 B9 44 BB BA 45
+R 00 00 00 17
+T 00 00 D0 B0 4F 4E B1 4C B3 B2 4D 48 B7 B6 49 B4
+R 00 00 00 17
+T 00 00 DD 4B 4A B5 A0 5F 5E A1 5C A3 A2 5D 58 A7
+R 00 00 00 17
+T 00 00 EA A6 59 A4 5B 5A A5 50 AF AE 51 AC 53 52
+R 00 00 00 17
+T 00 00 F7 AD A8 57 56 A9 54 AB AA 55
+R 00 00 00 17
+
+
+M:pn15outtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15adv
+
+;!FILE libmf/pn15adv.asm
+XH3
+H 1A areas 28 global symbols
+M pn15adv
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S _pn15_adv_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2B flags 20 addr 0
+S G$pn15_advance$0$0 Def000000
+S _pn15_advance Def000000
+S A$pn15adv$110 Def000000
+S A$pn15adv$120 Def00000B
+S A$pn15adv$111 Def000002
+S A$pn15adv$130 Def000019
+S A$pn15adv$121 Def00000C
+S A$pn15adv$140 Def000024
+S A$pn15adv$131 Def00001B
+S A$pn15adv$122 Def00000E
+S A$pn15adv$141 Def000026
+S A$pn15adv$132 Def00001C
+S A$pn15adv$123 Def00000F
+S A$pn15adv$114 Def000004
+S A$pn15adv$142 Def000027
+S A$pn15adv$133 Def00001D
+S A$pn15adv$124 Def000010
+S A$pn15adv$143 Def000028
+S A$pn15adv$134 Def00001E
+S A$pn15adv$125 Def000011
+S XG$pn15_advance$0$0 Def00002A
+S A$pn15adv$135 Def00001F
+S A$pn15adv$126 Def000012
+S A$pn15adv$117 Def000007
+S A$pn15adv$136 Def000020
+S A$pn15adv$127 Def000014
+S A$pn15adv$118 Def000009
+S A$pn15adv$146 Def00002A
+S A$pn15adv$137 Def000021
+S A$pn15adv$128 Def000016
+S A$pn15adv$119 Def00000A
+S A$pn15adv$138 Def000022
+S A$pn15adv$129 Def000017
+S A$pn15adv$139 Def000023
+S C$pn15adv.c$5$1$63 Def000004
+S C$pn15adv.c$6$1$63 Def000007
+S C$pn15adv.c$7$1$63 Def00002A
+S C$pn15adv.c$3$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 53 07 7F 8F 04 E4 FD CE 25
+R 00 00 00 16
+T 00 00 0D E0 CE 33 FF EE 24 00 00 00 F5 82 EF 34
+R 00 00 00 16 F1 03 09 00 01
+T 00 00 18 00 00 00 F5 83 E4 93 FE A3 E4 93 FF EE
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 23 6C F5 82 EF 6D F5 83 22
+R 00 00 00 16
+
+
+M:pn15adv
+F:G$pn15_advance$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn15adv.pn15_advance$pn15$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15out
+
+;!FILE libmf/pn15out.asm
+XH3
+H 1A areas 14 global symbols
+M pn15out
+O -mmcs51 --model-small
+S _pn15_out_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13 flags 20 addr 0
+S A$pn15out$119 Def00000C
+S C$pn15out.c$5$1$63 Def000002
+S C$pn15out.c$6$1$63 Def000010
+S C$pn15out.c$3$0$0 Def000000
+S G$pn15_output$0$0 Def000000
+S _pn15_output Def000000
+S A$pn15out$110 Def000000
+S A$pn15out$120 Def00000E
+S A$pn15out$121 Def00000F
+S A$pn15out$113 Def000002
+S A$pn15out$114 Def000004
+S A$pn15out$124 Def000010
+S A$pn15out$115 Def000005
+S A$pn15out$125 Def000012
+S A$pn15out$116 Def000007
+S A$pn15out$117 Def000009
+S A$pn15out$118 Def00000A
+S XG$pn15_output$0$0 Def000010
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 7F 00 EE 24 00 00 00 F5 82 EF 34
+R 00 00 00 16 F1 03 09 00 00
+T 00 00 0B 00 00 00 F5 83 E4 93 F5 82 22
+R 00 00 00 16 F1 83 03 00 00
+
+
+M:pn15out
+F:G$pn15_output$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lpn15out.pn15_output$pn15$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+rev8
+
+;!FILE libmf/rev8.asm
+XH3
+H 1A areas 2A global symbols
+M rev8
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2E flags 20 addr 0
+S G$rev8$0$0 Def000000
+S A$rev8$120 Def00000C
+S A$rev8$130 Def000018
+S A$rev8$121 Def00000E
+S A$rev8$112 Def000000
+S A$rev8$140 Def000022
+S A$rev8$131 Def000019
+S A$rev8$113 Def000002
+S A$rev8$150 Def00002B
+S A$rev8$141 Def000023
+S A$rev8$132 Def00001A
+S A$rev8$114 Def000003
+S _rev8 Def000000
+S A$rev8$151 Def00002D
+S A$rev8$142 Def000026
+S A$rev8$133 Def00001C
+S A$rev8$124 Def00000F
+S A$rev8$115 Def000004
+S A$rev8$143 Def000027
+S A$rev8$134 Def00001E
+S A$rev8$125 Def000010
+S A$rev8$116 Def000006
+S A$rev8$144 Def000028
+S A$rev8$126 Def000011
+S A$rev8$117 Def000007
+S A$rev8$145 Def00002A
+S A$rev8$127 Def000012
+S A$rev8$118 Def00000A
+S A$rev8$137 Def00001F
+S A$rev8$128 Def000014
+S A$rev8$119 Def00000B
+S A$rev8$138 Def000020
+S A$rev8$129 Def000015
+S A$rev8$139 Def000021
+S XG$rev8$0$0 Def00002B
+S C$rev8.c$5$1$28 Def000000
+S C$rev8.c$6$1$28 Def00000F
+S C$rev8.c$7$1$28 Def00001F
+S C$rev8.c$8$1$28 Def00002B
+S C$rev8.c$3$0$0 Def000000
+S C$rev8.c$9$1$28 Def00002B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF C4 54 0F FE 53 06 0F EF C4 54
+R 00 00 00 16
+T 00 00 0D F0 4E FF 03 03 54 3F FE 53 06 33 EF 2F
+R 00 00 00 16
+T 00 00 1A 25 E0 54 CC 4E FF C3 13 FE 53 06 55 EF
+R 00 00 00 16
+T 00 00 27 2F 54 AA 4E F5 82 22
+R 00 00 00 16
+
+
+M:rev8
+F:G$rev8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lrev8.rev8$x$1$27({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight8
+
+;!FILE libmf/hweight8.asm
+XH3
+H 1A areas 1C global symbols
+M hweight8
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$hweight8$110 Def000007
+S A$hweight8$120 Def000019
+S A$hweight8$111 Def000009
+S A$hweight8$121 Def00001B
+S A$hweight8$112 Def00000B
+S A$hweight8$122 Def00001D
+S A$hweight8$113 Def00000D
+S A$hweight8$123 Def00001E
+S A$hweight8$114 Def00000F
+S _hweight8 Def000000
+S A$hweight8$124 Def000020
+S A$hweight8$115 Def000011
+S A$hweight8$106 Def000000
+S A$hweight8$125 Def000022
+S A$hweight8$116 Def000012
+S A$hweight8$107 Def000002
+S A$hweight8$126 Def000024
+S A$hweight8$117 Def000013
+S A$hweight8$108 Def000004
+S C$hweight8.c$30$1$28 Def000000
+S A$hweight8$118 Def000015
+S A$hweight8$109 Def000006
+S C$hweight8.c$31$1$28 Def000025
+S A$hweight8$119 Def000017
+S XG$hweight8$0$0 Def000025
+S C$hweight8.c$5$0$0 Def000000
+S G$hweight8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 54 55 C5 82 03 54 55 25 82 F5 82
+R 00 00 00 16
+T 00 00 0D 54 33 C5 82 03 03 54 33 25 82 F5 82 54
+R 00 00 00 16
+T 00 00 1A 0F C5 82 C4 54 0F 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight8
+F:G$hweight8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight8.hweight8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight16
+
+;!FILE libmf/hweight16.asm
+XH3
+H 1A areas 11 global symbols
+M hweight16
+O -mmcs51 --model-small
+S _hweight8 Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13 flags 20 addr 0
+S C$hweight16.c$19$1$28 Def000013
+S XG$hweight16$0$0 Def000013
+S C$hweight16.c$5$0$0 Def000000
+S G$hweight16$0$0 Def000000
+S A$hweight16$110 Def000009
+S A$hweight16$111 Def00000C
+S A$hweight16$112 Def00000E
+S A$hweight16$113 Def000010
+S A$hweight16$114 Def000012
+S _hweight16 Def000000
+S A$hweight16$106 Def000000
+S A$hweight16$107 Def000003
+S A$hweight16$108 Def000005
+S A$hweight16$109 Def000007
+S C$hweight16.c$18$1$28 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 12 00 00 E5 82 C5 83 F5 82 12 00 00 E5
+R 00 00 00 16 02 04 00 00 02 0D 00 00
+T 00 00 0D 83 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight16
+F:G$hweight16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight16.hweight16$x$1$27({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight32
+
+;!FILE libmf/hweight32.asm
+XH3
+H 1A areas 17 global symbols
+M hweight32
+O -mmcs51 --model-small
+S _hweight8 Ref000000
+S .__.ABS. Def000000
+S _hweight16 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1F flags 20 addr 0
+S XG$hweight32$0$0 Def00001F
+S C$hweight32.c$5$0$0 Def000000
+S G$hweight32$0$0 Def000000
+S A$hweight32$110 Def000009
+S A$hweight32$111 Def00000C
+S A$hweight32$112 Def00000E
+S A$hweight32$113 Def000010
+S A$hweight32$114 Def000012
+S _hweight32 Def000000
+S A$hweight32$115 Def000015
+S A$hweight32$106 Def000000
+S A$hweight32$116 Def000018
+S A$hweight32$107 Def000002
+S A$hweight32$117 Def00001A
+S A$hweight32$108 Def000005
+S A$hweight32$118 Def00001C
+S A$hweight32$109 Def000007
+S A$hweight32$119 Def00001E
+S C$hweight32.c$23$1$28 Def000000
+S C$hweight32.c$24$1$28 Def00001F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 E0 12 00 00 F5 83 D0 82 12 00 00 E5
+R 00 00 00 16 02 06 00 02 02 0D 00 00
+T 00 00 0D 83 25 82 F5 83 85 F0 82 12 00 00 E5 83
+R 00 00 00 16 02 0C 00 00
+T 00 00 1A 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight32
+F:G$hweight32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight32.hweight32$x$1$27({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext12
+
+;!FILE libmf/signext12.asm
+XH3
+H 1A areas 13 global symbols
+M signext12
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 14 flags 20 addr 0
+S A$signext12$110 Def000008
+S A$signext12$111 Def000009
+S A$signext12$112 Def00000A
+S A$signext12$113 Def00000C
+S A$signext12$114 Def00000E
+S A$signext12$115 Def00000F
+S A$signext12$106 Def000000
+S A$signext12$116 Def000011
+S A$signext12$107 Def000002
+S A$signext12$117 Def000013
+S A$signext12$108 Def000004
+S XG$signextend12$0$0 Def000014
+S C$signext12.c$21$1$28 Def000000
+S A$signext12$109 Def000006
+S C$signext12.c$22$1$28 Def000014
+S C$signext12.c$5$0$0 Def000000
+S G$signextend12$0$0 Def000000
+S _signextend12 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F F5 83 54 08 F4 04 45 83 F5
+R 00 00 00 16
+T 00 00 0D 83 33 95 E0 F5 F0 22
+R 00 00 00 16
+
+
+M:signext12
+F:G$signextend12$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext12.signextend12$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext16
+
+;!FILE libmf/signext16.asm
+XH3
+H 1A areas C global symbols
+M signext16
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 8 flags 20 addr 0
+S A$signext16$110 Def000007
+S A$signext16$106 Def000000
+S A$signext16$107 Def000002
+S A$signext16$108 Def000003
+S XG$signextend16$0$0 Def000008
+S A$signext16$109 Def000005
+S C$signext16.c$14$1$28 Def000000
+S C$signext16.c$15$1$28 Def000008
+S C$signext16.c$5$0$0 Def000000
+S G$signextend16$0$0 Def000000
+S _signextend16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 33 95 E0 F5 F0 22
+R 00 00 00 16
+
+
+M:signext16
+F:G$signextend16$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext16.signextend16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext20
+
+;!FILE libmf/signext20.asm
+XH3
+H 1A areas 12 global symbols
+M signext20
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 12 flags 20 addr 0
+S A$signext20$111 Def000009
+S A$signext20$112 Def00000A
+S A$signext20$113 Def00000C
+S A$signext20$114 Def00000E
+S A$signext20$115 Def00000F
+S A$signext20$106 Def000000
+S A$signext20$116 Def000011
+S A$signext20$107 Def000002
+S C$signext20.c$20$1$28 Def000000
+S A$signext20$108 Def000004
+S XG$signextend20$0$0 Def000012
+S C$signext20.c$21$1$28 Def000012
+S A$signext20$109 Def000006
+S C$signext20.c$5$0$0 Def000000
+S G$signextend20$0$0 Def000000
+S _signextend20 Def000000
+S A$signext20$110 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 F0 54 0F F5 F0 54 08 F4 04 45 F0 F5
+R 00 00 00 16
+T 00 00 0D F0 33 95 E0 22
+R 00 00 00 16
+
+
+M:signext20
+F:G$signextend20$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext20.signextend20$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext24
+
+;!FILE libmf/signext24.asm
+XH3
+H 1A areas B global symbols
+M signext24
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 6 flags 20 addr 0
+S A$signext24$106 Def000000
+S A$signext24$107 Def000002
+S A$signext24$108 Def000003
+S XG$signextend24$0$0 Def000006
+S A$signext24$109 Def000005
+S C$signext24.c$13$1$28 Def000000
+S C$signext24.c$14$1$28 Def000006
+S C$signext24.c$5$0$0 Def000000
+S G$signextend24$0$0 Def000000
+S _signextend24 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 F0 33 95 E0 22
+R 00 00 00 16
+
+
+M:signext24
+F:G$signextend24$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext24.signextend24$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+chksgnlim16
+
+;!FILE libmf/chksgnlim16.asm
+XH3
+H 1A areas 20 global symbols
+M chksgnlim16
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S A$chksgnlim16$120 Def00000C
+S A$chksgnlim16$130 Def00001A
+S A$chksgnlim16$121 Def00000E
+S A$chksgnlim16$140 Def000026
+S A$chksgnlim16$131 Def00001B
+S A$chksgnlim16$122 Def00000F
+S A$chksgnlim16$132 Def00001C
+S A$chksgnlim16$123 Def000010
+S A$chksgnlim16$114 Def000000
+S A$chksgnlim16$133 Def00001E
+S A$chksgnlim16$124 Def000012
+S A$chksgnlim16$115 Def000002
+S A$chksgnlim16$125 Def000013
+S A$chksgnlim16$116 Def000004
+S A$chksgnlim16$135 Def00001F
+S A$chksgnlim16$126 Def000015
+S A$chksgnlim16$117 Def000006
+S A$chksgnlim16$136 Def000020
+S A$chksgnlim16$118 Def000007
+S A$chksgnlim16$137 Def000021
+S A$chksgnlim16$128 Def000017
+S A$chksgnlim16$119 Def000009
+S A$chksgnlim16$138 Def000022
+S A$chksgnlim16$129 Def000018
+S C$chksgnlim16.c$42$1$28 Def000000
+S A$chksgnlim16$139 Def000024
+S C$chksgnlim16.c$43$1$28 Def000027
+S G$checksignedlimit16$0$0 Def000000
+S _checksignedlimit16 Def000000
+S C$chksgnlim16.c$5$0$0 Def000000
+S XG$checksignedlimit16$0$0 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 E5 81 24 FC F8 E5 83 30 E7 0B E5
+R 00 00 00 16
+T 00 00 0D 82 26 08 E5 83 36 64 80 80 08
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 D3 E5 82 96 08 E5 83 96
+R 00 00 00 16
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F 33 E4 33 F5 82 D0 00 22
+R 00 00 00 16
+
+
+M:chksgnlim16
+F:G$checksignedlimit16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lchksgnlim16.checksignedlimit16$lim$1$27({2}SI:S),B,1,-4
+S:Lchksgnlim16.checksignedlimit16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sgnlim16
+
+;!FILE libmf/sgnlim16.asm
+XH3
+H 1A areas 2B global symbols
+M sgnlim16
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 37 flags 20 addr 0
+S A$sgnlim16$120 Def00000C
+S A$sgnlim16$130 Def00001A
+S A$sgnlim16$121 Def00000E
+S A$sgnlim16$140 Def000026
+S A$sgnlim16$131 Def00001B
+S A$sgnlim16$122 Def00000F
+S A$sgnlim16$141 Def000028
+S A$sgnlim16$132 Def00001D
+S A$sgnlim16$123 Def000010
+S A$sgnlim16$114 Def000000
+S A$sgnlim16$151 Def000034
+S A$sgnlim16$142 Def000029
+S A$sgnlim16$133 Def00001E
+S A$sgnlim16$124 Def000012
+S A$sgnlim16$115 Def000002
+S A$sgnlim16$152 Def000036
+S A$sgnlim16$143 Def00002C
+S A$sgnlim16$134 Def00001F
+S A$sgnlim16$125 Def000013
+S A$sgnlim16$116 Def000004
+S A$sgnlim16$144 Def00002D
+S A$sgnlim16$126 Def000016
+S A$sgnlim16$117 Def000006
+S G$signedlimit16$0$0 Def000000
+S A$sgnlim16$145 Def00002E
+S A$sgnlim16$136 Def000021
+S A$sgnlim16$127 Def000017
+S A$sgnlim16$118 Def000007
+S A$sgnlim16$146 Def00002F
+S A$sgnlim16$137 Def000022
+S A$sgnlim16$128 Def000018
+S A$sgnlim16$119 Def000009
+S A$sgnlim16$147 Def000031
+S A$sgnlim16$138 Def000024
+S A$sgnlim16$129 Def000019
+S A$sgnlim16$139 Def000025
+S A$sgnlim16$149 Def000032
+S C$sgnlim16.c$53$1$28 Def000000
+S C$sgnlim16.c$54$1$28 Def000037
+S _signedlimit16 Def000000
+S C$sgnlim16.c$5$0$0 Def000000
+S XG$signedlimit16$0$0 Def000037
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 E5 81 24 FC F8 E5 83 30 E7 15 E5
+R 00 00 00 16
+T 00 00 0D 82 26 08 E5 83 36 30 E7 1E 18 C3 E4 96
+R 00 00 00 16
+T 00 00 1A 08 F5 82 E4 96 80 11
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 D3 E5 82 96 08 E5 83 96 20 E7 08 18 E6
+R 00 00 00 16
+T 00 00 2E 08 F5 82 E6
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 F5 83
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 D0 00 22
+R 00 00 00 16
+
+
+M:sgnlim16
+F:G$signedlimit16$0$0({2}DF,SI:S),Z,0,0,0,0,0
+S:Lsgnlim16.signedlimit16$lim$1$27({2}SI:S),B,1,-4
+S:Lsgnlim16.signedlimit16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+chksgnlim32
+
+;!FILE libmf/chksgnlim32.asm
+XH3
+H 1A areas 2F global symbols
+M chksgnlim32
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 39 flags 20 addr 0
+S A$chksgnlim32$120 Def00000A
+S A$chksgnlim32$130 Def000019
+S A$chksgnlim32$121 Def00000B
+S A$chksgnlim32$140 Def000025
+S A$chksgnlim32$131 Def00001A
+S A$chksgnlim32$122 Def00000E
+S A$chksgnlim32$150 Def000030
+S A$chksgnlim32$141 Def000027
+S A$chksgnlim32$132 Def00001B
+S A$chksgnlim32$123 Def000010
+S A$chksgnlim32$114 Def000000
+S A$chksgnlim32$151 Def000031
+S A$chksgnlim32$142 Def000028
+S A$chksgnlim32$133 Def00001C
+S A$chksgnlim32$124 Def000011
+S A$chksgnlim32$115 Def000002
+S A$chksgnlim32$152 Def000032
+S A$chksgnlim32$143 Def000029
+S A$chksgnlim32$134 Def00001E
+S A$chksgnlim32$125 Def000012
+S A$chksgnlim32$116 Def000004
+S A$chksgnlim32$153 Def000034
+S A$chksgnlim32$144 Def00002B
+S A$chksgnlim32$126 Def000014
+S A$chksgnlim32$117 Def000005
+S A$chksgnlim32$154 Def000036
+S A$chksgnlim32$145 Def00002C
+S A$chksgnlim32$136 Def000020
+S A$chksgnlim32$127 Def000015
+S A$chksgnlim32$118 Def000007
+S A$chksgnlim32$155 Def000038
+S A$chksgnlim32$146 Def00002D
+S A$chksgnlim32$137 Def000021
+S A$chksgnlim32$128 Def000016
+S A$chksgnlim32$119 Def000009
+S A$chksgnlim32$147 Def00002E
+S A$chksgnlim32$138 Def000023
+S A$chksgnlim32$129 Def000018
+S A$chksgnlim32$139 Def000024
+S A$chksgnlim32$149 Def00002F
+S G$checksignedlimit32$0$0 Def000000
+S C$chksgnlim32.c$57$1$28 Def000000
+S C$chksgnlim32.c$58$1$28 Def000039
+S _checksignedlimit32 Def000000
+S C$chksgnlim32.c$5$0$0 Def000000
+S XG$checksignedlimit32$0$0 Def000039
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 C0 01 F9 E5 81 24 F9 F8 E9 30 E7
+R 00 00 00 16
+T 00 00 0D 12 E5 82 26 08 E5 83 36 08 E5 F0 36 08
+R 00 00 00 16
+T 00 00 1A E9 36 64 80 80 0F
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 D3 E5 82 96 08 E5 83 96 08 E5 F0 96 08
+R 00 00 00 16
+T 00 00 2D E9 96
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 33 E4 33 F5 82 D0 01 D0 00 22
+R 00 00 00 16
+
+
+M:chksgnlim32
+F:G$checksignedlimit32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lchksgnlim32.checksignedlimit32$lim$1$27({4}SL:S),B,1,-6
+S:Lchksgnlim32.checksignedlimit32$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sgnlim32
+
+;!FILE libmf/sgnlim32.asm
+XH3
+H 1A areas 4D global symbols
+M sgnlim32
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 60 flags 20 addr 0
+S A$sgnlim32$120 Def00000A
+S A$sgnlim32$130 Def000019
+S A$sgnlim32$121 Def00000B
+S A$sgnlim32$140 Def000025
+S A$sgnlim32$131 Def00001A
+S A$sgnlim32$122 Def00000E
+S A$sgnlim32$150 Def000032
+S A$sgnlim32$141 Def000026
+S A$sgnlim32$132 Def00001B
+S A$sgnlim32$123 Def000010
+S A$sgnlim32$114 Def000000
+S A$sgnlim32$160 Def00003E
+S A$sgnlim32$151 Def000033
+S A$sgnlim32$142 Def000028
+S A$sgnlim32$133 Def00001C
+S A$sgnlim32$124 Def000011
+S A$sgnlim32$115 Def000002
+S A$sgnlim32$170 Def00004B
+S A$sgnlim32$161 Def00003F
+S A$sgnlim32$152 Def000034
+S A$sgnlim32$143 Def000029
+S A$sgnlim32$134 Def00001F
+S A$sgnlim32$125 Def000012
+S A$sgnlim32$116 Def000004
+S A$sgnlim32$180 Def000058
+S A$sgnlim32$171 Def00004C
+S A$sgnlim32$162 Def000041
+S A$sgnlim32$144 Def00002A
+S A$sgnlim32$135 Def000020
+S A$sgnlim32$126 Def000014
+S A$sgnlim32$117 Def000005
+S G$signedlimit32$0$0 Def000000
+S A$sgnlim32$172 Def00004D
+S A$sgnlim32$163 Def000042
+S A$sgnlim32$154 Def000036
+S A$sgnlim32$145 Def00002B
+S A$sgnlim32$136 Def000021
+S A$sgnlim32$127 Def000015
+S A$sgnlim32$118 Def000007
+S A$sgnlim32$182 Def00005A
+S A$sgnlim32$173 Def00004F
+S A$sgnlim32$164 Def000043
+S A$sgnlim32$155 Def000037
+S A$sgnlim32$146 Def00002D
+S A$sgnlim32$137 Def000022
+S A$sgnlim32$128 Def000016
+S A$sgnlim32$119 Def000009
+S A$sgnlim32$174 Def000050
+S A$sgnlim32$165 Def000044
+S A$sgnlim32$156 Def000039
+S A$sgnlim32$147 Def00002E
+S A$sgnlim32$138 Def000023
+S A$sgnlim32$129 Def000018
+S A$sgnlim32$184 Def00005B
+S A$sgnlim32$175 Def000051
+S A$sgnlim32$166 Def000045
+S A$sgnlim32$157 Def00003A
+S A$sgnlim32$148 Def00002F
+S A$sgnlim32$139 Def000024
+S A$sgnlim32$185 Def00005D
+S A$sgnlim32$176 Def000053
+S A$sgnlim32$167 Def000048
+S A$sgnlim32$158 Def00003B
+S A$sgnlim32$149 Def000030
+S A$sgnlim32$186 Def00005F
+S A$sgnlim32$177 Def000054
+S A$sgnlim32$168 Def000049
+S A$sgnlim32$159 Def00003D
+S A$sgnlim32$178 Def000055
+S A$sgnlim32$169 Def00004A
+S A$sgnlim32$179 Def000057
+S C$sgnlim32.c$87$1$28 Def000000
+S _signedlimit32 Def000000
+S C$sgnlim32.c$88$1$28 Def000060
+S C$sgnlim32.c$5$0$0 Def000000
+S XG$signedlimit32$0$0 Def000060
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 C0 01 F9 E5 81 24 F9 F8 E9 30 E7
+R 00 00 00 16
+T 00 00 0D 28 E5 82 26 08 E5 83 36 08 E5 F0 36 08
+R 00 00 00 16
+T 00 00 1A E9 36 30 E7 3B 18 18 18 C3 E4 96 08 F5
+R 00 00 00 16
+T 00 00 27 82 E4 96 08 F5 83 E4 96 08 F5 F0 E4 96
+R 00 00 00 16
+T 00 00 34 80 25
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 D3 E5 82 96 08 E5 83 96 08 E5 F0 96 08
+R 00 00 00 16
+T 00 00 43 E9 96 20 E7 12 18 18 18 E6 08 F5 82 E6
+R 00 00 00 16
+T 00 00 50 08 F5 83 E6 08 F5 F0 E6 80 01
+R 00 00 00 16
+T 00 00 5A
+R 00 00 00 16
+T 00 00 5A E9
+R 00 00 00 16
+T 00 00 5B
+R 00 00 00 16
+T 00 00 5B D0 01 D0 00 22
+R 00 00 00 16
+
+
+M:sgnlim32
+F:G$signedlimit32$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsgnlim32.signedlimit32$lim$1$27({4}SL:S),B,1,-6
+S:Lsgnlim32.signedlimit32$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+grayenc8
+
+;!FILE libmf/grayenc8.asm
+XH3
+H 1A areas C global symbols
+M grayenc8
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S A$grayenc8$105 Def000000
+S A$grayenc8$106 Def000002
+S A$grayenc8$107 Def000003
+S A$grayenc8$108 Def000004
+S A$grayenc8$109 Def000006
+S C$grayenc8.c$13$1$28 Def000000
+S C$grayenc8.c$14$1$28 Def000007
+S G$gray_encode8$0$0 Def000000
+S _gray_encode8 Def000000
+S C$grayenc8.c$5$0$0 Def000000
+S XG$gray_encode8$0$0 Def000007
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 C3 13 62 82 22
+R 00 00 00 16
+
+
+M:grayenc8
+F:G$gray_encode8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lgrayenc8.gray_encode8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+graydec8
+
+;!FILE libmf/graydec8.asm
+XH3
+H 1A areas 24 global symbols
+M graydec8
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 32 flags 20 addr 0
+S C$graydec8.c$37$1$28 Def000000
+S C$graydec8.c$38$1$28 Def000032
+S G$gray_decode8$0$0 Def000000
+S _gray_decode8 Def000000
+S C$graydec8.c$5$0$0 Def000000
+S XG$gray_decode8$0$0 Def000032
+S A$graydec8$110 Def000009
+S A$graydec8$120 Def00001A
+S A$graydec8$111 Def00000A
+S A$graydec8$130 Def00002C
+S A$graydec8$121 Def00001C
+S A$graydec8$112 Def00000C
+S A$graydec8$131 Def00002D
+S A$graydec8$122 Def00001E
+S A$graydec8$113 Def00000E
+S A$graydec8$132 Def00002F
+S A$graydec8$123 Def00001F
+S A$graydec8$114 Def000010
+S A$graydec8$105 Def000000
+S A$graydec8$133 Def000031
+S A$graydec8$124 Def000021
+S A$graydec8$115 Def000011
+S A$graydec8$106 Def000002
+S A$graydec8$125 Def000023
+S A$graydec8$116 Def000013
+S A$graydec8$107 Def000003
+S A$graydec8$126 Def000025
+S A$graydec8$117 Def000015
+S A$graydec8$108 Def000005
+S A$graydec8$127 Def000026
+S A$graydec8$118 Def000017
+S A$graydec8$109 Def000007
+S A$graydec8$128 Def000028
+S A$graydec8$119 Def000018
+S A$graydec8$129 Def00002A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 03 54 40 62 82 E5 82 03 54 20 62
+R 00 00 00 16
+T 00 00 0D 82 E5 82 03 54 10 62 82 E5 82 03 54 08
+R 00 00 00 16
+T 00 00 1A 62 82 E5 82 03 54 04 62 82 E5 82 03 54
+R 00 00 00 16
+T 00 00 27 02 62 82 E5 82 03 54 01 62 82 22
+R 00 00 00 16
+
+
+M:graydec8
+F:G$gray_decode8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lgraydec8.gray_decode8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+fmemset
+
+;!FILE libmf/fmemset.asm
+XH3
+H 1A areas 2F1 global symbols
+M fmemset
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S A$fmemset$1221 Def00002F
+S A$fmemset$1203 Def000017
+S A$fmemset$1222 Def000031
+S A$fmemset$1213 Def000026
+S A$fmemset$1204 Def00001A
+S A$fmemset$1223 Def000033
+S A$fmemset$1214 Def000027
+S A$fmemset$1205 Def00001C
+S A$fmemset$1215 Def000028
+S A$fmemset$1216 Def00002A
+S A$fmemset$1207 Def00001F
+S G$fmemset$0$0 Def000000
+S A$fmemset$1217 Def00002C
+S A$fmemset$1208 Def000020
+S A$fmemset$1190 Def00000A
+S A$fmemset$1209 Def000021
+S A$fmemset$1191 Def00000B
+S A$fmemset$1219 Def00002D
+S A$fmemset$1192 Def00000C
+S A$fmemset$1183 Def000000
+S A$fmemset$1193 Def00000E
+S A$fmemset$1184 Def000002
+S A$fmemset$1194 Def00000F
+S A$fmemset$1185 Def000003
+S A$fmemset$1186 Def000004
+S A$fmemset$1196 Def000011
+S A$fmemset$1187 Def000006
+S A$fmemset$1188 Def000007
+S A$fmemset$1198 Def000012
+S A$fmemset$1189 Def000009
+S _fmemset Def000000
+S C$fmemset.c$60$1$28 Def000000
+S C$fmemset.c$10$0$0 Def000000
+S C$fmemset.c$61$1$28 Def000034
+S XG$fmemset$0$0 Def000034
+S A$fmemset$1210 Def000023
+S A$fmemset$1201 Def000013
+S A$fmemset$1220 Def00002E
+S A$fmemset$1211 Def000025
+S A$fmemset$1202 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 86 05 18 86 07 18 E6 FE 70
+R 00 00 00 16
+T 00 00 0D 04 4F 70 02
+R 00 00 00 16
+T 00 00 11
+R 00 00 00 16
+T 00 00 11 22
+R 00 00 00 16
+T 00 00 12
+R 00 00 00 16
+T 00 00 12 0F
+R 00 00 00 16
+T 00 00 13
+R 00 00 00 16
+T 00 00 13 ED 20 F7 FA 30 F6 13 A8 82 20 F5 07
+R 00 00 00 16
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F F6 08 DE FC DF FA 22
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 F2 08 DE FC DF FA 22
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D F0 A3 DE FC DF FA 22
+R 00 00 00 16
+
+
+M:fmemset
+F:G$fmemset$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lfmemset.fmemset$c$1$27({1}SC:S),B,1,-3
+S:Lfmemset.fmemset$n$1$27({2}SI:U),B,1,-5
+S:Lfmemset.fmemset$p$1$27({3}DG,SV:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+fmemcpy
+
+;!FILE libmf/fmemcpy.asm
+XH3
+H 1A areas 35F global symbols
+M fmemcpy
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E6 flags 20 addr 0
+S A$fmemcpy$1320 Def0000C5
+S A$fmemcpy$1302 Def0000AA
+S A$fmemcpy$1230 Def000042
+S A$fmemcpy$1221 Def000038
+S A$fmemcpy$1212 Def000029
+S A$fmemcpy$1330 Def0000D2
+S A$fmemcpy$1321 Def0000C7
+S A$fmemcpy$1312 Def0000B8
+S A$fmemcpy$1303 Def0000AB
+S A$fmemcpy$1240 Def00004F
+S A$fmemcpy$1231 Def000044
+S A$fmemcpy$1222 Def000039
+S A$fmemcpy$1340 Def0000DC
+S A$fmemcpy$1322 Def0000C9
+S A$fmemcpy$1313 Def0000BB
+S A$fmemcpy$1304 Def0000AC
+S A$fmemcpy$1232 Def000046
+S A$fmemcpy$1223 Def00003B
+S A$fmemcpy$1214 Def00002C
+S A$fmemcpy$1205 Def000019
+S A$fmemcpy$1341 Def0000DD
+S A$fmemcpy$1332 Def0000D3
+S A$fmemcpy$1314 Def0000BE
+S A$fmemcpy$1305 Def0000AD
+S A$fmemcpy$1260 Def000069
+S A$fmemcpy$1251 Def00005A
+S A$fmemcpy$1242 Def000050
+S A$fmemcpy$1224 Def00003D
+S A$fmemcpy$1215 Def00002F
+S A$fmemcpy$1206 Def00001A
+S A$fmemcpy$1342 Def0000DE
+S A$fmemcpy$1333 Def0000D4
+S A$fmemcpy$1324 Def0000CA
+S A$fmemcpy$1306 Def0000AF
+S A$fmemcpy$1261 Def00006B
+S A$fmemcpy$1252 Def00005D
+S A$fmemcpy$1243 Def000051
+S A$fmemcpy$1234 Def000047
+S A$fmemcpy$1216 Def000032
+S A$fmemcpy$1207 Def00001D
+S G$fmemcpy$0$0 Def000000
+S A$fmemcpy$1343 Def0000DF
+S A$fmemcpy$1334 Def0000D5
+S A$fmemcpy$1325 Def0000CB
+S A$fmemcpy$1316 Def0000C1
+S A$fmemcpy$1307 Def0000B1
+S A$fmemcpy$1280 Def000085
+S A$fmemcpy$1271 Def000075
+S A$fmemcpy$1253 Def000060
+S A$fmemcpy$1244 Def000052
+S A$fmemcpy$1235 Def000048
+S A$fmemcpy$1226 Def00003E
+S A$fmemcpy$1208 Def000020
+S A$fmemcpy$1190 Def00000A
+S A$fmemcpy$1344 Def0000E0
+S A$fmemcpy$1335 Def0000D6
+S A$fmemcpy$1326 Def0000CC
+S A$fmemcpy$1317 Def0000C2
+S A$fmemcpy$1308 Def0000B3
+S A$fmemcpy$1281 Def000086
+S A$fmemcpy$1272 Def000077
+S A$fmemcpy$1263 Def00006C
+S A$fmemcpy$1245 Def000053
+S A$fmemcpy$1236 Def000049
+S A$fmemcpy$1227 Def00003F
+S A$fmemcpy$1218 Def000035
+S A$fmemcpy$1209 Def000022
+S A$fmemcpy$1191 Def00000C
+S A$fmemcpy$1345 Def0000E1
+S A$fmemcpy$1336 Def0000D7
+S A$fmemcpy$1327 Def0000CD
+S A$fmemcpy$1318 Def0000C3
+S A$fmemcpy$1309 Def0000B5
+S A$fmemcpy$1291 Def000096
+S A$fmemcpy$1282 Def000089
+S A$fmemcpy$1273 Def000079
+S A$fmemcpy$1264 Def00006D
+S A$fmemcpy$1255 Def000063
+S A$fmemcpy$1246 Def000054
+S A$fmemcpy$1237 Def00004A
+S A$fmemcpy$1228 Def000040
+S A$fmemcpy$1219 Def000036
+S A$fmemcpy$1192 Def00000D
+S A$fmemcpy$1183 Def000000
+S A$fmemcpy$1346 Def0000E3
+S A$fmemcpy$1337 Def0000D9
+S A$fmemcpy$1328 Def0000CE
+S A$fmemcpy$1319 Def0000C4
+S A$fmemcpy$1292 Def000098
+S A$fmemcpy$1283 Def00008A
+S A$fmemcpy$1274 Def00007B
+S A$fmemcpy$1265 Def00006E
+S A$fmemcpy$1256 Def000064
+S A$fmemcpy$1247 Def000055
+S A$fmemcpy$1238 Def00004B
+S A$fmemcpy$1229 Def000041
+S A$fmemcpy$1193 Def00000F
+S A$fmemcpy$1184 Def000002
+S A$fmemcpy$1347 Def0000E5
+S A$fmemcpy$1338 Def0000DB
+S A$fmemcpy$1329 Def0000D0
+S A$fmemcpy$1293 Def00009A
+S A$fmemcpy$1284 Def00008B
+S A$fmemcpy$1275 Def00007D
+S A$fmemcpy$1266 Def00006F
+S A$fmemcpy$1257 Def000065
+S A$fmemcpy$1248 Def000057
+S A$fmemcpy$1239 Def00004D
+S A$fmemcpy$1194 Def000010
+S A$fmemcpy$1185 Def000003
+S A$fmemcpy$1294 Def00009C
+S A$fmemcpy$1285 Def00008D
+S A$fmemcpy$1276 Def00007F
+S A$fmemcpy$1267 Def000070
+S A$fmemcpy$1258 Def000066
+S A$fmemcpy$1249 Def000059
+S A$fmemcpy$1195 Def000011
+S A$fmemcpy$1186 Def000004
+S A$fmemcpy$1295 Def00009E
+S A$fmemcpy$1286 Def00008F
+S A$fmemcpy$1268 Def000072
+S A$fmemcpy$1259 Def000067
+S A$fmemcpy$1196 Def000012
+S A$fmemcpy$1187 Def000006
+S A$fmemcpy$1296 Def0000A0
+S A$fmemcpy$1287 Def000091
+S A$fmemcpy$1278 Def000081
+S A$fmemcpy$1269 Def000074
+S A$fmemcpy$1197 Def000014
+S A$fmemcpy$1188 Def000007
+S A$fmemcpy$1288 Def000093
+S A$fmemcpy$1279 Def000084
+S A$fmemcpy$1198 Def000015
+S A$fmemcpy$1189 Def000009
+S C$fmemcpy.c$184$1$28 Def000000
+S A$fmemcpy$1298 Def0000A2
+S A$fmemcpy$1289 Def000095
+S C$fmemcpy.c$185$1$28 Def0000E6
+S A$fmemcpy$1299 Def0000A5
+S _fmemcpy Def000000
+S C$fmemcpy.c$10$0$0 Def000000
+S XG$fmemcpy$0$0 Def0000E6
+S A$fmemcpy$1200 Def000017
+S A$fmemcpy$1300 Def0000A6
+S A$fmemcpy$1210 Def000024
+S A$fmemcpy$1310 Def0000B7
+S A$fmemcpy$1301 Def0000A7
+S A$fmemcpy$1220 Def000037
+S A$fmemcpy$1211 Def000026
+S A$fmemcpy$1202 Def000018
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 86 03 18 86 02 18 86 01 18
+R 00 00 00 16
+T 00 00 0D 86 07 18 E6 FE 70 04 4F 70 02
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 22
+R 00 00 00 16
+T 00 00 18
+R 00 00 00 16
+T 00 00 18 0F
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 EB 20 F7 FA 30 F6 3A A8 82 89 82 8A 83
+R 00 00 00 16
+T 00 00 26 30 F5 03 02 00 B8
+R 00 00 00 16 00 07 00 16
+T 00 00 2C
+R 00 00 00 16
+T 00 00 2C 20 E7 21 30 E6 15 20 E5 09
+R 00 00 00 16
+T 00 00 35
+R 00 00 00 16
+T 00 00 35 E7 09 F6 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E E3 09 F6 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 E0 A3 F6 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 50
+R 00 00 00 16
+T 00 00 50 E4 93 A3 F6 08 DE F9 DF F7 22
+R 00 00 00 16
+T 00 00 5A
+R 00 00 00 16
+T 00 00 5A 20 E7 39 30 E6 15 20 E5 09
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 E7 09 F0 A3 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C E3 09 F0 A3 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 C0 A8 C2 AF C0 84 C0 85 89 84 8A 85
+R 00 00 00 16
+T 00 00 81
+R 00 00 00 16
+T 00 00 81 63 86 01 E0 A3 63 86 01 F0 A3 DE F4 DF
+R 00 00 00 16
+T 00 00 8E F2 D0 85 D0 84 D0 A8 22
+R 00 00 00 16
+T 00 00 96
+R 00 00 00 16
+T 00 00 96 C0 A8 C2 AF C0 84 C0 85 89 84 8A 85
+R 00 00 00 16
+T 00 00 A2
+R 00 00 00 16
+T 00 00 A2 63 86 01 E4 93 63 86 01 A3 F0 A3 DE F3
+R 00 00 00 16
+T 00 00 AF DF F1 D0 85 D0 84 D0 A8 22
+R 00 00 00 16
+T 00 00 B8
+R 00 00 00 16
+T 00 00 B8 20 E7 21 30 E6 15 20 E5 09
+R 00 00 00 16
+T 00 00 C1
+R 00 00 00 16
+T 00 00 C1 E7 09 F2 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 CA
+R 00 00 00 16
+T 00 00 CA E3 09 F2 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 D3
+R 00 00 00 16
+T 00 00 D3 E0 A3 F2 08 DE FA DF F8 22
+R 00 00 00 16
+T 00 00 DC
+R 00 00 00 16
+T 00 00 DC E4 93 A3 F2 08 DE F9 DF F7 22
+R 00 00 00 16
+
+
+M:fmemcpy
+F:G$fmemcpy$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lfmemcpy.fmemcpy$s$1$27({3}DG,SV:S),B,1,-5
+S:Lfmemcpy.fmemcpy$n$1$27({2}SI:U),B,1,-7
+S:Lfmemcpy.fmemcpy$d$1$27({3}DG,SV:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+delay
+
+;!FILE libmf/delay.asm
+XH3
+H 1A areas 11 global symbols
+M delay
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 14 flags 20 addr 0
+S C$delay.c$9$0$0 Def000000
+S G$delay$0$0 Def000000
+S A$delay$110 Def000007
+S A$delay$112 Def000008
+S A$delay$114 Def00000A
+S A$delay$105 Def000000
+S _delay Def000000
+S A$delay$115 Def00000D
+S A$delay$106 Def000002
+S A$delay$116 Def000010
+S A$delay$107 Def000004
+S A$delay$117 Def000013
+S A$delay$109 Def000006
+S C$delay.c$23$1$28 Def000000
+S C$delay.c$24$1$28 Def000014
+S XG$delay$0$0 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 60 02 05 83
+R 00 00 00 16
+T 00 00 06
+R 00 00 00 16
+T 00 00 06 00 00
+R 00 00 00 16
+T 00 00 08
+R 00 00 00 16
+T 00 00 08 74 03
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A D5 E0 FD D5 82 F6 D5 83 F5 22
+R 00 00 00 16
+
+
+M:delay
+F:G$delay$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldelay.delay$us$1$27({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+random
+
+;!FILE libmf/random.asm
+XH3
+H 1A areas 1F global symbols
+M random
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S G$random_seed$0$0 Def000000
+S _random_seed Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2B flags 20 addr 0
+S G$random$0$0 Def000000
+S A$random$120 Def00000C
+S A$random$130 Def000020
+S A$random$121 Def00000E
+S A$random$131 Def000022
+S A$random$122 Def000010
+S A$random$132 Def000024
+S A$random$123 Def000012
+S A$random$114 Def000000
+S _random Def000000
+S A$random$133 Def000027
+S A$random$124 Def000015
+S A$random$115 Def000002
+S A$random$134 Def000029
+S A$random$125 Def000016
+S A$random$116 Def000005
+S A$random$126 Def000018
+S A$random$117 Def000006
+S A$random$127 Def00001A
+S A$random$118 Def000008
+S A$random$137 Def00002A
+S A$random$128 Def00001C
+S A$random$119 Def00000A
+S A$random$129 Def00001F
+S C$random.c$11$0$0 Def000000
+S C$random.c$35$1$28 Def000000
+S C$random.c$36$1$28 Def00002A
+S XG$random$0$0 Def00002A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 00 00 00 75 F0 D5 A4 24 9D F5 82 E5
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 0B F0 34 00 F5 83 E5 00 00 00 75 F0 6F A4
+R 00 00 00 16 F1 21 09 00 05
+T 00 00 16 25 83 F5 83 E5 00 00 01 75 F0 D5 A4 25
+R 00 00 00 16 F1 21 08 00 05
+T 00 00 21 83 F5 83 85 82 00 00 00 F5 00 00 01 22
+R 00 00 00 16 F1 21 08 00 05 F1 21 0C 00 05
+T 00 00 2A 22
+R 00 00 00 16
+
+
+M:random
+F:G$random$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sleep
+
+;!FILE libmf/sleep.asm
+XH3
+H 1A areas 2E3 global symbols
+M sleep
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S XG$enter_sleep$0$0 Def000025
+S G$enter_sleep$0$0 Def000000
+S A$sleep$1180 Def000011
+S A$sleep$1171 Def000000
+S A$sleep$1190 Def000022
+S A$sleep$1181 Def000012
+S A$sleep$1172 Def000003
+S A$sleep$1182 Def000014
+S A$sleep$1173 Def000004
+S A$sleep$1183 Def000015
+S A$sleep$1174 Def000006
+S A$sleep$1184 Def000016
+S A$sleep$1175 Def000007
+S A$sleep$1185 Def000017
+S A$sleep$1176 Def000009
+S A$sleep$1186 Def000019
+S A$sleep$1177 Def00000A
+S A$sleep$1187 Def00001B
+S A$sleep$1178 Def00000C
+S A$sleep$1188 Def00001D
+S A$sleep$1179 Def00000E
+S A$sleep$1189 Def00001F
+S _enter_sleep Def000000
+S C$sleep.c$33$1$28 Def000000
+S C$sleep.c$10$0$0 Def000000
+S C$sleep.c$34$1$28 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 F5 98 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 0C F0 78 FF F6 18 F6 E5 87 54
+R 00 00 00 16
+T 00 00 1A 0C 44 02 F5 87 75 97 D3 02 E0 47
+R 00 00 00 16
+
+
+M:sleep
+F:G$enter_sleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+deepsleep
+
+;!FILE libmf/deepsleep.asm
+XH3
+H 1A areas 2DE global symbols
+M deepsleep
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1C flags 20 addr 0
+S G$enter_deepsleep$0$0 Def000000
+S A$deepsleep$1180 Def000010
+S A$deepsleep$1171 Def000000
+S A$deepsleep$1181 Def000011
+S A$deepsleep$1172 Def000003
+S A$deepsleep$1182 Def000012
+S A$deepsleep$1173 Def000004
+S A$deepsleep$1183 Def000013
+S A$deepsleep$1174 Def000006
+S A$deepsleep$1184 Def000016
+S A$deepsleep$1175 Def000007
+S A$deepsleep$1185 Def000019
+S A$deepsleep$1176 Def000009
+S A$deepsleep$1177 Def00000A
+S A$deepsleep$1178 Def00000D
+S A$deepsleep$1179 Def00000E
+S _enter_deepsleep Def000000
+S C$deepsleep.c$10$0$0 Def000000
+S XG$enter_deepsleep$0$0 Def00001C
+S C$deepsleep.c$28$1$28 Def000000
+S C$deepsleep.c$29$1$28 Def00001C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 90 70 0C
+R 00 00 00 16
+T 00 00 0D F0 78 FF F6 18 F6 75 87 03 75 97 D3 02
+R 00 00 00 16
+T 00 00 1A E0 47
+R 00 00 00 16
+
+
+M:deepsleep
+F:G$enter_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sleepcont
+
+;!FILE libmf/sleepcont.asm
+XH3
+H 1A areas 2F9 global symbols
+M sleepcont
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S __sdcc_external_startup Ref000000
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 1A flags 20 addr 0
+S A$sleepcont$1220 Def000002
+S A$sleepcont$1230 Def000011
+S A$sleepcont$1221 Def000004
+S A$sleepcont$1231 Def000014
+S A$sleepcont$1222 Def000007
+S A$sleepcont$1232 Def000015
+S A$sleepcont$1223 Def000008
+S A$sleepcont$1233 Def000017
+S A$sleepcont$1224 Def000009
+S A$sleepcont$1225 Def00000A
+S A$sleepcont$1226 Def00000B
+S A$sleepcont$1228 Def00000D
+S A$sleepcont$1219 Def000000
+S XFsleepcont$dummy$0$0 Def00001A
+S A$sleepcont$1229 Def000010
+S C$sleepcont.c$72$1$30 Def00001A
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2A flags 20 addr 0
+S _enter_sleep_cont Def000000
+S Fsleepcont$dummy$0$0 Def00002A
+S XG$enter_sleep_cont$0$0 Def00002A
+S A$sleepcont$1180 Def000011
+S A$sleepcont$1171 Def000000
+S A$sleepcont$1190 Def000022
+S A$sleepcont$1181 Def000012
+S A$sleepcont$1172 Def000003
+S A$sleepcont$1191 Def000024
+S A$sleepcont$1182 Def000014
+S A$sleepcont$1173 Def000004
+S A$sleepcont$1192 Def000027
+S A$sleepcont$1183 Def000016
+S A$sleepcont$1174 Def000006
+S A$sleepcont$1184 Def000017
+S A$sleepcont$1175 Def000007
+S A$sleepcont$1185 Def000019
+S A$sleepcont$1176 Def000009
+S A$sleepcont$1186 Def00001A
+S A$sleepcont$1177 Def00000A
+S A$sleepcont$1187 Def00001C
+S A$sleepcont$1178 Def00000C
+S A$sleepcont$1188 Def00001E
+S A$sleepcont$1179 Def00000E
+S A$sleepcont$1189 Def000020
+S C$sleepcont.c$71$1$30 Def00002A
+S C$sleepcont.c$41$1$28 Def00002A
+S C$sleepcont.c$13$0$0 Def000000
+S C$sleepcont.c$38$1$28 Def000000
+S C$sleepcont.c$39$1$28 Def00002A
+S G$enter_sleep_cont$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 F5 98 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 0C F0 78 FF 76 BE 18 76 37 18
+R 00 00 00 16
+T 00 00 1A A6 81 E5 87 54 0C 44 02 F5 87 75 97 D3
+R 00 00 00 16
+T 00 00 27 02 E0 47
+R 00 00 00 16
+T 00 00 2A
+R 00 00 00 16
+T 00 00 00 78 FF E5 87 20 E6 06 E4 F6 18 F6 80 0D
+R 00 00 00 0F
+T 00 00 0D
+R 00 00 00 0F
+T 00 00 0D B6 BE 0A 18 B6 37 06 18 86 81 02 00 00
+R 00 00 00 0F 02 0E 00 AE
+T 00 00 1A
+R 00 00 00 0F
+
+
+M:sleepcont
+F:G$enter_sleep_cont$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fsleepcont$dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:Fsleepcont$dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+standby
+
+;!FILE libmf/standby.asm
+XH3
+H 1A areas 2DA global symbols
+M standby
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S G$enter_standby$0$0 Def000000
+S A$standby$1180 Def00000D
+S A$standby$1171 Def000000
+S A$standby$1181 Def00000E
+S A$standby$1172 Def000002
+S A$standby$1173 Def000004
+S A$standby$1174 Def000006
+S A$standby$1175 Def000008
+S A$standby$1176 Def000009
+S A$standby$1177 Def00000A
+S A$standby$1178 Def00000B
+S A$standby$1179 Def00000C
+S _enter_standby Def000000
+S C$standby.c$24$1$28 Def000000
+S C$standby.c$10$0$0 Def000000
+S C$standby.c$25$1$28 Def00000F
+S XG$enter_standby$0$0 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 87 54 0C 44 01 F5 87 00 22 00 00 00
+R 00 00 00 16
+T 00 00 0D 00 00
+R 00 00 00 16
+
+
+M:standby
+F:G$enter_standby$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
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+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
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+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
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+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
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+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
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+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
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+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
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+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
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+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_4$0$0({1}SX:U),J,0,0
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+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
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+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+resetcpu
+
+;!FILE libmf/resetcpu.asm
+XH3
+H 1A areas 2D9 global symbols
+M resetcpu
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E flags 20 addr 0
+S A$resetcpu$1182 Def000005
+S A$resetcpu$1192 Def00000D
+S A$resetcpu$1183 Def000006
+S A$resetcpu$1186 Def000007
+S A$resetcpu$1178 Def000000
+S A$resetcpu$1189 Def00000A
+S C$resetcpu.c$12$1$28 Def000000
+S C$resetcpu.c$13$1$28 Def000002
+S C$resetcpu.c$14$1$28 Def000007
+S C$resetcpu.c$10$0$0 Def000000
+S C$resetcpu.c$17$1$28 Def00000A
+S C$resetcpu.c$18$1$28 Def00000D
+S G$reset_cpu$0$0 Def000000
+S _reset_cpu Def000000
+S XG$reset_cpu$0$0 Def00000D
+S A$resetcpu$1181 Def000002
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 AF 90 70 0C E4 F0 75 97 D3 02 E0 47
+R 00 00 00 16
+T 00 00 0D 22
+R 00 00 00 16
+
+
+M:resetcpu
+F:G$reset_cpu$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+flashunlock
+
+;!FILE libmf/flashunlock.asm
+XH3
+H 1B areas 2DD global symbols
+M flashunlock
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S Fflashunlock$flash_deviceid$0$0 Def00FC06
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11 flags 20 addr 0
+S G$flash_unlock$0$0 Def000000
+S C$flashunlock.c$6$1$35 Def000000
+S C$flashunlock.c$7$1$35 Def000005
+S C$flashunlock.c$8$1$35 Def000007
+S C$flashunlock.c$9$1$35 Def00000A
+S C$flashunlock.c$4$0$0 Def000000
+S _flash_unlock Def000000
+S XG$flash_unlock$0$0 Def000010
+S A$flashunlock$1201 Def000010
+S A$flashunlock$1191 Def000007
+S A$flashunlock$1183 Def000000
+S A$flashunlock$1184 Def000002
+S A$flashunlock$1194 Def00000A
+S A$flashunlock$1185 Def000004
+S A$flashunlock$1197 Def00000D
+S A$flashunlock$1188 Def000005
+S A$flashunlock$1198 Def00000E
+S C$flashunlock.c$10$1$35 Def00000D
+S C$flashunlock.c$11$1$35 Def000010
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 74 80 55 A8 FF C2 AF 75 96 41 75 96 78
+R 00 00 00 17
+T 00 00 0D EF 42 A8 22
+R 00 00 00 17
+
+
+M:flashunlock
+F:G$flash_unlock$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashunlock$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashlock
+
+;!FILE libmf/flashlock.asm
+XH3
+H 1A areas 2D2 global symbols
+M flashlock
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S Fflashlock$flash_deviceid$0$0 Def00FC06
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4 flags 20 addr 0
+S XG$flash_lock$0$0 Def000003
+S A$flashlock$1180 Def000000
+S A$flashlock$1183 Def000003
+S G$flash_lock$0$0 Def000000
+S C$flashlock.c$6$1$35 Def000000
+S C$flashlock.c$7$1$35 Def000003
+S C$flashlock.c$4$0$0 Def000000
+S _flash_lock Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 96 00 22
+R 00 00 00 16
+
+
+M:flashlock
+F:G$flash_lock$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
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+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashwait
+
+;!FILE libmf/flashwait.asm
+XH3
+H 1B areas 2F2 global symbols
+M flashwait
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S Fflashwait$flash_deviceid$0$0 Def00FC06
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 26 flags 20 addr 0
+S C$flashwait.c$8$1$0 Def000006
+S _flash_wait Def000000
+S XG$flash_wait$0$0 Def000025
+S A$flashwait$1220 Def000019
+S A$flashwait$1211 Def000010
+S A$flashwait$1230 Def000020
+S A$flashwait$1221 Def00001C
+S A$flashwait$1212 Def000013
+S A$flashwait$1206 Def00000A
+S A$flashwait$1216 Def000015
+S A$flashwait$1207 Def00000C
+S A$flashwait$1235 Def000022
+S A$flashwait$1217 Def000016
+S A$flashwait$1208 Def00000D
+S A$flashwait$1227 Def00001E
+S A$flashwait$1193 Def000006
+S A$flashwait$1184 Def000000
+S A$flashwait$1239 Def000025
+S A$flashwait$1194 Def000007
+S A$flashwait$1185 Def000002
+S A$flashwait$1195 Def000008
+S A$flashwait$1188 Def000004
+S A$flashwait$1198 Def000009
+S C$flashwait.c$10$1$35 Def000009
+S C$flashwait.c$21$1$35 Def000022
+S C$flashwait.c$22$1$35 Def000022
+S C$flashwait.c$20$2$36 Def000020
+S C$flashwait.c$23$1$35 Def000025
+S C$flashwait.c$12$2$36 Def00000A
+S C$flashwait.c$13$3$37 Def00000A
+S C$flashwait.c$14$3$37 Def00000A
+S C$flashwait.c$15$3$37 Def000010
+S C$flashwait.c$16$3$37 Def000015
+S C$flashwait.c$19$2$36 Def00001E
+S C$flashwait.c$17$3$37 Def000019
+S C$flashwait.c$18$3$37 Def00001E
+S G$flash_wait$0$0 Def000000
+S C$flashwait.c$9$1$35 Def000006
+S C$flashwait.c$4$0$0 Def000000
+S C$flashwait.c$7$1$0 Def000004
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 AE 82 AF 83 8F 05 ED 04 FF 0E
+R 00 00 00 17
+T 00 00 0A
+R 00 00 00 17
+T 00 00 0A E5 91 FD 20 E1 05 75 82 FE 80 10
+R 00 00 00 17
+T 00 00 15
+R 00 00 00 17
+T 00 00 15 ED 20 E0 05 75 82 00 80 07
+R 00 00 00 17
+T 00 00 1E
+R 00 00 00 17
+T 00 00 1E DE EA DF E8 75 82 FF
+R 00 00 00 17
+T 00 00 25
+R 00 00 00 17
+T 00 00 25 22
+R 00 00 00 17
+
+
+M:flashwait
+F:G$flash_wait$0$0({2}DF,SC:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashwait$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashpgerase
+
+;!FILE libmf/flashpgerase.asm
+XH3
+H 1A areas 2DC global symbols
+M flashpgerase
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S _flash_wait Ref000000
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S Fflashpgerase$flash_deviceid$0$0 Def00FC06
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 12 flags 20 addr 0
+S XG$flash_pageerase$0$0 Def000011
+S A$flashpgerase$1181 Def000000
+S A$flashpgerase$1191 Def000008
+S A$flashpgerase$1182 Def000002
+S A$flashpgerase$1194 Def00000B
+S A$flashpgerase$1185 Def000004
+S A$flashpgerase$1195 Def00000E
+S A$flashpgerase$1188 Def000006
+S A$flashpgerase$1198 Def000011
+S C$flashpgerase.c$10$1$35 Def000011
+S C$flashpgerase.c$6$1$35 Def000004
+S C$flashpgerase.c$7$1$35 Def000006
+S C$flashpgerase.c$8$1$35 Def000008
+S C$flashpgerase.c$9$1$35 Def00000B
+S C$flashpgerase.c$4$0$0 Def000000
+S G$flash_pageerase$0$0 Def000000
+S _flash_pageerase Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 8E 92 8F 93 75 91 20 90
+R 00 00 00 16
+T 00 00 0C FF FF 12 00 00 22
+R 00 00 00 16 02 06 00 18
+
+
+M:flashpgerase
+F:G$flash_pageerase$0$0({2}DF,SC:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lflashpgerase.flash_pageerase$pgaddr$1$34({2}SI:U),R,0,0,[r6,r7]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashpgerase$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
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+
+
+
+
+flashwrite
+
+;!FILE libmf/flashwrite.asm
+XH3
+H 1A areas 2E2 global symbols
+M flashwrite
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S _flash_wait Ref000000
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
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+S G$EIP_5$0$0 Def0000B5
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+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
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+S _EIE_4 Def00009C
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+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
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+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
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+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
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+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
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+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
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+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
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+S G$FRCOSCKFILT$0$0 Def007072
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+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
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+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
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+S G$LPOSCKFILT$0$0 Def007062
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+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
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+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
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+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
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+S G$ADCCH3VAL0$0$0 Def007026
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+S _NVKEY Def000096
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+S _FRCOSCREF1 Def007075
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+S G$T2CNT0$0$0 Def0000AC
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+S _DMA1ADDR1 Def007013
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+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
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+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
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+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
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+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
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+S __XPAGE Def0000D9
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+S G$E2IP_2$0$0 Def0000C2
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+S G$IC1STATUS$0$0 Def0000D5
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+S G$E2IP_4$0$0 Def0000C4
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+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
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+S G$E2IP_6$0$0 Def0000C6
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+S _ADCCH2VAL1 Def007025
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+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
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+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
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+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
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+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
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+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
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+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
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+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
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+S G$T2CNT$0$0 Def00ADAC
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+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
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+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 8E 92 8F 93 85 00 00 00 94
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 0B 85 00 00 01 95 75 91 30 90 00 80 12
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 15 00 00 22
+R 00 00 00 16 02 03 00 18
+
+
+M:flashwrite
+F:G$flash_write$0$0({2}DF,SC:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lflashwrite.flash_write$wdata$1$34({2}SI:U),E,0,0
+S:Lflashwrite.flash_write$waddr$1$34({2}SI:U),R,0,0,[r6,r7]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashwrite$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
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+S:G$E2IE_4$0$0({1}SX:U),J,0,0
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+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
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+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
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+S:G$EIP_7$0$0({1}SX:U),J,0,0
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+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashread
+
+;!FILE libmf/flashread.asm
+XH3
+H 1B areas 17 global symbols
+M flashread
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S Fflashread$flash_deviceid$0$0 Def00FC06
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 16 flags 20 addr 0
+S A$flashread$120 Def000009
+S A$flashread$131 Def000011
+S A$flashread$132 Def000013
+S A$flashread$123 Def00000B
+S A$flashread$114 Def000000
+S A$flashread$133 Def000015
+S A$flashread$124 Def00000C
+S A$flashread$115 Def000002
+S A$flashread$125 Def00000D
+S A$flashread$126 Def00000E
+S A$flashread$127 Def00000F
+S A$flashread$118 Def000004
+S A$flashread$128 Def000010
+S A$flashread$119 Def000007
+S C$flashread.c$5$1$35 Def000004
+S G$flash_read$0$0 Def000000
+S C$flashread.c$6$1$35 Def00000B
+S C$flashread.c$7$1$35 Def000011
+S C$flashread.c$3$0$0 Def000000
+S _flash_read Def000000
+S XG$flash_read$0$0 Def000011
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 AE 82 AF 83 53 06 FE 8E 82 8F 83 E4 93
+R 00 00 00 17
+T 00 00 0D FE A3 E4 93 8E 82 F5 83 22
+R 00 00 00 17
+
+
+M:flashread
+F:G$flash_read$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fflashread$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashcal
+
+;!FILE libmf/flashcal.asm
+XH3
+H 1A areas 3E0 global symbols
+M flashcal
+O -mmcs51 --model-small
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
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+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
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+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
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+S G$ADCCALG01GAIN1$0$0 Def007033
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+S G$WTCNTA$0$0 Def00F3F2
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+S _E2IE Def0000A0
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+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S _crc_crc8ccitt_msbtable Ref000000
+S G$B_2$0$0 Def0000F2
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+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
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+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
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+S G$B_5$0$0 Def0000F5
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+S G$IC1CAPT1$0$0 Def0000D7
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+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
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+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
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+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
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+S _RADIOFSTATADDR Def007042
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+S _FRCOSCREF1 Def007075
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+S _DMA1ADDR1 Def007013
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+S G$PORTC_5$0$0 Def000095
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+S G$SPSHREG$0$0 Def0000DE
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+S G$DPH$0$0 Def000083
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+S G$PORTB_7$0$0 Def00008F
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+S G$WTEVTC$0$0 Def00FDFC
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+S G$PORTC_7$0$0 Def000097
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+S _B_1 Def0000F1
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+S G$PALTRADIO$0$0 Def007046
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+S __XPAGE Def0000D9
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+S _E2IE_0 Def0000A0
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+S _ADCCH0VAL0 Def007020
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+S _E2IE_2 Def0000A2
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+S _E2IE_3 Def0000A3
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+S _ADCCH2VAL1 Def007025
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+S G$ADCCH0VAL$0$0 Def007020
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+S _OSCRUN Def007051
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+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
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+S Fflashcal$flash_deviceid$0$0 Def00FC06
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+S _RADIOFDATAADDR1 Def007041
+S _POWCTRL0 Def007F10
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
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+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
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+S G$LPOSCPER$0$0 Def007068
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+S _POWCTRL1 Def007F11
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
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+S _PORTA_7 Def000087
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+S G$RADIOMUX$0$0 Def007044
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+S _FRCOSCFREQ0 Def007076
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+S _ADCCALTEMPGAIN1 Def007039
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+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
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+S C$flashcal.c$280$1$153 Def000000
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+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+flashcsec
+
+XH3
+H 1A areas 2 global symbols
+M flashcsec
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+S Fflashcsec$flash_calsector$0$0 Def00FC00
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:flashcsec
+T:Fflashcsec$calsector[({0}S:S$id$0$0({5}DA5d,SC:U),Z,0,0)({5}S:S$len$0$0({1}SC:U),Z,0,0)({6}S:S$devid$0$0({6}DA6d,SC:U),Z,0,0)({12}S:S$calg00gain$0$0({2}DA2d,SC:U),Z,0,0)({14}S:S$calg01gain$0$0({2}DA2d,SC:U),Z,0,0)({16}S:S$calg10gain$0$0({2}DA2d,SC:U),
+
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+Z,0,0)({18}S:S$caltempgain$0$0({2}DA2d,SC:U),Z,0,0)({20}S:S$caltempoffs$0$0({2}DA2d,SC:U),Z,0,0)({22}S:S$frcoscfreq$0$0({2}DA2d,SC:U),Z,0,0)({24}S:S$lposcfreq$0$0({2}DA2d,SC:U),Z,0,0)({26}S:S$lposcfreq_fast$0$0({2}DA2d,SC:U),Z,0,0)({28}S:S$powctrl0$0$0(
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+{1}SC:U),Z,0,0)({29}S:S$powctrl1$0$0({1}SC:U),Z,0,0)({30}S:S$ref$0$0({1}SC:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fflashcsec$flash_calsector$0$0({31}STcalsector:S),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer0
+
+;!FILE libmf/uarttimer0.asm
+XH3
+H 1A areas 408 global symbols
+M uarttimer0
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 186 flags 20 addr 0
+S _uart_timer0_baud Def000000
+S C$uarttimer0.c$9$0$0 Def000000
+S XG$uart_timer0_baud$0$0 Def000185
+S A$uarttimer0$1200 Def000014
+S A$uarttimer0$1300 Def00007C
+S A$uarttimer0$1210 Def00001E
+S A$uarttimer0$1201 Def000015
+S A$uarttimer0$1400 Def0000DC
+S A$uarttimer0$1310 Def000083
+S A$uarttimer0$1301 Def00007D
+S A$uarttimer0$1220 Def000029
+S A$uarttimer0$1202 Def000016
+S A$uarttimer0$1500 Def00015F
+S A$uarttimer0$1410 Def0000E8
+S A$uarttimer0$1401 Def0000DE
+S A$uarttimer0$1320 Def000090
+S A$uarttimer0$1311 Def000085
+S A$uarttimer0$1302 Def00007E
+S A$uarttimer0$1230 Def000033
+S A$uarttimer0$1221 Def00002A
+S A$uarttimer0$1501 Def000160
+S A$uarttimer0$1420 Def0000F2
+S A$uarttimer0$1411 Def0000E9
+S A$uarttimer0$1402 Def0000E0
+S A$uarttimer0$1330 Def00009C
+S A$uarttimer0$1321 Def000092
+S A$uarttimer0$1312 Def000087
+S A$uarttimer0$1240 Def00003B
+S A$uarttimer0$1231 Def000034
+S A$uarttimer0$1222 Def00002B
+S A$uarttimer0$1213 Def000020
+S A$uarttimer0$1520 Def000172
+S A$uarttimer0$1502 Def000161
+S A$uarttimer0$1430 Def0000FD
+S A$uarttimer0$1421 Def0000F3
+S A$uarttimer0$1412 Def0000EA
+S A$uarttimer0$1403 Def0000E1
+S A$uarttimer0$1340 Def0000A6
+S A$uarttimer0$1331 Def00009D
+S A$uarttimer0$1322 Def000093
+S A$uarttimer0$1232 Def000035
+S A$uarttimer0$1223 Def00002C
+S A$uarttimer0$1214 Def000022
+S A$uarttimer0$1205 Def000017
+S A$uarttimer0$1530 Def00017D
+S A$uarttimer0$1521 Def000173
+S A$uarttimer0$1512 Def000169
+S A$uarttimer0$1503 Def000162
+S A$uarttimer0$1440 Def00010D
+S A$uarttimer0$1431 Def0000FE
+S A$uarttimer0$1422 Def0000F4
+S A$uarttimer0$1413 Def0000EB
+S A$uarttimer0$1350 Def0000B1
+S A$uarttimer0$1341 Def0000A7
+S A$uarttimer0$1332 Def00009E
+S A$uarttimer0$1323 Def000094
+S A$uarttimer0$1314 Def000089
+S A$uarttimer0$1305 Def00007F
+S A$uarttimer0$1260 Def000051
+S A$uarttimer0$1251 Def000047
+S A$uarttimer0$1224 Def00002D
+S A$uarttimer0$1215 Def000024
+S A$uarttimer0$1206 Def000018
+S A$uarttimer0$1531 Def00017E
+S A$uarttimer0$1522 Def000174
+S A$uarttimer0$1513 Def00016A
+S A$uarttimer0$1504 Def000163
+S A$uarttimer0$1450 Def00011D
+S A$uarttimer0$1441 Def00010E
+S A$uarttimer0$1432 Def000100
+S A$uarttimer0$1423 Def0000F5
+S A$uarttimer0$1414 Def0000EC
+S A$uarttimer0$1405 Def0000E3
+S A$uarttimer0$1351 Def0000B2
+S A$uarttimer0$1342 Def0000A9
+S A$uarttimer0$1333 Def00009F
+S A$uarttimer0$1324 Def000096
+S A$uarttimer0$1270 Def00005D
+S A$uarttimer0$1261 Def000052
+S A$uarttimer0$1225 Def00002E
+S A$uarttimer0$1216 Def000025
+S A$uarttimer0$1207 Def000019
+S A$uarttimer0$1532 Def000180
+S A$uarttimer0$1514 Def00016C
+S A$uarttimer0$1505 Def000164
+S A$uarttimer0$1460 Def00012E
+S A$uarttimer0$1451 Def00011F
+S A$uarttimer0$1442 Def000110
+S A$uarttimer0$1433 Def000101
+S A$uarttimer0$1415 Def0000ED
+S A$uarttimer0$1406 Def0000E4
+S A$uarttimer0$1370 Def0000C1
+S A$uarttimer0$1361 Def0000B8
+S A$uarttimer0$1352 Def0000B3
+S A$uarttimer0$1343 Def0000AA
+S A$uarttimer0$1334 Def0000A0
+S A$uarttimer0$1325 Def000097
+S A$uarttimer0$1316 Def00008C
+S A$uarttimer0$1280 Def000068
+S A$uarttimer0$1271 Def00005E
+S A$uarttimer0$1262 Def000053
+S A$uarttimer0$1244 Def00003D
+S A$uarttimer0$1235 Def000037
+S A$uarttimer0$1226 Def00002F
+S A$uarttimer0$1217 Def000026
+S A$uarttimer0$1208 Def00001B
+S A$uarttimer0$1533 Def000181
+S A$uarttimer0$1515 Def00016D
+S A$uarttimer0$1506 Def000165
+S A$uarttimer0$1470 Def00013A
+S A$uarttimer0$1461 Def000130
+S A$uarttimer0$1452 Def000121
+S A$uarttimer0$1443 Def000111
+S A$uarttimer0$1434 Def000103
+S A$uarttimer0$1425 Def0000F6
+S A$uarttimer0$1416 Def0000EE
+S A$uarttimer0$1407 Def0000E5
+S A$uarttimer0$1380 Def0000CD
+S A$uarttimer0$1371 Def0000C3
+S A$uarttimer0$1353 Def0000B4
+S A$uarttimer0$1344 Def0000AB
+S A$uarttimer0$1335 Def0000A1
+S A$uarttimer0$1326 Def000098
+S A$uarttimer0$1290 Def000073
+S A$uarttimer0$1281 Def000069
+S A$uarttimer0$1272 Def00005F
+S A$uarttimer0$1263 Def000054
+S A$uarttimer0$1254 Def000049
+S A$uarttimer0$1245 Def00003E
+S A$uarttimer0$1236 Def000038
+S A$uarttimer0$1227 Def000030
+S A$uarttimer0$1218 Def000027
+S A$uarttimer0$1191 Def000009
+S A$uarttimer0$1182 Def000000
+S A$uarttimer0$1534 Def000183
+S A$uarttimer0$1525 Def000176
+S A$uarttimer0$1507 Def000166
+S A$uarttimer0$1480 Def000147
+S A$uarttimer0$1471 Def00013C
+S A$uarttimer0$1462 Def000131
+S A$uarttimer0$1453 Def000123
+S A$uarttimer0$1444 Def000113
+S A$uarttimer0$1435 Def000104
+S A$uarttimer0$1417 Def0000EF
+S A$uarttimer0$1408 Def0000E6
+S A$uarttimer0$1381 Def0000CE
+S A$uarttimer0$1372 Def0000C4
+S A$uarttimer0$1354 Def0000B5
+S A$uarttimer0$1345 Def0000AC
+S A$uarttimer0$1336 Def0000A2
+S A$uarttimer0$1327 Def000099
+S A$uarttimer0$1309 Def000082
+S A$uarttimer0$1291 Def000074
+S A$uarttimer0$1282 Def00006A
+S A$uarttimer0$1273 Def000060
+S A$uarttimer0$1264 Def000056
+S A$uarttimer0$1255 Def00004B
+S A$uarttimer0$1246 Def000040
+S A$uarttimer0$1237 Def00003A
+S A$uarttimer0$1228 Def000031
+S A$uarttimer0$1219 Def000028
+S A$uarttimer0$1192 Def00000A
+S A$uarttimer0$1183 Def000002
+S A$uarttimer0$1508 Def000167
+S A$uarttimer0$1490 Def000155
+S A$uarttimer0$1481 Def000148
+S A$uarttimer0$1472 Def00013D
+S A$uarttimer0$1463 Def000133
+S A$uarttimer0$1454 Def000124
+S A$uarttimer0$1445 Def000114
+S A$uarttimer0$1436 Def000106
+S A$uarttimer0$1418 Def0000F0
+S A$uarttimer0$1409 Def0000E7
+S A$uarttimer0$1382 Def0000CF
+S A$uarttimer0$1373 Def0000C5
+S A$uarttimer0$1346 Def0000AD
+S A$uarttimer0$1337 Def0000A3
+S A$uarttimer0$1328 Def00009A
+S A$uarttimer0$1319 Def00008E
+S A$uarttimer0$1292 Def000075
+S A$uarttimer0$1283 Def00006B
+S A$uarttimer0$1274 Def000061
+S A$uarttimer0$1265 Def000057
+S A$uarttimer0$1256 Def00004D
+S A$uarttimer0$1247 Def000042
+S A$uarttimer0$1229 Def000032
+S A$uarttimer0$1193 Def00000C
+S A$uarttimer0$1184 Def000005
+S A$uarttimer0$1509 Def000168
+S A$uarttimer0$1491 Def000156
+S A$uarttimer0$1482 Def00014A
+S A$uarttimer0$1473 Def00013E
+S A$uarttimer0$1464 Def000134
+S A$uarttimer0$1455 Def000126
+S A$uarttimer0$1446 Def000116
+S A$uarttimer0$1437 Def000107
+S A$uarttimer0$1428 Def0000F9
+S A$uarttimer0$1419 Def0000F1
+S A$uarttimer0$1392 Def0000D5
+S A$uarttimer0$1383 Def0000D0
+S A$uarttimer0$1374 Def0000C7
+S A$uarttimer0$1365 Def0000BB
+S A$uarttimer0$1347 Def0000AE
+S A$uarttimer0$1338 Def0000A4
+S A$uarttimer0$1329 Def00009B
+S A$uarttimer0$1293 Def000077
+S A$uarttimer0$1284 Def00006C
+S A$uarttimer0$1275 Def000062
+S A$uarttimer0$1266 Def000058
+S A$uarttimer0$1257 Def00004E
+S A$uarttimer0$1537 Def000185
+S A$uarttimer0$1528 Def000179
+S A$uarttimer0$1519 Def00016F
+S A$uarttimer0$1492 Def000157
+S A$uarttimer0$1483 Def00014C
+S A$uarttimer0$1474 Def00013F
+S A$uarttimer0$1456 Def000128
+S A$uarttimer0$1447 Def000117
+S A$uarttimer0$1438 Def000109
+S A$uarttimer0$1429 Def0000FB
+S A$uarttimer0$1384 Def0000D1
+S A$uarttimer0$1375 Def0000C8
+S A$uarttimer0$1366 Def0000BC
+S A$uarttimer0$1357 Def0000B6
+S A$uarttimer0$1348 Def0000AF
+S A$uarttimer0$1339 Def0000A5
+S A$uarttimer0$1294 Def000078
+S A$uarttimer0$1285 Def00006D
+S A$uarttimer0$1276 Def000063
+S A$uarttimer0$1267 Def000059
+S A$uarttimer0$1258 Def00004F
+S A$uarttimer0$1249 Def000044
+S A$uarttimer0$1529 Def00017B
+S A$uarttimer0$1493 Def000158
+S A$uarttimer0$1484 Def00014D
+S A$uarttimer0$1475 Def000140
+S A$uarttimer0$1457 Def00012A
+S A$uarttimer0$1448 Def000118
+S A$uarttimer0$1439 Def00010B
+S A$uarttimer0$1385 Def0000D2
+S A$uarttimer0$1376 Def0000C9
+S A$uarttimer0$1358 Def0000B7
+S A$uarttimer0$1349 Def0000B0
+S A$uarttimer0$1295 Def000079
+S A$uarttimer0$1286 Def00006E
+S A$uarttimer0$1277 Def000064
+S A$uarttimer0$1268 Def00005A
+S A$uarttimer0$1259 Def000050
+S A$uarttimer0$1187 Def000007
+S A$uarttimer0$1494 Def000159
+S A$uarttimer0$1485 Def00014F
+S A$uarttimer0$1476 Def000142
+S A$uarttimer0$1467 Def000136
+S A$uarttimer0$1458 Def00012B
+S A$uarttimer0$1449 Def00011A
+S A$uarttimer0$1386 Def0000D3
+S A$uarttimer0$1377 Def0000CA
+S A$uarttimer0$1296 Def00007A
+S A$uarttimer0$1287 Def000070
+S A$uarttimer0$1278 Def000065
+S A$uarttimer0$1269 Def00005B
+S A$uarttimer0$1197 Def00000F
+S A$uarttimer0$1495 Def00015A
+S A$uarttimer0$1477 Def000143
+S A$uarttimer0$1459 Def00012D
+S A$uarttimer0$1378 Def0000CB
+S A$uarttimer0$1369 Def0000BF
+S A$uarttimer0$1288 Def000071
+S A$uarttimer0$1279 Def000067
+S A$uarttimer0$1198 Def000011
+S C$uarttimer0.c$12$1$31 Def000009
+S A$uarttimer0$1496 Def00015B
+S A$uarttimer0$1478 Def000144
+S A$uarttimer0$1469 Def000138
+S A$uarttimer0$1379 Def0000CC
+S A$uarttimer0$1289 Def000072
+S A$uarttimer0$1199 Def000013
+S A$uarttimer0$1497 Def00015C
+S A$uarttimer0$1488 Def000151
+S A$uarttimer0$1479 Def000146
+S A$uarttimer0$1398 Def0000D8
+S A$uarttimer0$1389 Def0000D4
+S A$uarttimer0$1299 Def00007B
+S C$uarttimer0.c$13$2$31 Def00000F
+S A$uarttimer0$1498 Def00015D
+S A$uarttimer0$1489 Def000153
+S A$uarttimer0$1399 Def0000DA
+S A$uarttimer0$1499 Def00015E
+S C$uarttimer0.c$43$1$31 Def00016F
+S C$uarttimer0.c$34$1$31 Def0000D8
+S C$uarttimer0.c$20$3$34 Def000049
+S C$uarttimer0.c$14$2$32 Def000017
+S C$uarttimer0.c$44$1$31 Def000176
+S C$uarttimer0.c$24$2$32 Def000082
+S C$uarttimer0.c$21$3$34 Def00007B
+S C$uarttimer0.c$45$1$31 Def000179
+S C$uarttimer0.c$36$1$31 Def0000D8
+S C$uarttimer0.c$22$3$34 Def00007F
+S C$uarttimer0.c$46$1$31 Def000185
+S C$uarttimer0.c$37$1$31 Def0000F9
+S C$uarttimer0.c$30$3$36 Def0000BF
+S C$uarttimer0.c$15$3$33 Def000020
+S C$uarttimer0.c$40$2$37 Def000151
+S C$uarttimer0.c$31$3$36 Def0000D4
+S C$uarttimer0.c$16$3$33 Def000037
+S C$uarttimer0.c$41$2$37 Def000169
+S C$uarttimer0.c$39$1$31 Def000136
+S C$uarttimer0.c$32$3$36 Def0000D5
+S C$uarttimer0.c$19$2$32 Def00003D
+S C$uarttimer0.c$17$3$33 Def00003B
+S C$uarttimer0.c$29$2$32 Def0000BB
+S C$uarttimer0.c$25$3$35 Def00008E
+S C$uarttimer0.c$26$3$35 Def0000B6
+S C$uarttimer0.c$11$1$0 Def000007
+S C$uarttimer0.c$27$3$35 Def0000B8
+S G$uart_timer0_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
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+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
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+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
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+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
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+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 86
+R 00 00 00 16 F1 23 07 01 F7
+T 00 00 FF 00 00 00 08 86 00 00 01 08 86
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 05 00 00 02 08 86 00 00 03 E5
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 0A 00 00 00 24 FA F8 86 82 08 86 83 08 86
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 15 F0 08 E6 C0 07 12 00 00 AB 82 AC 83 AD
+R 00 00 00 16 02 09 01 6F
+T 00 01 22 F0 FE D0 07 E5 00 00 00 24 FA F8 A6 03
+R 00 00 00 16 F1 23 08 01 F7
+T 00 01 2D 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 38
+R 00 00 00 16
+T 00 01 38 E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 43 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 50 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 5B 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 68 F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 6F
+R 00 00 00 16
+T 00 01 6F 53 07 07 EF 4E F5 9A 75 99 04 E5
+R 00 00 00 16
+T 00 01 7A 00 00 00 24 FA F8 86 9E 08 86 9F D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 84 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer0
+F:G$uart_timer0_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer0.uart_timer0_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer0.uart_timer0_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer0.uart_timer0_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer0.uart_timer0_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer0.uart_timer0_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer1
+
+;!FILE libmf/uarttimer1.asm
+XH3
+H 1A areas 408 global symbols
+M uarttimer1
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 186 flags 20 addr 0
+S _uart_timer1_baud Def000000
+S C$uarttimer1.c$9$0$0 Def000000
+S XG$uart_timer1_baud$0$0 Def000185
+S A$uarttimer1$1200 Def000014
+S A$uarttimer1$1300 Def00007C
+S A$uarttimer1$1210 Def00001E
+S A$uarttimer1$1201 Def000015
+S A$uarttimer1$1400 Def0000DC
+S A$uarttimer1$1310 Def000083
+S A$uarttimer1$1301 Def00007D
+S A$uarttimer1$1220 Def000029
+S A$uarttimer1$1202 Def000016
+S A$uarttimer1$1500 Def00015F
+S A$uarttimer1$1410 Def0000E8
+S A$uarttimer1$1401 Def0000DE
+S A$uarttimer1$1320 Def000090
+S A$uarttimer1$1311 Def000085
+S A$uarttimer1$1302 Def00007E
+S A$uarttimer1$1230 Def000033
+S A$uarttimer1$1221 Def00002A
+S A$uarttimer1$1501 Def000160
+S A$uarttimer1$1420 Def0000F2
+S A$uarttimer1$1411 Def0000E9
+S A$uarttimer1$1402 Def0000E0
+S A$uarttimer1$1330 Def00009C
+S A$uarttimer1$1321 Def000092
+S A$uarttimer1$1312 Def000087
+S A$uarttimer1$1240 Def00003B
+S A$uarttimer1$1231 Def000034
+S A$uarttimer1$1222 Def00002B
+S A$uarttimer1$1213 Def000020
+S A$uarttimer1$1520 Def000172
+S A$uarttimer1$1502 Def000161
+S A$uarttimer1$1430 Def0000FD
+S A$uarttimer1$1421 Def0000F3
+S A$uarttimer1$1412 Def0000EA
+S A$uarttimer1$1403 Def0000E1
+S A$uarttimer1$1340 Def0000A6
+S A$uarttimer1$1331 Def00009D
+S A$uarttimer1$1322 Def000093
+S A$uarttimer1$1232 Def000035
+S A$uarttimer1$1223 Def00002C
+S A$uarttimer1$1214 Def000022
+S A$uarttimer1$1205 Def000017
+S A$uarttimer1$1530 Def00017D
+S A$uarttimer1$1521 Def000173
+S A$uarttimer1$1512 Def000169
+S A$uarttimer1$1503 Def000162
+S A$uarttimer1$1440 Def00010D
+S A$uarttimer1$1431 Def0000FE
+S A$uarttimer1$1422 Def0000F4
+S A$uarttimer1$1413 Def0000EB
+S A$uarttimer1$1350 Def0000B1
+S A$uarttimer1$1341 Def0000A7
+S A$uarttimer1$1332 Def00009E
+S A$uarttimer1$1323 Def000094
+S A$uarttimer1$1314 Def000089
+S A$uarttimer1$1305 Def00007F
+S A$uarttimer1$1260 Def000051
+S A$uarttimer1$1251 Def000047
+S A$uarttimer1$1224 Def00002D
+S A$uarttimer1$1215 Def000024
+S A$uarttimer1$1206 Def000018
+S A$uarttimer1$1531 Def00017E
+S A$uarttimer1$1522 Def000174
+S A$uarttimer1$1513 Def00016A
+S A$uarttimer1$1504 Def000163
+S A$uarttimer1$1450 Def00011D
+S A$uarttimer1$1441 Def00010E
+S A$uarttimer1$1432 Def000100
+S A$uarttimer1$1423 Def0000F5
+S A$uarttimer1$1414 Def0000EC
+S A$uarttimer1$1405 Def0000E3
+S A$uarttimer1$1351 Def0000B2
+S A$uarttimer1$1342 Def0000A9
+S A$uarttimer1$1333 Def00009F
+S A$uarttimer1$1324 Def000096
+S A$uarttimer1$1270 Def00005D
+S A$uarttimer1$1261 Def000052
+S A$uarttimer1$1225 Def00002E
+S A$uarttimer1$1216 Def000025
+S A$uarttimer1$1207 Def000019
+S A$uarttimer1$1532 Def000180
+S A$uarttimer1$1514 Def00016C
+S A$uarttimer1$1505 Def000164
+S A$uarttimer1$1460 Def00012E
+S A$uarttimer1$1451 Def00011F
+S A$uarttimer1$1442 Def000110
+S A$uarttimer1$1433 Def000101
+S A$uarttimer1$1415 Def0000ED
+S A$uarttimer1$1406 Def0000E4
+S A$uarttimer1$1370 Def0000C1
+S A$uarttimer1$1361 Def0000B8
+S A$uarttimer1$1352 Def0000B3
+S A$uarttimer1$1343 Def0000AA
+S A$uarttimer1$1334 Def0000A0
+S A$uarttimer1$1325 Def000097
+S A$uarttimer1$1316 Def00008C
+S A$uarttimer1$1280 Def000068
+S A$uarttimer1$1271 Def00005E
+S A$uarttimer1$1262 Def000053
+S A$uarttimer1$1244 Def00003D
+S A$uarttimer1$1235 Def000037
+S A$uarttimer1$1226 Def00002F
+S A$uarttimer1$1217 Def000026
+S A$uarttimer1$1208 Def00001B
+S A$uarttimer1$1533 Def000181
+S A$uarttimer1$1515 Def00016D
+S A$uarttimer1$1506 Def000165
+S A$uarttimer1$1470 Def00013A
+S A$uarttimer1$1461 Def000130
+S A$uarttimer1$1452 Def000121
+S A$uarttimer1$1443 Def000111
+S A$uarttimer1$1434 Def000103
+S A$uarttimer1$1425 Def0000F6
+S A$uarttimer1$1416 Def0000EE
+S A$uarttimer1$1407 Def0000E5
+S A$uarttimer1$1380 Def0000CD
+S A$uarttimer1$1371 Def0000C3
+S A$uarttimer1$1353 Def0000B4
+S A$uarttimer1$1344 Def0000AB
+S A$uarttimer1$1335 Def0000A1
+S A$uarttimer1$1326 Def000098
+S A$uarttimer1$1290 Def000073
+S A$uarttimer1$1281 Def000069
+S A$uarttimer1$1272 Def00005F
+S A$uarttimer1$1263 Def000054
+S A$uarttimer1$1254 Def000049
+S A$uarttimer1$1245 Def00003E
+S A$uarttimer1$1236 Def000038
+S A$uarttimer1$1227 Def000030
+S A$uarttimer1$1218 Def000027
+S A$uarttimer1$1191 Def000009
+S A$uarttimer1$1182 Def000000
+S A$uarttimer1$1534 Def000183
+S A$uarttimer1$1525 Def000176
+S A$uarttimer1$1507 Def000166
+S A$uarttimer1$1480 Def000147
+S A$uarttimer1$1471 Def00013C
+S A$uarttimer1$1462 Def000131
+S A$uarttimer1$1453 Def000123
+S A$uarttimer1$1444 Def000113
+S A$uarttimer1$1435 Def000104
+S A$uarttimer1$1417 Def0000EF
+S A$uarttimer1$1408 Def0000E6
+S A$uarttimer1$1381 Def0000CE
+S A$uarttimer1$1372 Def0000C4
+S A$uarttimer1$1354 Def0000B5
+S A$uarttimer1$1345 Def0000AC
+S A$uarttimer1$1336 Def0000A2
+S A$uarttimer1$1327 Def000099
+S A$uarttimer1$1309 Def000082
+S A$uarttimer1$1291 Def000074
+S A$uarttimer1$1282 Def00006A
+S A$uarttimer1$1273 Def000060
+S A$uarttimer1$1264 Def000056
+S A$uarttimer1$1255 Def00004B
+S A$uarttimer1$1246 Def000040
+S A$uarttimer1$1237 Def00003A
+S A$uarttimer1$1228 Def000031
+S A$uarttimer1$1219 Def000028
+S A$uarttimer1$1192 Def00000A
+S A$uarttimer1$1183 Def000002
+S A$uarttimer1$1508 Def000167
+S A$uarttimer1$1490 Def000155
+S A$uarttimer1$1481 Def000148
+S A$uarttimer1$1472 Def00013D
+S A$uarttimer1$1463 Def000133
+S A$uarttimer1$1454 Def000124
+S A$uarttimer1$1445 Def000114
+S A$uarttimer1$1436 Def000106
+S A$uarttimer1$1418 Def0000F0
+S A$uarttimer1$1409 Def0000E7
+S A$uarttimer1$1382 Def0000CF
+S A$uarttimer1$1373 Def0000C5
+S A$uarttimer1$1346 Def0000AD
+S A$uarttimer1$1337 Def0000A3
+S A$uarttimer1$1328 Def00009A
+S A$uarttimer1$1319 Def00008E
+S A$uarttimer1$1292 Def000075
+S A$uarttimer1$1283 Def00006B
+S A$uarttimer1$1274 Def000061
+S A$uarttimer1$1265 Def000057
+S A$uarttimer1$1256 Def00004D
+S A$uarttimer1$1247 Def000042
+S A$uarttimer1$1229 Def000032
+S A$uarttimer1$1193 Def00000C
+S A$uarttimer1$1184 Def000005
+S A$uarttimer1$1509 Def000168
+S A$uarttimer1$1491 Def000156
+S A$uarttimer1$1482 Def00014A
+S A$uarttimer1$1473 Def00013E
+S A$uarttimer1$1464 Def000134
+S A$uarttimer1$1455 Def000126
+S A$uarttimer1$1446 Def000116
+S A$uarttimer1$1437 Def000107
+S A$uarttimer1$1428 Def0000F9
+S A$uarttimer1$1419 Def0000F1
+S A$uarttimer1$1392 Def0000D5
+S A$uarttimer1$1383 Def0000D0
+S A$uarttimer1$1374 Def0000C7
+S A$uarttimer1$1365 Def0000BB
+S A$uarttimer1$1347 Def0000AE
+S A$uarttimer1$1338 Def0000A4
+S A$uarttimer1$1329 Def00009B
+S A$uarttimer1$1293 Def000077
+S A$uarttimer1$1284 Def00006C
+S A$uarttimer1$1275 Def000062
+S A$uarttimer1$1266 Def000058
+S A$uarttimer1$1257 Def00004E
+S A$uarttimer1$1537 Def000185
+S A$uarttimer1$1528 Def000179
+S A$uarttimer1$1519 Def00016F
+S A$uarttimer1$1492 Def000157
+S A$uarttimer1$1483 Def00014C
+S A$uarttimer1$1474 Def00013F
+S A$uarttimer1$1456 Def000128
+S A$uarttimer1$1447 Def000117
+S A$uarttimer1$1438 Def000109
+S A$uarttimer1$1429 Def0000FB
+S A$uarttimer1$1384 Def0000D1
+S A$uarttimer1$1375 Def0000C8
+S A$uarttimer1$1366 Def0000BC
+S A$uarttimer1$1357 Def0000B6
+S A$uarttimer1$1348 Def0000AF
+S A$uarttimer1$1339 Def0000A5
+S A$uarttimer1$1294 Def000078
+S A$uarttimer1$1285 Def00006D
+S A$uarttimer1$1276 Def000063
+S A$uarttimer1$1267 Def000059
+S A$uarttimer1$1258 Def00004F
+S A$uarttimer1$1249 Def000044
+S A$uarttimer1$1529 Def00017B
+S A$uarttimer1$1493 Def000158
+S A$uarttimer1$1484 Def00014D
+S A$uarttimer1$1475 Def000140
+S A$uarttimer1$1457 Def00012A
+S A$uarttimer1$1448 Def000118
+S A$uarttimer1$1439 Def00010B
+S A$uarttimer1$1385 Def0000D2
+S A$uarttimer1$1376 Def0000C9
+S A$uarttimer1$1358 Def0000B7
+S A$uarttimer1$1349 Def0000B0
+S A$uarttimer1$1295 Def000079
+S A$uarttimer1$1286 Def00006E
+S A$uarttimer1$1277 Def000064
+S A$uarttimer1$1268 Def00005A
+S A$uarttimer1$1259 Def000050
+S A$uarttimer1$1187 Def000007
+S A$uarttimer1$1494 Def000159
+S A$uarttimer1$1485 Def00014F
+S A$uarttimer1$1476 Def000142
+S A$uarttimer1$1467 Def000136
+S A$uarttimer1$1458 Def00012B
+S A$uarttimer1$1449 Def00011A
+S A$uarttimer1$1386 Def0000D3
+S A$uarttimer1$1377 Def0000CA
+S A$uarttimer1$1296 Def00007A
+S A$uarttimer1$1287 Def000070
+S A$uarttimer1$1278 Def000065
+S A$uarttimer1$1269 Def00005B
+S A$uarttimer1$1197 Def00000F
+S A$uarttimer1$1495 Def00015A
+S A$uarttimer1$1477 Def000143
+S A$uarttimer1$1459 Def00012D
+S A$uarttimer1$1378 Def0000CB
+S A$uarttimer1$1369 Def0000BF
+S A$uarttimer1$1288 Def000071
+S A$uarttimer1$1279 Def000067
+S A$uarttimer1$1198 Def000011
+S C$uarttimer1.c$12$1$31 Def000009
+S A$uarttimer1$1496 Def00015B
+S A$uarttimer1$1478 Def000144
+S A$uarttimer1$1469 Def000138
+S A$uarttimer1$1379 Def0000CC
+S A$uarttimer1$1289 Def000072
+S A$uarttimer1$1199 Def000013
+S A$uarttimer1$1497 Def00015C
+S A$uarttimer1$1488 Def000151
+S A$uarttimer1$1479 Def000146
+S A$uarttimer1$1398 Def0000D8
+S A$uarttimer1$1389 Def0000D4
+S A$uarttimer1$1299 Def00007B
+S C$uarttimer1.c$13$2$31 Def00000F
+S A$uarttimer1$1498 Def00015D
+S A$uarttimer1$1489 Def000153
+S A$uarttimer1$1399 Def0000DA
+S A$uarttimer1$1499 Def00015E
+S C$uarttimer1.c$43$1$31 Def00016F
+S C$uarttimer1.c$34$1$31 Def0000D8
+S C$uarttimer1.c$20$3$34 Def000049
+S C$uarttimer1.c$14$2$32 Def000017
+S C$uarttimer1.c$44$1$31 Def000176
+S C$uarttimer1.c$24$2$32 Def000082
+S C$uarttimer1.c$21$3$34 Def00007B
+S C$uarttimer1.c$45$1$31 Def000179
+S C$uarttimer1.c$36$1$31 Def0000D8
+S C$uarttimer1.c$22$3$34 Def00007F
+S C$uarttimer1.c$46$1$31 Def000185
+S C$uarttimer1.c$37$1$31 Def0000F9
+S C$uarttimer1.c$30$3$36 Def0000BF
+S C$uarttimer1.c$15$3$33 Def000020
+S C$uarttimer1.c$40$2$37 Def000151
+S C$uarttimer1.c$31$3$36 Def0000D4
+S C$uarttimer1.c$16$3$33 Def000037
+S C$uarttimer1.c$41$2$37 Def000169
+S C$uarttimer1.c$39$1$31 Def000136
+S C$uarttimer1.c$32$3$36 Def0000D5
+S C$uarttimer1.c$19$2$32 Def00003D
+S C$uarttimer1.c$17$3$33 Def00003B
+S C$uarttimer1.c$29$2$32 Def0000BB
+S C$uarttimer1.c$25$3$35 Def00008E
+S C$uarttimer1.c$26$3$35 Def0000B6
+S C$uarttimer1.c$11$1$0 Def000007
+S C$uarttimer1.c$27$3$35 Def0000B8
+S G$uart_timer1_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
+R 00 00 00 16
+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 BE 02 00
+R 00 00 00 16
+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 86
+R 00 00 00 16 F1 23 07 01 F7
+T 00 00 FF 00 00 00 08 86 00 00 01 08 86
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 05 00 00 02 08 86 00 00 03 E5
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 0A 00 00 00 24 FA F8 86 82 08 86 83 08 86
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 15 F0 08 E6 C0 07 12 00 00 AB 82 AC 83 AD
+R 00 00 00 16 02 09 01 6F
+T 00 01 22 F0 FE D0 07 E5 00 00 00 24 FA F8 A6 03
+R 00 00 00 16 F1 23 08 01 F7
+T 00 01 2D 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 38
+R 00 00 00 16
+T 00 01 38 E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 43 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 50 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 5B 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 68 F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 6F
+R 00 00 00 16
+T 00 01 6F 53 07 07 EF 4E F5 A2 75 A1 04 E5
+R 00 00 00 16
+T 00 01 7A 00 00 00 24 FA F8 86 A6 08 86 A7 D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 84 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer1
+F:G$uart_timer1_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer1.uart_timer1_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer1.uart_timer1_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer1.uart_timer1_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer1.uart_timer1_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer1.uart_timer1_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer2
+
+;!FILE libmf/uarttimer2.asm
+XH3
+H 1A areas 408 global symbols
+M uarttimer2
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 186 flags 20 addr 0
+S _uart_timer2_baud Def000000
+S C$uarttimer2.c$9$0$0 Def000000
+S XG$uart_timer2_baud$0$0 Def000185
+S A$uarttimer2$1200 Def000014
+S A$uarttimer2$1300 Def00007C
+S A$uarttimer2$1210 Def00001E
+S A$uarttimer2$1201 Def000015
+S A$uarttimer2$1400 Def0000DC
+S A$uarttimer2$1310 Def000083
+S A$uarttimer2$1301 Def00007D
+S A$uarttimer2$1220 Def000029
+S A$uarttimer2$1202 Def000016
+S A$uarttimer2$1500 Def00015F
+S A$uarttimer2$1410 Def0000E8
+S A$uarttimer2$1401 Def0000DE
+S A$uarttimer2$1320 Def000090
+S A$uarttimer2$1311 Def000085
+S A$uarttimer2$1302 Def00007E
+S A$uarttimer2$1230 Def000033
+S A$uarttimer2$1221 Def00002A
+S A$uarttimer2$1501 Def000160
+S A$uarttimer2$1420 Def0000F2
+S A$uarttimer2$1411 Def0000E9
+S A$uarttimer2$1402 Def0000E0
+S A$uarttimer2$1330 Def00009C
+S A$uarttimer2$1321 Def000092
+S A$uarttimer2$1312 Def000087
+S A$uarttimer2$1240 Def00003B
+S A$uarttimer2$1231 Def000034
+S A$uarttimer2$1222 Def00002B
+S A$uarttimer2$1213 Def000020
+S A$uarttimer2$1520 Def000172
+S A$uarttimer2$1502 Def000161
+S A$uarttimer2$1430 Def0000FD
+S A$uarttimer2$1421 Def0000F3
+S A$uarttimer2$1412 Def0000EA
+S A$uarttimer2$1403 Def0000E1
+S A$uarttimer2$1340 Def0000A6
+S A$uarttimer2$1331 Def00009D
+S A$uarttimer2$1322 Def000093
+S A$uarttimer2$1232 Def000035
+S A$uarttimer2$1223 Def00002C
+S A$uarttimer2$1214 Def000022
+S A$uarttimer2$1205 Def000017
+S A$uarttimer2$1530 Def00017D
+S A$uarttimer2$1521 Def000173
+S A$uarttimer2$1512 Def000169
+S A$uarttimer2$1503 Def000162
+S A$uarttimer2$1440 Def00010D
+S A$uarttimer2$1431 Def0000FE
+S A$uarttimer2$1422 Def0000F4
+S A$uarttimer2$1413 Def0000EB
+S A$uarttimer2$1350 Def0000B1
+S A$uarttimer2$1341 Def0000A7
+S A$uarttimer2$1332 Def00009E
+S A$uarttimer2$1323 Def000094
+S A$uarttimer2$1314 Def000089
+S A$uarttimer2$1305 Def00007F
+S A$uarttimer2$1260 Def000051
+S A$uarttimer2$1251 Def000047
+S A$uarttimer2$1224 Def00002D
+S A$uarttimer2$1215 Def000024
+S A$uarttimer2$1206 Def000018
+S A$uarttimer2$1531 Def00017E
+S A$uarttimer2$1522 Def000174
+S A$uarttimer2$1513 Def00016A
+S A$uarttimer2$1504 Def000163
+S A$uarttimer2$1450 Def00011D
+S A$uarttimer2$1441 Def00010E
+S A$uarttimer2$1432 Def000100
+S A$uarttimer2$1423 Def0000F5
+S A$uarttimer2$1414 Def0000EC
+S A$uarttimer2$1405 Def0000E3
+S A$uarttimer2$1351 Def0000B2
+S A$uarttimer2$1342 Def0000A9
+S A$uarttimer2$1333 Def00009F
+S A$uarttimer2$1324 Def000096
+S A$uarttimer2$1270 Def00005D
+S A$uarttimer2$1261 Def000052
+S A$uarttimer2$1225 Def00002E
+S A$uarttimer2$1216 Def000025
+S A$uarttimer2$1207 Def000019
+S A$uarttimer2$1532 Def000180
+S A$uarttimer2$1514 Def00016C
+S A$uarttimer2$1505 Def000164
+S A$uarttimer2$1460 Def00012E
+S A$uarttimer2$1451 Def00011F
+S A$uarttimer2$1442 Def000110
+S A$uarttimer2$1433 Def000101
+S A$uarttimer2$1415 Def0000ED
+S A$uarttimer2$1406 Def0000E4
+S A$uarttimer2$1370 Def0000C1
+S A$uarttimer2$1361 Def0000B8
+S A$uarttimer2$1352 Def0000B3
+S A$uarttimer2$1343 Def0000AA
+S A$uarttimer2$1334 Def0000A0
+S A$uarttimer2$1325 Def000097
+S A$uarttimer2$1316 Def00008C
+S A$uarttimer2$1280 Def000068
+S A$uarttimer2$1271 Def00005E
+S A$uarttimer2$1262 Def000053
+S A$uarttimer2$1244 Def00003D
+S A$uarttimer2$1235 Def000037
+S A$uarttimer2$1226 Def00002F
+S A$uarttimer2$1217 Def000026
+S A$uarttimer2$1208 Def00001B
+S A$uarttimer2$1533 Def000181
+S A$uarttimer2$1515 Def00016D
+S A$uarttimer2$1506 Def000165
+S A$uarttimer2$1470 Def00013A
+S A$uarttimer2$1461 Def000130
+S A$uarttimer2$1452 Def000121
+S A$uarttimer2$1443 Def000111
+S A$uarttimer2$1434 Def000103
+S A$uarttimer2$1425 Def0000F6
+S A$uarttimer2$1416 Def0000EE
+S A$uarttimer2$1407 Def0000E5
+S A$uarttimer2$1380 Def0000CD
+S A$uarttimer2$1371 Def0000C3
+S A$uarttimer2$1353 Def0000B4
+S A$uarttimer2$1344 Def0000AB
+S A$uarttimer2$1335 Def0000A1
+S A$uarttimer2$1326 Def000098
+S A$uarttimer2$1290 Def000073
+S A$uarttimer2$1281 Def000069
+S A$uarttimer2$1272 Def00005F
+S A$uarttimer2$1263 Def000054
+S A$uarttimer2$1254 Def000049
+S A$uarttimer2$1245 Def00003E
+S A$uarttimer2$1236 Def000038
+S A$uarttimer2$1227 Def000030
+S A$uarttimer2$1218 Def000027
+S A$uarttimer2$1191 Def000009
+S A$uarttimer2$1182 Def000000
+S A$uarttimer2$1534 Def000183
+S A$uarttimer2$1525 Def000176
+S A$uarttimer2$1507 Def000166
+S A$uarttimer2$1480 Def000147
+S A$uarttimer2$1471 Def00013C
+S A$uarttimer2$1462 Def000131
+S A$uarttimer2$1453 Def000123
+S A$uarttimer2$1444 Def000113
+S A$uarttimer2$1435 Def000104
+S A$uarttimer2$1417 Def0000EF
+S A$uarttimer2$1408 Def0000E6
+S A$uarttimer2$1381 Def0000CE
+S A$uarttimer2$1372 Def0000C4
+S A$uarttimer2$1354 Def0000B5
+S A$uarttimer2$1345 Def0000AC
+S A$uarttimer2$1336 Def0000A2
+S A$uarttimer2$1327 Def000099
+S A$uarttimer2$1309 Def000082
+S A$uarttimer2$1291 Def000074
+S A$uarttimer2$1282 Def00006A
+S A$uarttimer2$1273 Def000060
+S A$uarttimer2$1264 Def000056
+S A$uarttimer2$1255 Def00004B
+S A$uarttimer2$1246 Def000040
+S A$uarttimer2$1237 Def00003A
+S A$uarttimer2$1228 Def000031
+S A$uarttimer2$1219 Def000028
+S A$uarttimer2$1192 Def00000A
+S A$uarttimer2$1183 Def000002
+S A$uarttimer2$1508 Def000167
+S A$uarttimer2$1490 Def000155
+S A$uarttimer2$1481 Def000148
+S A$uarttimer2$1472 Def00013D
+S A$uarttimer2$1463 Def000133
+S A$uarttimer2$1454 Def000124
+S A$uarttimer2$1445 Def000114
+S A$uarttimer2$1436 Def000106
+S A$uarttimer2$1418 Def0000F0
+S A$uarttimer2$1409 Def0000E7
+S A$uarttimer2$1382 Def0000CF
+S A$uarttimer2$1373 Def0000C5
+S A$uarttimer2$1346 Def0000AD
+S A$uarttimer2$1337 Def0000A3
+S A$uarttimer2$1328 Def00009A
+S A$uarttimer2$1319 Def00008E
+S A$uarttimer2$1292 Def000075
+S A$uarttimer2$1283 Def00006B
+S A$uarttimer2$1274 Def000061
+S A$uarttimer2$1265 Def000057
+S A$uarttimer2$1256 Def00004D
+S A$uarttimer2$1247 Def000042
+S A$uarttimer2$1229 Def000032
+S A$uarttimer2$1193 Def00000C
+S A$uarttimer2$1184 Def000005
+S A$uarttimer2$1509 Def000168
+S A$uarttimer2$1491 Def000156
+S A$uarttimer2$1482 Def00014A
+S A$uarttimer2$1473 Def00013E
+S A$uarttimer2$1464 Def000134
+S A$uarttimer2$1455 Def000126
+S A$uarttimer2$1446 Def000116
+S A$uarttimer2$1437 Def000107
+S A$uarttimer2$1428 Def0000F9
+S A$uarttimer2$1419 Def0000F1
+S A$uarttimer2$1392 Def0000D5
+S A$uarttimer2$1383 Def0000D0
+S A$uarttimer2$1374 Def0000C7
+S A$uarttimer2$1365 Def0000BB
+S A$uarttimer2$1347 Def0000AE
+S A$uarttimer2$1338 Def0000A4
+S A$uarttimer2$1329 Def00009B
+S A$uarttimer2$1293 Def000077
+S A$uarttimer2$1284 Def00006C
+S A$uarttimer2$1275 Def000062
+S A$uarttimer2$1266 Def000058
+S A$uarttimer2$1257 Def00004E
+S A$uarttimer2$1537 Def000185
+S A$uarttimer2$1528 Def000179
+S A$uarttimer2$1519 Def00016F
+S A$uarttimer2$1492 Def000157
+S A$uarttimer2$1483 Def00014C
+S A$uarttimer2$1474 Def00013F
+S A$uarttimer2$1456 Def000128
+S A$uarttimer2$1447 Def000117
+S A$uarttimer2$1438 Def000109
+S A$uarttimer2$1429 Def0000FB
+S A$uarttimer2$1384 Def0000D1
+S A$uarttimer2$1375 Def0000C8
+S A$uarttimer2$1366 Def0000BC
+S A$uarttimer2$1357 Def0000B6
+S A$uarttimer2$1348 Def0000AF
+S A$uarttimer2$1339 Def0000A5
+S A$uarttimer2$1294 Def000078
+S A$uarttimer2$1285 Def00006D
+S A$uarttimer2$1276 Def000063
+S A$uarttimer2$1267 Def000059
+S A$uarttimer2$1258 Def00004F
+S A$uarttimer2$1249 Def000044
+S A$uarttimer2$1529 Def00017B
+S A$uarttimer2$1493 Def000158
+S A$uarttimer2$1484 Def00014D
+S A$uarttimer2$1475 Def000140
+S A$uarttimer2$1457 Def00012A
+S A$uarttimer2$1448 Def000118
+S A$uarttimer2$1439 Def00010B
+S A$uarttimer2$1385 Def0000D2
+S A$uarttimer2$1376 Def0000C9
+S A$uarttimer2$1358 Def0000B7
+S A$uarttimer2$1349 Def0000B0
+S A$uarttimer2$1295 Def000079
+S A$uarttimer2$1286 Def00006E
+S A$uarttimer2$1277 Def000064
+S A$uarttimer2$1268 Def00005A
+S A$uarttimer2$1259 Def000050
+S A$uarttimer2$1187 Def000007
+S A$uarttimer2$1494 Def000159
+S A$uarttimer2$1485 Def00014F
+S A$uarttimer2$1476 Def000142
+S A$uarttimer2$1467 Def000136
+S A$uarttimer2$1458 Def00012B
+S A$uarttimer2$1449 Def00011A
+S A$uarttimer2$1386 Def0000D3
+S A$uarttimer2$1377 Def0000CA
+S A$uarttimer2$1296 Def00007A
+S A$uarttimer2$1287 Def000070
+S A$uarttimer2$1278 Def000065
+S A$uarttimer2$1269 Def00005B
+S A$uarttimer2$1197 Def00000F
+S A$uarttimer2$1495 Def00015A
+S A$uarttimer2$1477 Def000143
+S A$uarttimer2$1459 Def00012D
+S A$uarttimer2$1378 Def0000CB
+S A$uarttimer2$1369 Def0000BF
+S A$uarttimer2$1288 Def000071
+S A$uarttimer2$1279 Def000067
+S A$uarttimer2$1198 Def000011
+S C$uarttimer2.c$12$1$31 Def000009
+S A$uarttimer2$1496 Def00015B
+S A$uarttimer2$1478 Def000144
+S A$uarttimer2$1469 Def000138
+S A$uarttimer2$1379 Def0000CC
+S A$uarttimer2$1289 Def000072
+S A$uarttimer2$1199 Def000013
+S A$uarttimer2$1497 Def00015C
+S A$uarttimer2$1488 Def000151
+S A$uarttimer2$1479 Def000146
+S A$uarttimer2$1398 Def0000D8
+S A$uarttimer2$1389 Def0000D4
+S A$uarttimer2$1299 Def00007B
+S C$uarttimer2.c$13$2$31 Def00000F
+S A$uarttimer2$1498 Def00015D
+S A$uarttimer2$1489 Def000153
+S A$uarttimer2$1399 Def0000DA
+S A$uarttimer2$1499 Def00015E
+S C$uarttimer2.c$43$1$31 Def00016F
+S C$uarttimer2.c$34$1$31 Def0000D8
+S C$uarttimer2.c$20$3$34 Def000049
+S C$uarttimer2.c$14$2$32 Def000017
+S C$uarttimer2.c$44$1$31 Def000176
+S C$uarttimer2.c$24$2$32 Def000082
+S C$uarttimer2.c$21$3$34 Def00007B
+S C$uarttimer2.c$45$1$31 Def000179
+S C$uarttimer2.c$36$1$31 Def0000D8
+S C$uarttimer2.c$22$3$34 Def00007F
+S C$uarttimer2.c$46$1$31 Def000185
+S C$uarttimer2.c$37$1$31 Def0000F9
+S C$uarttimer2.c$30$3$36 Def0000BF
+S C$uarttimer2.c$15$3$33 Def000020
+S C$uarttimer2.c$40$2$37 Def000151
+S C$uarttimer2.c$31$3$36 Def0000D4
+S C$uarttimer2.c$16$3$33 Def000037
+S C$uarttimer2.c$41$2$37 Def000169
+S C$uarttimer2.c$39$1$31 Def000136
+S C$uarttimer2.c$32$3$36 Def0000D5
+S C$uarttimer2.c$19$2$32 Def00003D
+S C$uarttimer2.c$17$3$33 Def00003B
+S C$uarttimer2.c$29$2$32 Def0000BB
+S C$uarttimer2.c$25$3$35 Def00008E
+S C$uarttimer2.c$26$3$35 Def0000B6
+S C$uarttimer2.c$11$1$0 Def000007
+S C$uarttimer2.c$27$3$35 Def0000B8
+S G$uart_timer2_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
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+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
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+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
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+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 86
+R 00 00 00 16 F1 23 07 01 F7
+T 00 00 FF 00 00 00 08 86 00 00 01 08 86
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 05 00 00 02 08 86 00 00 03 E5
+R 00 00 00 16 F1 23 03 00 3A F1 23 08 00 3A
+T 00 01 0A 00 00 00 24 FA F8 86 82 08 86 83 08 86
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 15 F0 08 E6 C0 07 12 00 00 AB 82 AC 83 AD
+R 00 00 00 16 02 09 01 6F
+T 00 01 22 F0 FE D0 07 E5 00 00 00 24 FA F8 A6 03
+R 00 00 00 16 F1 23 08 01 F7
+T 00 01 2D 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 38
+R 00 00 00 16
+T 00 01 38 E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 43 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 50 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 5B 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 68 F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 6F
+R 00 00 00 16
+T 00 01 6F 53 07 07 EF 4E F5 AA 75 A9 04 E5
+R 00 00 00 16
+T 00 01 7A 00 00 00 24 FA F8 86 AE 08 86 AF D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 84 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer2
+F:G$uart_timer2_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer2.uart_timer2_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer2.uart_timer2_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer2.uart_timer2_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer2.uart_timer2_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer2.uart_timer2_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0init
+
+;!FILE libmf/uart0init.asm
+XH3
+H 24 areas 456 global symbols
+M uart0init
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S _uart0_rxbuffer Ref000000
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S _uart0_txbuffer Ref000000
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart0init$uart0_fiforxrd$0$0 Def000001
+S Fuart0init$uart0_fifotxrd$0$0 Def000003
+S Fuart0init$uart0_fiforxwr$0$0 Def000000
+S Fuart0init$uart0_fifotxwr$0$0 Def000002
+A OSEG size 2 flags 4 addr 0
+S Luart0init.uart0_init$stop$1$101 Def000001
+S Luart0init.uart0_init$wl$1$101 Def000000
+S _uart0_init_PARM_2 Def000000
+S _uart0_init_PARM_3 Def000001
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$uart0init.c$148$1$68 Def000022
+S XG$uart0_irq$0$0 Def000022
+S C$uart0init.c$97$1$63 Def000000
+S G$uart0_poll$0$0 Def000022
+S _uart0_poll Def000022
+S XFuart0init$dummy0$0$0 Def000000
+S G$uart0_irq$0$0 Def000000
+S A$uart0init$1240 Def00000C
+S C$uart0init.c$101$1$63 Def000000
+S A$uart0init$1241 Def00000F
+S A$uart0init$1242 Def000012
+S A$uart0init$1270 Def000027
+S A$uart0init$1243 Def000015
+S A$uart0init$1234 Def000000
+S A$uart0init$1271 Def000029
+S A$uart0init$1244 Def000017
+S A$uart0init$1235 Def000002
+S C$uart0init.c$120$1$66 Def000000
+S A$uart0init$1272 Def00002B
+S A$uart0init$1245 Def000019
+S A$uart0init$1236 Def000004
+S C$uart0init.c$121$1$66 Def000022
+S A$uart0init$1273 Def00002E
+S A$uart0init$1246 Def00001B
+S A$uart0init$1237 Def000006
+S _uart0_irq Def000000
+S A$uart0init$1274 Def000030
+S A$uart0init$1247 Def00001D
+S A$uart0init$1238 Def000008
+S C$uart0init.c$123$1$66 Def000022
+S A$uart0init$1275 Def000031
+S A$uart0init$1248 Def00001F
+S A$uart0init$1239 Def00000A
+S A$uart0init$1276 Def000032
+S A$uart0init$1267 Def000022
+S A$uart0init$1249 Def000021
+S A$uart0init$1277 Def000034
+S A$uart0init$1268 Def000024
+S A$uart0init$1278 Def000036
+S A$uart0init$1269 Def000026
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7D flags 20 addr 0
+S A$uart0init$1886 Def00006A
+S A$uart0init$1877 Def00005C
+S A$uart0init$1868 Def00004D
+S A$uart0init$1859 Def000043
+S A$uart0init$1796 Def000031
+S A$uart0init$1769 Def00001E
+S XG$uart0_txidle$0$0 Def000043
+S A$uart0init$1887 Def00006B
+S A$uart0init$1878 Def00005E
+S A$uart0init$1869 Def00004F
+S A$uart0init$1797 Def000033
+S C$uart0init.c$429$1$94 Def000007
+S A$uart0init$1897 Def000076
+S A$uart0init$1888 Def00006C
+S A$uart0init$1879 Def000060
+S A$uart0init$1798 Def000035
+S A$uart0init$1898 Def000078
+S A$uart0init$1889 Def00006E
+S A$uart0init$1799 Def000037
+S A$uart0init$1899 Def00007A
+S C$uart0init.c$449$1$96 Def000016
+S XG$uart0_rxpeek$0$0 Def000007
+S _uart0_txpoke Def000007
+S C$uart0init.c$466$1$98 Def00002C
+S C$uart0init.c$467$1$98 Def000043
+S C$uart0init.c$469$1$98 Def000043
+S _uart0_txpokehex Def000016
+S C$uart0init.c$1033$1$100 Def000043
+S C$uart0init.c$96$1$63 Def000000
+S Fuart0init$dummy0$0$0 Def000000
+S C$uart0init.c$84$0$0 Def000000
+S C$uart0init.c$1035$1$102 Def000049
+S XG$uart0_txpoke$0$0 Def000016
+S C$uart0init.c$1036$1$102 Def00004C
+S G$uart0_init$0$0 Def000043
+S C$uart0init.c$1037$1$102 Def000073
+S C$uart0init.c$1038$1$102 Def000076
+S C$uart0init.c$1039$1$102 Def00007C
+S XG$uart0_rxbuffersize$0$0 Def000000
+S XG$uart0_txpokehex$0$0 Def00002C
+S XFuart0init$wtimer_cansleep_dummy$0$0 Def000043
+S _uart0_init Def000043
+S C$uart0init.c$484$1$100 Def000043
+S C$uart0init.c$485$1$100 Def000043
+S G$uart0_txidle$0$0 Def00002C
+S XG$uart0_init$0$0 Def00007C
+S G$uart0_rxpeek$0$0 Def000000
+S A$uart0init$1800 Def000039
+S A$uart0init$1710 Def000000
+S A$uart0init$1711 Def000003
+S C$uart0init.c$401$1$90 Def000000
+S A$uart0init$1802 Def00003B
+S A$uart0init$1712 Def000004
+S _uart0_txidle Def00002C
+S A$uart0init$1902 Def00007C
+S A$uart0init$1803 Def00003E
+S A$uart0init$1740 Def000011
+S A$uart0init$1713 Def000006
+S C$uart0init.c$403$1$90 Def000000
+S A$uart0init$1741 Def000012
+S C$uart0init.c$411$1$92 Def000000
+S A$uart0init$1805 Def00003F
+S A$uart0init$1742 Def000013
+S C$uart0init.c$412$1$92 Def000007
+S A$uart0init$1860 Def000045
+S A$uart0init$1806 Def000042
+S A$uart0init$1770 Def000020
+S A$uart0init$1743 Def000015
+S A$uart0init$1734 Def000007
+S A$uart0init$1870 Def000051
+S A$uart0init$1861 Def000047
+S A$uart0init$1771 Def000022
+S A$uart0init$1735 Def000009
+S C$uart0init.c$430$1$94 Def000016
+S C$uart0init.c$414$1$92 Def000007
+S G$uart0_txpoke$0$0 Def000007
+S _uart0_rxpeek Def000000
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+S A$uart0init$1871 Def000053
+S A$uart0init$1772 Def000024
+S A$uart0init$1736 Def00000B
+S A$uart0init$1890 Def00006F
+S A$uart0init$1881 Def000063
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+S A$uart0init$1764 Def000016
+S A$uart0init$1737 Def00000D
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+S A$uart0init$1882 Def000065
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+S A$uart0init$1775 Def000028
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+S A$uart0init$1776 Def000029
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+S Fuart0init$wtimer_cansleep_dummy$0$0 Def000043
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+S Fuart0init$uart0_iocore$0$0 Def000000
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+
+
+M:uart0init
+F:Fuart0init$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart0_irq$0$0({2}DF,SV:S),Z,0,0,1,11,0
+F:G$uart0_poll$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart0init$uart0_iocore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$uart0_rxadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_rxadvance$idx$1$71({1}SC:U),R,0,0,[]
+F:G$uart0_txadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txadvance$idx$1$73({1}SC:U),R,0,0,[]
+F:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_rxbufptr$idx$1$75({1}SC:U),R,0,0,[]
+F:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_txbufptr$idx$1$77({1}SC:U),R,0,0,[]
+F:G$uart0_txfreelinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_txfree$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxcountlinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxcount$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_txbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxpeek$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_rxpeek$idx$1$91({1}SC:U),R,0,0,[]
+F:G$uart0_txpoke$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txpoke$ch$1$93({1}SC:U),B,1,-3
+S:Luart0init.uart0_txpoke$idx$1$93({1}SC:U),R,0,0,[]
+F:G$uart0_txpokehex$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txpokehex$ch$1$95({1}SC:U),B,1,-3
+S:Luart0init.uart0_txpokehex$idx$1$95({1}SC:U),R,0,0,[]
+F:G$uart0_txidle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart0init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart0_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart0init$uart0_fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart0_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart0_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0init$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fuart0init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1init
+
+;!FILE libmf/uart1init.asm
+XH3
+H 24 areas 456 global symbols
+M uart1init
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S _uart1_rxbuffer Ref000000
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _uart1_txbuffer Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart1init$uart1_fiforxrd$0$0 Def000001
+S Fuart1init$uart1_fifotxrd$0$0 Def000003
+S Fuart1init$uart1_fiforxwr$0$0 Def000000
+S Fuart1init$uart1_fifotxwr$0$0 Def000002
+A OSEG size 2 flags 4 addr 0
+S _uart1_init_PARM_3 Def000001
+S Luart1init.uart1_init$stop$1$101 Def000001
+S Luart1init.uart1_init$wl$1$101 Def000000
+S _uart1_init_PARM_2 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$uart1init.c$148$1$68 Def000022
+S XG$uart1_irq$0$0 Def000022
+S C$uart1init.c$97$1$63 Def000000
+S G$uart1_poll$0$0 Def000022
+S _uart1_poll Def000022
+S XFuart1init$dummy0$0$0 Def000000
+S G$uart1_irq$0$0 Def000000
+S A$uart1init$1240 Def00000C
+S C$uart1init.c$101$1$63 Def000000
+S A$uart1init$1241 Def00000F
+S A$uart1init$1242 Def000012
+S A$uart1init$1270 Def000027
+S A$uart1init$1243 Def000015
+S A$uart1init$1234 Def000000
+S A$uart1init$1271 Def000029
+S A$uart1init$1244 Def000017
+S A$uart1init$1235 Def000002
+S C$uart1init.c$120$1$66 Def000000
+S A$uart1init$1272 Def00002B
+S A$uart1init$1245 Def000019
+S A$uart1init$1236 Def000004
+S C$uart1init.c$121$1$66 Def000022
+S A$uart1init$1273 Def00002E
+S A$uart1init$1246 Def00001B
+S A$uart1init$1237 Def000006
+S _uart1_irq Def000000
+S A$uart1init$1274 Def000030
+S A$uart1init$1247 Def00001D
+S A$uart1init$1238 Def000008
+S C$uart1init.c$123$1$66 Def000022
+S A$uart1init$1275 Def000031
+S A$uart1init$1248 Def00001F
+S A$uart1init$1239 Def00000A
+S A$uart1init$1276 Def000032
+S A$uart1init$1267 Def000022
+S A$uart1init$1249 Def000021
+S A$uart1init$1277 Def000034
+S A$uart1init$1268 Def000024
+S A$uart1init$1278 Def000036
+S A$uart1init$1269 Def000026
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7D flags 20 addr 0
+S A$uart1init$1894 Def000073
+S A$uart1init$1885 Def000069
+S A$uart1init$1876 Def00005A
+S A$uart1init$1867 Def00004C
+S A$uart1init$1795 Def00002E
+S A$uart1init$1768 Def00001D
+S Fuart1init$wtimer_cansleep_dummy$0$0 Def000043
+S C$uart1init.c$452$1$96 Def00002C
+S A$uart1init$1886 Def00006A
+S A$uart1init$1877 Def00005C
+S A$uart1init$1868 Def00004D
+S A$uart1init$1859 Def000043
+S A$uart1init$1796 Def000031
+S A$uart1init$1769 Def00001E
+S XG$uart1_txidle$0$0 Def000043
+S A$uart1init$1887 Def00006B
+S A$uart1init$1878 Def00005E
+S A$uart1init$1869 Def00004F
+S A$uart1init$1797 Def000033
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+S Fuart1init$dummy0$0$0 Def000000
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+S XFuart1init$wtimer_cansleep_dummy$0$0 Def000043
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+T 00 00 50 14 F5 82 22
+R 00 00 00 1B
+T 00 00 54
+R 00 00 00 1B
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 12 00 99 E0 F5 82 22
+R 00 00 00 17 00 04 00 18
+T 00 00 07
+R 00 00 00 17
+T 00 00 07 C0 00 E5 81 24 FD F8
+R 00 00 00 17
+T 00 00 0E
+R 00 00 00 17
+T 00 00 0E 12 00 BB E6 F0 D0 00 22
+R 00 00 00 17 00 04 00 18
+T 00 00 16
+R 00 00 00 17
+T 00 00 16 C0 00 E5 81 24 FD F8 E6 54 0F 24 F6 50
+R 00 00 00 17
+T 00 00 23 02 24 07
+R 00 00 00 17
+T 00 00 26
+R 00 00 00 17
+T 00 00 26 24 3A F6 02 00 0E
+R 00 00 00 17 00 07 00 17
+T 00 00 2C
+R 00 00 00 17
+T 00 00 2C E5 EC 30 E1 0A 54 08 70 0A E5 ED 54 40
+R 00 00 00 17
+T 00 00 39 60 04
+R 00 00 00 17
+T 00 00 3B
+R 00 00 00 17
+T 00 00 3B 75 82 01 22
+R 00 00 00 17
+T 00 00 3F
+R 00 00 00 17
+T 00 00 3F 75 82 00 22
+R 00 00 00 17
+T 00 00 43
+R 00 00 00 17
+T 00 00 00 12 00 2C E5 82 70 01 22
+R 00 00 00 1F 00 04 00 17
+T 00 00 08
+R 00 00 00 1F
+T 00 00 43
+R 00 00 00 17
+T 00 00 43 C0 07 C0 06 AF 82 75 00 00 03 00 E4 F5
+R 00 00 00 17 F1 21 0A 00 05
+T 00 00 4E 00 00 02 F5 00 00 01 F5
+R 00 00 00 17 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 52 00 00 00 EF 04 54 03 FF 74 07 55
+R 00 00 00 17 F1 21 03 00 05
+T 00 00 5B 00 00 00 25 E0 25 E0 42 07 C3 E5
+R 00 00 00 17 F1 21 03 00 06
+T 00 00 64 00 00 01 94 02 B3 E4 33 C4 23 54 E0 4F
+R 00 00 00 17 F1 21 03 00 06
+T 00 00 6F 44 40 F5 EF 75 EC 07 D2 9D D0 06 D0 07
+R 00 00 00 17
+T 00 00 7C 22
+R 00 00 00 17
+
+
+M:uart1init
+F:Fuart1init$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart1_irq$0$0({2}DF,SV:S),Z,0,0,1,12,0
+F:G$uart1_poll$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart1init$uart1_iocore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$uart1_rxadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_rxadvance$idx$1$71({1}SC:U),R,0,0,[]
+F:G$uart1_txadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txadvance$idx$1$73({1}SC:U),R,0,0,[]
+F:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_rxbufptr$idx$1$75({1}SC:U),R,0,0,[]
+F:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_txbufptr$idx$1$77({1}SC:U),R,0,0,[]
+F:G$uart1_txfreelinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_txfree$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxcountlinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxcount$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_txbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxpeek$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_rxpeek$idx$1$91({1}SC:U),R,0,0,[]
+F:G$uart1_txpoke$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txpoke$ch$1$93({1}SC:U),B,1,-3
+S:Luart1init.uart1_txpoke$idx$1$93({1}SC:U),R,0,0,[]
+F:G$uart1_txpokehex$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txpokehex$ch$1$95({1}SC:U),B,1,-3
+S:Luart1init.uart1_txpokehex$idx$1$95({1}SC:U),R,0,0,[]
+F:G$uart1_txidle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart1init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart1_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart1init$uart1_fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart1_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart1_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1init$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fuart1init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0stop
+
+;!FILE libmf/uart0stop.asm
+XH3
+H 1A areas 2D9 global symbols
+M uart0stop
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart0stop$fiforxrd$0$0 Def000001
+S Fuart0stop$fifotxrd$0$0 Def000003
+S Fuart0stop$fiforxwr$0$0 Def000000
+S Fuart0stop$fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 9 flags 20 addr 0
+S A$uart0stop$1190 Def000000
+S A$uart0stop$1193 Def000002
+S A$uart0stop$1196 Def000005
+S A$uart0stop$1199 Def000008
+S C$uart0stop.c$76$1$63 Def000000
+S C$uart0stop.c$77$1$63 Def000002
+S C$uart0stop.c$78$1$63 Def000005
+S C$uart0stop.c$79$1$63 Def000008
+S C$uart0stop.c$74$0$0 Def000000
+S G$uart0_stop$0$0 Def000000
+S _uart0_stop Def000000
+S XG$uart0_stop$0$0 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 9C 75 E7 00 75 E4 00 22
+R 00 00 00 16
+
+
+M:uart0stop
+F:G$uart0_stop$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart0stop$fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart0_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart0_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
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+S:G$E2IE_1$0$0({1}SX:U),J,0,0
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+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
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+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1stop
+
+;!FILE libmf/uart1stop.asm
+XH3
+H 1A areas 2D9 global symbols
+M uart1stop
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart1stop$fiforxrd$0$0 Def000001
+S Fuart1stop$fifotxrd$0$0 Def000003
+S Fuart1stop$fiforxwr$0$0 Def000000
+S Fuart1stop$fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 9 flags 20 addr 0
+S A$uart1stop$1190 Def000000
+S A$uart1stop$1193 Def000002
+S A$uart1stop$1196 Def000005
+S A$uart1stop$1199 Def000008
+S C$uart1stop.c$76$1$63 Def000000
+S C$uart1stop.c$77$1$63 Def000002
+S C$uart1stop.c$78$1$63 Def000005
+S C$uart1stop.c$79$1$63 Def000008
+S C$uart1stop.c$74$0$0 Def000000
+S G$uart1_stop$0$0 Def000000
+S _uart1_stop Def000000
+S XG$uart1_stop$0$0 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 9D 75 EF 00 75 EC 00 22
+R 00 00 00 16
+
+
+M:uart1stop
+F:G$uart1_stop$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart1stop$fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart1_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart1_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0txbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart0txbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart0_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart0txbuf.c$5$1$60 Def000000
+S C$uart0txbuf.c$5$0$0 Def000000
+S Fuart0txbuf$uart0_define_txbuffer$0$0 Def000000
+S XFuart0txbuf$uart0_define_txbuffer$0$0 Def000000
+A UART0S0 size 0 flags 20 addr 0
+A UART0S1 size 2 flags 20 addr 0
+A UART0S2 size 0 flags 20 addr 0
+A UART0S3 size 0 flags 20 addr 0
+A UART0S4 size 1 flags 20 addr 0
+A UART0S5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:uart0txbuf
+F:Fuart0txbuf$uart0_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0txbuf$uart0_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1txbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart1txbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart1_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart1txbuf.c$5$1$60 Def000000
+S C$uart1txbuf.c$5$0$0 Def000000
+S Fuart1txbuf$uart1_define_txbuffer$0$0 Def000000
+S XFuart1txbuf$uart1_define_txbuffer$0$0 Def000000
+A UART1S0 size 0 flags 20 addr 0
+A UART1S1 size 2 flags 20 addr 0
+A UART1S2 size 0 flags 20 addr 0
+A UART1S3 size 0 flags 20 addr 0
+A UART1S4 size 1 flags 20 addr 0
+A UART1S5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:uart1txbuf
+F:Fuart1txbuf$uart1_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1txbuf$uart1_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0rxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart0rxbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart0_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart0rxbuf.c$5$1$60 Def000000
+S C$uart0rxbuf.c$5$0$0 Def000000
+S Fuart0rxbuf$uart0_define_rxbuffer$0$0 Def000000
+S XFuart0rxbuf$uart0_define_rxbuffer$0$0 Def000000
+A UART0S0 size 0 flags 20 addr 0
+A UART0S1 size 0 flags 20 addr 0
+A UART0S2 size 2 flags 20 addr 0
+A UART0S3 size 0 flags 20 addr 0
+A UART0S4 size 0 flags 20 addr 0
+A UART0S5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:uart0rxbuf
+F:Fuart0rxbuf$uart0_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0rxbuf$uart0_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1rxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart1rxbuf
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart1_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart1rxbuf.c$5$1$60 Def000000
+S C$uart1rxbuf.c$5$0$0 Def000000
+S Fuart1rxbuf$uart1_define_rxbuffer$0$0 Def000000
+S XFuart1rxbuf$uart1_define_rxbuffer$0$0 Def000000
+A UART1S0 size 0 flags 20 addr 0
+A UART1S1 size 0 flags 20 addr 0
+A UART1S2 size 2 flags 20 addr 0
+A UART1S3 size 0 flags 20 addr 0
+A UART1S4 size 0 flags 20 addr 0
+A UART1S5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:uart1rxbuf
+F:Fuart1rxbuf$uart1_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1rxbuf$uart1_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0tx
+
+;!FILE libmf/uart0tx.asm
+XH3
+H 1A areas 327 global symbols
+M uart0tx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S _uart0_txpoke Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _uart0_poll Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S _uart0_txadvance Ref000000
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _uart0_txidle Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _uart0_txfree Ref000000
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$uart0tx.c$29$2$61 Def00000F
+S G$uart0_wait_txfree$0$0 Def000000
+S C$uart0tx.c$45$2$64 Def000040
+S C$uart0tx.c$54$1$66 Def000057
+S C$uart0tx.c$46$2$64 Def000047
+S C$uart0tx.c$24$0$0 Def000000
+S C$uart0tx.c$55$1$66 Def00005D
+S C$uart0tx.c$47$2$64 Def00004A
+S C$uart0tx.c$49$1$63 Def00004F
+S C$uart0tx.c$56$1$66 Def000067
+S G$uart0_wait_txdone$0$0 Def000032
+S C$uart0tx.c$57$1$66 Def00006F
+S G$uart0_tx$0$0 Def000053
+S _uart0_wait_txfree Def000000
+S _uart0_wait_txdone Def000032
+S _uart0_tx Def000053
+S XG$uart0_wait_txfree$0$0 Def000031
+S XG$uart0_wait_txdone$0$0 Def000052
+S XG$uart0_tx$0$0 Def00006F
+S A$uart0tx$1300 Def000055
+S A$uart0tx$1201 Def00000D
+S A$uart0tx$1310 Def000065
+S A$uart0tx$1230 Def00002D
+S A$uart0tx$1221 Def000023
+S A$uart0tx$1212 Def000019
+S A$uart0tx$1303 Def000057
+S A$uart0tx$1231 Def00002F
+S A$uart0tx$1222 Def000024
+S A$uart0tx$1213 Def00001C
+S A$uart0tx$1204 Def00000F
+S A$uart0tx$1313 Def000067
+S A$uart0tx$1304 Def00005A
+S A$uart0tx$1223 Def000026
+S A$uart0tx$1214 Def00001E
+S A$uart0tx$1205 Def000012
+S A$uart0tx$1314 Def00006A
+S A$uart0tx$1251 Def000032
+S A$uart0tx$1206 Def000014
+S A$uart0tx$1315 Def00006D
+S A$uart0tx$1252 Def000034
+S A$uart0tx$1234 Def000031
+S A$uart0tx$1207 Def000015
+S A$uart0tx$1307 Def00005D
+S A$uart0tx$1262 Def000039
+S A$uart0tx$1253 Def000036
+S A$uart0tx$1217 Def000020
+S A$uart0tx$1208 Def000016
+S A$uart0tx$1190 Def000006
+S A$uart0tx$1308 Def00005F
+S A$uart0tx$1272 Def000047
+S A$uart0tx$1263 Def00003C
+S A$uart0tx$1227 Def000028
+S A$uart0tx$1209 Def000017
+S A$uart0tx$1318 Def00006F
+S A$uart0tx$1309 Def000062
+S A$uart0tx$1282 Def00004F
+S A$uart0tx$1264 Def00003E
+S A$uart0tx$1228 Def000029
+S A$uart0tx$1283 Def000050
+S A$uart0tx$1229 Def00002B
+S A$uart0tx$1193 Def000008
+S A$uart0tx$1194 Def00000A
+S A$uart0tx$1276 Def00004A
+S A$uart0tx$1267 Def000040
+S A$uart0tx$1195 Def00000C
+S A$uart0tx$1286 Def000052
+S A$uart0tx$1277 Def00004B
+S A$uart0tx$1268 Def000043
+S A$uart0tx$1259 Def000037
+S A$uart0tx$1187 Def000000
+S A$uart0tx$1278 Def00004D
+S A$uart0tx$1269 Def000045
+S A$uart0tx$1188 Def000002
+S A$uart0tx$1189 Def000004
+S A$uart0tx$1299 Def000053
+S C$uart0tx.c$31$2$61 Def000019
+S C$uart0tx.c$40$1$63 Def000032
+S C$uart0tx.c$32$2$61 Def000020
+S C$uart0tx.c$50$1$63 Def000052
+S C$uart0tx.c$33$2$61 Def000023
+S C$uart0tx.c$35$1$60 Def000028
+S C$uart0tx.c$26$1$60 Def000008
+S C$uart0tx.c$36$1$60 Def000031
+S C$uart0tx.c$52$1$63 Def000053
+S C$uart0tx.c$42$2$64 Def000037
+S C$uart0tx.c$38$1$60 Def000032
+S C$uart0tx.c$43$2$64 Def000039
+S C$uart0tx.c$28$2$61 Def00000D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 62
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 5E 02 0A 00 80
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 02 23 02 0D 01 5E
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 80
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A EF 42 A8 80 E8
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 00 3A 02 0E 01 8B
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:uart0tx
+F:G$uart0_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_wait_txfree$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart0tx.uart0_wait_txfree$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart0_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_wait_txdone$iesave$1$63({1}SC:U),R,0,0,[r7]
+F:G$uart0_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_tx$v$1$65({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1tx
+
+;!FILE libmf/uart1tx.asm
+XH3
+H 1A areas 327 global symbols
+M uart1tx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _uart1_txpoke Ref000000
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _uart1_poll Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S _uart1_txadvance Ref000000
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S _uart1_txidle Ref000000
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S _uart1_txfree Ref000000
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$uart1tx.c$43$2$64 Def000039
+S C$uart1tx.c$28$2$61 Def00000D
+S C$uart1tx.c$29$2$61 Def00000F
+S G$uart1_wait_txfree$0$0 Def000000
+S C$uart1tx.c$45$2$64 Def000040
+S C$uart1tx.c$54$1$66 Def000057
+S C$uart1tx.c$46$2$64 Def000047
+S C$uart1tx.c$24$0$0 Def000000
+S C$uart1tx.c$55$1$66 Def00005D
+S C$uart1tx.c$47$2$64 Def00004A
+S C$uart1tx.c$49$1$63 Def00004F
+S C$uart1tx.c$56$1$66 Def000067
+S G$uart1_wait_txdone$0$0 Def000032
+S C$uart1tx.c$57$1$66 Def00006F
+S G$uart1_tx$0$0 Def000053
+S _uart1_wait_txfree Def000000
+S _uart1_wait_txdone Def000032
+S _uart1_tx Def000053
+S XG$uart1_wait_txfree$0$0 Def000031
+S XG$uart1_wait_txdone$0$0 Def000052
+S XG$uart1_tx$0$0 Def00006F
+S A$uart1tx$1300 Def000055
+S A$uart1tx$1201 Def00000D
+S A$uart1tx$1310 Def000065
+S A$uart1tx$1230 Def00002D
+S A$uart1tx$1221 Def000023
+S A$uart1tx$1212 Def000019
+S A$uart1tx$1303 Def000057
+S A$uart1tx$1231 Def00002F
+S A$uart1tx$1222 Def000024
+S A$uart1tx$1213 Def00001C
+S A$uart1tx$1204 Def00000F
+S A$uart1tx$1313 Def000067
+S A$uart1tx$1304 Def00005A
+S A$uart1tx$1223 Def000026
+S A$uart1tx$1214 Def00001E
+S A$uart1tx$1205 Def000012
+S A$uart1tx$1314 Def00006A
+S A$uart1tx$1251 Def000032
+S A$uart1tx$1206 Def000014
+S A$uart1tx$1315 Def00006D
+S A$uart1tx$1252 Def000034
+S A$uart1tx$1234 Def000031
+S A$uart1tx$1207 Def000015
+S A$uart1tx$1307 Def00005D
+S A$uart1tx$1262 Def000039
+S A$uart1tx$1253 Def000036
+S A$uart1tx$1217 Def000020
+S A$uart1tx$1208 Def000016
+S A$uart1tx$1190 Def000006
+S A$uart1tx$1308 Def00005F
+S A$uart1tx$1272 Def000047
+S A$uart1tx$1263 Def00003C
+S A$uart1tx$1227 Def000028
+S A$uart1tx$1209 Def000017
+S A$uart1tx$1318 Def00006F
+S A$uart1tx$1309 Def000062
+S A$uart1tx$1282 Def00004F
+S A$uart1tx$1264 Def00003E
+S A$uart1tx$1228 Def000029
+S A$uart1tx$1283 Def000050
+S A$uart1tx$1229 Def00002B
+S A$uart1tx$1193 Def000008
+S A$uart1tx$1194 Def00000A
+S A$uart1tx$1276 Def00004A
+S A$uart1tx$1267 Def000040
+S A$uart1tx$1195 Def00000C
+S A$uart1tx$1286 Def000052
+S A$uart1tx$1277 Def00004B
+S A$uart1tx$1268 Def000043
+S A$uart1tx$1259 Def000037
+S A$uart1tx$1187 Def000000
+S A$uart1tx$1278 Def00004D
+S A$uart1tx$1269 Def000045
+S A$uart1tx$1188 Def000002
+S A$uart1tx$1189 Def000004
+S A$uart1tx$1299 Def000053
+S C$uart1tx.c$31$2$61 Def000019
+S C$uart1tx.c$40$1$63 Def000032
+S C$uart1tx.c$32$2$61 Def000020
+S C$uart1tx.c$50$1$63 Def000052
+S C$uart1tx.c$33$2$61 Def000023
+S C$uart1tx.c$35$1$60 Def000028
+S C$uart1tx.c$26$1$60 Def000008
+S C$uart1tx.c$36$1$60 Def000031
+S C$uart1tx.c$52$1$63 Def000053
+S C$uart1tx.c$42$2$64 Def000037
+S C$uart1tx.c$38$1$60 Def000032
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 71
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 63 02 0A 00 80
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 02 34 02 0D 01 63
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 80
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A EF 42 A8 80 E8
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 00 44 02 0E 01 97
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:uart1tx
+F:G$uart1_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_wait_txfree$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart1tx.uart1_wait_txfree$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart1_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_wait_txdone$iesave$1$63({1}SC:U),R,0,0,[r7]
+F:G$uart1_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_tx$v$1$65({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0rx
+
+;!FILE libmf/uart0rx.asm
+XH3
+H 1A areas 309 global symbols
+M uart0rx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _uart0_poll Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S _uart0_rxadvance Ref000000
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S _uart0_rxpeek Ref000000
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S _uart0_rxcount Ref000000
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$uart0rx.c$24$0$0 Def000000
+S G$uart0_wait_rxcount$0$0 Def000000
+S G$uart0_rx$0$0 Def000032
+S _uart0_wait_rxcount Def000000
+S _uart0_rx Def000032
+S XG$uart0_wait_rxcount$0$0 Def000031
+S XG$uart0_rx$0$0 Def00004C
+S A$uart0rx$1210 Def000019
+S A$uart0rx$1220 Def000024
+S A$uart0rx$1211 Def00001C
+S A$uart0rx$1202 Def00000F
+S A$uart0rx$1221 Def000026
+S A$uart0rx$1212 Def00001E
+S A$uart0rx$1203 Def000012
+S A$uart0rx$1204 Def000014
+S A$uart0rx$1250 Def000034
+S A$uart0rx$1232 Def000031
+S A$uart0rx$1205 Def000015
+S A$uart0rx$1260 Def000045
+S A$uart0rx$1251 Def000037
+S A$uart0rx$1215 Def000020
+S A$uart0rx$1206 Def000016
+S A$uart0rx$1225 Def000028
+S A$uart0rx$1207 Def000017
+S A$uart0rx$1226 Def000029
+S A$uart0rx$1263 Def000048
+S A$uart0rx$1254 Def00003A
+S A$uart0rx$1227 Def00002B
+S A$uart0rx$1191 Def000008
+S A$uart0rx$1264 Def00004A
+S A$uart0rx$1255 Def00003D
+S A$uart0rx$1228 Def00002D
+S A$uart0rx$1219 Def000023
+S A$uart0rx$1192 Def00000A
+S A$uart0rx$1256 Def000040
+S A$uart0rx$1247 Def000032
+S A$uart0rx$1229 Def00002F
+S A$uart0rx$1193 Def00000C
+S A$uart0rx$1185 Def000000
+S A$uart0rx$1267 Def00004C
+S A$uart0rx$1186 Def000002
+S A$uart0rx$1259 Def000042
+S A$uart0rx$1187 Def000004
+S A$uart0rx$1188 Def000006
+S A$uart0rx$1199 Def00000D
+S C$uart0rx.c$31$2$61 Def000019
+S C$uart0rx.c$32$2$61 Def000020
+S C$uart0rx.c$41$1$63 Def000034
+S C$uart0rx.c$33$2$61 Def000023
+S C$uart0rx.c$35$1$60 Def000028
+S C$uart0rx.c$26$1$60 Def000008
+S C$uart0rx.c$42$1$63 Def00003A
+S C$uart0rx.c$36$1$60 Def000031
+S C$uart0rx.c$43$1$63 Def000042
+S C$uart0rx.c$44$1$63 Def000048
+S C$uart0rx.c$38$1$60 Def000032
+S C$uart0rx.c$45$1$63 Def00004C
+S C$uart0rx.c$28$2$61 Def00000D
+S C$uart0rx.c$29$2$61 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 B8
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 5D 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 02 6F 02 0B 01 78
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:uart0rx
+F:G$uart0_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0rx.uart0_wait_rxcount$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart0rx.uart0_wait_rxcount$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart0_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0rx.uart0_rx$x$1$63({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1rx
+
+;!FILE libmf/uart1rx.asm
+XH3
+H 1A areas 309 global symbols
+M uart1rx
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _uart1_poll Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S _uart1_rxadvance Ref000000
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S _uart1_rxpeek Ref000000
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _uart1_rxcount Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$uart1rx.c$24$0$0 Def000000
+S G$uart1_wait_rxcount$0$0 Def000000
+S G$uart1_rx$0$0 Def000032
+S _uart1_wait_rxcount Def000000
+S _uart1_rx Def000032
+S XG$uart1_wait_rxcount$0$0 Def000031
+S XG$uart1_rx$0$0 Def00004C
+S A$uart1rx$1210 Def000019
+S A$uart1rx$1220 Def000024
+S A$uart1rx$1211 Def00001C
+S A$uart1rx$1202 Def00000F
+S A$uart1rx$1221 Def000026
+S A$uart1rx$1212 Def00001E
+S A$uart1rx$1203 Def000012
+S A$uart1rx$1204 Def000014
+S A$uart1rx$1250 Def000034
+S A$uart1rx$1232 Def000031
+S A$uart1rx$1205 Def000015
+S A$uart1rx$1260 Def000045
+S A$uart1rx$1251 Def000037
+S A$uart1rx$1215 Def000020
+S A$uart1rx$1206 Def000016
+S A$uart1rx$1225 Def000028
+S A$uart1rx$1207 Def000017
+S A$uart1rx$1226 Def000029
+S A$uart1rx$1263 Def000048
+S A$uart1rx$1254 Def00003A
+S A$uart1rx$1227 Def00002B
+S A$uart1rx$1191 Def000008
+S A$uart1rx$1264 Def00004A
+S A$uart1rx$1255 Def00003D
+S A$uart1rx$1228 Def00002D
+S A$uart1rx$1219 Def000023
+S A$uart1rx$1192 Def00000A
+S A$uart1rx$1256 Def000040
+S A$uart1rx$1247 Def000032
+S A$uart1rx$1229 Def00002F
+S A$uart1rx$1193 Def00000C
+S A$uart1rx$1185 Def000000
+S A$uart1rx$1267 Def00004C
+S A$uart1rx$1186 Def000002
+S A$uart1rx$1259 Def000042
+S A$uart1rx$1187 Def000004
+S A$uart1rx$1188 Def000006
+S A$uart1rx$1199 Def00000D
+S C$uart1rx.c$31$2$61 Def000019
+S C$uart1rx.c$32$2$61 Def000020
+S C$uart1rx.c$41$1$63 Def000034
+S C$uart1rx.c$33$2$61 Def000023
+S C$uart1rx.c$35$1$60 Def000028
+S C$uart1rx.c$26$1$60 Def000008
+S C$uart1rx.c$42$1$63 Def00003A
+S C$uart1rx.c$36$1$60 Def000031
+S C$uart1rx.c$43$1$63 Def000042
+S C$uart1rx.c$44$1$63 Def000048
+S C$uart1rx.c$38$1$60 Def000032
+S C$uart1rx.c$45$1$63 Def00004C
+S C$uart1rx.c$28$2$61 Def00000D
+S C$uart1rx.c$29$2$61 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 C4
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 62 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 02 80 02 0B 01 81
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:uart1rx
+F:G$uart1_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1rx.uart1_wait_rxcount$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart1rx.uart1_wait_rxcount$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart1_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1rx.uart1_rx$x$1$63({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhexu16
+
+;!FILE libmf/uart0wrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M uart0wrhexu16
+O -mmcs51 --model-small
+S _uart0_txpokehex Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S XG$uart0_writehexu16$0$0 Def00003D
+S A$uart0wrhexu16$122 Def000009
+S C$uart0wrhexu16.c$30$1$60 Def00003D
+S A$uart0wrhexu16$150 Def000028
+S A$uart0wrhexu16$141 Def00001B
+S A$uart0wrhexu16$132 Def000015
+S A$uart0wrhexu16$123 Def00000B
+S A$uart0wrhexu16$160 Def000034
+S A$uart0wrhexu16$151 Def000029
+S A$uart0wrhexu16$142 Def00001D
+S A$uart0wrhexu16$124 Def00000D
+S C$uart0wrhexu16.c$23$1$60 Def000010
+S A$uart0wrhexu16$152 Def00002A
+S A$uart0wrhexu16$143 Def00001F
+S A$uart0wrhexu16$134 Def000017
+S A$uart0wrhexu16$125 Def00000E
+S A$uart0wrhexu16$116 Def000000
+S C$uart0wrhexu16.c$24$1$60 Def000015
+S A$uart0wrhexu16$153 Def00002C
+S A$uart0wrhexu16$144 Def000021
+S A$uart0wrhexu16$135 Def000018
+S A$uart0wrhexu16$117 Def000002
+S A$uart0wrhexu16$154 Def00002D
+S A$uart0wrhexu16$145 Def000024
+S A$uart0wrhexu16$118 Def000005
+S A$uart0wrhexu16$164 Def000036
+S A$uart0wrhexu16$155 Def00002E
+S A$uart0wrhexu16$128 Def000010
+S A$uart0wrhexu16$119 Def000007
+S C$uart0wrhexu16.c$25$2$61 Def00001A
+S A$uart0wrhexu16$165 Def000038
+S A$uart0wrhexu16$156 Def000030
+S A$uart0wrhexu16$138 Def00001A
+S A$uart0wrhexu16$129 Def000012
+S C$uart0wrhexu16.c$26$2$61 Def00001B
+S A$uart0wrhexu16$166 Def00003B
+S A$uart0wrhexu16$157 Def000031
+S A$uart0wrhexu16$148 Def000026
+S C$uart0wrhexu16.c$29$1$60 Def000036
+S C$uart0wrhexu16.c$27$2$61 Def000026
+S A$uart0wrhexu16$158 Def000032
+S A$uart0wrhexu16$149 Def000027
+S A$uart0wrhexu16$159 Def000033
+S C$uart0wrhexu16.c$21$1$0 Def000009
+S A$uart0wrhexu16$169 Def00003D
+S C$uart0wrhexu16.c$19$0$0 Def000000
+S G$uart0_writehexu16$0$0 Def000000
+S _uart0_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 01
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 03 F1 23 09 00 04
+
+
+M:uart0wrhexu16
+F:G$uart0_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wrhexu16.uart0_writehexu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart0wrhexu16.uart0_writehexu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart0wrhexu16.uart0_writehexu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart0wrhexu16.uart0_writehexu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhexu16
+
+;!FILE libmf/uart1wrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M uart1wrhexu16
+O -mmcs51 --model-small
+S _uart1_txpokehex Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S XG$uart1_writehexu16$0$0 Def00003D
+S A$uart1wrhexu16$122 Def000009
+S C$uart1wrhexu16.c$30$1$60 Def00003D
+S A$uart1wrhexu16$150 Def000028
+S A$uart1wrhexu16$141 Def00001B
+S A$uart1wrhexu16$132 Def000015
+S A$uart1wrhexu16$123 Def00000B
+S A$uart1wrhexu16$160 Def000034
+S A$uart1wrhexu16$151 Def000029
+S A$uart1wrhexu16$142 Def00001D
+S A$uart1wrhexu16$124 Def00000D
+S C$uart1wrhexu16.c$23$1$60 Def000010
+S A$uart1wrhexu16$152 Def00002A
+S A$uart1wrhexu16$143 Def00001F
+S A$uart1wrhexu16$134 Def000017
+S A$uart1wrhexu16$125 Def00000E
+S A$uart1wrhexu16$116 Def000000
+S C$uart1wrhexu16.c$24$1$60 Def000015
+S A$uart1wrhexu16$153 Def00002C
+S A$uart1wrhexu16$144 Def000021
+S A$uart1wrhexu16$135 Def000018
+S A$uart1wrhexu16$117 Def000002
+S A$uart1wrhexu16$154 Def00002D
+S A$uart1wrhexu16$145 Def000024
+S A$uart1wrhexu16$118 Def000005
+S A$uart1wrhexu16$164 Def000036
+S A$uart1wrhexu16$155 Def00002E
+S A$uart1wrhexu16$128 Def000010
+S A$uart1wrhexu16$119 Def000007
+S C$uart1wrhexu16.c$25$2$61 Def00001A
+S A$uart1wrhexu16$165 Def000038
+S A$uart1wrhexu16$156 Def000030
+S A$uart1wrhexu16$138 Def00001A
+S A$uart1wrhexu16$129 Def000012
+S C$uart1wrhexu16.c$26$2$61 Def00001B
+S A$uart1wrhexu16$166 Def00003B
+S A$uart1wrhexu16$157 Def000031
+S A$uart1wrhexu16$148 Def000026
+S C$uart1wrhexu16.c$29$1$60 Def000036
+S C$uart1wrhexu16.c$27$2$61 Def000026
+S A$uart1wrhexu16$158 Def000032
+S A$uart1wrhexu16$149 Def000027
+S A$uart1wrhexu16$159 Def000033
+S C$uart1wrhexu16.c$21$1$0 Def000009
+S A$uart1wrhexu16$169 Def00003D
+S C$uart1wrhexu16.c$19$0$0 Def000000
+S G$uart1_writehexu16$0$0 Def000000
+S _uart1_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 01
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 03 F1 23 09 00 04
+
+
+M:uart1wrhexu16
+F:G$uart1_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wrhexu16.uart1_writehexu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart1wrhexu16.uart1_writehexu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart1wrhexu16.uart1_writehexu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart1wrhexu16.uart1_writehexu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhexu32
+
+;!FILE libmf/uart0wrhexu32.asm
+XH3
+H 1A areas 43 global symbols
+M uart0wrhexu32
+O -mmcs51 --model-small
+S _uart0_txpokehex Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S _uart0_writehexu32_PARM_2 Def000000
+S Luart0wrhexu32.uart0_writehexu32$nrdig$1$59 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 49 flags 20 addr 0
+S XG$uart0_writehexu32$0$0 Def000048
+S A$uart0wrhexu32$120 Def000000
+S A$uart0wrhexu32$130 Def00000B
+S A$uart0wrhexu32$121 Def000002
+S A$uart0wrhexu32$122 Def000004
+S C$uart0wrhexu32.c$30$1$60 Def000048
+S A$uart0wrhexu32$150 Def000020
+S A$uart0wrhexu32$123 Def000006
+S A$uart0wrhexu32$160 Def00002C
+S A$uart0wrhexu32$151 Def000021
+S A$uart0wrhexu32$142 Def000014
+S A$uart0wrhexu32$133 Def00000E
+S C$uart0wrhexu32.c$23$1$60 Def000009
+S A$uart0wrhexu32$170 Def000037
+S A$uart0wrhexu32$161 Def00002D
+S A$uart0wrhexu32$152 Def000022
+S A$uart0wrhexu32$143 Def000016
+S C$uart0wrhexu32.c$24$1$60 Def00000E
+S A$uart0wrhexu32$171 Def000039
+S A$uart0wrhexu32$162 Def00002E
+S A$uart0wrhexu32$153 Def000023
+S A$uart0wrhexu32$144 Def000018
+S A$uart0wrhexu32$135 Def000010
+S A$uart0wrhexu32$126 Def000007
+S A$uart0wrhexu32$172 Def00003A
+S A$uart0wrhexu32$163 Def00002F
+S A$uart0wrhexu32$154 Def000025
+S A$uart0wrhexu32$145 Def00001A
+S A$uart0wrhexu32$136 Def000011
+S A$uart0wrhexu32$182 Def000043
+S A$uart0wrhexu32$173 Def00003B
+S A$uart0wrhexu32$164 Def000031
+S A$uart0wrhexu32$155 Def000026
+S A$uart0wrhexu32$146 Def00001D
+S C$uart0wrhexu32.c$25$2$61 Def000013
+S A$uart0wrhexu32$183 Def000045
+S A$uart0wrhexu32$174 Def00003D
+S A$uart0wrhexu32$165 Def000032
+S A$uart0wrhexu32$156 Def000027
+S A$uart0wrhexu32$129 Def000009
+S C$uart0wrhexu32.c$26$2$61 Def000014
+S A$uart0wrhexu32$175 Def00003E
+S A$uart0wrhexu32$166 Def000033
+S A$uart0wrhexu32$157 Def000029
+S A$uart0wrhexu32$139 Def000013
+S C$uart0wrhexu32.c$29$1$60 Def000043
+S C$uart0wrhexu32.c$27$2$61 Def00001F
+S A$uart0wrhexu32$176 Def00003F
+S A$uart0wrhexu32$167 Def000034
+S A$uart0wrhexu32$158 Def00002A
+S A$uart0wrhexu32$149 Def00001F
+S A$uart0wrhexu32$186 Def000048
+S A$uart0wrhexu32$177 Def000040
+S A$uart0wrhexu32$168 Def000035
+S A$uart0wrhexu32$159 Def00002B
+S C$uart0wrhexu32.c$21$1$0 Def000007
+S A$uart0wrhexu32$178 Def000041
+S A$uart0wrhexu32$169 Def000036
+S C$uart0wrhexu32.c$19$0$0 Def000000
+S G$uart0_writehexu32$0$0 Def000000
+S _uart0_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 01
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 30 1A 8C 01 C0 01 8A 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 1D 15 81 ED C4 CC C4 54 0F 6C CC 54 0F CC
+R 00 00 00 16
+T 00 00 2A 6C CC FD EE C4 54 F0 4D FD EF C4 CE C4
+R 00 00 00 16
+T 00 00 37 54 0F 6E CE 54 0F CE 6E CE FF 80 CD
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 03
+
+
+M:uart0wrhexu32
+F:G$uart0_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart0wrhexu32.uart0_writehexu32$nrdig$1$59({1}SC:U),E,0,0
+S:Luart0wrhexu32.uart0_writehexu32$val$1$59({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Luart0wrhexu32.uart0_writehexu32$nrdig1$1$60({1}SC:U),R,0,0,[r3]
+S:Luart0wrhexu32.uart0_writehexu32$digit$1$60({1}SC:U),R,0,0,[r2]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhexu32
+
+;!FILE libmf/uart1wrhexu32.asm
+XH3
+H 1A areas 43 global symbols
+M uart1wrhexu32
+O -mmcs51 --model-small
+S _uart1_txpokehex Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S _uart1_writehexu32_PARM_2 Def000000
+S Luart1wrhexu32.uart1_writehexu32$nrdig$1$59 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 49 flags 20 addr 0
+S XG$uart1_writehexu32$0$0 Def000048
+S A$uart1wrhexu32$120 Def000000
+S A$uart1wrhexu32$130 Def00000B
+S A$uart1wrhexu32$121 Def000002
+S A$uart1wrhexu32$122 Def000004
+S C$uart1wrhexu32.c$30$1$60 Def000048
+S A$uart1wrhexu32$150 Def000020
+S A$uart1wrhexu32$123 Def000006
+S A$uart1wrhexu32$160 Def00002C
+S A$uart1wrhexu32$151 Def000021
+S A$uart1wrhexu32$142 Def000014
+S A$uart1wrhexu32$133 Def00000E
+S C$uart1wrhexu32.c$23$1$60 Def000009
+S A$uart1wrhexu32$170 Def000037
+S A$uart1wrhexu32$161 Def00002D
+S A$uart1wrhexu32$152 Def000022
+S A$uart1wrhexu32$143 Def000016
+S C$uart1wrhexu32.c$24$1$60 Def00000E
+S A$uart1wrhexu32$171 Def000039
+S A$uart1wrhexu32$162 Def00002E
+S A$uart1wrhexu32$153 Def000023
+S A$uart1wrhexu32$144 Def000018
+S A$uart1wrhexu32$135 Def000010
+S A$uart1wrhexu32$126 Def000007
+S A$uart1wrhexu32$172 Def00003A
+S A$uart1wrhexu32$163 Def00002F
+S A$uart1wrhexu32$154 Def000025
+S A$uart1wrhexu32$145 Def00001A
+S A$uart1wrhexu32$136 Def000011
+S A$uart1wrhexu32$182 Def000043
+S A$uart1wrhexu32$173 Def00003B
+S A$uart1wrhexu32$164 Def000031
+S A$uart1wrhexu32$155 Def000026
+S A$uart1wrhexu32$146 Def00001D
+S C$uart1wrhexu32.c$25$2$61 Def000013
+S A$uart1wrhexu32$183 Def000045
+S A$uart1wrhexu32$174 Def00003D
+S A$uart1wrhexu32$165 Def000032
+S A$uart1wrhexu32$156 Def000027
+S A$uart1wrhexu32$129 Def000009
+S C$uart1wrhexu32.c$26$2$61 Def000014
+S A$uart1wrhexu32$175 Def00003E
+S A$uart1wrhexu32$166 Def000033
+S A$uart1wrhexu32$157 Def000029
+S A$uart1wrhexu32$139 Def000013
+S C$uart1wrhexu32.c$29$1$60 Def000043
+S C$uart1wrhexu32.c$27$2$61 Def00001F
+S A$uart1wrhexu32$176 Def00003F
+S A$uart1wrhexu32$167 Def000034
+S A$uart1wrhexu32$158 Def00002A
+S A$uart1wrhexu32$149 Def00001F
+S A$uart1wrhexu32$186 Def000048
+S A$uart1wrhexu32$177 Def000040
+S A$uart1wrhexu32$168 Def000035
+S A$uart1wrhexu32$159 Def00002B
+S C$uart1wrhexu32.c$21$1$0 Def000007
+S A$uart1wrhexu32$178 Def000041
+S A$uart1wrhexu32$169 Def000036
+S C$uart1wrhexu32.c$19$0$0 Def000000
+S G$uart1_writehexu32$0$0 Def000000
+S _uart1_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 01
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 30 1A 8C 01 C0 01 8A 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 1D 15 81 ED C4 CC C4 54 0F 6C CC 54 0F CC
+R 00 00 00 16
+T 00 00 2A 6C CC FD EE C4 54 F0 4D FD EF C4 CE C4
+R 00 00 00 16
+T 00 00 37 54 0F 6E CE 54 0F CE 6E CE FF 80 CD
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 03
+
+
+M:uart1wrhexu32
+F:G$uart1_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart1wrhexu32.uart1_writehexu32$nrdig$1$59({1}SC:U),E,0,0
+S:Luart1wrhexu32.uart1_writehexu32$val$1$59({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Luart1wrhexu32.uart1_writehexu32$nrdig1$1$60({1}SC:U),R,0,0,[r3]
+S:Luart1wrhexu32.uart1_writehexu32$digit$1$60({1}SC:U),R,0,0,[r2]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrstr
+
+;!FILE libmf/uart0wrstr.asm
+XH3
+H 1A areas 51 global symbols
+M uart0wrstr
+O -mmcs51 --model-small
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+S _uart0_txbufptr Ref000000
+S _uart0_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S A$uart0wrstr$120 Def00000A
+S A$uart0wrstr$130 Def000018
+S A$uart0wrstr$121 Def00000D
+S A$uart0wrstr$140 Def000025
+S A$uart0wrstr$131 Def000019
+S A$uart0wrstr$113 Def000000
+S A$uart0wrstr$150 Def00002F
+S A$uart0wrstr$141 Def000026
+S A$uart0wrstr$132 Def00001A
+S A$uart0wrstr$123 Def000010
+S A$uart0wrstr$114 Def000002
+S A$uart0wrstr$160 Def000040
+S A$uart0wrstr$151 Def000031
+S A$uart0wrstr$142 Def000027
+S A$uart0wrstr$133 Def00001B
+S A$uart0wrstr$124 Def000011
+S A$uart0wrstr$115 Def000004
+S A$uart0wrstr$170 Def000054
+S A$uart0wrstr$161 Def000042
+S A$uart0wrstr$152 Def000032
+S A$uart0wrstr$143 Def000029
+S A$uart0wrstr$134 Def00001D
+S A$uart0wrstr$125 Def000012
+S A$uart0wrstr$116 Def000005
+S A$uart0wrstr$180 Def000064
+S A$uart0wrstr$171 Def000055
+S A$uart0wrstr$162 Def000044
+S A$uart0wrstr$153 Def000033
+S A$uart0wrstr$144 Def00002B
+S A$uart0wrstr$135 Def00001F
+S A$uart0wrstr$117 Def000006
+S A$uart0wrstr$190 Def000071
+S A$uart0wrstr$181 Def000065
+S A$uart0wrstr$172 Def000056
+S A$uart0wrstr$163 Def000046
+S A$uart0wrstr$154 Def000035
+S A$uart0wrstr$191 Def000073
+S A$uart0wrstr$182 Def000066
+S A$uart0wrstr$173 Def000058
+S A$uart0wrstr$164 Def000049
+S A$uart0wrstr$155 Def000036
+S A$uart0wrstr$128 Def000014
+S A$uart0wrstr$119 Def000007
+S A$uart0wrstr$183 Def000068
+S A$uart0wrstr$174 Def00005B
+S A$uart0wrstr$165 Def00004C
+S A$uart0wrstr$156 Def000038
+S A$uart0wrstr$147 Def00002D
+S A$uart0wrstr$138 Def000021
+S A$uart0wrstr$129 Def000016
+S A$uart0wrstr$184 Def00006A
+S A$uart0wrstr$175 Def00005D
+S A$uart0wrstr$166 Def00004E
+S A$uart0wrstr$157 Def00003A
+S A$uart0wrstr$148 Def00002E
+S A$uart0wrstr$139 Def000023
+S A$uart0wrstr$185 Def00006B
+S A$uart0wrstr$167 Def000051
+S A$uart0wrstr$195 Def000076
+S A$uart0wrstr$186 Def00006C
+S A$uart0wrstr$177 Def00005F
+S A$uart0wrstr$159 Def00003D
+S A$uart0wrstr$178 Def000061
+S A$uart0wrstr$169 Def000053
+S A$uart0wrstr$188 Def00006E
+S A$uart0wrstr$179 Def000063
+S A$uart0wrstr$189 Def00006F
+S C$uart0wrstr.c$27$0$0 Def000000
+S G$uart0_writestr$0$0 Def000000
+S _uart0_writestr Def000000
+S XG$uart0_writestr$0$0 Def000076
+S C$uart0wrstr.c$102$1$60 Def000000
+S C$uart0wrstr.c$103$1$60 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 07 F1 23 09 00 06
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 05
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 02
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 04
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 00 02 08 00 04
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 03
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 02
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:uart0wrstr
+F:G$uart0_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wrstr.uart0_writestr$ch$1$59({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrstr
+
+;!FILE libmf/uart1wrstr.asm
+XH3
+H 1A areas 51 global symbols
+M uart1wrstr
+O -mmcs51 --model-small
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+S _uart1_txbufptr Ref000000
+S _uart1_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S A$uart1wrstr$120 Def00000A
+S A$uart1wrstr$130 Def000018
+S A$uart1wrstr$121 Def00000D
+S A$uart1wrstr$140 Def000025
+S A$uart1wrstr$131 Def000019
+S A$uart1wrstr$113 Def000000
+S A$uart1wrstr$150 Def00002F
+S A$uart1wrstr$141 Def000026
+S A$uart1wrstr$132 Def00001A
+S A$uart1wrstr$123 Def000010
+S A$uart1wrstr$114 Def000002
+S A$uart1wrstr$160 Def000040
+S A$uart1wrstr$151 Def000031
+S A$uart1wrstr$142 Def000027
+S A$uart1wrstr$133 Def00001B
+S A$uart1wrstr$124 Def000011
+S A$uart1wrstr$115 Def000004
+S A$uart1wrstr$170 Def000054
+S A$uart1wrstr$161 Def000042
+S A$uart1wrstr$152 Def000032
+S A$uart1wrstr$143 Def000029
+S A$uart1wrstr$134 Def00001D
+S A$uart1wrstr$125 Def000012
+S A$uart1wrstr$116 Def000005
+S A$uart1wrstr$180 Def000064
+S A$uart1wrstr$171 Def000055
+S A$uart1wrstr$162 Def000044
+S A$uart1wrstr$153 Def000033
+S A$uart1wrstr$144 Def00002B
+S A$uart1wrstr$135 Def00001F
+S A$uart1wrstr$117 Def000006
+S A$uart1wrstr$190 Def000071
+S A$uart1wrstr$181 Def000065
+S A$uart1wrstr$172 Def000056
+S A$uart1wrstr$163 Def000046
+S A$uart1wrstr$154 Def000035
+S A$uart1wrstr$191 Def000073
+S A$uart1wrstr$182 Def000066
+S A$uart1wrstr$173 Def000058
+S A$uart1wrstr$164 Def000049
+S A$uart1wrstr$155 Def000036
+S A$uart1wrstr$128 Def000014
+S A$uart1wrstr$119 Def000007
+S A$uart1wrstr$183 Def000068
+S A$uart1wrstr$174 Def00005B
+S A$uart1wrstr$165 Def00004C
+S A$uart1wrstr$156 Def000038
+S A$uart1wrstr$147 Def00002D
+S A$uart1wrstr$138 Def000021
+S A$uart1wrstr$129 Def000016
+S A$uart1wrstr$184 Def00006A
+S A$uart1wrstr$175 Def00005D
+S A$uart1wrstr$166 Def00004E
+S A$uart1wrstr$157 Def00003A
+S A$uart1wrstr$148 Def00002E
+S A$uart1wrstr$139 Def000023
+S A$uart1wrstr$185 Def00006B
+S A$uart1wrstr$167 Def000051
+S A$uart1wrstr$195 Def000076
+S A$uart1wrstr$186 Def00006C
+S A$uart1wrstr$177 Def00005F
+S A$uart1wrstr$159 Def00003D
+S A$uart1wrstr$178 Def000061
+S A$uart1wrstr$169 Def000053
+S A$uart1wrstr$188 Def00006E
+S A$uart1wrstr$179 Def000063
+S A$uart1wrstr$189 Def00006F
+S C$uart1wrstr.c$27$0$0 Def000000
+S G$uart1_writestr$0$0 Def000000
+S _uart1_writestr Def000000
+S XG$uart1_writestr$0$0 Def000076
+S C$uart1wrstr.c$102$1$60 Def000000
+S C$uart1wrstr.c$103$1$60 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 07 F1 23 09 00 06
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 05
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 02
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 04
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 00 02 08 00 04
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 03
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 02
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:uart1wrstr
+F:G$uart1_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wrstr.uart1_writestr$ch$1$59({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wru16
+
+;!FILE libmf/uart0wru16.asm
+XH3
+H 1A areas 46 global symbols
+M uart0wru16
+O -mmcs51 --model-small
+S __divuint Ref000000
+S _uart0_txpoke Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _uart0_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$uart0wru16$120 Def000007
+S A$uart0wru16$130 Def000012
+S A$uart0wru16$150 Def00002F
+S A$uart0wru16$123 Def000009
+S C$uart0wru16.c$31$1$60 Def000055
+S A$uart0wru16$160 Def00003F
+S A$uart0wru16$151 Def000031
+S A$uart0wru16$142 Def00001C
+S A$uart0wru16$133 Def000015
+S A$uart0wru16$124 Def00000B
+S C$uart0wru16.c$32$1$60 Def00005C
+S C$uart0wru16.c$23$1$60 Def000010
+S A$uart0wru16$161 Def000040
+S A$uart0wru16$152 Def000033
+S A$uart0wru16$143 Def00001F
+S A$uart0wru16$125 Def00000D
+S C$uart0wru16.c$24$1$60 Def000015
+S A$uart0wru16$171 Def000046
+S A$uart0wru16$162 Def000041
+S A$uart0wru16$153 Def000035
+S A$uart0wru16$144 Def000022
+S A$uart0wru16$135 Def000017
+S A$uart0wru16$126 Def00000E
+S A$uart0wru16$117 Def000000
+S A$uart0wru16$172 Def000048
+S A$uart0wru16$163 Def000042
+S A$uart0wru16$154 Def000037
+S A$uart0wru16$145 Def000024
+S A$uart0wru16$136 Def000018
+S A$uart0wru16$118 Def000002
+S C$uart0wru16.c$26$1$60 Def00001C
+S C$uart0wru16.c$25$2$60 Def00001A
+S A$uart0wru16$182 Def000055
+S A$uart0wru16$173 Def000049
+S A$uart0wru16$164 Def000043
+S A$uart0wru16$146 Def000026
+S A$uart0wru16$119 Def000005
+S A$uart0wru16$183 Def000057
+S A$uart0wru16$174 Def00004A
+S A$uart0wru16$165 Def000044
+S A$uart0wru16$147 Def000028
+S A$uart0wru16$129 Def000010
+S A$uart0wru16$184 Def00005A
+S A$uart0wru16$175 Def00004C
+S A$uart0wru16$157 Def000039
+S A$uart0wru16$148 Def00002A
+S A$uart0wru16$139 Def00001A
+S C$uart0wru16.c$27$2$61 Def000039
+S A$uart0wru16$176 Def00004E
+S A$uart0wru16$158 Def00003B
+S A$uart0wru16$149 Def00002C
+S C$uart0wru16.c$28$2$61 Def000045
+S A$uart0wru16$177 Def000051
+S A$uart0wru16$168 Def000045
+S A$uart0wru16$159 Def00003C
+S C$uart0wru16.c$29$2$61 Def000046
+S C$uart0wru16.c$21$1$0 Def000009
+S A$uart0wru16$187 Def00005C
+S A$uart0wru16$178 Def000053
+S C$uart0wru16.c$19$0$0 Def000000
+S G$uart0_writeu16$0$0 Def000000
+S _uart0_writeu16 Def000000
+S XG$uart0_writeu16$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 06
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 02
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3B 8E 03 75 00 00 00 0A 75
+R 00 00 00 16 F1 23 09 00 04
+T 00 00 20 00 00 01 00 8E 82 8F 83 C0 05 C0 04 C0
+R 00 00 00 16 F1 23 03 00 04
+T 00 00 2B 03 12 00 00 AE 82 AF 83 D0 03 D0 04 D0
+R 00 00 00 16 02 05 00 00
+T 00 00 38 05 8E 02 EA 75 F0 0A A4 FA EB C3 9A FB
+R 00 00 00 16
+T 00 00 45 1C 74 30 2B FB C0 03 8C 82 12 00 00 15
+R 00 00 00 16 02 0D 00 01
+T 00 00 52 81 80 C2
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 05 F1 23 09 00 06
+
+
+M:uart0wru16
+F:G$uart0_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wru16.uart0_writeu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart0wru16.uart0_writeu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart0wru16.uart0_writeu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart0wru16.uart0_writeu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:Luart0wru16.uart0_writeu16$v1$2$61({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wru16
+
+;!FILE libmf/uart1wru16.asm
+XH3
+H 1A areas 46 global symbols
+M uart1wru16
+O -mmcs51 --model-small
+S __divuint Ref000000
+S _uart1_txpoke Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _uart1_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$uart1wru16$120 Def000007
+S A$uart1wru16$130 Def000012
+S A$uart1wru16$150 Def00002F
+S A$uart1wru16$123 Def000009
+S C$uart1wru16.c$31$1$60 Def000055
+S A$uart1wru16$160 Def00003F
+S A$uart1wru16$151 Def000031
+S A$uart1wru16$142 Def00001C
+S A$uart1wru16$133 Def000015
+S A$uart1wru16$124 Def00000B
+S C$uart1wru16.c$32$1$60 Def00005C
+S C$uart1wru16.c$23$1$60 Def000010
+S A$uart1wru16$161 Def000040
+S A$uart1wru16$152 Def000033
+S A$uart1wru16$143 Def00001F
+S A$uart1wru16$125 Def00000D
+S C$uart1wru16.c$24$1$60 Def000015
+S A$uart1wru16$171 Def000046
+S A$uart1wru16$162 Def000041
+S A$uart1wru16$153 Def000035
+S A$uart1wru16$144 Def000022
+S A$uart1wru16$135 Def000017
+S A$uart1wru16$126 Def00000E
+S A$uart1wru16$117 Def000000
+S A$uart1wru16$172 Def000048
+S A$uart1wru16$163 Def000042
+S A$uart1wru16$154 Def000037
+S A$uart1wru16$145 Def000024
+S A$uart1wru16$136 Def000018
+S A$uart1wru16$118 Def000002
+S C$uart1wru16.c$26$1$60 Def00001C
+S C$uart1wru16.c$25$2$60 Def00001A
+S A$uart1wru16$182 Def000055
+S A$uart1wru16$173 Def000049
+S A$uart1wru16$164 Def000043
+S A$uart1wru16$146 Def000026
+S A$uart1wru16$119 Def000005
+S A$uart1wru16$183 Def000057
+S A$uart1wru16$174 Def00004A
+S A$uart1wru16$165 Def000044
+S A$uart1wru16$147 Def000028
+S A$uart1wru16$129 Def000010
+S A$uart1wru16$184 Def00005A
+S A$uart1wru16$175 Def00004C
+S A$uart1wru16$157 Def000039
+S A$uart1wru16$148 Def00002A
+S A$uart1wru16$139 Def00001A
+S C$uart1wru16.c$27$2$61 Def000039
+S A$uart1wru16$176 Def00004E
+S A$uart1wru16$158 Def00003B
+S A$uart1wru16$149 Def00002C
+S C$uart1wru16.c$28$2$61 Def000045
+S A$uart1wru16$177 Def000051
+S A$uart1wru16$168 Def000045
+S A$uart1wru16$159 Def00003C
+S C$uart1wru16.c$29$2$61 Def000046
+S C$uart1wru16.c$21$1$0 Def000009
+S A$uart1wru16$187 Def00005C
+S A$uart1wru16$178 Def000053
+S C$uart1wru16.c$19$0$0 Def000000
+S G$uart1_writeu16$0$0 Def000000
+S _uart1_writeu16 Def000000
+S XG$uart1_writeu16$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 06
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 02
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3B 8E 03 75 00 00 00 0A 75
+R 00 00 00 16 F1 23 09 00 04
+T 00 00 20 00 00 01 00 8E 82 8F 83 C0 05 C0 04 C0
+R 00 00 00 16 F1 23 03 00 04
+T 00 00 2B 03 12 00 00 AE 82 AF 83 D0 03 D0 04 D0
+R 00 00 00 16 02 05 00 00
+T 00 00 38 05 8E 02 EA 75 F0 0A A4 FA EB C3 9A FB
+R 00 00 00 16
+T 00 00 45 1C 74 30 2B FB C0 03 8C 82 12 00 00 15
+R 00 00 00 16 02 0D 00 01
+T 00 00 52 81 80 C2
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 05 F1 23 09 00 06
+
+
+M:uart1wru16
+F:G$uart1_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wru16.uart1_writeu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart1wru16.uart1_writeu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart1wru16.uart1_writeu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart1wru16.uart1_writeu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:Luart1wru16.uart1_writeu16$v1$2$61({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wru32
+
+;!FILE libmf/uart0wru32.asm
+XH3
+H 1A areas 49 global symbols
+M uart0wru32
+O -mmcs51 --model-small
+S _uart0_txpoke Ref000000
+S __divulong_PARM_2 Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _uart0_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S _uart0_writeu32_PARM_2 Def000000
+S Luart0wru32.uart0_writeu32$nrdig$1$59 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$uart0wru32$130 Def000009
+S A$uart0wru32$121 Def000000
+S A$uart0wru32$140 Def000013
+S A$uart0wru32$131 Def00000B
+S A$uart0wru32$122 Def000002
+S A$uart0wru32$150 Def000023
+S A$uart0wru32$123 Def000004
+S C$uart0wru32.c$31$1$60 Def000057
+S A$uart0wru32$160 Def000036
+S A$uart0wru32$151 Def000025
+S A$uart0wru32$124 Def000006
+S C$uart0wru32.c$32$1$60 Def00005C
+S C$uart0wru32.c$23$1$60 Def000009
+S A$uart0wru32$170 Def000044
+S A$uart0wru32$161 Def000038
+S A$uart0wru32$152 Def000026
+S A$uart0wru32$143 Def000015
+S A$uart0wru32$134 Def00000E
+S C$uart0wru32.c$24$1$60 Def00000E
+S A$uart0wru32$180 Def00004B
+S A$uart0wru32$171 Def000045
+S A$uart0wru32$162 Def00003A
+S A$uart0wru32$153 Def000028
+S A$uart0wru32$144 Def000018
+S A$uart0wru32$190 Def000059
+S A$uart0wru32$181 Def00004C
+S A$uart0wru32$172 Def000046
+S A$uart0wru32$154 Def00002A
+S A$uart0wru32$145 Def000019
+S A$uart0wru32$136 Def000010
+S A$uart0wru32$127 Def000007
+S C$uart0wru32.c$26$1$60 Def000015
+S C$uart0wru32.c$25$2$60 Def000013
+S A$uart0wru32$182 Def00004E
+S A$uart0wru32$155 Def00002C
+S A$uart0wru32$146 Def00001B
+S A$uart0wru32$137 Def000011
+S A$uart0wru32$183 Def000050
+S A$uart0wru32$165 Def00003C
+S A$uart0wru32$156 Def00002F
+S A$uart0wru32$147 Def00001D
+S A$uart0wru32$193 Def00005C
+S A$uart0wru32$184 Def000053
+S A$uart0wru32$175 Def000047
+S A$uart0wru32$166 Def00003E
+S A$uart0wru32$157 Def000031
+S A$uart0wru32$148 Def00001F
+S C$uart0wru32.c$27$2$61 Def00003C
+S A$uart0wru32$185 Def000055
+S A$uart0wru32$167 Def00003F
+S A$uart0wru32$158 Def000033
+S A$uart0wru32$149 Def000021
+S C$uart0wru32.c$28$2$61 Def000047
+S A$uart0wru32$168 Def000042
+S A$uart0wru32$159 Def000035
+S C$uart0wru32.c$29$2$61 Def000048
+S C$uart0wru32.c$21$1$0 Def000007
+S A$uart0wru32$178 Def000048
+S A$uart0wru32$169 Def000043
+S A$uart0wru32$179 Def00004A
+S A$uart0wru32$189 Def000057
+S C$uart0wru32.c$19$0$0 Def000000
+S G$uart0_writeu32$0$0 Def000000
+S _uart0_writeu32 Def000000
+S XG$uart0_writeu32$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 02
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 44 8C 01 75 00 00 00 0A E4 F5
+R 00 00 00 16 F1 23 09 00 01
+T 00 00 1A 00 00 01 F5 00 00 02 F5
+R 00 00 00 16 F1 23 03 00 01 F1 23 07 00 01
+T 00 00 1E 00 00 03 8C 82 8D 83 8E F0 EF C0 03 C0
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 29 02 C0 01 12 00 00 AC 82 AD 83 AE F0 FF
+R 00 00 00 16 02 07 00 04
+T 00 00 36 D0 01 D0 02 D0 03 8C 00 E8 75 F0 0A A4
+R 00 00 00 16
+T 00 00 43 D3 99 F4 F9 1A 74 30 29 F9 C0 01 8A 82
+R 00 00 00 16
+T 00 00 50 12 00 00 15 81 80 B9
+R 00 00 00 16 02 04 00 00
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 05
+
+
+M:uart0wru32
+F:G$uart0_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart0wru32.uart0_writeu32$nrdig$1$59({1}SC:U),E,0,0
+S:Luart0wru32.uart0_writeu32$val$1$59({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Luart0wru32.uart0_writeu32$nrdig1$1$60({1}SC:U),R,0,0,[r3]
+S:Luart0wru32.uart0_writeu32$digit$1$60({1}SC:U),R,0,0,[r2]
+S:Luart0wru32.uart0_writeu32$v1$2$61({1}SC:U),R,0,0,[r1]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wru32
+
+;!FILE libmf/uart1wru32.asm
+XH3
+H 1A areas 49 global symbols
+M uart1wru32
+O -mmcs51 --model-small
+S __divulong_PARM_2 Ref000000
+S _uart1_txpoke Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _uart1_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 1 flags 0 addr 0
+S _uart1_writeu32_PARM_2 Def000000
+S Luart1wru32.uart1_writeu32$nrdig$1$59 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S A$uart1wru32$130 Def000009
+S A$uart1wru32$121 Def000000
+S A$uart1wru32$140 Def000013
+S A$uart1wru32$131 Def00000B
+S A$uart1wru32$122 Def000002
+S A$uart1wru32$150 Def000023
+S A$uart1wru32$123 Def000004
+S C$uart1wru32.c$31$1$60 Def000057
+S A$uart1wru32$160 Def000036
+S A$uart1wru32$151 Def000025
+S A$uart1wru32$124 Def000006
+S C$uart1wru32.c$32$1$60 Def00005C
+S C$uart1wru32.c$23$1$60 Def000009
+S A$uart1wru32$170 Def000044
+S A$uart1wru32$161 Def000038
+S A$uart1wru32$152 Def000026
+S A$uart1wru32$143 Def000015
+S A$uart1wru32$134 Def00000E
+S C$uart1wru32.c$24$1$60 Def00000E
+S A$uart1wru32$180 Def00004B
+S A$uart1wru32$171 Def000045
+S A$uart1wru32$162 Def00003A
+S A$uart1wru32$153 Def000028
+S A$uart1wru32$144 Def000018
+S A$uart1wru32$190 Def000059
+S A$uart1wru32$181 Def00004C
+S A$uart1wru32$172 Def000046
+S A$uart1wru32$154 Def00002A
+S A$uart1wru32$145 Def000019
+S A$uart1wru32$136 Def000010
+S A$uart1wru32$127 Def000007
+S C$uart1wru32.c$26$1$60 Def000015
+S C$uart1wru32.c$25$2$60 Def000013
+S A$uart1wru32$182 Def00004E
+S A$uart1wru32$155 Def00002C
+S A$uart1wru32$146 Def00001B
+S A$uart1wru32$137 Def000011
+S A$uart1wru32$183 Def000050
+S A$uart1wru32$165 Def00003C
+S A$uart1wru32$156 Def00002F
+S A$uart1wru32$147 Def00001D
+S A$uart1wru32$193 Def00005C
+S A$uart1wru32$184 Def000053
+S A$uart1wru32$175 Def000047
+S A$uart1wru32$166 Def00003E
+S A$uart1wru32$157 Def000031
+S A$uart1wru32$148 Def00001F
+S C$uart1wru32.c$27$2$61 Def00003C
+S A$uart1wru32$185 Def000055
+S A$uart1wru32$167 Def00003F
+S A$uart1wru32$158 Def000033
+S A$uart1wru32$149 Def000021
+S C$uart1wru32.c$28$2$61 Def000047
+S A$uart1wru32$168 Def000042
+S A$uart1wru32$159 Def000035
+S C$uart1wru32.c$29$2$61 Def000048
+S C$uart1wru32.c$21$1$0 Def000007
+S A$uart1wru32$178 Def000048
+S A$uart1wru32$169 Def000043
+S A$uart1wru32$179 Def00004A
+S A$uart1wru32$189 Def000057
+S C$uart1wru32.c$19$0$0 Def000000
+S G$uart1_writeu32$0$0 Def000000
+S _uart1_writeu32 Def000000
+S XG$uart1_writeu32$0$0 Def00005C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AC 82 AD 83 AE F0 FF AB 00 00 00 8B 82
+R 00 00 00 16 F1 21 0B 00 05
+T 00 00 0B 12 00 00 8B 02
+R 00 00 00 16 02 04 00 02
+T 00 00 10
+R 00 00 00 16
+T 00 00 10 EA 60 44 8C 01 75 00 00 00 0A E4 F5
+R 00 00 00 16 F1 23 09 00 00
+T 00 00 1A 00 00 01 F5 00 00 02 F5
+R 00 00 00 16 F1 23 03 00 00 F1 23 07 00 00
+T 00 00 1E 00 00 03 8C 82 8D 83 8E F0 EF C0 03 C0
+R 00 00 00 16 F1 23 03 00 00
+T 00 00 29 02 C0 01 12 00 00 AC 82 AD 83 AE F0 FF
+R 00 00 00 16 02 07 00 04
+T 00 00 36 D0 01 D0 02 D0 03 8C 00 E8 75 F0 0A A4
+R 00 00 00 16
+T 00 00 43 D3 99 F4 F9 1A 74 30 29 F9 C0 01 8A 82
+R 00 00 00 16
+T 00 00 50 12 00 00 15 81 80 B9
+R 00 00 00 16 02 04 00 01
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 8B 82 12 00 00 22
+R 00 00 00 16 02 06 00 05
+
+
+M:uart1wru32
+F:G$uart1_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart1wru32.uart1_writeu32$nrdig$1$59({1}SC:U),E,0,0
+S:Luart1wru32.uart1_writeu32$val$1$59({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Luart1wru32.uart1_writeu32$nrdig1$1$60({1}SC:U),R,0,0,[r3]
+S:Luart1wru32.uart1_writeu32$digit$1$60({1}SC:U),R,0,0,[r2]
+S:Luart1wru32.uart1_writeu32$v1$2$61({1}SC:U),R,0,0,[r1]
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrnum16
+
+;!FILE libmf/uart0wrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M uart0wrnum16
+O -mmcs51 --model-small
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S G$uart0_writenum16$0$0 Def000000
+S _uart0_writenum16 Def000000
+S XG$uart0_writenum16$0$0 Def0000F6
+S C$uart0wrnum16.c$240$1$62 Def000000
+S C$uart0wrnum16.c$241$1$62 Def0000F6
+S A$uart0wrnum16$200 Def000059
+S A$uart0wrnum16$300 Def0000D9
+S A$uart0wrnum16$210 Def000065
+S A$uart0wrnum16$201 Def00005A
+S A$uart0wrnum16$120 Def000005
+S A$uart0wrnum16$310 Def0000ED
+S A$uart0wrnum16$301 Def0000DC
+S A$uart0wrnum16$220 Def000070
+S A$uart0wrnum16$211 Def000066
+S A$uart0wrnum16$202 Def00005C
+S A$uart0wrnum16$121 Def000006
+S A$uart0wrnum16$311 Def0000EF
+S A$uart0wrnum16$302 Def0000DD
+S A$uart0wrnum16$230 Def000080
+S A$uart0wrnum16$203 Def00005D
+S A$uart0wrnum16$140 Def000014
+S A$uart0wrnum16$122 Def000007
+S A$uart0wrnum16$312 Def0000F1
+S A$uart0wrnum16$303 Def0000DF
+S A$uart0wrnum16$240 Def000090
+S A$uart0wrnum16$231 Def000082
+S A$uart0wrnum16$213 Def000068
+S A$uart0wrnum16$204 Def00005E
+S A$uart0wrnum16$150 Def000026
+S A$uart0wrnum16$141 Def000016
+S A$uart0wrnum16$132 Def00000F
+S A$uart0wrnum16$123 Def000009
+S A$uart0wrnum16$241 Def000092
+S A$uart0wrnum16$205 Def000060
+S A$uart0wrnum16$142 Def000019
+S A$uart0wrnum16$314 Def0000F3
+S A$uart0wrnum16$305 Def0000E1
+S A$uart0wrnum16$242 Def000095
+S A$uart0wrnum16$233 Def000084
+S A$uart0wrnum16$224 Def000072
+S A$uart0wrnum16$215 Def00006B
+S A$uart0wrnum16$152 Def000028
+S A$uart0wrnum16$143 Def00001A
+S A$uart0wrnum16$125 Def00000B
+S A$uart0wrnum16$306 Def0000E3
+S A$uart0wrnum16$270 Def0000AE
+S A$uart0wrnum16$261 Def0000A4
+S A$uart0wrnum16$243 Def000098
+S A$uart0wrnum16$234 Def000087
+S A$uart0wrnum16$225 Def000074
+S A$uart0wrnum16$162 Def000036
+S A$uart0wrnum16$153 Def00002B
+S A$uart0wrnum16$144 Def00001B
+S A$uart0wrnum16$126 Def00000C
+S A$uart0wrnum16$117 Def000000
+S A$uart0wrnum16$316 Def0000F4
+S A$uart0wrnum16$307 Def0000E5
+S A$uart0wrnum16$280 Def0000BE
+S A$uart0wrnum16$244 Def00009A
+S A$uart0wrnum16$235 Def000088
+S A$uart0wrnum16$226 Def000076
+S A$uart0wrnum16$217 Def00006E
+S A$uart0wrnum16$208 Def000063
+S A$uart0wrnum16$163 Def000037
+S A$uart0wrnum16$154 Def00002E
+S A$uart0wrnum16$145 Def00001D
+S A$uart0wrnum16$118 Def000002
+S A$uart0wrnum16$308 Def0000E7
+S A$uart0wrnum16$290 Def0000C7
+S A$uart0wrnum16$281 Def0000C0
+S A$uart0wrnum16$272 Def0000B0
+S A$uart0wrnum16$263 Def0000A7
+S A$uart0wrnum16$245 Def00009C
+S A$uart0wrnum16$236 Def00008A
+S A$uart0wrnum16$227 Def000078
+S A$uart0wrnum16$218 Def00006F
+S A$uart0wrnum16$209 Def000064
+S A$uart0wrnum16$182 Def000047
+S A$uart0wrnum16$173 Def00003E
+S A$uart0wrnum16$164 Def000039
+S A$uart0wrnum16$155 Def000030
+S A$uart0wrnum16$146 Def00001F
+S A$uart0wrnum16$128 Def00000D
+S A$uart0wrnum16$119 Def000004
+S A$uart0wrnum16$309 Def0000EA
+S A$uart0wrnum16$291 Def0000C9
+S A$uart0wrnum16$282 Def0000C2
+S A$uart0wrnum16$273 Def0000B1
+S A$uart0wrnum16$255 Def00009F
+S A$uart0wrnum16$228 Def00007B
+S A$uart0wrnum16$192 Def00004E
+S A$uart0wrnum16$183 Def000048
+S A$uart0wrnum16$174 Def000041
+S A$uart0wrnum16$165 Def00003A
+S A$uart0wrnum16$156 Def000032
+S A$uart0wrnum16$147 Def000020
+S A$uart0wrnum16$292 Def0000CB
+S A$uart0wrnum16$265 Def0000AA
+S A$uart0wrnum16$247 Def00009E
+S A$uart0wrnum16$238 Def00008C
+S A$uart0wrnum16$229 Def00007E
+S A$uart0wrnum16$193 Def00004F
+S A$uart0wrnum16$184 Def000049
+S A$uart0wrnum16$175 Def000042
+S A$uart0wrnum16$166 Def00003C
+S A$uart0wrnum16$148 Def000022
+S A$uart0wrnum16$139 Def000011
+S A$uart0wrnum16$293 Def0000CC
+S A$uart0wrnum16$284 Def0000C4
+S A$uart0wrnum16$275 Def0000B3
+S A$uart0wrnum16$266 Def0000AB
+S A$uart0wrnum16$257 Def0000A1
+S A$uart0wrnum16$239 Def00008E
+S A$uart0wrnum16$185 Def00004A
+S A$uart0wrnum16$176 Def000044
+S A$uart0wrnum16$167 Def00003D
+S A$uart0wrnum16$158 Def000034
+S A$uart0wrnum16$149 Def000024
+S A$uart0wrnum16$294 Def0000CE
+S A$uart0wrnum16$276 Def0000B5
+S A$uart0wrnum16$258 Def0000A3
+S A$uart0wrnum16$195 Def000050
+S A$uart0wrnum16$186 Def00004C
+S A$uart0wrnum16$177 Def000046
+S A$uart0wrnum16$295 Def0000D0
+S A$uart0wrnum16$277 Def0000B7
+S A$uart0wrnum16$196 Def000052
+S A$uart0wrnum16$187 Def00004D
+S A$uart0wrnum16$296 Def0000D3
+S A$uart0wrnum16$278 Def0000B9
+S A$uart0wrnum16$269 Def0000AC
+S A$uart0wrnum16$197 Def000054
+S A$uart0wrnum16$297 Def0000D5
+S A$uart0wrnum16$279 Def0000BB
+S A$uart0wrnum16$198 Def000057
+S C$uart0wrnum16.c$25$0$0 Def000000
+S A$uart0wrnum16$298 Def0000D7
+S A$uart0wrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrnum16
+F:G$uart0_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrnum16.uart0_writenum16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrnum16.uart0_writenum16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrnum16.uart0_writenum16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrnum32
+
+;!FILE libmf/uart0wrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M uart0wrnum32
+O -mmcs51 --model-small
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S _uart0_writenum32 Def000000
+S XG$uart0_writenum32$0$0 Def000128
+S A$uart0wrnum32$200 Def00005A
+S A$uart0wrnum32$300 Def0000D4
+S A$uart0wrnum32$210 Def000062
+S A$uart0wrnum32$201 Def00005C
+S A$uart0wrnum32$120 Def000005
+S C$uart0wrnum32.c$276$1$62 Def000000
+S A$uart0wrnum32$310 Def0000DD
+S A$uart0wrnum32$301 Def0000D5
+S A$uart0wrnum32$220 Def00006A
+S A$uart0wrnum32$211 Def000063
+S A$uart0wrnum32$130 Def000010
+S A$uart0wrnum32$121 Def000007
+S C$uart0wrnum32.c$277$1$62 Def000128
+S A$uart0wrnum32$311 Def0000DF
+S A$uart0wrnum32$230 Def00007B
+S A$uart0wrnum32$221 Def00006C
+S A$uart0wrnum32$122 Def000008
+S A$uart0wrnum32$330 Def0000FA
+S A$uart0wrnum32$312 Def0000E1
+S A$uart0wrnum32$240 Def000087
+S A$uart0wrnum32$231 Def00007C
+S A$uart0wrnum32$222 Def00006E
+S A$uart0wrnum32$150 Def000024
+S A$uart0wrnum32$141 Def000014
+S A$uart0wrnum32$123 Def000009
+S A$uart0wrnum32$340 Def00010D
+S A$uart0wrnum32$331 Def0000FD
+S A$uart0wrnum32$313 Def0000E3
+S A$uart0wrnum32$304 Def0000D6
+S A$uart0wrnum32$250 Def000092
+S A$uart0wrnum32$241 Def000088
+S A$uart0wrnum32$232 Def00007E
+S A$uart0wrnum32$223 Def00006F
+S A$uart0wrnum32$160 Def000030
+S A$uart0wrnum32$151 Def000026
+S A$uart0wrnum32$142 Def000017
+S A$uart0wrnum32$124 Def00000A
+S A$uart0wrnum32$350 Def00011F
+S A$uart0wrnum32$341 Def00010F
+S A$uart0wrnum32$332 Def0000FF
+S A$uart0wrnum32$314 Def0000E5
+S A$uart0wrnum32$305 Def0000D8
+S A$uart0wrnum32$260 Def0000A2
+S A$uart0wrnum32$233 Def00007F
+S A$uart0wrnum32$224 Def000072
+S A$uart0wrnum32$206 Def00005D
+S A$uart0wrnum32$161 Def000033
+S A$uart0wrnum32$152 Def000027
+S A$uart0wrnum32$143 Def000018
+S A$uart0wrnum32$134 Def000012
+S A$uart0wrnum32$125 Def00000C
+S A$uart0wrnum32$116 Def000000
+S A$uart0wrnum32$351 Def000121
+S A$uart0wrnum32$342 Def000111
+S A$uart0wrnum32$333 Def000101
+S A$uart0wrnum32$324 Def0000EF
+S A$uart0wrnum32$315 Def0000E8
+S A$uart0wrnum32$270 Def0000B4
+S A$uart0wrnum32$261 Def0000A4
+S A$uart0wrnum32$243 Def00008A
+S A$uart0wrnum32$234 Def000080
+S A$uart0wrnum32$225 Def000073
+S A$uart0wrnum32$216 Def000064
+S A$uart0wrnum32$207 Def00005E
+S A$uart0wrnum32$162 Def000036
+S A$uart0wrnum32$153 Def000028
+S A$uart0wrnum32$144 Def00001B
+S A$uart0wrnum32$117 Def000001
+S A$uart0wrnum32$352 Def000123
+S A$uart0wrnum32$325 Def0000F1
+S A$uart0wrnum32$316 Def0000EA
+S A$uart0wrnum32$307 Def0000DA
+S A$uart0wrnum32$280 Def0000C6
+S A$uart0wrnum32$235 Def000082
+S A$uart0wrnum32$226 Def000075
+S A$uart0wrnum32$208 Def00005F
+S A$uart0wrnum32$190 Def00004E
+S A$uart0wrnum32$172 Def000040
+S A$uart0wrnum32$163 Def000038
+S A$uart0wrnum32$154 Def000029
+S A$uart0wrnum32$145 Def00001C
+S A$uart0wrnum32$127 Def00000E
+S A$uart0wrnum32$335 Def000103
+S A$uart0wrnum32$326 Def0000F3
+S A$uart0wrnum32$317 Def0000EC
+S A$uart0wrnum32$308 Def0000DB
+S A$uart0wrnum32$290 Def0000C9
+S A$uart0wrnum32$263 Def0000A6
+S A$uart0wrnum32$254 Def000094
+S A$uart0wrnum32$245 Def00008D
+S A$uart0wrnum32$227 Def000077
+S A$uart0wrnum32$218 Def000066
+S A$uart0wrnum32$209 Def000060
+S A$uart0wrnum32$191 Def000050
+S A$uart0wrnum32$173 Def000041
+S A$uart0wrnum32$164 Def00003A
+S A$uart0wrnum32$155 Def00002A
+S A$uart0wrnum32$146 Def00001D
+S A$uart0wrnum32$128 Def00000F
+S A$uart0wrnum32$119 Def000003
+S A$uart0wrnum32$354 Def000125
+S A$uart0wrnum32$345 Def000113
+S A$uart0wrnum32$336 Def000106
+S A$uart0wrnum32$327 Def0000F5
+S A$uart0wrnum32$282 Def0000C8
+S A$uart0wrnum32$273 Def0000B6
+S A$uart0wrnum32$264 Def0000A9
+S A$uart0wrnum32$255 Def000096
+S A$uart0wrnum32$228 Def000079
+S A$uart0wrnum32$219 Def000068
+S A$uart0wrnum32$174 Def000043
+S A$uart0wrnum32$165 Def00003B
+S A$uart0wrnum32$156 Def00002B
+S A$uart0wrnum32$147 Def00001F
+S A$uart0wrnum32$346 Def000115
+S A$uart0wrnum32$337 Def000107
+S A$uart0wrnum32$328 Def0000F6
+S A$uart0wrnum32$319 Def0000EE
+S A$uart0wrnum32$292 Def0000CB
+S A$uart0wrnum32$274 Def0000B8
+S A$uart0wrnum32$265 Def0000AA
+S A$uart0wrnum32$256 Def000098
+S A$uart0wrnum32$247 Def000090
+S A$uart0wrnum32$238 Def000085
+S A$uart0wrnum32$193 Def000051
+S A$uart0wrnum32$175 Def000044
+S A$uart0wrnum32$166 Def00003C
+S A$uart0wrnum32$157 Def00002C
+S A$uart0wrnum32$148 Def000021
+S A$uart0wrnum32$356 Def000126
+S A$uart0wrnum32$347 Def000117
+S A$uart0wrnum32$338 Def000109
+S A$uart0wrnum32$329 Def0000F8
+S A$uart0wrnum32$293 Def0000CD
+S A$uart0wrnum32$275 Def0000BA
+S A$uart0wrnum32$266 Def0000AC
+S A$uart0wrnum32$257 Def00009A
+S A$uart0wrnum32$248 Def000091
+S A$uart0wrnum32$239 Def000086
+S A$uart0wrnum32$194 Def000052
+S A$uart0wrnum32$176 Def000046
+S A$uart0wrnum32$158 Def00002E
+S A$uart0wrnum32$149 Def000022
+S A$uart0wrnum32$348 Def000119
+S A$uart0wrnum32$339 Def00010B
+S A$uart0wrnum32$276 Def0000BC
+S A$uart0wrnum32$267 Def0000AE
+S A$uart0wrnum32$258 Def00009D
+S A$uart0wrnum32$195 Def000054
+S A$uart0wrnum32$177 Def000047
+S A$uart0wrnum32$168 Def00003E
+S A$uart0wrnum32$349 Def00011C
+S A$uart0wrnum32$277 Def0000BF
+S A$uart0wrnum32$268 Def0000B0
+S A$uart0wrnum32$259 Def0000A0
+S A$uart0wrnum32$196 Def000056
+S A$uart0wrnum32$187 Def000048
+S A$uart0wrnum32$296 Def0000CE
+S A$uart0wrnum32$278 Def0000C2
+S A$uart0wrnum32$269 Def0000B2
+S A$uart0wrnum32$188 Def00004B
+S A$uart0wrnum32$279 Def0000C4
+S A$uart0wrnum32$198 Def000057
+S A$uart0wrnum32$189 Def00004C
+S C$uart0wrnum32.c$25$0$0 Def000000
+S A$uart0wrnum32$298 Def0000D1
+S A$uart0wrnum32$199 Def000058
+S G$uart0_writenum32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:uart0wrnum32
+F:G$uart0_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrnum32.uart0_writenum32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrnum32.uart0_writenum32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrnum32.uart0_writenum32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhex16
+
+;!FILE libmf/uart0wrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M uart0wrhex16
+O -mmcs51 --model-small
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S _uart0_writehex16 Def000000
+S XG$uart0_writehex16$0$0 Def000111
+S C$uart0wrhex16.c$264$1$62 Def000000
+S C$uart0wrhex16.c$265$1$62 Def000111
+S A$uart0wrhex16$200 Def000058
+S A$uart0wrhex16$201 Def000059
+S A$uart0wrhex16$120 Def000005
+S A$uart0wrhex16$310 Def0000DB
+S A$uart0wrhex16$301 Def0000CB
+S A$uart0wrhex16$220 Def000069
+S A$uart0wrhex16$211 Def000063
+S A$uart0wrhex16$202 Def00005B
+S A$uart0wrhex16$121 Def000006
+S A$uart0wrhex16$320 Def0000E4
+S A$uart0wrhex16$311 Def0000DD
+S A$uart0wrhex16$302 Def0000CC
+S A$uart0wrhex16$230 Def000075
+S A$uart0wrhex16$221 Def00006B
+S A$uart0wrhex16$203 Def00005D
+S A$uart0wrhex16$140 Def000014
+S A$uart0wrhex16$122 Def000007
+S A$uart0wrhex16$330 Def0000F7
+S A$uart0wrhex16$321 Def0000E6
+S A$uart0wrhex16$240 Def000081
+S A$uart0wrhex16$231 Def000077
+S A$uart0wrhex16$150 Def000026
+S A$uart0wrhex16$141 Def000016
+S A$uart0wrhex16$132 Def00000F
+S A$uart0wrhex16$123 Def000009
+S A$uart0wrhex16$340 Def00010A
+S A$uart0wrhex16$331 Def0000F8
+S A$uart0wrhex16$322 Def0000E7
+S A$uart0wrhex16$313 Def0000DF
+S A$uart0wrhex16$304 Def0000CE
+S A$uart0wrhex16$232 Def000078
+S A$uart0wrhex16$223 Def00006D
+S A$uart0wrhex16$205 Def00005F
+S A$uart0wrhex16$142 Def000019
+S A$uart0wrhex16$341 Def00010C
+S A$uart0wrhex16$332 Def0000FA
+S A$uart0wrhex16$323 Def0000E9
+S A$uart0wrhex16$305 Def0000D0
+S A$uart0wrhex16$260 Def00009D
+S A$uart0wrhex16$242 Def000083
+S A$uart0wrhex16$233 Def000079
+S A$uart0wrhex16$224 Def00006F
+S A$uart0wrhex16$152 Def000028
+S A$uart0wrhex16$143 Def00001A
+S A$uart0wrhex16$125 Def00000B
+S A$uart0wrhex16$324 Def0000EB
+S A$uart0wrhex16$306 Def0000D2
+S A$uart0wrhex16$270 Def0000AD
+S A$uart0wrhex16$234 Def00007B
+S A$uart0wrhex16$225 Def000072
+S A$uart0wrhex16$207 Def000060
+S A$uart0wrhex16$162 Def000036
+S A$uart0wrhex16$153 Def00002B
+S A$uart0wrhex16$144 Def00001B
+S A$uart0wrhex16$126 Def00000C
+S A$uart0wrhex16$117 Def000000
+S A$uart0wrhex16$343 Def00010E
+S A$uart0wrhex16$334 Def0000FC
+S A$uart0wrhex16$325 Def0000EE
+S A$uart0wrhex16$307 Def0000D4
+S A$uart0wrhex16$271 Def0000B0
+S A$uart0wrhex16$262 Def00009F
+S A$uart0wrhex16$253 Def00008D
+S A$uart0wrhex16$244 Def000086
+S A$uart0wrhex16$208 Def000062
+S A$uart0wrhex16$163 Def000037
+S A$uart0wrhex16$154 Def00002E
+S A$uart0wrhex16$145 Def00001D
+S A$uart0wrhex16$118 Def000002
+S A$uart0wrhex16$335 Def0000FE
+S A$uart0wrhex16$326 Def0000F0
+S A$uart0wrhex16$308 Def0000D6
+S A$uart0wrhex16$290 Def0000BF
+S A$uart0wrhex16$272 Def0000B3
+S A$uart0wrhex16$263 Def0000A2
+S A$uart0wrhex16$254 Def00008F
+S A$uart0wrhex16$227 Def000074
+S A$uart0wrhex16$218 Def000065
+S A$uart0wrhex16$182 Def000047
+S A$uart0wrhex16$173 Def00003E
+S A$uart0wrhex16$164 Def000039
+S A$uart0wrhex16$155 Def000030
+S A$uart0wrhex16$146 Def00001F
+S A$uart0wrhex16$128 Def00000D
+S A$uart0wrhex16$119 Def000004
+S A$uart0wrhex16$345 Def00010F
+S A$uart0wrhex16$336 Def000100
+S A$uart0wrhex16$327 Def0000F2
+S A$uart0wrhex16$318 Def0000E0
+S A$uart0wrhex16$309 Def0000D9
+S A$uart0wrhex16$273 Def0000B5
+S A$uart0wrhex16$264 Def0000A3
+S A$uart0wrhex16$255 Def000091
+S A$uart0wrhex16$246 Def000089
+S A$uart0wrhex16$237 Def00007E
+S A$uart0wrhex16$219 Def000067
+S A$uart0wrhex16$192 Def00004E
+S A$uart0wrhex16$183 Def000048
+S A$uart0wrhex16$174 Def000041
+S A$uart0wrhex16$165 Def00003A
+S A$uart0wrhex16$156 Def000032
+S A$uart0wrhex16$147 Def000020
+S A$uart0wrhex16$337 Def000102
+S A$uart0wrhex16$319 Def0000E2
+S A$uart0wrhex16$292 Def0000C2
+S A$uart0wrhex16$274 Def0000B7
+S A$uart0wrhex16$265 Def0000A5
+S A$uart0wrhex16$256 Def000093
+S A$uart0wrhex16$247 Def00008A
+S A$uart0wrhex16$238 Def00007F
+S A$uart0wrhex16$193 Def00004F
+S A$uart0wrhex16$184 Def000049
+S A$uart0wrhex16$175 Def000042
+S A$uart0wrhex16$166 Def00003C
+S A$uart0wrhex16$148 Def000022
+S A$uart0wrhex16$139 Def000011
+S A$uart0wrhex16$338 Def000105
+S A$uart0wrhex16$329 Def0000F4
+S A$uart0wrhex16$284 Def0000BA
+S A$uart0wrhex16$257 Def000096
+S A$uart0wrhex16$239 Def000080
+S A$uart0wrhex16$194 Def000050
+S A$uart0wrhex16$185 Def00004A
+S A$uart0wrhex16$176 Def000044
+S A$uart0wrhex16$167 Def00003D
+S A$uart0wrhex16$158 Def000034
+S A$uart0wrhex16$149 Def000024
+S A$uart0wrhex16$339 Def000108
+S A$uart0wrhex16$294 Def0000C5
+S A$uart0wrhex16$276 Def0000B9
+S A$uart0wrhex16$267 Def0000A7
+S A$uart0wrhex16$258 Def000099
+S A$uart0wrhex16$249 Def00008B
+S A$uart0wrhex16$195 Def000051
+S A$uart0wrhex16$186 Def00004C
+S A$uart0wrhex16$177 Def000046
+S A$uart0wrhex16$295 Def0000C6
+S A$uart0wrhex16$286 Def0000BC
+S A$uart0wrhex16$268 Def0000A9
+S A$uart0wrhex16$259 Def00009B
+S A$uart0wrhex16$196 Def000052
+S A$uart0wrhex16$187 Def00004D
+S A$uart0wrhex16$287 Def0000BE
+S A$uart0wrhex16$269 Def0000AB
+S A$uart0wrhex16$197 Def000054
+S A$uart0wrhex16$198 Def000056
+S C$uart0wrhex16.c$25$0$0 Def000000
+S A$uart0wrhex16$298 Def0000C7
+S A$uart0wrhex16$299 Def0000C9
+S G$uart0_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrhex16
+F:G$uart0_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrhex16.uart0_writehex16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrhex16.uart0_writehex16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrhex16.uart0_writehex16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhex32
+
+;!FILE libmf/uart0wrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M uart0wrhex32
+O -mmcs51 --model-small
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S XG$uart0_writehex32$0$0 Def000127
+S C$uart0wrhex32.c$282$1$62 Def000000
+S C$uart0wrhex32.c$283$1$62 Def000127
+S A$uart0wrhex32$210 Def000062
+S A$uart0wrhex32$120 Def000005
+S A$uart0wrhex32$310 Def0000D5
+S A$uart0wrhex32$220 Def00006F
+S A$uart0wrhex32$211 Def000063
+S A$uart0wrhex32$202 Def000058
+S A$uart0wrhex32$130 Def000010
+S A$uart0wrhex32$121 Def000007
+S A$uart0wrhex32$221 Def000070
+S A$uart0wrhex32$212 Def000065
+S A$uart0wrhex32$203 Def000059
+S A$uart0wrhex32$122 Def000008
+S A$uart0wrhex32$330 Def0000F1
+S A$uart0wrhex32$321 Def0000E1
+S A$uart0wrhex32$312 Def0000D8
+S A$uart0wrhex32$240 Def00007F
+S A$uart0wrhex32$231 Def000079
+S A$uart0wrhex32$222 Def000072
+S A$uart0wrhex32$213 Def000067
+S A$uart0wrhex32$204 Def00005A
+S A$uart0wrhex32$150 Def000024
+S A$uart0wrhex32$141 Def000014
+S A$uart0wrhex32$123 Def000009
+S A$uart0wrhex32$340 Def0000FA
+S A$uart0wrhex32$331 Def0000F3
+S A$uart0wrhex32$322 Def0000E2
+S A$uart0wrhex32$304 Def0000D0
+S A$uart0wrhex32$250 Def00008B
+S A$uart0wrhex32$241 Def000081
+S A$uart0wrhex32$223 Def000073
+S A$uart0wrhex32$205 Def00005B
+S A$uart0wrhex32$160 Def000030
+S A$uart0wrhex32$151 Def000026
+S A$uart0wrhex32$142 Def000017
+S A$uart0wrhex32$124 Def00000A
+S A$uart0wrhex32$350 Def00010D
+S A$uart0wrhex32$341 Def0000FC
+S A$uart0wrhex32$314 Def0000DB
+S A$uart0wrhex32$260 Def000097
+S A$uart0wrhex32$251 Def00008D
+S A$uart0wrhex32$215 Def000069
+S A$uart0wrhex32$206 Def00005C
+S A$uart0wrhex32$161 Def000033
+S A$uart0wrhex32$152 Def000027
+S A$uart0wrhex32$143 Def000018
+S A$uart0wrhex32$134 Def000012
+S A$uart0wrhex32$125 Def00000C
+S A$uart0wrhex32$116 Def000000
+S A$uart0wrhex32$360 Def000120
+S A$uart0wrhex32$351 Def00010E
+S A$uart0wrhex32$342 Def0000FD
+S A$uart0wrhex32$333 Def0000F5
+S A$uart0wrhex32$324 Def0000E4
+S A$uart0wrhex32$315 Def0000DC
+S A$uart0wrhex32$306 Def0000D2
+S A$uart0wrhex32$252 Def00008E
+S A$uart0wrhex32$243 Def000083
+S A$uart0wrhex32$225 Def000075
+S A$uart0wrhex32$216 Def00006A
+S A$uart0wrhex32$207 Def00005E
+S A$uart0wrhex32$162 Def000036
+S A$uart0wrhex32$153 Def000028
+S A$uart0wrhex32$144 Def00001B
+S A$uart0wrhex32$117 Def000001
+S A$uart0wrhex32$361 Def000122
+S A$uart0wrhex32$352 Def000110
+S A$uart0wrhex32$343 Def0000FF
+S A$uart0wrhex32$325 Def0000E6
+S A$uart0wrhex32$307 Def0000D4
+S A$uart0wrhex32$280 Def0000B3
+S A$uart0wrhex32$262 Def000099
+S A$uart0wrhex32$253 Def00008F
+S A$uart0wrhex32$244 Def000085
+S A$uart0wrhex32$217 Def00006C
+S A$uart0wrhex32$208 Def000060
+S A$uart0wrhex32$172 Def000040
+S A$uart0wrhex32$163 Def000038
+S A$uart0wrhex32$154 Def000029
+S A$uart0wrhex32$145 Def00001C
+S A$uart0wrhex32$127 Def00000E
+S A$uart0wrhex32$344 Def000101
+S A$uart0wrhex32$326 Def0000E8
+S A$uart0wrhex32$290 Def0000C3
+S A$uart0wrhex32$254 Def000091
+S A$uart0wrhex32$245 Def000088
+S A$uart0wrhex32$227 Def000076
+S A$uart0wrhex32$218 Def00006D
+S A$uart0wrhex32$173 Def000041
+S A$uart0wrhex32$164 Def00003A
+S A$uart0wrhex32$155 Def00002A
+S A$uart0wrhex32$146 Def00001D
+S A$uart0wrhex32$128 Def00000F
+S A$uart0wrhex32$119 Def000003
+S A$uart0wrhex32$363 Def000124
+S A$uart0wrhex32$354 Def000112
+S A$uart0wrhex32$345 Def000104
+S A$uart0wrhex32$327 Def0000EA
+S A$uart0wrhex32$318 Def0000DD
+S A$uart0wrhex32$291 Def0000C6
+S A$uart0wrhex32$282 Def0000B5
+S A$uart0wrhex32$273 Def0000A3
+S A$uart0wrhex32$264 Def00009C
+S A$uart0wrhex32$228 Def000078
+S A$uart0wrhex32$192 Def000051
+S A$uart0wrhex32$183 Def000048
+S A$uart0wrhex32$174 Def000043
+S A$uart0wrhex32$165 Def00003B
+S A$uart0wrhex32$156 Def00002B
+S A$uart0wrhex32$147 Def00001F
+S A$uart0wrhex32$355 Def000114
+S A$uart0wrhex32$346 Def000106
+S A$uart0wrhex32$328 Def0000EC
+S A$uart0wrhex32$319 Def0000DF
+S A$uart0wrhex32$292 Def0000C9
+S A$uart0wrhex32$283 Def0000B8
+S A$uart0wrhex32$274 Def0000A5
+S A$uart0wrhex32$247 Def00008A
+S A$uart0wrhex32$238 Def00007B
+S A$uart0wrhex32$193 Def000052
+S A$uart0wrhex32$184 Def00004B
+S A$uart0wrhex32$175 Def000044
+S A$uart0wrhex32$166 Def00003C
+S A$uart0wrhex32$157 Def00002C
+S A$uart0wrhex32$148 Def000021
+S A$uart0wrhex32$365 Def000125
+S A$uart0wrhex32$356 Def000116
+S A$uart0wrhex32$347 Def000108
+S A$uart0wrhex32$338 Def0000F6
+S A$uart0wrhex32$329 Def0000EF
+S A$uart0wrhex32$293 Def0000CB
+S A$uart0wrhex32$284 Def0000B9
+S A$uart0wrhex32$275 Def0000A7
+S A$uart0wrhex32$266 Def00009F
+S A$uart0wrhex32$257 Def000094
+S A$uart0wrhex32$239 Def00007D
+S A$uart0wrhex32$194 Def000053
+S A$uart0wrhex32$185 Def00004C
+S A$uart0wrhex32$176 Def000046
+S A$uart0wrhex32$158 Def00002E
+S A$uart0wrhex32$149 Def000022
+S A$uart0wrhex32$357 Def000118
+S A$uart0wrhex32$339 Def0000F8
+S A$uart0wrhex32$294 Def0000CD
+S A$uart0wrhex32$285 Def0000BB
+S A$uart0wrhex32$276 Def0000A9
+S A$uart0wrhex32$267 Def0000A0
+S A$uart0wrhex32$258 Def000095
+S A$uart0wrhex32$195 Def000054
+S A$uart0wrhex32$186 Def00004E
+S A$uart0wrhex32$177 Def000047
+S A$uart0wrhex32$168 Def00003E
+S A$uart0wrhex32$358 Def00011B
+S A$uart0wrhex32$349 Def00010A
+S A$uart0wrhex32$277 Def0000AC
+S A$uart0wrhex32$259 Def000096
+S A$uart0wrhex32$196 Def000056
+S A$uart0wrhex32$187 Def000050
+S A$uart0wrhex32$359 Def00011E
+S A$uart0wrhex32$296 Def0000CF
+S A$uart0wrhex32$287 Def0000BD
+S A$uart0wrhex32$278 Def0000AF
+S A$uart0wrhex32$269 Def0000A1
+S A$uart0wrhex32$197 Def000057
+S A$uart0wrhex32$288 Def0000BF
+S A$uart0wrhex32$279 Def0000B1
+S C$uart0wrhex32.c$25$0$0 Def000000
+S A$uart0wrhex32$289 Def0000C1
+S G$uart0_writehex32$0$0 Def000000
+S _uart0_writehex32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrhex32
+F:G$uart0_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrhex32.uart0_writehex32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrhex32.uart0_writehex32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrhex32.uart0_writehex32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrnum16
+
+;!FILE libmf/uart1wrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M uart1wrnum16
+O -mmcs51 --model-small
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S G$uart1_writenum16$0$0 Def000000
+S _uart1_writenum16 Def000000
+S XG$uart1_writenum16$0$0 Def0000F6
+S C$uart1wrnum16.c$240$1$62 Def000000
+S C$uart1wrnum16.c$241$1$62 Def0000F6
+S A$uart1wrnum16$200 Def000059
+S A$uart1wrnum16$300 Def0000D9
+S A$uart1wrnum16$210 Def000065
+S A$uart1wrnum16$201 Def00005A
+S A$uart1wrnum16$120 Def000005
+S A$uart1wrnum16$310 Def0000ED
+S A$uart1wrnum16$301 Def0000DC
+S A$uart1wrnum16$220 Def000070
+S A$uart1wrnum16$211 Def000066
+S A$uart1wrnum16$202 Def00005C
+S A$uart1wrnum16$121 Def000006
+S A$uart1wrnum16$311 Def0000EF
+S A$uart1wrnum16$302 Def0000DD
+S A$uart1wrnum16$230 Def000080
+S A$uart1wrnum16$203 Def00005D
+S A$uart1wrnum16$140 Def000014
+S A$uart1wrnum16$122 Def000007
+S A$uart1wrnum16$312 Def0000F1
+S A$uart1wrnum16$303 Def0000DF
+S A$uart1wrnum16$240 Def000090
+S A$uart1wrnum16$231 Def000082
+S A$uart1wrnum16$213 Def000068
+S A$uart1wrnum16$204 Def00005E
+S A$uart1wrnum16$150 Def000026
+S A$uart1wrnum16$141 Def000016
+S A$uart1wrnum16$132 Def00000F
+S A$uart1wrnum16$123 Def000009
+S A$uart1wrnum16$241 Def000092
+S A$uart1wrnum16$205 Def000060
+S A$uart1wrnum16$142 Def000019
+S A$uart1wrnum16$314 Def0000F3
+S A$uart1wrnum16$305 Def0000E1
+S A$uart1wrnum16$242 Def000095
+S A$uart1wrnum16$233 Def000084
+S A$uart1wrnum16$224 Def000072
+S A$uart1wrnum16$215 Def00006B
+S A$uart1wrnum16$152 Def000028
+S A$uart1wrnum16$143 Def00001A
+S A$uart1wrnum16$125 Def00000B
+S A$uart1wrnum16$306 Def0000E3
+S A$uart1wrnum16$270 Def0000AE
+S A$uart1wrnum16$261 Def0000A4
+S A$uart1wrnum16$243 Def000098
+S A$uart1wrnum16$234 Def000087
+S A$uart1wrnum16$225 Def000074
+S A$uart1wrnum16$162 Def000036
+S A$uart1wrnum16$153 Def00002B
+S A$uart1wrnum16$144 Def00001B
+S A$uart1wrnum16$126 Def00000C
+S A$uart1wrnum16$117 Def000000
+S A$uart1wrnum16$316 Def0000F4
+S A$uart1wrnum16$307 Def0000E5
+S A$uart1wrnum16$280 Def0000BE
+S A$uart1wrnum16$244 Def00009A
+S A$uart1wrnum16$235 Def000088
+S A$uart1wrnum16$226 Def000076
+S A$uart1wrnum16$217 Def00006E
+S A$uart1wrnum16$208 Def000063
+S A$uart1wrnum16$163 Def000037
+S A$uart1wrnum16$154 Def00002E
+S A$uart1wrnum16$145 Def00001D
+S A$uart1wrnum16$118 Def000002
+S A$uart1wrnum16$308 Def0000E7
+S A$uart1wrnum16$290 Def0000C7
+S A$uart1wrnum16$281 Def0000C0
+S A$uart1wrnum16$272 Def0000B0
+S A$uart1wrnum16$263 Def0000A7
+S A$uart1wrnum16$245 Def00009C
+S A$uart1wrnum16$236 Def00008A
+S A$uart1wrnum16$227 Def000078
+S A$uart1wrnum16$218 Def00006F
+S A$uart1wrnum16$209 Def000064
+S A$uart1wrnum16$182 Def000047
+S A$uart1wrnum16$173 Def00003E
+S A$uart1wrnum16$164 Def000039
+S A$uart1wrnum16$155 Def000030
+S A$uart1wrnum16$146 Def00001F
+S A$uart1wrnum16$128 Def00000D
+S A$uart1wrnum16$119 Def000004
+S A$uart1wrnum16$309 Def0000EA
+S A$uart1wrnum16$291 Def0000C9
+S A$uart1wrnum16$282 Def0000C2
+S A$uart1wrnum16$273 Def0000B1
+S A$uart1wrnum16$255 Def00009F
+S A$uart1wrnum16$228 Def00007B
+S A$uart1wrnum16$192 Def00004E
+S A$uart1wrnum16$183 Def000048
+S A$uart1wrnum16$174 Def000041
+S A$uart1wrnum16$165 Def00003A
+S A$uart1wrnum16$156 Def000032
+S A$uart1wrnum16$147 Def000020
+S A$uart1wrnum16$292 Def0000CB
+S A$uart1wrnum16$265 Def0000AA
+S A$uart1wrnum16$247 Def00009E
+S A$uart1wrnum16$238 Def00008C
+S A$uart1wrnum16$229 Def00007E
+S A$uart1wrnum16$193 Def00004F
+S A$uart1wrnum16$184 Def000049
+S A$uart1wrnum16$175 Def000042
+S A$uart1wrnum16$166 Def00003C
+S A$uart1wrnum16$148 Def000022
+S A$uart1wrnum16$139 Def000011
+S A$uart1wrnum16$293 Def0000CC
+S A$uart1wrnum16$284 Def0000C4
+S A$uart1wrnum16$275 Def0000B3
+S A$uart1wrnum16$266 Def0000AB
+S A$uart1wrnum16$257 Def0000A1
+S A$uart1wrnum16$239 Def00008E
+S A$uart1wrnum16$185 Def00004A
+S A$uart1wrnum16$176 Def000044
+S A$uart1wrnum16$167 Def00003D
+S A$uart1wrnum16$158 Def000034
+S A$uart1wrnum16$149 Def000024
+S A$uart1wrnum16$294 Def0000CE
+S A$uart1wrnum16$276 Def0000B5
+S A$uart1wrnum16$258 Def0000A3
+S A$uart1wrnum16$195 Def000050
+S A$uart1wrnum16$186 Def00004C
+S A$uart1wrnum16$177 Def000046
+S A$uart1wrnum16$295 Def0000D0
+S A$uart1wrnum16$277 Def0000B7
+S A$uart1wrnum16$196 Def000052
+S A$uart1wrnum16$187 Def00004D
+S A$uart1wrnum16$296 Def0000D3
+S A$uart1wrnum16$278 Def0000B9
+S A$uart1wrnum16$269 Def0000AC
+S A$uart1wrnum16$197 Def000054
+S A$uart1wrnum16$297 Def0000D5
+S A$uart1wrnum16$279 Def0000BB
+S A$uart1wrnum16$198 Def000057
+S C$uart1wrnum16.c$25$0$0 Def000000
+S A$uart1wrnum16$298 Def0000D7
+S A$uart1wrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrnum16
+F:G$uart1_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrnum16.uart1_writenum16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrnum16.uart1_writenum16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrnum16.uart1_writenum16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrnum32
+
+;!FILE libmf/uart1wrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M uart1wrnum32
+O -mmcs51 --model-small
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S _uart1_writenum32 Def000000
+S XG$uart1_writenum32$0$0 Def000128
+S A$uart1wrnum32$200 Def00005A
+S A$uart1wrnum32$300 Def0000D4
+S A$uart1wrnum32$210 Def000062
+S A$uart1wrnum32$201 Def00005C
+S A$uart1wrnum32$120 Def000005
+S C$uart1wrnum32.c$276$1$62 Def000000
+S A$uart1wrnum32$310 Def0000DD
+S A$uart1wrnum32$301 Def0000D5
+S A$uart1wrnum32$220 Def00006A
+S A$uart1wrnum32$211 Def000063
+S A$uart1wrnum32$130 Def000010
+S A$uart1wrnum32$121 Def000007
+S C$uart1wrnum32.c$277$1$62 Def000128
+S A$uart1wrnum32$311 Def0000DF
+S A$uart1wrnum32$230 Def00007B
+S A$uart1wrnum32$221 Def00006C
+S A$uart1wrnum32$122 Def000008
+S A$uart1wrnum32$330 Def0000FA
+S A$uart1wrnum32$312 Def0000E1
+S A$uart1wrnum32$240 Def000087
+S A$uart1wrnum32$231 Def00007C
+S A$uart1wrnum32$222 Def00006E
+S A$uart1wrnum32$150 Def000024
+S A$uart1wrnum32$141 Def000014
+S A$uart1wrnum32$123 Def000009
+S A$uart1wrnum32$340 Def00010D
+S A$uart1wrnum32$331 Def0000FD
+S A$uart1wrnum32$313 Def0000E3
+S A$uart1wrnum32$304 Def0000D6
+S A$uart1wrnum32$250 Def000092
+S A$uart1wrnum32$241 Def000088
+S A$uart1wrnum32$232 Def00007E
+S A$uart1wrnum32$223 Def00006F
+S A$uart1wrnum32$160 Def000030
+S A$uart1wrnum32$151 Def000026
+S A$uart1wrnum32$142 Def000017
+S A$uart1wrnum32$124 Def00000A
+S A$uart1wrnum32$350 Def00011F
+S A$uart1wrnum32$341 Def00010F
+S A$uart1wrnum32$332 Def0000FF
+S A$uart1wrnum32$314 Def0000E5
+S A$uart1wrnum32$305 Def0000D8
+S A$uart1wrnum32$260 Def0000A2
+S A$uart1wrnum32$233 Def00007F
+S A$uart1wrnum32$224 Def000072
+S A$uart1wrnum32$206 Def00005D
+S A$uart1wrnum32$161 Def000033
+S A$uart1wrnum32$152 Def000027
+S A$uart1wrnum32$143 Def000018
+S A$uart1wrnum32$134 Def000012
+S A$uart1wrnum32$125 Def00000C
+S A$uart1wrnum32$116 Def000000
+S A$uart1wrnum32$351 Def000121
+S A$uart1wrnum32$342 Def000111
+S A$uart1wrnum32$333 Def000101
+S A$uart1wrnum32$324 Def0000EF
+S A$uart1wrnum32$315 Def0000E8
+S A$uart1wrnum32$270 Def0000B4
+S A$uart1wrnum32$261 Def0000A4
+S A$uart1wrnum32$243 Def00008A
+S A$uart1wrnum32$234 Def000080
+S A$uart1wrnum32$225 Def000073
+S A$uart1wrnum32$216 Def000064
+S A$uart1wrnum32$207 Def00005E
+S A$uart1wrnum32$162 Def000036
+S A$uart1wrnum32$153 Def000028
+S A$uart1wrnum32$144 Def00001B
+S A$uart1wrnum32$117 Def000001
+S A$uart1wrnum32$352 Def000123
+S A$uart1wrnum32$325 Def0000F1
+S A$uart1wrnum32$316 Def0000EA
+S A$uart1wrnum32$307 Def0000DA
+S A$uart1wrnum32$280 Def0000C6
+S A$uart1wrnum32$235 Def000082
+S A$uart1wrnum32$226 Def000075
+S A$uart1wrnum32$208 Def00005F
+S A$uart1wrnum32$190 Def00004E
+S A$uart1wrnum32$172 Def000040
+S A$uart1wrnum32$163 Def000038
+S A$uart1wrnum32$154 Def000029
+S A$uart1wrnum32$145 Def00001C
+S A$uart1wrnum32$127 Def00000E
+S A$uart1wrnum32$335 Def000103
+S A$uart1wrnum32$326 Def0000F3
+S A$uart1wrnum32$317 Def0000EC
+S A$uart1wrnum32$308 Def0000DB
+S A$uart1wrnum32$290 Def0000C9
+S A$uart1wrnum32$263 Def0000A6
+S A$uart1wrnum32$254 Def000094
+S A$uart1wrnum32$245 Def00008D
+S A$uart1wrnum32$227 Def000077
+S A$uart1wrnum32$218 Def000066
+S A$uart1wrnum32$209 Def000060
+S A$uart1wrnum32$191 Def000050
+S A$uart1wrnum32$173 Def000041
+S A$uart1wrnum32$164 Def00003A
+S A$uart1wrnum32$155 Def00002A
+S A$uart1wrnum32$146 Def00001D
+S A$uart1wrnum32$128 Def00000F
+S A$uart1wrnum32$119 Def000003
+S A$uart1wrnum32$354 Def000125
+S A$uart1wrnum32$345 Def000113
+S A$uart1wrnum32$336 Def000106
+S A$uart1wrnum32$327 Def0000F5
+S A$uart1wrnum32$282 Def0000C8
+S A$uart1wrnum32$273 Def0000B6
+S A$uart1wrnum32$264 Def0000A9
+S A$uart1wrnum32$255 Def000096
+S A$uart1wrnum32$228 Def000079
+S A$uart1wrnum32$219 Def000068
+S A$uart1wrnum32$174 Def000043
+S A$uart1wrnum32$165 Def00003B
+S A$uart1wrnum32$156 Def00002B
+S A$uart1wrnum32$147 Def00001F
+S A$uart1wrnum32$346 Def000115
+S A$uart1wrnum32$337 Def000107
+S A$uart1wrnum32$328 Def0000F6
+S A$uart1wrnum32$319 Def0000EE
+S A$uart1wrnum32$292 Def0000CB
+S A$uart1wrnum32$274 Def0000B8
+S A$uart1wrnum32$265 Def0000AA
+S A$uart1wrnum32$256 Def000098
+S A$uart1wrnum32$247 Def000090
+S A$uart1wrnum32$238 Def000085
+S A$uart1wrnum32$193 Def000051
+S A$uart1wrnum32$175 Def000044
+S A$uart1wrnum32$166 Def00003C
+S A$uart1wrnum32$157 Def00002C
+S A$uart1wrnum32$148 Def000021
+S A$uart1wrnum32$356 Def000126
+S A$uart1wrnum32$347 Def000117
+S A$uart1wrnum32$338 Def000109
+S A$uart1wrnum32$329 Def0000F8
+S A$uart1wrnum32$293 Def0000CD
+S A$uart1wrnum32$275 Def0000BA
+S A$uart1wrnum32$266 Def0000AC
+S A$uart1wrnum32$257 Def00009A
+S A$uart1wrnum32$248 Def000091
+S A$uart1wrnum32$239 Def000086
+S A$uart1wrnum32$194 Def000052
+S A$uart1wrnum32$176 Def000046
+S A$uart1wrnum32$158 Def00002E
+S A$uart1wrnum32$149 Def000022
+S A$uart1wrnum32$348 Def000119
+S A$uart1wrnum32$339 Def00010B
+S A$uart1wrnum32$276 Def0000BC
+S A$uart1wrnum32$267 Def0000AE
+S A$uart1wrnum32$258 Def00009D
+S A$uart1wrnum32$195 Def000054
+S A$uart1wrnum32$177 Def000047
+S A$uart1wrnum32$168 Def00003E
+S A$uart1wrnum32$349 Def00011C
+S A$uart1wrnum32$277 Def0000BF
+S A$uart1wrnum32$268 Def0000B0
+S A$uart1wrnum32$259 Def0000A0
+S A$uart1wrnum32$196 Def000056
+S A$uart1wrnum32$187 Def000048
+S A$uart1wrnum32$296 Def0000CE
+S A$uart1wrnum32$278 Def0000C2
+S A$uart1wrnum32$269 Def0000B2
+S A$uart1wrnum32$188 Def00004B
+S A$uart1wrnum32$279 Def0000C4
+S A$uart1wrnum32$198 Def000057
+S A$uart1wrnum32$189 Def00004C
+S C$uart1wrnum32.c$25$0$0 Def000000
+S A$uart1wrnum32$298 Def0000D1
+S A$uart1wrnum32$199 Def000058
+S G$uart1_writenum32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:uart1wrnum32
+F:G$uart1_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrnum32.uart1_writenum32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrnum32.uart1_writenum32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrnum32.uart1_writenum32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhex16
+
+;!FILE libmf/uart1wrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M uart1wrhex16
+O -mmcs51 --model-small
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S _uart1_writehex16 Def000000
+S XG$uart1_writehex16$0$0 Def000111
+S C$uart1wrhex16.c$264$1$62 Def000000
+S C$uart1wrhex16.c$265$1$62 Def000111
+S A$uart1wrhex16$200 Def000058
+S A$uart1wrhex16$201 Def000059
+S A$uart1wrhex16$120 Def000005
+S A$uart1wrhex16$310 Def0000DB
+S A$uart1wrhex16$301 Def0000CB
+S A$uart1wrhex16$220 Def000069
+S A$uart1wrhex16$211 Def000063
+S A$uart1wrhex16$202 Def00005B
+S A$uart1wrhex16$121 Def000006
+S A$uart1wrhex16$320 Def0000E4
+S A$uart1wrhex16$311 Def0000DD
+S A$uart1wrhex16$302 Def0000CC
+S A$uart1wrhex16$230 Def000075
+S A$uart1wrhex16$221 Def00006B
+S A$uart1wrhex16$203 Def00005D
+S A$uart1wrhex16$140 Def000014
+S A$uart1wrhex16$122 Def000007
+S A$uart1wrhex16$330 Def0000F7
+S A$uart1wrhex16$321 Def0000E6
+S A$uart1wrhex16$240 Def000081
+S A$uart1wrhex16$231 Def000077
+S A$uart1wrhex16$150 Def000026
+S A$uart1wrhex16$141 Def000016
+S A$uart1wrhex16$132 Def00000F
+S A$uart1wrhex16$123 Def000009
+S A$uart1wrhex16$340 Def00010A
+S A$uart1wrhex16$331 Def0000F8
+S A$uart1wrhex16$322 Def0000E7
+S A$uart1wrhex16$313 Def0000DF
+S A$uart1wrhex16$304 Def0000CE
+S A$uart1wrhex16$232 Def000078
+S A$uart1wrhex16$223 Def00006D
+S A$uart1wrhex16$205 Def00005F
+S A$uart1wrhex16$142 Def000019
+S A$uart1wrhex16$341 Def00010C
+S A$uart1wrhex16$332 Def0000FA
+S A$uart1wrhex16$323 Def0000E9
+S A$uart1wrhex16$305 Def0000D0
+S A$uart1wrhex16$260 Def00009D
+S A$uart1wrhex16$242 Def000083
+S A$uart1wrhex16$233 Def000079
+S A$uart1wrhex16$224 Def00006F
+S A$uart1wrhex16$152 Def000028
+S A$uart1wrhex16$143 Def00001A
+S A$uart1wrhex16$125 Def00000B
+S A$uart1wrhex16$324 Def0000EB
+S A$uart1wrhex16$306 Def0000D2
+S A$uart1wrhex16$270 Def0000AD
+S A$uart1wrhex16$234 Def00007B
+S A$uart1wrhex16$225 Def000072
+S A$uart1wrhex16$207 Def000060
+S A$uart1wrhex16$162 Def000036
+S A$uart1wrhex16$153 Def00002B
+S A$uart1wrhex16$144 Def00001B
+S A$uart1wrhex16$126 Def00000C
+S A$uart1wrhex16$117 Def000000
+S A$uart1wrhex16$343 Def00010E
+S A$uart1wrhex16$334 Def0000FC
+S A$uart1wrhex16$325 Def0000EE
+S A$uart1wrhex16$307 Def0000D4
+S A$uart1wrhex16$271 Def0000B0
+S A$uart1wrhex16$262 Def00009F
+S A$uart1wrhex16$253 Def00008D
+S A$uart1wrhex16$244 Def000086
+S A$uart1wrhex16$208 Def000062
+S A$uart1wrhex16$163 Def000037
+S A$uart1wrhex16$154 Def00002E
+S A$uart1wrhex16$145 Def00001D
+S A$uart1wrhex16$118 Def000002
+S A$uart1wrhex16$335 Def0000FE
+S A$uart1wrhex16$326 Def0000F0
+S A$uart1wrhex16$308 Def0000D6
+S A$uart1wrhex16$290 Def0000BF
+S A$uart1wrhex16$272 Def0000B3
+S A$uart1wrhex16$263 Def0000A2
+S A$uart1wrhex16$254 Def00008F
+S A$uart1wrhex16$227 Def000074
+S A$uart1wrhex16$218 Def000065
+S A$uart1wrhex16$182 Def000047
+S A$uart1wrhex16$173 Def00003E
+S A$uart1wrhex16$164 Def000039
+S A$uart1wrhex16$155 Def000030
+S A$uart1wrhex16$146 Def00001F
+S A$uart1wrhex16$128 Def00000D
+S A$uart1wrhex16$119 Def000004
+S A$uart1wrhex16$345 Def00010F
+S A$uart1wrhex16$336 Def000100
+S A$uart1wrhex16$327 Def0000F2
+S A$uart1wrhex16$318 Def0000E0
+S A$uart1wrhex16$309 Def0000D9
+S A$uart1wrhex16$273 Def0000B5
+S A$uart1wrhex16$264 Def0000A3
+S A$uart1wrhex16$255 Def000091
+S A$uart1wrhex16$246 Def000089
+S A$uart1wrhex16$237 Def00007E
+S A$uart1wrhex16$219 Def000067
+S A$uart1wrhex16$192 Def00004E
+S A$uart1wrhex16$183 Def000048
+S A$uart1wrhex16$174 Def000041
+S A$uart1wrhex16$165 Def00003A
+S A$uart1wrhex16$156 Def000032
+S A$uart1wrhex16$147 Def000020
+S A$uart1wrhex16$337 Def000102
+S A$uart1wrhex16$319 Def0000E2
+S A$uart1wrhex16$292 Def0000C2
+S A$uart1wrhex16$274 Def0000B7
+S A$uart1wrhex16$265 Def0000A5
+S A$uart1wrhex16$256 Def000093
+S A$uart1wrhex16$247 Def00008A
+S A$uart1wrhex16$238 Def00007F
+S A$uart1wrhex16$193 Def00004F
+S A$uart1wrhex16$184 Def000049
+S A$uart1wrhex16$175 Def000042
+S A$uart1wrhex16$166 Def00003C
+S A$uart1wrhex16$148 Def000022
+S A$uart1wrhex16$139 Def000011
+S A$uart1wrhex16$338 Def000105
+S A$uart1wrhex16$329 Def0000F4
+S A$uart1wrhex16$284 Def0000BA
+S A$uart1wrhex16$257 Def000096
+S A$uart1wrhex16$239 Def000080
+S A$uart1wrhex16$194 Def000050
+S A$uart1wrhex16$185 Def00004A
+S A$uart1wrhex16$176 Def000044
+S A$uart1wrhex16$167 Def00003D
+S A$uart1wrhex16$158 Def000034
+S A$uart1wrhex16$149 Def000024
+S A$uart1wrhex16$339 Def000108
+S A$uart1wrhex16$294 Def0000C5
+S A$uart1wrhex16$276 Def0000B9
+S A$uart1wrhex16$267 Def0000A7
+S A$uart1wrhex16$258 Def000099
+S A$uart1wrhex16$249 Def00008B
+S A$uart1wrhex16$195 Def000051
+S A$uart1wrhex16$186 Def00004C
+S A$uart1wrhex16$177 Def000046
+S A$uart1wrhex16$295 Def0000C6
+S A$uart1wrhex16$286 Def0000BC
+S A$uart1wrhex16$268 Def0000A9
+S A$uart1wrhex16$259 Def00009B
+S A$uart1wrhex16$196 Def000052
+S A$uart1wrhex16$187 Def00004D
+S A$uart1wrhex16$287 Def0000BE
+S A$uart1wrhex16$269 Def0000AB
+S A$uart1wrhex16$197 Def000054
+S A$uart1wrhex16$198 Def000056
+S C$uart1wrhex16.c$25$0$0 Def000000
+S A$uart1wrhex16$298 Def0000C7
+S A$uart1wrhex16$299 Def0000C9
+S G$uart1_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrhex16
+F:G$uart1_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrhex16.uart1_writehex16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrhex16.uart1_writehex16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrhex16.uart1_writehex16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhex32
+
+;!FILE libmf/uart1wrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M uart1wrhex32
+O -mmcs51 --model-small
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S _uart1_writehex32 Def000000
+S XG$uart1_writehex32$0$0 Def000127
+S C$uart1wrhex32.c$282$1$62 Def000000
+S C$uart1wrhex32.c$283$1$62 Def000127
+S A$uart1wrhex32$210 Def000062
+S A$uart1wrhex32$120 Def000005
+S A$uart1wrhex32$310 Def0000D5
+S A$uart1wrhex32$220 Def00006F
+S A$uart1wrhex32$211 Def000063
+S A$uart1wrhex32$202 Def000058
+S A$uart1wrhex32$130 Def000010
+S A$uart1wrhex32$121 Def000007
+S A$uart1wrhex32$221 Def000070
+S A$uart1wrhex32$212 Def000065
+S A$uart1wrhex32$203 Def000059
+S A$uart1wrhex32$122 Def000008
+S A$uart1wrhex32$330 Def0000F1
+S A$uart1wrhex32$321 Def0000E1
+S A$uart1wrhex32$312 Def0000D8
+S A$uart1wrhex32$240 Def00007F
+S A$uart1wrhex32$231 Def000079
+S A$uart1wrhex32$222 Def000072
+S A$uart1wrhex32$213 Def000067
+S A$uart1wrhex32$204 Def00005A
+S A$uart1wrhex32$150 Def000024
+S A$uart1wrhex32$141 Def000014
+S A$uart1wrhex32$123 Def000009
+S A$uart1wrhex32$340 Def0000FA
+S A$uart1wrhex32$331 Def0000F3
+S A$uart1wrhex32$322 Def0000E2
+S A$uart1wrhex32$304 Def0000D0
+S A$uart1wrhex32$250 Def00008B
+S A$uart1wrhex32$241 Def000081
+S A$uart1wrhex32$223 Def000073
+S A$uart1wrhex32$205 Def00005B
+S A$uart1wrhex32$160 Def000030
+S A$uart1wrhex32$151 Def000026
+S A$uart1wrhex32$142 Def000017
+S A$uart1wrhex32$124 Def00000A
+S A$uart1wrhex32$350 Def00010D
+S A$uart1wrhex32$341 Def0000FC
+S A$uart1wrhex32$314 Def0000DB
+S A$uart1wrhex32$260 Def000097
+S A$uart1wrhex32$251 Def00008D
+S A$uart1wrhex32$215 Def000069
+S A$uart1wrhex32$206 Def00005C
+S A$uart1wrhex32$161 Def000033
+S A$uart1wrhex32$152 Def000027
+S A$uart1wrhex32$143 Def000018
+S A$uart1wrhex32$134 Def000012
+S A$uart1wrhex32$125 Def00000C
+S A$uart1wrhex32$116 Def000000
+S A$uart1wrhex32$360 Def000120
+S A$uart1wrhex32$351 Def00010E
+S A$uart1wrhex32$342 Def0000FD
+S A$uart1wrhex32$333 Def0000F5
+S A$uart1wrhex32$324 Def0000E4
+S A$uart1wrhex32$315 Def0000DC
+S A$uart1wrhex32$306 Def0000D2
+S A$uart1wrhex32$252 Def00008E
+S A$uart1wrhex32$243 Def000083
+S A$uart1wrhex32$225 Def000075
+S A$uart1wrhex32$216 Def00006A
+S A$uart1wrhex32$207 Def00005E
+S A$uart1wrhex32$162 Def000036
+S A$uart1wrhex32$153 Def000028
+S A$uart1wrhex32$144 Def00001B
+S A$uart1wrhex32$117 Def000001
+S A$uart1wrhex32$361 Def000122
+S A$uart1wrhex32$352 Def000110
+S A$uart1wrhex32$343 Def0000FF
+S A$uart1wrhex32$325 Def0000E6
+S A$uart1wrhex32$307 Def0000D4
+S A$uart1wrhex32$280 Def0000B3
+S A$uart1wrhex32$262 Def000099
+S A$uart1wrhex32$253 Def00008F
+S A$uart1wrhex32$244 Def000085
+S A$uart1wrhex32$217 Def00006C
+S A$uart1wrhex32$208 Def000060
+S A$uart1wrhex32$172 Def000040
+S A$uart1wrhex32$163 Def000038
+S A$uart1wrhex32$154 Def000029
+S A$uart1wrhex32$145 Def00001C
+S A$uart1wrhex32$127 Def00000E
+S A$uart1wrhex32$344 Def000101
+S A$uart1wrhex32$326 Def0000E8
+S A$uart1wrhex32$290 Def0000C3
+S A$uart1wrhex32$254 Def000091
+S A$uart1wrhex32$245 Def000088
+S A$uart1wrhex32$227 Def000076
+S A$uart1wrhex32$218 Def00006D
+S A$uart1wrhex32$173 Def000041
+S A$uart1wrhex32$164 Def00003A
+S A$uart1wrhex32$155 Def00002A
+S A$uart1wrhex32$146 Def00001D
+S A$uart1wrhex32$128 Def00000F
+S A$uart1wrhex32$119 Def000003
+S A$uart1wrhex32$363 Def000124
+S A$uart1wrhex32$354 Def000112
+S A$uart1wrhex32$345 Def000104
+S A$uart1wrhex32$327 Def0000EA
+S A$uart1wrhex32$318 Def0000DD
+S A$uart1wrhex32$291 Def0000C6
+S A$uart1wrhex32$282 Def0000B5
+S A$uart1wrhex32$273 Def0000A3
+S A$uart1wrhex32$264 Def00009C
+S A$uart1wrhex32$228 Def000078
+S A$uart1wrhex32$192 Def000051
+S A$uart1wrhex32$183 Def000048
+S A$uart1wrhex32$174 Def000043
+S A$uart1wrhex32$165 Def00003B
+S A$uart1wrhex32$156 Def00002B
+S A$uart1wrhex32$147 Def00001F
+S A$uart1wrhex32$355 Def000114
+S A$uart1wrhex32$346 Def000106
+S A$uart1wrhex32$328 Def0000EC
+S A$uart1wrhex32$319 Def0000DF
+S A$uart1wrhex32$292 Def0000C9
+S A$uart1wrhex32$283 Def0000B8
+S A$uart1wrhex32$274 Def0000A5
+S A$uart1wrhex32$247 Def00008A
+S A$uart1wrhex32$238 Def00007B
+S A$uart1wrhex32$193 Def000052
+S A$uart1wrhex32$184 Def00004B
+S A$uart1wrhex32$175 Def000044
+S A$uart1wrhex32$166 Def00003C
+S A$uart1wrhex32$157 Def00002C
+S A$uart1wrhex32$148 Def000021
+S A$uart1wrhex32$365 Def000125
+S A$uart1wrhex32$356 Def000116
+S A$uart1wrhex32$347 Def000108
+S A$uart1wrhex32$338 Def0000F6
+S A$uart1wrhex32$329 Def0000EF
+S A$uart1wrhex32$293 Def0000CB
+S A$uart1wrhex32$284 Def0000B9
+S A$uart1wrhex32$275 Def0000A7
+S A$uart1wrhex32$266 Def00009F
+S A$uart1wrhex32$257 Def000094
+S A$uart1wrhex32$239 Def00007D
+S A$uart1wrhex32$194 Def000053
+S A$uart1wrhex32$185 Def00004C
+S A$uart1wrhex32$176 Def000046
+S A$uart1wrhex32$158 Def00002E
+S A$uart1wrhex32$149 Def000022
+S A$uart1wrhex32$357 Def000118
+S A$uart1wrhex32$339 Def0000F8
+S A$uart1wrhex32$294 Def0000CD
+S A$uart1wrhex32$285 Def0000BB
+S A$uart1wrhex32$276 Def0000A9
+S A$uart1wrhex32$267 Def0000A0
+S A$uart1wrhex32$258 Def000095
+S A$uart1wrhex32$195 Def000054
+S A$uart1wrhex32$186 Def00004E
+S A$uart1wrhex32$177 Def000047
+S A$uart1wrhex32$168 Def00003E
+S A$uart1wrhex32$358 Def00011B
+S A$uart1wrhex32$349 Def00010A
+S A$uart1wrhex32$277 Def0000AC
+S A$uart1wrhex32$259 Def000096
+S A$uart1wrhex32$196 Def000056
+S A$uart1wrhex32$187 Def000050
+S A$uart1wrhex32$359 Def00011E
+S A$uart1wrhex32$296 Def0000CF
+S A$uart1wrhex32$287 Def0000BD
+S A$uart1wrhex32$278 Def0000AF
+S A$uart1wrhex32$269 Def0000A1
+S A$uart1wrhex32$197 Def000057
+S A$uart1wrhex32$288 Def0000BF
+S A$uart1wrhex32$279 Def0000B1
+S C$uart1wrhex32.c$25$0$0 Def000000
+S A$uart1wrhex32$289 Def0000C1
+S G$uart1_writehex32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrhex32
+F:G$uart1_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrhex32.uart1_writehex32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrhex32.uart1_writehex32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrhex32.uart1_writehex32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+adctemp
+
+;!FILE libmf/adctemp.asm
+XH3
+H 1A areas 33F global symbols
+M adctemp
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size AA flags 20 addr 0
+S C$adctemp.c$6$0$0 Def000000
+S G$adc_measure_temperature$0$0 Def000000
+S _adc_measure_temperature Def000000
+S A$adctemp$1200 Def000027
+S A$adctemp$1210 Def00003D
+S A$adctemp$1201 Def000029
+S A$adctemp$1301 Def0000A5
+S A$adctemp$1220 Def00004D
+S A$adctemp$1211 Def000040
+S A$adctemp$1202 Def00002C
+S A$adctemp$1302 Def0000A7
+S A$adctemp$1230 Def00005B
+S A$adctemp$1221 Def00004E
+S A$adctemp$1212 Def000042
+S A$adctemp$1203 Def00002E
+S A$adctemp$1240 Def00006B
+S A$adctemp$1231 Def00005E
+S A$adctemp$1222 Def00004F
+S A$adctemp$1213 Def000044
+S A$adctemp$1204 Def000031
+S A$adctemp$1250 Def000075
+S A$adctemp$1241 Def00006C
+S A$adctemp$1232 Def00005F
+S A$adctemp$1214 Def000046
+S A$adctemp$1205 Def000033
+S A$adctemp$1305 Def0000A9
+S A$adctemp$1260 Def00007F
+S A$adctemp$1251 Def000076
+S A$adctemp$1242 Def00006D
+S A$adctemp$1233 Def000060
+S A$adctemp$1215 Def000048
+S A$adctemp$1206 Def000036
+S A$adctemp$1261 Def000080
+S A$adctemp$1252 Def000077
+S A$adctemp$1243 Def00006E
+S A$adctemp$1234 Def000062
+S A$adctemp$1225 Def000051
+S A$adctemp$1216 Def000049
+S A$adctemp$1207 Def000039
+S A$adctemp$1180 Def000004
+S XG$adc_measure_temperature$0$0 Def0000A9
+S A$adctemp$1280 Def000093
+S A$adctemp$1271 Def000089
+S A$adctemp$1253 Def000078
+S A$adctemp$1244 Def00006F
+S A$adctemp$1235 Def000064
+S A$adctemp$1226 Def000053
+S A$adctemp$1217 Def00004A
+S A$adctemp$1190 Def000017
+S A$adctemp$1181 Def000006
+S A$adctemp$1290 Def00009B
+S A$adctemp$1281 Def000094
+S A$adctemp$1272 Def00008A
+S A$adctemp$1263 Def000083
+S A$adctemp$1245 Def000070
+S A$adctemp$1236 Def000067
+S A$adctemp$1227 Def000055
+S A$adctemp$1218 Def00004B
+S A$adctemp$1209 Def00003B
+S A$adctemp$1191 Def000018
+S A$adctemp$1182 Def000008
+S A$adctemp$1291 Def00009C
+S A$adctemp$1282 Def000095
+S A$adctemp$1273 Def00008B
+S A$adctemp$1264 Def000084
+S A$adctemp$1246 Def000071
+S A$adctemp$1237 Def000068
+S A$adctemp$1228 Def000057
+S A$adctemp$1219 Def00004C
+S A$adctemp$1192 Def000019
+S A$adctemp$1183 Def00000A
+S A$adctemp$1283 Def000096
+S A$adctemp$1274 Def00008C
+S A$adctemp$1265 Def000085
+S A$adctemp$1256 Def00007B
+S A$adctemp$1247 Def000072
+S A$adctemp$1238 Def000069
+S A$adctemp$1229 Def000059
+S A$adctemp$1193 Def00001A
+S A$adctemp$1184 Def00000C
+S C$adctemp.c$144$1$36 Def000000
+S A$adctemp$1293 Def00009F
+S A$adctemp$1275 Def00008D
+S A$adctemp$1266 Def000086
+S A$adctemp$1257 Def00007C
+S A$adctemp$1248 Def000073
+S A$adctemp$1239 Def00006A
+S A$adctemp$1194 Def00001B
+S A$adctemp$1185 Def00000E
+S C$adctemp.c$145$1$36 Def0000A9
+S A$adctemp$1294 Def0000A0
+S A$adctemp$1276 Def00008E
+S A$adctemp$1267 Def000087
+S A$adctemp$1258 Def00007D
+S A$adctemp$1249 Def000074
+S A$adctemp$1195 Def00001C
+S A$adctemp$1186 Def000011
+S A$adctemp$1295 Def0000A1
+S A$adctemp$1286 Def000097
+S A$adctemp$1268 Def000088
+S A$adctemp$1259 Def00007E
+S A$adctemp$1196 Def00001D
+S A$adctemp$1187 Def000013
+S A$adctemp$1178 Def000000
+S A$adctemp$1296 Def0000A2
+S A$adctemp$1287 Def000098
+S A$adctemp$1278 Def000091
+S A$adctemp$1197 Def00001F
+S A$adctemp$1188 Def000014
+S A$adctemp$1179 Def000001
+S A$adctemp$1297 Def0000A3
+S A$adctemp$1288 Def000099
+S A$adctemp$1279 Def000092
+S A$adctemp$1198 Def000022
+S A$adctemp$1189 Def000015
+S A$adctemp$1298 Def0000A4
+S A$adctemp$1289 Def00009A
+S A$adctemp$1199 Def000024
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E4 85 A8 F0 F5 A8 A8 98 F5 98 A9 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 28 74 01 F0 A3 74 06 F0 A3 E0
+R 00 00 00 16
+T 00 00 1A FA E4 F0 AB D1 75 D1 30 AC CA 75 CA D8
+R 00 00 00 16
+T 00 00 27 AD CB 75 CB D8 AE D2 75 D2 D8 AF D3 75
+R 00 00 00 16
+T 00 00 34 D3 D8 75 C9 01 D2 9E
+R 00 00 00 16
+T 00 00 3B
+R 00 00 00 16
+T 00 00 3B E5 C9 20 E7 11 E5 87 54 0C 44 01 F5 87
+R 00 00 00 16
+T 00 00 48 00 00 00 00 00 00 00 80 EA
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 8C CA 8D CB 8E D2 8F D3 8B D1 90 70 2A
+R 00 00 00 16
+T 00 00 5E EA F0 88 98 89 A0 90 70 22 E0 FA A3 E0
+R 00 00 00 16
+T 00 00 6B FB A3 E0 FC A3 E0 FD A3 E0 FE A3 E0 FF
+R 00 00 00 16
+T 00 00 78 85 F0 A8 EC C3 9A ED 9B 30 E7 06 EA CC
+R 00 00 00 16
+T 00 00 85 FA EB CD FB
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 EE C3 9C EF 9D 30 E7 06 EC CE FC ED CF
+R 00 00 00 16
+T 00 00 96 FD
+R 00 00 00 16
+T 00 00 97
+R 00 00 00 16
+T 00 00 97 EC C3 9A ED 9B 30 E7 06 EA CC FA EB CD
+R 00 00 00 16
+T 00 00 A4 FB
+R 00 00 00 16
+T 00 00 A5
+R 00 00 00 16
+T 00 00 A5 8C 82 8D 83 22
+R 00 00 00 16
+
+
+M:adctemp
+F:G$adc_measure_temperature$0$0({2}DF,SI:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccal
+
+;!FILE libmf/adccal.asm
+XH3
+H 1A areas 2D5 global symbols
+M adccal
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _adc_calibrate_gain Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _adc_calibrate_temp Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S G$adc_calibrate$0$0 Def000000
+S C$adccal.c$6$1$36 Def000000
+S C$adccal.c$7$1$36 Def000003
+S _adc_calibrate Def000000
+S C$adccal.c$8$1$36 Def000006
+S C$adccal.c$4$0$0 Def000000
+S XG$adc_calibrate$0$0 Def000006
+S A$adccal$1180 Def000000
+S A$adccal$1183 Def000003
+S A$adccal$1186 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 12 00 00 12 00 00 22
+R 00 00 00 16 02 04 00 7F 02 07 01 62
+
+
+M:adccal
+F:G$adc_calibrate$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
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+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
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+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
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+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
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+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
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+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
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+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
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+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$DIRC$0$0({1}SC:U),I,0,0
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+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
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+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
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+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
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+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
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+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
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+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
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+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccalg
+
+;!FILE libmf/adccalg.asm
+XH3
+H 1A areas 36E global symbols
+M adccalg
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S __divslong_PARM_2 Ref000000
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S __divslong Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _ADCCALG00GAIN0 Def007030
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG00GAIN1 Def007031
+S _ADCCALG01GAIN0 Def007032
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F9 flags 20 addr 0
+S _adc_calibrate_gain Def000000
+S A$adccalg$1300 Def00008F
+S A$adccalg$1210 Def00000C
+S A$adccalg$1310 Def00009B
+S A$adccalg$1301 Def000091
+S A$adccalg$1220 Def00001C
+S A$adccalg$1211 Def00000E
+S A$adccalg$1320 Def0000B1
+S A$adccalg$1311 Def00009D
+S A$adccalg$1230 Def000032
+S A$adccalg$1221 Def00001F
+S A$adccalg$1212 Def000010
+S A$adccalg$1330 Def0000C1
+S A$adccalg$1321 Def0000B3
+S A$adccalg$1312 Def00009F
+S A$adccalg$1240 Def000045
+S A$adccalg$1222 Def000022
+S A$adccalg$1213 Def000011
+S A$adccalg$1204 Def000000
+S A$adccalg$1340 Def0000D7
+S A$adccalg$1331 Def0000C3
+S A$adccalg$1322 Def0000B6
+S A$adccalg$1313 Def0000A0
+S A$adccalg$1250 Def000051
+S A$adccalg$1241 Def000046
+S A$adccalg$1232 Def000035
+S A$adccalg$1223 Def000025
+S A$adccalg$1214 Def000012
+S A$adccalg$1205 Def000001
+S A$adccalg$1350 Def0000EA
+S A$adccalg$1341 Def0000D8
+S A$adccalg$1332 Def0000C6
+S A$adccalg$1323 Def0000B7
+S A$adccalg$1314 Def0000A2
+S A$adccalg$1260 Def00005B
+S A$adccalg$1251 Def000052
+S A$adccalg$1242 Def000047
+S A$adccalg$1233 Def000037
+S A$adccalg$1224 Def000028
+S A$adccalg$1215 Def000013
+S A$adccalg$1206 Def000003
+S A$adccalg$1360 Def0000F8
+S A$adccalg$1351 Def0000ED
+S A$adccalg$1342 Def0000D9
+S A$adccalg$1333 Def0000C9
+S A$adccalg$1324 Def0000B8
+S A$adccalg$1315 Def0000A4
+S A$adccalg$1306 Def000093
+S A$adccalg$1270 Def000067
+S A$adccalg$1261 Def00005C
+S A$adccalg$1252 Def000053
+S A$adccalg$1243 Def000048
+S A$adccalg$1234 Def000039
+S A$adccalg$1225 Def00002A
+S A$adccalg$1216 Def000014
+S A$adccalg$1207 Def000005
+S A$adccalg$1352 Def0000EF
+S A$adccalg$1343 Def0000DB
+S A$adccalg$1334 Def0000CB
+S A$adccalg$1325 Def0000B9
+S A$adccalg$1316 Def0000A7
+S A$adccalg$1307 Def000095
+S A$adccalg$1280 Def000072
+S A$adccalg$1271 Def000068
+S A$adccalg$1262 Def00005E
+S A$adccalg$1253 Def000054
+S A$adccalg$1244 Def00004A
+S A$adccalg$1235 Def00003B
+S A$adccalg$1226 Def00002B
+S A$adccalg$1217 Def000015
+S A$adccalg$1208 Def000007
+S A$adccalg$1353 Def0000F1
+S A$adccalg$1344 Def0000DD
+S A$adccalg$1335 Def0000CE
+S A$adccalg$1326 Def0000BA
+S A$adccalg$1317 Def0000AA
+S A$adccalg$1308 Def000097
+S A$adccalg$1290 Def00007D
+S A$adccalg$1281 Def000073
+S A$adccalg$1272 Def000069
+S A$adccalg$1263 Def00005F
+S A$adccalg$1254 Def000055
+S A$adccalg$1245 Def00004B
+S A$adccalg$1236 Def00003D
+S A$adccalg$1227 Def00002E
+S A$adccalg$1218 Def000016
+S A$adccalg$1209 Def00000A
+S A$adccalg$1354 Def0000F4
+S A$adccalg$1345 Def0000DE
+S A$adccalg$1336 Def0000D0
+S A$adccalg$1327 Def0000BC
+S A$adccalg$1318 Def0000AC
+S A$adccalg$1309 Def000099
+S A$adccalg$1291 Def00007F
+S A$adccalg$1282 Def000074
+S A$adccalg$1273 Def00006B
+S A$adccalg$1264 Def000060
+S A$adccalg$1255 Def000057
+S A$adccalg$1246 Def00004C
+S A$adccalg$1237 Def00003F
+S A$adccalg$1228 Def00002F
+S A$adccalg$1219 Def000019
+S A$adccalg$1355 Def0000F5
+S A$adccalg$1346 Def0000E0
+S A$adccalg$1337 Def0000D2
+S A$adccalg$1328 Def0000BE
+S A$adccalg$1319 Def0000AF
+S A$adccalg$1292 Def000080
+S A$adccalg$1283 Def000075
+S A$adccalg$1274 Def00006C
+S A$adccalg$1265 Def000061
+S A$adccalg$1256 Def000058
+S A$adccalg$1247 Def00004D
+S A$adccalg$1238 Def000042
+S A$adccalg$1356 Def0000F6
+S A$adccalg$1347 Def0000E2
+S A$adccalg$1338 Def0000D5
+S A$adccalg$1329 Def0000BF
+S A$adccalg$1293 Def000081
+S A$adccalg$1284 Def000076
+S A$adccalg$1266 Def000062
+S A$adccalg$1248 Def00004E
+S XG$adc_calibrate_gain$0$0 Def0000F8
+S A$adccalg$1357 Def0000F7
+S A$adccalg$1348 Def0000E5
+S A$adccalg$1339 Def0000D6
+S A$adccalg$1285 Def000077
+S A$adccalg$1276 Def00006D
+S A$adccalg$1267 Def000063
+S A$adccalg$1258 Def000059
+S A$adccalg$1249 Def00004F
+S A$adccalg$1349 Def0000E8
+S A$adccalg$1295 Def000084
+S A$adccalg$1286 Def000079
+S A$adccalg$1277 Def00006E
+S A$adccalg$1268 Def000065
+S A$adccalg$1259 Def00005A
+S A$adccalg$1296 Def000087
+S A$adccalg$1287 Def00007A
+S A$adccalg$1278 Def00006F
+S A$adccalg$1269 Def000066
+S A$adccalg$1297 Def000089
+S A$adccalg$1288 Def00007B
+S A$adccalg$1279 Def000070
+S A$adccalg$1298 Def00008A
+S A$adccalg$1289 Def00007C
+S A$adccalg$1299 Def00008D
+S C$adccalg.c$178$1$36 Def000000
+S C$adccalg.c$179$1$36 Def0000F8
+S C$adccalg.c$13$0$0 Def000000
+S G$adc_calibrate_gain$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E4 C0 A8 F5 A8 C0 98 75 98 40 C0 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 F5 C9 F8 F9 FA FB FC FD 75 D1 28 75
+R 00 00 00 16
+T 00 00 1A CA E0 75 CB E8 75 D2 F0 75 D3 FF 90
+R 00 00 00 16
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+
+
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+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccalt
+
+;!FILE libmf/adccalt.asm
+XH3
+H 1A areas 35B global symbols
+M adccalt
+O -mmcs51 --model-small
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S __divslong_PARM_2 Ref000000
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S __mullong_PARM_2 Ref000000
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S __divslong Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$ADCCALTEMPGAIN0$0$0 Def007038
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$ADCCALTEMPGAIN1$0$0 Def007039
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S __mullong Ref000000
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _ADCCALTEMPGAIN0 Def007038
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _ADCCALTEMPGAIN1 Def007039
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$ADCCALTEMPOFFS0$0$0 Def00703A
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E1 flags 20 addr 0
+S G$adc_calibrate_temp$0$0 Def000000
+S A$adccalt$1200 Def000003
+S A$adccalt$1300 Def0000A1
+S A$adccalt$1210 Def000014
+S A$adccalt$1201 Def000005
+S A$adccalt$1310 Def0000AF
+S A$adccalt$1301 Def0000A2
+S A$adccalt$1220 Def00002D
+S A$adccalt$1211 Def000017
+S A$adccalt$1202 Def000007
+S A$adccalt$1311 Def0000B2
+S A$adccalt$1302 Def0000A3
+S A$adccalt$1230 Def000040
+S A$adccalt$1212 Def00001A
+S A$adccalt$1203 Def00000A
+S A$adccalt$1330 Def0000D5
+S A$adccalt$1321 Def0000C1
+S A$adccalt$1312 Def0000B4
+S A$adccalt$1303 Def0000A5
+S A$adccalt$1240 Def00004C
+S A$adccalt$1222 Def000030
+S A$adccalt$1213 Def00001D
+S A$adccalt$1204 Def00000C
+S A$adccalt$1331 Def0000D7
+S A$adccalt$1322 Def0000C3
+S A$adccalt$1313 Def0000B6
+S A$adccalt$1304 Def0000A6
+S A$adccalt$1250 Def000057
+S A$adccalt$1241 Def00004D
+S A$adccalt$1232 Def000043
+S A$adccalt$1214 Def000020
+S A$adccalt$1205 Def00000E
+S A$adccalt$1332 Def0000D9
+S A$adccalt$1323 Def0000C5
+S A$adccalt$1314 Def0000B8
+S A$adccalt$1305 Def0000A7
+S A$adccalt$1260 Def000063
+S A$adccalt$1251 Def000058
+S A$adccalt$1242 Def00004F
+S A$adccalt$1233 Def000044
+S A$adccalt$1224 Def000033
+S A$adccalt$1215 Def000023
+S A$adccalt$1206 Def000010
+S A$adccalt$1333 Def0000DC
+S A$adccalt$1324 Def0000C6
+S A$adccalt$1315 Def0000BB
+S A$adccalt$1306 Def0000A9
+S A$adccalt$1270 Def000071
+S A$adccalt$1261 Def000064
+S A$adccalt$1252 Def000059
+S A$adccalt$1243 Def000050
+S A$adccalt$1234 Def000045
+S A$adccalt$1225 Def000035
+S A$adccalt$1216 Def000026
+S A$adccalt$1207 Def000011
+S A$adccalt$1334 Def0000DD
+S A$adccalt$1325 Def0000C8
+S A$adccalt$1316 Def0000BC
+S A$adccalt$1307 Def0000AA
+S A$adccalt$1271 Def000073
+S A$adccalt$1262 Def000065
+S A$adccalt$1253 Def00005A
+S A$adccalt$1244 Def000051
+S A$adccalt$1235 Def000046
+S A$adccalt$1226 Def000037
+S A$adccalt$1217 Def000028
+S A$adccalt$1208 Def000012
+S A$adccalt$1335 Def0000DE
+S A$adccalt$1326 Def0000CA
+S A$adccalt$1317 Def0000BD
+S A$adccalt$1308 Def0000AC
+S A$adccalt$1290 Def00008B
+S A$adccalt$1281 Def00007D
+S A$adccalt$1272 Def000074
+S A$adccalt$1263 Def000066
+S A$adccalt$1254 Def00005C
+S A$adccalt$1245 Def000052
+S A$adccalt$1236 Def000048
+S A$adccalt$1227 Def000039
+S A$adccalt$1218 Def000029
+S A$adccalt$1209 Def000013
+S A$adccalt$1336 Def0000DF
+S A$adccalt$1327 Def0000CD
+S A$adccalt$1318 Def0000BE
+S A$adccalt$1309 Def0000AE
+S A$adccalt$1291 Def00008D
+S A$adccalt$1282 Def00007F
+S A$adccalt$1273 Def000077
+S A$adccalt$1264 Def000067
+S A$adccalt$1255 Def00005D
+S A$adccalt$1246 Def000053
+S A$adccalt$1237 Def000049
+S A$adccalt$1228 Def00003B
+S A$adccalt$1219 Def00002C
+S C$adccalt.c$161$1$36 Def000000
+S _adc_calibrate_temp Def000000
+S A$adccalt$1328 Def0000D0
+S A$adccalt$1319 Def0000C0
+S A$adccalt$1292 Def000090
+S A$adccalt$1274 Def000079
+S A$adccalt$1265 Def000069
+S A$adccalt$1256 Def00005E
+S A$adccalt$1247 Def000055
+S A$adccalt$1238 Def00004A
+S A$adccalt$1229 Def00003D
+S C$adccalt.c$162$1$36 Def0000E0
+S A$adccalt$1329 Def0000D2
+S A$adccalt$1293 Def000093
+S A$adccalt$1284 Def000081
+S A$adccalt$1275 Def00007B
+S A$adccalt$1266 Def00006A
+S A$adccalt$1257 Def00005F
+S A$adccalt$1248 Def000056
+S A$adccalt$1239 Def00004B
+S A$adccalt$1339 Def0000E0
+S A$adccalt$1294 Def000095
+S A$adccalt$1285 Def000083
+S A$adccalt$1267 Def00006B
+S A$adccalt$1258 Def000060
+S A$adccalt$1295 Def000098
+S A$adccalt$1286 Def000085
+S A$adccalt$1259 Def000061
+S A$adccalt$1296 Def000099
+S A$adccalt$1287 Def000086
+S A$adccalt$1269 Def00006E
+S A$adccalt$1297 Def00009B
+S A$adccalt$1288 Def000087
+S A$adccalt$1198 Def000000
+S A$adccalt$1298 Def00009D
+S A$adccalt$1289 Def000089
+S A$adccalt$1199 Def000001
+S A$adccalt$1299 Def00009F
+S XG$adc_calibrate_temp$0$0 Def0000E0
+S C$adccalt.c$11$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E4 C0 A8 F5 A8 C0 98 75 98 40 C0 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 F5 C9 F8 F9 FA FB 75 D1 28 75 CA F8
+R 00 00 00 16
+T 00 00 1A 75 CB F9 75 D2 FF 75 D3 FF 90 70 29 74
+R 00 00 00 16
+T 00 00 27 F2 F0 90 70 20 E0 75 F0 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 75 C9 01
+R 00 00 00 16
+T 00 00 33
+R 00 00 00 16
+T 00 00 33 E5 87 54 0C 44 01 F5 87 E5 D1 20 E7 F3
+R 00 00 00 16
+T 00 00 40 90 70 20 E0 A3 C4 54 0F FE E0 A3 C4 FF
+R 00 00 00 16
+T 00 00 4D 54 F0 4E 28 F8 EF 54 0F 39 F9 E0 A3 C4
+R 00 00 00 16
+T 00 00 5A 54 0F FE E0 A3 C4 FF 54 F0 4E 2A FA EF
+R 00 00 00 16
+T 00 00 67 54 0F 3B FB D5 F0 C2 90 70 29 74 02 F0
+R 00 00 00 16
+T 00 00 74 75 D1 07 D0 A0 D0 98 D0 A8 C0 00 C0 01
+R 00 00 00 16
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+R 00 00 00 16 F1 23 04 01 2E F1 23 08 01 2E
+T 00 00 8A 00 00 02 F5 00 00 03 90 A5 32 75 F0 00
+R 00 00 00 16 F1 23 03 01 2E F1 23 07 01 2E
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+R 00 00 00 16 02 06 02 96
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+R 00 00 00 16 F1 23 07 00 2B F1 23 0D 00 2B
+T 00 00 A9 E4 F5 00 00 02 F5 00 00 03 E9 12
+R 00 00 00 16 F1 23 05 00 2B F1 23 09 00 2B
+T 00 00 B0 00 00 A8 83 E5 82 24 77 90 70 3A F0 A3
+R 00 00 00 16 02 03 01 69
+T 00 00 BD E8 34 3F F0 D0 00 00 01 D0 00 00 00 E4
+R 00 00 00 16 F1 23 08 00 2B F1 23 0C 00 2B
+T 00 00 C6 F5 00 00 02 F5 00 00 03 90 83 12 75 F0
+R 00 00 00 16 F1 23 04 00 2B F1 23 08 00 2B
+T 00 00 CF C0 74 13 12 00 00 E5 82 A8 83 90 70 38
+R 00 00 00 16 02 07 01 69
+T 00 00 DC F0 A3 E8 F0 22
+R 00 00 00 16
+
+
+M:adccalt
+F:G$adc_calibrate_temp$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
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+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
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+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
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+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
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+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPGAIN0$0$0({1}SC:U),F,0,0
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+S:G$ADCCALTEMPOFFS0$0$0({1}SC:U),F,0,0
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+S:G$ACC$0$0({1}SC:U),I,0,0
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+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
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+S:G$PORTB$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
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+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
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+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
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+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
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+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
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+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
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+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
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+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
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+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
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+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
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+S:G$T1CNT$0$0({2}SI:U),I,0,0
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+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
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+S:G$U0SHREG$0$0({1}SC:U),I,0,0
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+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
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+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
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+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcuncal
+
+;!FILE libmf/adcuncal.asm
+XH3
+H 1A areas 30A global symbols
+M adcuncal
+O -mmcs51 --model-small
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _ADCCALG00GAIN0 Def007030
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG00GAIN1 Def007031
+S _ADCCALG01GAIN0 Def007032
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
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+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$ADCCALTEMPGAIN1$0$0 Def007039
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _ADCCALTEMPGAIN0 Def007038
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _ADCCALTEMPGAIN1 Def007039
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$ADCCALTEMPOFFS0$0$0 Def00703A
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
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+A GSINIT2 size 0 flags 20 addr 0
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 36 flags 20 addr 0
+S A$adcuncal$1210 Def000004
+S A$adcuncal$1220 Def00000F
+S A$adcuncal$1230 Def00001A
+S A$adcuncal$1240 Def000025
+S A$adcuncal$1213 Def000005
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+S A$adcuncal$1214 Def000008
+S A$adcuncal$1233 Def00001B
+S A$adcuncal$1224 Def000013
+S A$adcuncal$1215 Def00000A
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+S A$adcuncal$1234 Def00001E
+S A$adcuncal$1225 Def000015
+S A$adcuncal$1253 Def000031
+S A$adcuncal$1244 Def000029
+S A$adcuncal$1235 Def000020
+S A$adcuncal$1208 Def000000
+S A$adcuncal$1254 Def000034
+S A$adcuncal$1245 Def00002B
+S A$adcuncal$1218 Def00000B
+S A$adcuncal$1209 Def000003
+S A$adcuncal$1228 Def000016
+S A$adcuncal$1219 Def00000E
+S A$adcuncal$1238 Def000021
+S A$adcuncal$1229 Def000019
+S A$adcuncal$1257 Def000035
+S A$adcuncal$1248 Def00002C
+S A$adcuncal$1239 Def000024
+S A$adcuncal$1249 Def00002F
+S C$adcuncal.c$20$1$36 Def000010
+S C$adcuncal.c$21$1$36 Def000016
+S C$adcuncal.c$22$1$36 Def00001B
+S C$adcuncal.c$23$1$36 Def000021
+S C$adcuncal.c$24$1$36 Def000026
+S C$adcuncal.c$25$1$36 Def00002C
+S C$adcuncal.c$26$1$36 Def000031
+S C$adcuncal.c$17$1$36 Def000000
+S C$adcuncal.c$27$1$36 Def000035
+S C$adcuncal.c$18$1$36 Def000005
+S C$adcuncal.c$19$1$36 Def00000B
+S G$adc_uncalibrate$0$0 Def000000
+S C$adcuncal.c$15$0$0 Def000000
+S _adc_uncalibrate Def000000
+S XG$adc_uncalibrate$0$0 Def000035
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 30 E4 F0 90 70 31 74 40 F0 90
+R 00 00 00 16
+T 00 00 0C 70 32 E4 F0 90 70 33 74 40 F0 90 70 34
+R 00 00 00 16
+T 00 00 19 E4 F0 90 70 35 74 40 F0 90 70 38 E4 F0
+R 00 00 00 16
+T 00 00 26 90 70 39 74 40 F0 90 70 3A E4 F0 90
+R 00 00 00 16
+T 00 00 32 70 3B F0 22
+R 00 00 00 16
+
+
+M:adcuncal
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+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs00
+
+;!FILE libmf/adcseoffs00.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs00
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
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+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
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+S _WTEVTA0 Def0000F4
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+S G$FRCOSCPER1$0$0 Def007079
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+S G$ADCCH1VAL1$0$0 Def007023
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+S G$ADCCH3VAL0$0$0 Def007026
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+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN$0$0({2}SI:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs01
+
+;!FILE libmf/adcseoffs01.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs01
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG01GAIN0 Def007032
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _E2IP Def0000C0
+S _P Def0000D0
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+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
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+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
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+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
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+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
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+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
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+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
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+S G$OC0COMP1$0$0 Def0000BD
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+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
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+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
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+S _PORTB_0 Def000088
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+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
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+S _PORTB_1 Def000089
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+S _T0CNT1 Def00009D
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+S _PORTA_5 Def000085
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+S _RADIOSTAT0 Def0000BE
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+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
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+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN$0$0({2}SI:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs10
+
+;!FILE libmf/adcseoffs10.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs10
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$ADCCALG10GAIN$0$0 Def007034
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _ADCCALG10GAIN Def007034
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
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+A REG_BANK_0 size 8 flags 4 addr 0
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+A OSEG size 0 flags 4 addr 0
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+A IABS size 0 flags 8 addr 0
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+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
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+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
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+S C$adcseoffs10.c$8$0$0 Def000000
+S XG$adc_singleended_offset_x10$0$0 Def000051
+S A$adcseoffs10$1200 Def00000A
+S A$adcseoffs10$1201 Def00000B
+S A$adcseoffs10$1220 Def00001D
+S A$adcseoffs10$1211 Def000013
+S A$adcseoffs10$1202 Def00000C
+S A$adcseoffs10$1230 Def000026
+S A$adcseoffs10$1221 Def00001F
+S A$adcseoffs10$1212 Def000014
+S A$adcseoffs10$1240 Def00002F
+S A$adcseoffs10$1231 Def000027
+S A$adcseoffs10$1222 Def000020
+S A$adcseoffs10$1213 Def000015
+S A$adcseoffs10$1250 Def000038
+S A$adcseoffs10$1241 Def000030
+S A$adcseoffs10$1232 Def000028
+S A$adcseoffs10$1223 Def000021
+S A$adcseoffs10$1214 Def000016
+S A$adcseoffs10$1205 Def00000D
+S A$adcseoffs10$1260 Def000040
+S A$adcseoffs10$1251 Def000039
+S A$adcseoffs10$1242 Def000031
+S A$adcseoffs10$1224 Def000022
+S A$adcseoffs10$1215 Def000017
+S A$adcseoffs10$1206 Def00000F
+S A$adcseoffs10$1261 Def000041
+S A$adcseoffs10$1252 Def00003A
+S A$adcseoffs10$1243 Def000033
+S A$adcseoffs10$1216 Def000018
+S A$adcseoffs10$1207 Def000011
+S A$adcseoffs10$1271 Def00004B
+S A$adcseoffs10$1262 Def000043
+S A$adcseoffs10$1253 Def00003B
+S A$adcseoffs10$1244 Def000034
+S A$adcseoffs10$1235 Def000029
+S A$adcseoffs10$1217 Def000019
+S A$adcseoffs10$1208 Def000012
+S A$adcseoffs10$1281 Def000051
+S A$adcseoffs10$1272 Def00004C
+S A$adcseoffs10$1263 Def000044
+S A$adcseoffs10$1254 Def00003C
+S A$adcseoffs10$1245 Def000035
+S A$adcseoffs10$1236 Def00002A
+S A$adcseoffs10$1227 Def000023
+S A$adcseoffs10$1218 Def00001B
+S A$adcseoffs10$1191 Def000000
+S A$adcseoffs10$1282 Def000053
+S A$adcseoffs10$1273 Def00004D
+S A$adcseoffs10$1264 Def000045
+S A$adcseoffs10$1246 Def000036
+S A$adcseoffs10$1237 Def00002B
+S A$adcseoffs10$1228 Def000024
+S A$adcseoffs10$1219 Def00001C
+S A$adcseoffs10$1192 Def000003
+S A$adcseoffs10$1283 Def000055
+S A$adcseoffs10$1274 Def00004E
+S A$adcseoffs10$1265 Def000047
+S A$adcseoffs10$1238 Def00002C
+S A$adcseoffs10$1229 Def000025
+S A$adcseoffs10$1193 Def000004
+S A$adcseoffs10$1275 Def00004F
+S A$adcseoffs10$1266 Def000048
+S A$adcseoffs10$1257 Def00003D
+S A$adcseoffs10$1239 Def00002D
+S A$adcseoffs10$1194 Def000005
+S A$adcseoffs10$1276 Def000050
+S A$adcseoffs10$1267 Def000049
+S A$adcseoffs10$1258 Def00003E
+S A$adcseoffs10$1249 Def000037
+S A$adcseoffs10$1195 Def000006
+S A$adcseoffs10$1268 Def00004A
+S A$adcseoffs10$1259 Def00003F
+S A$adcseoffs10$1198 Def000007
+S A$adcseoffs10$1199 Def000008
+S C$adcseoffs10.c$20$1$36 Def000029
+S C$adcseoffs10.c$21$1$36 Def000037
+S C$adcseoffs10.c$22$1$36 Def00003D
+S C$adcseoffs10.c$23$1$36 Def00004B
+S C$adcseoffs10.c$24$1$36 Def000051
+S C$adcseoffs10.c$25$1$36 Def000051
+S C$adcseoffs10.c$16$1$36 Def000007
+S C$adcseoffs10.c$17$1$36 Def00000D
+S C$adcseoffs10.c$18$1$36 Def000013
+S C$adcseoffs10.c$11$1$0 Def000000
+S C$adcseoffs10.c$19$1$36 Def000023
+S G$adc_singleended_offset_x10$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
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+T 00 00 00 90 70 34 E0 FE A3 E0 CE 25 E0 CE 33 FF
+R 00 00 00 17
+T 00 00 0D 8E 04 74 80 2F FD EF C4 03 CE C4 03 54
+R 00 00 00 17
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+R 00 00 00 17
+T 00 00 27 3D FD EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 17
+T 00 00 34 6E CE FF EE 2C FC EF 3D FD EF C4 CE C4
+R 00 00 00 17
+T 00 00 41 54 0F 6E CE 54 0F CE 6E CE FF EC C3 9E
+R 00 00 00 17
+T 00 00 4E FC ED 9F 8C 82 F5 83 22
+R 00 00 00 17
+
+
+M:adcseoffs10
+F:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN$0$0({2}SI:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
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+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
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+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+bch3121dec
+
+;!FILE libmf/bch3121dec.asm
+XH3
+H 1A areas 35B global symbols
+M bch3121dec
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S _bch3121_syndrometable Ref000000
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Lbch3121dec.bch3121_decode$cw$1$32 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size C8 flags 20 addr 0
+S C$bch3121dec.c$14$1$33 Def000076
+S C$bch3121dec.c$15$1$33 Def000085
+S C$bch3121dec.c$16$1$33 Def00008C
+S C$bch3121dec.c$17$1$33 Def0000B5
+S C$bch3121dec.c$18$1$33 Def0000C7
+S G$bch3121_decode$0$0 Def000000
+S C$bch3121dec.c$6$1$33 Def000000
+S C$bch3121dec.c$8$1$33 Def000012
+S _bch3121_decode Def000000
+S C$bch3121dec.c$4$0$0 Def000000
+S XG$bch3121_decode$0$0 Def0000C7
+S A$bch3121dec$1200 Def000019
+S A$bch3121dec$1300 Def000098
+S A$bch3121dec$1210 Def000027
+S A$bch3121dec$1201 Def00001A
+S A$bch3121dec$1310 Def0000A2
+S A$bch3121dec$1220 Def000031
+S A$bch3121dec$1211 Def000028
+S A$bch3121dec$1202 Def00001B
+S A$bch3121dec$1320 Def0000AF
+S A$bch3121dec$1311 Def0000A3
+S A$bch3121dec$1302 Def00009A
+S A$bch3121dec$1230 Def000041
+S A$bch3121dec$1212 Def000029
+S A$bch3121dec$1203 Def00001C
+S A$bch3121dec$1330 Def0000BC
+S A$bch3121dec$1321 Def0000B0
+S A$bch3121dec$1312 Def0000A4
+S A$bch3121dec$1303 Def00009B
+S A$bch3121dec$1231 Def000043
+S A$bch3121dec$1213 Def00002A
+S A$bch3121dec$1204 Def00001E
+S A$bch3121dec$1331 Def0000BE
+S A$bch3121dec$1322 Def0000B2
+S A$bch3121dec$1313 Def0000A5
+S A$bch3121dec$1304 Def00009C
+S A$bch3121dec$1250 Def00005B
+S A$bch3121dec$1232 Def000045
+S A$bch3121dec$1223 Def000034
+S A$bch3121dec$1214 Def00002B
+S A$bch3121dec$1205 Def000020
+S A$bch3121dec$1332 Def0000C0
+S A$bch3121dec$1323 Def0000B3
+S A$bch3121dec$1305 Def00009D
+S A$bch3121dec$1260 Def000065
+S A$bch3121dec$1251 Def00005C
+S A$bch3121dec$1242 Def00004D
+S A$bch3121dec$1233 Def000046
+S A$bch3121dec$1224 Def000036
+S A$bch3121dec$1206 Def000021
+S A$bch3121dec$1333 Def0000C2
+S A$bch3121dec$1315 Def0000A6
+S A$bch3121dec$1306 Def00009E
+S A$bch3121dec$1270 Def000073
+S A$bch3121dec$1261 Def000066
+S A$bch3121dec$1252 Def00005D
+S A$bch3121dec$1243 Def00004F
+S A$bch3121dec$1225 Def000038
+S A$bch3121dec$1207 Def000023
+S A$bch3121dec$1334 Def0000C4
+S A$bch3121dec$1316 Def0000A9
+S A$bch3121dec$1307 Def00009F
+S A$bch3121dec$1280 Def00007C
+S A$bch3121dec$1271 Def000074
+S A$bch3121dec$1253 Def00005E
+S A$bch3121dec$1244 Def000051
+S A$bch3121dec$1226 Def000039
+S A$bch3121dec$1217 Def00002C
+S A$bch3121dec$1208 Def000025
+S A$bch3121dec$1190 Def00000B
+S A$bch3121dec$1335 Def0000C6
+S A$bch3121dec$1326 Def0000B5
+S A$bch3121dec$1317 Def0000AA
+S A$bch3121dec$1308 Def0000A0
+S A$bch3121dec$1290 Def000088
+S A$bch3121dec$1281 Def00007E
+S A$bch3121dec$1263 Def000067
+S A$bch3121dec$1254 Def00005F
+S A$bch3121dec$1245 Def000053
+S A$bch3121dec$1227 Def00003B
+S A$bch3121dec$1218 Def00002E
+S A$bch3121dec$1209 Def000026
+S A$bch3121dec$1191 Def00000E
+S A$bch3121dec$1327 Def0000B7
+S A$bch3121dec$1318 Def0000AC
+S A$bch3121dec$1309 Def0000A1
+S A$bch3121dec$1291 Def00008A
+S A$bch3121dec$1282 Def00007F
+S A$bch3121dec$1264 Def00006A
+S A$bch3121dec$1255 Def000060
+S A$bch3121dec$1246 Def000055
+S A$bch3121dec$1237 Def000049
+S A$bch3121dec$1228 Def00003D
+S A$bch3121dec$1219 Def000030
+S A$bch3121dec$1192 Def000010
+S A$bch3121dec$1328 Def0000B9
+S A$bch3121dec$1319 Def0000AD
+S A$bch3121dec$1283 Def000080
+S A$bch3121dec$1274 Def000076
+S A$bch3121dec$1265 Def00006B
+S A$bch3121dec$1256 Def000061
+S A$bch3121dec$1247 Def000057
+S A$bch3121dec$1238 Def00004B
+S A$bch3121dec$1229 Def00003F
+S A$bch3121dec$1329 Def0000BA
+S A$bch3121dec$1284 Def000082
+S A$bch3121dec$1275 Def000077
+S A$bch3121dec$1266 Def00006D
+S A$bch3121dec$1257 Def000062
+S A$bch3121dec$1248 Def000059
+S A$bch3121dec$1239 Def00004C
+S A$bch3121dec$1339 Def0000C7
+S A$bch3121dec$1294 Def00008C
+S A$bch3121dec$1285 Def000083
+S A$bch3121dec$1276 Def000078
+S A$bch3121dec$1267 Def00006E
+S A$bch3121dec$1258 Def000063
+S A$bch3121dec$1195 Def000012
+S A$bch3121dec$1186 Def000000
+S A$bch3121dec$1295 Def00008E
+S A$bch3121dec$1286 Def000084
+S A$bch3121dec$1277 Def000079
+S A$bch3121dec$1268 Def000070
+S A$bch3121dec$1259 Def000064
+S A$bch3121dec$1196 Def000014
+S A$bch3121dec$1187 Def000003
+S A$bch3121dec$1296 Def000090
+S A$bch3121dec$1278 Def00007A
+S A$bch3121dec$1269 Def000071
+S A$bch3121dec$1197 Def000015
+S A$bch3121dec$1188 Def000006
+S A$bch3121dec$1297 Def000092
+S A$bch3121dec$1279 Def00007B
+S A$bch3121dec$1198 Def000016
+S A$bch3121dec$1189 Def000009
+S C$bch3121dec.c$10$1$33 Def00002C
+S A$bch3121dec$1298 Def000094
+S A$bch3121dec$1289 Def000085
+S A$bch3121dec$1199 Def000018
+S C$bch3121dec.c$11$1$33 Def000034
+S A$bch3121dec$1299 Def000096
+S C$bch3121dec.c$12$1$33 Def000049
+S C$bch3121dec.c$13$1$33 Def00004D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 85 82 00 00 00 85 83 00 00 01 85 F0
+R 00 00 00 16 F1 21 05 00 05 F1 21 0A 00 05
+T 00 00 08 00 00 02 F5 00 00 03 12
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 0C 00 00 AA 82 AB 83 8A 00 EB C8 25 E0 C8
+R 00 00 00 16 02 03 01 64
+T 00 00 19 33 F9 E8 24 00 00 00 F5 82 E9 34
+R 00 00 00 16 F1 03 07 01 A1
+T 00 00 22 00 00 00 F5 83 E4 93 FA A3 E4 93 FB 8A
+R 00 00 00 16 F1 83 03 01 A1
+T 00 00 2D 00 8B 01 E9 30 E7 15 74 01 45 00 00 00
+R 00 00 00 16 F1 21 0D 00 05
+T 00 00 38 F8 A9 00 00 01 AE 00 00 02 AF
+R 00 00 00 16 F1 21 05 00 05 F1 21 09 00 05
+T 00 00 3E 00 00 03 88 82 89 83 8E F0 EF 02 00 C7
+R 00 00 00 16 F1 21 03 00 05 00 0E 00 16
+T 00 00 49
+R 00 00 00 16
+T 00 00 49 74 1F 5A FE 8E F0 05 F0 79 01 7C 00 7D
+R 00 00 00 16
+T 00 00 56 00 7F 00 80 0C
+R 00 00 00 16
+T 00 00 5B
+R 00 00 00 16
+T 00 00 5B E9 29 F9 EC 33 FC ED 33 FD EF 33 FF
+R 00 00 00 16
+T 00 00 67
+R 00 00 00 16
+T 00 00 67 D5 F0 F1 E9 62 00 00 00 EC 62 00 00 01
+R 00 00 00 16 F1 21 08 00 05 F1 21 0D 00 05
+T 00 00 70 ED 62 00 00 02 EF 62 00 00 03 EB C4 03
+R 00 00 00 16 F1 21 05 00 05 F1 21 0A 00 05
+T 00 00 79 CA C4 03 54 07 6A CA 54 07 CA 6A CA 53
+R 00 00 00 16
+T 00 00 86 02 1F 7B 00 8A 06 8E F0 05 F0 7E 01 7F
+R 00 00 00 16
+T 00 00 93 00 7D 00 7C 00 80 0C
+R 00 00 00 16
+T 00 00 9A
+R 00 00 00 16
+T 00 00 9A EE 2E FE EF 33 FF ED 33 FD EC 33 FC
+R 00 00 00 16
+T 00 00 A6
+R 00 00 00 16
+T 00 00 A6 D5 F0 F1 EE 62 00 00 00 EF 62 00 00 01
+R 00 00 00 16 F1 21 08 00 05 F1 21 0D 00 05
+T 00 00 AF ED 62 00 00 02 EC 62 00 00 03 74 FE 55
+R 00 00 00 16 F1 21 05 00 05 F1 21 0A 00 05
+T 00 00 B8 00 00 00 FC AD 00 00 01 AE
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 BD 00 00 02 AF 00 00 03 8C 82 8D 83 8E F0
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 C6 EF
+R 00 00 00 16
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 22
+R 00 00 00 16
+
+
+M:bch3121dec
+F:G$bch3121_decode$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lbch3121dec.bch3121_decode$cw$1$32({4}SL:U),E,0,0
+S:Lbch3121dec.bch3121_decode$x$1$33({2}SI:U),R,0,0,[r2,r3]
+S:Lbch3121dec.bch3121_decode$p$1$33({1}SC:U),R,0,0,[r6]
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+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121decp
+
+;!FILE libmf/bch3121decp.asm
+XH3
+H 1A areas 308 global symbols
+M bch3121decp
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S _bch3121_decode Ref000000
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
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+S G$ADCCH3VAL0$0$0 Def007026
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+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
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+S _WTEVTC0 Def0000FC
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+S G$OSCREADY$0$0 Def007052
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+S G$PORTC_3$0$0 Def000093
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+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
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+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
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+S G$PORTC_4$0$0 Def000094
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+S G$E2IE_7$0$0 Def0000A7
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+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
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+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
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+S G$IE_2$0$0 Def0000AA
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+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
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+S G$PALTRADIO$0$0 Def007046
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+S _hweight32 Ref000000
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+S _ADCCH0VAL0 Def007020
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+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
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+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
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+S G$SP$0$0 Def000081
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+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
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+S _PORTB_1 Def000089
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+S _ADCCH2VAL0 Def007024
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+S _PORTB_2 Def00008A
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+S _ACC_3 Def0000E3
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+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
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+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
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+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
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+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
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+A XSEG size 0 flags 40 addr 0
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+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
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+S C$bch3121decp.c$6$1$33 Def000007
+S C$bch3121decp.c$7$1$33 Def00000B
+S G$bch3121_decode_parity$0$0 Def000000
+S C$bch3121decp.c$8$1$33 Def000020
+S C$bch3121decp.c$9$1$33 Def000024
+S C$bch3121decp.c$4$0$0 Def000000
+S _bch3121_decode_parity Def000000
+S XG$bch3121_decode_parity$0$0 Def000054
+S A$bch3121decp$1200 Def00001B
+S A$bch3121decp$1210 Def000026
+S A$bch3121decp$1201 Def00001D
+S A$bch3121decp$1220 Def000033
+S A$bch3121decp$1211 Def000028
+S A$bch3121decp$1202 Def00001E
+S A$bch3121decp$1230 Def000042
+S A$bch3121decp$1221 Def000034
+S A$bch3121decp$1212 Def00002A
+S A$bch3121decp$1240 Def00004F
+S A$bch3121decp$1231 Def000044
+S A$bch3121decp$1222 Def000037
+S A$bch3121decp$1213 Def00002B
+S A$bch3121decp$1241 Def000051
+S A$bch3121decp$1232 Def000045
+S A$bch3121decp$1223 Def000039
+S A$bch3121decp$1205 Def000020
+S A$bch3121decp$1242 Def000053
+S A$bch3121decp$1233 Def000047
+S A$bch3121decp$1224 Def00003B
+S A$bch3121decp$1206 Def000021
+S A$bch3121decp$1234 Def000048
+S A$bch3121decp$1225 Def00003D
+S A$bch3121decp$1235 Def00004A
+S A$bch3121decp$1226 Def00003E
+S A$bch3121decp$1217 Def00002D
+S A$bch3121decp$1181 Def000000
+S A$bch3121decp$1236 Def00004B
+S A$bch3121decp$1227 Def00003F
+S A$bch3121decp$1218 Def00002F
+S A$bch3121decp$1209 Def000024
+S A$bch3121decp$1182 Def000002
+S A$bch3121decp$1246 Def000054
+S A$bch3121decp$1228 Def000040
+S A$bch3121decp$1219 Def000031
+S A$bch3121decp$1192 Def00000B
+S A$bch3121decp$1183 Def000004
+S A$bch3121decp$1229 Def000041
+S A$bch3121decp$1193 Def00000D
+S A$bch3121decp$1184 Def000006
+S A$bch3121decp$1239 Def00004D
+S A$bch3121decp$1194 Def00000F
+S A$bch3121decp$1195 Def000011
+S A$bch3121decp$1196 Def000012
+S A$bch3121decp$1187 Def000007
+S A$bch3121decp$1197 Def000014
+S A$bch3121decp$1188 Def000009
+S A$bch3121decp$1198 Def000017
+S A$bch3121decp$1189 Def00000A
+S C$bch3121decp.c$10$1$33 Def00002D
+S A$bch3121decp$1199 Def000019
+S C$bch3121decp.c$11$1$33 Def00004D
+S C$bch3121decp.c$12$1$33 Def000054
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
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+R 00 00 00 16
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+T 00 00 3A 01 62 00 E4 F9 FA FB E8 42 04 E9 42 05
+R 00 00 00 16
+T 00 00 47 EA 42 06 EB 42 07 8C 82 8D 83 8E F0 EF
+R 00 00 00 16
+T 00 00 54
+R 00 00 00 16
+T 00 00 54 22
+R 00 00 00 16
+
+
+M:bch3121decp
+F:G$bch3121_decode_parity$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lbch3121decp.bch3121_decode_parity$cw$1$32({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Lbch3121decp.bch3121_decode_parity$p$1$33({1}SC:U),R,0,0,[r0]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121enc
+
+;!FILE libmf/bch3121enc.asm
+XH3
+H 1A areas 2FE global symbols
+M bch3121enc
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4A flags 20 addr 0
+S A$bch3121enc$1219 Def00003D
+S A$bch3121enc$1192 Def000011
+S A$bch3121enc$1193 Def000013
+S A$bch3121enc$1184 Def000005
+S A$bch3121enc$1194 Def000015
+S A$bch3121enc$1185 Def000007
+S A$bch3121enc$1195 Def000017
+S A$bch3121enc$1196 Def000019
+S A$bch3121enc$1197 Def00001C
+S A$bch3121enc$1188 Def00000A
+S A$bch3121enc$1179 Def000000
+S A$bch3121enc$1198 Def00001E
+S A$bch3121enc$1189 Def00000C
+S A$bch3121enc$1199 Def000020
+S G$bch3121_encode$0$0 Def000000
+S C$bch3121enc.c$6$1$33 Def000005
+S C$bch3121enc.c$7$1$33 Def00000A
+S C$bch3121enc.c$8$1$33 Def000042
+S C$bch3121enc.c$9$1$33 Def000049
+S _bch3121_encode Def000000
+S C$bch3121enc.c$4$0$0 Def000000
+S XG$bch3121_encode$0$0 Def000049
+S A$bch3121enc$1200 Def000022
+S A$bch3121enc$1210 Def000031
+S A$bch3121enc$1201 Def000024
+S A$bch3121enc$1220 Def00003F
+S A$bch3121enc$1211 Def000033
+S A$bch3121enc$1202 Def000026
+S A$bch3121enc$1230 Def000049
+S A$bch3121enc$1221 Def000040
+S A$bch3121enc$1212 Def000034
+S A$bch3121enc$1203 Def000028
+S A$bch3121enc$1213 Def000035
+S A$bch3121enc$1204 Def000029
+S A$bch3121enc$1214 Def000036
+S A$bch3121enc$1205 Def00002A
+S A$bch3121enc$1224 Def000042
+S A$bch3121enc$1215 Def000037
+S A$bch3121enc$1206 Def00002C
+S A$bch3121enc$1225 Def000044
+S A$bch3121enc$1216 Def000039
+S A$bch3121enc$1207 Def00002D
+S A$bch3121enc$1180 Def000002
+S A$bch3121enc$1226 Def000046
+S A$bch3121enc$1217 Def00003A
+S A$bch3121enc$1208 Def00002E
+S A$bch3121enc$1190 Def00000E
+S A$bch3121enc$1181 Def000004
+S A$bch3121enc$1227 Def000048
+S A$bch3121enc$1218 Def00003C
+S A$bch3121enc$1209 Def00002F
+S A$bch3121enc$1191 Def000010
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AD 83 AE F0 FF 7C 00 53 05 F8 8C 82 8D
+R 00 00 00 16
+T 00 00 0D 83 8E F0 EF C0 07 C0 06 C0 05 C0 04 12
+R 00 00 00 16
+T 00 00 1A 00 00 AA 82 AB 83 D0 04 D0 05 D0 06 D0
+R 00 00 00 16 02 03 01 64
+T 00 00 27 07 EB CA 25 E0 CA 33 FB 8A 00 8B 01 E4
+R 00 00 00 16
+T 00 00 34 FA FB E8 42 04 E9 42 05 EA 42 06 EB 42
+R 00 00 00 16
+T 00 00 41 07 8C 82 8D 83 8E F0 EF 22
+R 00 00 00 16
+
+
+M:bch3121enc
+F:G$bch3121_encode$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lbch3121enc.bch3121_encode$cw$1$32({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
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+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
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+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
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+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
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+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121encp
+
+;!FILE libmf/bch3121encp.asm
+XH3
+H 1A areas 314 global symbols
+M bch3121encp
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _hweight32 Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S C$bch3121encp.c$6$1$33 Def000005
+S C$bch3121encp.c$7$1$33 Def00000A
+S G$bch3121_encode_parity$0$0 Def000000
+S C$bch3121encp.c$8$1$33 Def000042
+S C$bch3121encp.c$9$1$33 Def000061
+S C$bch3121encp.c$4$0$0 Def000000
+S _bch3121_encode_parity Def000000
+S XG$bch3121_encode_parity$0$0 Def000068
+S A$bch3121encp$1200 Def000020
+S A$bch3121encp$1210 Def00002F
+S A$bch3121encp$1201 Def000022
+S A$bch3121encp$1220 Def00003D
+S A$bch3121encp$1211 Def000031
+S A$bch3121encp$1202 Def000024
+S A$bch3121encp$1230 Def00004C
+S A$bch3121encp$1221 Def00003F
+S A$bch3121encp$1212 Def000033
+S A$bch3121encp$1203 Def000026
+S A$bch3121encp$1240 Def000059
+S A$bch3121encp$1231 Def00004E
+S A$bch3121encp$1222 Def000040
+S A$bch3121encp$1213 Def000034
+S A$bch3121encp$1204 Def000028
+S A$bch3121encp$1250 Def000067
+S A$bch3121encp$1241 Def00005B
+S A$bch3121encp$1232 Def000050
+S A$bch3121encp$1214 Def000035
+S A$bch3121encp$1205 Def000029
+S A$bch3121encp$1242 Def00005C
+S A$bch3121encp$1233 Def000051
+S A$bch3121encp$1215 Def000036
+S A$bch3121encp$1206 Def00002A
+S A$bch3121encp$1243 Def00005E
+S A$bch3121encp$1234 Def000052
+S A$bch3121encp$1225 Def000042
+S A$bch3121encp$1216 Def000037
+S A$bch3121encp$1207 Def00002C
+S A$bch3121encp$1180 Def000000
+S A$bch3121encp$1253 Def000068
+S A$bch3121encp$1244 Def00005F
+S A$bch3121encp$1235 Def000053
+S A$bch3121encp$1226 Def000044
+S A$bch3121encp$1217 Def000039
+S A$bch3121encp$1208 Def00002D
+S A$bch3121encp$1190 Def00000C
+S A$bch3121encp$1181 Def000002
+S A$bch3121encp$1236 Def000054
+S A$bch3121encp$1227 Def000046
+S A$bch3121encp$1218 Def00003A
+S A$bch3121encp$1209 Def00002E
+S A$bch3121encp$1191 Def00000E
+S A$bch3121encp$1182 Def000004
+S A$bch3121encp$1237 Def000055
+S A$bch3121encp$1228 Def000048
+S A$bch3121encp$1219 Def00003C
+S A$bch3121encp$1192 Def000010
+S A$bch3121encp$1247 Def000061
+S A$bch3121encp$1238 Def000056
+S A$bch3121encp$1229 Def000049
+S A$bch3121encp$1193 Def000011
+S A$bch3121encp$1248 Def000063
+S A$bch3121encp$1239 Def000058
+S A$bch3121encp$1194 Def000013
+S A$bch3121encp$1185 Def000005
+S A$bch3121encp$1249 Def000065
+S A$bch3121encp$1195 Def000015
+S A$bch3121encp$1186 Def000007
+S A$bch3121encp$1196 Def000017
+S A$bch3121encp$1197 Def000019
+S A$bch3121encp$1198 Def00001C
+S A$bch3121encp$1189 Def00000A
+S C$bch3121encp.c$10$1$33 Def000068
+S A$bch3121encp$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AD 83 AE F0 FF 7C 00 53 05 F8 8C 82 8D
+R 00 00 00 16
+T 00 00 0D 83 8E F0 EF C0 07 C0 06 C0 05 C0 04 12
+R 00 00 00 16
+T 00 00 1A 00 00 AA 82 AB 83 D0 04 D0 05 D0 06 D0
+R 00 00 00 16 02 03 01 64
+T 00 00 27 07 EB CA 25 E0 CA 33 FB 8A 00 8B 01 E4
+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 41 07 8C 82 8D 83 8E F0 EF 12 00 00 E5 82
+R 00 00 00 16 02 0C 02 20
+T 00 00 4E 54 01 F8 E4 F9 FA FB E8 42 04 E9 42 05
+R 00 00 00 16
+T 00 00 5B EA 42 06 EB 42 07 8C 82 8D 83 8E F0 EF
+R 00 00 00 16
+T 00 00 68 22
+R 00 00 00 16
+
+
+M:bch3121encp
+F:G$bch3121_encode_parity$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lbch3121encp.bch3121_encode_parity$cw$1$32({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
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+S:G$U1SHREG$0$0({1}SC:U),I,0,0
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+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
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+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_3$0$0({1}SX:U),J,0,0
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+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
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+S:G$PINC_3$0$0({1}SX:U),J,0,0
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+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
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+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
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+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
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+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
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+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121stab
+
+XH3
+H 1A areas 3 global symbols
+M bch3121stab
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 800 flags 20 addr 0
+S G$bch3121_syndrometable$0$0 Def000000
+S _bch3121_syndrometable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 01 00 02 00 41 00 03 00 61 00 62
+R 00 00 00 17
+T 00 00 0D 00 00 80 04 00 81 00 82 00 00 80 83 00
+R 00 00 00 17
+T 00 00 1A 94 03 00 80 76 03 05 00 A1 00 A2 00 F4
+R 00 00 00 17
+T 00 00 27 02 A3 00 00 80 00 80 00 80 A4 00 2C 03
+R 00 00 00 17
+T 00 00 34 B5 03 00 80 00 80 00 80 97 03 AB 01 06
+R 00 00 00 17
+T 00 00 41 00 C1 00 C2 00 00 80 C3 00 00 80 15 03
+R 00 00 00 17
+T 00 00 4E 2E 03 C4 00 00 80 00 80 00 80 00 80 4B
+R 00 00 00 17
+T 00 00 5B 03 00 80 00 80 C5 00 00 80 4D 03 00 80
+R 00 00 00 17
+T 00 00 68 D6 03 00 80 00 80 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 00 75 80 DB 03 B8 03 00 80 CC 01 00 80 07 00
+R 00 00 00 17
+T 00 00 82 E1 00 E2 00 79 03 E3 00 00 80 00 80 00
+R 00 00 00 17
+T 00 00 8F 80 E4 00 00 80 00 80 00 80 36 03 00 80
+R 00 00 00 17
+T 00 00 9C 4F 03 00 80 E5 00 08 03 00 80 6A 02 00
+R 00 00 00 17
+T 00 00 A9 80 CC 02 00 80 00 80 00 80 00 80 6C 03
+R 00 00 00 17
+T 00 00 B6 00 80 00 80 00 80 00 80 CE 03 E6 00 CC
+R 00 00 00 17
+T 00 00 C3 03 00 80 EB 01 6E 03 00 80 00 80 51 02
+R 00 00 00 17
+T 00 00 D0 F7 03 00 80 00 80 CE 02 00 80 A8 03 00
+R 00 00 00 17
+T 00 00 DD 80 00 80 00 80 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 00 EA 00 80 FC 03 A8 02 D9 03 00 80 00 80 F4
+R 00 00 00 17
+T 00 00 F7 03 ED 01 09 02 00 80 00 80 08 00 01 01
+R 00 00 00 17
+T 00 01 04 02 01 00 80 03 01 C9 01 9A 03 00 80 04
+R 00 00 00 17
+T 00 01 11 01 00 80 00 80 54 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 01 1E 00 80 05 01 07 03 00 80 D0 02 00 80 00
+R 00 00 00 17
+T 00 01 2B 80 00 80 00 80 57 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 01 38 70 03 4A 02 00 80 00 80 06 01 00 80 29
+R 00 00 00 17
+T 00 01 45 03 00 80 00 80 00 80 8B 02 D0 03 00 80
+R 00 00 00 17
+T 00 01 52 71 02 ED 02 8B 03 00 80 A7 03 00 80 00
+R 00 00 00 17
+T 00 01 5F 80 00 80 00 80 00 80 00 80 8D 03 EB 02
+R 00 00 00 17
+T 00 01 6C 00 80 A7 02 00 80 8D 02 00 80 89 01 00
+R 00 00 00 17
+T 00 01 79 80 00 80 EF 03 00 80 07 01 05 03 ED 03
+R 00 00 00 17
+T 00 01 86 00 80 00 80 8F 02 0C 02 00 80 8F 03 00
+R 00 00 00 17
+T 00 01 93 80 00 80 00 80 00 80 A6 03 72 02 00 80
+R 00 00 00 17
+T 00 01 A0 01 03 18 00 00 80 02 03 00 80 03 03 EF
+R 00 00 00 17
+T 00 01 AD 02 A6 02 00 80 04 03 C9 03 00 80 00 80
+R 00 00 00 17
+T 00 01 BA EB 03 00 80 30 03 00 80 69 03 00 80 00
+R 00 00 00 17
+T 00 01 C7 80 00 80 A4 03 00 80 A5 02 00 80 A3 03
+R 00 00 00 17
+T 00 01 D4 00 80 00 80 A1 03 1D 00 C9 02 A2 03 FA
+R 00 00 00 17
+T 00 01 E1 03 06 03 00 80 A3 02 00 80 A2 02 A1 02
+R 00 00 00 17
+T 00 01 EE 15 00 0E 02 00 80 2A 02 00 80 00 80 A5
+R 00 00 00 17
+T 00 01 FB 03 00 80 A4 02 09 00 21 01 22 01 B6 03
+R 00 00 00 17
+T 00 02 08 23 01 C8 01 00 80 00 80 24 01 00 80 EA
+R 00 00 00 17
+T 00 02 15 01 D8 03 BB 03 00 80 00 80 00 80 25 01
+R 00 00 00 17
+T 00 02 22 00 80 00 80 00 80 00 80 00 80 75 03 53
+R 00 00 00 17
+T 00 02 2F 03 00 80 D5 02 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 02 3C 00 80 00 80 26 01 00 80 28 03 00 80 00
+R 00 00 00 17
+T 00 02 49 80 6D 02 F1 02 00 80 00 80 F2 03 00 80
+R 00 00 00 17
+T 00 02 56 00 80 00 80 D5 03 00 80 00 80 78 03 00
+R 00 00 00 17
+T 00 02 63 80 00 80 00 80 00 80 91 02 00 80 DD 03
+R 00 00 00 17
+T 00 02 70 91 03 00 80 6B 02 88 01 00 80 07 02 00
+R 00 00 00 17
+T 00 02 7D 80 16 03 27 01 F2 02 00 80 00 80 4A 03
+R 00 00 00 17
+T 00 02 8A 00 80 00 80 00 80 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 02 97 80 AC 02 00 80 F1 03 B9 03 00 80 00 80
+R 00 00 00 17
+T 00 02 A4 92 02 00 80 0E 03 35 03 AC 03 00 80 00
+R 00 00 00 17
+T 00 02 B1 80 6F 02 C8 03 00 80 00 80 06 02 00 80
+R 00 00 00 17
+T 00 02 BE 92 03 00 80 68 03 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 02 CB 80 00 80 00 80 AE 03 6A 01 0C 03 00 80
+R 00 00 00 17
+T 00 02 D8 00 80 05 02 C8 02 00 80 00 80 00 80 AE
+R 00 00 00 17
+T 00 02 E5 02 38 03 00 80 04 02 AA 01 00 80 00 80
+R 00 00 00 17
+T 00 02 F2 03 02 00 80 00 80 01 02 10 00 00 80 02
+R 00 00 00 17
+T 00 02 FF 02 28 01 C3 01 26 03 00 80 C1 01 0E 00
+R 00 00 00 17
+T 00 03 0C 00 80 C2 01 00 80 00 80 B0 02 00 80 2D
+R 00 00 00 17
+T 00 03 19 02 C4 01 00 80 F3 02 B0 03 93 03 00 80
+R 00 00 00 17
+T 00 03 26 2B 02 00 80 C5 01 00 80 4F 02 00 80 00
+R 00 00 00 17
+T 00 03 33 80 C7 03 86 01 93 02 00 80 00 80 00 80
+R 00 00 00 17
+T 00 03 40 22 03 67 03 19 00 21 03 00 80 C6 01 23
+R 00 00 00 17
+T 00 03 4D 03 00 80 00 80 00 80 24 03 85 01 10 03
+R 00 00 00 17
+T 00 03 5A 00 80 C7 02 00 80 00 80 00 80 25 03 84
+R 00 00 00 17
+T 00 03 67 01 EA 03 00 80 00 80 00 80 00 80 82 01
+R 00 00 00 17
+T 00 03 74 81 01 0C 00 00 80 00 80 51 03 83 01 00
+R 00 00 00 17
+T 00 03 81 80 66 03 8A 03 00 80 00 80 C7 01 00 80
+R 00 00 00 17
+T 00 03 8E 00 80 00 80 00 80 C5 03 00 80 00 80 00
+R 00 00 00 17
+T 00 03 9B 80 C6 02 8A 02 00 80 09 03 C4 03 00 80
+R 00 00 00 17
+T 00 03 A8 00 80 00 80 00 80 00 80 C2 03 52 03 1E
+R 00 00 00 17
+T 00 03 B5 00 C1 03 EA 02 00 80 C3 03 00 80 61 03
+R 00 00 00 17
+T 00 03 C2 1B 00 27 03 62 03 00 80 63 03 C4 02 F3
+R 00 00 00 17
+T 00 03 CF 03 00 80 64 03 C3 02 4D 02 C2 02 A9 03
+R 00 00 00 17
+T 00 03 DC 16 00 C1 02 2F 02 65 03 00 80 00 80 4B
+R 00 00 00 17
+T 00 03 E9 02 00 80 00 80 A9 02 00 80 00 80 C6 03
+R 00 00 00 17
+T 00 03 F6 87 01 00 80 08 02 C5 02 00 80 0A 00 41
+R 00 00 00 17
+T 00 04 03 01 42 01 00 80 43 01 00 80 D7 03 00 80
+R 00 00 00 17
+T 00 04 10 44 01 00 80 E9 01 0D 02 00 80 B1 02 00
+R 00 00 00 17
+T 00 04 1D 80 EC 03 45 01 00 80 00 80 67 02 0B 02
+R 00 00 00 17
+T 00 04 2A D4 03 F9 03 B1 03 DC 03 00 80 00 80 00
+R 00 00 00 17
+T 00 04 37 80 00 80 48 02 00 80 00 80 46 01 D4 02
+R 00 00 00 17
+T 00 04 44 00 80 9B 03 00 80 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 04 51 80 00 80 00 80 11 03 96 03 00 80 74 03
+R 00 00 00 17
+T 00 04 5E 00 80 00 80 EE 03 F6 02 00 80 00 80 00
+R 00 00 00 17
+T 00 04 6B 80 00 80 00 80 00 80 50 03 00 80 00 80
+R 00 00 00 17
+T 00 04 78 00 80 77 03 00 80 00 80 47 01 00 80 00
+R 00 00 00 17
+T 00 04 85 80 65 02 49 03 00 80 00 80 8E 03 00 80
+R 00 00 00 17
+T 00 04 92 00 80 8E 02 00 80 12 03 00 80 00 80 00
+R 00 00 00 17
+T 00 04 9F 80 00 80 62 02 61 02 13 00 00 80 FB 03
+R 00 00 00 17
+T 00 04 AC 00 80 63 02 00 80 EE 02 F6 03 64 02 00
+R 00 00 00 17
+T 00 04 B9 80 00 80 00 80 00 80 99 03 00 80 00 80
+R 00 00 00 17
+T 00 04 C6 00 80 00 80 00 80 00 80 EC 02 00 80 69
+R 00 00 00 17
+T 00 04 D3 01 B2 02 00 80 00 80 34 03 FE 03 00 80
+R 00 00 00 17
+T 00 04 E0 B2 03 00 80 00 80 66 02 8C 02 00 80 A9
+R 00 00 00 17
+T 00 04 ED 01 0F 02 00 80 8C 03 28 02 00 80 00 80
+R 00 00 00 17
+T 00 04 FA 00 80 37 03 00 80 48 01 00 80 13 03 00
+R 00 00 00 17
+T 00 05 07 80 00 80 00 80 00 80 CB 02 6B 03 00 80
+R 00 00 00 17
+T 00 05 14 00 80 00 80 00 80 45 02 00 80 EE 01 00
+R 00 00 00 17
+T 00 05 21 80 00 80 00 80 00 80 00 80 44 02 00 80
+R 00 00 00 17
+T 00 05 2E 6D 03 CD 02 43 02 00 80 00 80 41 02 12
+R 00 00 00 17
+T 00 05 3B 00 DA 03 42 02 00 80 F0 02 00 80 00 80
+R 00 00 00 17
+T 00 05 48 B3 02 7A 03 00 80 00 80 2F 03 00 80 56
+R 00 00 00 17
+T 00 05 55 03 00 80 CD 03 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 62 EC 01 90 02 CB 03 E9 03 00 80 00 80 00
+R 00 00 00 17
+T 00 05 6F 80 00 80 00 80 27 02 00 80 00 80 46 02
+R 00 00 00 17
+T 00 05 7C B3 03 90 03 00 80 4E 03 89 03 00 80 00
+R 00 00 00 17
+T 00 05 89 80 00 80 00 80 00 80 00 80 F0 03 00 80
+R 00 00 00 17
+T 00 05 96 2B 03 00 80 AC 01 00 80 89 02 CF 03 0A
+R 00 00 00 17
+T 00 05 A3 03 8B 01 68 02 2D 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 B0 00 80 00 80 26 02 00 80 E9 02 47 02 00
+R 00 00 00 17
+T 00 05 BD 80 00 80 00 80 00 80 00 80 00 80 CF 02
+R 00 00 00 17
+T 00 05 CA 00 80 59 03 00 80 00 80 00 80 25 02 6F
+R 00 00 00 17
+T 00 05 D7 03 CB 01 AA 03 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 E4 24 02 CD 01 00 80 00 80 00 80 AA 02 22
+R 00 00 00 17
+T 00 05 F1 02 00 80 11 00 21 02 00 80 00 80 23 02
+R 00 00 00 17
+T 00 05 FE 4C 03 49 01 00 80 E4 01 00 80 47 03 00
+R 00 00 00 17
+T 00 06 0B 80 00 80 00 80 E2 01 00 80 0F 00 E1 01
+R 00 00 00 17
+T 00 06 18 00 80 17 03 E3 01 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 06 25 80 98 03 D1 02 00 80 00 80 00 80 4E 02
+R 00 00 00 17
+T 00 06 32 00 80 E5 01 71 03 00 80 00 80 14 03 00
+R 00 00 00 17
+T 00 06 3F 80 D1 03 00 80 B4 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 06 4C 4C 02 00 80 00 80 67 01 E6 01 F5 02 00
+R 00 00 00 17
+T 00 06 59 80 00 80 70 02 BC 03 00 80 B7 03 00 80
+R 00 00 00 17
+T 00 06 66 00 80 E8 03 95 03 A7 01 00 80 B4 02 00
+R 00 00 00 17
+T 00 06 73 80 00 80 00 80 00 80 00 80 00 80 32 03
+R 00 00 00 17
+T 00 06 80 43 03 2C 02 88 03 F5 03 1A 00 41 03 42
+R 00 00 00 17
+T 00 06 8D 03 D2 03 00 80 66 01 E7 01 00 80 44 03
+R 00 00 00 17
+T 00 06 9A 00 80 00 80 88 02 00 80 00 80 00 80 69
+R 00 00 00 17
+T 00 06 A7 02 45 03 00 80 A6 01 00 80 31 03 FD 03
+R 00 00 00 17
+T 00 06 B4 00 80 00 80 E8 02 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 06 C1 80 64 01 00 80 00 80 46 03 F8 03 A5 01
+R 00 00 00 17
+T 00 06 CE 00 80 61 01 0B 00 00 80 62 01 00 80 63
+R 00 00 00 17
+T 00 06 DB 01 00 80 00 80 00 80 00 80 A3 01 D2 02
+R 00 00 00 17
+T 00 06 E8 A2 01 00 80 0D 00 A1 01 00 80 65 01 00
+R 00 00 00 17
+T 00 06 F5 80 00 80 72 03 0A 02 A4 01 2E 02 00 80
+R 00 00 00 17
+T 00 07 02 AD 02 87 03 00 80 AB 03 CA 01 00 80 30
+R 00 00 00 17
+T 00 07 0F 02 00 80 D3 03 E8 01 00 80 00 80 00 80
+R 00 00 00 17
+T 00 07 1C 00 80 87 02 00 80 00 80 00 80 00 80 E6
+R 00 00 00 17
+T 00 07 29 03 58 03 00 80 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 07 36 AD 03 E7 02 49 02 AB 02 00 80 00 80 00
+R 00 00 00 17
+T 00 07 43 80 2A 03 00 80 E5 03 00 80 00 80 0D 03
+R 00 00 00 17
+T 00 07 50 00 80 BA 03 00 80 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 07 5D 80 00 80 E3 03 00 80 73 03 55 03 1F 00
+R 00 00 00 17
+T 00 07 6A E1 03 E2 03 00 80 0B 03 00 80 00 80 8A
+R 00 00 00 17
+T 00 07 77 01 E4 03 D3 02 00 80 00 80 82 03 00 80
+R 00 00 00 17
+T 00 07 84 1C 00 81 03 48 03 00 80 83 03 84 02 00
+R 00 00 00 17
+T 00 07 91 80 00 80 84 03 83 02 E5 02 82 02 81 02
+R 00 00 00 17
+T 00 07 9E 14 00 00 80 00 80 85 03 00 80 E4 02 00
+R 00 00 00 17
+T 00 07 AB 80 6E 02 00 80 E3 02 00 80 CA 03 0F 03
+R 00 00 00 17
+T 00 07 B8 17 00 E1 02 E2 02 85 02 50 02 6A 03 86
+R 00 00 00 17
+T 00 07 C5 03 00 80 00 80 00 80 00 80 AF 03 6C 02
+R 00 00 00 17
+T 00 07 D2 68 01 00 80 00 80 00 80 00 80 CA 02 86
+R 00 00 00 17
+T 00 07 DF 02 00 80 33 03 00 80 00 80 E7 03 00 80
+R 00 00 00 17
+T 00 07 EC A8 01 00 80 00 80 00 80 29 02 00 80 E6
+R 00 00 00 17
+T 00 07 F9 02 AF 02 00 80 00 80
+R 00 00 00 17
+
+
+M:bch3121stab
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121syn
+
+;!FILE libmf/bch3121syn.asm
+XH3
+H 1B areas 301 global symbols
+M bch3121syn
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3D flags 20 addr 0
+S C$bch3121syn.c$7$1$33 Def000009
+S C$bch3121syn.c$8$2$34 Def000009
+S C$bch3121syn.c$9$2$34 Def00000D
+S C$bch3121syn.c$4$0$0 Def000000
+S C$bch3121syn.c$6$1$0 Def000007
+S G$bch3121_syndrome$0$0 Def000000
+S A$bch3121syn$1210 Def00001C
+S A$bch3121syn$1201 Def000013
+S A$bch3121syn$1211 Def00001D
+S A$bch3121syn$1202 Def000014
+S A$bch3121syn$1230 Def000030
+S A$bch3121syn$1212 Def00001E
+S A$bch3121syn$1203 Def000015
+S A$bch3121syn$1231 Def000031
+S A$bch3121syn$1222 Def000025
+S A$bch3121syn$1204 Def000016
+S A$bch3121syn$1241 Def00003C
+S A$bch3121syn$1232 Def000032
+S A$bch3121syn$1223 Def000027
+S A$bch3121syn$1205 Def000017
+S A$bch3121syn$1233 Def000033
+S A$bch3121syn$1224 Def000028
+S A$bch3121syn$1215 Def00001F
+S A$bch3121syn$1206 Def000018
+S A$bch3121syn$1234 Def000034
+S A$bch3121syn$1225 Def00002A
+S A$bch3121syn$1216 Def000020
+S A$bch3121syn$1207 Def000019
+S A$bch3121syn$1180 Def000000
+S A$bch3121syn$1235 Def000035
+S A$bch3121syn$1226 Def00002B
+S A$bch3121syn$1217 Def000021
+S A$bch3121syn$1208 Def00001A
+S A$bch3121syn$1181 Def000002
+S A$bch3121syn$1236 Def000037
+S A$bch3121syn$1227 Def00002C
+S A$bch3121syn$1218 Def000022
+S A$bch3121syn$1209 Def00001B
+S A$bch3121syn$1182 Def000004
+S _bch3121_syndrome Def000000
+S A$bch3121syn$1237 Def000038
+S A$bch3121syn$1228 Def00002D
+S A$bch3121syn$1219 Def000023
+S A$bch3121syn$1192 Def000009
+S A$bch3121syn$1183 Def000006
+S A$bch3121syn$1238 Def00003A
+S A$bch3121syn$1229 Def00002E
+S A$bch3121syn$1193 Def00000A
+S A$bch3121syn$1186 Def000007
+S A$bch3121syn$1196 Def00000D
+S A$bch3121syn$1197 Def000010
+S C$bch3121syn.c$11$1$33 Def00001F
+S C$bch3121syn.c$12$1$33 Def000025
+S C$bch3121syn.c$10$2$34 Def000013
+S C$bch3121syn.c$13$1$33 Def00003C
+S XG$bch3121_syndrome$0$0 Def00003C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 AC 82 AD 83 AE F0 FF 7B 15
+R 00 00 00 17
+T 00 00 09
+R 00 00 00 17
+T 00 00 09 EF 30 E7 06 63 06 20 63 07 ED
+R 00 00 00 17
+T 00 00 13
+R 00 00 00 17
+T 00 00 13 EC 2C FC ED 33 FD EE 33 FE EF 33 FF EB
+R 00 00 00 17
+T 00 00 20 14 FA FB 70 E4 8E 04 EF A2 E7 CC 33 CC
+R 00 00 00 17
+T 00 00 2D 33 A2 E7 CC 33 CC 33 CC 54 03 FD 8C 82
+R 00 00 00 17
+T 00 00 3A 8D 83 22
+R 00 00 00 17
+
+
+M:bch3121syn
+F:G$bch3121_syndrome$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+wrnum16
+
+;!FILE libmf/wrnum16.asm
+XH3
+H 1A areas 48 global symbols
+M wrnum16
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 62 flags 20 addr 0
+S A$wrnum16$160 Def000043
+S A$wrnum16$151 Def00003A
+S A$wrnum16$142 Def00002A
+S A$wrnum16$133 Def00001C
+S A$wrnum16$124 Def000010
+S A$wrnum16$115 Def000000
+S A$wrnum16$161 Def000044
+S A$wrnum16$143 Def00002C
+S A$wrnum16$134 Def00001E
+S A$wrnum16$125 Def000011
+S A$wrnum16$116 Def000002
+S A$wrnum16$180 Def00005B
+S A$wrnum16$171 Def00004E
+S A$wrnum16$162 Def000045
+S A$wrnum16$153 Def00003C
+S A$wrnum16$144 Def00002F
+S A$wrnum16$135 Def000020
+S A$wrnum16$126 Def000012
+S A$wrnum16$117 Def000004
+S A$wrnum16$181 Def00005D
+S A$wrnum16$172 Def00004F
+S A$wrnum16$163 Def000046
+S A$wrnum16$154 Def00003D
+S A$wrnum16$145 Def000031
+S A$wrnum16$136 Def000021
+S A$wrnum16$127 Def000014
+S A$wrnum16$118 Def000006
+S A$wrnum16$182 Def00005F
+S A$wrnum16$173 Def000050
+S A$wrnum16$164 Def000048
+S A$wrnum16$155 Def00003E
+S A$wrnum16$146 Def000033
+S A$wrnum16$137 Def000024
+S A$wrnum16$128 Def000016
+S A$wrnum16$119 Def000008
+S A$wrnum16$183 Def000061
+S A$wrnum16$174 Def000051
+S A$wrnum16$165 Def000049
+S A$wrnum16$156 Def00003F
+S A$wrnum16$147 Def000034
+S A$wrnum16$129 Def000017
+S A$wrnum16$175 Def000053
+S A$wrnum16$166 Def00004A
+S A$wrnum16$157 Def000040
+S A$wrnum16$148 Def000036
+S A$wrnum16$139 Def000026
+S A$wrnum16$176 Def000055
+S A$wrnum16$167 Def00004B
+S A$wrnum16$158 Def000041
+S A$wrnum16$149 Def000038
+S C$wrnum16.c$87$1$30 Def000000
+S C$wrnum16.c$12$0$0 Def000000
+S A$wrnum16$168 Def00004C
+S A$wrnum16$159 Def000042
+S C$wrnum16.c$88$1$30 Def000062
+S A$wrnum16$178 Def000057
+S A$wrnum16$169 Def00004D
+S A$wrnum16$179 Def000059
+S G$libmf_num16_digit$0$0 Def000000
+S _libmf_num16_digit Def000000
+S XG$libmf_num16_digit$0$0 Def000062
+S A$wrnum16$120 Def00000A
+S A$wrnum16$130 Def000018
+S A$wrnum16$121 Def00000C
+S A$wrnum16$140 Def000027
+S A$wrnum16$122 Def00000E
+S A$wrnum16$150 Def000039
+S A$wrnum16$141 Def000028
+S A$wrnum16$132 Def00001A
+S A$wrnum16$123 Def00000F
+A CONST size 20 flags 20 addr 0
+S Fwrnum16$subtbl$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 03 C0 06 C0 07 C0 00 C0 01 E5 81 24
+R 00 00 00 16
+T 00 00 0D F9 F8 E6 F8 E6 24 FA 50 04 E4 F6 80 3D
+R 00 00 00 16
+T 00 00 1A
+R 00 00 00 16
+T 00 00 1A 24 04 40 08 E5 82 F6 90 00 00 80 31
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 C4 03 AF 82 AE 83 90 00 00 25 82 F5 82
+R 00 00 00 16 00 0A 00 17
+T 00 00 33 E4 35 83 F5 83 E4 F6 74 08
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C F9 E4 93 A3 2F FB E4 93 A3 3E 50 06 FE
+R 00 00 00 16
+T 00 00 49 EB FF E6 49 F6
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E E9 C3 13 70 E9 8F 82 8E 83
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 D0 01 D0 00 D0 07 D0 06 D0 03 22
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 B0 FF D8 FF EC FF F6 FF E0 FC 70 FE 38
+R 00 00 00 17
+T 00 00 0D FF 9C FF C0 E0 60 F0 30 F8 18 FC 00 00
+R 00 00 00 17
+T 00 00 1A C0 63 E0 B1 F0 D8
+R 00 00 00 17
+
+
+M:wrnum16
+F:G$libmf_num16_digit$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lwrnum16.libmf_num16_digit$dp$1$29({1}DD,SC:U),B,1,-3
+S:Lwrnum16.libmf_num16_digit$val$1$29({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:Fwrnum16$subtbl$0$0({32}DA16d,SI:U),D,0,0
+
+
+
+
+wrnum32
+
+;!FILE libmf/wrnum32.asm
+XH3
+H 1A areas 62 global symbols
+M wrnum32
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 87 flags 20 addr 0
+S A$wrnum32$207 Def000082
+S A$wrnum32$180 Def00005D
+S A$wrnum32$171 Def000053
+S A$wrnum32$162 Def00004A
+S A$wrnum32$153 Def00003F
+S A$wrnum32$144 Def00002F
+S A$wrnum32$135 Def000020
+S A$wrnum32$126 Def000015
+S A$wrnum32$117 Def000004
+S A$wrnum32$208 Def000084
+S A$wrnum32$190 Def000069
+S A$wrnum32$181 Def00005F
+S A$wrnum32$172 Def000054
+S A$wrnum32$163 Def00004B
+S A$wrnum32$154 Def000040
+S A$wrnum32$127 Def000016
+S A$wrnum32$118 Def000006
+S A$wrnum32$209 Def000086
+S A$wrnum32$182 Def000060
+S A$wrnum32$173 Def000055
+S A$wrnum32$164 Def00004C
+S A$wrnum32$155 Def000042
+S A$wrnum32$146 Def000031
+S A$wrnum32$137 Def000022
+S A$wrnum32$128 Def000017
+S A$wrnum32$119 Def000008
+S A$wrnum32$192 Def00006A
+S A$wrnum32$183 Def000062
+S A$wrnum32$174 Def000056
+S A$wrnum32$165 Def00004D
+S A$wrnum32$156 Def000044
+S A$wrnum32$147 Def000032
+S A$wrnum32$138 Def000024
+S A$wrnum32$129 Def000018
+S A$wrnum32$193 Def00006B
+S A$wrnum32$184 Def000063
+S A$wrnum32$175 Def000057
+S A$wrnum32$166 Def00004E
+S A$wrnum32$157 Def000045
+S A$wrnum32$148 Def000034
+S A$wrnum32$139 Def000026
+S A$wrnum32$194 Def00006C
+S A$wrnum32$185 Def000064
+S A$wrnum32$176 Def000059
+S A$wrnum32$167 Def00004F
+S A$wrnum32$158 Def000046
+S A$wrnum32$149 Def000036
+S A$wrnum32$195 Def00006D
+S A$wrnum32$186 Def000065
+S A$wrnum32$177 Def00005A
+S A$wrnum32$168 Def000050
+S A$wrnum32$196 Def00006F
+S A$wrnum32$187 Def000066
+S A$wrnum32$178 Def00005B
+S A$wrnum32$169 Def000051
+S A$wrnum32$197 Def000071
+S A$wrnum32$188 Def000067
+S A$wrnum32$179 Def00005C
+S A$wrnum32$198 Def000073
+S A$wrnum32$189 Def000068
+S A$wrnum32$199 Def000075
+S C$wrnum32.c$17$0$0 Def000000
+S G$libmf_num32_digit$0$0 Def000000
+S _libmf_num32_digit Def000000
+S C$wrnum32.c$118$1$30 Def000000
+S C$wrnum32.c$119$1$30 Def000087
+S XG$libmf_num32_digit$0$0 Def000087
+S A$wrnum32$201 Def000076
+S A$wrnum32$120 Def00000A
+S A$wrnum32$202 Def000078
+S A$wrnum32$130 Def000019
+S A$wrnum32$121 Def00000C
+S A$wrnum32$203 Def00007A
+S A$wrnum32$140 Def000028
+S A$wrnum32$131 Def00001B
+S A$wrnum32$122 Def00000E
+S A$wrnum32$204 Def00007C
+S A$wrnum32$150 Def000038
+S A$wrnum32$141 Def000029
+S A$wrnum32$132 Def00001D
+S A$wrnum32$123 Def000010
+S A$wrnum32$205 Def00007E
+S A$wrnum32$160 Def000048
+S A$wrnum32$151 Def00003B
+S A$wrnum32$142 Def00002A
+S A$wrnum32$133 Def00001E
+S A$wrnum32$124 Def000011
+S A$wrnum32$115 Def000000
+S A$wrnum32$206 Def000080
+S A$wrnum32$170 Def000052
+S A$wrnum32$161 Def000049
+S A$wrnum32$152 Def00003D
+S A$wrnum32$143 Def00002C
+S A$wrnum32$134 Def00001F
+S A$wrnum32$125 Def000013
+S A$wrnum32$116 Def000002
+A CONST size 90 flags 20 addr 0
+S Fwrnum32$subtbl$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 02 C0 03 C0 04 C0 05 C0 06 C0 07 C0
+R 00 00 00 16
+T 00 00 0D 00 C0 01 FC E5 81 24 F6 F8 E6 F8 E6 24
+R 00 00 00 16
+T 00 00 1A F5 50 05 E4 F6 EC 80 54
+R 00 00 00 16
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 24 09 40 0B E5 82 F6 E4 F5 F0 90 00 00
+R 00 00 00 16
+T 00 00 2F 80 45
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 C4 AF 82 AE 83 AD F0 90 00 00 25 82 F5
+R 00 00 00 16 00 0B 00 17
+T 00 00 3E 82 E4 35 83 F5 83 E4 F6 74 08
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 F9 E4 93 A3 2F FB E4 93 A3 3E FA E4 93
+R 00 00 00 16
+T 00 00 55 A3 3D F5 F0 E4 93 A3 3C 50 0B FC E5 F0
+R 00 00 00 16
+T 00 00 62 FD EA FE EB FF E6 49 F6
+R 00 00 00 16
+T 00 00 6A
+R 00 00 00 16
+T 00 00 6A E9 C3 13 70 D9 8F 82 8E 83 8D F0 EC
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 D0 01 D0 00 D0 07 D0 06 D0 05 D0 04 D0
+R 00 00 00 16
+T 00 00 83 03 D0 02 22
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 B0 FF FF FF D8 FF FF FF EC FF FF FF F6
+R 00 00 00 17
+T 00 00 0D FF FF FF E0 FC FF FF 70 FE FF FF 38 FF
+R 00 00 00 17
+T 00 00 1A FF FF 9C FF FF FF C0 E0 FF FF 60 F0 FF
+R 00 00 00 17
+T 00 00 27 FF 30 F8 FF FF 18 FC FF FF 80 C7 FE FF
+R 00 00 00 17
+T 00 00 34 C0 63 FF FF E0 B1 FF FF F0 D8 FF FF 00
+R 00 00 00 17
+T 00 00 41 CB F3 FF 80 E5 F9 FF C0 F2 FC FF 60 79
+R 00 00 00 17
+T 00 00 4E FE FF 00 EE 85 FF 00 F7 C2 FF 80 7B E1
+R 00 00 00 17
+T 00 00 5B FF C0 BD F0 FF 00 4C 3B FB 00 A6 9D FD
+R 00 00 00 17
+T 00 00 68 00 D3 CE FE 80 69 67 FF 00 F8 50 D0 00
+R 00 00 00 17
+T 00 00 75 7C 28 E8 00 3E 14 F4 00 1F 0A FA 00 00
+R 00 00 00 17
+T 00 00 82 00 00 00 00 00 80 00 6C CA 88 00 36 65
+R 00 00 00 17
+T 00 00 8F C4
+R 00 00 00 17
+
+
+M:wrnum32
+F:G$libmf_num32_digit$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lwrnum32.libmf_num32_digit$dp$1$29({1}DD,SC:U),B,1,-3
+S:Lwrnum32.libmf_num32_digit$val$1$29({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:Fwrnum32$subtbl$0$0({144}DA36d,SL:U),D,0,0
+
+
+
+
+offxosc
+
+;!FILE libmf/offxosc.asm
+XH3
+H 1A areas 316 global symbols
+M offxosc
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 57 flags 20 addr 0
+S A$offxosc$1200 Def000014
+S A$offxosc$1210 Def000021
+S A$offxosc$1201 Def000017
+S A$offxosc$1202 Def000018
+S A$offxosc$1203 Def000019
+S A$offxosc$1240 Def000036
+S A$offxosc$1231 Def00002F
+S A$offxosc$1222 Def000028
+S A$offxosc$1213 Def000022
+S A$offxosc$1204 Def00001B
+S A$offxosc$1241 Def000039
+S A$offxosc$1223 Def00002B
+S A$offxosc$1205 Def00001C
+S A$offxosc$1260 Def000047
+S A$offxosc$1242 Def00003A
+S A$offxosc$1224 Def00002C
+S A$offxosc$1270 Def00004E
+S A$offxosc$1261 Def000048
+S A$offxosc$1243 Def00003B
+S A$offxosc$1234 Def000031
+S A$offxosc$1216 Def000024
+S A$offxosc$1280 Def000056
+S A$offxosc$1271 Def000051
+S A$offxosc$1244 Def00003D
+S A$offxosc$1208 Def00001D
+S A$offxosc$1190 Def00000A
+S A$offxosc$1272 Def000052
+S A$offxosc$1254 Def000041
+S A$offxosc$1245 Def00003E
+S A$offxosc$1227 Def00002D
+S A$offxosc$1209 Def00001F
+S A$offxosc$1191 Def00000D
+S A$offxosc$1264 Def00004A
+S A$offxosc$1237 Def000033
+S A$offxosc$1228 Def00002E
+S A$offxosc$1219 Def000026
+S A$offxosc$1192 Def00000E
+S A$offxosc$1193 Def00000F
+S A$offxosc$1184 Def000000
+S A$offxosc$1275 Def000053
+S A$offxosc$1257 Def000044
+S A$offxosc$1248 Def00003F
+S A$offxosc$1185 Def000003
+S A$offxosc$1276 Def000054
+S A$offxosc$1267 Def00004C
+S A$offxosc$1258 Def000045
+S A$offxosc$1186 Def000004
+S A$offxosc$1259 Def000046
+S A$offxosc$1196 Def000012
+S A$offxosc$1187 Def000005
+S G$turn_off_xosc$0$0 Def000000
+S A$offxosc$1188 Def000008
+S C$offxosc.c$20$1$33 Def00002D
+S C$offxosc.c$30$1$33 Def00004C
+S C$offxosc.c$21$1$33 Def00002F
+S C$offxosc.c$12$1$33 Def000000
+S C$offxosc.c$31$1$33 Def00004E
+S C$offxosc.c$22$1$33 Def000031
+S C$offxosc.c$13$1$33 Def000012
+S C$offxosc.c$32$1$33 Def000053
+S C$offxosc.c$23$1$33 Def000033
+S C$offxosc.c$14$1$33 Def000014
+S C$offxosc.c$33$1$33 Def000056
+S C$offxosc.c$24$1$33 Def000036
+S C$offxosc.c$15$1$33 Def00001D
+S C$offxosc.c$25$1$33 Def00003F
+S C$offxosc.c$16$1$33 Def000022
+S C$offxosc.c$26$1$33 Def000041
+S C$offxosc.c$17$1$33 Def000024
+S C$offxosc.c$18$1$33 Def000026
+S C$offxosc.c$28$1$33 Def000044
+S C$offxosc.c$19$1$33 Def000028
+S C$offxosc.c$29$1$33 Def00004A
+S C$offxosc.c$27$2$34 Def000041
+S _turn_off_xosc Def000000
+S XG$turn_off_xosc$0$0 Def000056
+S C$offxosc.c$8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 7F 00 E0 FF BF 8E 02 80 0A
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 90 7F 01 E0 FF 30 E1 02 80 42
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 90 7F 01 E0 FF 74 02 4F F0 74 80 55 A8
+R 00 00 00 16
+T 00 00 21 FF C2 AF AE 80 AD 89 90 7F 1A E0 FC E4
+R 00 00 00 16
+T 00 00 2E F0 D2 80 C2 81 43 89 03 90 70 50 E0 FB
+R 00 00 00 16
+T 00 00 3B 74 FB 5B F0 7B 06
+R 00 00 00 16
+T 00 00 41
+R 00 00 00 16
+T 00 00 41 63 80 03 EB 14 FA FB 70 F7 8D 89 8E 80
+R 00 00 00 16
+T 00 00 4E 90 7F 1A EC F0 EF 42 A8
+R 00 00 00 16
+T 00 00 56
+R 00 00 00 16
+T 00 00 56 22
+R 00 00 00 16
+
+
+M:offxosc
+F:G$turn_off_xosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Loffxosc.turn_off_xosc$iesave$1$33({1}SC:U),R,0,0,[r7]
+S:Loffxosc.turn_off_xosc$portasave$1$33({1}SC:U),R,0,0,[r6]
+S:Loffxosc.turn_off_xosc$dirasave$1$33({1}SC:U),R,0,0,[r5]
+S:Loffxosc.turn_off_xosc$xtalreadysave$1$33({1}SC:U),R,0,0,[r4]
+S:Loffxosc.turn_off_xosc$i$1$33({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+offlpxosc
+
+;!FILE libmf/offlpxosc.asm
+XH3
+H 1A areas 315 global symbols
+M offlpxosc
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S XG$turn_off_lpxosc$0$0 Def000053
+S C$offlpxosc.c$8$0$0 Def000000
+S A$offlpxosc$1200 Def000014
+S A$offlpxosc$1210 Def000021
+S A$offlpxosc$1201 Def000017
+S A$offlpxosc$1202 Def000018
+S A$offlpxosc$1203 Def000019
+S A$offlpxosc$1231 Def00002F
+S A$offlpxosc$1222 Def000028
+S A$offlpxosc$1213 Def000022
+S A$offlpxosc$1204 Def00001B
+S A$offlpxosc$1232 Def000032
+S A$offlpxosc$1205 Def00001C
+S A$offlpxosc$1233 Def000033
+S A$offlpxosc$1252 Def00003D
+S A$offlpxosc$1234 Def000034
+S A$offlpxosc$1225 Def00002A
+S A$offlpxosc$1216 Def000024
+S A$offlpxosc$1280 Def000053
+S A$offlpxosc$1262 Def000046
+S A$offlpxosc$1253 Def00003E
+S A$offlpxosc$1235 Def000036
+S A$offlpxosc$1208 Def00001D
+S A$offlpxosc$1190 Def00000A
+S A$offlpxosc$1272 Def00004E
+S A$offlpxosc$1263 Def000047
+S A$offlpxosc$1254 Def00003F
+S A$offlpxosc$1245 Def00003A
+S A$offlpxosc$1236 Def000037
+S A$offlpxosc$1209 Def00001F
+S A$offlpxosc$1191 Def00000D
+S A$offlpxosc$1264 Def000048
+S A$offlpxosc$1255 Def000040
+S A$offlpxosc$1228 Def00002C
+S A$offlpxosc$1219 Def000026
+S A$offlpxosc$1192 Def00000E
+S A$offlpxosc$1265 Def000049
+S A$offlpxosc$1256 Def000041
+S A$offlpxosc$1193 Def00000F
+S A$offlpxosc$1184 Def000000
+S A$offlpxosc$1275 Def000050
+S A$offlpxosc$1266 Def00004A
+S A$offlpxosc$1239 Def000038
+S A$offlpxosc$1185 Def000003
+S A$offlpxosc$1276 Def000051
+S A$offlpxosc$1249 Def00003C
+S A$offlpxosc$1186 Def000004
+S A$offlpxosc$1259 Def000043
+S A$offlpxosc$1196 Def000012
+S A$offlpxosc$1187 Def000005
+S G$turn_off_lpxosc$0$0 Def000000
+S A$offlpxosc$1269 Def00004C
+S A$offlpxosc$1188 Def000008
+S C$offlpxosc.c$20$1$33 Def00002A
+S C$offlpxosc.c$30$1$33 Def000046
+S C$offlpxosc.c$21$1$33 Def00002C
+S C$offlpxosc.c$12$1$33 Def000000
+S C$offlpxosc.c$31$1$33 Def00004C
+S C$offlpxosc.c$22$1$33 Def00002F
+S C$offlpxosc.c$13$1$33 Def000012
+S C$offlpxosc.c$32$1$33 Def00004E
+S C$offlpxosc.c$23$1$33 Def000038
+S C$offlpxosc.c$14$1$33 Def000014
+S C$offlpxosc.c$33$1$33 Def000050
+S C$offlpxosc.c$24$1$33 Def00003A
+S C$offlpxosc.c$15$1$33 Def00001D
+S C$offlpxosc.c$34$1$33 Def000053
+S C$offlpxosc.c$16$1$33 Def000022
+S C$offlpxosc.c$25$2$33 Def00003A
+S C$offlpxosc.c$17$1$33 Def000024
+S C$offlpxosc.c$18$1$33 Def000026
+S C$offlpxosc.c$19$1$33 Def000028
+S _turn_off_lpxosc Def000000
+S C$offlpxosc.c$28$2$34 Def00003D
+S C$offlpxosc.c$29$2$34 Def000043
+S C$offlpxosc.c$27$3$35 Def00003C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 7F 00 E0 FF BF 8E 02 80 0A
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 90 7F 01 E0 FF 30 E0 02 80 3F
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 90 7F 01 E0 FF 74 01 4F F0 74 80 55 A8
+R 00 00 00 16
+T 00 00 21 FF C2 AF AE 80 AD 89 D2 84 C2 85 43 89
+R 00 00 00 16
+T 00 00 2E 18 90 70 50 E0 FC 74 F7 5C F0 7C 06
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A 7B 80
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 00 EB 14 FA FB 70 F9 63 80 18 EC 14 FB
+R 00 00 00 16
+T 00 00 49 FC 70 EE 8D 89 8E 80 EF 42 A8
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 22
+R 00 00 00 16
+
+
+M:offlpxosc
+F:G$turn_off_lpxosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lofflpxosc.turn_off_lpxosc$iesave$1$33({1}SC:U),R,0,0,[r7]
+S:Lofflpxosc.turn_off_lpxosc$portasave$1$33({1}SC:U),R,0,0,[r6]
+S:Lofflpxosc.turn_off_lpxosc$dirasave$1$33({1}SC:U),R,0,0,[r5]
+S:Lofflpxosc.turn_off_lpxosc$i$1$33({1}SC:U),R,0,0,[r4]
+S:Lofflpxosc.turn_off_lpxosc$j$2$34({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
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+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setuplpxosc
+
+;!FILE libmf/setuplpxosc.asm
+XH3
+H 1A areas 2E3 global symbols
+M setuplpxosc
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1D flags 20 addr 0
+S C$setuplpxosc.c$8$0$0 Def000000
+S _setup_lpxosc Def000000
+S XG$setup_lpxosc$0$0 Def00001C
+S A$setuplpxosc$1202 Def00001C
+S A$setuplpxosc$1180 Def000005
+S A$setuplpxosc$1190 Def00000E
+S A$setuplpxosc$1181 Def000006
+S A$setuplpxosc$1182 Def000007
+S A$setuplpxosc$1183 Def000009
+S A$setuplpxosc$1193 Def000011
+S A$setuplpxosc$1184 Def00000A
+S A$setuplpxosc$1194 Def000014
+S A$setuplpxosc$1176 Def000000
+S A$setuplpxosc$1195 Def000015
+S A$setuplpxosc$1196 Def000016
+S A$setuplpxosc$1187 Def00000B
+S A$setuplpxosc$1197 Def000018
+S A$setuplpxosc$1179 Def000002
+S A$setuplpxosc$1198 Def000019
+S C$setuplpxosc.c$10$1$33 Def000002
+S A$setuplpxosc$1199 Def00001A
+S C$setuplpxosc.c$11$1$33 Def00000B
+S C$setuplpxosc.c$12$1$33 Def00000E
+S C$setuplpxosc.c$13$1$33 Def000011
+S C$setuplpxosc.c$14$1$33 Def00001C
+S G$setup_lpxosc$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 90 70 07 E0 FF 74 18 4F F0 53 89
+R 00 00 00 16
+T 00 00 0D E7 53 80 E7 90 7F 01 E0 FF 74 FE 5F F0
+R 00 00 00 16
+T 00 00 1A D0 07 22
+R 00 00 00 16
+
+
+M:setuplpxosc
+F:G$setup_lpxosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setupxosc
+
+;!FILE libmf/setupxosc.asm
+XH3
+H 1A areas 2E3 global symbols
+M setupxosc
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1D flags 20 addr 0
+S A$setupxosc$1180 Def000005
+S A$setupxosc$1190 Def00000E
+S A$setupxosc$1181 Def000006
+S A$setupxosc$1182 Def000007
+S A$setupxosc$1183 Def000009
+S A$setupxosc$1193 Def000011
+S A$setupxosc$1184 Def00000A
+S A$setupxosc$1194 Def000014
+S A$setupxosc$1176 Def000000
+S A$setupxosc$1195 Def000015
+S A$setupxosc$1196 Def000016
+S A$setupxosc$1187 Def00000B
+S A$setupxosc$1197 Def000018
+S A$setupxosc$1179 Def000002
+S A$setupxosc$1198 Def000019
+S C$setupxosc.c$10$1$33 Def000002
+S A$setupxosc$1199 Def00001A
+S C$setupxosc.c$11$1$33 Def00000B
+S C$setupxosc.c$12$1$33 Def00000E
+S C$setupxosc.c$13$1$33 Def000011
+S C$setupxosc.c$14$1$33 Def00001C
+S G$setup_xosc$0$0 Def000000
+S C$setupxosc.c$8$0$0 Def000000
+S _setup_xosc Def000000
+S XG$setup_xosc$0$0 Def00001C
+S A$setupxosc$1202 Def00001C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 90 70 07 E0 FF 74 03 4F F0 53 89
+R 00 00 00 16
+T 00 00 0D FC 53 80 FC 90 7F 01 E0 FF 74 FD 5F F0
+R 00 00 00 16
+T 00 00 1A D0 07 22
+R 00 00 00 16
+
+
+M:setupxosc
+F:G$setup_xosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setupcal
+
+;!FILE libmf/setupcal.asm
+XH3
+H 1A areas 484 global symbols
+M setupcal
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _setup_lpxosc Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S _setup_xosc Ref000000
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25A flags 20 addr 0
+S A$setupcal$1669 Def00021F
+S A$setupcal$1588 Def0001C4
+S A$setupcal$1579 Def0001B6
+S A$setupcal$1498 Def000158
+S C$setupcal.c$50$2$40 Def000127
+S A$setupcal$1589 Def0001C6
+S A$setupcal$1499 Def000159
+S C$setupcal.c$51$2$40 Def00012B
+S C$setupcal.c$23$1$33 Def00004D
+S A$setupcal$1698 Def000233
+S A$setupcal$1689 Def00022E
+S A$setupcal$1599 Def0001D6
+S C$setupcal.c$52$2$40 Def00012F
+S C$setupcal.c$13$2$34 Def00001A
+S C$setupcal.c$53$2$40 Def000134
+S C$setupcal.c$14$2$34 Def00001E
+S C$setupcal.c$30$2$37 Def00006F
+S C$setupcal.c$15$2$34 Def000022
+S C$setupcal.c$72$1$42 Def000172
+S C$setupcal.c$31$2$37 Def000078
+S C$setupcal.c$18$1$33 Def000036
+S C$setupcal.c$16$2$34 Def000027
+S C$setupcal.c$73$1$42 Def000192
+S C$setupcal.c$43$1$36 Def0000EF
+S C$setupcal.c$32$2$37 Def00009C
+S C$setupcal.c$19$1$33 Def000045
+S C$setupcal.c$74$1$42 Def000196
+S C$setupcal.c$35$1$36 Def0000A3
+S C$setupcal.c$75$1$42 Def00019C
+S C$setupcal.c$45$1$36 Def0000F0
+S C$setupcal.c$11$1$0 Def000007
+S C$setupcal.c$90$2$45 Def0001FE
+S C$setupcal.c$76$1$42 Def0001C2
+S C$setupcal.c$28$1$36 Def00005A
+S C$setupcal.c$91$2$45 Def000203
+S C$setupcal.c$84$2$43 Def0001E4
+S C$setupcal.c$77$1$42 Def0001D6
+S C$setupcal.c$47$1$36 Def0000F7
+S C$setupcal.c$29$1$36 Def000065
+S C$setupcal.c$92$2$45 Def000206
+S C$setupcal.c$63$1$39 Def00015C
+S C$setupcal.c$93$2$45 Def00020F
+S C$setupcal.c$88$1$42 Def0001EB
+S C$setupcal.c$64$1$39 Def00015E
+S C$setupcal.c$55$1$39 Def000143
+S Fsetupcal$compute_frcoscref$0$0 Def00004D
+S C$setupcal.c$94$2$45 Def000212
+S C$setupcal.c$89$1$42 Def0001F4
+S C$setupcal.c$86$2$44 Def0001E8
+S C$setupcal.c$56$1$39 Def00014F
+S C$setupcal.c$95$2$45 Def000215
+S C$setupcal.c$79$2$43 Def0001DA
+S C$setupcal.c$66$1$39 Def00015F
+S C$setupcal.c$48$1$39 Def0000F9
+S G$setup_osc_calibration$0$0 Def00015F
+S C$setupcal.c$58$1$39 Def000154
+S C$setupcal.c$49$1$39 Def000119
+S C$setupcal.c$97$2$45 Def000215
+S C$setupcal.c$68$1$39 Def00016B
+S C$setupcal.c$98$2$45 Def000217
+S C$setupcal.c$99$2$45 Def00021A
+S XFsetupcal$compute_frcosccfg$0$0 Def00004C
+S _setup_osc_calibration Def00015F
+S C$setupcal.c$9$0$0 Def000000
+S Fsetupcal$compute_lposccfg$0$0 Def0000F0
+S XFsetupcal$compute_frcoscref$0$0 Def0000EF
+S XG$setup_osc_calibration$0$0 Def000259
+S A$setupcal$1200 Def000016
+S A$setupcal$1300 Def000074
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+S:Lsetupcal.compute_frcosccfg$reffreq$1$32({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Lsetupcal.compute_frcosccfg$x$1$33({1}SC:U),R,0,0,[r3]
+F:Fsetupcal$compute_frcoscref$0$0({2}DF,SV:S),C,0,4,0,0,0
+S:Lsetupcal.compute_frcoscref$calcfg$1$35({1}SC:U),B,1,-3
+S:Lsetupcal.compute_frcoscref$reffreq$1$35({4}SL:U),B,1,1
+F:Fsetupcal$compute_lposccfg$0$0({2}DF,SC:U),C,0,0,0,0,0
+S:Lsetupcal.compute_lposccfg$reffreq$1$38({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Lsetupcal.compute_lposccfg$x$1$39({1}SC:U),R,0,0,[r3]
+F:G$setup_osc_calibration$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lsetupcal.setup_osc_calibration$refosc$1$41({1}SC:U),B,1,-3
+S:Lsetupcal.setup_osc_calibration$reffreq$1$41({4}SL:U),R,0,0,[r4,r5,r6,r7]
+S:Lsetupcal.setup_osc_calibration$refosc1$1$42({1}SC:U),R,0,0,[r3]
+S:Lsetupcal.setup_osc_calibration$lposccfg$1$42({1}SC:U),R,0,0,[r7]
+S:Lsetupcal.setup_osc_calibration$frcosccfg$1$42({1}SC:U),R,0,0,[r2]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:Fsetupcal$compute_frcosccfg$0$0({2}DF,SC:U),C,0,0
+S:Fsetupcal$compute_frcoscref$0$0({2}DF,SV:S),C,0,4
+S:Fsetupcal$compute_lposccfg$0$0({2}DF,SC:U),C,0,0
+S:Lsetupcal.compute_frcoscref$refs$1$36({36}DA9d,SL:U),D,0,0
+
+
+
+
+wtimer
+
+;!FILE libmf/wtimer.asm
+XH3
+H 21 areas 691 global symbols
+M wtimer
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _enter_sleep_cont Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S _enter_standby Ref000000
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S _enter_sleep Ref000000
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A BIT_BANK size 1 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 12 flags 40 addr 0
+S G$wtimer_state$0$0 Def000000
+S G$wtimer_pending$0$0 Def000010
+S _wtimer_state Def000000
+S _wtimer_pending Def000010
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 1BB flags 20 addr 0
+S C$wtimer.c$28$2$62 Def000038
+S C$wtimer.c$23$1$59 Def000021
+S C$wtimer.c$18$1$59 Def000000
+S Fwtimer$dummy1$0$0 Def00006B
+S Fwtimer$dummy3$0$0 Def000113
+S _wtimer0_update Def0000E7
+S XG$wtimer0_schedq$0$0 Def0000E6
+S _wtimer1_update Def00018F
+S Fwtimer$dummy5$0$0 Def0001BB
+S XG$wtimer1_schedq$0$0 Def00018E
+S XG$wtimer0_update$0$0 Def000113
+S XG$wtimer1_update$0$0 Def0001BB
+S G$wtimer_irq$0$0 Def000000
+S XFwtimer$dummy0$0$0 Def000000
+S XFwtimer$dummy2$0$0 Def00006B
+S XFwtimer$dummy4$0$0 Def000113
+S _wtimer_irq Def000000
+S A$wtimer$2000 Def00017B
+S A$wtimer$2010 Def000189
+S A$wtimer$2001 Def00017C
+S A$wtimer$2011 Def00018A
+S A$wtimer$2002 Def00017D
+S A$wtimer$1300 Def000056
+S A$wtimer$2030 Def00018F
+S A$wtimer$2012 Def00018B
+S A$wtimer$1301 Def000058
+S A$wtimer$2040 Def00019D
+S A$wtimer$2031 Def000191
+S A$wtimer$2013 Def00018D
+S A$wtimer$2004 Def000180
+S A$wtimer$1302 Def00005A
+S A$wtimer$2050 Def0001AB
+S A$wtimer$2041 Def00019E
+S A$wtimer$2032 Def000193
+S A$wtimer$2005 Def000183
+S A$wtimer$1312 Def00006A
+S A$wtimer$1303 Def00005C
+S A$wtimer$1240 Def00000C
+S A$wtimer$2060 Def0001B6
+S A$wtimer$2051 Def0001AC
+S A$wtimer$2042 Def00019F
+S A$wtimer$2033 Def000196
+S A$wtimer$2006 Def000184
+S A$wtimer$1700 Def0000D8
+S A$wtimer$1304 Def00005E
+S A$wtimer$1241 Def00000E
+S A$wtimer$2061 Def0001B7
+S A$wtimer$2052 Def0001AD
+S A$wtimer$2043 Def0001A0
+S A$wtimer$2034 Def000197
+S A$wtimer$2016 Def00018E
+S A$wtimer$2007 Def000185
+S A$wtimer$1701 Def0000DB
+S A$wtimer$1611 Def00006B
+S A$wtimer$1305 Def000060
+S A$wtimer$1260 Def000026
+S A$wtimer$1251 Def00001F
+S A$wtimer$1242 Def000010
+S A$wtimer$2062 Def0001B9
+S A$wtimer$2053 Def0001AE
+S A$wtimer$2044 Def0001A1
+S A$wtimer$2035 Def000198
+S A$wtimer$2008 Def000186
+S A$wtimer$1702 Def0000DC
+S A$wtimer$1621 Def000079
+S A$wtimer$1612 Def00006E
+S A$wtimer$1306 Def000062
+S A$wtimer$1270 Def000034
+S A$wtimer$1261 Def000027
+S A$wtimer$1243 Def000012
+S A$wtimer$1234 Def000000
+S A$wtimer$2054 Def0001AF
+S A$wtimer$2045 Def0001A2
+S A$wtimer$2036 Def000199
+S A$wtimer$2009 Def000187
+S A$wtimer$1730 Def0000EF
+S A$wtimer$1712 Def0000E6
+S A$wtimer$1703 Def0000DD
+S A$wtimer$1640 Def000092
+S A$wtimer$1622 Def00007C
+S A$wtimer$1613 Def00006F
+S A$wtimer$1307 Def000064
+S A$wtimer$1280 Def00003D
+S A$wtimer$1271 Def000036
+S A$wtimer$1244 Def000014
+S A$wtimer$1235 Def000002
+S C$wtimer.c$510$1$90 Def00018F
+S A$wtimer$2064 Def0001BA
+S A$wtimer$2055 Def0001B0
+S A$wtimer$2046 Def0001A4
+S A$wtimer$2037 Def00019A
+S A$wtimer$1920 Def00011A
+S A$wtimer$1740 Def0000F9
+S A$wtimer$1731 Def0000F0
+S A$wtimer$1704 Def0000DE
+S A$wtimer$1650 Def00009E
+S A$wtimer$1641 Def000093
+S A$wtimer$1632 Def000088
+S A$wtimer$1623 Def00007D
+S A$wtimer$1614 Def000070
+S A$wtimer$1308 Def000066
+S A$wtimer$1254 Def000021
+S A$wtimer$1245 Def000016
+S A$wtimer$1236 Def000004
+S C$wtimer.c$301$1$84 Def000113
+S A$wtimer$2056 Def0001B1
+S A$wtimer$2047 Def0001A6
+S A$wtimer$2038 Def00019B
+S A$wtimer$1930 Def00012A
+S A$wtimer$1921 Def00011B
+S A$wtimer$1750 Def000107
+S A$wtimer$1741 Def0000FA
+S A$wtimer$1732 Def0000F1
+S A$wtimer$1705 Def0000DF
+S A$wtimer$1660 Def0000A8
+S A$wtimer$1651 Def00009F
+S A$wtimer$1642 Def000094
+S A$wtimer$1633 Def00008A
+S A$wtimer$1624 Def00007F
+S A$wtimer$1615 Def000071
+S A$wtimer$1309 Def000068
+S A$wtimer$1291 Def00004A
+S A$wtimer$1264 Def00002A
+S A$wtimer$1246 Def000018
+S A$wtimer$1237 Def000006
+S XG$wtimer_irq$0$0 Def00006A
+S A$wtimer$2057 Def0001B2
+S A$wtimer$2048 Def0001A9
+S A$wtimer$2039 Def00019C
+S A$wtimer$1940 Def000136
+S A$wtimer$1931 Def00012B
+S A$wtimer$1922 Def00011E
+S A$wtimer$1760 Def000112
+S A$wtimer$1751 Def000108
+S A$wtimer$1742 Def0000FC
+S A$wtimer$1733 Def0000F2
+S A$wtimer$1706 Def0000E1
+S A$wtimer$1670 Def0000B3
+S A$wtimer$1661 Def0000A9
+S A$wtimer$1652 Def0000A0
+S A$wtimer$1643 Def000095
+S A$wtimer$1634 Def00008C
+S A$wtimer$1625 Def000081
+S A$wtimer$1616 Def000072
+S A$wtimer$1283 Def000040
+S A$wtimer$1274 Def000038
+S A$wtimer$1265 Def00002C
+S A$wtimer$1247 Def00001A
+S A$wtimer$1238 Def000008
+S C$wtimer.c$253$1$80 Def00006B
+S A$wtimer$2058 Def0001B4
+S A$wtimer$2049 Def0001AA
+S A$wtimer$1950 Def000140
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+S G$wtimer1_schedq$0$0 Def000113
+S C$wtimer.c$257$1$80 Def0000E7
+S A$wtimer$1990 Def000171
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+S A$wtimer$1927 Def000125
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+S C$wtimer.c$403$1$88 Def000113
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+T 00 01 7C
+R 00 00 00 17
+T 00 01 7C C3 13 DC FC 2A FA E4 3B FB E4 3C FC
+R 00 00 00 17
+T 00 01 88
+R 00 00 00 17
+T 00 01 88 90 00 00 E0 2A F0 A3 E0 3B F0 A3 E0 3C
+R 00 00 00 17 00 04 00 0B
+T 00 01 95 F0 A3 E0 34 00 F0
+R 00 00 00 17
+T 00 01 9B
+R 00 00 00 17
+T 00 01 9B 22
+R 00 00 00 17
+T 00 01 9C
+R 00 00 00 17
+T 00 01 9C D3 E5 F4 95 F2 FA E5 F5 95 EB FB 74 10
+R 00 00 00 17
+T 00 01 A9 2B 40 19 D3 E5 F6 95 FA FA E5 F7 95 EB
+R 00 00 00 17
+T 00 01 B6 FB 74 10 2B 40 09 E5 EA 54 21 70 03 F5
+R 00 00 00 17
+T 00 01 C3 82 22
+R 00 00 00 17
+T 00 01 C5
+R 00 00 00 17
+T 00 01 C5 75 82 01 22
+R 00 00 00 17
+T 00 01 C9
+R 00 00 00 17
+T 00 00 00
+R 00 00 00 18
+T 00 00 00 75 82 00 22
+R 00 00 00 18
+T 00 00 04
+R 00 00 00 18
+T 00 00 04 90 00 0E E0 F4 70 F5 A3 E0 F4 70 F0
+R 00 00 00 18 00 04 00 0B
+T 00 00 00 75 82 01 22
+R 00 00 00 1A
+T 00 00 00 C0 00 C0 01 C0 02 C0 03 C0 04 C0 05 C0
+R 00 00 00 1C
+T 00 00 0D 06 C0 07 12 01 C9 75 82 02 12 02 4A D0
+R 00 00 00 1C 00 07 00 17 00 0D 00 17
+T 00 00 1A 07 D0 06 D0 05 D0 04 D0 03 D0 02 D0 01
+R 00 00 00 1C
+T 00 00 27 D0 00 22
+R 00 00 00 1C
+T 00 01 C9
+R 00 00 00 17
+T 00 01 C9 7F 00
+R 00 00 00 17
+T 00 01 CB
+R 00 00 00 17
+T 00 01 CB 74 80 55 A8 FE C2 AF 12 00 E7 C0 07 C0
+R 00 00 00 17 00 0B 00 0E
+T 00 01 D8 06 12 00 6B 12 01 8F 12
+R 00 00 00 17 00 05 00 0E 00 08 00 0E
+T 00 01 E0 01 13 D0 06 D0 07 8F 05
+R 00 00 00 17 00 03 00 0E
+T 00 01 E8
+R 00 00 00 17
+T 00 01 E8 90 00 10 E0 FB A3 E0 FC BB FF 05 BC FF
+R 00 00 00 17 00 04 00 0B
+T 00 01 F5 02 80 42
+R 00 00 00 17
+T 00 01 F8
+R 00 00 00 17
+T 00 01 F8 8B 82 8C 83 E0 F9 A3 E0 FA 90 00 10 E9
+R 00 00 00 17 00 0D 00 0B
+T 00 02 05 F0 EA A3 F0 EE 42 A8 0D 8B 82 8C 83 A3
+R 00 00 00 17
+T 00 02 12 A3 E0 F9 A3 E0 FA C0 06 C0 05 C0 02 C0
+R 00 00 00 17
+T 00 02 1F 01 12 02 25 80 09
+R 00 00 00 17 00 05 00 17
+T 00 02 25
+R 00 00 00 17
+T 00 02 25 C0 01 C0 02 8B 82 8C 83 22
+R 00 00 00 17
+T 00 02 2E
+R 00 00 00 17
+T 00 02 2E D0 01 D0 02 D0 05 D0 06 C2 AF 80 AE
+R 00 00 00 17
+T 00 02 3A
+R 00 00 00 17
+T 00 02 3A 8D 07 12 01 9C AC 82 EE 42 A8 EC 70 84
+R 00 00 00 17 00 06 00 17
+T 00 02 47 8D 82 22
+R 00 00 00 17
+T 00 02 4A
+R 00 00 00 17
+T 00 02 4A AF 82 74 80 55 A8 FE C2 AF 90 00 10 E0
+R 00 00 00 17 00 0D 00 0B
+T 00 02 57 FC A3 E0 FD BC FF 0A BD FF 07 12 01 9C
+R 00 00 00 17 00 0E 00 17
+T 00 02 64 E5 82 60 08
+R 00 00 00 17
+T 00 02 68
+R 00 00 00 17
+T 00 02 68 EE 42 A8 75 82 01 80 5D
+R 00 00 00 17
+T 00 02 70
+R 00 00 00 17
+T 00 02 70 EF 54 05 60 4B C0 07 C0 06 12 00 04 E5
+R 00 00 00 17 00 0D 00 18
+T 00 02 7D 82 D0 06 D0 07 60 3C 12 01 43 74 F0 24
+R 00 00 00 17 00 0B 00 17
+T 00 02 8A 00 00 00 40 08 74 0C 55 87 44 04 F5 87
+R 00 00 00 17 F1 81 03 00 0B
+T 00 02 95
+R 00 00 00 17
+T 00 02 95 C3 74 00 00 00 94 F8 74 00 00 00 94 0F
+R 00 00 00 17 F1 01 05 00 0B F1 81 0B 00 0B
+T 00 02 9E 40 08 74 0C 55 87 44 08 F5 87
+R 00 00 00 17
+T 00 02 A8
+R 00 00 00 17
+T 00 02 A8 EF 30 E2 0F C0 06 12 00 00 D0 06 EE 42
+R 00 00 00 17 02 0A 00 5B
+T 00 02 B5 A8 75 82 02 80 12
+R 00 00 00 17
+T 00 02 BB
+R 00 00 00 17
+T 00 02 BB 12 00 00 80 07
+R 00 00 00 17 02 04 02 32
+T 00 02 C0
+R 00 00 00 17
+T 00 02 C0 EF 30 E1 03 12 00 00
+R 00 00 00 17 02 08 00 CE
+T 00 02 C7
+R 00 00 00 17
+T 00 02 C7 EE 42 A8 75 82 00
+R 00 00 00 17
+T 00 02 CD
+R 00 00 00 17
+T 00 02 CD 22
+R 00 00 00 17
+
+
+M:wtimer
+F:Fwtimer$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer_irq$0$0({2}DF,SV:S),Z,0,0,1,1,0
+F:Fwtimer$dummy1$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:Fwtimer$wtimer_doinit$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:Lwtimer.wtimer_doinit$wakeup$1$66({1}SC:U),R,0,0,[r7]
+F:G$wtimer_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer_addcb_core$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer_addcb_core$desc$1$74({2}DX,STwtimer_callback:S),R,0,0,[r6,r7]
+S:Lwtimer.wtimer_addcb_core$d$1$75({2}DX,STwtimer_callback:S),R,0,0,[r4,r5]
+S:Lwtimer.wtimer_addcb_core$dn$2$76({2}DX,STwtimer_callback:S),R,0,0,[r2,r3]
+F:Fwtimer$dummy2$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer0_schedq$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer0_update$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fwtimer$dummy3$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer0_addcore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer0_addcore$desc$1$85({2}DX,STwtimer_desc:S),R,0,0,[]
+F:Fwtimer$dummy4$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer1_schedq$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer1_update$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fwtimer$dummy5$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer1_addcore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer1_addcore$desc$1$95({2}DX,STwtimer_desc:S),R,0,0,[]
+F:Fwtimer$wtimer_preparesleep$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:Fwtimer$wtimer_checkexpired$0$0({2}DF,SC:U),C,0,0,0,0,0
+F:Fwtimer$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer_runcallbacks$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$wtimer_idle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtimer.wtimer_idle$flags$1$112({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_idle$iesave$1$113({1}SC:U),R,0,0,[r6]
+T:Fwtimer$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtimer$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtimer$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtimer$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lwtimer.wtimer_irq$dpssave$1$61({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_irq$s$1$61({1}SC:U),R,0,0,[r6]
+S:Lwtimer.wtimer_runcallbacks$ret$1$106({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_runcallbacks$iesave$2$107({1}SC:U),R,0,0,[r6]
+S:Lwtimer.wtimer_runcallbacks$d$4$109({2}DX,STwtimer_callback:S),R,0,0,[r3,r4]
+S:Lwtimer.wtimer_runcallbacks$exp$4$111({1}SC:U),R,0,0,[r4]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:Fwtimer$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy1$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_doinit$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy2$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy3$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy4$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy5$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_preparesleep$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_checkexpired$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:Fwtimer$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wtrem
+
+;!FILE libmf/wtrem.asm
+XH3
+H 1A areas 30C global symbols
+M wtrem
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S _wtimer_pending Ref000000
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 51 flags 20 addr 0
+S A$wtrem$1232 Def000037
+S A$wtrem$1223 Def00002F
+S A$wtrem$1214 Def000024
+S A$wtrem$1205 Def000019
+S A$wtrem$1260 Def000047
+S A$wtrem$1233 Def00003A
+S A$wtrem$1224 Def000031
+S A$wtrem$1215 Def000026
+S A$wtrem$1206 Def00001B
+S A$wtrem$1261 Def000049
+S A$wtrem$1234 Def00003D
+S A$wtrem$1225 Def000032
+S A$wtrem$1216 Def000028
+S A$wtrem$1226 Def000033
+S A$wtrem$1217 Def000029
+S A$wtrem$1190 Def000006
+S A$wtrem$1281 Def00004B
+S A$wtrem$1227 Def000034
+S A$wtrem$1218 Def00002A
+S A$wtrem$1209 Def00001C
+S A$wtrem$1191 Def000008
+S A$wtrem$1282 Def00004D
+S A$wtrem$1237 Def00003F
+S A$wtrem$1228 Def000035
+S A$wtrem$1219 Def00002B
+S A$wtrem$1283 Def00004F
+S A$wtrem$1238 Def000041
+S A$wtrem$1184 Def000000
+S A$wtrem$1239 Def000043
+S A$wtrem$1194 Def00000A
+S A$wtrem$1185 Def000002
+S A$wtrem$1195 Def00000C
+S A$wtrem$1259 Def000045
+S A$wtrem$1196 Def00000E
+S A$wtrem$1197 Def00000F
+S A$wtrem$1188 Def000004
+S A$wtrem$1198 Def000010
+S A$wtrem$1199 Def000011
+S G$wtimer0_removecb_core$0$0 Def000045
+S G$wtimer1_removecb_core$0$0 Def00004B
+S C$wtrem.c$85$1$61 Def000045
+S C$wtrem.c$86$1$61 Def00004B
+S C$wtrem.c$95$1$63 Def00004B
+S C$wtrem.c$88$1$61 Def00004B
+S C$wtrem.c$96$1$63 Def000051
+S C$wtrem.c$75$1$59 Def000000
+S C$wtrem.c$76$1$59 Def000045
+S C$wtrem.c$78$1$59 Def000045
+S _wtimer0_removecb_core Def000045
+S _wtimer1_removecb_core Def00004B
+S G$wtimer_removecb_core$0$0 Def000000
+S C$wtrem.c$6$0$0 Def000000
+S XG$wtimer0_removecb_core$0$0 Def00004B
+S XG$wtimer1_removecb_core$0$0 Def000051
+S _wtimer_removecb_core Def000000
+S A$wtrem$1200 Def000012
+S A$wtrem$1210 Def00001D
+S A$wtrem$1220 Def00002C
+S A$wtrem$1211 Def000020
+S A$wtrem$1202 Def000013
+S XG$wtimer_removecb_core$0$0 Def000045
+S A$wtrem$1230 Def000036
+S A$wtrem$1212 Def000021
+S A$wtrem$1203 Def000016
+S A$wtrem$1222 Def00002D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 7C 00 00 00 7D 00 00 00
+R 00 00 00 16 F1 03 04 02 7E F1 83 08 02 7E
+T 00 00 04
+R 00 00 00 16
+T 00 00 04 78 00 AA 82 AB 83
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 8C 82 8D 83 E0 FE A3 E0 FF BE FF 06 BF
+R 00 00 00 16
+T 00 00 17 FF 03
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 88 82 22
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C EA B5 06 1F EB B5 07 1B 8E 82 8F 83 E0
+R 00 00 00 16
+T 00 00 29 FE A3 E0 FF 8C 82 8D 83 EE F0 A3 EF F0
+R 00 00 00 16
+T 00 00 36 08 BE FF 05 BF FF 02 80 DA
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F AC 06 AD 07 80 C5
+R 00 00 00 16
+T 00 00 45
+R 00 00 00 16
+T 00 00 45 7C 00 00 06 7D 00 00 06 80 B9
+R 00 00 00 16 F1 03 04 02 40 F1 83 08 02 40
+T 00 00 4B
+R 00 00 00 16
+T 00 00 4B 7C 00 00 0E 7D 00 00 0E 80 B3
+R 00 00 00 16 F1 03 04 02 40 F1 83 08 02 40
+
+
+M:wtrem
+F:G$wtimer_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer_removecb_core$desc$1$58({2}DX,STwtimer_callback:S),R,0,0,[]
+F:G$wtimer0_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer0_removecb_core$desc$1$60({2}DX,STwtimer_desc:S),R,0,0,[]
+F:G$wtimer1_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer1_removecb_core$desc$1$62({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwtrem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtrem$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtrem$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtrem$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wtcbadd
+
+;!FILE libmf/wtcbadd.asm
+XH3
+H 1A areas 2E1 global symbols
+M wtcbadd
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S _wtimer_addcb_core Ref000000
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1A flags 20 addr 0
+S _wtimer_add_callback Def000000
+S C$wtcbadd.c$4$0$0 Def000000
+S C$wtcbadd.c$6$1$59 Def000004
+S C$wtcbadd.c$7$1$59 Def000009
+S C$wtcbadd.c$8$1$59 Def00000B
+S C$wtcbadd.c$9$1$59 Def000016
+S XG$wtimer_add_callback$0$0 Def000019
+S A$wtcbadd$1200 Def000017
+S A$wtcbadd$1203 Def000019
+S A$wtcbadd$1180 Def000000
+S A$wtcbadd$1181 Def000002
+S A$wtcbadd$1192 Def00000B
+S A$wtcbadd$1193 Def00000D
+S A$wtcbadd$1184 Def000004
+S A$wtcbadd$1194 Def00000F
+S A$wtcbadd$1185 Def000006
+S A$wtcbadd$1195 Def000011
+S A$wtcbadd$1186 Def000008
+S A$wtcbadd$1196 Def000014
+S A$wtcbadd$1189 Def000009
+S A$wtcbadd$1199 Def000016
+S C$wtcbadd.c$10$1$59 Def000019
+S G$wtimer_add_callback$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF 8E 82
+R 00 00 00 16
+T 00 00 0D 8F 83 C0 05 12 00 00 D0 05 ED 42 A8 22
+R 00 00 00 16 02 08 00 8C
+
+
+M:wtcbadd
+F:G$wtimer_add_callback$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtcbadd.wtimer_add_callback$desc$1$58({2}DX,STwtimer_callback:S),R,0,0,[r6,r7]
+S:Lwtcbadd.wtimer_add_callback$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwtcbadd$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtcbadd$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtcbadd$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtcbadd$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wtcbrem
+
+;!FILE libmf/wtcbrem.asm
+XH3
+H 1A areas 2E4 global symbols
+M wtcbrem
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S A$wtcbrem$1202 Def000018
+S A$wtcbrem$1203 Def000019
+S A$wtcbrem$1206 Def00001B
+S A$wtcbrem$1209 Def00001D
+S A$wtcbrem$1191 Def000009
+S A$wtcbrem$1182 Def000000
+S A$wtcbrem$1183 Def000002
+S A$wtcbrem$1194 Def00000B
+S A$wtcbrem$1195 Def00000D
+S A$wtcbrem$1186 Def000004
+S A$wtcbrem$1196 Def00000F
+S A$wtcbrem$1187 Def000006
+S A$wtcbrem$1197 Def000011
+S A$wtcbrem$1188 Def000008
+S A$wtcbrem$1198 Def000014
+S A$wtcbrem$1199 Def000016
+S C$wtcbrem.c$10$1$59 Def00000B
+S C$wtcbrem.c$11$1$59 Def000018
+S C$wtcbrem.c$12$1$59 Def00001B
+S C$wtcbrem.c$13$1$59 Def00001D
+S G$wtimer_remove_callback$0$0 Def000000
+S C$wtcbrem.c$4$0$0 Def000000
+S C$wtcbrem.c$8$1$59 Def000004
+S C$wtcbrem.c$9$1$59 Def000009
+S _wtimer_remove_callback Def000000
+S XG$wtimer_remove_callback$0$0 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF 8E 82
+R 00 00 00 16
+T 00 00 0D 8F 83 C0 05 12 00 00 AF 82 D0 05 ED 42
+R 00 00 00 16 02 08 01 FF
+T 00 00 1A A8 8F 82 22
+R 00 00 00 16
+
+
+M:wtcbrem
+F:G$wtimer_remove_callback$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtcbrem.wtimer_remove_callback$desc$1$58({2}DX,STwtimer_callback:S),R,0,0,[r6,r7]
+S:Lwtcbrem.wtimer_remove_callback$d$1$59({2}DX,STwtimer_desc:S),B,1,3
+S:Lwtcbrem.wtimer_remove_callback$ret$1$59({1}SC:U),R,0,0,[r7]
+S:Lwtcbrem.wtimer_remove_callback$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwtcbrem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtcbrem$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtcbrem$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtcbrem$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0setcfg
+
+;!FILE libmf/wt0setcfg.asm
+XH3
+H 1A areas 2E4 global symbols
+M wt0setcfg
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S _wtimer0_setconfig Def000000
+S C$wt0setcfg.c$4$0$0 Def000000
+S C$wt0setcfg.c$6$1$59 Def000000
+S C$wt0setcfg.c$7$1$59 Def00000B
+S C$wt0setcfg.c$8$1$59 Def00000D
+S C$wt0setcfg.c$9$1$59 Def000010
+S XG$wtimer0_setconfig$0$0 Def00001D
+S A$wt0setcfg$1211 Def00001D
+S A$wt0setcfg$1202 Def000016
+S A$wt0setcfg$1203 Def000018
+S A$wt0setcfg$1204 Def000019
+S A$wt0setcfg$1207 Def00001B
+S A$wt0setcfg$1180 Def000000
+S A$wt0setcfg$1181 Def000002
+S A$wt0setcfg$1182 Def000003
+S A$wt0setcfg$1183 Def000005
+S A$wt0setcfg$1193 Def00000D
+S A$wt0setcfg$1184 Def000007
+S A$wt0setcfg$1185 Def000009
+S A$wt0setcfg$1196 Def000010
+S A$wt0setcfg$1189 Def00000B
+S A$wt0setcfg$1199 Def000013
+S C$wt0setcfg.c$10$1$59 Def000013
+S C$wt0setcfg.c$11$1$59 Def000016
+S G$wtimer0_setconfig$0$0 Def000000
+S C$wt0setcfg.c$12$1$59 Def00001B
+S C$wt0setcfg.c$13$1$59 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF 65 F1 54 3F 60 02 80 02
+R 00 00 00 16
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B 80 10
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D 53 07 3F 43 F1 04 75 F1 0F 74 FC 4F 52
+R 00 00 00 16
+T 00 00 1A F1 8F F1
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 22
+R 00 00 00 16
+
+
+M:wt0setcfg
+F:G$wtimer0_setconfig$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0setcfg.wtimer0_setconfig$cfg$1$58({1}SC:U),R,0,0,[r7]
+T:Fwt0setcfg$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0setcfg$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0setcfg$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0setcfg$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1setcfg
+
+;!FILE libmf/wt1setcfg.asm
+XH3
+H 1A areas 2E4 global symbols
+M wt1setcfg
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S _wtimer1_setconfig Def000000
+S C$wt1setcfg.c$4$0$0 Def000000
+S C$wt1setcfg.c$6$1$59 Def000000
+S C$wt1setcfg.c$7$1$59 Def00000B
+S C$wt1setcfg.c$8$1$59 Def00000D
+S C$wt1setcfg.c$9$1$59 Def000010
+S XG$wtimer1_setconfig$0$0 Def00001D
+S A$wt1setcfg$1211 Def00001D
+S A$wt1setcfg$1202 Def000016
+S A$wt1setcfg$1203 Def000018
+S A$wt1setcfg$1204 Def000019
+S A$wt1setcfg$1207 Def00001B
+S A$wt1setcfg$1180 Def000000
+S A$wt1setcfg$1181 Def000002
+S A$wt1setcfg$1182 Def000003
+S A$wt1setcfg$1183 Def000005
+S A$wt1setcfg$1193 Def00000D
+S A$wt1setcfg$1184 Def000007
+S A$wt1setcfg$1185 Def000009
+S A$wt1setcfg$1196 Def000010
+S A$wt1setcfg$1189 Def00000B
+S A$wt1setcfg$1199 Def000013
+S C$wt1setcfg.c$10$1$59 Def000013
+S C$wt1setcfg.c$11$1$59 Def000016
+S G$wtimer1_setconfig$0$0 Def000000
+S C$wt1setcfg.c$12$1$59 Def00001B
+S C$wt1setcfg.c$13$1$59 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF 65 F9 54 3F 60 02 80 02
+R 00 00 00 16
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B 80 10
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D 53 07 3F 43 F9 04 75 F9 0F 74 FC 4F 52
+R 00 00 00 16
+T 00 00 1A F9 8F F9
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 22
+R 00 00 00 16
+
+
+M:wt1setcfg
+F:G$wtimer1_setconfig$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1setcfg.wtimer1_setconfig$cfg$1$58({1}SC:U),R,0,0,[r7]
+T:Fwt1setcfg$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1setcfg$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1setcfg$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1setcfg$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wtstdby
+
+;!FILE libmf/wtstdby.asm
+XH3
+H 1D areas 2D5 global symbols
+M wtstdby
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A WTSTDBY0 size 0 flags 20 addr 0
+S _wtimer_standby Def000000
+S C$wtstdby.c$24$1$28 Def000000
+S C$wtstdby.c$10$0$0 Def000000
+S G$wtimer_standby$0$0 Def000000
+A WTSTDBY1 size 0 flags 20 addr 0
+A WTSTDBY2 size A flags 20 addr 0
+S XG$wtimer_standby$0$0 Def000009
+S A$wtstdby$1190 Def000009
+S A$wtstdby$1183 Def000000
+S A$wtstdby$1184 Def000002
+S A$wtstdby$1185 Def000004
+S A$wtstdby$1186 Def000006
+S A$wtstdby$1187 Def000008
+S C$wtstdby.c$25$1$28 Def000009
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 74 0C 55 87 44 01 F5 87 22 22
+R 00 00 00 19
+
+
+M:wtstdby
+F:G$wtimer_standby$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
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+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wt0adda
+
+;!FILE libmf/wt0adda.asm
+XH3
+H 1A areas 2ED global symbols
+M wt0adda
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer0_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S _wtimer0_addcore Ref000000
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _wtimer0_schedq Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S A$wt0adda$1197 Def000011
+S A$wt0adda$1188 Def000008
+S A$wt0adda$1198 Def000014
+S A$wt0adda$1199 Def000016
+S G$wtimer0_addabsolute$0$0 Def000000
+S C$wt0adda.c$10$1$59 Def000023
+S C$wt0adda.c$11$1$59 Def000028
+S C$wt0adda.c$12$1$59 Def00002B
+S _wtimer0_addabsolute Def000000
+S XG$wtimer0_addabsolute$0$0 Def00002B
+S C$wt0adda.c$4$0$0 Def000000
+S C$wt0adda.c$6$1$59 Def000004
+S C$wt0adda.c$7$1$59 Def000009
+S C$wt0adda.c$8$1$59 Def00000B
+S C$wt0adda.c$9$1$59 Def00001A
+S A$wt0adda$1200 Def000018
+S A$wt0adda$1210 Def000026
+S A$wt0adda$1203 Def00001A
+S A$wt0adda$1213 Def000028
+S A$wt0adda$1204 Def00001C
+S A$wt0adda$1214 Def000029
+S A$wt0adda$1205 Def00001E
+S A$wt0adda$1206 Def000020
+S A$wt0adda$1217 Def00002B
+S A$wt0adda$1209 Def000023
+S A$wt0adda$1191 Def000009
+S A$wt0adda$1182 Def000000
+S A$wt0adda$1183 Def000002
+S A$wt0adda$1194 Def00000B
+S A$wt0adda$1195 Def00000D
+S A$wt0adda$1186 Def000004
+S A$wt0adda$1196 Def00000F
+S A$wt0adda$1187 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF C0 07
+R 00 00 00 16
+T 00 00 0D C0 06 C0 05 12 00 00 D0 05 D0 06 D0 07
+R 00 00 00 16 02 08 00 6B
+T 00 00 1A 8E 82 8F 83 C0 05 12 00 00 12 00 00 D0
+R 00 00 00 16 02 0A 00 FF 02 0D 02 C2
+T 00 00 27 05 ED 42 A8 22
+R 00 00 00 16
+
+
+M:wt0adda
+F:G$wtimer0_addabsolute$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0adda.wtimer0_addabsolute$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt0adda.wtimer0_addabsolute$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt0adda$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0adda$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0adda$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0adda$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1adda
+
+;!FILE libmf/wt1adda.asm
+XH3
+H 1A areas 2ED global symbols
+M wt1adda
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S _wtimer1_update Ref000000
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S _wtimer1_addcore Ref000000
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+S _wtimer1_schedq Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S A$wt1adda$1196 Def00000F
+S A$wt1adda$1187 Def000006
+S A$wt1adda$1197 Def000011
+S A$wt1adda$1188 Def000008
+S A$wt1adda$1198 Def000014
+S A$wt1adda$1199 Def000016
+S G$wtimer1_addabsolute$0$0 Def000000
+S C$wt1adda.c$10$1$59 Def000023
+S C$wt1adda.c$11$1$59 Def000028
+S C$wt1adda.c$12$1$59 Def00002B
+S _wtimer1_addabsolute Def000000
+S XG$wtimer1_addabsolute$0$0 Def00002B
+S C$wt1adda.c$4$0$0 Def000000
+S C$wt1adda.c$6$1$59 Def000004
+S C$wt1adda.c$7$1$59 Def000009
+S C$wt1adda.c$8$1$59 Def00000B
+S C$wt1adda.c$9$1$59 Def00001A
+S A$wt1adda$1200 Def000018
+S A$wt1adda$1210 Def000026
+S A$wt1adda$1203 Def00001A
+S A$wt1adda$1213 Def000028
+S A$wt1adda$1204 Def00001C
+S A$wt1adda$1214 Def000029
+S A$wt1adda$1205 Def00001E
+S A$wt1adda$1206 Def000020
+S A$wt1adda$1217 Def00002B
+S A$wt1adda$1209 Def000023
+S A$wt1adda$1191 Def000009
+S A$wt1adda$1182 Def000000
+S A$wt1adda$1183 Def000002
+S A$wt1adda$1194 Def00000B
+S A$wt1adda$1195 Def00000D
+S A$wt1adda$1186 Def000004
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF C0 07
+R 00 00 00 16
+T 00 00 0D C0 06 C0 05 12 00 00 D0 05 D0 06 D0 07
+R 00 00 00 16 02 08 00 77
+T 00 00 1A 8E 82 8F 83 C0 05 12 00 00 12 00 00 D0
+R 00 00 00 16 02 0A 01 0F 02 0D 02 CB
+T 00 00 27 05 ED 42 A8 22
+R 00 00 00 16
+
+
+M:wt1adda
+F:G$wtimer1_addabsolute$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1adda.wtimer1_addabsolute$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt1adda.wtimer1_addabsolute$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt1adda$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1adda$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1adda$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1adda$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0addr
+
+;!FILE libmf/wt0addr.asm
+XH3
+H 1A areas 304 global symbols
+M wt0addr
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _wtimer0_update Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S _wtimer0_addcore Ref000000
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S _wtimer0_schedq Ref000000
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 47 flags 20 addr 0
+S A$wt0addr$1200 Def000028
+S A$wt0addr$1210 Def000032
+S A$wt0addr$1201 Def000029
+S A$wt0addr$1220 Def000042
+S A$wt0addr$1211 Def000033
+S A$wt0addr$1202 Def00002A
+S A$wt0addr$1221 Def000044
+S A$wt0addr$1212 Def000034
+S A$wt0addr$1203 Def00002B
+S A$wt0addr$1222 Def000046
+S A$wt0addr$1213 Def000035
+S A$wt0addr$1204 Def00002C
+S A$wt0addr$1214 Def000036
+S A$wt0addr$1205 Def00002D
+S A$wt0addr$1215 Def000037
+S A$wt0addr$1206 Def00002E
+S A$wt0addr$1216 Def000038
+S A$wt0addr$1207 Def00002F
+S A$wt0addr$1217 Def00003A
+S A$wt0addr$1208 Def000030
+S A$wt0addr$1190 Def00001A
+S A$wt0addr$1181 Def00000F
+S A$wt0addr$1218 Def00003C
+S A$wt0addr$1209 Def000031
+S A$wt0addr$1191 Def00001B
+S A$wt0addr$1182 Def000012
+S A$wt0addr$1173 Def000000
+S _wtimer0_addrelative Def000000
+S A$wt0addr$1219 Def00003F
+S A$wt0addr$1192 Def00001C
+S A$wt0addr$1183 Def000013
+S A$wt0addr$1174 Def000002
+S A$wt0addr$1193 Def00001D
+S A$wt0addr$1184 Def000014
+S A$wt0addr$1175 Def000004
+S A$wt0addr$1194 Def00001F
+S A$wt0addr$1185 Def000015
+S A$wt0addr$1176 Def000006
+S A$wt0addr$1195 Def000021
+S A$wt0addr$1186 Def000016
+S A$wt0addr$1177 Def000008
+S A$wt0addr$1196 Def000023
+S A$wt0addr$1187 Def000017
+S A$wt0addr$1178 Def00000A
+S A$wt0addr$1197 Def000025
+S A$wt0addr$1188 Def000018
+S A$wt0addr$1179 Def00000C
+S A$wt0addr$1198 Def000026
+S A$wt0addr$1189 Def000019
+S A$wt0addr$1199 Def000027
+S XG$wtimer0_addrelative$0$0 Def000047
+S C$wt0addr.c$60$1$59 Def000047
+S C$wt0addr.c$59$1$59 Def000000
+S C$wt0addr.c$6$0$0 Def000000
+S G$wtimer0_addrelative$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 A8 54 80 C0 E0 C2 AF C0 82 C0 83 12
+R 00 00 00 16
+T 00 00 0D 00 00 90 00 00 E0 FA A3 E0 FB A3 E0 FC
+R 00 00 00 16 02 03 00 5B 02 06 02 42
+T 00 00 1A A3 E0 FD D0 83 D0 82 AE 82 AF 83 A3 A3
+R 00 00 00 16
+T 00 00 27 A3 A3 E0 2A F0 A3 E0 3B F0 A3 E0 3C F0
+R 00 00 00 16
+T 00 00 34 A3 E0 3D F0 8E 82 8F 83 12 00 00 12
+R 00 00 00 16 02 0C 00 F4
+T 00 00 40 00 00 D0 E0 42 A8 22
+R 00 00 00 16 02 03 02 B7
+
+
+M:wt0addr
+F:G$wtimer0_addrelative$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0addr.wtimer0_addrelative$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwt0addr$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0addr$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0addr$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0addr$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1addr
+
+;!FILE libmf/wt1addr.asm
+XH3
+H 1A areas 304 global symbols
+M wt1addr
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer1_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S _wtimer1_addcore Ref000000
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _wtimer1_schedq Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 47 flags 20 addr 0
+S G$wtimer1_addrelative$0$0 Def000000
+S A$wt1addr$1200 Def000028
+S A$wt1addr$1210 Def000032
+S A$wt1addr$1201 Def000029
+S A$wt1addr$1220 Def000042
+S A$wt1addr$1211 Def000033
+S A$wt1addr$1202 Def00002A
+S A$wt1addr$1221 Def000044
+S A$wt1addr$1212 Def000034
+S A$wt1addr$1203 Def00002B
+S A$wt1addr$1222 Def000046
+S A$wt1addr$1213 Def000035
+S A$wt1addr$1204 Def00002C
+S A$wt1addr$1214 Def000036
+S A$wt1addr$1205 Def00002D
+S A$wt1addr$1215 Def000037
+S A$wt1addr$1206 Def00002E
+S A$wt1addr$1216 Def000038
+S A$wt1addr$1207 Def00002F
+S A$wt1addr$1217 Def00003A
+S A$wt1addr$1208 Def000030
+S A$wt1addr$1190 Def00001A
+S A$wt1addr$1181 Def00000F
+S A$wt1addr$1218 Def00003C
+S A$wt1addr$1209 Def000031
+S A$wt1addr$1191 Def00001B
+S A$wt1addr$1182 Def000012
+S A$wt1addr$1173 Def000000
+S _wtimer1_addrelative Def000000
+S A$wt1addr$1219 Def00003F
+S A$wt1addr$1192 Def00001C
+S A$wt1addr$1183 Def000013
+S A$wt1addr$1174 Def000002
+S A$wt1addr$1193 Def00001D
+S A$wt1addr$1184 Def000014
+S A$wt1addr$1175 Def000004
+S A$wt1addr$1194 Def00001F
+S A$wt1addr$1185 Def000015
+S A$wt1addr$1176 Def000006
+S A$wt1addr$1195 Def000021
+S A$wt1addr$1186 Def000016
+S A$wt1addr$1177 Def000008
+S A$wt1addr$1196 Def000023
+S A$wt1addr$1187 Def000017
+S A$wt1addr$1178 Def00000A
+S A$wt1addr$1197 Def000025
+S A$wt1addr$1188 Def000018
+S A$wt1addr$1179 Def00000C
+S A$wt1addr$1198 Def000026
+S A$wt1addr$1189 Def000019
+S A$wt1addr$1199 Def000027
+S XG$wtimer1_addrelative$0$0 Def000047
+S C$wt1addr.c$60$1$59 Def000047
+S C$wt1addr.c$59$1$59 Def000000
+S C$wt1addr.c$6$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 A8 54 80 C0 E0 C2 AF C0 82 C0 83 12
+R 00 00 00 16
+T 00 00 0D 00 00 90 00 08 E0 FA A3 E0 FB A3 E0 FC
+R 00 00 00 16 02 03 00 6B 02 06 02 42
+T 00 00 1A A3 E0 FD D0 83 D0 82 AE 82 AF 83 A3 A3
+R 00 00 00 16
+T 00 00 27 A3 A3 E0 2A F0 A3 E0 3B F0 A3 E0 3C F0
+R 00 00 00 16
+T 00 00 34 A3 E0 3D F0 8E 82 8F 83 12 00 00 12
+R 00 00 00 16 02 0C 00 FF
+T 00 00 40 00 00 D0 E0 42 A8 22
+R 00 00 00 16 02 03 02 C3
+
+
+M:wt1addr
+F:G$wtimer1_addrelative$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1addr.wtimer1_addrelative$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwt1addr$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1addr$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1addr$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1addr$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0curt
+
+;!FILE libmf/wt0curt.asm
+XH3
+H 1A areas 2F0 global symbols
+M wt0curt
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer0_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$wt0curt.c$13$1$59 Def000026
+S XG$wtimer0_curtime$0$0 Def000026
+S C$wt0curt.c$4$0$0 Def000000
+S C$wt0curt.c$7$1$59 Def000000
+S C$wt0curt.c$8$1$59 Def000005
+S C$wt0curt.c$9$1$59 Def000007
+S A$wt0curt$1200 Def000015
+S A$wt0curt$1210 Def00001D
+S A$wt0curt$1201 Def000016
+S A$wt0curt$1202 Def000017
+S A$wt0curt$1203 Def000018
+S A$wt0curt$1213 Def00001F
+S A$wt0curt$1204 Def000019
+S A$wt0curt$1214 Def000021
+S A$wt0curt$1205 Def00001A
+S A$wt0curt$1215 Def000023
+S A$wt0curt$1206 Def00001B
+S A$wt0curt$1216 Def000025
+S A$wt0curt$1190 Def000007
+S A$wt0curt$1209 Def00001C
+S A$wt0curt$1191 Def000009
+S A$wt0curt$1182 Def000000
+S A$wt0curt$1219 Def000026
+S A$wt0curt$1192 Def00000C
+S A$wt0curt$1183 Def000002
+S A$wt0curt$1184 Def000004
+S A$wt0curt$1195 Def00000E
+S A$wt0curt$1196 Def000011
+S A$wt0curt$1187 Def000005
+S G$wtimer0_curtime$0$0 Def000000
+S A$wt0curt$1197 Def000012
+S A$wt0curt$1198 Def000013
+S A$wt0curt$1199 Def000014
+S C$wt0curt.c$10$1$59 Def00000E
+S C$wt0curt.c$11$1$59 Def00001C
+S C$wt0curt.c$12$1$59 Def00001F
+S _wtimer0_curtime Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF C0 07 12 00 00 D0
+R 00 00 00 16 02 0D 00 6B
+T 00 00 0D 07 90 00 00 E0 FB A3 E0 FC A3 E0 FD A3
+R 00 00 00 16 02 05 02 41
+T 00 00 1A E0 FE EF 42 A8 8B 82 8C 83 8D F0 EE 22
+R 00 00 00 16
+
+
+M:wt0curt
+F:G$wtimer0_curtime$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lwt0curt.wtimer0_curtime$r$1$59({4}SL:U),R,0,0,[r3,r4,r5,r6]
+S:Lwt0curt.wtimer0_curtime$iesave$1$59({1}SC:U),R,0,0,[r7]
+T:Fwt0curt$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0curt$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0curt$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0curt$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1curt
+
+;!FILE libmf/wt1curt.asm
+XH3
+H 1A areas 2F0 global symbols
+M wt1curt
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S _wtimer1_update Ref000000
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$wt1curt.c$12$1$59 Def00001F
+S _wtimer1_curtime Def000000
+S C$wt1curt.c$13$1$59 Def000026
+S XG$wtimer1_curtime$0$0 Def000026
+S C$wt1curt.c$4$0$0 Def000000
+S C$wt1curt.c$7$1$59 Def000000
+S C$wt1curt.c$8$1$59 Def000005
+S C$wt1curt.c$9$1$59 Def000007
+S A$wt1curt$1200 Def000015
+S A$wt1curt$1210 Def00001D
+S A$wt1curt$1201 Def000016
+S A$wt1curt$1202 Def000017
+S A$wt1curt$1203 Def000018
+S A$wt1curt$1213 Def00001F
+S A$wt1curt$1204 Def000019
+S A$wt1curt$1214 Def000021
+S A$wt1curt$1205 Def00001A
+S A$wt1curt$1215 Def000023
+S A$wt1curt$1206 Def00001B
+S A$wt1curt$1216 Def000025
+S A$wt1curt$1190 Def000007
+S A$wt1curt$1209 Def00001C
+S A$wt1curt$1191 Def000009
+S A$wt1curt$1182 Def000000
+S A$wt1curt$1219 Def000026
+S A$wt1curt$1192 Def00000C
+S A$wt1curt$1183 Def000002
+S A$wt1curt$1184 Def000004
+S A$wt1curt$1195 Def00000E
+S A$wt1curt$1196 Def000011
+S A$wt1curt$1187 Def000005
+S G$wtimer1_curtime$0$0 Def000000
+S A$wt1curt$1197 Def000012
+S A$wt1curt$1198 Def000013
+S A$wt1curt$1199 Def000014
+S C$wt1curt.c$10$1$59 Def00000E
+S C$wt1curt.c$11$1$59 Def00001C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF C0 07 12 00 00 D0
+R 00 00 00 16 02 0D 00 77
+T 00 00 0D 07 90 00 08 E0 FB A3 E0 FC A3 E0 FD A3
+R 00 00 00 16 02 05 02 41
+T 00 00 1A E0 FE EF 42 A8 8B 82 8C 83 8D F0 EE 22
+R 00 00 00 16
+
+
+M:wt1curt
+F:G$wtimer1_curtime$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lwt1curt.wtimer1_curtime$r$1$59({4}SL:U),R,0,0,[r3,r4,r5,r6]
+S:Lwt1curt.wtimer1_curtime$iesave$1$59({1}SC:U),R,0,0,[r7]
+T:Fwt1curt$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1curt$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1curt$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1curt$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0rem
+
+;!FILE libmf/wt0rem.asm
+XH3
+H 1A areas 2F5 global symbols
+M wt0rem
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _wtimer0_removecb_core Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
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+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
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+S C$wt0rem.c$10$1$59 Def00000B
+S C$wt0rem.c$11$1$59 Def000020
+S C$wt0rem.c$12$1$59 Def000034
+S C$wt0rem.c$13$1$59 Def000037
+S C$wt0rem.c$14$1$59 Def000039
+S G$wtimer0_remove$0$0 Def000000
+S _wtimer0_remove Def000000
+S C$wt0rem.c$4$0$0 Def000000
+S C$wt0rem.c$8$1$59 Def000004
+S C$wt0rem.c$9$1$59 Def000009
+S XG$wtimer0_remove$0$0 Def000039
+S A$wt0rem$1200 Def000015
+S A$wt0rem$1210 Def000026
+S A$wt0rem$1201 Def000018
+S A$wt0rem$1220 Def000034
+S A$wt0rem$1211 Def000028
+S A$wt0rem$1202 Def00001A
+S A$wt0rem$1221 Def000035
+S A$wt0rem$1212 Def00002B
+S A$wt0rem$1203 Def00001C
+S A$wt0rem$1213 Def00002D
+S A$wt0rem$1204 Def00001E
+S A$wt0rem$1214 Def00002F
+S A$wt0rem$1224 Def000037
+S A$wt0rem$1215 Def000031
+S A$wt0rem$1216 Def000032
+S A$wt0rem$1207 Def000020
+S A$wt0rem$1217 Def000033
+S A$wt0rem$1208 Def000022
+S A$wt0rem$1227 Def000039
+S A$wt0rem$1209 Def000024
+S A$wt0rem$1192 Def000009
+S A$wt0rem$1183 Def000000
+S A$wt0rem$1184 Def000002
+S A$wt0rem$1195 Def00000B
+S A$wt0rem$1196 Def00000D
+S A$wt0rem$1187 Def000004
+S A$wt0rem$1197 Def00000F
+S A$wt0rem$1188 Def000006
+S A$wt0rem$1198 Def000011
+S A$wt0rem$1189 Def000008
+S A$wt0rem$1199 Def000013
+A CONST size 0 flags 20 addr 0
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+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF 8E 82
+R 00 00 00 16
+T 00 00 0D 8F 83 C0 07 C0 06 C0 05 12 00 00 AC 82
+R 00 00 00 16 02 0C 02 00
+T 00 00 1A D0 05 D0 06 D0 07 8E 82 8F 83 C0 05 C0
+R 00 00 00 16
+T 00 00 27 04 12 00 00 AF 82 D0 04 D0 05 EF 2C FC
+R 00 00 00 16 02 05 01 5C
+T 00 00 34 ED 42 A8 8C 82 22
+R 00 00 00 16
+
+
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+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
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+S:G$INTCHGB$0$0({1}SC:U),F,0,0
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+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
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+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
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+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
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+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
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+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
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+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
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+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
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+S:G$ACC_7$0$0({1}SX:U),J,0,0
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+S:G$E2IE_0$0$0({1}SX:U),J,0,0
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+S:G$E2IE_5$0$0({1}SX:U),J,0,0
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+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
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+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
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+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1rem
+
+;!FILE libmf/wt1rem.asm
+XH3
+H 1A areas 2F5 global symbols
+M wt1rem
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _wtimer1_removecb_core Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
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+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
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+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
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+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
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+S G$ADCCH3VAL$0$0 Def007026
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+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
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+S _WTEVTC Def00FDFC
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+S _IE_0 Def0000A8
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+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
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+A XSEG size 0 flags 40 addr 0
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+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3A flags 20 addr 0
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+S C$wt1rem.c$11$1$59 Def000020
+S C$wt1rem.c$12$1$59 Def000034
+S C$wt1rem.c$13$1$59 Def000037
+S C$wt1rem.c$14$1$59 Def000039
+S G$wtimer1_remove$0$0 Def000000
+S _wtimer1_remove Def000000
+S C$wt1rem.c$4$0$0 Def000000
+S C$wt1rem.c$8$1$59 Def000004
+S C$wt1rem.c$9$1$59 Def000009
+S XG$wtimer1_remove$0$0 Def000039
+S A$wt1rem$1200 Def000015
+S A$wt1rem$1210 Def000026
+S A$wt1rem$1201 Def000018
+S A$wt1rem$1220 Def000034
+S A$wt1rem$1211 Def000028
+S A$wt1rem$1202 Def00001A
+S A$wt1rem$1221 Def000035
+S A$wt1rem$1212 Def00002B
+S A$wt1rem$1203 Def00001C
+S A$wt1rem$1213 Def00002D
+S A$wt1rem$1204 Def00001E
+S A$wt1rem$1214 Def00002F
+S A$wt1rem$1224 Def000037
+S A$wt1rem$1215 Def000031
+S A$wt1rem$1216 Def000032
+S A$wt1rem$1207 Def000020
+S A$wt1rem$1217 Def000033
+S A$wt1rem$1208 Def000022
+S A$wt1rem$1227 Def000039
+S A$wt1rem$1209 Def000024
+S A$wt1rem$1192 Def000009
+S A$wt1rem$1183 Def000000
+S A$wt1rem$1184 Def000002
+S A$wt1rem$1195 Def00000B
+S A$wt1rem$1196 Def00000D
+S A$wt1rem$1187 Def000004
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+S A$wt1rem$1188 Def000006
+S A$wt1rem$1198 Def000011
+S A$wt1rem$1189 Def000008
+S A$wt1rem$1199 Def000013
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+T 00 00 34 ED 42 A8 8C 82 22
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+
+
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+S:Lwt1rem.wtimer1_remove$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt1rem.wtimer1_remove$d$1$59({2}DX,STwtimer_desc:S),B,1,3
+S:Lwt1rem.wtimer1_remove$ret$1$59({1}SC:U),R,0,0,[r4]
+S:Lwt1rem.wtimer1_remove$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt1rem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
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+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt01rem
+
+;!FILE libmf/wt01rem.asm
+XH3
+H 1A areas 306 global symbols
+M wt01rem
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
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+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
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+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
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+S G$FRCOSCREF1$0$0 Def007075
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+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
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+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
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+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _wtimer1_removecb_core Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
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+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
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+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
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+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
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+S _T2CLKSRC Def0000AA
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+S G$RS0$0$0 Def0000D3
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+S G$B_4$0$0 Def0000F4
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+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
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+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
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+S G$ACC_0$0$0 Def0000E0
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+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
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+S G$ACC_1$0$0 Def0000E1
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+S G$ADCCH1VAL1$0$0 Def007023
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+S G$PORTA_3$0$0 Def000083
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+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
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+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
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+S G$RADIOFDATAADDR1$0$0 Def007041
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+S G$ACC_5$0$0 Def0000E5
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+S G$T2CNT0$0$0 Def0000AC
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+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
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+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
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+S G$DMA0ADDR$0$0 Def007010
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+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
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+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
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+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
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+S _wtimer_removecb_core Ref000000
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+S G$EIE_4$0$0 Def00009C
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+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
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+S G$ADCCH1VAL$0$0 Def007022
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+S G$WTSTAT$0$0 Def0000EA
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+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
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+S _RADIOSTAT0 Def0000BE
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+S _WTEVTA Def00F5F4
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+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+radiord16
+
+;!FILE libmf/radiord16.asm
+XH3
+H 1A areas 2E1 global symbols
+M radiord16
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 23 flags 20 addr 0
+S G$radio_read16$0$0 Def000000
+S C$radiord16.c$7$0$0 Def000000
+S _radio_read16 Def000000
+S XG$radio_read16$0$0 Def000023
+S A$radiord16$1180 Def00000B
+S A$radiord16$1190 Def000020
+S A$radiord16$1181 Def00000D
+S A$radiord16$1191 Def000022
+S A$radiord16$1182 Def00000F
+S A$radiord16$1183 Def000011
+S A$radiord16$1174 Def000000
+S A$radiord16$1184 Def000013
+S A$radiord16$1175 Def000002
+S A$radiord16$1185 Def000015
+S A$radiord16$1176 Def000004
+S A$radiord16$1186 Def000017
+S A$radiord16$1177 Def000006
+S A$radiord16$1187 Def000018
+S A$radiord16$1178 Def000008
+S A$radiord16$1188 Def00001B
+S A$radiord16$1179 Def00000A
+S A$radiord16$1189 Def00001D
+S C$radiord16.c$30$1$64 Def000023
+S C$radiord16.c$29$1$64 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 01 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 F5 83 85 B5 82 92 AF 22
+R 00 00 00 16
+
+
+M:radiord16
+F:G$radio_read16$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lradiord16.radio_read16$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
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+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
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+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
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+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
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+S:G$E2IP_3$0$0({1}SX:U),J,0,0
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+S:G$E2IP_5$0$0({1}SX:U),J,0,0
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+S:G$E2IP_7$0$0({1}SX:U),J,0,0
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+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
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+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiord24
+
+;!FILE libmf/radiord24.asm
+XH3
+H 1A areas 2E3 global symbols
+M radiord24
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S G$radio_read24$0$0 Def000000
+S C$radiord24.c$7$0$0 Def000000
+S _radio_read24 Def000000
+S XG$radio_read24$0$0 Def000027
+S A$radiord24$1180 Def00000B
+S A$radiord24$1190 Def000020
+S A$radiord24$1181 Def00000D
+S A$radiord24$1191 Def000023
+S A$radiord24$1182 Def00000F
+S A$radiord24$1192 Def000025
+S A$radiord24$1183 Def000011
+S A$radiord24$1174 Def000000
+S A$radiord24$1193 Def000026
+S A$radiord24$1184 Def000013
+S A$radiord24$1175 Def000002
+S A$radiord24$1185 Def000015
+S A$radiord24$1176 Def000004
+S A$radiord24$1186 Def000017
+S A$radiord24$1177 Def000006
+S A$radiord24$1187 Def000018
+S A$radiord24$1178 Def000008
+S A$radiord24$1188 Def00001B
+S A$radiord24$1179 Def00000A
+S A$radiord24$1189 Def00001D
+S C$radiord24.c$31$1$64 Def000000
+S C$radiord24.c$32$1$64 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 02 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 F5 F0 85 B5 83 85 B6 82 92 AF E4 22
+R 00 00 00 16
+
+
+M:radiord24
+F:G$radio_read24$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lradiord24.radio_read24$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
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+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiord32
+
+;!FILE libmf/radiord32.asm
+XH3
+H 1A areas 2E2 global symbols
+M radiord32
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S G$radio_read32$0$0 Def000000
+S C$radiord32.c$7$0$0 Def000000
+S _radio_read32 Def000000
+S XG$radio_read32$0$0 Def000027
+S A$radiord32$1180 Def00000B
+S A$radiord32$1190 Def000021
+S A$radiord32$1181 Def00000D
+S A$radiord32$1191 Def000024
+S A$radiord32$1182 Def00000F
+S A$radiord32$1192 Def000026
+S A$radiord32$1183 Def000011
+S A$radiord32$1174 Def000000
+S A$radiord32$1184 Def000013
+S A$radiord32$1175 Def000002
+S A$radiord32$1185 Def000015
+S A$radiord32$1176 Def000004
+S A$radiord32$1186 Def000017
+S A$radiord32$1177 Def000006
+S A$radiord32$1187 Def000018
+S A$radiord32$1178 Def000008
+S A$radiord32$1188 Def00001B
+S A$radiord32$1179 Def00000A
+S A$radiord32$1189 Def00001E
+S C$radiord32.c$30$1$64 Def000000
+S C$radiord32.c$31$1$64 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 03 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 85 B5 F0 85 B6 83 85 B7 82 92 AF 22
+R 00 00 00 16
+
+
+M:radiord32
+F:G$radio_read32$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lradiord32.radio_read32$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr16
+
+;!FILE libmf/radiowr16.asm
+XH3
+H 1A areas 2E7 global symbols
+M radiowr16
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2B flags 20 addr 0
+S C$radiowr16.c$45$1$64 Def000000
+S C$radiowr16.c$46$1$64 Def00002B
+S G$radio_write16$0$0 Def000000
+S C$radiowr16.c$7$0$0 Def000000
+S _radio_write16 Def000000
+S A$radiowr16$1200 Def000020
+S XG$radio_write16$0$0 Def00002B
+S A$radiowr16$1201 Def000021
+S A$radiowr16$1202 Def000022
+S A$radiowr16$1203 Def000023
+S A$radiowr16$1204 Def000026
+S A$radiowr16$1205 Def000028
+S A$radiowr16$1206 Def00002A
+S A$radiowr16$1190 Def00000E
+S A$radiowr16$1191 Def00000F
+S A$radiowr16$1192 Def000011
+S A$radiowr16$1183 Def000000
+S A$radiowr16$1193 Def000012
+S A$radiowr16$1184 Def000002
+S A$radiowr16$1194 Def000014
+S A$radiowr16$1185 Def000004
+S A$radiowr16$1195 Def000016
+S A$radiowr16$1186 Def000006
+S A$radiowr16$1196 Def000018
+S A$radiowr16$1187 Def000008
+S A$radiowr16$1197 Def00001A
+S A$radiowr16$1188 Def00000A
+S A$radiowr16$1198 Def00001C
+S A$radiowr16$1189 Def00000C
+S A$radiowr16$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FD C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B5 08 E6 F0 85 F0 B1 92
+R 00 00 00 16
+T 00 00 27 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr16
+F:G$radio_write16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lradiowr16.radio_write16$d$1$63({2}SI:U),B,1,-4
+S:Lradiowr16.radio_write16$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr24
+
+;!FILE libmf/radiowr24.asm
+XH3
+H 1A areas 2E9 global symbols
+M radiowr24
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2E flags 20 addr 0
+S C$radiowr24.c$47$1$64 Def000000
+S C$radiowr24.c$48$1$64 Def00002E
+S G$radio_write24$0$0 Def000000
+S C$radiowr24.c$7$0$0 Def000000
+S _radio_write24 Def000000
+S A$radiowr24$1200 Def000020
+S XG$radio_write24$0$0 Def00002E
+S A$radiowr24$1201 Def000021
+S A$radiowr24$1202 Def000023
+S A$radiowr24$1203 Def000024
+S A$radiowr24$1204 Def000025
+S A$radiowr24$1205 Def000026
+S A$radiowr24$1206 Def000029
+S A$radiowr24$1207 Def00002B
+S A$radiowr24$1208 Def00002D
+S A$radiowr24$1190 Def00000E
+S A$radiowr24$1191 Def00000F
+S A$radiowr24$1192 Def000011
+S A$radiowr24$1183 Def000000
+S A$radiowr24$1193 Def000012
+S A$radiowr24$1184 Def000002
+S A$radiowr24$1194 Def000014
+S A$radiowr24$1185 Def000004
+S A$radiowr24$1195 Def000016
+S A$radiowr24$1186 Def000006
+S A$radiowr24$1196 Def000018
+S A$radiowr24$1187 Def000008
+S A$radiowr24$1197 Def00001A
+S A$radiowr24$1188 Def00000A
+S A$radiowr24$1198 Def00001C
+S A$radiowr24$1189 Def00000C
+S A$radiowr24$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FB C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B6 08 86 B5 08 E6 F0 85
+R 00 00 00 16
+T 00 00 27 F0 B1 92 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr24
+F:G$radio_write24$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lradiowr24.radio_write24$d$1$63({4}SL:U),B,1,-6
+S:Lradiowr24.radio_write24$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr32
+
+;!FILE libmf/radiowr32.asm
+XH3
+H 1A areas 2EB global symbols
+M radiowr32
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 31 flags 20 addr 0
+S C$radiowr32.c$50$1$64 Def000031
+S C$radiowr32.c$49$1$64 Def000000
+S G$radio_write32$0$0 Def000000
+S C$radiowr32.c$7$0$0 Def000000
+S _radio_write32 Def000000
+S A$radiowr32$1200 Def000020
+S XG$radio_write32$0$0 Def000031
+S A$radiowr32$1210 Def000030
+S A$radiowr32$1201 Def000021
+S A$radiowr32$1202 Def000023
+S A$radiowr32$1203 Def000024
+S A$radiowr32$1204 Def000026
+S A$radiowr32$1205 Def000027
+S A$radiowr32$1206 Def000028
+S A$radiowr32$1207 Def000029
+S A$radiowr32$1208 Def00002C
+S A$radiowr32$1190 Def00000E
+S A$radiowr32$1209 Def00002E
+S A$radiowr32$1191 Def00000F
+S A$radiowr32$1192 Def000011
+S A$radiowr32$1183 Def000000
+S A$radiowr32$1193 Def000012
+S A$radiowr32$1184 Def000002
+S A$radiowr32$1194 Def000014
+S A$radiowr32$1185 Def000004
+S A$radiowr32$1195 Def000016
+S A$radiowr32$1186 Def000006
+S A$radiowr32$1196 Def000018
+S A$radiowr32$1187 Def000008
+S A$radiowr32$1197 Def00001A
+S A$radiowr32$1188 Def00000A
+S A$radiowr32$1198 Def00001C
+S A$radiowr32$1189 Def00000C
+S A$radiowr32$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FB C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B7 08 86 B6 08 86 B5 08
+R 00 00 00 16
+T 00 00 27 E6 F0 85 F0 B1 92 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr32
+F:G$radio_write32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lradiowr32.radio_write32$d$1$63({4}SL:U),B,1,-6
+S:Lradiowr32.radio_write32$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiodswakecore
+
+;!FILE libmf/radiodswakecore.asm
+XH3
+H 1A areas 86D global symbols
+M radiodswakecore
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 32 flags 20 addr 0
+S XG$radio_wakeup_deepsleep_core$0$0 Def000031
+S A$radiodswakecore$3301 Def000015
+S A$radiodswakecore$3311 Def00001C
+S A$radiodswakecore$3330 Def000029
+S A$radiodswakecore$3321 Def000024
+S A$radiodswakecore$3312 Def00001D
+S A$radiodswakecore$3331 Def00002C
+S A$radiodswakecore$3313 Def00001E
+S A$radiodswakecore$3304 Def000017
+S A$radiodswakecore$3332 Def00002E
+S A$radiodswakecore$3314 Def00001F
+S A$radiodswakecore$3315 Def000020
+S A$radiodswakecore$3335 Def00002F
+S A$radiodswakecore$3308 Def000019
+S A$radiodswakecore$3281 Def000002
+S A$radiodswakecore$3327 Def000026
+S A$radiodswakecore$3318 Def000022
+S A$radiodswakecore$3291 Def00000A
+S C$radiodswakecore.c$10$1$30 Def000005
+S A$radiodswakecore$3338 Def000031
+S A$radiodswakecore$3284 Def000005
+S A$radiodswakecore$3294 Def00000D
+S C$radiodswakecore.c$21$1$30 Def000022
+S C$radiodswakecore.c$22$1$30 Def000024
+S C$radiodswakecore.c$20$2$31 Def00001C
+S A$radiodswakecore$3278 Def000000
+S C$radiodswakecore.c$23$1$30 Def000026
+S A$radiodswakecore$3297 Def000010
+S A$radiodswakecore$3288 Def000007
+S C$radiodswakecore.c$24$1$30 Def000026
+S A$radiodswakecore$3298 Def000012
+S C$radiodswakecore.c$25$1$30 Def000029
+S C$radiodswakecore.c$12$3$32 Def000007
+S C$radiodswakecore.c$26$1$30 Def00002F
+S C$radiodswakecore.c$13$3$32 Def00000A
+S C$radiodswakecore.c$27$1$30 Def000031
+S C$radiodswakecore.c$14$3$32 Def00000D
+S C$radiodswakecore.c$15$3$32 Def000010
+S C$radiodswakecore.c$16$4$33 Def000015
+S C$radiodswakecore.c$19$3$32 Def000019
+S C$radiodswakecore.c$17$4$33 Def000017
+S C$radiodswakecore.c$8$1$30 Def000002
+S G$radio_wakeup_deepsleep_core$0$0 Def000000
+S C$radiodswakecore.c$5$0$0 Def000000
+S C$radiodswakecore.c$7$1$0 Def000000
+S _radio_wakeup_deepsleep_core Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 7F 00 53 8C F7 7E 03
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 43 8E 08 53 8E F7 53 8C FE E5 8D 30 E3
+R 00 00 00 16
+T 00 00 14 04 7D 00 80 0D
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 43 8C 01 EF 14 FC FF 70 E5 DE E3 7D 04
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 43 8C 09 90 70 44 74 47 F0 8D 82 22
+R 00 00 00 16
+
+
+M:radiodswakecore
+F:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lradiodswakecore.radio_wakeup_deepsleep_core$i$1$30({1}SC:U),R,0,0,[r5]
+S:Lradiodswakecore.radio_wakeup_deepsleep_core$j$1$30({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSEL$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_REF$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCE$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLY$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCMINMAX0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCMINMAX2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AMPLITUDEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AMPLITUDEGAIN3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBOFFSRES3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQDEV01$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
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+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031comminit
+
+;!FILE libmf/ax5031comminit.asm
+XH3
+H 1A areas 3A7 global symbols
+M ax5031comminit
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S _ax5031_comminit Def000000
+S XG$ax5031_comminit$0$0 Def000026
+S A$ax5031comminit$1460 Def000000
+S A$ax5031comminit$1471 Def00000C
+S A$ax5031comminit$1490 Def000021
+S A$ax5031comminit$1463 Def000003
+S A$ax5031comminit$1491 Def000024
+S A$ax5031comminit$1482 Def000018
+S A$ax5031comminit$1492 Def000025
+S A$ax5031comminit$1483 Def00001B
+S A$ax5031comminit$1474 Def00000F
+S A$ax5031comminit$1484 Def00001D
+S A$ax5031comminit$1475 Def000012
+S A$ax5031comminit$1466 Def000006
+S A$ax5031comminit$1485 Def00001E
+S A$ax5031comminit$1476 Def000014
+S A$ax5031comminit$1467 Def000009
+S A$ax5031comminit$1495 Def000026
+S A$ax5031comminit$1486 Def00001F
+S A$ax5031comminit$1477 Def000015
+S A$ax5031comminit$1468 Def00000B
+S A$ax5031comminit$1487 Def000020
+S A$ax5031comminit$1478 Def000016
+S A$ax5031comminit$1479 Def000017
+S C$ax5031comminit.c$10$1$66 Def000000
+S C$ax5031comminit.c$11$1$66 Def000003
+S C$ax5031comminit.c$12$1$66 Def000006
+S C$ax5031comminit.c$13$1$66 Def00000C
+S C$ax5031comminit.c$23$1$66 Def000021
+S C$ax5031comminit.c$24$1$66 Def000026
+S C$ax5031comminit.c$15$1$66 Def00000F
+S C$ax5031comminit.c$16$1$66 Def000018
+S G$ax5031_comminit$0$0 Def000000
+S C$ax5031comminit.c$8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 40 74 05 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 26 22
+R 00 00 00 16
+
+
+M:ax5031comminit
+F:G$ax5031_comminit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
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+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031commslpexit
+
+;!FILE libmf/ax5031commslpexit.asm
+XH3
+H 1A areas 3A9 global symbols
+M ax5031commslpexit
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S _ax5031_probeirq Ref000000
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5031commslpexit.c$8$0$0 Def000000
+S G$ax5031_commsleepexit$0$0 Def000000
+S _ax5031_commsleepexit Def000000
+S XG$ax5031_commsleepexit$0$0 Def000027
+S A$ax5031commslpexit$1470 Def00000B
+S A$ax5031commslpexit$1461 Def000000
+S A$ax5031commslpexit$1480 Def000017
+S A$ax5031commslpexit$1471 Def00000D
+S A$ax5031commslpexit$1490 Def000022
+S A$ax5031commslpexit$1481 Def000018
+S A$ax5031commslpexit$1472 Def00000E
+S A$ax5031commslpexit$1491 Def000023
+S A$ax5031commslpexit$1482 Def000019
+S A$ax5031commslpexit$1464 Def000003
+S A$ax5031commslpexit$1483 Def00001A
+S A$ax5031commslpexit$1475 Def00000F
+S A$ax5031commslpexit$1494 Def000024
+S A$ax5031commslpexit$1467 Def000006
+S A$ax5031commslpexit$1486 Def00001B
+S A$ax5031commslpexit$1468 Def000009
+S A$ax5031commslpexit$1487 Def00001E
+S A$ax5031commslpexit$1478 Def000012
+S A$ax5031commslpexit$1469 Def00000A
+S A$ax5031commslpexit$1497 Def000027
+S A$ax5031commslpexit$1488 Def000020
+S A$ax5031commslpexit$1479 Def000015
+S A$ax5031commslpexit$1489 Def000021
+S C$ax5031commslpexit.c$10$1$66 Def000000
+S C$ax5031commslpexit.c$11$1$66 Def000003
+S C$ax5031commslpexit.c$12$1$66 Def000006
+S C$ax5031commslpexit.c$13$1$66 Def00000F
+S C$ax5031commslpexit.c$24$1$66 Def000024
+S C$ax5031commslpexit.c$15$1$66 Def000012
+S C$ax5031commslpexit.c$25$1$66 Def000027
+S C$ax5031commslpexit.c$16$1$66 Def00001B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
+R 00 00 00 16
+T 00 00 0D 4F F0 75 B1 00 90 70 40 74 05 F0 E4 A3
+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 04 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 47
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5031commslpexit
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+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
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+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031reset
+
+;!FILE libmf/ax5031reset.asm
+XH3
+H 1A areas 436 global symbols
+M ax5031reset
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S _delay Ref000000
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size DF flags 20 addr 0
+S C$ax5031reset.c$8$0$0 Def000000
+S _ax5031_reset Def000000
+S _ax5031_probeirq Def000079
+S XG$ax5031_reset$0$0 Def000078
+S XG$ax5031_probeirq$0$0 Def0000DE
+S A$ax5031reset$1500 Def00002A
+S A$ax5031reset$1501 Def00002C
+S A$ax5031reset$1700 Def0000D9
+S A$ax5031reset$1610 Def000088
+S A$ax5031reset$1601 Def000081
+S A$ax5031reset$1520 Def00003B
+S A$ax5031reset$1620 Def000093
+S A$ax5031reset$1611 Def00008B
+S A$ax5031reset$1530 Def000045
+S A$ax5031reset$1521 Def00003E
+S A$ax5031reset$1512 Def000035
+S A$ax5031reset$1630 Def00009D
+S A$ax5031reset$1621 Def000095
+S A$ax5031reset$1612 Def00008C
+S A$ax5031reset$1531 Def000048
+S A$ax5031reset$1513 Def000038
+S A$ax5031reset$1504 Def00002D
+S A$ax5031reset$1703 Def0000DB
+S A$ax5031reset$1640 Def0000A6
+S A$ax5031reset$1631 Def00009E
+S A$ax5031reset$1622 Def000097
+S A$ax5031reset$1604 Def000083
+S A$ax5031reset$1532 Def00004A
+S A$ax5031reset$1505 Def00002E
+S A$ax5031reset$1650 Def0000B0
+S A$ax5031reset$1641 Def0000A9
+S A$ax5031reset$1632 Def00009F
+S A$ax5031reset$1560 Def000067
+S A$ax5031reset$1542 Def000052
+S A$ax5031reset$1470 Def000006
+S A$ax5031reset$1660 Def0000B9
+S A$ax5031reset$1651 Def0000B3
+S A$ax5031reset$1615 Def00008D
+S A$ax5031reset$1570 Def000073
+S A$ax5031reset$1552 Def00005D
+S A$ax5031reset$1543 Def000055
+S A$ax5031reset$1525 Def000040
+S A$ax5031reset$1516 Def000039
+S A$ax5031reset$1480 Def000014
+S A$ax5031reset$1471 Def000009
+S A$ax5031reset$1652 Def0000B4
+S A$ax5031reset$1625 Def000098
+S A$ax5031reset$1616 Def000090
+S A$ax5031reset$1607 Def000085
+S A$ax5031reset$1553 Def00005E
+S A$ax5031reset$1535 Def00004B
+S A$ax5031reset$1526 Def000043
+S A$ax5031reset$1517 Def00003A
+S A$ax5031reset$1508 Def00002F
+S A$ax5031reset$1472 Def00000B
+S A$ax5031reset$1707 Def0000DE
+S A$ax5031reset$1680 Def0000CB
+S A$ax5031reset$1653 Def0000B5
+S A$ax5031reset$1635 Def0000A1
+S A$ax5031reset$1626 Def00009A
+S A$ax5031reset$1617 Def000092
+S A$ax5031reset$1554 Def00005F
+S A$ax5031reset$1536 Def00004C
+S A$ax5031reset$1509 Def000032
+S A$ax5031reset$1491 Def00001E
+S A$ax5031reset$1464 Def000000
+S A$ax5031reset$1690 Def0000D2
+S A$ax5031reset$1681 Def0000CC
+S A$ax5031reset$1654 Def0000B7
+S A$ax5031reset$1645 Def0000AB
+S A$ax5031reset$1636 Def0000A4
+S A$ax5031reset$1564 Def000069
+S A$ax5031reset$1555 Def000062
+S A$ax5031reset$1537 Def00004D
+S A$ax5031reset$1492 Def000021
+S A$ax5031reset$1483 Def000015
+S A$ax5031reset$1664 Def0000BB
+S A$ax5031reset$1655 Def0000B8
+S A$ax5031reset$1646 Def0000AE
+S A$ax5031reset$1637 Def0000A5
+S A$ax5031reset$1574 Def000075
+S A$ax5031reset$1565 Def00006C
+S A$ax5031reset$1547 Def000057
+S A$ax5031reset$1538 Def000050
+S A$ax5031reset$1493 Def000023
+S A$ax5031reset$1484 Def000018
+S A$ax5031reset$1475 Def00000C
+S A$ax5031reset$1674 Def0000C4
+S A$ax5031reset$1665 Def0000BE
+S A$ax5031reset$1629 Def00009B
+S A$ax5031reset$1566 Def00006E
+S A$ax5031reset$1548 Def00005A
+S A$ax5031reset$1494 Def000024
+S A$ax5031reset$1485 Def00001A
+S A$ax5031reset$1467 Def000003
+S A$ax5031reset$1684 Def0000CD
+S A$ax5031reset$1666 Def0000BF
+S A$ax5031reset$1549 Def00005C
+S A$ax5031reset$1495 Def000025
+S A$ax5031reset$1486 Def00001B
+S A$ax5031reset$1694 Def0000D4
+S A$ax5031reset$1667 Def0000C0
+S A$ax5031reset$1595 Def000079
+S A$ax5031reset$1559 Def000064
+S A$ax5031reset$1496 Def000026
+S A$ax5031reset$1487 Def00001C
+S A$ax5031reset$1478 Def00000F
+S A$ax5031reset$1695 Def0000D5
+S A$ax5031reset$1668 Def0000C2
+S A$ax5031reset$1596 Def00007C
+S A$ax5031reset$1578 Def000078
+S A$ax5031reset$1569 Def000070
+S A$ax5031reset$1488 Def00001D
+S A$ax5031reset$1479 Def000012
+S A$ax5031reset$1696 Def0000D6
+S A$ax5031reset$1687 Def0000CF
+S A$ax5031reset$1678 Def0000C6
+S A$ax5031reset$1669 Def0000C3
+S A$ax5031reset$1597 Def00007D
+S A$ax5031reset$1697 Def0000D7
+S A$ax5031reset$1679 Def0000C9
+S A$ax5031reset$1598 Def00007E
+S A$ax5031reset$1499 Def000027
+S C$ax5031reset.c$20$1$66 Def00000F
+S C$ax5031reset.c$12$1$66 Def000000
+S C$ax5031reset.c$22$1$66 Def000015
+S C$ax5031reset.c$13$1$66 Def000003
+S C$ax5031reset.c$23$1$66 Def00001E
+S C$ax5031reset.c$60$1$66 Def000075
+S C$ax5031reset.c$51$1$66 Def000045
+S C$ax5031reset.c$42$1$66 Def000035
+S C$ax5031reset.c$61$1$66 Def000078
+S C$ax5031reset.c$52$1$66 Def00004B
+S C$ax5031reset.c$43$1$66 Def000039
+S C$ax5031reset.c$53$1$66 Def000052
+S C$ax5031reset.c$35$1$66 Def000027
+S C$ax5031reset.c$17$1$66 Def000006
+S C$ax5031reset.c$70$1$68 Def000085
+S C$ax5031reset.c$54$1$66 Def000057
+S C$ax5031reset.c$36$1$66 Def00002D
+S C$ax5031reset.c$71$1$68 Def000088
+S C$ax5031reset.c$64$1$66 Def000079
+S C$ax5031reset.c$55$1$66 Def00005D
+S C$ax5031reset.c$19$1$66 Def00000C
+S C$ax5031reset.c$72$1$68 Def00008D
+S C$ax5031reset.c$56$1$66 Def000064
+S C$ax5031reset.c$91$1$68 Def0000D2
+S C$ax5031reset.c$80$2$69 Def0000B9
+S C$ax5031reset.c$73$1$68 Def000093
+S C$ax5031reset.c$48$1$66 Def00003B
+S C$ax5031reset.c$39$1$66 Def00002F
+S C$ax5031reset.c$92$1$68 Def0000D4
+S C$ax5031reset.c$90$2$69 Def0000CF
+S C$ax5031reset.c$74$1$68 Def000098
+S C$ax5031reset.c$58$1$66 Def000069
+S C$ax5031reset.c$49$1$66 Def000040
+S C$ax5031reset.c$93$1$68 Def0000D9
+S C$ax5031reset.c$82$2$69 Def0000B9
+S C$ax5031reset.c$75$1$68 Def00009B
+S C$ax5031reset.c$59$1$66 Def000070
+S C$ax5031reset.c$94$1$68 Def0000DB
+S C$ax5031reset.c$83$2$69 Def0000BB
+S C$ax5031reset.c$76$1$68 Def0000A1
+S C$ax5031reset.c$67$1$68 Def000079
+S C$ax5031reset.c$95$1$68 Def0000DE
+S C$ax5031reset.c$84$2$69 Def0000C4
+S C$ax5031reset.c$77$1$68 Def0000A6
+S C$ax5031reset.c$68$1$68 Def000081
+S C$ax5031reset.c$69$1$68 Def000083
+S G$ax5031_reset$0$0 Def000000
+S C$ax5031reset.c$86$2$69 Def0000C4
+S G$ax5031_probeirq$0$0 Def000079
+S C$ax5031reset.c$78$2$69 Def0000AB
+S C$ax5031reset.c$88$2$69 Def0000C6
+S C$ax5031reset.c$79$2$69 Def0000B0
+S C$ax5031reset.c$89$2$69 Def0000CD
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 00 0A 12
+R 00 00 00 16
+T 00 00 33 00 00 90 40 00 E0 E0 FF BF 21 02 80 05
+R 00 00 00 16 02 03 02 70
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 75 82 01 80 33
+R 00 00 00 16
+T 00 00 45
+R 00 00 00 16
+T 00 00 45 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 75 82 02 80 21
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 75 82 02 80 0F
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 12 00 79 E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 04 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 75 82 00
+R 00 00 00 16
+T 00 00 78
+R 00 00 00 16
+T 00 00 78 22
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 86 8C EB 90 40 0C EF F0 90 40 0D 74 22 F0
+R 00 00 00 16
+T 00 00 93 74 60 55 8D FD 74 20 F0 E5 8D F4 FC 52
+R 00 00 00 16
+T 00 00 A0 05 90 40 0D E4 F0 BD 20 02 80 05
+R 00 00 00 16
+T 00 00 AB
+R 00 00 00 16
+T 00 00 AB BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 B0
+R 00 00 00 16
+T 00 00 B0 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 C6
+R 00 00 00 16
+T 00 00 C6 90 40 0C 74 20 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 D3 0A
+R 00 00 00 16
+T 00 00 D4
+R 00 00 00 16
+T 00 00 D4 ED F4 FD 52 8C 8E A8 75 82 00
+R 00 00 00 16
+T 00 00 DE
+R 00 00 00 16
+T 00 00 DE 22
+R 00 00 00 16
+
+
+M:ax5031reset
+F:G$ax5031_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5031reset.ax5031_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5031_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5031reset.ax5031_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5031reset.ax5031_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5031reset.ax5031_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031deepsleep
+
+XH3
+H 1A areas 385 global symbols
+M ax5031deepsleep
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5031deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031rclkena
+
+;!FILE libmf/ax5031rclkena.asm
+XH3
+H 1A areas 3B7 global symbols
+M ax5031rclkena
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3D flags 20 addr 0
+S G$ax5031_rclk_enable$0$0 Def000000
+S A$ax5031rclkena$1500 Def000025
+S A$ax5031rclkena$1501 Def000028
+S _ax5031_rclk_enable Def000000
+S A$ax5031rclkena$1520 Def00003A
+S A$ax5031rclkena$1511 Def000030
+S A$ax5031rclkena$1512 Def000032
+S A$ax5031rclkena$1513 Def000033
+S A$ax5031rclkena$1504 Def000029
+S A$ax5031rclkena$1523 Def00003C
+S A$ax5031rclkena$1514 Def000036
+S A$ax5031rclkena$1505 Def00002A
+S A$ax5031rclkena$1515 Def000038
+S A$ax5031rclkena$1506 Def00002C
+S A$ax5031rclkena$1470 Def000007
+S A$ax5031rclkena$1507 Def00002E
+S A$ax5031rclkena$1480 Def00000F
+S A$ax5031rclkena$1462 Def000000
+S A$ax5031rclkena$1490 Def000019
+S A$ax5031rclkena$1481 Def000011
+S A$ax5031rclkena$1491 Def00001C
+S A$ax5031rclkena$1519 Def000039
+S A$ax5031rclkena$1492 Def00001F
+S A$ax5031rclkena$1474 Def000009
+S A$ax5031rclkena$1465 Def000002
+S A$ax5031rclkena$1493 Def000020
+S A$ax5031rclkena$1484 Def000012
+S A$ax5031rclkena$1475 Def00000A
+S A$ax5031rclkena$1494 Def000021
+S A$ax5031rclkena$1476 Def00000C
+S A$ax5031rclkena$1467 Def000005
+S XG$ax5031_rclk_enable$0$0 Def00003C
+S A$ax5031rclkena$1487 Def000014
+S A$ax5031rclkena$1497 Def000022
+S A$ax5031rclkena$1488 Def000017
+S A$ax5031rclkena$1479 Def00000D
+S A$ax5031rclkena$1489 Def000018
+S C$ax5031rclkena.c$10$1$64 Def000009
+S C$ax5031rclkena.c$11$1$64 Def00000D
+S C$ax5031rclkena.c$12$1$64 Def000012
+S C$ax5031rclkena.c$13$1$64 Def000014
+S C$ax5031rclkena.c$14$1$64 Def000022
+S C$ax5031rclkena.c$15$1$64 Def000025
+S C$ax5031rclkena.c$16$1$64 Def000029
+S C$ax5031rclkena.c$17$1$64 Def000030
+S C$ax5031rclkena.c$18$1$64 Def000039
+S C$ax5031rclkena.c$19$1$64 Def00003C
+S C$ax5031rclkena.c$8$1$64 Def000002
+S C$ax5031rclkena.c$9$1$64 Def000007
+S C$ax5031rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 09
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031rclkena
+F:G$ax5031_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031rclkena.ax5031_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5031rclkena.ax5031_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5031rclkena.ax5031_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
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+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
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+S:G$T1CNT1$0$0({1}SC:U),I,0,0
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+S:G$WDTCFG$0$0({1}SC:U),I,0,0
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+S:G$WTSTAT$0$0({1}SC:U),I,0,0
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+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
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+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
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+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5031rclkdis
+
+;!FILE libmf/ax5031rclkdis.asm
+XH3
+H 1A areas 3AC global symbols
+M ax5031rclkdis
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S C$ax5031rclkdis.c$8$1$64 Def000000
+S C$ax5031rclkdis.c$9$1$64 Def000005
+S C$ax5031rclkdis.c$5$0$0 Def000000
+S XG$ax5031_rclk_disable$0$0 Def00002B
+S A$ax5031rclkdis$1501 Def000028
+S A$ax5031rclkdis$1502 Def000029
+S A$ax5031rclkdis$1505 Def00002B
+S A$ax5031rclkdis$1480 Def000014
+S A$ax5031rclkdis$1471 Def000007
+S A$ax5031rclkdis$1490 Def00001D
+S A$ax5031rclkdis$1463 Def000000
+S A$ax5031rclkdis$1491 Def00001E
+S A$ax5031rclkdis$1464 Def000002
+S A$ax5031rclkdis$1483 Def000015
+S A$ax5031rclkdis$1474 Def00000A
+S A$ax5031rclkdis$1465 Def000004
+S A$ax5031rclkdis$1484 Def000018
+S A$ax5031rclkdis$1475 Def00000D
+S A$ax5031rclkdis$1494 Def000021
+S A$ax5031rclkdis$1485 Def000019
+S A$ax5031rclkdis$1476 Def00000E
+S A$ax5031rclkdis$1495 Def000024
+S A$ax5031rclkdis$1477 Def00000F
+S A$ax5031rclkdis$1468 Def000005
+S A$ax5031rclkdis$1496 Def000026
+S A$ax5031rclkdis$1478 Def000011
+S A$ax5031rclkdis$1497 Def000027
+S A$ax5031rclkdis$1488 Def00001A
+S A$ax5031rclkdis$1479 Def000012
+S A$ax5031rclkdis$1489 Def00001C
+S C$ax5031rclkdis.c$10$1$64 Def000007
+S C$ax5031rclkdis.c$11$1$64 Def00000A
+S C$ax5031rclkdis.c$12$1$64 Def000015
+S C$ax5031rclkdis.c$13$1$64 Def00001A
+S C$ax5031rclkdis.c$14$1$64 Def000021
+S C$ax5031rclkdis.c$15$1$64 Def000028
+S G$ax5031_rclk_disable$0$0 Def000000
+S C$ax5031rclkdis.c$16$1$64 Def00002B
+S _ax5031_rclk_disable Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 74 0F 5E FD BD 05 07 90 40 02 74 F0 5E
+R 00 00 00 16
+T 00 00 27 F0
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031rclkdis
+F:G$ax5031_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031rclkdis.ax5031_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5031rclkdis.ax5031_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
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+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5031rdfifo
+
+;!FILE libmf/ax5031rdfifo.asm
+XH3
+H 1A areas 3BD global symbols
+M ax5031rdfifo
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S C$ax5031rdfifo.c$10$0$0 Def000000
+S C$ax5031rdfifo.c$74$1$66 Def000000
+S C$ax5031rdfifo.c$75$1$66 Def000054
+S G$ax5031_readfifo$0$0 Def000000
+S _ax5031_readfifo Def000000
+S A$ax5031rdfifo$1500 Def00003C
+S A$ax5031rdfifo$1510 Def00004B
+S A$ax5031rdfifo$1501 Def00003E
+S XG$ax5031_readfifo$0$0 Def000054
+S A$ax5031rdfifo$1511 Def00004C
+S A$ax5031rdfifo$1502 Def000040
+S A$ax5031rdfifo$1512 Def00004E
+S A$ax5031rdfifo$1503 Def000041
+S A$ax5031rdfifo$1513 Def000050
+S A$ax5031rdfifo$1504 Def000043
+S A$ax5031rdfifo$1514 Def000051
+S A$ax5031rdfifo$1505 Def000045
+S A$ax5031rdfifo$1460 Def000005
+S A$ax5031rdfifo$1515 Def000053
+S A$ax5031rdfifo$1506 Def000048
+S A$ax5031rdfifo$1470 Def000018
+S A$ax5031rdfifo$1461 Def000006
+S A$ax5031rdfifo$1480 Def000020
+S A$ax5031rdfifo$1471 Def000019
+S A$ax5031rdfifo$1462 Def000008
+S A$ax5031rdfifo$1508 Def00004A
+S A$ax5031rdfifo$1481 Def000022
+S A$ax5031rdfifo$1472 Def00001A
+S A$ax5031rdfifo$1463 Def000009
+S A$ax5031rdfifo$1491 Def000031
+S A$ax5031rdfifo$1464 Def00000C
+S A$ax5031rdfifo$1492 Def000032
+S A$ax5031rdfifo$1483 Def000023
+S A$ax5031rdfifo$1474 Def00001C
+S A$ax5031rdfifo$1465 Def00000F
+S A$ax5031rdfifo$1493 Def000033
+S A$ax5031rdfifo$1484 Def000025
+S A$ax5031rdfifo$1466 Def000011
+S A$ax5031rdfifo$1457 Def000000
+S A$ax5031rdfifo$1494 Def000034
+S A$ax5031rdfifo$1485 Def000027
+S A$ax5031rdfifo$1467 Def000014
+S A$ax5031rdfifo$1458 Def000002
+S A$ax5031rdfifo$1495 Def000036
+S A$ax5031rdfifo$1486 Def000028
+S A$ax5031rdfifo$1477 Def00001D
+S A$ax5031rdfifo$1459 Def000004
+S A$ax5031rdfifo$1496 Def000038
+S A$ax5031rdfifo$1487 Def00002A
+S A$ax5031rdfifo$1478 Def00001E
+S A$ax5031rdfifo$1469 Def000017
+S A$ax5031rdfifo$1497 Def000039
+S A$ax5031rdfifo$1488 Def00002C
+S A$ax5031rdfifo$1479 Def00001F
+S A$ax5031rdfifo$1498 Def00003B
+S A$ax5031rdfifo$1489 Def00002F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
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+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
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+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
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+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031wrfifo
+
+;!FILE libmf/ax5031wrfifo.asm
+XH3
+H 1A areas 3BF global symbols
+M ax5031wrfifo
+O -mmcs51 --model-small
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S A$ax5031wrfifo$1511 Def00004D
+S A$ax5031wrfifo$1502 Def000040
+S A$ax5031wrfifo$1512 Def00004E
+S A$ax5031wrfifo$1503 Def000041
+S A$ax5031wrfifo$1513 Def000050
+S A$ax5031wrfifo$1504 Def000043
+S A$ax5031wrfifo$1514 Def000052
+S A$ax5031wrfifo$1505 Def000045
+S A$ax5031wrfifo$1460 Def000005
+S A$ax5031wrfifo$1515 Def000053
+S A$ax5031wrfifo$1506 Def000048
+S A$ax5031wrfifo$1470 Def000018
+S A$ax5031wrfifo$1461 Def000006
+S A$ax5031wrfifo$1516 Def000055
+S A$ax5031wrfifo$1480 Def000020
+S A$ax5031wrfifo$1471 Def000019
+S A$ax5031wrfifo$1462 Def000008
+S A$ax5031wrfifo$1508 Def00004A
+S A$ax5031wrfifo$1481 Def000022
+S A$ax5031wrfifo$1472 Def00001A
+S A$ax5031wrfifo$1463 Def000009
+S A$ax5031wrfifo$1509 Def00004B
+S A$ax5031wrfifo$1491 Def000031
+S A$ax5031wrfifo$1464 Def00000C
+S A$ax5031wrfifo$1492 Def000032
+S A$ax5031wrfifo$1483 Def000023
+S A$ax5031wrfifo$1474 Def00001C
+S A$ax5031wrfifo$1465 Def00000F
+S A$ax5031wrfifo$1493 Def000033
+S A$ax5031wrfifo$1484 Def000025
+S A$ax5031wrfifo$1466 Def000011
+S A$ax5031wrfifo$1457 Def000000
+S A$ax5031wrfifo$1494 Def000034
+S A$ax5031wrfifo$1485 Def000027
+S A$ax5031wrfifo$1467 Def000014
+S A$ax5031wrfifo$1458 Def000002
+S A$ax5031wrfifo$1495 Def000036
+S A$ax5031wrfifo$1486 Def000028
+S A$ax5031wrfifo$1477 Def00001D
+S A$ax5031wrfifo$1459 Def000004
+S A$ax5031wrfifo$1496 Def000038
+S A$ax5031wrfifo$1487 Def00002A
+S A$ax5031wrfifo$1478 Def00001E
+S A$ax5031wrfifo$1469 Def000017
+S A$ax5031wrfifo$1497 Def000039
+S A$ax5031wrfifo$1488 Def00002C
+S A$ax5031wrfifo$1479 Def00001F
+S A$ax5031wrfifo$1498 Def00003B
+S A$ax5031wrfifo$1489 Def00002F
+S C$ax5031wrfifo.c$10$0$0 Def000000
+S C$ax5031wrfifo.c$75$1$66 Def000000
+S C$ax5031wrfifo.c$76$1$66 Def000056
+S G$ax5031_writefifo$0$0 Def000000
+S _ax5031_writefifo Def000000
+S XG$ax5031_writefifo$0$0 Def000056
+S A$ax5031wrfifo$1500 Def00003C
+S A$ax5031wrfifo$1510 Def00004C
+S A$ax5031wrfifo$1501 Def00003E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
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+T 00 00 00
+R 00 00 00 03
+T 00 00 00
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+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 17 E6 F0 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
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+T 00 00 1D E2 F0 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
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+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 05
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E0 F2 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 05
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E4 93 F2 A3 DF FA 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031wrfifo
+F:G$ax5031_writefifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031wrfifo.ax5031_writefifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5031wrfifo.ax5031_writefifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5031regs
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5031regs
+
+
+
+
+ax5042comminit
+
+;!FILE libmf/ax5042comminit.asm
+XH3
+H 1A areas 3FF global symbols
+M ax5042comminit
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
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+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
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+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
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+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
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+S C$ax5042comminit.c$15$1$66 Def00000F
+S C$ax5042comminit.c$16$1$66 Def000018
+S G$ax5042_comminit$0$0 Def000000
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+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
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+
+
+M:ax5042comminit
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+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042commslpexit
+
+;!FILE libmf/ax5042commslpexit.asm
+XH3
+H 1A areas 401 global symbols
+M ax5042commslpexit
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _ax5042_probeirq Ref000000
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5042commslpexit.c$24$1$66 Def000024
+S C$ax5042commslpexit.c$15$1$66 Def000012
+S C$ax5042commslpexit.c$25$1$66 Def000027
+S C$ax5042commslpexit.c$16$1$66 Def00001B
+S C$ax5042commslpexit.c$8$0$0 Def000000
+S G$ax5042_commsleepexit$0$0 Def000000
+S _ax5042_commsleepexit Def000000
+S A$ax5042commslpexit$1600 Def000009
+S A$ax5042commslpexit$1610 Def000012
+S A$ax5042commslpexit$1601 Def00000A
+S A$ax5042commslpexit$1620 Def000020
+S A$ax5042commslpexit$1611 Def000015
+S A$ax5042commslpexit$1602 Def00000B
+S A$ax5042commslpexit$1621 Def000021
+S A$ax5042commslpexit$1612 Def000017
+S A$ax5042commslpexit$1603 Def00000D
+S A$ax5042commslpexit$1622 Def000022
+S A$ax5042commslpexit$1613 Def000018
+S A$ax5042commslpexit$1604 Def00000E
+S XG$ax5042_commsleepexit$0$0 Def000027
+S A$ax5042commslpexit$1623 Def000023
+S A$ax5042commslpexit$1614 Def000019
+S A$ax5042commslpexit$1615 Def00001A
+S A$ax5042commslpexit$1607 Def00000F
+S A$ax5042commslpexit$1626 Def000024
+S A$ax5042commslpexit$1618 Def00001B
+S A$ax5042commslpexit$1619 Def00001E
+S A$ax5042commslpexit$1629 Def000027
+S A$ax5042commslpexit$1593 Def000000
+S A$ax5042commslpexit$1596 Def000003
+S A$ax5042commslpexit$1599 Def000006
+S C$ax5042commslpexit.c$10$1$66 Def000000
+S C$ax5042commslpexit.c$11$1$66 Def000003
+S C$ax5042commslpexit.c$12$1$66 Def000006
+S C$ax5042commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
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+T 00 00 00
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+T 00 00 00
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+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
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+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 04 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 5F
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5042commslpexit
+F:G$ax5042_commsleepexit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042reset
+
+;!FILE libmf/ax5042reset.asm
+XH3
+H 1A areas 49B global symbols
+M ax5042reset
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F3 flags 20 addr 0
+S C$ax5042reset.c$8$0$0 Def000000
+S _ax5042_reset Def000000
+S _ax5042_probeirq Def00008A
+S XG$ax5042_reset$0$0 Def000089
+S XG$ax5042_probeirq$0$0 Def0000F2
+S A$ax5042reset$1610 Def000012
+S A$ax5042reset$1601 Def000006
+S A$ax5042reset$1800 Def0000C8
+S A$ax5042reset$1701 Def00006E
+S A$ax5042reset$1611 Def000014
+S A$ax5042reset$1602 Def000009
+S A$ax5042reset$1801 Def0000C9
+S A$ax5042reset$1711 Def00007A
+S A$ax5042reset$1702 Def000071
+S A$ax5042reset$1630 Def000027
+S A$ax5042reset$1603 Def00000B
+S A$ax5042reset$1802 Def0000CB
+S A$ax5042reset$1721 Def000086
+S A$ax5042reset$1712 Def00007D
+S A$ax5042reset$1703 Def000073
+S A$ax5042reset$1640 Def000032
+S A$ax5042reset$1631 Def00002A
+S A$ax5042reset$1622 Def00001E
+S A$ax5042reset$1812 Def0000CF
+S A$ax5042reset$1803 Def0000CC
+S A$ax5042reset$1713 Def00007F
+S A$ax5042reset$1632 Def00002C
+S A$ax5042reset$1623 Def000021
+S A$ax5042reset$1614 Def000015
+S A$ax5042reset$1822 Def0000D8
+S A$ax5042reset$1813 Def0000D2
+S A$ax5042reset$1624 Def000023
+S A$ax5042reset$1615 Def000018
+S A$ax5042reset$1606 Def00000C
+S A$ax5042reset$1832 Def0000E1
+S A$ax5042reset$1814 Def0000D3
+S A$ax5042reset$1760 Def00009F
+S A$ax5042reset$1751 Def000094
+S A$ax5042reset$1742 Def00008A
+S A$ax5042reset$1706 Def000074
+S A$ax5042reset$1670 Def00004F
+S A$ax5042reset$1652 Def00003A
+S A$ax5042reset$1643 Def000033
+S A$ax5042reset$1625 Def000024
+S A$ax5042reset$1616 Def00001A
+S A$ax5042reset$1851 Def0000EF
+S A$ax5042reset$1842 Def0000E8
+S A$ax5042reset$1815 Def0000D4
+S A$ax5042reset$1770 Def0000AA
+S A$ax5042reset$1743 Def00008D
+S A$ax5042reset$1725 Def000089
+S A$ax5042reset$1716 Def000081
+S A$ax5042reset$1707 Def000077
+S A$ax5042reset$1680 Def000058
+S A$ax5042reset$1662 Def000045
+S A$ax5042reset$1653 Def00003D
+S A$ax5042reset$1644 Def000034
+S A$ax5042reset$1635 Def00002D
+S A$ax5042reset$1626 Def000025
+S A$ax5042reset$1617 Def00001B
+S A$ax5042reset$1843 Def0000E9
+S A$ax5042reset$1816 Def0000D6
+S A$ax5042reset$1780 Def0000B2
+S A$ax5042reset$1744 Def00008E
+S A$ax5042reset$1717 Def000084
+S A$ax5042reset$1708 Def000079
+S A$ax5042reset$1681 Def000059
+S A$ax5042reset$1663 Def000046
+S A$ax5042reset$1636 Def00002E
+S A$ax5042reset$1627 Def000026
+S A$ax5042reset$1618 Def00001C
+S A$ax5042reset$1609 Def00000F
+S A$ax5042reset$1844 Def0000EA
+S A$ax5042reset$1835 Def0000E3
+S A$ax5042reset$1826 Def0000DA
+S A$ax5042reset$1817 Def0000D7
+S A$ax5042reset$1808 Def0000CD
+S A$ax5042reset$1763 Def0000A0
+S A$ax5042reset$1754 Def000096
+S A$ax5042reset$1745 Def00008F
+S A$ax5042reset$1691 Def000063
+S A$ax5042reset$1682 Def00005C
+S A$ax5042reset$1664 Def000047
+S A$ax5042reset$1619 Def00001D
+S A$ax5042reset$1845 Def0000EB
+S A$ax5042reset$1827 Def0000DD
+S A$ax5042reset$1773 Def0000AB
+S A$ax5042reset$1764 Def0000A3
+S A$ax5042reset$1692 Def000066
+S A$ax5042reset$1674 Def000051
+S A$ax5042reset$1665 Def00004A
+S A$ax5042reset$1647 Def000035
+S A$ax5042reset$1855 Def0000F2
+S A$ax5042reset$1828 Def0000DF
+S A$ax5042reset$1783 Def0000B4
+S A$ax5042reset$1774 Def0000AD
+S A$ax5042reset$1765 Def0000A5
+S A$ax5042reset$1693 Def000067
+S A$ax5042reset$1675 Def000054
+S A$ax5042reset$1657 Def00003F
+S A$ax5042reset$1648 Def000038
+S A$ax5042reset$1639 Def00002F
+S A$ax5042reset$1838 Def0000E6
+S A$ax5042reset$1829 Def0000E0
+S A$ax5042reset$1793 Def0000BF
+S A$ax5042reset$1784 Def0000B7
+S A$ax5042reset$1757 Def000099
+S A$ax5042reset$1748 Def000092
+S A$ax5042reset$1676 Def000056
+S A$ax5042reset$1658 Def000042
+S A$ax5042reset$1595 Def000000
+S A$ax5042reset$1848 Def0000ED
+S A$ax5042reset$1794 Def0000C2
+S A$ax5042reset$1785 Def0000B9
+S A$ax5042reset$1758 Def00009C
+S A$ax5042reset$1686 Def00005E
+S A$ax5042reset$1659 Def000044
+S A$ax5042reset$1777 Def0000AE
+S A$ax5042reset$1768 Def0000A6
+S A$ax5042reset$1759 Def00009E
+S A$ax5042reset$1696 Def000068
+S A$ax5042reset$1687 Def000061
+S A$ax5042reset$1669 Def00004C
+S A$ax5042reset$1778 Def0000B0
+S A$ax5042reset$1769 Def0000A8
+S A$ax5042reset$1697 Def00006B
+S A$ax5042reset$1679 Def000057
+S A$ax5042reset$1598 Def000003
+S A$ax5042reset$1788 Def0000BA
+S A$ax5042reset$1779 Def0000B1
+S A$ax5042reset$1698 Def00006D
+S A$ax5042reset$1798 Def0000C4
+S A$ax5042reset$1789 Def0000BD
+S A$ax5042reset$1799 Def0000C7
+S C$ax5042reset.c$20$1$66 Def00000F
+S C$ax5042reset.c$12$1$66 Def000000
+S C$ax5042reset.c$22$1$66 Def000015
+S C$ax5042reset.c$13$1$66 Def000003
+S C$ax5042reset.c$23$1$66 Def00001E
+S C$ax5042reset.c$60$1$66 Def00006E
+S C$ax5042reset.c$51$1$66 Def00003F
+S C$ax5042reset.c$42$1$66 Def00002F
+S C$ax5042reset.c$61$1$66 Def000074
+S C$ax5042reset.c$52$1$66 Def000045
+S C$ax5042reset.c$43$1$66 Def000033
+S C$ax5042reset.c$62$1$66 Def00007A
+S C$ax5042reset.c$53$1$66 Def00004C
+S C$ax5042reset.c$35$1$66 Def000027
+S C$ax5042reset.c$17$1$66 Def000006
+S C$ax5042reset.c$63$1$66 Def000081
+S C$ax5042reset.c$54$1$66 Def000051
+S C$ax5042reset.c$36$1$66 Def00002D
+S C$ax5042reset.c$80$1$68 Def0000B4
+S C$ax5042reset.c$71$1$68 Def00008A
+S C$ax5042reset.c$64$1$66 Def000086
+S C$ax5042reset.c$55$1$66 Def000057
+S C$ax5042reset.c$19$1$66 Def00000C
+S C$ax5042reset.c$81$1$68 Def0000BA
+S C$ax5042reset.c$72$1$68 Def000092
+S C$ax5042reset.c$65$1$66 Def000089
+S C$ax5042reset.c$56$1$66 Def00005E
+S C$ax5042reset.c$73$1$68 Def000094
+S C$ax5042reset.c$48$1$66 Def000035
+S C$ax5042reset.c$90$2$69 Def0000D8
+S C$ax5042reset.c$74$1$68 Def000096
+S C$ax5042reset.c$58$1$66 Def000063
+S C$ax5042reset.c$49$1$66 Def00003A
+S C$ax5042reset.c$82$2$69 Def0000BF
+S C$ax5042reset.c$75$1$68 Def000099
+S C$ax5042reset.c$68$1$66 Def00008A
+S C$ax5042reset.c$59$1$66 Def000068
+S C$ax5042reset.c$92$2$69 Def0000DA
+S C$ax5042reset.c$83$2$69 Def0000C4
+S C$ax5042reset.c$76$1$68 Def0000A0
+S C$ax5042reset.c$95$1$68 Def0000E6
+S C$ax5042reset.c$93$2$69 Def0000E1
+S C$ax5042reset.c$84$2$69 Def0000CD
+S C$ax5042reset.c$77$1$68 Def0000A6
+S C$ax5042reset.c$96$1$68 Def0000E8
+S C$ax5042reset.c$94$2$69 Def0000E3
+S C$ax5042reset.c$78$1$68 Def0000AB
+S G$ax5042_reset$0$0 Def000000
+S C$ax5042reset.c$97$1$68 Def0000ED
+S C$ax5042reset.c$86$2$69 Def0000CD
+S C$ax5042reset.c$79$1$68 Def0000AE
+S G$ax5042_probeirq$0$0 Def00008A
+S C$ax5042reset.c$98$1$68 Def0000EF
+S C$ax5042reset.c$87$2$69 Def0000CF
+S C$ax5042reset.c$99$1$68 Def0000F2
+S C$ax5042reset.c$88$2$69 Def0000D8
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 40 00 E0 E0
+R 00 00 00 16
+T 00 00 34 FF BF 02 02 80 05
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A 75 82 01 80 4A
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 4C
+R 00 00 00 16
+T 00 00 4C 75 82 02 80 38
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 5E
+R 00 00 00 16
+T 00 00 5E 75 82 02 80 26
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 90 40 08 E4 F0 90 40 39 74 0E F0 90
+R 00 00 00 16
+T 00 00 6F 40 74 74 01 F0 90 40 7D 74 35 F0 12
+R 00 00 00 16
+T 00 00 7B 00 8A E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 03 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 75 82 00
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 22
+R 00 00 00 16
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 97 8C EB 90 40 0C 74 D0 4F F0 90 40 0D 74
+R 00 00 00 16
+T 00 00 A4 E2 F0 74 60 55 8D FD 74 E0 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 B1 FC 52 05 90 40 0D 74 C0 F0 BD 20 02 80
+R 00 00 00 16
+T 00 00 BE 05
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 C4
+R 00 00 00 16
+T 00 00 C4 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 CF
+R 00 00 00 16
+T 00 00 CF 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 DA
+R 00 00 00 16
+T 00 00 DA 90 40 0C 74 F0 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 E7 0A
+R 00 00 00 16
+T 00 00 E8
+R 00 00 00 16
+T 00 00 E8 ED F4 FD 52 8C 8E A8 75 82 00
+R 00 00 00 16
+T 00 00 F2
+R 00 00 00 16
+T 00 00 F2 22
+R 00 00 00 16
+
+
+M:ax5042reset
+F:G$ax5042_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5042reset.ax5042_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5042_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5042reset.ax5042_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5042reset.ax5042_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5042reset.ax5042_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042deepsleep
+
+XH3
+H 1A areas 3DD global symbols
+M ax5042deepsleep
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5042deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042rclkena
+
+;!FILE libmf/ax5042rclkena.asm
+XH3
+H 1A areas 40D global symbols
+M ax5042rclkena
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 39 flags 20 addr 0
+S G$ax5042_rclk_enable$0$0 Def000000
+S _ax5042_rclk_enable Def000000
+S A$ax5042rclkena$1620 Def000017
+S A$ax5042rclkena$1611 Def00000D
+S A$ax5042rclkena$1602 Def000007
+S A$ax5042rclkena$1621 Def000018
+S A$ax5042rclkena$1612 Def00000F
+S A$ax5042rclkena$1622 Def000019
+S A$ax5042rclkena$1613 Def000011
+S A$ax5042rclkena$1650 Def000036
+S A$ax5042rclkena$1632 Def000025
+S A$ax5042rclkena$1623 Def00001C
+S A$ax5042rclkena$1633 Def000028
+S A$ax5042rclkena$1624 Def00001F
+S A$ax5042rclkena$1606 Def000009
+S A$ax5042rclkena$1643 Def000030
+S A$ax5042rclkena$1625 Def000020
+S A$ax5042rclkena$1616 Def000012
+S A$ax5042rclkena$1607 Def00000A
+S A$ax5042rclkena$1653 Def000038
+S A$ax5042rclkena$1644 Def000033
+S A$ax5042rclkena$1626 Def000021
+S A$ax5042rclkena$1608 Def00000C
+S A$ax5042rclkena$1645 Def000034
+S A$ax5042rclkena$1636 Def000029
+S A$ax5042rclkena$1637 Def00002A
+S A$ax5042rclkena$1619 Def000014
+S A$ax5042rclkena$1638 Def00002C
+S A$ax5042rclkena$1629 Def000022
+S A$ax5042rclkena$1639 Def00002E
+S A$ax5042rclkena$1594 Def000000
+S XG$ax5042_rclk_enable$0$0 Def000038
+S A$ax5042rclkena$1649 Def000035
+S A$ax5042rclkena$1597 Def000002
+S C$ax5042rclkena.c$10$1$64 Def000009
+S A$ax5042rclkena$1599 Def000005
+S C$ax5042rclkena.c$11$1$64 Def00000D
+S C$ax5042rclkena.c$12$1$64 Def000012
+S C$ax5042rclkena.c$13$1$64 Def000014
+S C$ax5042rclkena.c$14$1$64 Def000022
+S C$ax5042rclkena.c$15$1$64 Def000025
+S C$ax5042rclkena.c$16$1$64 Def000029
+S C$ax5042rclkena.c$17$1$64 Def000030
+S C$ax5042rclkena.c$18$1$64 Def000035
+S C$ax5042rclkena.c$19$1$64 Def000038
+S C$ax5042rclkena.c$8$1$64 Def000002
+S C$ax5042rclkena.c$9$1$64 Def000007
+S C$ax5042rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 05
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 90 40 70 E4 F0
+R 00 00 00 16
+T 00 00 35
+R 00 00 00 16
+T 00 00 35 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5042rclkena
+F:G$ax5042_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5042rclkena.ax5042_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5042rclkena.ax5042_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5042rclkena.ax5042_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
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+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
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+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5042rclkdis
+
+;!FILE libmf/ax5042rclkdis.asm
+XH3
+H 1A areas 402 global symbols
+M ax5042rclkdis
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2A flags 20 addr 0
+S _ax5042_rclk_disable Def000000
+S C$ax5042rclkdis.c$8$1$64 Def000000
+S C$ax5042rclkdis.c$9$1$64 Def000005
+S C$ax5042rclkdis.c$5$0$0 Def000000
+S XG$ax5042_rclk_disable$0$0 Def000029
+S A$ax5042rclkdis$1600 Def000005
+S A$ax5042rclkdis$1610 Def000011
+S A$ax5042rclkdis$1620 Def00001A
+S A$ax5042rclkdis$1611 Def000012
+S A$ax5042rclkdis$1621 Def00001C
+S A$ax5042rclkdis$1612 Def000014
+S A$ax5042rclkdis$1603 Def000007
+S A$ax5042rclkdis$1622 Def00001E
+S A$ax5042rclkdis$1632 Def000026
+S A$ax5042rclkdis$1633 Def000027
+S A$ax5042rclkdis$1615 Def000015
+S A$ax5042rclkdis$1606 Def00000A
+S A$ax5042rclkdis$1616 Def000018
+S A$ax5042rclkdis$1607 Def00000D
+S A$ax5042rclkdis$1626 Def000020
+S A$ax5042rclkdis$1608 Def00000E
+S A$ax5042rclkdis$1636 Def000029
+S A$ax5042rclkdis$1627 Def000023
+S A$ax5042rclkdis$1609 Def00000F
+S A$ax5042rclkdis$1628 Def000025
+S A$ax5042rclkdis$1619 Def000019
+S A$ax5042rclkdis$1595 Def000000
+S A$ax5042rclkdis$1596 Def000002
+S A$ax5042rclkdis$1597 Def000004
+S C$ax5042rclkdis.c$10$1$64 Def000007
+S C$ax5042rclkdis.c$11$1$64 Def00000A
+S C$ax5042rclkdis.c$12$1$64 Def000015
+S C$ax5042rclkdis.c$13$1$64 Def000019
+S C$ax5042rclkdis.c$14$1$64 Def000020
+S C$ax5042rclkdis.c$15$1$64 Def000026
+S G$ax5042_rclk_disable$0$0 Def000000
+S C$ax5042rclkdis.c$16$1$64 Def000029
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 54 2F 60 02 80 06
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 90 40 70 74 80 F0
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5042rclkdis
+F:G$ax5042_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5042rclkdis.ax5042_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5042rclkdis.ax5042_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5042rdfifo
+
+;!FILE libmf/ax5042rdfifo.asm
+XH3
+H 1A areas 415 global symbols
+M ax5042rdfifo
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
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+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
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+S G$U0STATUS$0$0 Def0000E5
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+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
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+S C$ax5042rdfifo.c$75$1$66 Def000054
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+S A$ax5042rdfifo$1598 Def000011
+S A$ax5042rdfifo$1589 Def000000
+S A$ax5042rdfifo$1599 Def000014
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+
+
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+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042wrfifo
+
+;!FILE libmf/ax5042wrfifo.asm
+XH3
+H 1A areas 417 global symbols
+M ax5042wrfifo
+O -mmcs51 --model-small
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S A$ax5042wrfifo$1610 Def00001E
+S A$ax5042wrfifo$1601 Def000017
+S A$ax5042wrfifo$1620 Def00002C
+S A$ax5042wrfifo$1611 Def00001F
+S A$ax5042wrfifo$1602 Def000018
+S A$ax5042wrfifo$1630 Def00003B
+S A$ax5042wrfifo$1621 Def00002F
+S A$ax5042wrfifo$1612 Def000020
+S A$ax5042wrfifo$1603 Def000019
+S A$ax5042wrfifo$1640 Def00004A
+S A$ax5042wrfifo$1613 Def000022
+S A$ax5042wrfifo$1604 Def00001A
+S A$ax5042wrfifo$1641 Def00004B
+S A$ax5042wrfifo$1632 Def00003C
+S A$ax5042wrfifo$1623 Def000031
+S A$ax5042wrfifo$1642 Def00004C
+S A$ax5042wrfifo$1633 Def00003E
+S A$ax5042wrfifo$1624 Def000032
+S A$ax5042wrfifo$1615 Def000023
+S A$ax5042wrfifo$1606 Def00001C
+S A$ax5042wrfifo$1643 Def00004D
+S A$ax5042wrfifo$1634 Def000040
+S A$ax5042wrfifo$1625 Def000033
+S A$ax5042wrfifo$1616 Def000025
+S A$ax5042wrfifo$1644 Def00004E
+S A$ax5042wrfifo$1635 Def000041
+S A$ax5042wrfifo$1626 Def000034
+S A$ax5042wrfifo$1617 Def000027
+S A$ax5042wrfifo$1590 Def000002
+S A$ax5042wrfifo$1645 Def000050
+S A$ax5042wrfifo$1636 Def000043
+S A$ax5042wrfifo$1627 Def000036
+S A$ax5042wrfifo$1618 Def000028
+S A$ax5042wrfifo$1609 Def00001D
+S A$ax5042wrfifo$1591 Def000004
+S A$ax5042wrfifo$1646 Def000052
+S A$ax5042wrfifo$1637 Def000045
+S A$ax5042wrfifo$1628 Def000038
+S A$ax5042wrfifo$1619 Def00002A
+S A$ax5042wrfifo$1592 Def000005
+S A$ax5042wrfifo$1647 Def000053
+S A$ax5042wrfifo$1638 Def000048
+S A$ax5042wrfifo$1629 Def000039
+S A$ax5042wrfifo$1593 Def000006
+S A$ax5042wrfifo$1648 Def000055
+S A$ax5042wrfifo$1594 Def000008
+S A$ax5042wrfifo$1595 Def000009
+S A$ax5042wrfifo$1596 Def00000C
+S A$ax5042wrfifo$1597 Def00000F
+S A$ax5042wrfifo$1598 Def000011
+S A$ax5042wrfifo$1589 Def000000
+S A$ax5042wrfifo$1599 Def000014
+S C$ax5042wrfifo.c$10$0$0 Def000000
+S C$ax5042wrfifo.c$75$1$66 Def000000
+S C$ax5042wrfifo.c$76$1$66 Def000056
+S G$ax5042_writefifo$0$0 Def000000
+S _ax5042_writefifo Def000000
+S XG$ax5042_writefifo$0$0 Def000056
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
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+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
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+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
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+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5042regs
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5042regs
+
+
+
+
+ax5043comminit
+
+;!FILE libmf/ax5043comminit.asm
+XH3
+H 1A areas 861 global symbols
+M ax5043comminit
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
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+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
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+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
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+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
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+S _E2IE_6 Def0000A6
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+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
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+S _XWTCNTB1 Def003FFB
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+S _AX5043_0xF18 Def004F18
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+S _AX5043_AGCAHYST3NB Def005152
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+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
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+S _AX5043_FREQUENCYGAIND3NB Def00515A
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+S G$AX5043_DRGAIN0$0$0 Def004125
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+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
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+S _AX5043_POWSTICKYSTATNB Def005004
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+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
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+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
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+S G$AX5043_DRGAIN1$0$0 Def004135
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+S G$RADIOFDATAADDR$0$0 Def007040
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+S G$WTIRQEN$0$0 Def0000E9
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+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
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+S _AX5043_AGCGAIN0 Def004120
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+S _AX5043_TXRATE2NB Def005165
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+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSEL$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RADIOEVENTREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_REF$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHR$0$0({1}SC:U),F,0,0
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+S:G$AX5043_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISION$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMER2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKRFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TXPWRCOEFFB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPFREQ1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPTIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLY$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCAHYST3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCMINMAX0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCMINMAX2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCTARGET3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AMPLITUDEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBOFFSRES3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_DRGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
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+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043commslpexit
+
+;!FILE libmf/ax5043commslpexit.asm
+XH3
+H 1A areas 863 global symbols
+M ax5043commslpexit
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S _ax5043_probeirq Ref000000
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5043commslpexit.c$24$1$66 Def000024
+S C$ax5043commslpexit.c$15$1$66 Def000012
+S C$ax5043commslpexit.c$25$1$66 Def000027
+S C$ax5043commslpexit.c$16$1$66 Def00001B
+S C$ax5043commslpexit.c$8$0$0 Def000000
+S G$ax5043_commsleepexit$0$0 Def000000
+S _ax5043_commsleepexit Def000000
+S A$ax5043commslpexit$3301 Def00001B
+S A$ax5043commslpexit$3302 Def00001E
+S A$ax5043commslpexit$3312 Def000027
+S A$ax5043commslpexit$3303 Def000020
+S A$ax5043commslpexit$3304 Def000021
+S A$ax5043commslpexit$3305 Def000022
+S XG$ax5043_commsleepexit$0$0 Def000027
+S A$ax5043commslpexit$3306 Def000023
+S A$ax5043commslpexit$3290 Def00000F
+S A$ax5043commslpexit$3309 Def000024
+S A$ax5043commslpexit$3282 Def000006
+S A$ax5043commslpexit$3283 Def000009
+S A$ax5043commslpexit$3293 Def000012
+S A$ax5043commslpexit$3284 Def00000A
+S A$ax5043commslpexit$3294 Def000015
+S A$ax5043commslpexit$3285 Def00000B
+S A$ax5043commslpexit$3276 Def000000
+S A$ax5043commslpexit$3295 Def000017
+S A$ax5043commslpexit$3286 Def00000D
+S A$ax5043commslpexit$3296 Def000018
+S A$ax5043commslpexit$3287 Def00000E
+S A$ax5043commslpexit$3297 Def000019
+S A$ax5043commslpexit$3279 Def000003
+S A$ax5043commslpexit$3298 Def00001A
+S C$ax5043commslpexit.c$10$1$66 Def000000
+S C$ax5043commslpexit.c$11$1$66 Def000003
+S C$ax5043commslpexit.c$12$1$66 Def000006
+S C$ax5043commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
+R 00 00 00 16
+T 00 00 0D 4F F0 75 B1 0C 90 70 40 74 29 F0 E4 A3
+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 28 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 EF
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5043commslpexit
+F:G$ax5043_commsleepexit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSEL$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RADIOEVENTREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_REF$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHR$0$0({1}SC:U),F,0,0
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+S:G$AX5043_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISION$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMER2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGC$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXCOARSEAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGTXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKAMPLITUDE0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKRFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TXPWRCOEFFB1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TXPWRCOEFFE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPTIMER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLY$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCAHYST3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCTARGET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AMPLITUDEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBOFFSRES2$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_DRGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINC3NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PHASEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043reset
+
+;!FILE libmf/ax5043reset.asm
+XH3
+H 1A areas 8ED global symbols
+M ax5043reset
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIODRV$0$0 Def007045
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S _delay Ref000000
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _radio_wakeup_deepsleep_core Ref000000
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIODRV Def007045
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size D7 flags 20 addr 0
+S C$ax5043reset.c$8$0$0 Def000000
+S _ax5043_reset Def000000
+S _ax5043_probeirq Def00007C
+S XG$ax5043_reset$0$0 Def00007B
+S XG$ax5043_probeirq$0$0 Def0000D6
+S A$ax5043reset$3400 Def00007B
+S A$ax5043reset$3310 Def00001E
+S A$ax5043reset$3311 Def000021
+S A$ax5043reset$3302 Def000015
+S A$ax5043reset$3330 Def000032
+S A$ax5043reset$3321 Def00002A
+S A$ax5043reset$3312 Def000023
+S A$ax5043reset$3303 Def000018
+S A$ax5043reset$3502 Def0000CA
+S A$ax5043reset$3430 Def00008B
+S A$ax5043reset$3331 Def000035
+S A$ax5043reset$3322 Def00002D
+S A$ax5043reset$3313 Def000024
+S A$ax5043reset$3304 Def00001A
+S A$ax5043reset$3512 Def0000D1
+S A$ax5043reset$3422 Def000080
+S A$ax5043reset$3323 Def00002F
+S A$ax5043reset$3314 Def000025
+S A$ax5043reset$3305 Def00001B
+S A$ax5043reset$3450 Def00009E
+S A$ax5043reset$3360 Def000053
+S A$ax5043reset$3342 Def00003E
+S A$ax5043reset$3315 Def000026
+S A$ax5043reset$3306 Def00001C
+S A$ax5043reset$3442 Def000093
+S A$ax5043reset$3433 Def00008C
+S A$ax5043reset$3370 Def00005D
+S A$ax5043reset$3352 Def000048
+S A$ax5043reset$3343 Def000041
+S A$ax5043reset$3334 Def000038
+S A$ax5043reset$3307 Def00001D
+S A$ax5043reset$3515 Def0000D3
+S A$ax5043reset$3506 Def0000CC
+S A$ax5043reset$3443 Def000095
+S A$ax5043reset$3434 Def00008E
+S A$ax5043reset$3425 Def000083
+S A$ax5043reset$3416 Def00007C
+S A$ax5043reset$3371 Def00005F
+S A$ax5043reset$3353 Def00004B
+S A$ax5043reset$3335 Def00003B
+S A$ax5043reset$3326 Def000030
+S A$ax5043reset$3290 Def000009
+S A$ax5043reset$3507 Def0000CD
+S A$ax5043reset$3480 Def0000B9
+S A$ax5043reset$3453 Def00009F
+S A$ax5043reset$3444 Def000096
+S A$ax5043reset$3435 Def000090
+S A$ax5043reset$3381 Def000067
+S A$ax5043reset$3354 Def00004D
+S A$ax5043reset$3327 Def000031
+S A$ax5043reset$3318 Def000027
+S A$ax5043reset$3291 Def00000B
+S A$ax5043reset$3508 Def0000CE
+S A$ax5043reset$3481 Def0000BB
+S A$ax5043reset$3463 Def0000A9
+S A$ax5043reset$3454 Def0000A2
+S A$ax5043reset$3445 Def000097
+S A$ax5043reset$3391 Def000073
+S A$ax5043reset$3382 Def00006A
+S A$ax5043reset$3364 Def000055
+S A$ax5043reset$3283 Def000000
+S A$ax5043reset$3509 Def0000CF
+S A$ax5043reset$3491 Def0000BF
+S A$ax5043reset$3482 Def0000BC
+S A$ax5043reset$3473 Def0000B2
+S A$ax5043reset$3464 Def0000AC
+S A$ax5043reset$3428 Def000086
+S A$ax5043reset$3419 Def00007E
+S A$ax5043reset$3392 Def000076
+S A$ax5043reset$3374 Def000060
+S A$ax5043reset$3365 Def000058
+S A$ax5043reset$3347 Def000043
+S A$ax5043reset$3338 Def00003C
+S A$ax5043reset$3519 Def0000D6
+S A$ax5043reset$3492 Def0000C2
+S A$ax5043reset$3465 Def0000AD
+S A$ax5043reset$3438 Def000091
+S A$ax5043reset$3429 Def000089
+S A$ax5043reset$3375 Def000061
+S A$ax5043reset$3357 Def00004E
+S A$ax5043reset$3348 Def000046
+S A$ax5043reset$3339 Def00003D
+S A$ax5043reset$3294 Def00000C
+S A$ax5043reset$3493 Def0000C4
+S A$ax5043reset$3466 Def0000AE
+S A$ax5043reset$3448 Def000099
+S A$ax5043reset$3439 Def000092
+S A$ax5043reset$3376 Def000062
+S A$ax5043reset$3358 Def00004F
+S A$ax5043reset$3286 Def000003
+S A$ax5043reset$3467 Def0000B0
+S A$ax5043reset$3458 Def0000A4
+S A$ax5043reset$3449 Def00009C
+S A$ax5043reset$3386 Def00006C
+S A$ax5043reset$3377 Def000065
+S A$ax5043reset$3359 Def000050
+S A$ax5043reset$3477 Def0000B4
+S A$ax5043reset$3468 Def0000B1
+S A$ax5043reset$3459 Def0000A7
+S A$ax5043reset$3396 Def000078
+S A$ax5043reset$3387 Def00006F
+S A$ax5043reset$3369 Def00005A
+S A$ax5043reset$3297 Def00000F
+S A$ax5043reset$3496 Def0000C5
+S A$ax5043reset$3487 Def0000BD
+S A$ax5043reset$3478 Def0000B7
+S A$ax5043reset$3388 Def000071
+S A$ax5043reset$3298 Def000012
+S A$ax5043reset$3289 Def000006
+S A$ax5043reset$3479 Def0000B8
+S A$ax5043reset$3299 Def000014
+S A$ax5043reset$3499 Def0000C7
+S C$ax5043reset.c$20$1$66 Def00000F
+S C$ax5043reset.c$12$1$66 Def000000
+S C$ax5043reset.c$22$1$66 Def000015
+S C$ax5043reset.c$13$1$66 Def000003
+S C$ax5043reset.c$32$1$66 Def000027
+S C$ax5043reset.c$23$1$66 Def00001E
+S C$ax5043reset.c$60$1$66 Def000078
+S C$ax5043reset.c$51$1$66 Def000048
+S C$ax5043reset.c$42$1$66 Def000038
+S C$ax5043reset.c$15$1$66 Def000006
+S C$ax5043reset.c$61$1$66 Def00007B
+S C$ax5043reset.c$52$1$66 Def00004E
+S C$ax5043reset.c$43$1$66 Def00003C
+S C$ax5043reset.c$53$1$66 Def000055
+S C$ax5043reset.c$35$1$66 Def00002A
+S C$ax5043reset.c$70$1$68 Def00007E
+S C$ax5043reset.c$54$1$66 Def00005A
+S C$ax5043reset.c$36$1$66 Def000030
+S C$ax5043reset.c$71$1$68 Def000080
+S C$ax5043reset.c$55$1$66 Def000060
+S C$ax5043reset.c$19$1$66 Def00000C
+S C$ax5043reset.c$72$1$68 Def000083
+S C$ax5043reset.c$56$1$66 Def000067
+S C$ax5043reset.c$80$2$69 Def0000A9
+S C$ax5043reset.c$73$1$68 Def000086
+S C$ax5043reset.c$66$1$66 Def00007C
+S C$ax5043reset.c$48$1$66 Def00003E
+S C$ax5043reset.c$39$1$66 Def000032
+S C$ax5043reset.c$92$1$68 Def0000CA
+S C$ax5043reset.c$90$2$69 Def0000C5
+S C$ax5043reset.c$81$2$69 Def0000B2
+S C$ax5043reset.c$74$1$68 Def00008C
+S C$ax5043reset.c$58$1$66 Def00006C
+S C$ax5043reset.c$49$1$66 Def000043
+S C$ax5043reset.c$93$1$68 Def0000CC
+S C$ax5043reset.c$91$2$69 Def0000C7
+S C$ax5043reset.c$75$1$68 Def000091
+S C$ax5043reset.c$59$1$66 Def000073
+S C$ax5043reset.c$94$1$68 Def0000D1
+S C$ax5043reset.c$83$2$69 Def0000B2
+S C$ax5043reset.c$76$1$68 Def000093
+S C$ax5043reset.c$69$1$66 Def00007C
+S C$ax5043reset.c$95$1$68 Def0000D3
+S C$ax5043reset.c$84$2$69 Def0000B4
+S C$ax5043reset.c$77$1$68 Def000099
+S C$ax5043reset.c$96$1$68 Def0000D6
+S C$ax5043reset.c$85$2$69 Def0000BD
+S C$ax5043reset.c$78$1$68 Def00009F
+S G$ax5043_reset$0$0 Def000000
+S G$ax5043_probeirq$0$0 Def00007C
+S C$ax5043reset.c$87$2$69 Def0000BD
+S C$ax5043reset.c$79$2$69 Def0000A4
+S C$ax5043reset.c$89$2$69 Def0000BF
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 07 F0 75
+R 00 00 00 16
+T 00 00 0D B1 0C 90 70 0C 74 01 F0 90 70 40 74 29
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 28 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 12 00 00 90 40 02 74 80 F0 E4 F0 90
+R 00 00 00 16 02 04 07 58
+T 00 00 33 00 0A 12 00 00 90 40 00 E0 E0 FF BF 51
+R 00 00 00 16 02 06 05 F3
+T 00 00 40 02 80 05
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 75 82 01 80 33
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 75 82 02 80 21
+R 00 00 00 16
+T 00 00 5A
+R 00 00 00 16
+T 00 00 5A 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 67
+R 00 00 00 16
+T 00 00 67 75 82 02 80 0F
+R 00 00 00 16
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C 12 00 7C E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 04 00 16
+T 00 00 78
+R 00 00 00 16
+T 00 00 78 75 82 00
+R 00 00 00 16
+T 00 00 7B
+R 00 00 00 16
+T 00 00 7B 22
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C AF A8 C2 AC 53 8C EB 43 8C 2B 90 40 24
+R 00 00 00 16
+T 00 00 89 74 01 F0 74 60 55 8D FE E4 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 96 FD 52 06 90 40 24 74 03 F0 BE 20 02 80
+R 00 00 00 16
+T 00 00 A3 05
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 BE 40 18 80 0B
+R 00 00 00 16
+T 00 00 A9
+R 00 00 00 16
+T 00 00 A9 90 70 44 E0 FD 74 F7 5D F0 80 18
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 90 70 44 E0 FD 74 08 4D F0 80 0D
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 90 40 24 74 02 F0 8F A8 75 82 01 80 0A
+R 00 00 00 16
+T 00 00 CC
+R 00 00 00 16
+T 00 00 CC EE F4 FE 52 8C 8F A8 75 82 00
+R 00 00 00 16
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 22
+R 00 00 00 16
+
+
+M:ax5043reset
+F:G$ax5043_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043reset.ax5043_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5043_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043reset.ax5043_probeirq$p$1$68({1}SC:U),R,0,0,[r6]
+S:Lax5043reset.ax5043_probeirq$iesave$1$68({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
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+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043deepsleep
+
+;!FILE libmf/ax5043deepsleep.asm
+XH3
+H 1A areas 894 global symbols
+M ax5043deepsleep
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S _ax5043_probeirq Ref000000
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _radio_wakeup_deepsleep_core Ref000000
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 63 flags 20 addr 0
+S C$ax5043deepsleep.c$21$1$66 Def000019
+S C$ax5043deepsleep.c$12$1$66 Def000000
+S C$ax5043deepsleep.c$22$1$66 Def00001F
+S C$ax5043deepsleep.c$13$1$66 Def000003
+S C$ax5043deepsleep.c$10$0$0 Def000000
+S C$ax5043deepsleep.c$31$1$68 Def00002F
+S C$ax5043deepsleep.c$24$1$66 Def000020
+S C$ax5043deepsleep.c$32$1$68 Def000038
+S C$ax5043deepsleep.c$17$1$66 Def000009
+S C$ax5043deepsleep.c$41$2$69 Def000046
+S C$ax5043deepsleep.c$18$1$66 Def00000E
+S _ax5043_wakeup_deepsleep Def000020
+S C$ax5043deepsleep.c$42$2$69 Def000049
+S C$ax5043deepsleep.c$26$1$68 Def000020
+S C$ax5043deepsleep.c$19$1$66 Def000010
+S C$ax5043deepsleep.c$45$1$68 Def000053
+S C$ax5043deepsleep.c$43$2$69 Def00004F
+S C$ax5043deepsleep.c$27$1$68 Def000023
+S C$ax5043deepsleep.c$46$1$68 Def00005A
+S C$ax5043deepsleep.c$28$1$68 Def000026
+S C$ax5043deepsleep.c$47$1$68 Def00005F
+S C$ax5043deepsleep.c$29$1$68 Def00002C
+S C$ax5043deepsleep.c$48$1$68 Def000062
+S C$ax5043deepsleep.c$39$1$68 Def000041
+S G$ax5043_enter_deepsleep$0$0 Def000000
+S XG$ax5043_wakeup_deepsleep$0$0 Def000062
+S _ax5043_enter_deepsleep Def000000
+S XG$ax5043_enter_deepsleep$0$0 Def00001F
+S A$ax5043deepsleep$3300 Def000018
+S A$ax5043deepsleep$3330 Def000029
+S A$ax5043deepsleep$3303 Def000019
+S A$ax5043deepsleep$3340 Def000035
+S A$ax5043deepsleep$3331 Def00002B
+S A$ax5043deepsleep$3304 Def00001B
+S A$ax5043deepsleep$3350 Def000040
+S A$ax5043deepsleep$3341 Def000036
+S A$ax5043deepsleep$3323 Def000020
+S A$ax5043deepsleep$3305 Def00001D
+S A$ax5043deepsleep$3342 Def000037
+S A$ax5043deepsleep$3361 Def000049
+S A$ax5043deepsleep$3334 Def00002C
+S A$ax5043deepsleep$3362 Def00004B
+S A$ax5043deepsleep$3353 Def000041
+S A$ax5043deepsleep$3326 Def000023
+S A$ax5043deepsleep$3308 Def00001F
+S A$ax5043deepsleep$3281 Def000003
+S A$ax5043deepsleep$3372 Def000053
+S A$ax5043deepsleep$3363 Def00004C
+S A$ax5043deepsleep$3354 Def000044
+S A$ax5043deepsleep$3345 Def000038
+S A$ax5043deepsleep$3291 Def00000E
+S A$ax5043deepsleep$3282 Def000006
+S A$ax5043deepsleep$3382 Def00005F
+S A$ax5043deepsleep$3373 Def000056
+S A$ax5043deepsleep$3364 Def00004D
+S A$ax5043deepsleep$3355 Def000045
+S A$ax5043deepsleep$3346 Def00003B
+S A$ax5043deepsleep$3337 Def00002F
+S A$ax5043deepsleep$3292 Def00000F
+S A$ax5043deepsleep$3283 Def000008
+S A$ax5043deepsleep$3374 Def000058
+S A$ax5043deepsleep$3347 Def00003D
+S A$ax5043deepsleep$3338 Def000032
+S A$ax5043deepsleep$3329 Def000026
+S A$ax5043deepsleep$3348 Def00003E
+S A$ax5043deepsleep$3339 Def000034
+S A$ax5043deepsleep$3367 Def00004F
+S A$ax5043deepsleep$3358 Def000046
+S A$ax5043deepsleep$3349 Def00003F
+S A$ax5043deepsleep$3295 Def000010
+S A$ax5043deepsleep$3286 Def000009
+S A$ax5043deepsleep$3386 Def000062
+S A$ax5043deepsleep$3377 Def00005A
+S A$ax5043deepsleep$3368 Def000051
+S A$ax5043deepsleep$3296 Def000013
+S A$ax5043deepsleep$3287 Def00000C
+S A$ax5043deepsleep$3278 Def000000
+S A$ax5043deepsleep$3378 Def00005D
+S A$ax5043deepsleep$3297 Def000014
+S A$ax5043deepsleep$3288 Def00000D
+S G$ax5043_wakeup_deepsleep$0$0 Def000020
+S A$ax5043deepsleep$3298 Def000015
+S A$ax5043deepsleep$3299 Def000017
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 43 8C 0B 90 40 21 74 01 F0 90 40 02 E4
+R 00 00 00 16
+T 00 00 0D F0 04 F0 90 70 44 E0 FF 74 BF 5F F0 74
+R 00 00 00 16
+T 00 00 1A F7 45 8D 52 8C 22
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 75 8E 15 75 8C EB 90 70 44 74 07 F0 75
+R 00 00 00 16
+T 00 00 2D B1 0C 90 70 40 74 29 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 39 70 42 74 28 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 46 12 00 00 E5 82 FF FE 60 04 8E 82 80 0F
+R 00 00 00 16 02 04 07 57
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 12 00 00 E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 02 04 00 EF
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 75 82 00
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 22
+R 00 00 00 16
+
+
+M:ax5043deepsleep
+F:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043deepsleep.ax5043_wakeup_deepsleep$i$2$69({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
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+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043rclkena
+
+;!FILE libmf/ax5043rclkena.asm
+XH3
+H 1A areas 86C global symbols
+M ax5043rclkena
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S G$ax5043_rclk_enable$0$0 Def000000
+S A$ax5043rclkena$3310 Def00001C
+S _ax5043_rclk_enable Def000000
+S A$ax5043rclkena$3311 Def00001F
+S A$ax5043rclkena$3302 Def000014
+S A$ax5043rclkena$3330 Def000031
+S A$ax5043rclkena$3321 Def000027
+S A$ax5043rclkena$3303 Def000017
+S A$ax5043rclkena$3322 Def000029
+S A$ax5043rclkena$3304 Def000018
+S A$ax5043rclkena$3323 Def00002A
+S A$ax5043rclkena$3314 Def000020
+S A$ax5043rclkena$3333 Def000033
+S A$ax5043rclkena$3324 Def00002D
+S A$ax5043rclkena$3315 Def000021
+S A$ax5043rclkena$3325 Def00002F
+S A$ax5043rclkena$3316 Def000023
+S A$ax5043rclkena$3307 Def000019
+S A$ax5043rclkena$3280 Def000002
+S A$ax5043rclkena$3317 Def000025
+S A$ax5043rclkena$3290 Def00000A
+S A$ax5043rclkena$3291 Def00000C
+S A$ax5043rclkena$3282 Def000005
+S A$ax5043rclkena$3329 Def000030
+S A$ax5043rclkena$3294 Def00000D
+S A$ax5043rclkena$3285 Def000007
+S A$ax5043rclkena$3295 Def00000F
+S A$ax5043rclkena$3277 Def000000
+S XG$ax5043_rclk_enable$0$0 Def000033
+S A$ax5043rclkena$3296 Def000011
+S A$ax5043rclkena$3289 Def000009
+S A$ax5043rclkena$3299 Def000012
+S C$ax5043rclkena.c$10$1$64 Def000009
+S C$ax5043rclkena.c$11$1$64 Def00000D
+S C$ax5043rclkena.c$12$1$64 Def000012
+S C$ax5043rclkena.c$13$1$64 Def000014
+S C$ax5043rclkena.c$14$1$64 Def000019
+S C$ax5043rclkena.c$15$1$64 Def00001C
+S C$ax5043rclkena.c$16$1$64 Def000020
+S C$ax5043rclkena.c$17$1$64 Def000027
+S C$ax5043rclkena.c$18$1$64 Def000030
+S C$ax5043rclkena.c$19$1$64 Def000033
+S C$ax5043rclkena.c$8$1$64 Def000002
+S C$ax5043rclkena.c$9$1$64 Def000007
+S C$ax5043rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0A 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0A
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 21 EF F0 53 8C FD 90 40 02 E0 FF 54
+R 00 00 00 16
+T 00 00 22 0F 60 02 80 09
+R 00 00 00 16
+T 00 00 27
+R 00 00 00 16
+T 00 00 27 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rclkena
+F:G$ax5043_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5043rclkena.ax5043_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5043rclkena.ax5043_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5043rclkena.ax5043_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
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+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5043rclkdis
+
+;!FILE libmf/ax5043rclkdis.asm
+XH3
+H 1A areas 862 global symbols
+M ax5043rclkdis
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S _ax5043_rclk_disable Def000000
+S C$ax5043rclkdis.c$8$1$64 Def000000
+S C$ax5043rclkdis.c$9$1$64 Def000005
+S C$ax5043rclkdis.c$5$0$0 Def000000
+S XG$ax5043_rclk_disable$0$0 Def000026
+S A$ax5043rclkdis$3300 Def000017
+S A$ax5043rclkdis$3301 Def000018
+S A$ax5043rclkdis$3302 Def000019
+S A$ax5043rclkdis$3312 Def000023
+S A$ax5043rclkdis$3313 Def000024
+S A$ax5043rclkdis$3305 Def00001C
+S A$ax5043rclkdis$3306 Def00001F
+S A$ax5043rclkdis$3316 Def000026
+S A$ax5043rclkdis$3307 Def000021
+S A$ax5043rclkdis$3280 Def000004
+S A$ax5043rclkdis$3308 Def000022
+S A$ax5043rclkdis$3290 Def00000D
+S A$ax5043rclkdis$3291 Def00000F
+S A$ax5043rclkdis$3283 Def000005
+S A$ax5043rclkdis$3294 Def000010
+S A$ax5043rclkdis$3295 Def000013
+S A$ax5043rclkdis$3286 Def000007
+S A$ax5043rclkdis$3296 Def000014
+S A$ax5043rclkdis$3278 Def000000
+S A$ax5043rclkdis$3279 Def000002
+S A$ax5043rclkdis$3289 Def00000A
+S A$ax5043rclkdis$3299 Def000015
+S C$ax5043rclkdis.c$10$1$64 Def000007
+S C$ax5043rclkdis.c$11$1$64 Def00000A
+S C$ax5043rclkdis.c$12$1$64 Def000010
+S C$ax5043rclkdis.c$13$1$64 Def000015
+S C$ax5043rclkdis.c$14$1$64 Def00001C
+S C$ax5043rclkdis.c$15$1$64 Def000023
+S G$ax5043_rclk_disable$0$0 Def000000
+S C$ax5043rclkdis.c$16$1$64 Def000026
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 21
+R 00 00 00 16
+T 00 00 0D 74 01 F0 90 40 02 E0 FE 74 0F 5E FD BD
+R 00 00 00 16
+T 00 00 1A 05 07 90 40 02 74 F0 5E F0
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rclkdis
+F:G$ax5043_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5043rclkdis.ax5043_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5043rclkdis.ax5043_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
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+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5043rdfifo
+
+;!FILE libmf/ax5043rdfifo.asm
+XH3
+H 1A areas 877 global symbols
+M ax5043rdfifo
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S C$ax5043rdfifo.c$10$0$0 Def000000
+S C$ax5043rdfifo.c$74$1$66 Def000000
+S C$ax5043rdfifo.c$75$1$66 Def000054
+S G$ax5043_readfifo$0$0 Def000000
+S _ax5043_readfifo Def000000
+S A$ax5043rdfifo$3300 Def000027
+S A$ax5043rdfifo$3310 Def000036
+S A$ax5043rdfifo$3301 Def000028
+S XG$ax5043_readfifo$0$0 Def000054
+S A$ax5043rdfifo$3320 Def000045
+S A$ax5043rdfifo$3311 Def000038
+S A$ax5043rdfifo$3302 Def00002A
+S A$ax5043rdfifo$3330 Def000053
+S A$ax5043rdfifo$3321 Def000048
+S A$ax5043rdfifo$3312 Def000039
+S A$ax5043rdfifo$3303 Def00002C
+S A$ax5043rdfifo$3313 Def00003B
+S A$ax5043rdfifo$3304 Def00002F
+S A$ax5043rdfifo$3323 Def00004A
+S A$ax5043rdfifo$3315 Def00003C
+S A$ax5043rdfifo$3306 Def000031
+S A$ax5043rdfifo$3325 Def00004B
+S A$ax5043rdfifo$3316 Def00003E
+S A$ax5043rdfifo$3307 Def000032
+S A$ax5043rdfifo$3280 Def00000F
+S A$ax5043rdfifo$3326 Def00004C
+S A$ax5043rdfifo$3317 Def000040
+S A$ax5043rdfifo$3308 Def000033
+S A$ax5043rdfifo$3281 Def000011
+S A$ax5043rdfifo$3272 Def000000
+S A$ax5043rdfifo$3327 Def00004E
+S A$ax5043rdfifo$3318 Def000041
+S A$ax5043rdfifo$3309 Def000034
+S A$ax5043rdfifo$3282 Def000014
+S A$ax5043rdfifo$3273 Def000002
+S A$ax5043rdfifo$3328 Def000050
+S A$ax5043rdfifo$3319 Def000043
+S A$ax5043rdfifo$3292 Def00001D
+S A$ax5043rdfifo$3274 Def000004
+S A$ax5043rdfifo$3329 Def000051
+S A$ax5043rdfifo$3293 Def00001E
+S A$ax5043rdfifo$3284 Def000017
+S A$ax5043rdfifo$3275 Def000005
+S A$ax5043rdfifo$3294 Def00001F
+S A$ax5043rdfifo$3285 Def000018
+S A$ax5043rdfifo$3276 Def000006
+S A$ax5043rdfifo$3295 Def000020
+S A$ax5043rdfifo$3286 Def000019
+S A$ax5043rdfifo$3277 Def000008
+S A$ax5043rdfifo$3296 Def000022
+S A$ax5043rdfifo$3287 Def00001A
+S A$ax5043rdfifo$3278 Def000009
+S A$ax5043rdfifo$3279 Def00000C
+S A$ax5043rdfifo$3298 Def000023
+S A$ax5043rdfifo$3289 Def00001C
+S A$ax5043rdfifo$3299 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
+T 00 00 0D F6 14 A8 82 90 40 29 20 F5 06
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 E0 F6 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D E0 F2 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 29
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E2 F0 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 29
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E2 A3 DF FC 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rdfifo
+F:G$ax5043_readfifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5043rdfifo.ax5043_readfifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5043rdfifo.ax5043_readfifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
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+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043wrfifo
+
+;!FILE libmf/ax5043wrfifo.asm
+XH3
+H 1A areas 879 global symbols
+M ax5043wrfifo
+O -mmcs51 --model-small
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
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+S G$IP_4$0$0 Def0000BC
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+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
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+S A$ax5043wrfifo$3286 Def000019
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+S A$ax5043wrfifo$3298 Def000023
+S A$ax5043wrfifo$3289 Def00001C
+S A$ax5043wrfifo$3299 Def000025
+S C$ax5043wrfifo.c$10$0$0 Def000000
+S C$ax5043wrfifo.c$75$1$66 Def000000
+S C$ax5043wrfifo.c$76$1$66 Def000056
+S G$ax5043_writefifo$0$0 Def000000
+S _ax5043_writefifo Def000000
+S XG$ax5043_writefifo$0$0 Def000056
+A CONST size 0 flags 20 addr 0
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+A CABS size 0 flags 28 addr 0
+T 00 00 00
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+
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+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
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+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5043regs
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5043regs
+
+
+
+
+ax5051comminit
+
+;!FILE libmf/ax5051comminit.asm
+XH3
+H 1A areas 423 global symbols
+M ax5051comminit
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$ax5051comminit.c$8$0$0 Def000000
+S _ax5051_comminit Def000000
+S XG$ax5051_comminit$0$0 Def000026
+S A$ax5051comminit$1660 Def00000F
+S A$ax5051comminit$1670 Def00001D
+S A$ax5051comminit$1661 Def000012
+S A$ax5051comminit$1652 Def000006
+S A$ax5051comminit$1671 Def00001E
+S A$ax5051comminit$1662 Def000014
+S A$ax5051comminit$1653 Def000009
+S A$ax5051comminit$1681 Def000026
+S A$ax5051comminit$1672 Def00001F
+S A$ax5051comminit$1663 Def000015
+S A$ax5051comminit$1654 Def00000B
+S A$ax5051comminit$1673 Def000020
+S A$ax5051comminit$1664 Def000016
+S A$ax5051comminit$1646 Def000000
+S A$ax5051comminit$1665 Def000017
+S A$ax5051comminit$1657 Def00000C
+S A$ax5051comminit$1676 Def000021
+S A$ax5051comminit$1649 Def000003
+S A$ax5051comminit$1677 Def000024
+S A$ax5051comminit$1668 Def000018
+S A$ax5051comminit$1678 Def000025
+S A$ax5051comminit$1669 Def00001B
+S C$ax5051comminit.c$10$1$66 Def000000
+S C$ax5051comminit.c$11$1$66 Def000003
+S C$ax5051comminit.c$12$1$66 Def000006
+S C$ax5051comminit.c$13$1$66 Def00000C
+S C$ax5051comminit.c$23$1$66 Def000021
+S C$ax5051comminit.c$24$1$66 Def000026
+S C$ax5051comminit.c$15$1$66 Def00000F
+S C$ax5051comminit.c$16$1$66 Def000018
+S G$ax5051_comminit$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
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+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
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+T 00 00 0D B1 00 90 70 40 74 05 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 26 22
+R 00 00 00 16
+
+
+M:ax5051comminit
+F:G$ax5051_comminit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
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+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
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+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051commslpexit
+
+;!FILE libmf/ax5051commslpexit.asm
+XH3
+H 1A areas 425 global symbols
+M ax5051commslpexit
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _ax5051_probeirq Ref000000
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
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+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
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+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
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+S C$ax5051commslpexit.c$15$1$66 Def000012
+S C$ax5051commslpexit.c$25$1$66 Def000027
+S C$ax5051commslpexit.c$16$1$66 Def00001B
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+S A$ax5051commslpexit$1683 Def000027
+S A$ax5051commslpexit$1674 Def000020
+S A$ax5051commslpexit$1665 Def000015
+S A$ax5051commslpexit$1656 Def00000B
+S A$ax5051commslpexit$1647 Def000000
+S A$ax5051commslpexit$1675 Def000021
+S A$ax5051commslpexit$1666 Def000017
+S A$ax5051commslpexit$1657 Def00000D
+S A$ax5051commslpexit$1676 Def000022
+S A$ax5051commslpexit$1667 Def000018
+S A$ax5051commslpexit$1658 Def00000E
+S A$ax5051commslpexit$1677 Def000023
+S A$ax5051commslpexit$1668 Def000019
+S A$ax5051commslpexit$1669 Def00001A
+S C$ax5051commslpexit.c$10$1$66 Def000000
+S C$ax5051commslpexit.c$11$1$66 Def000003
+S C$ax5051commslpexit.c$12$1$66 Def000006
+S C$ax5051commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
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+
+
+M:ax5051commslpexit
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+S:G$random_seed$0$0({2}SI:U),E,0,0
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+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051reset
+
+;!FILE libmf/ax5051reset.asm
+XH3
+H 1A areas 4F0 global symbols
+M ax5051reset
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13A flags 20 addr 0
+S C$ax5051reset.c$8$0$0 Def000000
+S _ax5051_reset Def000000
+S _ax5051_probeirq Def000088
+S XG$ax5051_reset$0$0 Def000087
+S XG$ax5051_probeirq$0$0 Def000139
+S A$ax5051reset$1800 Def000090
+S A$ax5051reset$1710 Def000042
+S A$ax5051reset$1701 Def000035
+S A$ax5051reset$1810 Def00009A
+S A$ax5051reset$1720 Def00004B
+S A$ax5051reset$1702 Def000038
+S A$ax5051reset$1910 Def0000F7
+S A$ax5051reset$1820 Def0000A4
+S A$ax5051reset$1811 Def00009C
+S A$ax5051reset$1721 Def00004C
+S A$ax5051reset$1920 Def000106
+S A$ax5051reset$1911 Def0000F8
+S A$ax5051reset$1902 Def0000EC
+S A$ax5051reset$1830 Def0000AE
+S A$ax5051reset$1821 Def0000A6
+S A$ax5051reset$1812 Def00009D
+S A$ax5051reset$1803 Def000092
+S A$ax5051reset$1731 Def000056
+S A$ax5051reset$1722 Def00004F
+S A$ax5051reset$1704 Def00003A
+S A$ax5051reset$1930 Def000114
+S A$ax5051reset$1921 Def000107
+S A$ax5051reset$1912 Def0000FB
+S A$ax5051reset$1903 Def0000EF
+S A$ax5051reset$1840 Def0000B8
+S A$ax5051reset$1831 Def0000AF
+S A$ax5051reset$1822 Def0000A8
+S A$ax5051reset$1750 Def00006C
+S A$ax5051reset$1732 Def000059
+S A$ax5051reset$1714 Def000044
+S A$ax5051reset$1705 Def00003D
+S A$ax5051reset$1660 Def00000C
+S C$ax5051reset.c$111$1$68 Def000117
+S A$ax5051reset$1940 Def00011C
+S A$ax5051reset$1931 Def000115
+S A$ax5051reset$1913 Def0000FE
+S A$ax5051reset$1904 Def0000F1
+S A$ax5051reset$1850 Def0000C2
+S A$ax5051reset$1841 Def0000BB
+S A$ax5051reset$1832 Def0000B0
+S A$ax5051reset$1760 Def000077
+S A$ax5051reset$1733 Def00005B
+S A$ax5051reset$1715 Def000047
+S A$ax5051reset$1670 Def00001A
+S A$ax5051reset$1652 Def000003
+S C$ax5051reset.c$112$1$68 Def00011C
+S C$ax5051reset.c$103$1$68 Def0000EA
+S A$ax5051reset$1941 Def00011F
+S A$ax5051reset$1932 Def000116
+S A$ax5051reset$1914 Def0000FF
+S A$ax5051reset$1905 Def0000F2
+S A$ax5051reset$1860 Def0000CB
+S A$ax5051reset$1851 Def0000C5
+S A$ax5051reset$1815 Def00009E
+S A$ax5051reset$1806 Def000094
+S A$ax5051reset$1743 Def000063
+S A$ax5051reset$1716 Def000049
+S A$ax5051reset$1680 Def000025
+S A$ax5051reset$1671 Def00001B
+S C$ax5051reset.c$113$1$68 Def00012B
+S A$ax5051reset$1960 Def000134
+S A$ax5051reset$1951 Def00012B
+S A$ax5051reset$1942 Def000120
+S A$ax5051reset$1924 Def000108
+S A$ax5051reset$1915 Def000100
+S A$ax5051reset$1852 Def0000C6
+S A$ax5051reset$1825 Def0000A9
+S A$ax5051reset$1816 Def0000A1
+S A$ax5051reset$1753 Def00006D
+S A$ax5051reset$1744 Def000066
+S A$ax5051reset$1726 Def000051
+S A$ax5051reset$1690 Def00002E
+S A$ax5051reset$1681 Def000026
+S A$ax5051reset$1672 Def00001C
+S A$ax5051reset$1663 Def00000F
+S C$ax5051reset.c$105$1$68 Def0000EC
+S A$ax5051reset$1952 Def00012C
+S A$ax5051reset$1943 Def000121
+S A$ax5051reset$1925 Def00010B
+S A$ax5051reset$1880 Def0000DD
+S A$ax5051reset$1853 Def0000C7
+S A$ax5051reset$1835 Def0000B2
+S A$ax5051reset$1826 Def0000AB
+S A$ax5051reset$1817 Def0000A3
+S A$ax5051reset$1763 Def000078
+S A$ax5051reset$1754 Def000070
+S A$ax5051reset$1736 Def00005C
+S A$ax5051reset$1727 Def000054
+S A$ax5051reset$1709 Def00003F
+S A$ax5051reset$1673 Def00001D
+S A$ax5051reset$1664 Def000012
+S A$ax5051reset$1655 Def000006
+S C$ax5051reset.c$115$1$68 Def00012E
+S C$ax5051reset.c$106$1$68 Def0000F3
+S A$ax5051reset$1944 Def000124
+S A$ax5051reset$1935 Def000117
+S A$ax5051reset$1926 Def00010C
+S A$ax5051reset$1908 Def0000F3
+S A$ax5051reset$1890 Def0000E4
+S A$ax5051reset$1881 Def0000DE
+S A$ax5051reset$1854 Def0000C9
+S A$ax5051reset$1845 Def0000BD
+S A$ax5051reset$1836 Def0000B5
+S A$ax5051reset$1809 Def000097
+S A$ax5051reset$1773 Def000084
+S A$ax5051reset$1764 Def00007B
+S A$ax5051reset$1755 Def000071
+S A$ax5051reset$1737 Def00005D
+S A$ax5051reset$1719 Def00004A
+S A$ax5051reset$1665 Def000014
+S A$ax5051reset$1656 Def000009
+S C$ax5051reset.c$116$1$68 Def000134
+S A$ax5051reset$1963 Def000136
+S A$ax5051reset$1945 Def000127
+S A$ax5051reset$1936 Def00011A
+S A$ax5051reset$1927 Def00010D
+S A$ax5051reset$1918 Def000101
+S A$ax5051reset$1909 Def0000F6
+S A$ax5051reset$1864 Def0000CD
+S A$ax5051reset$1855 Def0000CA
+S A$ax5051reset$1846 Def0000C0
+S A$ax5051reset$1837 Def0000B7
+S A$ax5051reset$1765 Def00007D
+S A$ax5051reset$1738 Def00005E
+S A$ax5051reset$1693 Def00002F
+S A$ax5051reset$1684 Def000027
+S A$ax5051reset$1657 Def00000B
+S C$ax5051reset.c$117$1$68 Def000136
+S C$ax5051reset.c$108$1$68 Def000101
+S A$ax5051reset$1955 Def00012E
+S A$ax5051reset$1946 Def000128
+S A$ax5051reset$1937 Def00011B
+S A$ax5051reset$1928 Def000110
+S A$ax5051reset$1919 Def000104
+S A$ax5051reset$1874 Def0000D6
+S A$ax5051reset$1865 Def0000D0
+S A$ax5051reset$1829 Def0000AC
+S A$ax5051reset$1748 Def000068
+S A$ax5051reset$1739 Def000061
+S A$ax5051reset$1694 Def000032
+S A$ax5051reset$1685 Def00002A
+S A$ax5051reset$1676 Def00001E
+S A$ax5051reset$1649 Def000000
+S C$ax5051reset.c$118$1$68 Def000139
+S C$ax5051reset.c$109$1$68 Def000108
+S A$ax5051reset$1956 Def000130
+S A$ax5051reset$1947 Def000129
+S A$ax5051reset$1929 Def000113
+S A$ax5051reset$1884 Def0000DF
+S A$ax5051reset$1866 Def0000D1
+S A$ax5051reset$1794 Def000088
+S A$ax5051reset$1758 Def000072
+S A$ax5051reset$1749 Def00006B
+S A$ax5051reset$1686 Def00002C
+S A$ax5051reset$1677 Def000021
+S A$ax5051reset$1668 Def000015
+S A$ax5051reset$1957 Def000132
+S A$ax5051reset$1948 Def00012A
+S A$ax5051reset$1894 Def0000E6
+S A$ax5051reset$1867 Def0000D2
+S A$ax5051reset$1795 Def00008B
+S A$ax5051reset$1777 Def000087
+S A$ax5051reset$1768 Def00007F
+S A$ax5051reset$1759 Def000075
+S A$ax5051reset$1678 Def000023
+S A$ax5051reset$1669 Def000018
+S A$ax5051reset$1967 Def000139
+S A$ax5051reset$1895 Def0000E7
+S A$ax5051reset$1868 Def0000D4
+S A$ax5051reset$1796 Def00008C
+S A$ax5051reset$1769 Def000082
+S A$ax5051reset$1697 Def000033
+S A$ax5051reset$1679 Def000024
+S A$ax5051reset$1896 Def0000E8
+S A$ax5051reset$1887 Def0000E1
+S A$ax5051reset$1878 Def0000D8
+S A$ax5051reset$1869 Def0000D5
+S A$ax5051reset$1797 Def00008D
+S A$ax5051reset$1698 Def000034
+S A$ax5051reset$1689 Def00002D
+S A$ax5051reset$1879 Def0000DB
+S C$ax5051reset.c$20$1$66 Def00000F
+S A$ax5051reset$1899 Def0000EA
+S C$ax5051reset.c$12$1$66 Def000000
+S C$ax5051reset.c$22$1$66 Def000015
+S C$ax5051reset.c$13$1$66 Def000003
+S C$ax5051reset.c$23$1$66 Def00001E
+S C$ax5051reset.c$60$1$66 Def000072
+S C$ax5051reset.c$51$1$66 Def000044
+S C$ax5051reset.c$42$1$66 Def00002F
+S C$ax5051reset.c$61$1$66 Def000078
+S C$ax5051reset.c$52$1$66 Def00004A
+S C$ax5051reset.c$43$1$66 Def000033
+S C$ax5051reset.c$62$1$66 Def00007F
+S C$ax5051reset.c$53$1$66 Def000051
+S C$ax5051reset.c$35$1$66 Def000027
+S C$ax5051reset.c$17$1$66 Def000006
+S C$ax5051reset.c$70$1$68 Def000088
+S C$ax5051reset.c$63$1$66 Def000084
+S C$ax5051reset.c$54$1$66 Def000056
+S C$ax5051reset.c$45$1$66 Def000035
+S C$ax5051reset.c$36$1$66 Def00002D
+S C$ax5051reset.c$80$1$68 Def0000B8
+S C$ax5051reset.c$71$1$68 Def000090
+S C$ax5051reset.c$64$1$66 Def000087
+S C$ax5051reset.c$55$1$66 Def00005C
+S C$ax5051reset.c$46$1$66 Def00003F
+S C$ax5051reset.c$19$1$66 Def00000C
+S C$ax5051reset.c$72$1$68 Def000092
+S C$ax5051reset.c$56$1$66 Def000063
+S C$ax5051reset.c$73$1$68 Def000094
+S C$ax5051reset.c$81$2$69 Def0000BD
+S C$ax5051reset.c$74$1$68 Def000097
+S C$ax5051reset.c$67$1$66 Def000088
+S C$ax5051reset.c$58$1$66 Def000068
+S C$ax5051reset.c$91$2$69 Def0000D8
+S C$ax5051reset.c$82$2$69 Def0000C2
+S C$ax5051reset.c$75$1$68 Def00009E
+S C$ax5051reset.c$59$1$66 Def00006D
+S C$ax5051reset.c$94$1$68 Def0000E4
+S C$ax5051reset.c$92$2$69 Def0000DF
+S C$ax5051reset.c$83$2$69 Def0000CB
+S C$ax5051reset.c$76$1$68 Def0000A4
+S C$ax5051reset.c$95$1$68 Def0000E6
+S C$ax5051reset.c$93$2$69 Def0000E1
+S C$ax5051reset.c$77$1$68 Def0000A9
+S C$ax5051reset.c$85$2$69 Def0000CB
+S C$ax5051reset.c$78$1$68 Def0000AC
+S G$ax5051_reset$0$0 Def000000
+S C$ax5051reset.c$86$2$69 Def0000CD
+S C$ax5051reset.c$79$1$68 Def0000B2
+S G$ax5051_probeirq$0$0 Def000088
+S C$ax5051reset.c$87$2$69 Def0000D6
+S C$ax5051reset.c$89$2$69 Def0000D6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 40 00 E0 E0
+R 00 00 00 16
+T 00 00 34 FF BF 16 02 80 0A
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A BF 14 02 80 05
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F 75 82 01 80 43
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 75 82 02 80 31
+R 00 00 00 16
+T 00 00 56
+R 00 00 00 16
+T 00 00 56 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 75 82 02 80 1F
+R 00 00 00 16
+T 00 00 68
+R 00 00 00 16
+T 00 00 68 90 40 08 E4 F0 90 40 72 04 F0 90 40 7D
+R 00 00 00 16
+T 00 00 75 74 35 F0 12 00 88 E5 82 60 05 75 82 03
+R 00 00 00 16 00 07 00 16
+T 00 00 82 80 03
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 75 82 00
+R 00 00 00 16
+T 00 00 87
+R 00 00 00 16
+T 00 00 87 22
+R 00 00 00 16
+T 00 00 88
+R 00 00 00 16
+T 00 00 88 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 95 8C EB 90 40 0C 74 D0 4F F0 90 40 0D 74
+R 00 00 00 16
+T 00 00 A2 F2 F0 74 60 55 8D FD 74 F0 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 AF FC 52 05 90 40 0D 74 D0 F0 BD 20 02 80
+R 00 00 00 16
+T 00 00 BC 05
+R 00 00 00 16
+T 00 00 BD
+R 00 00 00 16
+T 00 00 BD BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 C2
+R 00 00 00 16
+T 00 00 C2 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 CD
+R 00 00 00 16
+T 00 00 CD 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 90 40 0C 74 A0 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 E5 53
+R 00 00 00 16
+T 00 00 E6
+R 00 00 00 16
+T 00 00 E6 ED F4 52 8C C2 AF 90 40 0C 74 C0 4F F0
+R 00 00 00 16
+T 00 00 F3 90 40 0E E0 FC 53 04 01 90 40 0D E0 4C
+R 00 00 00 16
+T 00 01 00 F0 90 40 0C 74 80 4F F0 90 40 0E E0 FC
+R 00 00 00 16
+T 00 01 0D 53 04 04 90 40 0D E0 FB 4C F0 90 40 0C
+R 00 00 00 16
+T 00 01 1A EF F0 90 40 0E E0 FF 53 07 08 90 40 0D
+R 00 00 00 16
+T 00 01 27 E0 FC 4F F0 ED 42 A8 74 DF 45 8D 52 8C
+R 00 00 00 16
+T 00 01 34 8E A8 75 82 00
+R 00 00 00 16
+T 00 01 39
+R 00 00 00 16
+T 00 01 39 22
+R 00 00 00 16
+
+
+M:ax5051reset
+F:G$ax5051_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5051reset.ax5051_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5051_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5051reset.ax5051_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5051reset.ax5051_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5051reset.ax5051_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051deepsleep
+
+XH3
+H 1A areas 401 global symbols
+M ax5051deepsleep
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5051deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051rclkena
+
+;!FILE libmf/ax5051rclkena.asm
+XH3
+H 1A areas 433 global symbols
+M ax5051rclkena
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3D flags 20 addr 0
+S G$ax5051_rclk_enable$0$0 Def000000
+S _ax5051_rclk_enable Def000000
+S A$ax5051rclkena$1700 Def000036
+S A$ax5051rclkena$1701 Def000038
+S A$ax5051rclkena$1705 Def000039
+S A$ax5051rclkena$1660 Def000009
+S A$ax5051rclkena$1651 Def000002
+S A$ax5051rclkena$1706 Def00003A
+S A$ax5051rclkena$1670 Def000012
+S A$ax5051rclkena$1661 Def00000A
+S A$ax5051rclkena$1680 Def000021
+S A$ax5051rclkena$1662 Def00000C
+S A$ax5051rclkena$1653 Def000005
+S A$ax5051rclkena$1690 Def000029
+S A$ax5051rclkena$1709 Def00003C
+S A$ax5051rclkena$1691 Def00002A
+S A$ax5051rclkena$1673 Def000014
+S A$ax5051rclkena$1692 Def00002C
+S A$ax5051rclkena$1683 Def000022
+S A$ax5051rclkena$1674 Def000017
+S A$ax5051rclkena$1665 Def00000D
+S A$ax5051rclkena$1656 Def000007
+S A$ax5051rclkena$1693 Def00002E
+S A$ax5051rclkena$1675 Def000018
+S A$ax5051rclkena$1666 Def00000F
+S A$ax5051rclkena$1648 Def000000
+S XG$ax5051_rclk_enable$0$0 Def00003C
+S A$ax5051rclkena$1676 Def000019
+S A$ax5051rclkena$1667 Def000011
+S A$ax5051rclkena$1686 Def000025
+S A$ax5051rclkena$1677 Def00001C
+S A$ax5051rclkena$1687 Def000028
+S A$ax5051rclkena$1678 Def00001F
+S A$ax5051rclkena$1697 Def000030
+S A$ax5051rclkena$1679 Def000020
+S C$ax5051rclkena.c$10$1$64 Def000009
+S A$ax5051rclkena$1698 Def000032
+S C$ax5051rclkena.c$11$1$64 Def00000D
+S A$ax5051rclkena$1699 Def000033
+S C$ax5051rclkena.c$12$1$64 Def000012
+S C$ax5051rclkena.c$13$1$64 Def000014
+S C$ax5051rclkena.c$14$1$64 Def000022
+S C$ax5051rclkena.c$15$1$64 Def000025
+S C$ax5051rclkena.c$16$1$64 Def000029
+S C$ax5051rclkena.c$17$1$64 Def000030
+S C$ax5051rclkena.c$18$1$64 Def000039
+S C$ax5051rclkena.c$19$1$64 Def00003C
+S C$ax5051rclkena.c$8$1$64 Def000002
+S C$ax5051rclkena.c$9$1$64 Def000007
+S C$ax5051rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 09
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rclkena
+F:G$ax5051_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rclkena.ax5051_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5051rclkena.ax5051_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5051rclkena.ax5051_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
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+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$XPAGE$0$0({1}SC:U),I,0,0
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+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
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+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
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+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC0PIN$0$0({1}SC:U),I,0,0
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+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
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+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_7$0$0({1}SX:U),J,0,0
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+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
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+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5051rclkdis
+
+;!FILE libmf/ax5051rclkdis.asm
+XH3
+H 1A areas 428 global symbols
+M ax5051rclkdis
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S _ax5051_rclk_disable Def000000
+S C$ax5051rclkdis.c$8$1$64 Def000000
+S C$ax5051rclkdis.c$9$1$64 Def000005
+S C$ax5051rclkdis.c$5$0$0 Def000000
+S XG$ax5051_rclk_disable$0$0 Def00002B
+S A$ax5051rclkdis$1650 Def000002
+S A$ax5051rclkdis$1660 Def00000A
+S A$ax5051rclkdis$1651 Def000004
+S A$ax5051rclkdis$1670 Def000018
+S A$ax5051rclkdis$1661 Def00000D
+S A$ax5051rclkdis$1680 Def000021
+S A$ax5051rclkdis$1671 Def000019
+S A$ax5051rclkdis$1662 Def00000E
+S A$ax5051rclkdis$1681 Def000024
+S A$ax5051rclkdis$1663 Def00000F
+S A$ax5051rclkdis$1654 Def000005
+S A$ax5051rclkdis$1691 Def00002B
+S A$ax5051rclkdis$1682 Def000026
+S A$ax5051rclkdis$1664 Def000011
+S A$ax5051rclkdis$1683 Def000027
+S A$ax5051rclkdis$1674 Def00001A
+S A$ax5051rclkdis$1665 Def000012
+S A$ax5051rclkdis$1675 Def00001C
+S A$ax5051rclkdis$1666 Def000014
+S A$ax5051rclkdis$1657 Def000007
+S A$ax5051rclkdis$1676 Def00001D
+S A$ax5051rclkdis$1649 Def000000
+S A$ax5051rclkdis$1677 Def00001E
+S A$ax5051rclkdis$1687 Def000028
+S A$ax5051rclkdis$1669 Def000015
+S A$ax5051rclkdis$1688 Def000029
+S C$ax5051rclkdis.c$10$1$64 Def000007
+S C$ax5051rclkdis.c$11$1$64 Def00000A
+S C$ax5051rclkdis.c$12$1$64 Def000015
+S C$ax5051rclkdis.c$13$1$64 Def00001A
+S C$ax5051rclkdis.c$14$1$64 Def000021
+S C$ax5051rclkdis.c$15$1$64 Def000028
+S G$ax5051_rclk_disable$0$0 Def000000
+S C$ax5051rclkdis.c$16$1$64 Def00002B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 74 0F 5E FD BD 05 07 90 40 02 74 F0 5E
+R 00 00 00 16
+T 00 00 27 F0
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rclkdis
+F:G$ax5051_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rclkdis.ax5051_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5051rclkdis.ax5051_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5051rdfifo
+
+;!FILE libmf/ax5051rdfifo.asm
+XH3
+H 1A areas 439 global symbols
+M ax5051rdfifo
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S A$ax5051rdfifo$1699 Def000050
+S C$ax5051rdfifo.c$10$0$0 Def000000
+S C$ax5051rdfifo.c$74$1$66 Def000000
+S C$ax5051rdfifo.c$75$1$66 Def000054
+S G$ax5051_readfifo$0$0 Def000000
+S _ax5051_readfifo Def000000
+S XG$ax5051_readfifo$0$0 Def000054
+S A$ax5051rdfifo$1700 Def000051
+S A$ax5051rdfifo$1701 Def000053
+S A$ax5051rdfifo$1650 Def00000C
+S A$ax5051rdfifo$1660 Def00001C
+S A$ax5051rdfifo$1651 Def00000F
+S A$ax5051rdfifo$1670 Def000025
+S A$ax5051rdfifo$1652 Def000011
+S A$ax5051rdfifo$1643 Def000000
+S A$ax5051rdfifo$1680 Def000034
+S A$ax5051rdfifo$1671 Def000027
+S A$ax5051rdfifo$1653 Def000014
+S A$ax5051rdfifo$1644 Def000002
+S A$ax5051rdfifo$1690 Def000043
+S A$ax5051rdfifo$1681 Def000036
+S A$ax5051rdfifo$1672 Def000028
+S A$ax5051rdfifo$1663 Def00001D
+S A$ax5051rdfifo$1645 Def000004
+S A$ax5051rdfifo$1691 Def000045
+S A$ax5051rdfifo$1682 Def000038
+S A$ax5051rdfifo$1673 Def00002A
+S A$ax5051rdfifo$1664 Def00001E
+S A$ax5051rdfifo$1655 Def000017
+S A$ax5051rdfifo$1646 Def000005
+S A$ax5051rdfifo$1692 Def000048
+S A$ax5051rdfifo$1683 Def000039
+S A$ax5051rdfifo$1674 Def00002C
+S A$ax5051rdfifo$1665 Def00001F
+S A$ax5051rdfifo$1656 Def000018
+S A$ax5051rdfifo$1647 Def000006
+S A$ax5051rdfifo$1684 Def00003B
+S A$ax5051rdfifo$1675 Def00002F
+S A$ax5051rdfifo$1666 Def000020
+S A$ax5051rdfifo$1657 Def000019
+S A$ax5051rdfifo$1648 Def000008
+S A$ax5051rdfifo$1694 Def00004A
+S A$ax5051rdfifo$1667 Def000022
+S A$ax5051rdfifo$1658 Def00001A
+S A$ax5051rdfifo$1649 Def000009
+S A$ax5051rdfifo$1686 Def00003C
+S A$ax5051rdfifo$1677 Def000031
+S A$ax5051rdfifo$1696 Def00004B
+S A$ax5051rdfifo$1687 Def00003E
+S A$ax5051rdfifo$1678 Def000032
+S A$ax5051rdfifo$1669 Def000023
+S A$ax5051rdfifo$1697 Def00004C
+S A$ax5051rdfifo$1688 Def000040
+S A$ax5051rdfifo$1679 Def000033
+S A$ax5051rdfifo$1698 Def00004E
+S A$ax5051rdfifo$1689 Def000041
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
+T 00 00 0D F6 14 A8 82 90 40 05 20 F5 06
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 E0 F6 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D E0 F2 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 05
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E2 F0 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 05
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E2 A3 DF FC 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rdfifo
+F:G$ax5051_readfifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rdfifo.ax5051_readfifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5051rdfifo.ax5051_readfifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051wrfifo
+
+;!FILE libmf/ax5051wrfifo.asm
+XH3
+H 1A areas 43B global symbols
+M ax5051wrfifo
+O -mmcs51 --model-small
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S A$ax5051wrfifo$1700 Def000052
+S A$ax5051wrfifo$1701 Def000053
+S A$ax5051wrfifo$1702 Def000055
+S A$ax5051wrfifo$1650 Def00000C
+S A$ax5051wrfifo$1660 Def00001C
+S A$ax5051wrfifo$1651 Def00000F
+S A$ax5051wrfifo$1670 Def000025
+S A$ax5051wrfifo$1652 Def000011
+S A$ax5051wrfifo$1643 Def000000
+S A$ax5051wrfifo$1680 Def000034
+S A$ax5051wrfifo$1671 Def000027
+S A$ax5051wrfifo$1653 Def000014
+S A$ax5051wrfifo$1644 Def000002
+S A$ax5051wrfifo$1690 Def000043
+S A$ax5051wrfifo$1681 Def000036
+S A$ax5051wrfifo$1672 Def000028
+S A$ax5051wrfifo$1663 Def00001D
+S A$ax5051wrfifo$1645 Def000004
+S A$ax5051wrfifo$1691 Def000045
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+S A$ax5051wrfifo$1698 Def00004E
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+S C$ax5051wrfifo.c$75$1$66 Def000000
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+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
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+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
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+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
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+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
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+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
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+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5051regs
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5051regs
+
+
+
+
+ax8052regs
+
+XH3
+H 1A areas 1 global symbols
+M ax8052regs
+O -mmcs51 --model-small
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax8052regs
+
+
+
+
+
+
diff --git a/libs/libmf/sdcc/libmflarge.lib b/libs/libmf/sdcc/libmflarge.lib
new file mode 100644
index 00000000..ac2e1ecb
--- /dev/null
+++ b/libs/libmf/sdcc/libmflarge.lib
@@ -0,0 +1,309966 @@
+
+
+
+ 1594070
+
+lcdinit 9
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
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+_DMA0ADDR
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+Llcdinit.lcd_writecmd$cmd$1$57
+Llcdinit.lcd_write$v$1$54
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+A$lcdinit$1393
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+C$lcdinit.c$107$1$66
+A$lcdinit$1556
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+A$lcdinit$1493
+A$lcdinit$1367
+A$lcdinit$1358
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+A$lcdinit$1286
+A$lcdinit$1268
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+C$lcdinit.c$108$1$66
+A$lcdinit$1557
+A$lcdinit$1539
+A$lcdinit$1494
+A$lcdinit$1368
+A$lcdinit$1359
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+XG$lcd_writedata$0$0
+A$lcdinit$1549
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+A$lcdinit$1477
+A$lcdinit$1468
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+A$lcdinit$1387
+A$lcdinit$1369
+A$lcdinit$1288
+A$lcdinit$1487
+A$lcdinit$1199
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+A$lcdinit$1497
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+C$lcdinit.c$22$1$52
+C$lcdinit.c$20$2$53
+C$lcdinit.c$24$1$52
+C$lcdinit.c$51$1$62
+G$lcd_waitshort$0$0
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+C$lcdinit.c$52$1$62
+C$lcdinit.c$45$1$60
+C$lcdinit.c$30$2$56
+C$lcdinit.c$60$1$64
+C$lcdinit.c$53$1$62
+C$lcdinit.c$46$1$60
+C$lcdinit.c$33$1$55
+C$lcdinit.c$13$1$48
+C$lcdinit.c$11$2$49
+C$lcdinit.c$61$1$64
+C$lcdinit.c$47$1$60
+C$lcdinit.c$40$1$58
+C$lcdinit.c$34$1$55
+C$lcdinit.c$19$1$52
+C$lcdinit.c$14$1$48
+C$lcdinit.c$12$2$49
+C$lcdinit.c$62$1$64
+C$lcdinit.c$55$1$62
+C$lcdinit.c$41$1$58
+C$lcdinit.c$35$1$55
+C$lcdinit.c$26$1$55
+C$lcdinit.c$63$1$64
+C$lcdinit.c$49$1$60
+C$lcdinit.c$27$1$55
+C$lcdinit.c$16$1$48
+C$lcdinit.c$80$1$66
+C$lcdinit.c$64$1$64
+C$lcdinit.c$43$1$58
+C$lcdinit.c$37$1$55
+G$lcd_write$0$0
+_lcd_writecmd
+C$lcdinit.c$90$1$66
+C$lcdinit.c$81$1$66
+C$lcdinit.c$72$1$66
+C$lcdinit.c$65$1$64
+C$lcdinit.c$18$1$48
+C$lcdinit.c$82$1$66
+C$lcdinit.c$73$1$66
+C$lcdinit.c$66$1$64
+C$lcdinit.c$29$2$55
+C$lcdinit.c$92$1$66
+C$lcdinit.c$74$1$66
+C$lcdinit.c$67$1$64
+C$lcdinit.c$58$1$64
+C$lcdinit.c$93$1$66
+C$lcdinit.c$84$1$66
+C$lcdinit.c$75$1$66
+C$lcdinit.c$59$1$64
+C$lcdinit.c$76$1$66
+C$lcdinit.c$69$1$64
+C$lcdinit.c$39$1$58
+C$lcdinit.c$95$1$66
+C$lcdinit.c$86$1$66
+C$lcdinit.c$77$1$66
+_lcd_waitshort
+_lcd_waitlong
+C$lcdinit.c$96$1$66
+C$lcdinit.c$87$1$66
+C$lcdinit.c$78$1$66
+C$lcdinit.c$79$1$66
+C$lcdinit.c$98$1$66
+C$lcdinit.c$89$1$66
+G$lcd_init$0$0
+C$lcdinit.c$99$1$66
+XG$lcd_writecmd$0$0
+_lcd_write
+G$lcd_portinit$0$0
+C$lcdinit.c$7$1$48
+C$lcdinit.c$4$0$0
+C$lcdinit.c$8$2$48
+XG$lcd_waitshort$0$0
+XG$lcd_waitlong$0$0
+C$lcdinit.c$6$1$0
+C$lcdinit.c$9$2$49
+G$lcd_portoff$0$0
+_lcd_init
+XG$lcd_write$0$0
+G$lcd_writedata$0$0
+_lcd_portinit
+XG$lcd_init$0$0
+_lcd_portoff
+A$lcdinit$1200
+A$lcdinit$1210
+A$lcdinit$1201
+A$lcdinit$1220
+A$lcdinit$1500
+A$lcdinit$1302
+A$lcdinit$1230
+A$lcdinit$1221
+XG$lcd_portinit$0$0
+_lcd_writedata
+A$lcdinit$1501
+A$lcdinit$1420
+A$lcdinit$1411
+A$lcdinit$1330
+A$lcdinit$1312
+A$lcdinit$1303
+A$lcdinit$1231
+A$lcdinit$1222
+A$lcdinit$1204
+A$lcdinit$1511
+A$lcdinit$1340
+A$lcdinit$1331
+A$lcdinit$1313
+A$lcdinit$1304
+A$lcdinit$1250
+A$lcdinit$1232
+A$lcdinit$1521
+A$lcdinit$1341
+A$lcdinit$1332
+A$lcdinit$1260
+A$lcdinit$1251
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+A$lcdinit$1522
+A$lcdinit$1504
+A$lcdinit$1450
+A$lcdinit$1432
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+A$lcdinit$1360
+A$lcdinit$1342
+A$lcdinit$1261
+A$lcdinit$1234
+A$lcdinit$1225
+A$lcdinit$1216
+C$lcdinit.c$110$1$66
+C$lcdinit.c$101$1$66
+A$lcdinit$1550
+A$lcdinit$1532
+A$lcdinit$1514
+A$lcdinit$1370
+A$lcdinit$1361
+A$lcdinit$1316
+A$lcdinit$1307
+A$lcdinit$1271
+A$lcdinit$1226
+A$lcdinit$1217
+C$lcdinit.c$111$1$66
+C$lcdinit.c$102$1$66
+A$lcdinit$1560
+A$lcdinit$1542
+A$lcdinit$1515
+A$lcdinit$1371
+A$lcdinit$1335
+A$lcdinit$1308
+A$lcdinit$1254
+C$lcdinit.c$121$1$66
+A$lcdinit$1543
+A$lcdinit$1525
+A$lcdinit$1507
+A$lcdinit$1480
+A$lcdinit$1471
+A$lcdinit$1462
+A$lcdinit$1453
+A$lcdinit$1435
+A$lcdinit$1426
+A$lcdinit$1417
+A$lcdinit$1408
+A$lcdinit$1390
+A$lcdinit$1345
+A$lcdinit$1309
+A$lcdinit$1291
+A$lcdinit$1264
+A$lcdinit$1237
+C$lcdinit.c$113$1$66
+C$lcdinit.c$104$1$66
+XG$lcd_portoff$0$0
+A$lcdinit$1553
+A$lcdinit$1535
+A$lcdinit$1508
+A$lcdinit$1490
+A$lcdinit$1364
+A$lcdinit$1265
+A$lcdinit$1229
+C$lcdinit.c$114$1$66
+C$lcdinit.c$105$1$66
+A$lcdinit$1563
+A$lcdinit$1536
+A$lcdinit$1518
+A$lcdinit$1374
+A$lcdinit$1338
+A$lcdinit$1329
+A$lcdinit$1266
+
+
+
+lcdsetpos 40193
+.__.ABS.
+Llcdsetpos.lcd_setpos$v$1$47
+G$lcd_setpos$0$0
+C$lcdsetpos.c$5$1$48
+C$lcdsetpos.c$6$1$48
+C$lcdsetpos.c$3$0$0
+_lcd_setpos
+XG$lcd_setpos$0$0
+A$lcdsetpos$120
+A$lcdsetpos$121
+A$lcdsetpos$122
+A$lcdsetpos$123
+A$lcdsetpos$114
+A$lcdsetpos$124
+A$lcdsetpos$115
+A$lcdsetpos$125
+A$lcdsetpos$116
+A$lcdsetpos$117
+A$lcdsetpos$128
+
+
+
+lcdwrstr 43901
+.__.ABS.
+Llcdwrstr.lcd_writestr$ch$1$47
+XG$lcd_writestr$0$0
+A$lcdwrstr$120
+A$lcdwrstr$130
+A$lcdwrstr$121
+C$lcdwrstr.c$10$3$50
+A$lcdwrstr$140
+A$lcdwrstr$131
+A$lcdwrstr$122
+A$lcdwrstr$150
+A$lcdwrstr$141
+A$lcdwrstr$132
+A$lcdwrstr$123
+A$lcdwrstr$160
+A$lcdwrstr$151
+A$lcdwrstr$142
+A$lcdwrstr$133
+A$lcdwrstr$124
+C$lcdwrstr.c$12$3$51
+A$lcdwrstr$152
+A$lcdwrstr$143
+A$lcdwrstr$134
+A$lcdwrstr$125
+A$lcdwrstr$180
+A$lcdwrstr$153
+A$lcdwrstr$144
+A$lcdwrstr$135
+A$lcdwrstr$126
+A$lcdwrstr$117
+A$lcdwrstr$181
+A$lcdwrstr$172
+A$lcdwrstr$163
+A$lcdwrstr$154
+A$lcdwrstr$145
+A$lcdwrstr$136
+A$lcdwrstr$127
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+A$lcdwrstr$191
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+A$lcdwrstr$156
+A$lcdwrstr$147
+A$lcdwrstr$129
+A$lcdwrstr$184
+A$lcdwrstr$166
+A$lcdwrstr$148
+A$lcdwrstr$185
+A$lcdwrstr$167
+A$lcdwrstr$149
+A$lcdwrstr$186
+A$lcdwrstr$177
+A$lcdwrstr$168
+A$lcdwrstr$159
+C$lcdwrstr.c$16$1$48
+C$lcdwrstr.c$14$2$49
+A$lcdwrstr$187
+A$lcdwrstr$178
+A$lcdwrstr$188
+G$lcd_writestr$0$0
+C$lcdwrstr.c$3$0$0
+C$lcdwrstr.c$6$2$49
+C$lcdwrstr.c$7$2$49
+C$lcdwrstr.c$9$2$49
+_lcd_writestr
+
+
+
+lcdclear 49714
+.__.ABS.
+Llcdclear.lcd_clear$len$1$47
+_lcd_clear_PARM_2
+Llcdclear.lcd_clear$pos$1$47
+XG$lcd_clear$0$0
+A$lcdclear$130
+A$lcdclear$140
+A$lcdclear$122
+A$lcdclear$123
+A$lcdclear$133
+A$lcdclear$124
+A$lcdclear$161
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+A$lcdclear$134
+A$lcdclear$162
+A$lcdclear$144
+A$lcdclear$135
+C$lcdclear.c$10$1$48
+A$lcdclear$190
+A$lcdclear$163
+A$lcdclear$136
+A$lcdclear$127
+C$lcdclear.c$11$1$48
+A$lcdclear$182
+A$lcdclear$173
+A$lcdclear$164
+A$lcdclear$137
+A$lcdclear$128
+C$lcdclear.c$12$1$48
+A$lcdclear$183
+A$lcdclear$174
+A$lcdclear$156
+A$lcdclear$147
+A$lcdclear$129
+C$lcdclear.c$13$1$48
+A$lcdclear$175
+A$lcdclear$157
+C$lcdclear.c$14$1$48
+A$lcdclear$167
+A$lcdclear$158
+A$lcdclear$149
+C$lcdclear.c$15$1$48
+A$lcdclear$186
+A$lcdclear$168
+A$lcdclear$169
+A$lcdclear$179
+C$lcdclear.c$18$1$48
+C$lcdclear.c$16$2$49
+C$lcdclear.c$19$1$48
+C$lcdclear.c$17$2$49
+G$lcd_clear$0$0
+C$lcdclear.c$6$1$48
+C$lcdclear.c$3$0$0
+C$lcdclear.c$7$1$48
+C$lcdclear.c$8$1$48
+C$lcdclear.c$9$1$48
+_lcd_clear
+
+
+
+lcdclrdisp 55225
+.__.ABS.
+A$lcdclrdisp$111
+A$lcdclrdisp$112
+A$lcdclrdisp$115
+C$lcdclrdisp.c$5$1$48
+C$lcdclrdisp.c$6$1$48
+C$lcdclrdisp.c$3$0$0
+G$lcd_cleardisplay$0$0
+_lcd_cleardisplay
+XG$lcd_cleardisplay$0$0
+
+
+
+lcdwru16 58519
+.__.ABS.
+Llcdwru16.lcd_writeu16$val$1$47
+_lcd_writeu16_PARM_2
+_lcd_writeu16_PARM_3
+Llcdwru16.lcd_writeu16$pos$1$47
+Llcdwru16.lcd_writeu16$nrdig$1$47
+XG$lcd_writeu16$0$0
+A$lcdwru16$220
+A$lcdwru16$202
+A$lcdwru16$130
+A$lcdwru16$212
+A$lcdwru16$203
+A$lcdwru16$140
+A$lcdwru16$131
+A$lcdwru16$204
+A$lcdwru16$150
+A$lcdwru16$141
+A$lcdwru16$132
+A$lcdwru16$205
+A$lcdwru16$160
+A$lcdwru16$151
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+A$lcdwru16$215
+A$lcdwru16$206
+A$lcdwru16$170
+A$lcdwru16$161
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+A$lcdwru16$143
+A$lcdwru16$216
+A$lcdwru16$180
+A$lcdwru16$171
+A$lcdwru16$162
+A$lcdwru16$153
+A$lcdwru16$144
+A$lcdwru16$190
+A$lcdwru16$181
+A$lcdwru16$172
+A$lcdwru16$163
+A$lcdwru16$136
+A$lcdwru16$127
+A$lcdwru16$209
+A$lcdwru16$191
+A$lcdwru16$182
+A$lcdwru16$173
+A$lcdwru16$164
+A$lcdwru16$137
+A$lcdwru16$128
+C$lcdwru16.c$10$2$49
+A$lcdwru16$192
+A$lcdwru16$183
+A$lcdwru16$174
+A$lcdwru16$165
+A$lcdwru16$156
+A$lcdwru16$147
+A$lcdwru16$138
+A$lcdwru16$129
+C$lcdwru16.c$11$2$49
+A$lcdwru16$184
+A$lcdwru16$175
+A$lcdwru16$166
+A$lcdwru16$157
+A$lcdwru16$148
+A$lcdwru16$139
+C$lcdwru16.c$12$2$49
+A$lcdwru16$185
+A$lcdwru16$176
+A$lcdwru16$167
+A$lcdwru16$158
+A$lcdwru16$149
+C$lcdwru16.c$13$2$49
+A$lcdwru16$195
+A$lcdwru16$186
+A$lcdwru16$177
+A$lcdwru16$168
+A$lcdwru16$159
+C$lcdwru16.c$16$1$48
+C$lcdwru16.c$14$2$49
+A$lcdwru16$196
+A$lcdwru16$187
+A$lcdwru16$169
+A$lcdwru16$188
+A$lcdwru16$189
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+_lcd_writeu16
+
+
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+lcdwru32 65303
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+_lcd_writeu32
+
+
+
+lcdwrhexu16 73247
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+_lcd_writehexu16
+
+
+
+lcdwrhexu32 79899
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+_lcd_writehexu32
+
+
+
+lcduwrnum16 87983
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+
+
+
+lcduwrnum32 100352
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+_ADCCH3VAL1
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+_FRCOSCREF
+_EXTIRQ
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+
+
+
+dbglnktxbuf 196554
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+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
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+_DIRC
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+G$NVADDR0$0$0
+_XTALAMPL
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+_SPCLKSRC
+_E2IP_6
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+_OV
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+_ADCCH0VAL
+_OC0STATUS
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+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+_ADCCH2VAL
+_LPOSCPER
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+_IP_0
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+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
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+G$DMA0CONFIG$0$0
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+_LPOSCKFILT1
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
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+_PCON
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+_ADCTUNE1
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+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
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+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_dbglink_txbuffer
+C$dbglnktxbuf.c$5$1$59
+C$dbglnktxbuf.c$5$0$0
+Fdbglnktxbuf$dbglink_define_txbuffer$0$0
+XFdbglnktxbuf$dbglink_define_txbuffer$0$0
+
+
+
+dbglnkrxbuf 228270
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_dbglink_rxbuffer
+C$dbglnkrxbuf.c$5$1$59
+C$dbglnkrxbuf.c$5$0$0
+Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0
+XFdbglnkrxbuf$dbglink_define_rxbuffer$0$0
+
+
+
+dbglnktx 259986
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$dbglnktx.c$50$1$62
+C$dbglnktx.c$33$2$60
+C$dbglnktx.c$52$1$62
+C$dbglnktx.c$42$2$63
+C$dbglnktx.c$43$2$63
+C$dbglnktx.c$28$2$60
+C$dbglnktx.c$29$2$60
+_dbglink_tx
+C$dbglnktx.c$45$2$63
+C$dbglnktx.c$54$1$65
+C$dbglnktx.c$46$2$63
+XG$dbglink_wait_txfree$0$0
+C$dbglnktx.c$55$1$65
+C$dbglnktx.c$47$2$63
+C$dbglnktx.c$49$1$62
+C$dbglnktx.c$24$0$0
+C$dbglnktx.c$56$1$65
+C$dbglnktx.c$35$1$59
+C$dbglnktx.c$26$1$59
+C$dbglnktx.c$57$1$65
+C$dbglnktx.c$36$1$59
+XG$dbglink_wait_txdone$0$0
+C$dbglnktx.c$38$1$59
+XG$dbglink_tx$0$0
+A$dbglnktx$1300
+A$dbglnktx$1201
+A$dbglnktx$1310
+A$dbglnktx$1230
+A$dbglnktx$1221
+A$dbglnktx$1212
+A$dbglnktx$1303
+A$dbglnktx$1231
+A$dbglnktx$1222
+A$dbglnktx$1213
+A$dbglnktx$1204
+A$dbglnktx$1313
+A$dbglnktx$1304
+A$dbglnktx$1223
+A$dbglnktx$1214
+A$dbglnktx$1205
+G$dbglink_wait_txfree$0$0
+A$dbglnktx$1314
+A$dbglnktx$1251
+A$dbglnktx$1206
+A$dbglnktx$1315
+A$dbglnktx$1252
+A$dbglnktx$1234
+A$dbglnktx$1207
+A$dbglnktx$1307
+A$dbglnktx$1262
+A$dbglnktx$1253
+A$dbglnktx$1217
+A$dbglnktx$1208
+A$dbglnktx$1190
+A$dbglnktx$1308
+A$dbglnktx$1272
+A$dbglnktx$1263
+A$dbglnktx$1227
+A$dbglnktx$1209
+G$dbglink_wait_txdone$0$0
+A$dbglnktx$1318
+A$dbglnktx$1309
+A$dbglnktx$1282
+A$dbglnktx$1264
+A$dbglnktx$1228
+A$dbglnktx$1283
+A$dbglnktx$1229
+A$dbglnktx$1193
+A$dbglnktx$1194
+A$dbglnktx$1276
+A$dbglnktx$1267
+A$dbglnktx$1195
+A$dbglnktx$1286
+A$dbglnktx$1277
+A$dbglnktx$1268
+A$dbglnktx$1259
+A$dbglnktx$1187
+A$dbglnktx$1278
+A$dbglnktx$1269
+A$dbglnktx$1188
+G$dbglink_tx$0$0
+A$dbglnktx$1189
+_dbglink_wait_txfree
+A$dbglnktx$1299
+C$dbglnktx.c$31$2$60
+C$dbglnktx.c$40$1$62
+C$dbglnktx.c$32$2$60
+_dbglink_wait_txdone
+
+
+
+dbglnkrx 295099
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
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+
+
+
+dbglnkwrhexu16 328876
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+
+
+
+dbglnkwrhexu32 334940
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+
+
+
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+
+
+
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+
+
+crc8onewire 447263
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+_RADIODATA2
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+_RADIOFSTATADDR1
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+_INTCHGB
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+.__.ABS.
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+_EA
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+_OSCFORCERUN
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+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
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+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
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+
+
+
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+C$fmemset.c$10$0$0
+C$fmemset.c$61$1$28
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+A$fmemset$1210
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+A$fmemset$1211
+A$fmemset$1202
+
+
+
+fmemcpy 887923
+G$LPXOSCGM$0$0
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+_RADIOADDR1
+_RADIODATA2
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+_PINCHGC
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+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
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+_INTCHGA
+_SILICONREV
+_ADCCONV
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+_PINA_7
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+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
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+.__.ABS.
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+G$WTEVTA1$0$0
+_INTCHGC
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+_WTCNTA0
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+_B
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+_EA
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+_ACC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
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+G$RS0$0$0
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+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
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+G$B_5$0$0
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+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
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+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$fmemcpy$1320
+A$fmemcpy$1302
+A$fmemcpy$1230
+A$fmemcpy$1221
+A$fmemcpy$1212
+A$fmemcpy$1330
+A$fmemcpy$1321
+A$fmemcpy$1312
+A$fmemcpy$1303
+A$fmemcpy$1240
+A$fmemcpy$1231
+A$fmemcpy$1222
+A$fmemcpy$1340
+A$fmemcpy$1322
+A$fmemcpy$1313
+A$fmemcpy$1304
+A$fmemcpy$1232
+A$fmemcpy$1223
+A$fmemcpy$1214
+A$fmemcpy$1205
+A$fmemcpy$1341
+A$fmemcpy$1332
+A$fmemcpy$1314
+A$fmemcpy$1305
+A$fmemcpy$1260
+A$fmemcpy$1251
+A$fmemcpy$1242
+A$fmemcpy$1224
+A$fmemcpy$1215
+A$fmemcpy$1206
+A$fmemcpy$1342
+A$fmemcpy$1333
+A$fmemcpy$1324
+A$fmemcpy$1306
+A$fmemcpy$1261
+A$fmemcpy$1252
+A$fmemcpy$1243
+A$fmemcpy$1234
+A$fmemcpy$1216
+A$fmemcpy$1207
+G$fmemcpy$0$0
+A$fmemcpy$1343
+A$fmemcpy$1334
+A$fmemcpy$1325
+A$fmemcpy$1316
+A$fmemcpy$1307
+A$fmemcpy$1280
+A$fmemcpy$1271
+A$fmemcpy$1253
+A$fmemcpy$1244
+A$fmemcpy$1235
+A$fmemcpy$1226
+A$fmemcpy$1208
+A$fmemcpy$1190
+A$fmemcpy$1344
+A$fmemcpy$1335
+A$fmemcpy$1326
+A$fmemcpy$1317
+A$fmemcpy$1308
+A$fmemcpy$1281
+A$fmemcpy$1272
+A$fmemcpy$1263
+A$fmemcpy$1245
+A$fmemcpy$1236
+A$fmemcpy$1227
+A$fmemcpy$1218
+A$fmemcpy$1209
+A$fmemcpy$1191
+A$fmemcpy$1345
+A$fmemcpy$1336
+A$fmemcpy$1327
+A$fmemcpy$1318
+A$fmemcpy$1309
+A$fmemcpy$1291
+A$fmemcpy$1282
+A$fmemcpy$1273
+A$fmemcpy$1264
+A$fmemcpy$1255
+A$fmemcpy$1246
+A$fmemcpy$1237
+A$fmemcpy$1228
+A$fmemcpy$1219
+A$fmemcpy$1192
+A$fmemcpy$1183
+A$fmemcpy$1346
+A$fmemcpy$1337
+A$fmemcpy$1328
+A$fmemcpy$1319
+A$fmemcpy$1292
+A$fmemcpy$1283
+A$fmemcpy$1274
+A$fmemcpy$1265
+A$fmemcpy$1256
+A$fmemcpy$1247
+A$fmemcpy$1238
+A$fmemcpy$1229
+A$fmemcpy$1193
+A$fmemcpy$1184
+A$fmemcpy$1347
+A$fmemcpy$1338
+A$fmemcpy$1329
+A$fmemcpy$1293
+A$fmemcpy$1284
+A$fmemcpy$1275
+A$fmemcpy$1266
+A$fmemcpy$1257
+A$fmemcpy$1248
+A$fmemcpy$1239
+A$fmemcpy$1194
+A$fmemcpy$1185
+A$fmemcpy$1294
+A$fmemcpy$1285
+A$fmemcpy$1276
+A$fmemcpy$1267
+A$fmemcpy$1258
+A$fmemcpy$1249
+A$fmemcpy$1195
+A$fmemcpy$1186
+A$fmemcpy$1295
+A$fmemcpy$1286
+A$fmemcpy$1268
+A$fmemcpy$1259
+A$fmemcpy$1196
+A$fmemcpy$1187
+A$fmemcpy$1296
+A$fmemcpy$1287
+A$fmemcpy$1278
+A$fmemcpy$1269
+A$fmemcpy$1197
+A$fmemcpy$1188
+A$fmemcpy$1288
+A$fmemcpy$1279
+A$fmemcpy$1198
+A$fmemcpy$1189
+C$fmemcpy.c$184$1$28
+A$fmemcpy$1298
+A$fmemcpy$1289
+C$fmemcpy.c$185$1$28
+A$fmemcpy$1299
+_fmemcpy
+C$fmemcpy.c$10$0$0
+XG$fmemcpy$0$0
+A$fmemcpy$1200
+A$fmemcpy$1300
+A$fmemcpy$1210
+A$fmemcpy$1310
+A$fmemcpy$1301
+A$fmemcpy$1220
+A$fmemcpy$1211
+A$fmemcpy$1202
+
+
+
+delay 923687
+.__.ABS.
+C$delay.c$9$0$0
+G$delay$0$0
+A$delay$110
+A$delay$112
+A$delay$114
+A$delay$105
+_delay
+A$delay$115
+A$delay$106
+A$delay$116
+A$delay$107
+A$delay$117
+A$delay$109
+C$delay.c$23$1$28
+C$delay.c$24$1$28
+XG$delay$0$0
+
+
+
+random 926475
+.__.ABS.
+G$random_seed$0$0
+_random_seed
+G$random$0$0
+A$random$120
+A$random$130
+A$random$121
+A$random$131
+A$random$122
+A$random$132
+A$random$123
+A$random$114
+_random
+A$random$133
+A$random$124
+A$random$115
+A$random$134
+A$random$125
+A$random$116
+A$random$126
+A$random$117
+A$random$127
+A$random$118
+A$random$137
+A$random$128
+A$random$119
+A$random$129
+C$random.c$11$0$0
+C$random.c$35$1$28
+C$random.c$36$1$28
+XG$random$0$0
+
+
+
+sleep 929772
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$enter_sleep$0$0
+G$enter_sleep$0$0
+A$sleep$1180
+A$sleep$1171
+A$sleep$1190
+A$sleep$1181
+A$sleep$1172
+A$sleep$1182
+A$sleep$1173
+A$sleep$1183
+A$sleep$1174
+A$sleep$1184
+A$sleep$1175
+A$sleep$1185
+A$sleep$1176
+A$sleep$1186
+A$sleep$1177
+A$sleep$1187
+A$sleep$1178
+A$sleep$1188
+A$sleep$1179
+A$sleep$1189
+_enter_sleep
+C$sleep.c$33$1$28
+C$sleep.c$10$0$0
+C$sleep.c$34$1$28
+
+
+
+deepsleep 960369
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$enter_deepsleep$0$0
+A$deepsleep$1180
+A$deepsleep$1171
+A$deepsleep$1181
+A$deepsleep$1172
+A$deepsleep$1182
+A$deepsleep$1173
+A$deepsleep$1183
+A$deepsleep$1174
+A$deepsleep$1184
+A$deepsleep$1175
+A$deepsleep$1185
+A$deepsleep$1176
+A$deepsleep$1177
+A$deepsleep$1178
+A$deepsleep$1179
+_enter_deepsleep
+C$deepsleep.c$10$0$0
+XG$enter_deepsleep$0$0
+C$deepsleep.c$28$1$28
+C$deepsleep.c$29$1$28
+
+
+
+sleepcont 990914
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
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+_E2IP
+_P
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+_ADCCH3VAL1
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+_DPH
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_IE_0
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+_DMA1ADDR
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
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+_IE_3
+A$sleepcont$1220
+A$sleepcont$1230
+A$sleepcont$1221
+A$sleepcont$1231
+A$sleepcont$1222
+A$sleepcont$1232
+A$sleepcont$1223
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+A$sleepcont$1224
+A$sleepcont$1225
+A$sleepcont$1226
+A$sleepcont$1228
+A$sleepcont$1219
+XFsleepcont$dummy$0$0
+A$sleepcont$1229
+C$sleepcont.c$72$1$30
+_enter_sleep_cont
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+A$sleepcont$1180
+A$sleepcont$1171
+A$sleepcont$1190
+A$sleepcont$1181
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+A$sleepcont$1191
+A$sleepcont$1182
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+A$sleepcont$1192
+A$sleepcont$1183
+A$sleepcont$1174
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+A$sleepcont$1177
+A$sleepcont$1187
+A$sleepcont$1178
+A$sleepcont$1188
+A$sleepcont$1179
+A$sleepcont$1189
+C$sleepcont.c$71$1$30
+C$sleepcont.c$41$1$28
+C$sleepcont.c$13$0$0
+C$sleepcont.c$38$1$28
+C$sleepcont.c$39$1$28
+G$enter_sleep_cont$0$0
+
+
+
+standby 1022647
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
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+_FRCOSCKFILT0
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+_PCON
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+_T2PERIOD1
+_U0CTRL
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+_PINC_1
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+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINB_3
+_PINC_2
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+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
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+_PINC_5
+G$PINSEL$0$0
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+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
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+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+_WTCNTA0
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+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
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+G$DBGLNKBUF$0$0
+_WTCNTB1
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+_AC
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+_E2IE
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+_PORTA
+_T0CLKSRC
+_EA
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+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+_T1PERIOD
+_T2CLKSRC
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+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
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+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
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+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
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+G$IE_2$0$0
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+_EIE
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+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
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+G$E2IP_2$0$0
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+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
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+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
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+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
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+G$EIE_1$0$0
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+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
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+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
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+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+_PORTB_6
+_PORTC_5
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+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$enter_standby$0$0
+A$standby$1180
+A$standby$1171
+A$standby$1181
+A$standby$1172
+A$standby$1173
+A$standby$1174
+A$standby$1175
+A$standby$1176
+A$standby$1177
+A$standby$1178
+A$standby$1179
+_enter_standby
+C$standby.c$24$1$28
+C$standby.c$10$0$0
+C$standby.c$25$1$28
+XG$enter_standby$0$0
+
+
+
+resetcpu 1052969
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
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+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
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+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
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+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
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+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
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+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
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+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
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+_ADCTUNE0
+_PALTC
+_EIP_7
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
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+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
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+_IE_3
+A$resetcpu$1182
+A$resetcpu$1192
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+A$resetcpu$1189
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+C$resetcpu.c$13$1$28
+C$resetcpu.c$14$1$28
+C$resetcpu.c$10$0$0
+C$resetcpu.c$17$1$28
+C$resetcpu.c$18$1$28
+G$reset_cpu$0$0
+_reset_cpu
+XG$reset_cpu$0$0
+A$resetcpu$1181
+
+
+
+flashunlock 1083281
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$EIP_1$0$0
+G$NVDATA0$0$0
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+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
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+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$WDTRESET$0$0
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+_ADCCH0VAL
+_OC0STATUS
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+_ADCCH1VAL
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+_EIE_5
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+_ADCCH2VAL
+_LPOSCPER
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+G$XPAGE$0$0
+_ADCCH3VAL
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+_IP_1
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+_DPTR0
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+_T1MODE
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+_U0MODE
+_U1STATUS
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+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
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+_FRCOSCKFILT1
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+G$RADIOADDR0$0$0
+G$CLKCON$0$0
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+_LPOSCFREQ
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+_PCON
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+_ADCTUNE2
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+_F0
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+_F1
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+_T1PERIOD0
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+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
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+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
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+_FRCOSCKFILT
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINC_1
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+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINB_3
+_PINC_2
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+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
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+_WTCNTA0
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+G$IE$0$0
+_B
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+_PORTA
+_T0CLKSRC
+_EA
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+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+_T2CLKSRC
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+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$flash_unlock$0$0
+C$flashunlock.c$6$1$35
+C$flashunlock.c$7$1$35
+C$flashunlock.c$8$1$35
+C$flashunlock.c$9$1$35
+C$flashunlock.c$4$0$0
+_flash_unlock
+XG$flash_unlock$0$0
+A$flashunlock$1201
+A$flashunlock$1191
+A$flashunlock$1183
+A$flashunlock$1184
+A$flashunlock$1194
+A$flashunlock$1185
+A$flashunlock$1197
+A$flashunlock$1188
+A$flashunlock$1198
+C$flashunlock.c$10$1$35
+C$flashunlock.c$11$1$35
+
+
+
+flashlock 1114163
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+Fflashlock$flash_deviceid$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$flash_lock$0$0
+A$flashlock$1180
+A$flashlock$1183
+G$flash_lock$0$0
+C$flashlock.c$6$1$35
+C$flashlock.c$7$1$35
+C$flashlock.c$4$0$0
+_flash_lock
+
+
+
+flashwait 1144564
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+Fflashwait$flash_deviceid$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Lflashwait.flash_wait$timeout$1$34
+C$flashwait.c$8$1$0
+_flash_wait
+XG$flash_wait$0$0
+A$flashwait$1200
+A$flashwait$1201
+A$flashwait$1220
+A$flashwait$1211
+A$flashwait$1230
+A$flashwait$1221
+A$flashwait$1240
+A$flashwait$1233
+A$flashwait$1224
+A$flashwait$1206
+A$flashwait$1252
+A$flashwait$1243
+A$flashwait$1234
+A$flashwait$1225
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+A$flashwait$1208
+A$flashwait$1190
+A$flashwait$1191
+A$flashwait$1219
+A$flashwait$1192
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+A$flashwait$1248
+A$flashwait$1196
+A$flashwait$1187
+A$flashwait$1197
+A$flashwait$1188
+A$flashwait$1198
+A$flashwait$1189
+A$flashwait$1199
+C$flashwait.c$10$1$35
+C$flashwait.c$21$1$35
+C$flashwait.c$22$1$35
+C$flashwait.c$20$2$36
+C$flashwait.c$23$1$35
+C$flashwait.c$12$2$36
+C$flashwait.c$13$3$37
+C$flashwait.c$14$3$37
+C$flashwait.c$15$3$37
+C$flashwait.c$16$3$37
+C$flashwait.c$19$2$36
+C$flashwait.c$17$3$37
+C$flashwait.c$18$3$37
+G$flash_wait$0$0
+C$flashwait.c$9$1$35
+C$flashwait.c$4$0$0
+C$flashwait.c$7$1$0
+
+
+
+flashpgerase 1176819
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+Fflashpgerase$flash_deviceid$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Lflashpgerase.flash_pageerase$pgaddr$1$34
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+flashread 1240221
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+_ADCCH0VAL0
+_GPIOENABLE
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+
+
+
+flashcsec 1291302
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+
+
+
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+_DMA0ADDR1
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+_DMA1ADDR1
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+_WTEVTD1
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+_E2IP
+_P
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+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
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+_IC0CAPT1
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+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
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+_E2IE_2
+_RS1
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+_ADCCH0VAL1
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+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
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+_PORTA_2
+_PORTB_1
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+G$IE_7$0$0
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+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
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+G$SPCLKSRC$0$0
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+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
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+_PORTC_2
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+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
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+_PORTC_3
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
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+_WTEVTA
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+_DPH
+_RADIOSTAT1
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+_T2CNT1
+_WTEVTB
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+_CY
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+_PORTC_5
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+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$WTIRQEN$0$0
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+G$U0MODE$0$0
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+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
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+_FRCOSCFREQ1
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+_IE_2
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart_timer0_baud
+C$uarttimer0.c$9$0$0
+XG$uart_timer0_baud$0$0
+A$uarttimer0$1200
+A$uarttimer0$1300
+A$uarttimer0$1210
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+A$uarttimer0$1342
+A$uarttimer0$1333
+A$uarttimer0$1324
+A$uarttimer0$1270
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+A$uarttimer0$1376
+A$uarttimer0$1358
+A$uarttimer0$1349
+A$uarttimer0$1295
+A$uarttimer0$1286
+A$uarttimer0$1277
+A$uarttimer0$1268
+A$uarttimer0$1259
+A$uarttimer0$1187
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+A$uarttimer0$1467
+A$uarttimer0$1458
+A$uarttimer0$1449
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+A$uarttimer0$1377
+A$uarttimer0$1296
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+A$uarttimer0$1278
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+A$uarttimer0$1197
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+A$uarttimer0$1378
+A$uarttimer0$1369
+A$uarttimer0$1288
+A$uarttimer0$1279
+A$uarttimer0$1198
+C$uarttimer0.c$12$1$31
+A$uarttimer0$1496
+A$uarttimer0$1487
+A$uarttimer0$1478
+A$uarttimer0$1469
+A$uarttimer0$1379
+A$uarttimer0$1289
+A$uarttimer0$1199
+A$uarttimer0$1497
+A$uarttimer0$1488
+A$uarttimer0$1479
+A$uarttimer0$1398
+A$uarttimer0$1389
+A$uarttimer0$1299
+C$uarttimer0.c$13$2$31
+A$uarttimer0$1498
+A$uarttimer0$1489
+A$uarttimer0$1399
+A$uarttimer0$1499
+C$uarttimer0.c$43$1$31
+C$uarttimer0.c$34$1$31
+C$uarttimer0.c$20$3$34
+C$uarttimer0.c$14$2$32
+C$uarttimer0.c$44$1$31
+C$uarttimer0.c$24$2$32
+C$uarttimer0.c$21$3$34
+C$uarttimer0.c$45$1$31
+C$uarttimer0.c$36$1$31
+C$uarttimer0.c$22$3$34
+C$uarttimer0.c$46$1$31
+C$uarttimer0.c$37$1$31
+C$uarttimer0.c$30$3$36
+C$uarttimer0.c$15$3$33
+C$uarttimer0.c$40$2$37
+C$uarttimer0.c$31$3$36
+C$uarttimer0.c$16$3$33
+C$uarttimer0.c$41$2$37
+C$uarttimer0.c$39$1$31
+C$uarttimer0.c$32$3$36
+C$uarttimer0.c$19$2$32
+C$uarttimer0.c$17$3$33
+C$uarttimer0.c$29$2$32
+C$uarttimer0.c$25$3$35
+C$uarttimer0.c$26$3$35
+C$uarttimer0.c$11$1$0
+C$uarttimer0.c$27$3$35
+G$uart_timer0_baud$0$0
+
+
+
+uarttimer1 1337376
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
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+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+_LPXOSCGM
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+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
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+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
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+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
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+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
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+_DIRR
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+G$U0SHREG$0$0
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+G$ADCCONV$0$0
+_PALTA
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+G$PINB_7$0$0
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+_ADCTUNE2
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
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+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+C$uarttimer1.c$44$1$31
+C$uarttimer1.c$24$2$32
+C$uarttimer1.c$21$3$34
+C$uarttimer1.c$45$1$31
+C$uarttimer1.c$36$1$31
+C$uarttimer1.c$22$3$34
+C$uarttimer1.c$46$1$31
+C$uarttimer1.c$37$1$31
+C$uarttimer1.c$30$3$36
+C$uarttimer1.c$15$3$33
+C$uarttimer1.c$40$2$37
+C$uarttimer1.c$31$3$36
+C$uarttimer1.c$16$3$33
+C$uarttimer1.c$41$2$37
+C$uarttimer1.c$39$1$31
+C$uarttimer1.c$32$3$36
+C$uarttimer1.c$19$2$32
+C$uarttimer1.c$17$3$33
+C$uarttimer1.c$29$2$32
+C$uarttimer1.c$25$3$35
+C$uarttimer1.c$26$3$35
+C$uarttimer1.c$11$1$0
+C$uarttimer1.c$27$3$35
+G$uart_timer1_baud$0$0
+
+
+
+uarttimer2 1380460
+G$LPXOSCGM$0$0
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+_MISCCTRL
+_ANALOGCOMP
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+_RADIODATA2
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+.__.ABS.
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+G$_XPAGE$0$0
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+_OSCFORCERUN
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+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$B_5$0$0
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+G$CLKSTAT$0$0
+_ADCCLKSRC
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+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$ADCCH1VAL1$0$0
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+G$PORTA_3$0$0
+G$E2IE_4$0$0
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+G$ACC_2$0$0
+_RADIOFSTATADDR
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+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
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+_WTEVTC0
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+G$T1CNT0$0$0
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+_DMA0ADDR1
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+_DMA1ADDR1
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+_E2IP
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+_DPL1
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+_B_0
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+_WTCNTB
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+_EIE
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+__XPAGE
+_IC0CAPT0
+_B_3
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+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
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+_IC0CAPT1
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+_B_4
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+_RS0
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+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
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+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
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+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
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+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
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+_PORTC_3
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+_RADIOFDATAADDR1
+_RADIOSTAT0
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+_T2CNT0
+_WTEVTA
+_ACC_5
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+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$T0STATUS$0$0
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+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$FRCOSCKFILT0$0$0
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+G$WTIRQEN$0$0
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+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
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+G$T2CNT$0$0
+G$RADIOSTAT$0$0
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+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart_timer2_baud
+C$uarttimer2.c$9$0$0
+XG$uart_timer2_baud$0$0
+A$uarttimer2$1200
+A$uarttimer2$1300
+A$uarttimer2$1210
+A$uarttimer2$1201
+A$uarttimer2$1400
+A$uarttimer2$1310
+A$uarttimer2$1301
+A$uarttimer2$1220
+A$uarttimer2$1202
+A$uarttimer2$1500
+A$uarttimer2$1410
+A$uarttimer2$1401
+A$uarttimer2$1320
+A$uarttimer2$1311
+A$uarttimer2$1302
+A$uarttimer2$1230
+A$uarttimer2$1221
+A$uarttimer2$1510
+A$uarttimer2$1501
+A$uarttimer2$1420
+A$uarttimer2$1411
+A$uarttimer2$1402
+A$uarttimer2$1330
+A$uarttimer2$1321
+A$uarttimer2$1312
+A$uarttimer2$1240
+A$uarttimer2$1231
+A$uarttimer2$1222
+A$uarttimer2$1213
+A$uarttimer2$1520
+A$uarttimer2$1511
+A$uarttimer2$1502
+A$uarttimer2$1430
+A$uarttimer2$1421
+A$uarttimer2$1412
+A$uarttimer2$1403
+A$uarttimer2$1340
+A$uarttimer2$1331
+A$uarttimer2$1322
+A$uarttimer2$1232
+A$uarttimer2$1223
+A$uarttimer2$1214
+A$uarttimer2$1205
+A$uarttimer2$1530
+A$uarttimer2$1521
+A$uarttimer2$1512
+A$uarttimer2$1503
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+A$uarttimer2$1431
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+A$uarttimer2$1350
+A$uarttimer2$1341
+A$uarttimer2$1332
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+A$uarttimer2$1305
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+A$uarttimer2$1251
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+A$uarttimer2$1215
+A$uarttimer2$1206
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+A$uarttimer2$1522
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+A$uarttimer2$1504
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+A$uarttimer2$1432
+A$uarttimer2$1423
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+A$uarttimer2$1405
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+A$uarttimer2$1342
+A$uarttimer2$1333
+A$uarttimer2$1324
+A$uarttimer2$1270
+A$uarttimer2$1261
+A$uarttimer2$1225
+A$uarttimer2$1216
+A$uarttimer2$1207
+A$uarttimer2$1541
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+A$uarttimer2$1406
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+A$uarttimer2$1343
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+A$uarttimer2$1280
+A$uarttimer2$1271
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+A$uarttimer2$1244
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+A$uarttimer2$1506
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+A$uarttimer2$1461
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+A$uarttimer2$1218
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+A$uarttimer2$1480
+A$uarttimer2$1471
+A$uarttimer2$1462
+A$uarttimer2$1453
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+A$uarttimer2$1417
+A$uarttimer2$1408
+A$uarttimer2$1381
+A$uarttimer2$1372
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+A$uarttimer2$1292
+A$uarttimer2$1283
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+A$uarttimer2$1365
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+A$uarttimer2$1338
+A$uarttimer2$1329
+A$uarttimer2$1293
+A$uarttimer2$1284
+A$uarttimer2$1275
+A$uarttimer2$1266
+A$uarttimer2$1257
+A$uarttimer2$1537
+A$uarttimer2$1528
+A$uarttimer2$1492
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+A$uarttimer2$1465
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+A$uarttimer2$1384
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+A$uarttimer2$1366
+A$uarttimer2$1357
+A$uarttimer2$1348
+A$uarttimer2$1339
+A$uarttimer2$1294
+A$uarttimer2$1285
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+A$uarttimer2$1475
+A$uarttimer2$1466
+A$uarttimer2$1457
+A$uarttimer2$1448
+A$uarttimer2$1439
+A$uarttimer2$1385
+A$uarttimer2$1376
+A$uarttimer2$1358
+A$uarttimer2$1349
+A$uarttimer2$1295
+A$uarttimer2$1286
+A$uarttimer2$1277
+A$uarttimer2$1268
+A$uarttimer2$1259
+A$uarttimer2$1187
+A$uarttimer2$1539
+A$uarttimer2$1485
+A$uarttimer2$1467
+A$uarttimer2$1458
+A$uarttimer2$1449
+A$uarttimer2$1386
+A$uarttimer2$1377
+A$uarttimer2$1296
+A$uarttimer2$1287
+A$uarttimer2$1278
+A$uarttimer2$1269
+A$uarttimer2$1197
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+A$uarttimer2$1477
+A$uarttimer2$1468
+A$uarttimer2$1459
+A$uarttimer2$1378
+A$uarttimer2$1369
+A$uarttimer2$1288
+A$uarttimer2$1279
+A$uarttimer2$1198
+C$uarttimer2.c$12$1$31
+A$uarttimer2$1496
+A$uarttimer2$1487
+A$uarttimer2$1478
+A$uarttimer2$1469
+A$uarttimer2$1379
+A$uarttimer2$1289
+A$uarttimer2$1199
+A$uarttimer2$1497
+A$uarttimer2$1488
+A$uarttimer2$1479
+A$uarttimer2$1398
+A$uarttimer2$1389
+A$uarttimer2$1299
+C$uarttimer2.c$13$2$31
+A$uarttimer2$1498
+A$uarttimer2$1489
+A$uarttimer2$1399
+A$uarttimer2$1499
+C$uarttimer2.c$43$1$31
+C$uarttimer2.c$34$1$31
+C$uarttimer2.c$20$3$34
+C$uarttimer2.c$14$2$32
+C$uarttimer2.c$44$1$31
+C$uarttimer2.c$24$2$32
+C$uarttimer2.c$21$3$34
+C$uarttimer2.c$45$1$31
+C$uarttimer2.c$36$1$31
+C$uarttimer2.c$22$3$34
+C$uarttimer2.c$46$1$31
+C$uarttimer2.c$37$1$31
+C$uarttimer2.c$30$3$36
+C$uarttimer2.c$15$3$33
+C$uarttimer2.c$40$2$37
+C$uarttimer2.c$31$3$36
+C$uarttimer2.c$16$3$33
+C$uarttimer2.c$41$2$37
+C$uarttimer2.c$39$1$31
+C$uarttimer2.c$32$3$36
+C$uarttimer2.c$19$2$32
+C$uarttimer2.c$17$3$33
+C$uarttimer2.c$29$2$32
+C$uarttimer2.c$25$3$35
+C$uarttimer2.c$26$3$35
+C$uarttimer2.c$11$1$0
+C$uarttimer2.c$27$3$35
+G$uart_timer2_baud$0$0
+
+
+
+uart0init 1423544
+G$LPXOSCGM$0$0
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+_MISCCTRL
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+_FRCOSCKFILT0
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+_FRCOSCKFILT1
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+_DPTR1
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+_PCON
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
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+_PINC_3
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+_RADIOFSTATADDR1
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+_PINB_5
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+_INTCHGA
+_SILICONREV
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+_U0SHREG
+_PINA_7
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+_INTCHGB
+_NVADDR
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+_WDTCFG
+_PINB_7
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+.__.ABS.
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+_INTCHGC
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+_B
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+_PORTA
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+_EA
+G$B_2$0$0
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+_ACC
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+G$_XPAGE$0$0
+_PORTC
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+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
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+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
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+_DMA1ADDR
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+_LPOSCREF
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+_PALTRADIO
+_LPOSCFREQ1
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+_E2IP_1
+_IE_3
+Fuart0init$uart0_fiforxrd$0$0
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+Fuart0init$uart0_fiforxwr$0$0
+Fuart0init$uart0_fifotxwr$0$0
+Luart0init.uart0_init$timernr$1$101
+Luart0init.uart0_init$stop$1$101
+Luart0init.uart0_init$wl$1$101
+_uart0_init_PARM_2
+_uart0_init_PARM_3
+C$uart0init.c$148$1$68
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+C$uart0init.c$97$1$63
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+_uart0_poll
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+_uart0_irq
+A$uart0init$1274
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+_uart0_txpoke
+C$uart0init.c$466$1$98
+C$uart0init.c$467$1$98
+C$uart0init.c$469$1$98
+_uart0_txpokehex
+C$uart0init.c$1033$1$100
+C$uart0init.c$96$1$63
+Fuart0init$dummy0$0$0
+C$uart0init.c$84$0$0
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+G$uart0_init$0$0
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+C$uart0init.c$1038$1$102
+C$uart0init.c$1039$1$102
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+XFuart0init$wtimer_cansleep_dummy$0$0
+_uart0_init
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+C$uart0init.c$485$1$100
+G$uart0_txidle$0$0
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+_uart0_txidle
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+_uart0_rxpeek
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+Fuart0init$wtimer_cansleep_dummy$0$0
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+C$uart0init.c$284$1$76
+C$uart0init.c$259$1$74
+C$uart0init.c$149$1$68
+XFuart0init$uart0_iocore$0$0
+G$uart0_rxadvance$0$0
+G$uart0_rxbufptr$0$0
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+_uart0_rxadvance
+_uart0_rxbufptr
+_uart0_txadvance
+_uart0_txbufptr
+XG$uart0_poll$0$0
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+C$uart0init.c$151$1$68
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+A$uart0init$1396
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+A$uart0init$1479
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+C$uart0init.c$282$1$76
+C$uart0init.c$257$1$74
+Fuart0init$uart0_iocore$0$0
+A$uart0init$1399
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+C$uart0init.c$359$1$84
+C$uart0init.c$376$1$86
+XG$uart0_rxcountlinear$0$0
+XG$uart0_txfree$0$0
+C$uart0init.c$378$1$86
+C$uart0init.c$386$1$88
+C$uart0init.c$387$1$88
+C$uart0init.c$389$1$88
+XG$uart0_rxcount$0$0
+_uart0_rxbuffersize
+_uart0_txbuffersize
+XG$uart0_txbuffersize$0$0
+G$uart0_txfreelinear$0$0
+G$uart0_rxcountlinear$0$0
+G$uart0_txfree$0$0
+G$uart0_rxcount$0$0
+A$uart0init$1611
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+A$uart0init$1612
+C$uart0init.c$330$1$80
+_uart0_txfreelinear
+A$uart0init$1604
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+_uart0_rxcountlinear
+_uart0_txfree
+A$uart0init$1690
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+C$uart0init.c$344$1$82
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+A$uart0init$1685
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+_uart0_rxcount
+A$uart0init$1686
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+A$uart0init$1830
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+A$uart0init$1833
+
+
+
+uart1init 1474672
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
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+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
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+_IC0CAPT
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+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
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+
+
+
+uart0stop 1525800
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+_RADIODATA2
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+.__.ABS.
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+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Fuart0stop$fiforxrd$0$0
+Fuart0stop$fifotxrd$0$0
+Fuart0stop$fiforxwr$0$0
+Fuart0stop$fifotxwr$0$0
+A$uart0stop$1190
+A$uart0stop$1193
+A$uart0stop$1196
+A$uart0stop$1199
+C$uart0stop.c$76$1$63
+C$uart0stop.c$77$1$63
+C$uart0stop.c$78$1$63
+C$uart0stop.c$79$1$63
+C$uart0stop.c$74$0$0
+G$uart0_stop$0$0
+_uart0_stop
+XG$uart0_stop$0$0
+
+
+
+uart1stop 1558018
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Fuart1stop$fiforxrd$0$0
+Fuart1stop$fifotxrd$0$0
+Fuart1stop$fiforxwr$0$0
+Fuart1stop$fifotxwr$0$0
+A$uart1stop$1190
+A$uart1stop$1193
+A$uart1stop$1196
+A$uart1stop$1199
+C$uart1stop.c$76$1$63
+C$uart1stop.c$77$1$63
+C$uart1stop.c$78$1$63
+C$uart1stop.c$79$1$63
+C$uart1stop.c$74$0$0
+G$uart1_stop$0$0
+_uart1_stop
+XG$uart1_stop$0$0
+
+
+
+uart0txbuf 1590236
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart0_txbuffer
+C$uart0txbuf.c$5$1$60
+C$uart0txbuf.c$5$0$0
+Fuart0txbuf$uart0_define_txbuffer$0$0
+XFuart0txbuf$uart0_define_txbuffer$0$0
+
+
+
+uart1txbuf 1621902
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart1_txbuffer
+C$uart1txbuf.c$5$1$60
+C$uart1txbuf.c$5$0$0
+Fuart1txbuf$uart1_define_txbuffer$0$0
+XFuart1txbuf$uart1_define_txbuffer$0$0
+
+
+
+uart0rxbuf 1653568
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart0_rxbuffer
+C$uart0rxbuf.c$5$1$60
+C$uart0rxbuf.c$5$0$0
+Fuart0rxbuf$uart0_define_rxbuffer$0$0
+XFuart0rxbuf$uart0_define_rxbuffer$0$0
+
+
+
+uart1rxbuf 1685234
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+_OC1COMP0
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+_IE_5
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+_XTALAMPL
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+G$PCON$0$0
+_IC0CAPT
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+_EIE_2
+_IE_7
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+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+_ADCCH0VAL
+_OC0STATUS
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+_EIE_4
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+G$ANALOGA$0$0
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+_ADCCH1VAL
+_FRCOSCPER
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+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$ADCTUNE0$0$0
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+_ADCCH2VAL
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+_ADCCH3VAL
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+_EIE_7
+_IP_1
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+G$F0$0$0
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+_FRCOSCKFILT0
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+_DPTR0
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+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
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+_T2CNT
+_T2MODE
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+_LPOSCKFILT1
+_IP_4
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+_IP_6
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+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+_EIP_2
+_IP_7
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+G$PINA_5$0$0
+G$WTCFGA$0$0
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+_PCON
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+G$PINC_4$0$0
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+G$ADCCONV$0$0
+_PALTA
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+_ANALOGA
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+G$PINC_7$0$0
+_ADCTUNE0
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+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
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+_ADCTUNE2
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+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
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+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
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+G$E2IP$0$0
+_AC
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+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
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+G$PORTA_1$0$0
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+G$B_5$0$0
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+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
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+G$PORTA_2$0$0
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+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
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+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
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+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
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+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
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+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
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+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
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+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
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+G$DMA1ADDR$0$0
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+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
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+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
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+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
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+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_uart1_rxbuffer
+C$uart1rxbuf.c$5$1$60
+C$uart1rxbuf.c$5$0$0
+Fuart1rxbuf$uart1_define_rxbuffer$0$0
+XFuart1rxbuf$uart1_define_rxbuffer$0$0
+
+
+
+uart0tx 1716900
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+_EXTIRQ
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+_PALTRADIO
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+_IE_3
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+G$uart0_wait_txfree$0$0
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+C$uart0tx.c$54$1$66
+C$uart0tx.c$46$2$64
+C$uart0tx.c$24$0$0
+C$uart0tx.c$55$1$66
+C$uart0tx.c$47$2$64
+C$uart0tx.c$49$1$63
+C$uart0tx.c$56$1$66
+G$uart0_wait_txdone$0$0
+C$uart0tx.c$57$1$66
+G$uart0_tx$0$0
+_uart0_wait_txfree
+_uart0_wait_txdone
+_uart0_tx
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+A$uart0tx$1201
+A$uart0tx$1310
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+A$uart0tx$1213
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+A$uart0tx$1206
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+A$uart0tx$1252
+A$uart0tx$1234
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+A$uart0tx$1253
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+A$uart0tx$1277
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+A$uart0tx$1278
+A$uart0tx$1269
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+A$uart0tx$1189
+A$uart0tx$1299
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+C$uart0tx.c$40$1$63
+C$uart0tx.c$32$2$61
+C$uart0tx.c$50$1$63
+C$uart0tx.c$33$2$61
+C$uart0tx.c$35$1$60
+C$uart0tx.c$26$1$60
+C$uart0tx.c$36$1$60
+C$uart0tx.c$52$1$63
+C$uart0tx.c$42$2$64
+C$uart0tx.c$38$1$60
+C$uart0tx.c$43$2$64
+C$uart0tx.c$28$2$61
+
+
+
+uart1tx 1751865
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
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+_DIRB
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+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+A$uart1tx$1189
+A$uart1tx$1299
+C$uart1tx.c$31$2$61
+C$uart1tx.c$40$1$63
+C$uart1tx.c$32$2$61
+C$uart1tx.c$50$1$63
+C$uart1tx.c$33$2$61
+C$uart1tx.c$35$1$60
+C$uart1tx.c$26$1$60
+C$uart1tx.c$36$1$60
+C$uart1tx.c$52$1$63
+C$uart1tx.c$42$2$64
+C$uart1tx.c$38$1$60
+
+
+
+uart0rx 1786830
+G$LPXOSCGM$0$0
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+_MISCCTRL
+_ANALOGCOMP
+_DIRB
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+_E2IP_2
+_IE_4
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+_DIRC
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+_IE_5
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+_ADCCH1VAL
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+_ADCCH3VAL
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+_FRCOSCKFILT0
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+_PINC
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+_T1MODE
+_T2STATUS
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+_DPTR1
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+_RADIODATA2
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+_ADCCLKSRC
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+G$PORTA_2$0$0
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+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
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+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
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+_ADCCH0VAL0
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+_ADCCH0VAL1
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+_ADCCH1VAL1
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+_ACC_2
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+_E2IE_4
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+_PORTC_1
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+_ADCCH2VAL1
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+_DPH
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+_FRCOSCFREQ1
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+_IE_2
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+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$uart0rx.c$24$0$0
+G$uart0_wait_rxcount$0$0
+G$uart0_rx$0$0
+_uart0_wait_rxcount
+_uart0_rx
+XG$uart0_wait_rxcount$0$0
+XG$uart0_rx$0$0
+A$uart0rx$1210
+A$uart0rx$1220
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+A$uart0rx$1212
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+A$uart0rx$1186
+A$uart0rx$1259
+A$uart0rx$1187
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+A$uart0rx$1199
+C$uart0rx.c$31$2$61
+C$uart0rx.c$32$2$61
+C$uart0rx.c$41$1$63
+C$uart0rx.c$33$2$61
+C$uart0rx.c$35$1$60
+C$uart0rx.c$26$1$60
+C$uart0rx.c$42$1$63
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+C$uart0rx.c$45$1$63
+C$uart0rx.c$28$2$61
+C$uart0rx.c$29$2$61
+
+
+
+uart1rx 1820496
+G$LPXOSCGM$0$0
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+_IE_2
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$uart1rx.c$24$0$0
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+G$uart1_rx$0$0
+_uart1_wait_rxcount
+_uart1_rx
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+A$uart1rx$1210
+A$uart1rx$1220
+A$uart1rx$1211
+A$uart1rx$1202
+A$uart1rx$1221
+A$uart1rx$1212
+A$uart1rx$1203
+A$uart1rx$1204
+A$uart1rx$1250
+A$uart1rx$1232
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+A$uart1rx$1260
+A$uart1rx$1251
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+A$uart1rx$1193
+A$uart1rx$1185
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+A$uart1rx$1186
+A$uart1rx$1259
+A$uart1rx$1187
+A$uart1rx$1188
+A$uart1rx$1199
+C$uart1rx.c$31$2$61
+C$uart1rx.c$32$2$61
+C$uart1rx.c$41$1$63
+C$uart1rx.c$33$2$61
+C$uart1rx.c$35$1$60
+C$uart1rx.c$26$1$60
+C$uart1rx.c$42$1$63
+C$uart1rx.c$36$1$60
+C$uart1rx.c$43$1$63
+C$uart1rx.c$44$1$63
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+C$uart1rx.c$45$1$63
+C$uart1rx.c$28$2$61
+C$uart1rx.c$29$2$61
+
+
+
+uart0wrhexu16 1854162
+.__.ABS.
+XG$uart0_writehexu16$0$0
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+G$uart0_writehexu16$0$0
+_uart0_writehexu16
+
+
+
+uart1wrhexu16 1860128
+.__.ABS.
+XG$uart1_writehexu16$0$0
+A$uart1wrhexu16$122
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+A$uart1wrhexu16$150
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+A$uart1wrhexu16$152
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+G$uart1_writehexu16$0$0
+_uart1_writehexu16
+
+
+
+uart0wrhexu32 1866094
+.__.ABS.
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+_uart0_writehexu32_PARM_2
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+XG$uart0_writehexu32$0$0
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+A$uart0wrhexu32$193
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+C$uart0wrhexu32.c$29$1$60
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+A$uart0wrhexu32$194
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+C$uart0wrhexu32.c$19$0$0
+G$uart0_writehexu32$0$0
+_uart0_writehexu32
+
+
+
+uart1wrhexu32 1874147
+.__.ABS.
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+_uart1_writehexu32_PARM_2
+Luart1wrhexu32.uart1_writehexu32$nrdig$1$59
+XG$uart1_writehexu32$0$0
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+C$uart1wrhexu32.c$21$1$0
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+C$uart1wrhexu32.c$19$0$0
+G$uart1_writehexu32$0$0
+_uart1_writehexu32
+
+
+
+uart0wrstr 1882200
+.__.ABS.
+A$uart0wrstr$120
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+A$uart0wrstr$121
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+C$uart0wrstr.c$27$0$0
+G$uart0_writestr$0$0
+_uart0_writestr
+XG$uart0_writestr$0$0
+C$uart0wrstr.c$102$1$60
+C$uart0wrstr.c$103$1$60
+
+
+
+uart1wrstr 1889150
+.__.ABS.
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+A$uart1wrstr$121
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+A$uart1wrstr$179
+A$uart1wrstr$189
+C$uart1wrstr.c$27$0$0
+G$uart1_writestr$0$0
+_uart1_writestr
+XG$uart1_writestr$0$0
+C$uart1wrstr.c$102$1$60
+C$uart1wrstr.c$103$1$60
+
+
+
+uart0wru16 1896100
+.__.ABS.
+A$uart0wru16$120
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+A$uart0wru16$123
+C$uart0wru16.c$31$1$60
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+C$uart0wru16.c$32$1$60
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+A$uart0wru16$161
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+C$uart0wru16.c$24$1$60
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+C$uart0wru16.c$25$2$60
+A$uart0wru16$191
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+C$uart0wru16.c$19$0$0
+G$uart0_writeu16$0$0
+_uart0_writeu16
+XG$uart0_writeu16$0$0
+
+
+
+uart1wru16 1902755
+.__.ABS.
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+A$uart1wru16$130
+A$uart1wru16$150
+A$uart1wru16$123
+C$uart1wru16.c$31$1$60
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+C$uart1wru16.c$32$1$60
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+A$uart1wru16$161
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+C$uart1wru16.c$24$1$60
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+C$uart1wru16.c$26$1$60
+C$uart1wru16.c$25$2$60
+A$uart1wru16$191
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+C$uart1wru16.c$27$2$61
+A$uart1wru16$176
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+A$uart1wru16$186
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+C$uart1wru16.c$29$2$61
+C$uart1wru16.c$21$1$0
+A$uart1wru16$187
+A$uart1wru16$178
+A$uart1wru16$169
+A$uart1wru16$188
+A$uart1wru16$179
+C$uart1wru16.c$19$0$0
+G$uart1_writeu16$0$0
+_uart1_writeu16
+XG$uart1_writeu16$0$0
+
+
+
+uart0wru32 1909410
+.__.ABS.
+Luart0wru32.uart0_writeu32$val$1$59
+_uart0_writeu32_PARM_2
+Luart0wru32.uart0_writeu32$nrdig$1$59
+A$uart0wru32$200
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+G$uart0_writeu32$0$0
+_uart0_writeu32
+XG$uart0_writeu32$0$0
+
+
+
+uart1wru32 1918005
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+_uart1_writeu32_PARM_2
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+G$uart1_writeu32$0$0
+_uart1_writeu32
+XG$uart1_writeu32$0$0
+
+
+
+uart0wrnum16 1926600
+.__.ABS.
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+_uart0_writenum16
+XG$uart0_writenum16$0$0
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+
+
+
+uart0wrnum32 1936827
+.__.ABS.
+_uart0_writenum32
+XG$uart0_writenum32$0$0
+A$uart0wrnum32$200
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+G$uart0_writenum32$0$0
+
+
+
+uart0wrhex16 1948422
+.__.ABS.
+_uart0_writehex16
+XG$uart0_writehex16$0$0
+C$uart0wrhex16.c$264$1$62
+C$uart0wrhex16.c$265$1$62
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+
+
+
+uart0wrhex32 1959497
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+
+
+
+uart1wrnum16 1971296
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+
+
+
+uart1wrnum32 1981523
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+
+
+
+uart1wrhex16 1993118
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+
+
+
+uart1wrhex32 2004193
+.__.ABS.
+_uart1_writehex32
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+G$uart1_writehex32$0$0
+
+
+
+adctemp 2015992
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+_ADCCH2VAL
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+_ADCCH3VAL
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+_FRCOSCKFILT0
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+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
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+_LPOSCKFILT1
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
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+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
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+G$RADIOADDR1$0$0
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+_LPOSCFREQ
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+G$PINA_5$0$0
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+G$ADCCH3CONFIG$0$0
+_PCON
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+_DIRR
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+_PALTA
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+G$WDTCFG$0$0
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+G$NVADDR$0$0
+_ANALOGA
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+G$OSCCALIB$0$0
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+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
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+_F0
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+_LPOSCCONFIG
+_T0PERIOD0
+_F1
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+G$AC$0$0
+_DMA0CONFIG
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
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+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
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+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+_WTCNTB0
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+G$DBGLNKBUF$0$0
+_WTCNTB1
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+G$WTCNTB$0$0
+_PORTA
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+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
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+_SPSTATUS
+_T0PERIOD
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+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+G$PORTA_0$0$0
+G$RS0$0$0
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+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
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+G$PORTA_1$0$0
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+G$E2IE_2$0$0
+G$B_5$0$0
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+G$CLKSTAT$0$0
+_ADCCLKSRC
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+G$ADCCH1VAL0$0$0
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+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
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+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
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+G$PORTA_4$0$0
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+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
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+_DPH1
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+_WTEVTC0
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+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
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+_WTEVTD0
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+G$E2IE_7$0$0
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+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
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+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
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+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
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+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
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+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
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+_EIE
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+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
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+__XPAGE
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+_B_3
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+G$OC0COMP0$0$0
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+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
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+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
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+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
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+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
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+G$EIE_0$0$0
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+G$OC0COMP1$0$0
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+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
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+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
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+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
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+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
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+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+_PORTB_6
+_PORTC_5
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+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$adc_calibrate$0$0
+C$adccal.c$6$1$36
+C$adccal.c$7$1$36
+_adc_calibrate
+C$adccal.c$8$1$36
+C$adccal.c$4$0$0
+XG$adc_calibrate$0$0
+A$adccal$1180
+A$adccal$1183
+A$adccal$1186
+
+
+
+adccalg 2080960
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
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+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$ADCCALG00GAIN0$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$ADCCALG10GAIN0$0$0
+G$ADCCALG01GAIN0$0$0
+G$ADCCALG00GAIN1$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$ADCCALG10GAIN1$0$0
+G$ADCCALG01GAIN1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_ADCCALG00GAIN0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_ADCCALG00GAIN1
+_ADCCALG01GAIN0
+_ADCCALG10GAIN0
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_ADCCALG01GAIN1
+_ADCCALG10GAIN1
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
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+
+
+
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+_CY
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+_adc_uncalibrate
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+
+
+
+adcseoffs00 2186094
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+_OC1COMP0
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+G$NVADDR0$0$0
+_XTALAMPL
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+_T2STATUS
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+_FRCOSCKFILT1
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+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
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+_IP_6
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+_LPOSCFREQ
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+_IP_7
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+_PCON
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+_ADCCH0CONFIG
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+_T2PERIOD0
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+_PINB_1
+_PINC_0
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+G$PORTA$0$0
+_FRCOSCKFILT
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+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
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+_PINB_2
+_PINC_1
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+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
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+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+_WTCNTB0
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+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
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+G$DBGLNKBUF$0$0
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+G$DPL1$0$0
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
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+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
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+_OSCFORCERUN
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+
+
+
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+A$bch3121decp$1199
+C$bch3121decp.c$11$1$33
+C$bch3121decp.c$12$1$33
+
+
+
+bch3121enc 2360720
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+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+Lbch3121enc.bch3121_encode$cw$1$32
+A$bch3121enc$1291
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+
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+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$offxosc$1200
+A$offxosc$1210
+A$offxosc$1201
+A$offxosc$1202
+A$offxosc$1203
+A$offxosc$1240
+A$offxosc$1231
+A$offxosc$1222
+A$offxosc$1213
+A$offxosc$1204
+A$offxosc$1241
+A$offxosc$1223
+A$offxosc$1205
+A$offxosc$1260
+A$offxosc$1242
+A$offxosc$1224
+A$offxosc$1270
+A$offxosc$1261
+A$offxosc$1243
+A$offxosc$1234
+A$offxosc$1216
+A$offxosc$1280
+A$offxosc$1271
+A$offxosc$1244
+A$offxosc$1208
+A$offxosc$1190
+A$offxosc$1272
+A$offxosc$1254
+A$offxosc$1245
+A$offxosc$1227
+A$offxosc$1209
+A$offxosc$1191
+A$offxosc$1264
+A$offxosc$1237
+A$offxosc$1228
+A$offxosc$1219
+A$offxosc$1192
+A$offxosc$1193
+A$offxosc$1184
+A$offxosc$1275
+A$offxosc$1257
+A$offxosc$1248
+A$offxosc$1185
+A$offxosc$1276
+A$offxosc$1267
+A$offxosc$1258
+A$offxosc$1186
+A$offxosc$1259
+A$offxosc$1196
+A$offxosc$1187
+G$turn_off_xosc$0$0
+A$offxosc$1188
+C$offxosc.c$20$1$33
+C$offxosc.c$30$1$33
+C$offxosc.c$21$1$33
+C$offxosc.c$12$1$33
+C$offxosc.c$31$1$33
+C$offxosc.c$22$1$33
+C$offxosc.c$13$1$33
+C$offxosc.c$32$1$33
+C$offxosc.c$23$1$33
+C$offxosc.c$14$1$33
+C$offxosc.c$33$1$33
+C$offxosc.c$24$1$33
+C$offxosc.c$15$1$33
+C$offxosc.c$25$1$33
+C$offxosc.c$16$1$33
+C$offxosc.c$26$1$33
+C$offxosc.c$17$1$33
+C$offxosc.c$18$1$33
+C$offxosc.c$28$1$33
+C$offxosc.c$19$1$33
+C$offxosc.c$29$1$33
+C$offxosc.c$27$2$34
+_turn_off_xosc
+XG$turn_off_xosc$0$0
+C$offxosc.c$8$0$0
+
+
+
+offlpxosc 2523386
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
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+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
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+G$DPH1$0$0
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+G$FRCOSCREF1$0$0
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+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+G$CODECONFIG$0$0
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+_EA
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+G$EIE$0$0
+_ACC
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+G$B_3$0$0
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+G$_XPAGE$0$0
+_PORTC
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+G$RS0$0$0
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+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
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+_WTEVTC0
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+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
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+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
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+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
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+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
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+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
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+_EIE
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+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
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+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$EIE_0$0$0
+G$E2IP_3$0$0
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+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
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+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
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+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
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+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
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+G$IP_3$0$0
+G$U1MODE$0$0
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+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$turn_off_lpxosc$0$0
+C$offlpxosc.c$8$0$0
+A$offlpxosc$1200
+A$offlpxosc$1210
+A$offlpxosc$1201
+A$offlpxosc$1202
+A$offlpxosc$1203
+A$offlpxosc$1231
+A$offlpxosc$1222
+A$offlpxosc$1213
+A$offlpxosc$1204
+A$offlpxosc$1232
+A$offlpxosc$1205
+A$offlpxosc$1233
+A$offlpxosc$1252
+A$offlpxosc$1234
+A$offlpxosc$1225
+A$offlpxosc$1216
+A$offlpxosc$1280
+A$offlpxosc$1262
+A$offlpxosc$1253
+A$offlpxosc$1235
+A$offlpxosc$1208
+A$offlpxosc$1190
+A$offlpxosc$1272
+A$offlpxosc$1263
+A$offlpxosc$1254
+A$offlpxosc$1245
+A$offlpxosc$1236
+A$offlpxosc$1209
+A$offlpxosc$1191
+A$offlpxosc$1264
+A$offlpxosc$1255
+A$offlpxosc$1228
+A$offlpxosc$1219
+A$offlpxosc$1192
+A$offlpxosc$1265
+A$offlpxosc$1256
+A$offlpxosc$1193
+A$offlpxosc$1184
+A$offlpxosc$1275
+A$offlpxosc$1266
+A$offlpxosc$1239
+A$offlpxosc$1185
+A$offlpxosc$1276
+A$offlpxosc$1249
+A$offlpxosc$1186
+A$offlpxosc$1259
+A$offlpxosc$1196
+A$offlpxosc$1187
+G$turn_off_lpxosc$0$0
+A$offlpxosc$1269
+A$offlpxosc$1188
+C$offlpxosc.c$20$1$33
+C$offlpxosc.c$30$1$33
+C$offlpxosc.c$21$1$33
+C$offlpxosc.c$12$1$33
+C$offlpxosc.c$31$1$33
+C$offlpxosc.c$22$1$33
+C$offlpxosc.c$13$1$33
+C$offlpxosc.c$32$1$33
+C$offlpxosc.c$23$1$33
+C$offlpxosc.c$14$1$33
+C$offlpxosc.c$33$1$33
+C$offlpxosc.c$24$1$33
+C$offlpxosc.c$15$1$33
+C$offlpxosc.c$34$1$33
+C$offlpxosc.c$16$1$33
+C$offlpxosc.c$25$2$33
+C$offlpxosc.c$17$1$33
+C$offlpxosc.c$18$1$33
+C$offlpxosc.c$19$1$33
+_turn_off_lpxosc
+C$offlpxosc.c$28$2$34
+C$offlpxosc.c$29$2$34
+C$offlpxosc.c$27$3$35
+
+
+
+setuplpxosc 2556492
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
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+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
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+_IE_6
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+G$PCON$0$0
+_IC0CAPT
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+_EIE_2
+_IE_7
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+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
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+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
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+G$DMA0CONFIG$0$0
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+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+G$PINR$0$0
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+_LPXOSCGM
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+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$setuplpxosc.c$8$0$0
+_setup_lpxosc
+XG$setup_lpxosc$0$0
+A$setuplpxosc$1202
+A$setuplpxosc$1180
+A$setuplpxosc$1190
+A$setuplpxosc$1181
+A$setuplpxosc$1182
+A$setuplpxosc$1183
+A$setuplpxosc$1193
+A$setuplpxosc$1184
+A$setuplpxosc$1194
+A$setuplpxosc$1176
+A$setuplpxosc$1195
+A$setuplpxosc$1196
+A$setuplpxosc$1187
+A$setuplpxosc$1197
+A$setuplpxosc$1179
+A$setuplpxosc$1198
+C$setuplpxosc.c$10$1$33
+A$setuplpxosc$1199
+C$setuplpxosc.c$11$1$33
+C$setuplpxosc.c$12$1$33
+C$setuplpxosc.c$13$1$33
+C$setuplpxosc.c$14$1$33
+G$setup_lpxosc$0$0
+
+
+
+setupxosc 2587368
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
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+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
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+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$setupxosc$1180
+A$setupxosc$1190
+A$setupxosc$1181
+A$setupxosc$1182
+A$setupxosc$1183
+A$setupxosc$1193
+A$setupxosc$1184
+A$setupxosc$1194
+A$setupxosc$1176
+A$setupxosc$1195
+A$setupxosc$1196
+A$setupxosc$1187
+A$setupxosc$1197
+A$setupxosc$1179
+A$setupxosc$1198
+C$setupxosc.c$10$1$33
+A$setupxosc$1199
+C$setupxosc.c$11$1$33
+C$setupxosc.c$12$1$33
+C$setupxosc.c$13$1$33
+C$setupxosc.c$14$1$33
+G$setup_xosc$0$0
+C$setupxosc.c$8$0$0
+_setup_xosc
+XG$setup_xosc$0$0
+A$setupxosc$1202
+
+
+
+setupcal 2618184
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
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+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
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+
+
+
+wtcbadd 2771482
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+_RADIODATA2
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+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINB_4
+_PINC_3
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+_INTCHGA
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+_INTCHGB
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+_WDTCFG
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+.__.ABS.
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+G$WTEVTA1$0$0
+_INTCHGC
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+G$IE$0$0
+_B
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+_EA
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+G$_XPAGE$0$0
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+_OSCFORCERUN
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+_ADCCLKSRC
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+_PINSEL
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+G$PORTA_3$0$0
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+G$ACC_2$0$0
+_RADIOFSTATADDR
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+_WTEVTB0
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+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
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+_DPH1
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+_WTEVTC0
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+G$OSCRUN$0$0
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+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
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+G$PORTB_5$0$0
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+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
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+G$PORTA_7$0$0
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+G$SPSHREG$0$0
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+G$DPH$0$0
+_E2IP
+_P
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+G$PORTB_7$0$0
+G$IE_0$0$0
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+G$WTEVTC$0$0
+_DPL1
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+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
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+__XPAGE
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+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_wtimer_add_callback
+C$wtcbadd.c$4$0$0
+C$wtcbadd.c$6$1$59
+C$wtcbadd.c$7$1$59
+C$wtcbadd.c$8$1$59
+C$wtcbadd.c$9$1$59
+XG$wtimer_add_callback$0$0
+A$wtcbadd$1200
+A$wtcbadd$1203
+A$wtcbadd$1180
+A$wtcbadd$1181
+A$wtcbadd$1192
+A$wtcbadd$1193
+A$wtcbadd$1184
+A$wtcbadd$1194
+A$wtcbadd$1185
+A$wtcbadd$1195
+A$wtcbadd$1186
+A$wtcbadd$1196
+A$wtcbadd$1189
+A$wtcbadd$1199
+C$wtcbadd.c$10$1$59
+G$wtimer_add_callback$0$0
+
+
+
+wtcbrem 2804062
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$wtcbrem$1202
+A$wtcbrem$1203
+A$wtcbrem$1206
+A$wtcbrem$1209
+A$wtcbrem$1191
+A$wtcbrem$1182
+A$wtcbrem$1183
+A$wtcbrem$1194
+A$wtcbrem$1195
+A$wtcbrem$1186
+A$wtcbrem$1196
+A$wtcbrem$1187
+A$wtcbrem$1197
+A$wtcbrem$1188
+A$wtcbrem$1198
+A$wtcbrem$1199
+C$wtcbrem.c$10$1$59
+C$wtcbrem.c$11$1$59
+C$wtcbrem.c$12$1$59
+C$wtcbrem.c$13$1$59
+G$wtimer_remove_callback$0$0
+C$wtcbrem.c$4$0$0
+C$wtcbrem.c$8$1$59
+C$wtcbrem.c$9$1$59
+_wtimer_remove_callback
+XG$wtimer_remove_callback$0$0
+
+
+
+wt0setcfg 2836918
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_wtimer0_setconfig
+C$wt0setcfg.c$4$0$0
+C$wt0setcfg.c$6$1$59
+C$wt0setcfg.c$7$1$59
+C$wt0setcfg.c$8$1$59
+C$wt0setcfg.c$9$1$59
+XG$wtimer0_setconfig$0$0
+A$wt0setcfg$1211
+A$wt0setcfg$1202
+A$wt0setcfg$1203
+A$wt0setcfg$1204
+A$wt0setcfg$1207
+A$wt0setcfg$1180
+A$wt0setcfg$1181
+A$wt0setcfg$1182
+A$wt0setcfg$1183
+A$wt0setcfg$1193
+A$wt0setcfg$1184
+A$wt0setcfg$1185
+A$wt0setcfg$1196
+A$wt0setcfg$1189
+A$wt0setcfg$1199
+C$wt0setcfg.c$10$1$59
+C$wt0setcfg.c$11$1$59
+G$wtimer0_setconfig$0$0
+C$wt0setcfg.c$12$1$59
+C$wt0setcfg.c$13$1$59
+
+
+
+wt1setcfg 2869713
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
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+
+
+
+wtstdby 2902508
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+_XTALAMPL
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+G$NVADDR1$0$0
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+G$DIRR$0$0
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+_E2IP_6
+_EIE_3
+_OV
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+_ADCCH0VAL
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+_ADCCH1VAL
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+_ADCCH2VAL
+_LPOSCPER
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+_ADCCH3VAL
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+A$wt1adda$1187
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+C$wt1adda.c$12$1$59
+_wtimer1_addabsolute
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+A$wt1adda$1183
+A$wt1adda$1194
+A$wt1adda$1195
+A$wt1adda$1186
+
+
+
+wt0addr 2998836
+G$LPXOSCGM$0$0
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+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
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+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
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+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
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+_NVDATA1
+_EIP_2
+_IP_7
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+G$PINA_5$0$0
+G$WTCFGA$0$0
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+G$ADCCH3CONFIG$0$0
+_PCON
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+_PALTA
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+_ANALOGA
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+_ADCTUNE0
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+_ADCTUNE1
+_FRCOSCCTRL
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+G$B$0$0
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+_LPOSCCONFIG
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+_F1
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+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
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+_SCRATCH1
+_ADCCH0CONFIG
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+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
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+_FRCOSCKFILT
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+_CLKCON
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+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
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+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINB_3
+_PINC_2
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+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_PINB_4
+_PINC_3
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+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
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+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
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+_PINC_5
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+_INTCHGB
+_NVADDR
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+_WDTCFG
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+_PINC_6
+.__.ABS.
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+G$IE$0$0
+_B
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+_EA
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+_ACC
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+_SPSTATUS
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+G$B_3$0$0
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+G$_XPAGE$0$0
+_PORTC
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+_T1PERIOD
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+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
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+G$PORTA_2$0$0
+G$E2IE_3$0$0
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+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
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+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
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+_FRCOSCREF0
+_DPH1
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+_WTEVTC0
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+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
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+G$T2CNT0$0$0
+G$T1CNT1$0$0
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+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
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+G$PORTA_7$0$0
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+G$DPH$0$0
+_E2IP
+_P
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+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
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+_WTCNTB
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+_EIE
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+__XPAGE
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+_IC0CAPT1
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+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
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+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
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+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
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+_ADCCH1VAL1
+_ADCCH2VAL0
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+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
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+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
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+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+_PORTB_6
+_PORTC_5
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+G$OC0PIN$0$0
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$DPTR0$0$0
+_DMA1ADDR
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+_LPOSCREF
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+_IE_1
+_PORTC_7
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+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$wt0addr$1200
+A$wt0addr$1210
+A$wt0addr$1201
+A$wt0addr$1220
+A$wt0addr$1211
+A$wt0addr$1202
+A$wt0addr$1221
+A$wt0addr$1212
+A$wt0addr$1203
+A$wt0addr$1222
+A$wt0addr$1213
+A$wt0addr$1204
+A$wt0addr$1214
+A$wt0addr$1205
+A$wt0addr$1215
+A$wt0addr$1206
+A$wt0addr$1216
+A$wt0addr$1207
+A$wt0addr$1217
+A$wt0addr$1208
+A$wt0addr$1190
+A$wt0addr$1181
+A$wt0addr$1218
+A$wt0addr$1209
+A$wt0addr$1191
+A$wt0addr$1182
+A$wt0addr$1173
+_wtimer0_addrelative
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+A$wt0addr$1192
+A$wt0addr$1183
+A$wt0addr$1174
+A$wt0addr$1193
+A$wt0addr$1184
+A$wt0addr$1175
+A$wt0addr$1194
+A$wt0addr$1185
+A$wt0addr$1176
+A$wt0addr$1195
+A$wt0addr$1186
+A$wt0addr$1177
+A$wt0addr$1196
+A$wt0addr$1187
+A$wt0addr$1178
+A$wt0addr$1197
+A$wt0addr$1188
+A$wt0addr$1179
+A$wt0addr$1198
+A$wt0addr$1189
+A$wt0addr$1199
+XG$wtimer0_addrelative$0$0
+C$wt0addr.c$60$1$59
+C$wt0addr.c$59$1$59
+C$wt0addr.c$6$0$0
+G$wtimer0_addrelative$0$0
+
+
+
+wt1addr 3032548
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
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+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
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+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
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+_IP_0
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+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$F0$0$0
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
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+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
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+G$PINA_0$0$0
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
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+_T2MODE
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+
+
+
+wt0curt 3066260
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+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
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+_FRCOSCKFILT0
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+_wtimer0_curtime
+
+
+
+wt1curt 3099293
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+_U1MODE
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+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
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+_PALTRADIO
+_LPOSCFREQ1
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+_IC0STATUS
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+_IE_3
+C$wt1curt.c$12$1$59
+_wtimer1_curtime
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+
+
+
+wt0rem 3132326
+G$LPXOSCGM$0$0
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+_WTIRQEN
+_IP_2
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+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
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+
+
+
+wt1rem 3165753
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+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
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+G$ADCCONV$0$0
+_PALTA
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+_ADCTUNE0
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+_ADCTUNE1
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+_T1PERIOD1
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+_PINB_1
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+_CLKCON
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+_RADIODATA1
+_T2PERIOD1
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+_RADIODATA2
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+_OSCFORCERUN
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+
+
+
+radiord24 3265520
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+_IE_7
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+_FRCOSCFREQ
+_XTALREADY
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+_PCON
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+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
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+G$B$0$0
+_ADCTUNE2
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+_LPOSCCONFIG
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+_F1
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+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
+G$P$0$0
+G$E2IP$0$0
+_AC
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
+G$B_1$0$0
+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$radio_read24$0$0
+C$radiord24.c$7$0$0
+_radio_read24
+XG$radio_read24$0$0
+A$radiord24$1180
+A$radiord24$1190
+A$radiord24$1181
+A$radiord24$1191
+A$radiord24$1182
+A$radiord24$1192
+A$radiord24$1183
+A$radiord24$1174
+A$radiord24$1193
+A$radiord24$1184
+A$radiord24$1175
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+A$radiord24$1176
+A$radiord24$1186
+A$radiord24$1177
+A$radiord24$1187
+A$radiord24$1178
+A$radiord24$1188
+A$radiord24$1179
+A$radiord24$1189
+C$radiord24.c$31$1$64
+C$radiord24.c$32$1$64
+
+
+
+radiord32 3297839
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
+_EIP_3
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
+_OC0COMP
+_EIP_4
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_EIP_6
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
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+G$WTEVTC0$0$0
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+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
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+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_WTCNTB1
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+G$E2IP$0$0
+_AC
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+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_E2IE
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_RADIODATA
+_T2PERIOD
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
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+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
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+_DMA0ADDR0
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+_DPH1
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+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
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+_IE
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+_WTEVTD0
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+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_WTCNTB
+_B_1
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+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_EIE
+_WTCNTR1
+_B_2
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
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+G$U0STATUS$0$0
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+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
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+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$radio_read32$0$0
+C$radiord32.c$7$0$0
+_radio_read32
+XG$radio_read32$0$0
+A$radiord32$1180
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+C$radiord32.c$30$1$64
+C$radiord32.c$31$1$64
+
+
+
+radiowr16 3330129
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_PCON
+_NVADDR1
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+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_DIRR
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+G$INTCHGA$0$0
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+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_OC1COMP
+_WDTRESET
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+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
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+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_EIP_7
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_RADIOACC
+_F0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$EA$0$0
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+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_PINC_7
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
+G$LPOSCREF0$0$0
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+_OSCFORCERUN
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+_DPL1
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+_ADCCH0VAL0
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+_PALTRADIO
+_LPOSCFREQ1
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+_IE_3
+C$radiowr16.c$45$1$64
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+G$radio_write16$0$0
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+A$radiowr16$1198
+A$radiowr16$1189
+A$radiowr16$1199
+
+
+
+radiowr24 3362655
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
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+G$NVADDR0$0$0
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+G$ACC$0$0
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+_SCRATCH3
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+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_PINB_3
+_PINC_2
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+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
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+_INTCHGB
+_NVADDR
+_U1SHREG
+_WDTCFG
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+_PINC_6
+.__.ABS.
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+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
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+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_WTCNTA0
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+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
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+G$DBGLNKBUF$0$0
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+G$WTCNTB$0$0
+_PORTA
+_T0CLKSRC
+_EA
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+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
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+G$E2IE_0$0$0
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+
+
+radiowr32 3395248
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+
+
+
+radiodswakecore 3427908
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+G$AX5043_IRQINVERSION0NB$0$0
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+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
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+G$XIC0CAPT1$0$0
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+_AX5043_REF
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+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
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+_E2IP_2
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+_AX5043_PKTLENCFG
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+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
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+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
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+_EIE_1
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+_AX5043_RSSIREFERENCENB
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+_AX5043_FOURFSK0NB
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+_AX5043_0xF0C
+_AX5043_0xF21NB
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+_AX5043_FOURFSK1NB
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+_AX5043_PLLLOOP
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+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
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+_ADCCH1VAL
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+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
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+G$AX5043_FREQDEV03$0$0
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+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
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+G$ADCTUNE0$0$0
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+_ADCCH2VAL
+_LPOSCPER
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+_AX5043_0xF33NB
+_PINA
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+_EIE_6
+_IP_0
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+G$XWTEVTC$0$0
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+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
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+G$AX5043_FECSTATUS$0$0
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+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
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+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
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+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
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+_T2MODE
+_U1MODE
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+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+XG$radio_wakeup_deepsleep_core$0$0
+A$radiodswakecore$3301
+A$radiodswakecore$3311
+A$radiodswakecore$3330
+A$radiodswakecore$3321
+A$radiodswakecore$3312
+A$radiodswakecore$3331
+A$radiodswakecore$3313
+A$radiodswakecore$3304
+A$radiodswakecore$3332
+A$radiodswakecore$3314
+A$radiodswakecore$3315
+A$radiodswakecore$3335
+A$radiodswakecore$3308
+A$radiodswakecore$3281
+A$radiodswakecore$3327
+A$radiodswakecore$3318
+A$radiodswakecore$3291
+C$radiodswakecore.c$10$1$30
+A$radiodswakecore$3338
+A$radiodswakecore$3284
+A$radiodswakecore$3294
+C$radiodswakecore.c$21$1$30
+C$radiodswakecore.c$22$1$30
+C$radiodswakecore.c$20$2$31
+A$radiodswakecore$3278
+C$radiodswakecore.c$23$1$30
+A$radiodswakecore$3297
+A$radiodswakecore$3288
+C$radiodswakecore.c$24$1$30
+A$radiodswakecore$3298
+C$radiodswakecore.c$25$1$30
+C$radiodswakecore.c$12$3$32
+C$radiodswakecore.c$26$1$30
+C$radiodswakecore.c$13$3$32
+C$radiodswakecore.c$27$1$30
+C$radiodswakecore.c$14$3$32
+C$radiodswakecore.c$15$3$32
+C$radiodswakecore.c$16$4$33
+C$radiodswakecore.c$19$3$32
+C$radiodswakecore.c$17$4$33
+C$radiodswakecore.c$8$1$30
+G$radio_wakeup_deepsleep_core$0$0
+C$radiodswakecore.c$5$0$0
+C$radiodswakecore.c$7$1$0
+_radio_wakeup_deepsleep_core
+
+
+
+ax5031comminit 3533285
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
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+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031commslpexit.c$8$0$0
+G$ax5031_commsleepexit$0$0
+_ax5031_commsleepexit
+XG$ax5031_commsleepexit$0$0
+A$ax5031commslpexit$1470
+A$ax5031commslpexit$1461
+A$ax5031commslpexit$1480
+A$ax5031commslpexit$1471
+A$ax5031commslpexit$1490
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+A$ax5031commslpexit$1472
+A$ax5031commslpexit$1491
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+A$ax5031commslpexit$1468
+A$ax5031commslpexit$1487
+A$ax5031commslpexit$1478
+A$ax5031commslpexit$1469
+A$ax5031commslpexit$1497
+A$ax5031commslpexit$1488
+A$ax5031commslpexit$1479
+A$ax5031commslpexit$1489
+C$ax5031commslpexit.c$10$1$66
+C$ax5031commslpexit.c$11$1$66
+C$ax5031commslpexit.c$12$1$66
+C$ax5031commslpexit.c$13$1$66
+C$ax5031commslpexit.c$24$1$66
+C$ax5031commslpexit.c$15$1$66
+C$ax5031commslpexit.c$25$1$66
+C$ax5031commslpexit.c$16$1$66
+
+
+
+ax5031reset 3618902
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031reset.c$8$0$0
+_ax5031_reset
+_ax5031_probeirq
+XG$ax5031_reset$0$0
+XG$ax5031_probeirq$0$0
+A$ax5031reset$1500
+A$ax5031reset$1501
+A$ax5031reset$1700
+A$ax5031reset$1610
+A$ax5031reset$1601
+A$ax5031reset$1520
+A$ax5031reset$1620
+A$ax5031reset$1611
+A$ax5031reset$1530
+A$ax5031reset$1521
+A$ax5031reset$1512
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+A$ax5031reset$1621
+A$ax5031reset$1612
+A$ax5031reset$1531
+A$ax5031reset$1513
+A$ax5031reset$1504
+A$ax5031reset$1703
+A$ax5031reset$1640
+A$ax5031reset$1631
+A$ax5031reset$1622
+A$ax5031reset$1604
+A$ax5031reset$1532
+A$ax5031reset$1505
+A$ax5031reset$1650
+A$ax5031reset$1641
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+A$ax5031reset$1560
+A$ax5031reset$1542
+A$ax5031reset$1470
+A$ax5031reset$1660
+A$ax5031reset$1651
+A$ax5031reset$1615
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+A$ax5031reset$1543
+A$ax5031reset$1525
+A$ax5031reset$1516
+A$ax5031reset$1480
+A$ax5031reset$1471
+A$ax5031reset$1652
+A$ax5031reset$1625
+A$ax5031reset$1616
+A$ax5031reset$1607
+A$ax5031reset$1553
+A$ax5031reset$1535
+A$ax5031reset$1526
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+A$ax5031reset$1508
+A$ax5031reset$1472
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+A$ax5031reset$1680
+A$ax5031reset$1653
+A$ax5031reset$1635
+A$ax5031reset$1626
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+A$ax5031reset$1554
+A$ax5031reset$1536
+A$ax5031reset$1509
+A$ax5031reset$1491
+A$ax5031reset$1464
+A$ax5031reset$1690
+A$ax5031reset$1681
+A$ax5031reset$1654
+A$ax5031reset$1645
+A$ax5031reset$1636
+A$ax5031reset$1564
+A$ax5031reset$1555
+A$ax5031reset$1537
+A$ax5031reset$1492
+A$ax5031reset$1483
+A$ax5031reset$1664
+A$ax5031reset$1655
+A$ax5031reset$1646
+A$ax5031reset$1637
+A$ax5031reset$1574
+A$ax5031reset$1565
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+A$ax5031reset$1493
+A$ax5031reset$1484
+A$ax5031reset$1475
+A$ax5031reset$1674
+A$ax5031reset$1665
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+
+
+
+ax5031deepsleep 3667830
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
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+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
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+_IE_5
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+G$AX5031_PLLRANGING$0$0
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+_XTALAMPL
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+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
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+_EIE_1
+_IE_6
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+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
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+_SPCLKSRC
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+_EIE_3
+_OV
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+_ADCCH0VAL
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+_AX5031_IRQREQUESTNB
+_OC0STATUS
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+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5031_FSKDEV0$0$0
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+_ADCCH2VAL
+_LPOSCPER
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+_OC1MODE
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+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
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+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
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+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
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+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
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+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
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+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
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+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
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+G$PINC_1$0$0
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+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
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+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5031rclkena 3709060
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
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+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$LPOSCPER0$0$0
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+G$ADCCH2VAL0$0$0
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+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
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+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
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+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
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+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
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+G$XTALOSC$0$0
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+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
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+G$AX5031_PWRMODE$0$0
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+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
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+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
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+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
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+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
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+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
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+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
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+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
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+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
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+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
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+G$AX5031_PINCFG1$0$0
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+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
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+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
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+G$AX5031_PINCFG2$0$0
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+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
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+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
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+G$DPTR1$0$0
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+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5031_rclk_enable$0$0
+A$ax5031rclkena$1500
+A$ax5031rclkena$1501
+_ax5031_rclk_enable
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+A$ax5031rclkena$1497
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+A$ax5031rclkena$1479
+A$ax5031rclkena$1489
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+C$ax5031rclkena.c$11$1$64
+C$ax5031rclkena.c$12$1$64
+C$ax5031rclkena.c$13$1$64
+C$ax5031rclkena.c$14$1$64
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+C$ax5031rclkena.c$19$1$64
+C$ax5031rclkena.c$8$1$64
+C$ax5031rclkena.c$9$1$64
+C$ax5031rclkena.c$5$0$0
+
+
+
+ax5031rclkdis 3752652
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
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+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
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+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
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+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
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+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
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+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
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+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
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+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
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+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
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+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
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+G$PORTA_7$0$0
+G$CY$0$0
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+G$SPSHREG$0$0
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+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
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+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
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+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
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+G$XTALOSC$0$0
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+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
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+_WTCNTB
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+G$AX5031_PWRMODE$0$0
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+G$E2IP_0$0$0
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+_EIE
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+G$PALTRADIO$0$0
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+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
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+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
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+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
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+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
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+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
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+_PORTC_3
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+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
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+_T2CNT0
+_WTEVTA
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+_CY
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+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
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+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031rclkdis.c$8$1$64
+C$ax5031rclkdis.c$9$1$64
+C$ax5031rclkdis.c$5$0$0
+XG$ax5031_rclk_disable$0$0
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+_ax5031_rclk_disable
+
+
+
+ax5031rdfifo 3795605
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
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+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
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+_IC0MODE
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+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
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+_OC0COMP1
+_OC1COMP0
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+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
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+_ADCCH1VAL
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+_WTSTAT
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+_ADCCH3VAL
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+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
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+_T0MODE
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+_EIE_7
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+_FRCOSCKFILT0
+_RADIOFDATAADDR
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+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
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+_FRCOSCKFILT1
+_LPOSCKFILT0
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+_DPTR1
+_RADIOSTAT
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+_XTALREADY
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+_LPOSCFREQ
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+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
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+G$PINA_5$0$0
+G$WTCFGA$0$0
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+_AX5031_FREQA0NB
+_PCON
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+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
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+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
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+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
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+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
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+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
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+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
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+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
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+G$DIRA$0$0
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+__XPAGE
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+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
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+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
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+G$EIE_1$0$0
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+G$SP$0$0
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+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
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+G$IE_7$0$0
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+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
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+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
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+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
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+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
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+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
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+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
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+_PORTA_6
+_PORTB_5
+_PORTC_4
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+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
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+G$PINA$0$0
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+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
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+_CY
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+_PORTB_6
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+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
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+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
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+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
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+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
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+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5031rdfifo.c$10$0$0
+C$ax5031rdfifo.c$74$1$66
+C$ax5031rdfifo.c$75$1$66
+G$ax5031_readfifo$0$0
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+
+
+
+ax5031wrfifo 3839547
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5031_FOURFSK
+_AX5031_FREQA1
+_AX5031_FREQB0
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5031_FIFOCOUNT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5031_FREQA2
+_AX5031_FREQB1
+_AX5031_TXBITRATEMIDNB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5031_XTALOSCNB$0$0
+G$AX5031_PWRMODENB$0$0
+G$AX5031_XTALOSCCFG$0$0
+G$AX5031_PLLRANGING$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5031_FREQA3
+_AX5031_FREQB2
+_AX5031_PLLLOOP
+_AX5031_TXBITRATELONB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5031_FREQA0NB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5031_FREQB3
+_AX5031_MODULATORMISC
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5031_FREQB0NB$0$0
+G$AX5031_FREQA1NB$0$0
+G$AX5031_FOURFSKNB$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5031_FREQB1NB$0$0
+G$AX5031_FREQA2NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5031_TXPWR
+_AX5031_IRQREQUESTNB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5031_PLLLOOPNB$0$0
+G$AX5031_FREQB2NB$0$0
+G$AX5031_FREQA3NB$0$0
+G$AX5031_FIFOTHRESH$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5031_MODULATORMISCNB$0$0
+G$AX5031_FREQB3NB$0$0
+G$AX5031_FSKDEV0$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5031_VREG$0$0
+G$AX5031_IFMODE$0$0
+G$AX5031_FSKDEV1$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5031_PINCFG1
+_AX5031_IRQMASKNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5031_TXPWRNB$0$0
+G$AX5031_FSKDEV2$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5031_IRQINVERSION
+_AX5031_PINCFG2
+_AX5031_PLLRNGCLK
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5031_PINCFG3
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5031_FIFOCONTROL2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_IP_4
+G$AX5031_PINCFG1NB$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_EIP_0
+_IP_5
+G$AX5031_PLLRNGCLKNB$0$0
+G$AX5031_PINCFG2NB$0$0
+G$AX5031_IRQINVERSIONNB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5031_FIFOCOUNT
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5031_PINCFG3NB$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5031_PLLRANGING
+_AX5031_XTALOSCCFG
+_AX5031_PWRMODENB
+_AX5031_XTALOSCNB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5031_FREQA0NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5031_MODULATION$0$0
+G$AX5031_CRCINIT0$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5031_FOURFSKNB
+_AX5031_FREQA1NB
+_AX5031_FREQB0NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5031_FIFOCOUNTNB$0$0
+G$AX5031_CRCINIT1$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5031_FREQA2NB
+_AX5031_FREQB1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5031_XTALOSCCFGNB$0$0
+G$AX5031_PLLRANGINGNB$0$0
+G$AX5031_FIFODATA$0$0
+G$AX5031_CRCINIT2$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5031_FIFOTHRESH
+_AX5031_FREQA3NB
+_AX5031_FREQB2NB
+_AX5031_PLLLOOPNB
+_EIP_6
+G$AX5031_CRCINIT3$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5031_FSKDEV0
+_AX5031_FREQB3NB
+_AX5031_MODULATORMISCNB
+_EIP_7
+G$AX5031_SILICONREVISION$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5031_FSKDEV1
+_AX5031_IFMODE
+_AX5031_VREG
+_XPAGE
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5031_FSKDEV2
+_AX5031_TXPWRNB
+_RADIOACC
+_F0
+G$AX5031_FIFOTHRESHNB$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5031_FSKDEV0NB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5031_FIFOCONTROL2
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5031_VREGNB$0$0
+G$AX5031_IFMODENB$0$0
+G$AX5031_FSKDEV1NB$0$0
+G$AX5031_FRAMING$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5031_PINCFG1NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5031_FSKDEV2NB$0$0
+G$AX5031_FIFOCONTROL$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5031_IRQINVERSIONNB
+_AX5031_PINCFG2NB
+_AX5031_PLLRNGCLKNB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5031_PINCFG3NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5031_FIFOCONTROL2NB$0$0
+G$AX5031_ENCODING$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5031_TXBITRATEHI$0$0
+G$AX5031_SCRATCH$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5031_CRCINIT0
+_AX5031_MODULATION
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5031_CRCINIT1
+_AX5031_FIFOCOUNTNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5031_CRCINIT2
+_AX5031_FIFODATA
+_AX5031_PLLRANGINGNB
+_AX5031_XTALOSCCFGNB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5031_CRCINIT3
+_PINC_7
+G$AX5031_MODULATIONNB$0$0
+G$AX5031_CRCINIT0NB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5031_SILICONREVISION
+_WTCNTA0
+G$AX5031_CRCINIT1NB$0$0
+G$AX5031_XTALCAP$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5031_FIFODATANB$0$0
+G$AX5031_CRCINIT2NB$0$0
+G$AX5031_FEC$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5031_FIFOTHRESHNB
+_WTCNTB1
+G$AX5031_CRCINIT3NB$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5031_FSKDEV0NB
+_AC
+G$AX5031_SILICONREVISIONNB$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5031_FRAMING
+_AX5031_FSKDEV1NB
+_AX5031_IFMODENB
+_AX5031_VREGNB
+_E2IE
+G$AX5031_TXBITRATEMID$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5031_FIFOCONTROL
+_AX5031_FSKDEV2NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5031_TXBITRATELO$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5031_ENCODING
+_AX5031_FIFOCONTROL2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5031_FRAMINGNB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5031_SCRATCH
+_AX5031_TXBITRATEHI
+_RADIODATA
+_T2PERIOD
+G$AX5031_FIFOCONTROLNB$0$0
+G$AX5031_IRQREQUEST$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_ADCCLKSRC
+_RADIOADDR
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_WTEVTA0
+G$AX5031_ENCODINGNB$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5031_TXBITRATEHINB$0$0
+G$AX5031_SCRATCHNB$0$0
+G$AX5031_IRQMASK$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5031_CRCINIT0NB
+_AX5031_MODULATIONNB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5031_XTALCAP
+_AX5031_CRCINIT1NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5031_FEC
+_AX5031_CRCINIT2NB
+_AX5031_FIFODATANB
+_DBGLNKBUF
+_WTEVTD1
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5031_CRCINIT3NB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5031_SILICONREVISIONNB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5031_XTALCAPNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5031_TXBITRATEMID
+_WTCNTB
+_B_1
+G$AX5031_FECNB$0$0
+G$AX5031_XTALOSC$0$0
+G$AX5031_PWRMODE$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5031_TXBITRATELO
+_EIE
+_WTCNTR1
+_B_2
+G$AX5031_FREQA0$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5031_FREQB0$0$0
+G$AX5031_FREQA1$0$0
+G$AX5031_FOURFSK$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5031_FRAMINGNB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5031_TXBITRATEMIDNB$0$0
+G$AX5031_FREQB1$0$0
+G$AX5031_FREQA2$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5031_IRQREQUEST
+_AX5031_FIFOCONTROLNB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5031_TXBITRATELONB$0$0
+G$AX5031_PLLLOOP$0$0
+G$AX5031_FREQB2$0$0
+G$AX5031_FREQA3$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5031_MODULATORMISC$0$0
+G$AX5031_FREQB3$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5031_ENCODINGNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5031_IRQMASK
+_AX5031_SCRATCHNB
+_AX5031_TXBITRATEHINB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5031_IRQREQUESTNB$0$0
+G$AX5031_TXPWR$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5031_IRQMASKNB$0$0
+G$AX5031_PINCFG1$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5031_PLLRNGCLK$0$0
+G$AX5031_PINCFG2$0$0
+G$AX5031_IRQINVERSION$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5031_XTALCAPNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5031_PINCFG3$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5031_PWRMODE
+_AX5031_XTALOSC
+_AX5031_FECNB
+_E2IP_0
+_IE_2
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5031_FREQA0
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5031wrfifo$1511
+A$ax5031wrfifo$1502
+A$ax5031wrfifo$1512
+A$ax5031wrfifo$1503
+A$ax5031wrfifo$1513
+A$ax5031wrfifo$1504
+A$ax5031wrfifo$1514
+A$ax5031wrfifo$1505
+A$ax5031wrfifo$1460
+A$ax5031wrfifo$1515
+A$ax5031wrfifo$1506
+A$ax5031wrfifo$1470
+A$ax5031wrfifo$1461
+A$ax5031wrfifo$1516
+A$ax5031wrfifo$1480
+A$ax5031wrfifo$1471
+A$ax5031wrfifo$1462
+A$ax5031wrfifo$1508
+A$ax5031wrfifo$1481
+A$ax5031wrfifo$1472
+A$ax5031wrfifo$1463
+A$ax5031wrfifo$1509
+A$ax5031wrfifo$1491
+A$ax5031wrfifo$1464
+A$ax5031wrfifo$1492
+A$ax5031wrfifo$1483
+A$ax5031wrfifo$1474
+A$ax5031wrfifo$1465
+A$ax5031wrfifo$1493
+A$ax5031wrfifo$1484
+A$ax5031wrfifo$1466
+A$ax5031wrfifo$1457
+A$ax5031wrfifo$1494
+A$ax5031wrfifo$1485
+A$ax5031wrfifo$1467
+A$ax5031wrfifo$1458
+A$ax5031wrfifo$1495
+A$ax5031wrfifo$1486
+A$ax5031wrfifo$1477
+A$ax5031wrfifo$1459
+A$ax5031wrfifo$1496
+A$ax5031wrfifo$1487
+A$ax5031wrfifo$1478
+A$ax5031wrfifo$1469
+A$ax5031wrfifo$1497
+A$ax5031wrfifo$1488
+A$ax5031wrfifo$1479
+A$ax5031wrfifo$1498
+A$ax5031wrfifo$1489
+C$ax5031wrfifo.c$10$0$0
+C$ax5031wrfifo.c$75$1$66
+C$ax5031wrfifo.c$76$1$66
+G$ax5031_writefifo$0$0
+_ax5031_writefifo
+XG$ax5031_writefifo$0$0
+A$ax5031wrfifo$1500
+A$ax5031wrfifo$1510
+A$ax5031wrfifo$1501
+
+
+
+ax5031regs 3883564
+.__.ABS.
+
+
+
+ax5042comminit 3884602
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
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+
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+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
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+_ANALOGA
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+_AX5042_MODULATORMISCNB
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+_AX5042_CICDECLO
+_ADCCH0CONFIG
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+_PSW
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+_CLKCON
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+_RADIODATA1
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+_U0CTRL
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+G$PORTB$0$0
+G$ACC$0$0
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+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
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+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
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+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
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+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
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+G$ADCCLKSRC$0$0
+_INTCHGA
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+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
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+G$PINSEL$0$0
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+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
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+.__.ABS.
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+G$NVKEY$0$0
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+G$DMA0ADDR1$0$0
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+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
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+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
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+_WTCNTB1
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+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
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+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042commslpexit.c$24$1$66
+C$ax5042commslpexit.c$15$1$66
+C$ax5042commslpexit.c$25$1$66
+C$ax5042commslpexit.c$16$1$66
+C$ax5042commslpexit.c$8$0$0
+G$ax5042_commsleepexit$0$0
+_ax5042_commsleepexit
+A$ax5042commslpexit$1600
+A$ax5042commslpexit$1610
+A$ax5042commslpexit$1601
+A$ax5042commslpexit$1620
+A$ax5042commslpexit$1611
+A$ax5042commslpexit$1602
+A$ax5042commslpexit$1621
+A$ax5042commslpexit$1612
+A$ax5042commslpexit$1603
+A$ax5042commslpexit$1622
+A$ax5042commslpexit$1613
+A$ax5042commslpexit$1604
+XG$ax5042_commsleepexit$0$0
+A$ax5042commslpexit$1623
+A$ax5042commslpexit$1614
+A$ax5042commslpexit$1615
+A$ax5042commslpexit$1607
+A$ax5042commslpexit$1626
+A$ax5042commslpexit$1618
+A$ax5042commslpexit$1619
+A$ax5042commslpexit$1629
+A$ax5042commslpexit$1593
+A$ax5042commslpexit$1596
+A$ax5042commslpexit$1599
+C$ax5042commslpexit.c$10$1$66
+C$ax5042commslpexit.c$11$1$66
+C$ax5042commslpexit.c$12$1$66
+C$ax5042commslpexit.c$13$1$66
+
+
+
+ax5042reset 3980035
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
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+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
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+G$OC1MODE$0$0
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+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
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+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
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+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
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+G$AX5042_TRKAMPLITUDEHI$0$0
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+G$WTIRQEN$0$0
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+_DMA1ADDR
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+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
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+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042reset.c$8$0$0
+_ax5042_reset
+_ax5042_probeirq
+XG$ax5042_reset$0$0
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+A$ax5042reset$1610
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+A$ax5042reset$1789
+A$ax5042reset$1799
+C$ax5042reset.c$20$1$66
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+C$ax5042reset.c$90$2$69
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+C$ax5042reset.c$77$1$68
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+C$ax5042reset.c$94$2$69
+C$ax5042reset.c$78$1$68
+G$ax5042_reset$0$0
+C$ax5042reset.c$97$1$68
+C$ax5042reset.c$86$2$69
+C$ax5042reset.c$79$1$68
+G$ax5042_probeirq$0$0
+C$ax5042reset.c$98$1$68
+C$ax5042reset.c$87$2$69
+C$ax5042reset.c$99$1$68
+C$ax5042reset.c$88$2$69
+
+
+
+ax5042deepsleep 4034424
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
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+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
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+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
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+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
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+G$PALTA$0$0
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+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
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+G$AX5042_TRKFREQHI$0$0
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+_ADCCH1VAL
+_FRCOSCPER
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+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
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+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
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+G$ADCTUNE0$0$0
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+_ADCCH2VAL
+_LPOSCPER
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+_AX5042_IRQREQUESTNB
+_PINA
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+G$AX5042_FECSTATUS$0$0
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+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
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+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
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+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
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+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
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+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
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+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5042rclkena 4080562
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5042_rclk_enable$0$0
+_ax5042_rclk_enable
+A$ax5042rclkena$1620
+A$ax5042rclkena$1611
+A$ax5042rclkena$1602
+A$ax5042rclkena$1621
+A$ax5042rclkena$1612
+A$ax5042rclkena$1622
+A$ax5042rclkena$1613
+A$ax5042rclkena$1650
+A$ax5042rclkena$1632
+A$ax5042rclkena$1623
+A$ax5042rclkena$1633
+A$ax5042rclkena$1624
+A$ax5042rclkena$1606
+A$ax5042rclkena$1643
+A$ax5042rclkena$1625
+A$ax5042rclkena$1616
+A$ax5042rclkena$1607
+A$ax5042rclkena$1653
+A$ax5042rclkena$1644
+A$ax5042rclkena$1626
+A$ax5042rclkena$1608
+A$ax5042rclkena$1645
+A$ax5042rclkena$1636
+A$ax5042rclkena$1637
+A$ax5042rclkena$1619
+A$ax5042rclkena$1638
+A$ax5042rclkena$1629
+A$ax5042rclkena$1639
+A$ax5042rclkena$1594
+XG$ax5042_rclk_enable$0$0
+A$ax5042rclkena$1649
+A$ax5042rclkena$1597
+C$ax5042rclkena.c$10$1$64
+A$ax5042rclkena$1599
+C$ax5042rclkena.c$11$1$64
+C$ax5042rclkena.c$12$1$64
+C$ax5042rclkena.c$13$1$64
+C$ax5042rclkena.c$14$1$64
+C$ax5042rclkena.c$15$1$64
+C$ax5042rclkena.c$16$1$64
+C$ax5042rclkena.c$17$1$64
+C$ax5042rclkena.c$18$1$64
+C$ax5042rclkena.c$19$1$64
+C$ax5042rclkena.c$8$1$64
+C$ax5042rclkena.c$9$1$64
+C$ax5042rclkena.c$5$0$0
+
+
+
+ax5042rclkdis 4128984
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5042_rclk_disable
+C$ax5042rclkdis.c$8$1$64
+C$ax5042rclkdis.c$9$1$64
+C$ax5042rclkdis.c$5$0$0
+XG$ax5042_rclk_disable$0$0
+A$ax5042rclkdis$1600
+A$ax5042rclkdis$1610
+A$ax5042rclkdis$1620
+A$ax5042rclkdis$1611
+A$ax5042rclkdis$1621
+A$ax5042rclkdis$1612
+A$ax5042rclkdis$1603
+A$ax5042rclkdis$1622
+A$ax5042rclkdis$1632
+A$ax5042rclkdis$1633
+A$ax5042rclkdis$1615
+A$ax5042rclkdis$1606
+A$ax5042rclkdis$1616
+A$ax5042rclkdis$1607
+A$ax5042rclkdis$1626
+A$ax5042rclkdis$1608
+A$ax5042rclkdis$1636
+A$ax5042rclkdis$1627
+A$ax5042rclkdis$1609
+A$ax5042rclkdis$1628
+A$ax5042rclkdis$1619
+A$ax5042rclkdis$1595
+A$ax5042rclkdis$1596
+A$ax5042rclkdis$1597
+C$ax5042rclkdis.c$10$1$64
+C$ax5042rclkdis.c$11$1$64
+C$ax5042rclkdis.c$12$1$64
+C$ax5042rclkdis.c$13$1$64
+C$ax5042rclkdis.c$14$1$64
+C$ax5042rclkdis.c$15$1$64
+G$ax5042_rclk_disable$0$0
+C$ax5042rclkdis.c$16$1$64
+
+
+
+ax5042rdfifo 4176798
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5042rdfifo.c$10$0$0
+C$ax5042rdfifo.c$74$1$66
+C$ax5042rdfifo.c$75$1$66
+G$ax5042_readfifo$0$0
+_ax5042_readfifo
+XG$ax5042_readfifo$0$0
+A$ax5042rdfifo$1610
+A$ax5042rdfifo$1601
+A$ax5042rdfifo$1620
+A$ax5042rdfifo$1611
+A$ax5042rdfifo$1602
+A$ax5042rdfifo$1630
+A$ax5042rdfifo$1621
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+A$ax5042rdfifo$1640
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+A$ax5042rdfifo$1623
+A$ax5042rdfifo$1642
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+A$ax5042rdfifo$1624
+A$ax5042rdfifo$1615
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+A$ax5042rdfifo$1643
+A$ax5042rdfifo$1634
+A$ax5042rdfifo$1625
+A$ax5042rdfifo$1616
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+A$ax5042rdfifo$1590
+A$ax5042rdfifo$1645
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+A$ax5042rdfifo$1627
+A$ax5042rdfifo$1618
+A$ax5042rdfifo$1609
+A$ax5042rdfifo$1591
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+A$ax5042rdfifo$1637
+A$ax5042rdfifo$1628
+A$ax5042rdfifo$1619
+A$ax5042rdfifo$1592
+A$ax5042rdfifo$1647
+A$ax5042rdfifo$1638
+A$ax5042rdfifo$1629
+A$ax5042rdfifo$1593
+A$ax5042rdfifo$1594
+A$ax5042rdfifo$1595
+A$ax5042rdfifo$1596
+A$ax5042rdfifo$1597
+A$ax5042rdfifo$1598
+A$ax5042rdfifo$1589
+A$ax5042rdfifo$1599
+
+
+
+ax5042wrfifo 4225648
+G$AX5042_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5042_FREQ0
+_AX5042_PWRMODE
+_AX5042_XTALOSC
+_AX5042_FECNB
+_AX5042_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5042_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5042_FREQ1
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5042_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5042_FREQ2
+_AX5042_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5042_REFNB$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5042_DATARATELO
+_AX5042_FREQ3
+_AX5042_FREQUENCYGAINNB
+_AX5042_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5042_XTALOSCNB$0$0
+G$AX5042_PWRMODENB$0$0
+G$AX5042_FREQ0NB$0$0
+G$AX5042_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5042_PLLLOOP
+_AX5042_AGCTARGETNB
+_AX5042_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5042_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5042_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5042_FREQ2NB$0$0
+G$AX5042_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5042_FREQ3NB$0$0
+G$AX5042_DATARATELONB$0$0
+G$AX5042_TRKAMPLITUDELO$0$0
+G$AX5042_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5042_TXPWR
+_AX5042_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5042_PLLLOOPNB$0$0
+G$AX5042_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5042_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5042_MODULATORMISCNB$0$0
+G$AX5042_TRKPHASEHI$0$0
+G$AX5042_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5042_TRKAMPLITUDEHI
+_AX5042_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5042_IFMODE$0$0
+G$AX5042_FSKDEV1$0$0
+G$AX5042_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5042_PINCFG1
+_AX5042_IFFREQLONB
+_AX5042_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5042_TXPWRNB$0$0
+G$AX5042_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5042_IRQINVERSION
+_AX5042_PINCFG2
+_AX5042_PLLRNGCLK
+_AX5042_PLLVCOINB
+_IP_4
+G$AX5042_CICDECLO$0$0
+G$AX5042_APEOVERRIDE$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5042_PINCFG3
+_EIP_0
+_IP_5
+G$AX5042_TRKAMPLITUDEHINB$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5042_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5042_PINCFG1NB$0$0
+G$AX5042_TXDSPMODE$0$0
+G$AX5042_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5042_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5042_PLLRNGCLKNB$0$0
+G$AX5042_PINCFG2NB$0$0
+G$AX5042_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5042_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5042_PINCFG3NB$0$0
+G$AX5042_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5042_PLLRANGING
+_AX5042_FREQ0NB
+_AX5042_PWRMODENB
+_AX5042_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5042_AGCCOUNTERNB$0$0
+G$AX5042_PLLRNGMISC$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5042_FREQ1NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5042_CICDECHINB$0$0
+G$AX5042_MODULATION$0$0
+G$AX5042_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5042_TRKFREQHI
+_AX5042_FREQ2NB
+_EIP_6
+G$AX5042_TRKPHASELO$0$0
+G$AX5042_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5042_AGCDECAY
+_AX5042_TRKAMPLITUDELO
+_AX5042_DATARATELONB
+_AX5042_FREQ3NB
+_EIP_7
+G$AX5042_PLLRANGINGNB$0$0
+G$AX5042_FIFODATA$0$0
+G$AX5042_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5042_FECSTATUS
+_AX5042_PLLLOOPNB
+_XPAGE
+G$AX5042_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5042_FSKDEV0
+_AX5042_TRKPHASEHI
+_AX5042_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5042_TRKFREQHINB$0$0
+G$AX5042_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5042_ADCMISC
+_AX5042_FSKDEV1
+_AX5042_IFMODE
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5042_TRKAMPLITUDELONB$0$0
+G$AX5042_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5042_FSKDEV2
+_AX5042_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5042_FECSTATUSNB$0$0
+G$AX5042_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5042_APEOVERRIDE
+_AX5042_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5042_TRKPHASEHINB$0$0
+G$AX5042_FSKDEV0NB$0$0
+G$AX5042_FREQUENCYGAIN2$0$0
+G$AX5042_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5042_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5042_IFMODENB$0$0
+G$AX5042_FSKDEV1NB$0$0
+G$AX5042_ADCMISCNB$0$0
+G$AX5042_FRAMING$0$0
+G$AX5042_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5042_TIMINGGAINHI
+_AX5042_TXDSPMODE
+_AX5042_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5042_FSKDEV2NB$0$0
+G$AX5042_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5042_IRQINVERSIONNB
+_AX5042_PINCFG2NB
+_AX5042_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5042_CICDECLONB$0$0
+G$AX5042_APEOVERRIDENB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5042_TRKFREQLO
+_AX5042_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5042_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5042_PLLRNGMISC
+_AX5042_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5042_TXDSPMODENB$0$0
+G$AX5042_TIMINGGAINHINB$0$0
+G$AX5042_TXBITRATEHI$0$0
+G$AX5042_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5042_CRCINIT0
+_AX5042_MODULATION
+_AX5042_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5042_CRCINIT1
+_AX5042_TRKPHASELO
+_PINC_7
+G$AX5042_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5042_CRCINIT2
+_AX5042_FIFODATA
+_AX5042_PLLRANGINGNB
+_WTCNTA0
+G$AX5042_PLLRNGMISCNB$0$0
+G$AX5042_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5042_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5042_MODULATIONNB$0$0
+G$AX5042_CRCINIT0NB$0$0
+G$AX5042_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5042_SILICONREVISION
+_AX5042_TRKFREQHINB
+_WTCNTB1
+G$AX5042_TRKPHASELONB$0$0
+G$AX5042_CRCINIT1NB$0$0
+G$AX5042_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5042_AGCDECAYNB
+_AX5042_TRKAMPLITUDELONB
+_AC
+G$AX5042_FIFODATANB$0$0
+G$AX5042_CRCINIT2NB$0$0
+G$AX5042_IFFREQHI$0$0
+G$AX5042_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5042_TIMINGGAINLO
+_AX5042_FECSTATUSNB
+_E2IE
+G$AX5042_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5042_AGCATTACK
+_AX5042_FREQUENCYGAIN2
+_AX5042_FSKDEV0NB
+_AX5042_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5042_SILICONREVISIONNB$0$0
+G$AX5042_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5042_AMPLITUDEGAIN
+_AX5042_FRAMING
+_AX5042_ADCMISCNB
+_AX5042_FSKDEV1NB
+_AX5042_IFMODENB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5042_TXBITRATEMID$0$0
+G$AX5042_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5042_FIFOCONTROL
+_AX5042_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5042_TIMINGGAINLONB$0$0
+G$AX5042_TXBITRATELO$0$0
+G$AX5042_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5042_APEOVERRIDENB
+_AX5042_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5042_FREQUENCYGAIN2NB$0$0
+G$AX5042_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5042_ENCODING
+_ADCCLKSRC
+_RADIOADDR
+G$AX5042_FRAMINGNB$0$0
+G$AX5042_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5042_SCRATCH
+_AX5042_TXBITRATEHI
+_AX5042_TIMINGGAINHINB
+_AX5042_TXDSPMODENB
+_WTEVTA0
+G$AX5042_FIFOCONTROLNB$0$0
+G$AX5042_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5042_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5042_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5042_ENCODINGNB$0$0
+G$AX5042_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5042_FECSYNC
+_AX5042_PLLRNGMISCNB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5042_TXBITRATEHINB$0$0
+G$AX5042_SCRATCHNB$0$0
+G$AX5042_IRQMASK$0$0
+G$AX5042_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5042_DSPMODE
+_AX5042_CRCINIT0NB
+_AX5042_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5042_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5042_CICSHIFT
+_AX5042_CRCINIT1NB
+_AX5042_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5042_FEC
+_AX5042_IFFREQHI
+_AX5042_CRCINIT2NB
+_AX5042_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5042_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5042_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5042_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5042_PHASEGAIN
+_AX5042_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5042_CICSHIFTNB$0$0
+G$AX5042_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5042_FREQUENCYGAIN
+_AX5042_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5042_IFFREQHINB$0$0
+G$AX5042_FECNB$0$0
+G$AX5042_XTALOSC$0$0
+G$AX5042_PWRMODE$0$0
+G$AX5042_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5042_AGCTARGET
+_AX5042_TXBITRATELO
+_AX5042_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5042_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5042_AGCATTACKNB
+_AX5042_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5042_PHASEGAINNB$0$0
+G$AX5042_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5042_AMPLITUDEGAINNB
+_AX5042_FRAMINGNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5042_TXBITRATEMIDNB$0$0
+G$AX5042_FREQUENCYGAINNB$0$0
+G$AX5042_FREQ3$0$0
+G$AX5042_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5042_IRQREQUEST
+_AX5042_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5042_TXBITRATELONB$0$0
+G$AX5042_AGCTARGETNB$0$0
+G$AX5042_PLLLOOP$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5042_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5042_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5042_DATARATEHI
+_AX5042_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5042_IFFREQLO
+_AX5042_IRQMASK
+_AX5042_SCRATCHNB
+_AX5042_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5042_IRQREQUESTNB$0$0
+G$AX5042_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5042_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5042_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5042_DATARATEHINB$0$0
+G$AX5042_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5042_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5042_IRQMASKNB$0$0
+G$AX5042_IFFREQLONB$0$0
+G$AX5042_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5042_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5042_PLLVCOINB$0$0
+G$AX5042_PLLRNGCLK$0$0
+G$AX5042_PINCFG2$0$0
+G$AX5042_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5042_REF
+_AX5042_CICSHIFTNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5042wrfifo$1610
+A$ax5042wrfifo$1601
+A$ax5042wrfifo$1620
+A$ax5042wrfifo$1611
+A$ax5042wrfifo$1602
+A$ax5042wrfifo$1630
+A$ax5042wrfifo$1621
+A$ax5042wrfifo$1612
+A$ax5042wrfifo$1603
+A$ax5042wrfifo$1640
+A$ax5042wrfifo$1613
+A$ax5042wrfifo$1604
+A$ax5042wrfifo$1641
+A$ax5042wrfifo$1632
+A$ax5042wrfifo$1623
+A$ax5042wrfifo$1642
+A$ax5042wrfifo$1633
+A$ax5042wrfifo$1624
+A$ax5042wrfifo$1615
+A$ax5042wrfifo$1606
+A$ax5042wrfifo$1643
+A$ax5042wrfifo$1634
+A$ax5042wrfifo$1625
+A$ax5042wrfifo$1616
+A$ax5042wrfifo$1644
+A$ax5042wrfifo$1635
+A$ax5042wrfifo$1626
+A$ax5042wrfifo$1617
+A$ax5042wrfifo$1590
+A$ax5042wrfifo$1645
+A$ax5042wrfifo$1636
+A$ax5042wrfifo$1627
+A$ax5042wrfifo$1618
+A$ax5042wrfifo$1609
+A$ax5042wrfifo$1591
+A$ax5042wrfifo$1646
+A$ax5042wrfifo$1637
+A$ax5042wrfifo$1628
+A$ax5042wrfifo$1619
+A$ax5042wrfifo$1592
+A$ax5042wrfifo$1647
+A$ax5042wrfifo$1638
+A$ax5042wrfifo$1629
+A$ax5042wrfifo$1593
+A$ax5042wrfifo$1648
+A$ax5042wrfifo$1594
+A$ax5042wrfifo$1595
+A$ax5042wrfifo$1596
+A$ax5042wrfifo$1597
+A$ax5042wrfifo$1598
+A$ax5042wrfifo$1589
+A$ax5042wrfifo$1599
+C$ax5042wrfifo.c$10$0$0
+C$ax5042wrfifo.c$75$1$66
+C$ax5042wrfifo.c$76$1$66
+G$ax5042_writefifo$0$0
+_ax5042_writefifo
+XG$ax5042_writefifo$0$0
+
+
+
+ax5042regs 4274573
+.__.ABS.
+
+
+
+ax5043comminit 4275611
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
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+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
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+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
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+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043comminit.c$8$0$0
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+C$ax5043comminit.c$11$1$66
+C$ax5043comminit.c$12$1$66
+C$ax5043comminit.c$13$1$66
+C$ax5043comminit.c$23$1$66
+C$ax5043comminit.c$24$1$66
+C$ax5043comminit.c$15$1$66
+C$ax5043comminit.c$16$1$66
+G$ax5043_comminit$0$0
+
+
+
+ax5043commslpexit 4381721
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043commslpexit.c$24$1$66
+C$ax5043commslpexit.c$15$1$66
+C$ax5043commslpexit.c$25$1$66
+C$ax5043commslpexit.c$16$1$66
+C$ax5043commslpexit.c$8$0$0
+G$ax5043_commsleepexit$0$0
+_ax5043_commsleepexit
+A$ax5043commslpexit$3301
+A$ax5043commslpexit$3302
+A$ax5043commslpexit$3312
+A$ax5043commslpexit$3303
+A$ax5043commslpexit$3304
+A$ax5043commslpexit$3305
+XG$ax5043_commsleepexit$0$0
+A$ax5043commslpexit$3306
+A$ax5043commslpexit$3290
+A$ax5043commslpexit$3309
+A$ax5043commslpexit$3282
+A$ax5043commslpexit$3283
+A$ax5043commslpexit$3293
+A$ax5043commslpexit$3284
+A$ax5043commslpexit$3294
+A$ax5043commslpexit$3285
+A$ax5043commslpexit$3276
+A$ax5043commslpexit$3295
+A$ax5043commslpexit$3286
+A$ax5043commslpexit$3296
+A$ax5043commslpexit$3287
+A$ax5043commslpexit$3297
+A$ax5043commslpexit$3279
+A$ax5043commslpexit$3298
+C$ax5043commslpexit.c$10$1$66
+C$ax5043commslpexit.c$11$1$66
+C$ax5043commslpexit.c$12$1$66
+C$ax5043commslpexit.c$13$1$66
+
+
+
+ax5043reset 4488032
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$RADIODRV$0$0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIODRV
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043reset.c$8$0$0
+_ax5043_reset
+_ax5043_probeirq
+XG$ax5043_reset$0$0
+XG$ax5043_probeirq$0$0
+A$ax5043reset$3400
+A$ax5043reset$3310
+A$ax5043reset$3311
+A$ax5043reset$3302
+A$ax5043reset$3330
+A$ax5043reset$3321
+A$ax5043reset$3312
+A$ax5043reset$3303
+A$ax5043reset$3502
+A$ax5043reset$3430
+A$ax5043reset$3331
+A$ax5043reset$3322
+A$ax5043reset$3313
+A$ax5043reset$3304
+A$ax5043reset$3512
+A$ax5043reset$3422
+A$ax5043reset$3323
+A$ax5043reset$3314
+A$ax5043reset$3305
+A$ax5043reset$3450
+A$ax5043reset$3360
+A$ax5043reset$3342
+A$ax5043reset$3315
+A$ax5043reset$3306
+A$ax5043reset$3442
+A$ax5043reset$3433
+A$ax5043reset$3370
+A$ax5043reset$3352
+A$ax5043reset$3343
+A$ax5043reset$3334
+A$ax5043reset$3307
+A$ax5043reset$3515
+A$ax5043reset$3506
+A$ax5043reset$3443
+A$ax5043reset$3434
+A$ax5043reset$3425
+A$ax5043reset$3416
+A$ax5043reset$3371
+A$ax5043reset$3353
+A$ax5043reset$3335
+A$ax5043reset$3326
+A$ax5043reset$3290
+A$ax5043reset$3507
+A$ax5043reset$3480
+A$ax5043reset$3453
+A$ax5043reset$3444
+A$ax5043reset$3435
+A$ax5043reset$3381
+A$ax5043reset$3354
+A$ax5043reset$3327
+A$ax5043reset$3318
+A$ax5043reset$3291
+A$ax5043reset$3508
+A$ax5043reset$3481
+A$ax5043reset$3463
+A$ax5043reset$3454
+A$ax5043reset$3445
+A$ax5043reset$3391
+A$ax5043reset$3382
+A$ax5043reset$3364
+A$ax5043reset$3283
+A$ax5043reset$3509
+A$ax5043reset$3491
+A$ax5043reset$3482
+A$ax5043reset$3473
+A$ax5043reset$3464
+A$ax5043reset$3428
+A$ax5043reset$3419
+A$ax5043reset$3392
+A$ax5043reset$3374
+A$ax5043reset$3365
+A$ax5043reset$3347
+A$ax5043reset$3338
+A$ax5043reset$3519
+A$ax5043reset$3492
+A$ax5043reset$3465
+A$ax5043reset$3438
+A$ax5043reset$3429
+A$ax5043reset$3375
+A$ax5043reset$3357
+A$ax5043reset$3348
+A$ax5043reset$3339
+A$ax5043reset$3294
+A$ax5043reset$3493
+A$ax5043reset$3466
+A$ax5043reset$3448
+A$ax5043reset$3439
+A$ax5043reset$3376
+A$ax5043reset$3358
+A$ax5043reset$3286
+A$ax5043reset$3467
+A$ax5043reset$3458
+A$ax5043reset$3449
+A$ax5043reset$3386
+A$ax5043reset$3377
+A$ax5043reset$3359
+A$ax5043reset$3477
+A$ax5043reset$3468
+A$ax5043reset$3459
+A$ax5043reset$3396
+A$ax5043reset$3387
+A$ax5043reset$3369
+A$ax5043reset$3297
+A$ax5043reset$3496
+A$ax5043reset$3487
+A$ax5043reset$3478
+A$ax5043reset$3388
+A$ax5043reset$3298
+A$ax5043reset$3289
+A$ax5043reset$3479
+A$ax5043reset$3299
+A$ax5043reset$3499
+C$ax5043reset.c$20$1$66
+C$ax5043reset.c$12$1$66
+C$ax5043reset.c$22$1$66
+C$ax5043reset.c$13$1$66
+C$ax5043reset.c$32$1$66
+C$ax5043reset.c$23$1$66
+C$ax5043reset.c$60$1$66
+C$ax5043reset.c$51$1$66
+C$ax5043reset.c$42$1$66
+C$ax5043reset.c$15$1$66
+C$ax5043reset.c$61$1$66
+C$ax5043reset.c$52$1$66
+C$ax5043reset.c$43$1$66
+C$ax5043reset.c$53$1$66
+C$ax5043reset.c$35$1$66
+C$ax5043reset.c$70$1$68
+C$ax5043reset.c$54$1$66
+C$ax5043reset.c$36$1$66
+C$ax5043reset.c$71$1$68
+C$ax5043reset.c$55$1$66
+C$ax5043reset.c$19$1$66
+C$ax5043reset.c$72$1$68
+C$ax5043reset.c$56$1$66
+C$ax5043reset.c$80$2$69
+C$ax5043reset.c$73$1$68
+C$ax5043reset.c$66$1$66
+C$ax5043reset.c$48$1$66
+C$ax5043reset.c$39$1$66
+C$ax5043reset.c$92$1$68
+C$ax5043reset.c$90$2$69
+C$ax5043reset.c$81$2$69
+C$ax5043reset.c$74$1$68
+C$ax5043reset.c$58$1$66
+C$ax5043reset.c$49$1$66
+C$ax5043reset.c$93$1$68
+C$ax5043reset.c$91$2$69
+C$ax5043reset.c$75$1$68
+C$ax5043reset.c$59$1$66
+C$ax5043reset.c$94$1$68
+C$ax5043reset.c$83$2$69
+C$ax5043reset.c$76$1$68
+C$ax5043reset.c$69$1$66
+C$ax5043reset.c$95$1$68
+C$ax5043reset.c$84$2$69
+C$ax5043reset.c$77$1$68
+C$ax5043reset.c$96$1$68
+C$ax5043reset.c$85$2$69
+C$ax5043reset.c$78$1$68
+G$ax5043_reset$0$0
+G$ax5043_probeirq$0$0
+C$ax5043reset.c$87$2$69
+C$ax5043reset.c$79$2$69
+C$ax5043reset.c$89$2$69
+
+
+
+ax5043deepsleep 4600226
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043deepsleep.c$21$1$66
+C$ax5043deepsleep.c$12$1$66
+C$ax5043deepsleep.c$22$1$66
+C$ax5043deepsleep.c$13$1$66
+C$ax5043deepsleep.c$10$0$0
+C$ax5043deepsleep.c$31$1$68
+C$ax5043deepsleep.c$24$1$66
+C$ax5043deepsleep.c$32$1$68
+C$ax5043deepsleep.c$17$1$66
+C$ax5043deepsleep.c$41$2$69
+C$ax5043deepsleep.c$18$1$66
+_ax5043_wakeup_deepsleep
+C$ax5043deepsleep.c$42$2$69
+C$ax5043deepsleep.c$26$1$68
+C$ax5043deepsleep.c$19$1$66
+C$ax5043deepsleep.c$45$1$68
+C$ax5043deepsleep.c$43$2$69
+C$ax5043deepsleep.c$27$1$68
+C$ax5043deepsleep.c$46$1$68
+C$ax5043deepsleep.c$28$1$68
+C$ax5043deepsleep.c$47$1$68
+C$ax5043deepsleep.c$29$1$68
+C$ax5043deepsleep.c$48$1$68
+C$ax5043deepsleep.c$39$1$68
+G$ax5043_enter_deepsleep$0$0
+XG$ax5043_wakeup_deepsleep$0$0
+_ax5043_enter_deepsleep
+XG$ax5043_enter_deepsleep$0$0
+A$ax5043deepsleep$3300
+A$ax5043deepsleep$3330
+A$ax5043deepsleep$3303
+A$ax5043deepsleep$3340
+A$ax5043deepsleep$3331
+A$ax5043deepsleep$3304
+A$ax5043deepsleep$3350
+A$ax5043deepsleep$3341
+A$ax5043deepsleep$3323
+A$ax5043deepsleep$3305
+A$ax5043deepsleep$3342
+A$ax5043deepsleep$3361
+A$ax5043deepsleep$3334
+A$ax5043deepsleep$3362
+A$ax5043deepsleep$3353
+A$ax5043deepsleep$3326
+A$ax5043deepsleep$3308
+A$ax5043deepsleep$3281
+A$ax5043deepsleep$3372
+A$ax5043deepsleep$3363
+A$ax5043deepsleep$3354
+A$ax5043deepsleep$3345
+A$ax5043deepsleep$3291
+A$ax5043deepsleep$3282
+A$ax5043deepsleep$3382
+A$ax5043deepsleep$3373
+A$ax5043deepsleep$3364
+A$ax5043deepsleep$3355
+A$ax5043deepsleep$3346
+A$ax5043deepsleep$3337
+A$ax5043deepsleep$3292
+A$ax5043deepsleep$3283
+A$ax5043deepsleep$3374
+A$ax5043deepsleep$3347
+A$ax5043deepsleep$3338
+A$ax5043deepsleep$3329
+A$ax5043deepsleep$3348
+A$ax5043deepsleep$3339
+A$ax5043deepsleep$3367
+A$ax5043deepsleep$3358
+A$ax5043deepsleep$3349
+A$ax5043deepsleep$3295
+A$ax5043deepsleep$3286
+A$ax5043deepsleep$3386
+A$ax5043deepsleep$3377
+A$ax5043deepsleep$3368
+A$ax5043deepsleep$3296
+A$ax5043deepsleep$3287
+A$ax5043deepsleep$3278
+A$ax5043deepsleep$3378
+A$ax5043deepsleep$3297
+A$ax5043deepsleep$3288
+G$ax5043_wakeup_deepsleep$0$0
+A$ax5043deepsleep$3298
+A$ax5043deepsleep$3299
+
+
+
+ax5043rclkena 4708795
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5043_rclk_enable$0$0
+A$ax5043rclkena$3310
+_ax5043_rclk_enable
+A$ax5043rclkena$3311
+A$ax5043rclkena$3302
+A$ax5043rclkena$3330
+A$ax5043rclkena$3321
+A$ax5043rclkena$3303
+A$ax5043rclkena$3322
+A$ax5043rclkena$3304
+A$ax5043rclkena$3323
+A$ax5043rclkena$3314
+A$ax5043rclkena$3333
+A$ax5043rclkena$3324
+A$ax5043rclkena$3315
+A$ax5043rclkena$3325
+A$ax5043rclkena$3316
+A$ax5043rclkena$3307
+A$ax5043rclkena$3280
+A$ax5043rclkena$3317
+A$ax5043rclkena$3290
+A$ax5043rclkena$3291
+A$ax5043rclkena$3282
+A$ax5043rclkena$3329
+A$ax5043rclkena$3294
+A$ax5043rclkena$3285
+A$ax5043rclkena$3295
+A$ax5043rclkena$3277
+XG$ax5043_rclk_enable$0$0
+A$ax5043rclkena$3296
+A$ax5043rclkena$3289
+A$ax5043rclkena$3299
+C$ax5043rclkena.c$10$1$64
+C$ax5043rclkena.c$11$1$64
+C$ax5043rclkena.c$12$1$64
+C$ax5043rclkena.c$13$1$64
+C$ax5043rclkena.c$14$1$64
+C$ax5043rclkena.c$15$1$64
+C$ax5043rclkena.c$16$1$64
+C$ax5043rclkena.c$17$1$64
+C$ax5043rclkena.c$18$1$64
+C$ax5043rclkena.c$19$1$64
+C$ax5043rclkena.c$8$1$64
+C$ax5043rclkena.c$9$1$64
+C$ax5043rclkena.c$5$0$0
+
+
+
+ax5043rclkdis 4815572
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5043_rclk_disable
+C$ax5043rclkdis.c$8$1$64
+C$ax5043rclkdis.c$9$1$64
+C$ax5043rclkdis.c$5$0$0
+XG$ax5043_rclk_disable$0$0
+A$ax5043rclkdis$3300
+A$ax5043rclkdis$3301
+A$ax5043rclkdis$3302
+A$ax5043rclkdis$3312
+A$ax5043rclkdis$3313
+A$ax5043rclkdis$3305
+A$ax5043rclkdis$3306
+A$ax5043rclkdis$3316
+A$ax5043rclkdis$3307
+A$ax5043rclkdis$3280
+A$ax5043rclkdis$3308
+A$ax5043rclkdis$3290
+A$ax5043rclkdis$3291
+A$ax5043rclkdis$3283
+A$ax5043rclkdis$3294
+A$ax5043rclkdis$3295
+A$ax5043rclkdis$3286
+A$ax5043rclkdis$3296
+A$ax5043rclkdis$3278
+A$ax5043rclkdis$3279
+A$ax5043rclkdis$3289
+A$ax5043rclkdis$3299
+C$ax5043rclkdis.c$10$1$64
+C$ax5043rclkdis.c$11$1$64
+C$ax5043rclkdis.c$12$1$64
+C$ax5043rclkdis.c$13$1$64
+C$ax5043rclkdis.c$14$1$64
+C$ax5043rclkdis.c$15$1$64
+G$ax5043_rclk_disable$0$0
+C$ax5043rclkdis.c$16$1$64
+
+
+
+ax5043rdfifo 4921755
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5043rdfifo.c$10$0$0
+C$ax5043rdfifo.c$74$1$66
+C$ax5043rdfifo.c$75$1$66
+G$ax5043_readfifo$0$0
+_ax5043_readfifo
+A$ax5043rdfifo$3300
+A$ax5043rdfifo$3310
+A$ax5043rdfifo$3301
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+A$ax5043rdfifo$3330
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+A$ax5043rdfifo$3312
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+A$ax5043rdfifo$3315
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+A$ax5043rdfifo$3325
+A$ax5043rdfifo$3316
+A$ax5043rdfifo$3307
+A$ax5043rdfifo$3280
+A$ax5043rdfifo$3326
+A$ax5043rdfifo$3317
+A$ax5043rdfifo$3308
+A$ax5043rdfifo$3281
+A$ax5043rdfifo$3272
+A$ax5043rdfifo$3327
+A$ax5043rdfifo$3318
+A$ax5043rdfifo$3309
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+A$ax5043rdfifo$3273
+A$ax5043rdfifo$3328
+A$ax5043rdfifo$3319
+A$ax5043rdfifo$3292
+A$ax5043rdfifo$3274
+A$ax5043rdfifo$3329
+A$ax5043rdfifo$3293
+A$ax5043rdfifo$3284
+A$ax5043rdfifo$3275
+A$ax5043rdfifo$3294
+A$ax5043rdfifo$3285
+A$ax5043rdfifo$3276
+A$ax5043rdfifo$3295
+A$ax5043rdfifo$3286
+A$ax5043rdfifo$3277
+A$ax5043rdfifo$3296
+A$ax5043rdfifo$3287
+A$ax5043rdfifo$3278
+A$ax5043rdfifo$3279
+A$ax5043rdfifo$3298
+A$ax5043rdfifo$3289
+A$ax5043rdfifo$3299
+
+
+
+ax5043wrfifo 5029099
+G$AX5043_TMGRXBOOSTNB$0$0
+G$AX5043_PLLVCOINB$0$0
+G$AX5043_LPOSCPER1NB$0$0
+G$AX5043_IRQINVERSION0NB$0$0
+G$AX5043_PKTADDRMASK3$0$0
+G$AX5043_TRKRFFREQ2$0$0
+G$AX5043_TRKDATARATE2$0$0
+G$AX5043_PLLRNGCLK$0$0
+G$AX5043_PLLLOOPBOOST$0$0
+G$AX5043_PKTSTOREFLAGS$0$0
+G$XIC1CAPT0$0$0
+G$XIC0CAPT1$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_XT2PERIOD
+_AX5043_DECIMATION
+_AX5043_FIFOCOUNT0
+_AX5043_REF
+_AX5043_TMGRXAGC
+_AX5043_XTALSTATUS
+_AX5043_AGCGAIN3
+_AX5043_RADIOEVENTMASK0NB
+_AX5043_TMGRXPREAMBLE3NB
+_AX5043_XTALCAPNB
+_AX5043_BBOFFSRES1NB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5043_RXPARAMSETSNB$0$0
+G$AX5043_PKTADDRCFGNB$0$0
+G$AX5043_AGCGAIN0NB$0$0
+G$AX5043_TMGRXCOARSEAGCNB$0$0
+G$AX5043_PINFUNCANTSELNB$0$0
+G$AX5043_IRQINVERSION1NB$0$0
+G$AX5043_AFSKCTRLNB$0$0
+G$AX5043_PINFUNCPWRAMP$0$0
+G$XIC1CAPT1$0$0
+G$XCLKSTAT$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_XADCCLKSRC
+_AX5043_FIFOCOUNT1
+_AX5043_PWRMODE
+_AX5043_XTALOSC
+_AX5043_PKTLENCFG
+_AX5043_FECNB
+_AX5043_LPOSCREF0NB
+_AX5043_POWIRQMASKNB
+_AX5043_RADIOEVENTMASK1NB
+_AX5043_0xF00NB
+_AX5043_BBOFFSRES2NB
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5043_AGCGAIN1NB$0$0
+G$AX5043_TMGTXBOOSTNB$0$0
+G$AX5043_WAKEUPFREQ0$0$0
+G$AX5043_PLLVCOIR$0$0
+G$AX5043_LPOSCKFILT0$0$0
+G$AX5043_AGCCOUNTER$0$0
+G$XPORTR$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_XWTEVTA0
+_AX5043_FREQA0
+_AX5043_LPOSCFREQ0
+_AX5043_LPOSCREF1NB
+_AX5043_TRKFREQ0NB
+_AX5043_BBOFFSRES3NB
+_AX5043_FREQUENCYLEAKNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5043_AGCGAIN2NB$0$0
+G$AX5043_POWCTRL1NB$0$0
+G$AX5043_BGNDRSSINB$0$0
+G$AX5043_WAKEUPFREQ1$0$0
+G$AX5043_PINFUNCSYSCLK$0$0
+G$AX5043_LPOSCKFILT1$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_XWTEVTA1
+_XWTEVTB0
+_AX5043_FIFOSTAT
+_AX5043_FREQA1
+_AX5043_FREQB0
+_AX5043_LPOSCFREQ1
+_AX5043_RXDATARATE0
+_AX5043_RSSIREFERENCENB
+_AX5043_TRKFREQ1NB
+_AX5043_FOURFSK0NB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5043_AGCGAIN3NB$0$0
+G$AX5043_XTALSTATUSNB$0$0
+G$AX5043_TMGRXAGCNB$0$0
+G$AX5043_REFNB$0$0
+G$AX5043_FIFOCOUNT0NB$0$0
+G$AX5043_DECIMATIONNB$0$0
+G$AX5043_FREQDEV00$0$0
+G$AX5043_PINFUNCDATA$0$0
+G$AX5043_IFFREQ0$0$0
+G$XT0CNT0$0$0
+G$XIP$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_XNVKEY
+_XWTEVTB1
+_XWTEVTC0
+_AX5043_FREQA2
+_AX5043_FREQB1
+_AX5043_RXDATARATE1
+_AX5043_0xF0C
+_AX5043_0xF21NB
+_AX5043_0xF30NB
+_AX5043_FOURFSK1NB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5043_PKTLENCFGNB$0$0
+G$AX5043_XTALOSCNB$0$0
+G$AX5043_PWRMODENB$0$0
+G$AX5043_FIFOCOUNT1NB$0$0
+G$AX5043_FREQDEV10$0$0
+G$AX5043_FREQDEV01$0$0
+G$AX5043_TRKFSKDEMOD0$0$0
+G$AX5043_PLLLOCKDET$0$0
+G$AX5043_IFFREQ1$0$0
+G$XT1CNT0$0$0
+G$XT0CNT1$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_XIE
+_XWTEVTC1
+_XWTEVTD0
+_AX5043_FIFOTHRESH0
+_AX5043_FREQA3
+_AX5043_FREQB2
+_AX5043_GPADCPERIOD
+_AX5043_PLLLOOP
+_AX5043_RXDATARATE2
+_AX5043_0xF1C
+_AX5043_TRKPHASE0NB
+_AX5043_0xF22NB
+_AX5043_0xF31NB
+_AX5043_FOURFSK2NB
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5043_LPOSCFREQ0NB$0$0
+G$AX5043_FREQA0NB$0$0
+G$AX5043_FREQDEV11$0$0
+G$AX5043_FREQDEV02$0$0
+G$AX5043_TRKFSKDEMOD1$0$0
+G$AX5043_TRKAFSKDEMOD0$0$0
+G$AX5043_PLLRANGINGA$0$0
+G$XWTEVTA$0$0
+G$XT2CNT0$0$0
+G$XT1CNT1$0$0
+G$XRADIOSTAT0$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_XDBGLNKBUF
+_XWTEVTD1
+_AX5043_FIFOTHRESH1
+_AX5043_FREQB3
+_AX5043_PKTCHUNKSIZE
+_AX5043_TMGRXSETTLE
+_AX5043_XTALAMPL
+_AX5043_TMGRXRSSINB
+_AX5043_TRKPHASE1NB
+_AX5043_0xF23NB
+_AX5043_0xF32NB
+_AX5043_FOURFSK3NB
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5043_RXDATARATE0NB$0$0
+G$AX5043_LPOSCFREQ1NB$0$0
+G$AX5043_FREQB0NB$0$0
+G$AX5043_FREQA1NB$0$0
+G$AX5043_FIFOSTATNB$0$0
+G$AX5043_FREQDEV12$0$0
+G$AX5043_FREQDEV03$0$0
+G$AX5043_TRKAFSKDEMOD1$0$0
+G$AX5043_RADIOSTATE$0$0
+G$AX5043_PLLRANGINGB$0$0
+G$AX5043_GPADC13VALUE0$0$0
+G$AX5043_AMPLFILTER$0$0
+G$XWTEVTB$0$0
+G$XT2CNT1$0$0
+G$XSPSHREG$0$0
+G$XRADIOSTAT1$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5043_GPADCCTRLNB
+_AX5043_0xF33NB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5043_0xF0CNB$0$0
+G$AX5043_RXDATARATE1NB$0$0
+G$AX5043_FREQB1NB$0$0
+G$AX5043_FREQA2NB$0$0
+G$AX5043_RXPARAMCURSET$0$0
+G$AX5043_FREQDEV13$0$0
+G$AX5043_WAKEUPXOEARLY$0$0
+G$AX5043_TIMER0$0$0
+G$AX5043_PINFUNCDCLK$0$0
+G$AX5043_MODCFGA$0$0
+G$AX5043_GPADC13VALUE1$0$0
+G$XWTEVTC$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_XCODECONFIG
+_XWTCNTA
+_AX5043_LPOSCSTATUS
+_AX5043_TMGTXSETTLE
+_AX5043_DRGAIN0
+_AX5043_TMGRXOFFSACQNB
+_AX5043_0xF34NB
+_AX5043_PKTLENOFFSETNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5043_0xF1CNB$0$0
+G$AX5043_RXDATARATE2NB$0$0
+G$AX5043_PLLLOOPNB$0$0
+G$AX5043_GPADCPERIODNB$0$0
+G$AX5043_FREQB2NB$0$0
+G$AX5043_FREQA3NB$0$0
+G$AX5043_FIFOTHRESH0NB$0$0
+G$AX5043_TIMER1$0$0
+G$AX5043_POWSTAT$0$0
+G$AX5043_MATCH0PAT0$0$0
+G$AX5043_FECSTATUS$0$0
+G$XWTEVTD$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_XWTCNTB
+_AX5043_DRGAIN1
+_AX5043_PKTADDRMASK0
+_AX5043_0xF26NB
+_AX5043_0xF35NB
+_AX5043_0xF44NB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5043_XTALAMPLNB$0$0
+G$AX5043_TMGRXSETTLENB$0$0
+G$AX5043_PKTCHUNKSIZENB$0$0
+G$AX5043_FREQB3NB$0$0
+G$AX5043_FIFOTHRESH1NB$0$0
+G$AX5043_TIMER2$0$0
+G$AX5043_PLLVCODIV$0$0
+G$AX5043_MAXDROFFSET0$0$0
+G$AX5043_MATCH1PAT0$0$0
+G$AX5043_MATCH0PAT1$0$0
+G$AX5043_FSKDEV0$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_XWTCNTR1
+_AX5043_TRKDATARATE0
+_AX5043_TRKRFFREQ0
+_AX5043_DRGAIN2
+_AX5043_PKTADDRMASK1
+_AX5043_PWRAMPNB
+_AX5043_0xF18NB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5043_PKTMAXLEN$0$0
+G$AX5043_AMPLITUDEGAIN0$0$0
+G$AX5043_MAXDROFFSET1$0$0
+G$AX5043_MATCH1PAT1$0$0
+G$AX5043_MATCH0PAT2$0$0
+G$AX5043_FSKDEV1$0$0
+G$XIC0STATUS$0$0
+G$XDIRA$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_XIC0CAPT0
+_AX5043_PINSTATE
+_AX5043_TRKDATARATE1
+_AX5043_TRKRFFREQ1
+_AX5043_DRGAIN3
+_AX5043_PKTADDRMASK2
+_AX5043_LPOSCPER0NB
+_IP_4
+G$AX5043_DRGAIN0NB$0$0
+G$AX5043_TMGTXSETTLENB$0$0
+G$AX5043_LPOSCSTATUSNB$0$0
+G$AX5043_AMPLITUDEGAIN1$0$0
+G$AX5043_MAXRFOFFSET0$0$0
+G$AX5043_MAXDROFFSET2$0$0
+G$AX5043_MATCH0PAT3$0$0
+G$AX5043_FSKDEV2$0$0
+G$AX5043_DACVALUE0$0$0
+G$XOC0COMP0$0$0
+G$XIC1STATUS$0$0
+G$XIC0MODE$0$0
+G$XDIRB$0$0
+G$XANALOGCOMP$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_XIC0CAPT1
+_XIC1CAPT0
+_AX5043_PKTSTOREFLAGS
+_AX5043_PLLLOOPBOOST
+_AX5043_PLLRNGCLK
+_AX5043_TRKDATARATE2
+_AX5043_TRKRFFREQ2
+_AX5043_PKTADDRMASK3
+_AX5043_IRQINVERSION0NB
+_AX5043_LPOSCPER1NB
+_AX5043_PLLVCOINB
+_AX5043_TMGRXBOOSTNB
+_EIP_0
+_IP_5
+G$AX5043_PKTADDRMASK0NB$0$0
+G$AX5043_DRGAIN1NB$0$0
+G$AX5043_AMPLITUDEGAIN2$0$0
+G$AX5043_MODCFGF$0$0
+G$AX5043_MAXRFOFFSET1$0$0
+G$AX5043_FIFOFREE0$0$0
+G$AX5043_DACVALUE1$0$0
+G$XOC1COMP0$0$0
+G$XOC0COMP1$0$0
+G$XIC1MODE$0$0
+G$XDIRC$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_XCLKSTAT
+_XIC1CAPT1
+_AX5043_PINFUNCPWRAMP
+_AX5043_AFSKCTRLNB
+_AX5043_IRQINVERSION1NB
+_AX5043_PINFUNCANTSELNB
+_AX5043_TMGRXCOARSEAGCNB
+_AX5043_AGCGAIN0NB
+_AX5043_PKTADDRCFGNB
+_AX5043_RXPARAMSETSNB
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5043_PKTADDRMASK1NB$0$0
+G$AX5043_DRGAIN2NB$0$0
+G$AX5043_TRKRFFREQ0NB$0$0
+G$AX5043_TRKDATARATE0NB$0$0
+G$AX5043_AMPLITUDEGAIN3$0$0
+G$AX5043_MAXRFOFFSET2$0$0
+G$AX5043_LPOSCCONFIG$0$0
+G$AX5043_FIFOFREE1$0$0
+G$XOC1COMP1$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_XPORTR
+_AX5043_AGCCOUNTER
+_AX5043_LPOSCKFILT0
+_AX5043_PLLVCOIR
+_AX5043_WAKEUPFREQ0
+_AX5043_TMGTXBOOSTNB
+_AX5043_AGCGAIN1NB
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5043_PKTADDRMASK2NB$0$0
+G$AX5043_DRGAIN3NB$0$0
+G$AX5043_TRKRFFREQ1NB$0$0
+G$AX5043_TRKDATARATE1NB$0$0
+G$AX5043_PINSTATENB$0$0
+G$XIC0CAPT$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5043_LPOSCKFILT1
+_AX5043_PINFUNCSYSCLK
+_AX5043_WAKEUPFREQ1
+_AX5043_BGNDRSSINB
+_AX5043_POWCTRL1NB
+_AX5043_AGCGAIN2NB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5043_PKTADDRMASK3NB$0$0
+G$AX5043_TRKRFFREQ2NB$0$0
+G$AX5043_TRKDATARATE2NB$0$0
+G$AX5043_PLLRNGCLKNB$0$0
+G$AX5043_PLLLOOPBOOSTNB$0$0
+G$AX5043_PKTSTOREFLAGSNB$0$0
+G$AX5043_TXPWRCOEFFA0$0$0
+G$XSPCLKSRC$0$0
+G$XIC1CAPT$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_XIP
+_XT0CNT0
+_AX5043_IFFREQ0
+_AX5043_PINFUNCDATA
+_AX5043_FREQDEV00
+_AX5043_DECIMATIONNB
+_AX5043_FIFOCOUNT0NB
+_AX5043_REFNB
+_AX5043_TMGRXAGCNB
+_AX5043_XTALSTATUSNB
+_AX5043_AGCGAIN3NB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5043_PINFUNCPWRAMPNB$0$0
+G$AX5043_PKTADDR0$0$0
+G$AX5043_TXPWRCOEFFB0$0$0
+G$AX5043_TXPWRCOEFFA1$0$0
+G$XOC0STATUS$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_XT0CNT1
+_XT1CNT0
+_AX5043_IFFREQ1
+_AX5043_PLLLOCKDET
+_AX5043_TRKFSKDEMOD0
+_AX5043_FREQDEV01
+_AX5043_FREQDEV10
+_AX5043_FIFOCOUNT1NB
+_AX5043_PWRMODENB
+_AX5043_XTALOSCNB
+_AX5043_PKTLENCFGNB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5043_WAKEUPFREQ0NB$0$0
+G$AX5043_PLLVCOIRNB$0$0
+G$AX5043_LPOSCKFILT0NB$0$0
+G$AX5043_AGCCOUNTERNB$0$0
+G$AX5043_PKTADDR1$0$0
+G$AX5043_TXPWRCOEFFC0$0$0
+G$AX5043_TXPWRCOEFFB1$0$0
+G$AX5043_BGNDRSSIGAIN$0$0
+G$XWTSTAT$0$0
+G$XOC1STATUS$0$0
+G$XOC0MODE$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_XRADIOSTAT0
+_XT1CNT1
+_XT2CNT0
+_XWTEVTA
+_AX5043_PLLRANGINGA
+_AX5043_TRKAFSKDEMOD0
+_AX5043_TRKFSKDEMOD1
+_AX5043_FREQDEV02
+_AX5043_FREQDEV11
+_AX5043_FREQA0NB
+_AX5043_LPOSCFREQ0NB
+_EIP_6
+G$AX5043_WAKEUPFREQ1NB$0$0
+G$AX5043_PINFUNCSYSCLKNB$0$0
+G$AX5043_LPOSCKFILT1NB$0$0
+G$AX5043_PKTADDR2$0$0
+G$AX5043_TXPWRCOEFFD0$0$0
+G$AX5043_TXPWRCOEFFC1$0$0
+G$AX5043_MODULATION$0$0
+G$AX5043_MATCH0LEN$0$0
+G$AX5043_FSKDMIN0$0$0
+G$AX5043_CRCINIT0$0$0
+G$XT0STATUS$0$0
+G$XOC1MODE$0$0
+G$XPINA$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_XRADIOSTAT1
+_XSPSHREG
+_XT2CNT1
+_XWTEVTB
+_AX5043_AMPLFILTER
+_AX5043_GPADC13VALUE0
+_AX5043_PLLRANGINGB
+_AX5043_RADIOSTATE
+_AX5043_TRKAFSKDEMOD1
+_AX5043_FREQDEV03
+_AX5043_FREQDEV12
+_AX5043_FIFOSTATNB
+_AX5043_FREQA1NB
+_AX5043_FREQB0NB
+_AX5043_LPOSCFREQ1NB
+_AX5043_RXDATARATE0NB
+_EIP_7
+G$AX5043_FREQDEV00NB$0$0
+G$AX5043_PINFUNCDATANB$0$0
+G$AX5043_IFFREQ0NB$0$0
+G$AX5043_PKTADDR3$0$0
+G$AX5043_WAKEUP0$0$0
+G$AX5043_TXPWRCOEFFE0$0$0
+G$AX5043_TXPWRCOEFFD1$0$0
+G$AX5043_MATCH1LEN$0$0
+G$AX5043_FSKDMIN1$0$0
+G$AX5043_CRCINIT1$0$0
+G$XU0STATUS$0$0
+G$XT1STATUS$0$0
+G$XT0MODE$0$0
+G$XT0CNT$0$0
+G$XOC0PIN$0$0
+G$XPINB$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_XWTEVTC
+_AX5043_GPADC13VALUE1
+_AX5043_MODCFGA
+_AX5043_PINFUNCDCLK
+_AX5043_TIMER0
+_AX5043_WAKEUPXOEARLY
+_AX5043_FREQDEV13
+_AX5043_RXPARAMCURSET
+_AX5043_FREQA2NB
+_AX5043_FREQB1NB
+_AX5043_RXDATARATE1NB
+_AX5043_0xF0CNB
+_XPAGE
+G$AX5043_FREQDEV10NB$0$0
+G$AX5043_FREQDEV01NB$0$0
+G$AX5043_TRKFSKDEMOD0NB$0$0
+G$AX5043_PLLLOCKDETNB$0$0
+G$AX5043_IFFREQ1NB$0$0
+G$AX5043_TIMEGAIN0$0$0
+G$AX5043_WAKEUPTIMER0$0$0
+G$AX5043_WAKEUP1$0$0
+G$AX5043_TXPWRCOEFFE1$0$0
+G$AX5043_FSKDMAX0$0$0
+G$AX5043_FIFODATA$0$0
+G$AX5043_DACCONFIG$0$0
+G$AX5043_CRCINIT2$0$0
+G$XWTIRQEN$0$0
+G$XU1STATUS$0$0
+G$XU0MODE$0$0
+G$XT2STATUS$0$0
+G$XT1MODE$0$0
+G$XT1CNT$0$0
+G$XOC1PIN$0$0
+G$XPINC$0$0
+G$XDPTR0$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_XWTEVTD
+_AX5043_FECSTATUS
+_AX5043_MATCH0PAT0
+_AX5043_POWSTAT
+_AX5043_TIMER1
+_AX5043_FIFOTHRESH0NB
+_AX5043_FREQA3NB
+_AX5043_FREQB2NB
+_AX5043_GPADCPERIODNB
+_AX5043_PLLLOOPNB
+_AX5043_RXDATARATE2NB
+_AX5043_0xF1CNB
+_RADIOACC
+_F0
+G$AX5043_FREQDEV11NB$0$0
+G$AX5043_FREQDEV02NB$0$0
+G$AX5043_TRKFSKDEMOD1NB$0$0
+G$AX5043_TRKAFSKDEMOD0NB$0$0
+G$AX5043_PLLRANGINGANB$0$0
+G$AX5043_TIMEGAIN1$0$0
+G$AX5043_WAKEUPTIMER1$0$0
+G$AX5043_PINFUNCIRQ$0$0
+G$AX5043_FSKDMAX1$0$0
+G$AX5043_CRCINIT3$0$0
+G$XU1MODE$0$0
+G$XT2MODE$0$0
+G$XT2CNT$0$0
+G$XRADIOSTAT$0$0
+G$XDPTR1$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5043_FSKDEV0
+_AX5043_MATCH0PAT1
+_AX5043_MATCH1PAT0
+_AX5043_MAXDROFFSET0
+_AX5043_PLLVCODIV
+_AX5043_TIMER2
+_AX5043_FIFOTHRESH1NB
+_AX5043_FREQB3NB
+_AX5043_PKTCHUNKSIZENB
+_AX5043_TMGRXSETTLENB
+_AX5043_XTALAMPLNB
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5043_FREQDEV12NB$0$0
+G$AX5043_FREQDEV03NB$0$0
+G$AX5043_TRKAFSKDEMOD1NB$0$0
+G$AX5043_RADIOSTATENB$0$0
+G$AX5043_PLLRANGINGBNB$0$0
+G$AX5043_GPADC13VALUE0NB$0$0
+G$AX5043_AMPLFILTERNB$0$0
+G$AX5043_TIMEGAIN2$0$0
+G$AX5043_PHASEGAIN0$0$0
+G$AX5043_SILICONREVISION$0$0
+G$AX5043_MODCFGP$0$0
+G$AX5043_BBTUNE$0$0
+G$AX5043_AFSKMARK0$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_XDIRA
+_XIC0STATUS
+_AX5043_FSKDEV1
+_AX5043_MATCH0PAT2
+_AX5043_MATCH1PAT1
+_AX5043_MAXDROFFSET1
+_AX5043_AMPLITUDEGAIN0
+_AX5043_PKTMAXLEN
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5043_RXPARAMCURSETNB$0$0
+G$AX5043_FREQDEV13NB$0$0
+G$AX5043_WAKEUPXOEARLYNB$0$0
+G$AX5043_TIMER0NB$0$0
+G$AX5043_PINFUNCDCLKNB$0$0
+G$AX5043_MODCFGANB$0$0
+G$AX5043_GPADC13VALUE1NB$0$0
+G$AX5043_TIMEGAIN3$0$0
+G$AX5043_PHASEGAIN1$0$0
+G$AX5043_RSSI$0$0
+G$AX5043_MATCH0MIN$0$0
+G$AX5043_AFSKSPACE0$0$0
+G$AX5043_AFSKMARK1$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_XANALOGCOMP
+_XDIRB
+_XIC0MODE
+_XIC1STATUS
+_XOC0COMP0
+_AX5043_DACVALUE0
+_AX5043_FSKDEV2
+_AX5043_MATCH0PAT3
+_AX5043_MAXDROFFSET2
+_AX5043_MAXRFOFFSET0
+_AX5043_AMPLITUDEGAIN1
+_AX5043_LPOSCSTATUSNB
+_AX5043_TMGTXSETTLENB
+_AX5043_DRGAIN0NB
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5043_TIMER1NB$0$0
+G$AX5043_POWSTATNB$0$0
+G$AX5043_MATCH0PAT0NB$0$0
+G$AX5043_FECSTATUSNB$0$0
+G$AX5043_PHASEGAIN2$0$0
+G$AX5043_FREQUENCYGAINA0$0$0
+G$AX5043_AGCTARGET0$0$0
+G$AX5043_MATCH1MIN$0$0
+G$AX5043_AFSKSPACE1$0$0
+G$XNVDATA0$0$0
+G$XDBGLNKSTAT$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_XDIRC
+_XIC1MODE
+_XOC0COMP1
+_XOC1COMP0
+_AX5043_DACVALUE1
+_AX5043_FIFOFREE0
+_AX5043_MAXRFOFFSET1
+_AX5043_MODCFGF
+_AX5043_AMPLITUDEGAIN2
+_AX5043_DRGAIN1NB
+_AX5043_PKTADDRMASK0NB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5043_TIMER2NB$0$0
+G$AX5043_PLLVCODIVNB$0$0
+G$AX5043_MAXDROFFSET0NB$0$0
+G$AX5043_MATCH1PAT0NB$0$0
+G$AX5043_MATCH0PAT1NB$0$0
+G$AX5043_FSKDEV0NB$0$0
+G$AX5043_PHASEGAIN3$0$0
+G$AX5043_FREQUENCYGAINB0$0$0
+G$AX5043_FREQUENCYGAINA1$0$0
+G$AX5043_AGCTARGET1$0$0
+G$AX5043_MATCH0MAX$0$0
+G$AX5043_DIVERSITY$0$0
+G$XNVDATA1$0$0
+G$XNVADDR0$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_XOC1COMP1
+_AX5043_FIFOFREE1
+_AX5043_LPOSCCONFIG
+_AX5043_MAXRFOFFSET2
+_AX5043_AMPLITUDEGAIN3
+_AX5043_TRKDATARATE0NB
+_AX5043_TRKRFFREQ0NB
+_AX5043_DRGAIN2NB
+_AX5043_PKTADDRMASK1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5043_PKTMAXLENNB$0$0
+G$AX5043_AMPLITUDEGAIN0NB$0$0
+G$AX5043_MAXDROFFSET1NB$0$0
+G$AX5043_MATCH1PAT1NB$0$0
+G$AX5043_MATCH0PAT2NB$0$0
+G$AX5043_FSKDEV1NB$0$0
+G$AX5043_FREQUENCYGAINC0$0$0
+G$AX5043_FREQUENCYGAINB1$0$0
+G$AX5043_FREQUENCYGAINA2$0$0
+G$AX5043_AGCTARGET2$0$0
+G$AX5043_AGCAHYST0$0$0
+G$AX5043_PLLCPI$0$0
+G$AX5043_MATCH1MAX$0$0
+G$AX5043_FRAMING$0$0
+G$XNVADDR1$0$0
+G$XPCON$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_XIC0CAPT
+_AX5043_PINSTATENB
+_AX5043_TRKDATARATE1NB
+_AX5043_TRKRFFREQ1NB
+_AX5043_DRGAIN3NB
+_AX5043_PKTADDRMASK2NB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5043_AMPLITUDEGAIN1NB$0$0
+G$AX5043_MAXRFOFFSET0NB$0$0
+G$AX5043_MAXDROFFSET2NB$0$0
+G$AX5043_MATCH0PAT3NB$0$0
+G$AX5043_FSKDEV2NB$0$0
+G$AX5043_DACVALUE0NB$0$0
+G$AX5043_FREQUENCYGAIND0$0$0
+G$AX5043_FREQUENCYGAINC1$0$0
+G$AX5043_FREQUENCYGAINB2$0$0
+G$AX5043_FREQUENCYGAINA3$0$0
+G$AX5043_AGCTARGET3$0$0
+G$AX5043_AGCMINMAX0$0$0
+G$AX5043_AGCAHYST1$0$0
+G$AX5043_RSSIABSTHR$0$0
+G$AX5043_IRQREQUEST0$0$0
+G$XOC0COMP$0$0
+G$XDIRR$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_XIC1CAPT
+_XSPCLKSRC
+_AX5043_TXPWRCOEFFA0
+_AX5043_PKTSTOREFLAGSNB
+_AX5043_PLLLOOPBOOSTNB
+_AX5043_PLLRNGCLKNB
+_AX5043_TRKDATARATE2NB
+_AX5043_TRKRFFREQ2NB
+_AX5043_PKTADDRMASK3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5043_AMPLITUDEGAIN2NB$0$0
+G$AX5043_MODCFGFNB$0$0
+G$AX5043_MAXRFOFFSET1NB$0$0
+G$AX5043_FIFOFREE0NB$0$0
+G$AX5043_DACVALUE1NB$0$0
+G$AX5043_FREQUENCYGAIND1$0$0
+G$AX5043_FREQUENCYGAINC2$0$0
+G$AX5043_FREQUENCYGAINB3$0$0
+G$AX5043_AGCMINMAX1$0$0
+G$AX5043_AGCAHYST2$0$0
+G$AX5043_TRKAMPLITUDE0$0$0
+G$AX5043_IRQREQUEST1$0$0
+G$AX5043_BBOFFSCAP$0$0
+G$XWDTRESET$0$0
+G$XOC1COMP$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_XOC0STATUS
+_AX5043_TXPWRCOEFFA1
+_AX5043_TXPWRCOEFFB0
+_AX5043_PKTADDR0
+_AX5043_PINFUNCPWRAMPNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5043_AMPLITUDEGAIN3NB$0$0
+G$AX5043_MAXRFOFFSET2NB$0$0
+G$AX5043_LPOSCCONFIGNB$0$0
+G$AX5043_FIFOFREE1NB$0$0
+G$AX5043_FREQUENCYGAIND2$0$0
+G$AX5043_FREQUENCYGAINC3$0$0
+G$AX5043_AGCMINMAX2$0$0
+G$AX5043_AGCAHYST3$0$0
+G$AX5043_TRKAMPLITUDE1$0$0
+G$AX5043_ENCODING$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_XOC0MODE
+_XOC1STATUS
+_XWTSTAT
+_AX5043_BGNDRSSIGAIN
+_AX5043_TXPWRCOEFFB1
+_AX5043_TXPWRCOEFFC0
+_AX5043_PKTADDR1
+_AX5043_AGCCOUNTERNB
+_AX5043_LPOSCKFILT0NB
+_AX5043_PLLVCOIRNB
+_AX5043_WAKEUPFREQ0NB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$AX5043_FREQUENCYGAIND3$0$0
+G$AX5043_AGCMINMAX3$0$0
+G$AX5043_TXRATE0$0$0
+G$AX5043_SCRATCH$0$0
+G$AX5043_PKTMISCFLAGS$0$0
+G$AX5043_IRQMASK0$0$0
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_XPINA
+_XOC1MODE
+_XT0STATUS
+_AX5043_CRCINIT0
+_AX5043_FSKDMIN0
+_AX5043_MATCH0LEN
+_AX5043_MODULATION
+_AX5043_TXPWRCOEFFC1
+_AX5043_TXPWRCOEFFD0
+_AX5043_PKTADDR2
+_AX5043_LPOSCKFILT1NB
+_AX5043_PINFUNCSYSCLKNB
+_AX5043_WAKEUPFREQ1NB
+_PINC_7
+G$AX5043_TXPWRCOEFFA0NB$0$0
+G$AX5043_TXRATE1$0$0
+G$AX5043_RADIOEVENTREQ0$0$0
+G$AX5043_POWSTICKYSTAT$0$0
+G$AX5043_IRQMASK1$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_XPINB
+_XOC0PIN
+_XT0CNT
+_XT0MODE
+_XT1STATUS
+_XU0STATUS
+_AX5043_CRCINIT1
+_AX5043_FSKDMIN1
+_AX5043_MATCH1LEN
+_AX5043_TXPWRCOEFFD1
+_AX5043_TXPWRCOEFFE0
+_AX5043_WAKEUP0
+_AX5043_PKTADDR3
+_AX5043_IFFREQ0NB
+_AX5043_PINFUNCDATANB
+_AX5043_FREQDEV00NB
+_WTCNTA0
+G$AX5043_PKTADDR0NB$0$0
+G$AX5043_TXPWRCOEFFB0NB$0$0
+G$AX5043_TXPWRCOEFFA1NB$0$0
+G$AX5043_TXRATE2$0$0
+G$AX5043_RADIOEVENTREQ1$0$0
+G$AX5043_BGNDRSSITHR$0$0
+G$XRADIOACC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_XDPTR0
+_XPINC
+_XOC1PIN
+_XT1CNT
+_XT1MODE
+_XT2STATUS
+_XU0MODE
+_XU1STATUS
+_XWTIRQEN
+_AX5043_CRCINIT2
+_AX5043_DACCONFIG
+_AX5043_FIFODATA
+_AX5043_FSKDMAX0
+_AX5043_TXPWRCOEFFE1
+_AX5043_WAKEUP1
+_AX5043_WAKEUPTIMER0
+_AX5043_TIMEGAIN0
+_AX5043_IFFREQ1NB
+_AX5043_PLLLOCKDETNB
+_AX5043_TRKFSKDEMOD0NB
+_AX5043_FREQDEV01NB
+_AX5043_FREQDEV10NB
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5043_PKTADDR1NB$0$0
+G$AX5043_TXPWRCOEFFC0NB$0$0
+G$AX5043_TXPWRCOEFFB1NB$0$0
+G$AX5043_BGNDRSSIGAINNB$0$0
+G$AX5043_TMGRXPREAMBLE1$0$0
+G$AX5043_PLLCPIBOOST$0$0
+G$AX5043_FECSYNC$0$0
+G$XT0PERIOD0$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_XDPTR1
+_XRADIOSTAT
+_XT2CNT
+_XT2MODE
+_XU1MODE
+_AX5043_CRCINIT3
+_AX5043_FSKDMAX1
+_AX5043_PINFUNCIRQ
+_AX5043_WAKEUPTIMER1
+_AX5043_TIMEGAIN1
+_AX5043_PLLRANGINGANB
+_AX5043_TRKAFSKDEMOD0NB
+_AX5043_TRKFSKDEMOD1NB
+_AX5043_FREQDEV02NB
+_AX5043_FREQDEV11NB
+_WTCNTB1
+G$AX5043_PKTADDR2NB$0$0
+G$AX5043_TXPWRCOEFFD0NB$0$0
+G$AX5043_TXPWRCOEFFC1NB$0$0
+G$AX5043_MODULATIONNB$0$0
+G$AX5043_MATCH0LENNB$0$0
+G$AX5043_FSKDMIN0NB$0$0
+G$AX5043_CRCINIT0NB$0$0
+G$AX5043_BBOFFSRES0$0$0
+G$AX5043_TMGRXPREAMBLE2$0$0
+G$AX5043_PKTACCEPTFLAGS$0$0
+G$XT1PERIOD0$0$0
+G$XT0PERIOD1$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5043_AFSKMARK0
+_AX5043_BBTUNE
+_AX5043_MODCFGP
+_AX5043_SILICONREVISION
+_AX5043_PHASEGAIN0
+_AX5043_TIMEGAIN2
+_AX5043_AMPLFILTERNB
+_AX5043_GPADC13VALUE0NB
+_AX5043_PLLRANGINGBNB
+_AX5043_RADIOSTATENB
+_AX5043_TRKAFSKDEMOD1NB
+_AX5043_FREQDEV03NB
+_AX5043_FREQDEV12NB
+_AC
+G$AX5043_PKTADDR3NB$0$0
+G$AX5043_WAKEUP0NB$0$0
+G$AX5043_TXPWRCOEFFE0NB$0$0
+G$AX5043_TXPWRCOEFFD1NB$0$0
+G$AX5043_MATCH1LENNB$0$0
+G$AX5043_FSKDMIN1NB$0$0
+G$AX5043_CRCINIT1NB$0$0
+G$AX5043_BBOFFSRES1$0$0
+G$AX5043_XTALCAP$0$0
+G$AX5043_TMGRXPREAMBLE3$0$0
+G$AX5043_RADIOEVENTMASK0$0$0
+G$XT2PERIOD0$0$0
+G$XT1PERIOD1$0$0
+G$XRADIODATA0$0$0
+G$XPINR$0$0
+G$XADCCH0CONFIG$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5043_AFSKMARK1
+_AX5043_AFSKSPACE0
+_AX5043_MATCH0MIN
+_AX5043_RSSI
+_AX5043_PHASEGAIN1
+_AX5043_TIMEGAIN3
+_AX5043_GPADC13VALUE1NB
+_AX5043_MODCFGANB
+_AX5043_PINFUNCDCLKNB
+_AX5043_TIMER0NB
+_AX5043_WAKEUPXOEARLYNB
+_AX5043_FREQDEV13NB
+_AX5043_RXPARAMCURSETNB
+_E2IE
+G$AX5043_TIMEGAIN0NB$0$0
+G$AX5043_WAKEUPTIMER0NB$0$0
+G$AX5043_WAKEUP1NB$0$0
+G$AX5043_TXPWRCOEFFE1NB$0$0
+G$AX5043_FSKDMAX0NB$0$0
+G$AX5043_FIFODATANB$0$0
+G$AX5043_DACCONFIGNB$0$0
+G$AX5043_CRCINIT2NB$0$0
+G$AX5043_BBOFFSRES2$0$0
+G$AX5043_0xF00$0$0
+G$AX5043_RADIOEVENTMASK1$0$0
+G$AX5043_POWIRQMASK$0$0
+G$AX5043_LPOSCREF0$0$0
+G$AX5043_FEC$0$0
+G$XU0CTRL$0$0
+G$XT2PERIOD1$0$0
+G$XRADIODATA1$0$0
+G$XRADIOADDR0$0$0
+G$XCLKCON$0$0
+G$XADCCH1CONFIG$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_XDBGLNKSTAT
+_XNVDATA0
+_AX5043_AFSKSPACE1
+_AX5043_MATCH1MIN
+_AX5043_AGCTARGET0
+_AX5043_FREQUENCYGAINA0
+_AX5043_PHASEGAIN2
+_AX5043_FECSTATUSNB
+_AX5043_MATCH0PAT0NB
+_AX5043_POWSTATNB
+_AX5043_TIMER1NB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5043_TIMEGAIN1NB$0$0
+G$AX5043_WAKEUPTIMER1NB$0$0
+G$AX5043_PINFUNCIRQNB$0$0
+G$AX5043_FSKDMAX1NB$0$0
+G$AX5043_CRCINIT3NB$0$0
+G$AX5043_FREQUENCYLEAK$0$0
+G$AX5043_BBOFFSRES3$0$0
+G$AX5043_TRKFREQ0$0$0
+G$AX5043_LPOSCREF1$0$0
+G$XU1CTRL$0$0
+G$XRADIODATA2$0$0
+G$XRADIOADDR1$0$0
+G$XADCCH2CONFIG$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_XNVADDR0
+_XNVDATA1
+_AX5043_DIVERSITY
+_AX5043_MATCH0MAX
+_AX5043_AGCTARGET1
+_AX5043_FREQUENCYGAINA1
+_AX5043_FREQUENCYGAINB0
+_AX5043_PHASEGAIN3
+_AX5043_FSKDEV0NB
+_AX5043_MATCH0PAT1NB
+_AX5043_MATCH1PAT0NB
+_AX5043_MAXDROFFSET0NB
+_AX5043_PLLVCODIVNB
+_AX5043_TIMER2NB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5043_TIMEGAIN2NB$0$0
+G$AX5043_PHASEGAIN0NB$0$0
+G$AX5043_SILICONREVISIONNB$0$0
+G$AX5043_MODCFGPNB$0$0
+G$AX5043_BBTUNENB$0$0
+G$AX5043_AFSKMARK0NB$0$0
+G$AX5043_FOURFSK0$0$0
+G$AX5043_TRKFREQ1$0$0
+G$AX5043_RSSIREFERENCE$0$0
+G$XWTCFGA$0$0
+G$XRADIODATA3$0$0
+G$XADCCH3CONFIG$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_XPCON
+_XNVADDR1
+_AX5043_FRAMING
+_AX5043_MATCH1MAX
+_AX5043_PLLCPI
+_AX5043_AGCAHYST0
+_AX5043_AGCTARGET2
+_AX5043_FREQUENCYGAINA2
+_AX5043_FREQUENCYGAINB1
+_AX5043_FREQUENCYGAINC0
+_AX5043_FSKDEV1NB
+_AX5043_MATCH0PAT2NB
+_AX5043_MATCH1PAT1NB
+_AX5043_MAXDROFFSET1NB
+_AX5043_AMPLITUDEGAIN0NB
+_AX5043_PKTMAXLENNB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5043_TIMEGAIN3NB$0$0
+G$AX5043_PHASEGAIN1NB$0$0
+G$AX5043_RSSINB$0$0
+G$AX5043_MATCH0MINNB$0$0
+G$AX5043_AFSKSPACE0NB$0$0
+G$AX5043_AFSKMARK1NB$0$0
+G$AX5043_FOURFSK1$0$0
+G$AX5043_0xF30$0$0
+G$AX5043_0xF21$0$0
+G$XWTCFGB$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_XDIRR
+_XOC0COMP
+_AX5043_IRQREQUEST0
+_AX5043_RSSIABSTHR
+_AX5043_AGCAHYST1
+_AX5043_AGCMINMAX0
+_AX5043_AGCTARGET3
+_AX5043_FREQUENCYGAINA3
+_AX5043_FREQUENCYGAINB2
+_AX5043_FREQUENCYGAINC1
+_AX5043_FREQUENCYGAIND0
+_AX5043_DACVALUE0NB
+_AX5043_FSKDEV2NB
+_AX5043_MATCH0PAT3NB
+_AX5043_MAXDROFFSET2NB
+_AX5043_MAXRFOFFSET0NB
+_AX5043_AMPLITUDEGAIN1NB
+_RADIODATA
+_T2PERIOD
+G$AX5043_PHASEGAIN2NB$0$0
+G$AX5043_FREQUENCYGAINA0NB$0$0
+G$AX5043_AGCTARGET0NB$0$0
+G$AX5043_MATCH1MINNB$0$0
+G$AX5043_AFSKSPACE1NB$0$0
+G$AX5043_FOURFSK2$0$0
+G$AX5043_0xF31$0$0
+G$AX5043_0xF22$0$0
+G$AX5043_TRKPHASE0$0$0
+G$XU0SHREG$0$0
+G$XNVDATA$0$0
+G$XADCCONV$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_XOC1COMP
+_XWDTRESET
+_AX5043_BBOFFSCAP
+_AX5043_IRQREQUEST1
+_AX5043_TRKAMPLITUDE0
+_AX5043_AGCAHYST2
+_AX5043_AGCMINMAX1
+_AX5043_FREQUENCYGAINB3
+_AX5043_FREQUENCYGAINC2
+_AX5043_FREQUENCYGAIND1
+_AX5043_DACVALUE1NB
+_AX5043_FIFOFREE0NB
+_AX5043_MAXRFOFFSET1NB
+_AX5043_MODCFGFNB
+_AX5043_AMPLITUDEGAIN2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5043_PHASEGAIN3NB$0$0
+G$AX5043_FREQUENCYGAINB0NB$0$0
+G$AX5043_FREQUENCYGAINA1NB$0$0
+G$AX5043_AGCTARGET1NB$0$0
+G$AX5043_MATCH0MAXNB$0$0
+G$AX5043_DIVERSITYNB$0$0
+G$AX5043_FOURFSK3$0$0
+G$AX5043_0xF32$0$0
+G$AX5043_0xF23$0$0
+G$AX5043_TRKPHASE1$0$0
+G$AX5043_TMGRXRSSI$0$0
+G$XWDTCFG$0$0
+G$XU1SHREG$0$0
+G$XNVADDR$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5043_ENCODING
+_AX5043_TRKAMPLITUDE1
+_AX5043_AGCAHYST3
+_AX5043_AGCMINMAX2
+_AX5043_FREQUENCYGAINC3
+_AX5043_FREQUENCYGAIND2
+_AX5043_FIFOFREE1NB
+_AX5043_LPOSCCONFIGNB
+_AX5043_MAXRFOFFSET2NB
+_AX5043_AMPLITUDEGAIN3NB
+_WTEVTA0
+G$AX5043_FREQUENCYGAINC0NB$0$0
+G$AX5043_FREQUENCYGAINB1NB$0$0
+G$AX5043_FREQUENCYGAINA2NB$0$0
+G$AX5043_AGCTARGET2NB$0$0
+G$AX5043_AGCAHYST0NB$0$0
+G$AX5043_PLLCPINB$0$0
+G$AX5043_MATCH1MAXNB$0$0
+G$AX5043_FRAMINGNB$0$0
+G$AX5043_0xF33$0$0
+G$AX5043_GPADCCTRL$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_AX5043_IRQMASK0
+_AX5043_PKTMISCFLAGS
+_AX5043_SCRATCH
+_AX5043_TXRATE0
+_AX5043_AGCMINMAX3
+_AX5043_FREQUENCYGAIND3
+_WTEVTA1
+_WTEVTB0
+G$AX5043_FREQUENCYGAIND0NB$0$0
+G$AX5043_FREQUENCYGAINC1NB$0$0
+G$AX5043_FREQUENCYGAINB2NB$0$0
+G$AX5043_FREQUENCYGAINA3NB$0$0
+G$AX5043_AGCTARGET3NB$0$0
+G$AX5043_AGCMINMAX0NB$0$0
+G$AX5043_AGCAHYST1NB$0$0
+G$AX5043_RSSIABSTHRNB$0$0
+G$AX5043_IRQREQUEST0NB$0$0
+G$AX5043_PKTLENOFFSET$0$0
+G$AX5043_0xF34$0$0
+G$AX5043_TMGRXOFFSACQ$0$0
+G$XWTCNTA0$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5043_IRQMASK1
+_AX5043_POWSTICKYSTAT
+_AX5043_RADIOEVENTREQ0
+_AX5043_TXRATE1
+_AX5043_TXPWRCOEFFA0NB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5043_FREQUENCYGAIND1NB$0$0
+G$AX5043_FREQUENCYGAINC2NB$0$0
+G$AX5043_FREQUENCYGAINB3NB$0$0
+G$AX5043_AGCMINMAX1NB$0$0
+G$AX5043_AGCAHYST2NB$0$0
+G$AX5043_TRKAMPLITUDE0NB$0$0
+G$AX5043_IRQREQUEST1NB$0$0
+G$AX5043_BBOFFSCAPNB$0$0
+G$AX5043_0xF44$0$0
+G$AX5043_0xF35$0$0
+G$AX5043_0xF26$0$0
+G$XWTCNTB0$0$0
+G$XWTCNTA1$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_XRADIOACC
+_AX5043_BGNDRSSITHR
+_AX5043_RADIOEVENTREQ1
+_AX5043_TXRATE2
+_AX5043_TXPWRCOEFFA1NB
+_AX5043_TXPWRCOEFFB0NB
+_AX5043_PKTADDR0NB
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5043_FREQUENCYGAIND2NB$0$0
+G$AX5043_FREQUENCYGAINC3NB$0$0
+G$AX5043_AGCMINMAX2NB$0$0
+G$AX5043_AGCAHYST3NB$0$0
+G$AX5043_TRKAMPLITUDE1NB$0$0
+G$AX5043_ENCODINGNB$0$0
+G$AX5043_0xF18$0$0
+G$AX5043_PWRAMP$0$0
+G$XWTCNTB1$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_XT0PERIOD0
+_AX5043_FECSYNC
+_AX5043_PLLCPIBOOST
+_AX5043_TMGRXPREAMBLE1
+_AX5043_BGNDRSSIGAINNB
+_AX5043_TXPWRCOEFFB1NB
+_AX5043_TXPWRCOEFFC0NB
+_AX5043_PKTADDR1NB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5043_FREQUENCYGAIND3NB$0$0
+G$AX5043_AGCMINMAX3NB$0$0
+G$AX5043_TXRATE0NB$0$0
+G$AX5043_SCRATCHNB$0$0
+G$AX5043_PKTMISCFLAGSNB$0$0
+G$AX5043_IRQMASK0NB$0$0
+G$AX5043_LPOSCPER0$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_XT0PERIOD1
+_XT1PERIOD0
+_AX5043_PKTACCEPTFLAGS
+_AX5043_TMGRXPREAMBLE2
+_AX5043_BBOFFSRES0
+_AX5043_CRCINIT0NB
+_AX5043_FSKDMIN0NB
+_AX5043_MATCH0LENNB
+_AX5043_MODULATIONNB
+_AX5043_TXPWRCOEFFC1NB
+_AX5043_TXPWRCOEFFD0NB
+_AX5043_PKTADDR2NB
+_E2IP
+_P
+G$AX5043_TXRATE1NB$0$0
+G$AX5043_RADIOEVENTREQ0NB$0$0
+G$AX5043_POWSTICKYSTATNB$0$0
+G$AX5043_IRQMASK1NB$0$0
+G$AX5043_TMGRXBOOST$0$0
+G$AX5043_PLLVCOI$0$0
+G$AX5043_LPOSCPER1$0$0
+G$AX5043_IRQINVERSION0$0$0
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_XADCCH0CONFIG
+_XPINR
+_XRADIODATA0
+_XT1PERIOD1
+_XT2PERIOD0
+_AX5043_RADIOEVENTMASK0
+_AX5043_TMGRXPREAMBLE3
+_AX5043_XTALCAP
+_AX5043_BBOFFSRES1
+_AX5043_CRCINIT1NB
+_AX5043_FSKDMIN1NB
+_AX5043_MATCH1LENNB
+_AX5043_TXPWRCOEFFD1NB
+_AX5043_TXPWRCOEFFE0NB
+_AX5043_WAKEUP0NB
+_AX5043_PKTADDR3NB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5043_TXRATE2NB$0$0
+G$AX5043_RADIOEVENTREQ1NB$0$0
+G$AX5043_BGNDRSSITHRNB$0$0
+G$AX5043_RXPARAMSETS$0$0
+G$AX5043_PKTADDRCFG$0$0
+G$AX5043_AGCGAIN0$0$0
+G$AX5043_TMGRXCOARSEAGC$0$0
+G$AX5043_PINFUNCANTSEL$0$0
+G$AX5043_IRQINVERSION1$0$0
+G$AX5043_AFSKCTRL$0$0
+G$XT0CLKSRC$0$0
+G$XPORTA$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_XADCCH1CONFIG
+_XCLKCON
+_XRADIOADDR0
+_XRADIODATA1
+_XT2PERIOD1
+_XU0CTRL
+_AX5043_FEC
+_AX5043_LPOSCREF0
+_AX5043_POWIRQMASK
+_AX5043_RADIOEVENTMASK1
+_AX5043_0xF00
+_AX5043_BBOFFSRES2
+_AX5043_CRCINIT2NB
+_AX5043_DACCONFIGNB
+_AX5043_FIFODATANB
+_AX5043_FSKDMAX0NB
+_AX5043_TXPWRCOEFFE1NB
+_AX5043_WAKEUP1NB
+_AX5043_WAKEUPTIMER0NB
+_AX5043_TIMEGAIN0NB
+_WTCNTB
+_B_1
+G$AX5043_TMGRXPREAMBLE1NB$0$0
+G$AX5043_PLLCPIBOOSTNB$0$0
+G$AX5043_FECSYNCNB$0$0
+G$AX5043_AGCGAIN1$0$0
+G$AX5043_TMGTXBOOST$0$0
+G$XT1CLKSRC$0$0
+G$XT0PERIOD$0$0
+G$XSPSTATUS$0$0
+G$XPORTB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_XADCCH2CONFIG
+_XRADIOADDR1
+_XRADIODATA2
+_XU1CTRL
+_AX5043_LPOSCREF1
+_AX5043_TRKFREQ0
+_AX5043_BBOFFSRES3
+_AX5043_FREQUENCYLEAK
+_AX5043_CRCINIT3NB
+_AX5043_FSKDMAX1NB
+_AX5043_PINFUNCIRQNB
+_AX5043_WAKEUPTIMER1NB
+_AX5043_TIMEGAIN1NB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5043_BBOFFSRES0NB$0$0
+G$AX5043_TMGRXPREAMBLE2NB$0$0
+G$AX5043_PKTACCEPTFLAGSNB$0$0
+G$AX5043_AGCGAIN2$0$0
+G$AX5043_POWCTRL1$0$0
+G$AX5043_BGNDRSSI$0$0
+G$XT2CLKSRC$0$0
+G$XT1PERIOD$0$0
+G$XSPMODE$0$0
+G$XNVSTATUS$0$0
+G$XPORTC$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_XADCCH3CONFIG
+_XRADIODATA3
+_XWTCFGA
+_AX5043_RSSIREFERENCE
+_AX5043_TRKFREQ1
+_AX5043_FOURFSK0
+_AX5043_AFSKMARK0NB
+_AX5043_BBTUNENB
+_AX5043_MODCFGPNB
+_AX5043_SILICONREVISIONNB
+_AX5043_PHASEGAIN0NB
+_AX5043_TIMEGAIN2NB
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5043_BBOFFSRES1NB$0$0
+G$AX5043_XTALCAPNB$0$0
+G$AX5043_TMGRXPREAMBLE3NB$0$0
+G$AX5043_RADIOEVENTMASK0NB$0$0
+G$AX5043_AGCGAIN3$0$0
+G$AX5043_XTALSTATUS$0$0
+G$AX5043_TMGRXAGC$0$0
+G$AX5043_REF$0$0
+G$AX5043_FIFOCOUNT0$0$0
+G$AX5043_DECIMATION$0$0
+G$XT2PERIOD$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_XWTCFGB
+_AX5043_0xF21
+_AX5043_0xF30
+_AX5043_FOURFSK1
+_AX5043_AFSKMARK1NB
+_AX5043_AFSKSPACE0NB
+_AX5043_MATCH0MINNB
+_AX5043_RSSINB
+_AX5043_PHASEGAIN1NB
+_AX5043_TIMEGAIN3NB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5043_BBOFFSRES2NB$0$0
+G$AX5043_0xF00NB$0$0
+G$AX5043_RADIOEVENTMASK1NB$0$0
+G$AX5043_POWIRQMASKNB$0$0
+G$AX5043_LPOSCREF0NB$0$0
+G$AX5043_FECNB$0$0
+G$AX5043_PKTLENCFG$0$0
+G$AX5043_XTALOSC$0$0
+G$AX5043_PWRMODE$0$0
+G$AX5043_FIFOCOUNT1$0$0
+G$XADCCLKSRC$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_XADCCONV
+_XNVDATA
+_XU0SHREG
+_AX5043_TRKPHASE0
+_AX5043_0xF22
+_AX5043_0xF31
+_AX5043_FOURFSK2
+_AX5043_AFSKSPACE1NB
+_AX5043_MATCH1MINNB
+_AX5043_AGCTARGET0NB
+_AX5043_FREQUENCYGAINA0NB
+_AX5043_PHASEGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5043_FREQUENCYLEAKNB$0$0
+G$AX5043_BBOFFSRES3NB$0$0
+G$AX5043_TRKFREQ0NB$0$0
+G$AX5043_LPOSCREF1NB$0$0
+G$AX5043_LPOSCFREQ0$0$0
+G$AX5043_FREQA0$0$0
+G$XWTEVTA0$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_XNVADDR
+_XU1SHREG
+_XWDTCFG
+_AX5043_TMGRXRSSI
+_AX5043_TRKPHASE1
+_AX5043_0xF23
+_AX5043_0xF32
+_AX5043_FOURFSK3
+_AX5043_DIVERSITYNB
+_AX5043_MATCH0MAXNB
+_AX5043_AGCTARGET1NB
+_AX5043_FREQUENCYGAINA1NB
+_AX5043_FREQUENCYGAINB0NB
+_AX5043_PHASEGAIN3NB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5043_FOURFSK0NB$0$0
+G$AX5043_TRKFREQ1NB$0$0
+G$AX5043_RSSIREFERENCENB$0$0
+G$AX5043_RXDATARATE0$0$0
+G$AX5043_LPOSCFREQ1$0$0
+G$AX5043_FREQB0$0$0
+G$AX5043_FREQA1$0$0
+G$AX5043_FIFOSTAT$0$0
+G$XWTEVTB0$0$0
+G$XWTEVTA1$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5043_GPADCCTRL
+_AX5043_0xF33
+_AX5043_FRAMINGNB
+_AX5043_MATCH1MAXNB
+_AX5043_PLLCPINB
+_AX5043_AGCAHYST0NB
+_AX5043_AGCTARGET2NB
+_AX5043_FREQUENCYGAINA2NB
+_AX5043_FREQUENCYGAINB1NB
+_AX5043_FREQUENCYGAINC0NB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5043_FOURFSK1NB$0$0
+G$AX5043_0xF30NB$0$0
+G$AX5043_0xF21NB$0$0
+G$AX5043_0xF0C$0$0
+G$AX5043_RXDATARATE1$0$0
+G$AX5043_FREQB1$0$0
+G$AX5043_FREQA2$0$0
+G$XWTEVTC0$0$0
+G$XWTEVTB1$0$0
+G$XNVKEY$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_XWTCNTA0
+_AX5043_TMGRXOFFSACQ
+_AX5043_0xF34
+_AX5043_PKTLENOFFSET
+_AX5043_IRQREQUEST0NB
+_AX5043_RSSIABSTHRNB
+_AX5043_AGCAHYST1NB
+_AX5043_AGCMINMAX0NB
+_AX5043_AGCTARGET3NB
+_AX5043_FREQUENCYGAINA3NB
+_AX5043_FREQUENCYGAINB2NB
+_AX5043_FREQUENCYGAINC1NB
+_AX5043_FREQUENCYGAIND0NB
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5043_FOURFSK2NB$0$0
+G$AX5043_0xF31NB$0$0
+G$AX5043_0xF22NB$0$0
+G$AX5043_TRKPHASE0NB$0$0
+G$AX5043_0xF1C$0$0
+G$AX5043_RXDATARATE2$0$0
+G$AX5043_PLLLOOP$0$0
+G$AX5043_GPADCPERIOD$0$0
+G$AX5043_FREQB2$0$0
+G$AX5043_FREQA3$0$0
+G$AX5043_FIFOTHRESH0$0$0
+G$XWTEVTD0$0$0
+G$XWTEVTC1$0$0
+G$XIE$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_XWTCNTA1
+_XWTCNTB0
+_AX5043_0xF26
+_AX5043_0xF35
+_AX5043_0xF44
+_AX5043_BBOFFSCAPNB
+_AX5043_IRQREQUEST1NB
+_AX5043_TRKAMPLITUDE0NB
+_AX5043_AGCAHYST2NB
+_AX5043_AGCMINMAX1NB
+_AX5043_FREQUENCYGAINB3NB
+_AX5043_FREQUENCYGAINC2NB
+_AX5043_FREQUENCYGAIND1NB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$AX5043_FOURFSK3NB$0$0
+G$AX5043_0xF32NB$0$0
+G$AX5043_0xF23NB$0$0
+G$AX5043_TRKPHASE1NB$0$0
+G$AX5043_TMGRXRSSINB$0$0
+G$AX5043_XTALAMPL$0$0
+G$AX5043_TMGRXSETTLE$0$0
+G$AX5043_PKTCHUNKSIZE$0$0
+G$AX5043_FREQB3$0$0
+G$AX5043_FIFOTHRESH1$0$0
+G$XWTEVTD1$0$0
+G$XDBGLNKBUF$0$0
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_XWTCNTB1
+_AX5043_PWRAMP
+_AX5043_0xF18
+_AX5043_ENCODINGNB
+_AX5043_TRKAMPLITUDE1NB
+_AX5043_AGCAHYST3NB
+_AX5043_AGCMINMAX2NB
+_AX5043_FREQUENCYGAINC3NB
+_AX5043_FREQUENCYGAIND2NB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5043_0xF33NB$0$0
+G$AX5043_GPADCCTRLNB$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5043_LPOSCPER0
+_AX5043_IRQMASK0NB
+_AX5043_PKTMISCFLAGSNB
+_AX5043_SCRATCHNB
+_AX5043_TXRATE0NB
+_AX5043_AGCMINMAX3NB
+_AX5043_FREQUENCYGAIND3NB
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5043_PKTLENOFFSETNB$0$0
+G$AX5043_0xF34NB$0$0
+G$AX5043_TMGRXOFFSACQNB$0$0
+G$AX5043_DRGAIN0$0$0
+G$AX5043_TMGTXSETTLE$0$0
+G$AX5043_LPOSCSTATUS$0$0
+G$XWTCNTA$0$0
+G$XCODECONFIG$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_AX5043_IRQINVERSION0
+_AX5043_LPOSCPER1
+_AX5043_PLLVCOI
+_AX5043_TMGRXBOOST
+_AX5043_IRQMASK1NB
+_AX5043_POWSTICKYSTATNB
+_AX5043_RADIOEVENTREQ0NB
+_AX5043_TXRATE1NB
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5043_0xF44NB$0$0
+G$AX5043_0xF35NB$0$0
+G$AX5043_0xF26NB$0$0
+G$AX5043_PKTADDRMASK0$0$0
+G$AX5043_DRGAIN1$0$0
+G$XWTCNTB$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_XPORTA
+_XT0CLKSRC
+_AX5043_AFSKCTRL
+_AX5043_IRQINVERSION1
+_AX5043_PINFUNCANTSEL
+_AX5043_TMGRXCOARSEAGC
+_AX5043_AGCGAIN0
+_AX5043_PKTADDRCFG
+_AX5043_RXPARAMSETS
+_AX5043_BGNDRSSITHRNB
+_AX5043_RADIOEVENTREQ1NB
+_AX5043_TXRATE2NB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5043_0xF18NB$0$0
+G$AX5043_PWRAMPNB$0$0
+G$AX5043_PKTADDRMASK1$0$0
+G$AX5043_DRGAIN2$0$0
+G$AX5043_TRKRFFREQ0$0$0
+G$AX5043_TRKDATARATE0$0$0
+G$XWTCNTR1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_XPORTB
+_XSPSTATUS
+_XT0PERIOD
+_XT1CLKSRC
+_AX5043_TMGTXBOOST
+_AX5043_AGCGAIN1
+_AX5043_FECSYNCNB
+_AX5043_PLLCPIBOOSTNB
+_AX5043_TMGRXPREAMBLE1NB
+_E2IP_0
+_IE_2
+G$AX5043_LPOSCPER0NB$0$0
+G$AX5043_PKTADDRMASK2$0$0
+G$AX5043_DRGAIN3$0$0
+G$AX5043_TRKRFFREQ1$0$0
+G$AX5043_TRKDATARATE1$0$0
+G$AX5043_PINSTATE$0$0
+G$XIC0CAPT0$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_XPORTC
+_XNVSTATUS
+_XSPMODE
+_XT1PERIOD
+_XT2CLKSRC
+_AX5043_BGNDRSSI
+_AX5043_POWCTRL1
+_AX5043_AGCGAIN2
+_AX5043_PKTACCEPTFLAGSNB
+_AX5043_TMGRXPREAMBLE2NB
+_AX5043_BBOFFSRES0NB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5043wrfifo$3300
+A$ax5043wrfifo$3310
+A$ax5043wrfifo$3301
+A$ax5043wrfifo$3320
+A$ax5043wrfifo$3311
+A$ax5043wrfifo$3302
+A$ax5043wrfifo$3330
+A$ax5043wrfifo$3321
+A$ax5043wrfifo$3312
+A$ax5043wrfifo$3303
+A$ax5043wrfifo$3331
+A$ax5043wrfifo$3313
+A$ax5043wrfifo$3304
+A$ax5043wrfifo$3323
+A$ax5043wrfifo$3324
+A$ax5043wrfifo$3315
+A$ax5043wrfifo$3306
+A$ax5043wrfifo$3325
+A$ax5043wrfifo$3316
+A$ax5043wrfifo$3307
+A$ax5043wrfifo$3280
+A$ax5043wrfifo$3326
+A$ax5043wrfifo$3317
+A$ax5043wrfifo$3308
+A$ax5043wrfifo$3281
+A$ax5043wrfifo$3272
+A$ax5043wrfifo$3327
+A$ax5043wrfifo$3318
+A$ax5043wrfifo$3309
+A$ax5043wrfifo$3282
+A$ax5043wrfifo$3273
+A$ax5043wrfifo$3328
+A$ax5043wrfifo$3319
+A$ax5043wrfifo$3292
+A$ax5043wrfifo$3274
+A$ax5043wrfifo$3329
+A$ax5043wrfifo$3293
+A$ax5043wrfifo$3284
+A$ax5043wrfifo$3275
+A$ax5043wrfifo$3294
+A$ax5043wrfifo$3285
+A$ax5043wrfifo$3276
+A$ax5043wrfifo$3295
+A$ax5043wrfifo$3286
+A$ax5043wrfifo$3277
+A$ax5043wrfifo$3296
+A$ax5043wrfifo$3287
+A$ax5043wrfifo$3278
+A$ax5043wrfifo$3279
+A$ax5043wrfifo$3298
+A$ax5043wrfifo$3289
+A$ax5043wrfifo$3299
+C$ax5043wrfifo.c$10$0$0
+C$ax5043wrfifo.c$75$1$66
+C$ax5043wrfifo.c$76$1$66
+G$ax5043_writefifo$0$0
+_ax5043_writefifo
+XG$ax5043_writefifo$0$0
+
+
+
+ax5043regs 5136518
+.__.ABS.
+
+
+
+ax5051comminit 5137556
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
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+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
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+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
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+_LPOSCREF
+_XTALOSC
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+_PORTC_7
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+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
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+_AX5051_CICDECLO
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+_FRCOSCKFILT
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+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
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+_RADIODATA1
+_T2PERIOD1
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+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
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+_PINC_2
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+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
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+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
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+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
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+_INTCHGA
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+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
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+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
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+_AX5051_CICDECHINB
+_NVADDR
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+_WDTCFG
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+.__.ABS.
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+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
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+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
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+_AX5051_PLLRANGINGNB
+_WTCNTA0
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+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
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+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
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+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
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+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
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+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
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+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
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+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
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+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
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+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
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+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
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+G$PORTA_1$0$0
+G$RS1$0$0
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+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
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+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
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+G$ADCCH0VAL1$0$0
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+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
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+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
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+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
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+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+C$ax5051commslpexit.c$24$1$66
+C$ax5051commslpexit.c$15$1$66
+C$ax5051commslpexit.c$25$1$66
+C$ax5051commslpexit.c$16$1$66
+C$ax5051commslpexit.c$8$0$0
+G$ax5051_commsleepexit$0$0
+_ax5051_commsleepexit
+XG$ax5051_commsleepexit$0$0
+A$ax5051commslpexit$1650
+A$ax5051commslpexit$1661
+A$ax5051commslpexit$1680
+A$ax5051commslpexit$1653
+A$ax5051commslpexit$1672
+A$ax5051commslpexit$1654
+A$ax5051commslpexit$1673
+A$ax5051commslpexit$1664
+A$ax5051commslpexit$1655
+A$ax5051commslpexit$1683
+A$ax5051commslpexit$1674
+A$ax5051commslpexit$1665
+A$ax5051commslpexit$1656
+A$ax5051commslpexit$1647
+A$ax5051commslpexit$1675
+A$ax5051commslpexit$1666
+A$ax5051commslpexit$1657
+A$ax5051commslpexit$1676
+A$ax5051commslpexit$1667
+A$ax5051commslpexit$1658
+A$ax5051commslpexit$1677
+A$ax5051commslpexit$1668
+A$ax5051commslpexit$1669
+C$ax5051commslpexit.c$10$1$66
+C$ax5051commslpexit.c$11$1$66
+C$ax5051commslpexit.c$12$1$66
+C$ax5051commslpexit.c$13$1$66
+
+
+
+ax5051reset 5236589
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
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+
+
+
+ax5051deepsleep 5294763
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+_ANALOGCOMP
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+_FRCOSCKFILT0
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+_AX5051_DATARATEHINB
+_DPTR0
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+_AX5051_IRQMASKNB
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+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
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+_LPOSCFREQ
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+_AX5051_XTALOSCNB
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+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
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+_PALTA
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+_AX5051_FREQA0NB
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+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
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+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
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+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
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+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
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+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
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+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
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+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+
+
+
+ax5051rclkena 5342701
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+G$ax5051_rclk_enable$0$0
+_ax5051_rclk_enable
+A$ax5051rclkena$1700
+A$ax5051rclkena$1701
+A$ax5051rclkena$1705
+A$ax5051rclkena$1660
+A$ax5051rclkena$1651
+A$ax5051rclkena$1706
+A$ax5051rclkena$1670
+A$ax5051rclkena$1661
+A$ax5051rclkena$1680
+A$ax5051rclkena$1662
+A$ax5051rclkena$1653
+A$ax5051rclkena$1690
+A$ax5051rclkena$1709
+A$ax5051rclkena$1691
+A$ax5051rclkena$1673
+A$ax5051rclkena$1692
+A$ax5051rclkena$1683
+A$ax5051rclkena$1674
+A$ax5051rclkena$1665
+A$ax5051rclkena$1656
+A$ax5051rclkena$1693
+A$ax5051rclkena$1675
+A$ax5051rclkena$1666
+A$ax5051rclkena$1648
+XG$ax5051_rclk_enable$0$0
+A$ax5051rclkena$1676
+A$ax5051rclkena$1667
+A$ax5051rclkena$1686
+A$ax5051rclkena$1677
+A$ax5051rclkena$1687
+A$ax5051rclkena$1678
+A$ax5051rclkena$1697
+A$ax5051rclkena$1679
+C$ax5051rclkena.c$10$1$64
+A$ax5051rclkena$1698
+C$ax5051rclkena.c$11$1$64
+A$ax5051rclkena$1699
+C$ax5051rclkena.c$12$1$64
+C$ax5051rclkena.c$13$1$64
+C$ax5051rclkena.c$14$1$64
+C$ax5051rclkena.c$15$1$64
+C$ax5051rclkena.c$16$1$64
+C$ax5051rclkena.c$17$1$64
+C$ax5051rclkena.c$18$1$64
+C$ax5051rclkena.c$19$1$64
+C$ax5051rclkena.c$8$1$64
+C$ax5051rclkena.c$9$1$64
+C$ax5051rclkena.c$5$0$0
+
+
+
+ax5051rclkdis 5393001
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+_ax5051_rclk_disable
+C$ax5051rclkdis.c$8$1$64
+C$ax5051rclkdis.c$9$1$64
+C$ax5051rclkdis.c$5$0$0
+XG$ax5051_rclk_disable$0$0
+A$ax5051rclkdis$1650
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+A$ax5051rclkdis$1688
+C$ax5051rclkdis.c$10$1$64
+C$ax5051rclkdis.c$11$1$64
+C$ax5051rclkdis.c$12$1$64
+C$ax5051rclkdis.c$13$1$64
+C$ax5051rclkdis.c$14$1$64
+C$ax5051rclkdis.c$15$1$64
+G$ax5051_rclk_disable$0$0
+C$ax5051rclkdis.c$16$1$64
+
+
+
+ax5051rdfifo 5442662
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5051rdfifo$1699
+C$ax5051rdfifo.c$10$0$0
+C$ax5051rdfifo.c$74$1$66
+C$ax5051rdfifo.c$75$1$66
+G$ax5051_readfifo$0$0
+_ax5051_readfifo
+XG$ax5051_readfifo$0$0
+A$ax5051rdfifo$1700
+A$ax5051rdfifo$1701
+A$ax5051rdfifo$1650
+A$ax5051rdfifo$1660
+A$ax5051rdfifo$1651
+A$ax5051rdfifo$1670
+A$ax5051rdfifo$1652
+A$ax5051rdfifo$1643
+A$ax5051rdfifo$1680
+A$ax5051rdfifo$1671
+A$ax5051rdfifo$1653
+A$ax5051rdfifo$1644
+A$ax5051rdfifo$1690
+A$ax5051rdfifo$1681
+A$ax5051rdfifo$1672
+A$ax5051rdfifo$1663
+A$ax5051rdfifo$1645
+A$ax5051rdfifo$1691
+A$ax5051rdfifo$1682
+A$ax5051rdfifo$1673
+A$ax5051rdfifo$1664
+A$ax5051rdfifo$1655
+A$ax5051rdfifo$1646
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+A$ax5051rdfifo$1683
+A$ax5051rdfifo$1674
+A$ax5051rdfifo$1665
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+A$ax5051rdfifo$1647
+A$ax5051rdfifo$1684
+A$ax5051rdfifo$1675
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+A$ax5051rdfifo$1648
+A$ax5051rdfifo$1694
+A$ax5051rdfifo$1667
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+A$ax5051rdfifo$1649
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+A$ax5051rdfifo$1677
+A$ax5051rdfifo$1696
+A$ax5051rdfifo$1687
+A$ax5051rdfifo$1678
+A$ax5051rdfifo$1669
+A$ax5051rdfifo$1697
+A$ax5051rdfifo$1688
+A$ax5051rdfifo$1679
+A$ax5051rdfifo$1698
+A$ax5051rdfifo$1689
+
+
+
+ax5051wrfifo 5493312
+G$AX5051_PINCFG3$0$0
+G$LPXOSCGM$0$0
+G$IP_5$0$0
+G$EIP_0$0$0
+_MISCCTRL
+_AX5051_FREQ0
+_AX5051_PWRMODE
+_AX5051_XTALOSC
+_AX5051_FECNB
+_AX5051_IFFREQHINB
+_ANALOGCOMP
+_DIRB
+_IC0MODE
+_IC1STATUS
+_OC0COMP0
+_E2IP_2
+_IE_4
+G$AX5051_AGCCOUNTER$0$0
+G$XTALREADY$0$0
+G$FRCOSCFREQ$0$0
+G$IP_6$0$0
+G$EIP_1$0$0
+G$NVDATA0$0$0
+G$DBGLNKSTAT$0$0
+_AX5051_FREQ1
+_AX5051_FREQA0
+_DIRC
+_IC1MODE
+_OC0COMP1
+_OC1COMP0
+_E2IP_3
+_EIE_0
+_IE_5
+G$AX5051_CICDECHI$0$0
+G$LPOSCFREQ$0$0
+G$IP_7$0$0
+G$EIP_2$0$0
+G$NVDATA1$0$0
+G$NVADDR0$0$0
+_XTALAMPL
+_AX5051_FREQ2
+_AX5051_FREQA1
+_AX5051_PHASEGAINNB
+_SP
+_OC1COMP1
+_E2IP_4
+_EIE_1
+_IE_6
+G$AX5051_REFNB$0$0
+G$AX5051_FIFOCOUNT$0$0
+G$AX5051_FECMEM$0$0
+G$EIP_3$0$0
+G$NVADDR1$0$0
+G$PCON$0$0
+_AX5051_DATARATELO
+_AX5051_FREQ3
+_AX5051_FREQA2
+_AX5051_FREQUENCYGAINNB
+_AX5051_TXBITRATEMIDNB
+_IC0CAPT
+_E2IP_5
+_EIE_2
+_IE_7
+G$AX5051_XTALOSCNB$0$0
+G$AX5051_PWRMODENB$0$0
+G$AX5051_FREQ0NB$0$0
+G$AX5051_PLLRANGING$0$0
+G$EIP_4$0$0
+G$OC0COMP$0$0
+G$DIRR$0$0
+_AX5051_FREQA3
+_AX5051_PLLLOOP
+_AX5051_AGCTARGETNB
+_AX5051_TXBITRATELONB
+_IC1CAPT
+_SPCLKSRC
+_E2IP_6
+_EIE_3
+_OV
+G$AX5051_FREQA0NB$0$0
+G$AX5051_FREQ1NB$0$0
+G$PALTA$0$0
+G$EIP_5$0$0
+G$WDTRESET$0$0
+G$OC1COMP$0$0
+_ADCCH0VAL
+_AX5051_MODULATORMISC
+_OC0STATUS
+_E2IP_7
+_EIE_4
+G$AX5051_FREQA1NB$0$0
+G$AX5051_FREQ2NB$0$0
+G$AX5051_TRKFREQHI$0$0
+G$PALTB$0$0
+G$ANALOGA$0$0
+G$EIP_6$0$0
+_ADCCH1VAL
+_FRCOSCPER
+_DPS
+_OC0MODE
+_OC1STATUS
+_WTSTAT
+_EIE_5
+G$AX5051_FREQA2NB$0$0
+G$AX5051_FREQ3NB$0$0
+G$AX5051_DATARATELONB$0$0
+G$AX5051_TRKAMPLITUDELO$0$0
+G$AX5051_AGCDECAY$0$0
+G$PALTC$0$0
+G$ADCTUNE0$0$0
+G$EIP_7$0$0
+_ADCCH2VAL
+_LPOSCPER
+_AX5051_TXPWR
+_AX5051_IRQREQUESTNB
+_PINA
+_OC1MODE
+_T0STATUS
+_EIE_6
+_IP_0
+G$AX5051_PLLLOOPNB$0$0
+G$AX5051_FREQA3NB$0$0
+G$AX5051_FIFOTHRESH$0$0
+G$AX5051_FECSTATUS$0$0
+G$FRCOSCCTRL$0$0
+G$ADCTUNE1$0$0
+G$XPAGE$0$0
+_ADCCH3VAL
+_RADIOMUX
+_AX5051_RXMISCNB
+_PINB
+_OC0PIN
+_T0CNT
+_T0MODE
+_T1STATUS
+_U0STATUS
+_EIE_7
+_IP_1
+G$AX5051_MODULATORMISCNB$0$0
+G$AX5051_TRKPHASEHI$0$0
+G$AX5051_FSKDEV0$0$0
+G$FRCOSCCONFIG$0$0
+G$ADCTUNE2$0$0
+G$F0$0$0
+G$RADIOACC$0$0
+_FRCOSCKFILT0
+_RADIOFDATAADDR
+_AX5051_TRKAMPLITUDEHI
+_AX5051_DATARATEHINB
+_DPTR0
+_PINC
+_OC1PIN
+_T1CNT
+_T1MODE
+_T2STATUS
+_U0MODE
+_U1STATUS
+_WTIRQEN
+_IP_2
+G$AX5051_VREG$0$0
+G$AX5051_IFMODE$0$0
+G$AX5051_FSKDEV1$0$0
+G$AX5051_ADCMISC$0$0
+G$LPOSCCONFIG$0$0
+G$PINA_0$0$0
+G$F1$0$0
+G$T0PERIOD0$0$0
+_FRCOSCKFILT1
+_LPOSCKFILT0
+_AX5051_PINCFG1
+_AX5051_IFFREQLONB
+_AX5051_IRQMASKNB
+_DPTR1
+_RADIOSTAT
+_T2CNT
+_T2MODE
+_U1MODE
+_IP_3
+G$AX5051_TXPWRNB$0$0
+G$AX5051_FSKDEV2$0$0
+G$SCRATCH0$0$0
+G$DMA0CONFIG$0$0
+G$PINB_0$0$0
+G$PINA_1$0$0
+G$T1PERIOD0$0$0
+G$T0PERIOD1$0$0
+_LPOSCKFILT1
+_AX5051_IRQINVERSION
+_AX5051_PINCFG2
+_AX5051_PLLRNGCLK
+_AX5051_PLLVCOINB
+_IP_4
+G$AX5051_CICDECLO$0$0
+G$SCRATCH1$0$0
+G$DMA1CONFIG$0$0
+G$PINC_0$0$0
+G$PINB_1$0$0
+G$PINA_2$0$0
+G$T2PERIOD0$0$0
+G$T1PERIOD1$0$0
+G$RADIODATA0$0$0
+G$PINR$0$0
+G$ADCCH0CONFIG$0$0
+_LPXOSCGM
+_AX5051_PINCFG3
+_EIP_0
+_IP_5
+G$AX5051_TRKAMPLITUDEHINB$0$0
+G$AX5051_FIFOCONTROL2$0$0
+G$SCRATCH2$0$0
+G$PINCHGA$0$0
+G$FRCOSCKFILT$0$0
+G$PINC_1$0$0
+G$PINB_2$0$0
+G$PINA_3$0$0
+G$U0CTRL$0$0
+G$T2PERIOD1$0$0
+G$RADIODATA1$0$0
+G$RADIOADDR0$0$0
+G$CLKCON$0$0
+G$ADCCH1CONFIG$0$0
+G$PSW$0$0
+_FRCOSCFREQ
+_XTALREADY
+_AX5051_AGCCOUNTER
+_DBGLNKSTAT
+_NVDATA0
+_EIP_1
+_IP_6
+G$AX5051_PINCFG1NB$0$0
+G$AX5051_TXDSPMODE$0$0
+G$AX5051_TIMINGGAINHI$0$0
+G$SCRATCH3$0$0
+G$LPOSCKFILT$0$0
+G$PINCHGB$0$0
+G$PINC_2$0$0
+G$PINB_3$0$0
+G$PINA_4$0$0
+G$U1CTRL$0$0
+G$RADIODATA2$0$0
+G$RADIOADDR1$0$0
+G$ADCCH2CONFIG$0$0
+_LPOSCFREQ
+_AX5051_CICDECHI
+_NVADDR0
+_NVDATA1
+_EIP_2
+_IP_7
+G$AX5051_PLLRNGCLKNB$0$0
+G$AX5051_PINCFG2NB$0$0
+G$AX5051_IRQINVERSIONNB$0$0
+G$RADIOFSTATADDR0$0$0
+G$PINCHGC$0$0
+G$PINC_3$0$0
+G$PINB_4$0$0
+G$PINA_5$0$0
+G$WTCFGA$0$0
+G$RADIODATA3$0$0
+G$ADCCH3CONFIG$0$0
+_AX5051_FECMEM
+_AX5051_FIFOCOUNT
+_AX5051_REFNB
+_PCON
+_NVADDR1
+_EIP_3
+G$AX5051_PINCFG3NB$0$0
+G$AX5051_TRKFREQLO$0$0
+G$RADIOFSTATADDR1$0$0
+G$PINC_4$0$0
+G$PINB_5$0$0
+G$PINA_6$0$0
+G$WTCFGB$0$0
+_AX5051_PLLRANGING
+_AX5051_FREQ0NB
+_AX5051_PWRMODENB
+_AX5051_XTALOSCNB
+_DIRR
+_OC0COMP
+_EIP_4
+G$AX5051_AGCCOUNTERNB$0$0
+G$SILICONREV$0$0
+G$INTCHGA$0$0
+G$PINC_5$0$0
+G$PINB_6$0$0
+G$PINA_7$0$0
+G$U0SHREG$0$0
+G$NVDATA$0$0
+G$ADCCONV$0$0
+_PALTA
+_AX5051_FREQ1NB
+_AX5051_FREQA0NB
+_OC1COMP
+_WDTRESET
+_EIP_5
+G$AX5051_CICDECHINB$0$0
+G$AX5051_MODULATION$0$0
+G$AX5051_CRCINIT0$0$0
+G$INTCHGB$0$0
+G$PINC_6$0$0
+G$PINB_7$0$0
+G$WDTCFG$0$0
+G$U1SHREG$0$0
+G$NVADDR$0$0
+_ANALOGA
+_PALTB
+_AX5051_TRKFREQHI
+_AX5051_FREQ2NB
+_AX5051_FREQA1NB
+_EIP_6
+G$AX5051_FIFOCOUNTNB$0$0
+G$AX5051_FECMEMNB$0$0
+G$AX5051_TRKPHASELO$0$0
+G$AX5051_CRCINIT1$0$0
+G$OSCCALIB$0$0
+G$INTCHGC$0$0
+G$PINC_7$0$0
+_ADCTUNE0
+_PALTC
+_AX5051_AGCDECAY
+_AX5051_TRKAMPLITUDELO
+_AX5051_DATARATELONB
+_AX5051_FREQ3NB
+_AX5051_FREQA2NB
+_EIP_7
+G$AX5051_PLLRANGINGNB$0$0
+G$AX5051_FIFODATA$0$0
+G$AX5051_CRCINIT2$0$0
+G$WTCNTA0$0$0
+_ADCTUNE1
+_FRCOSCCTRL
+_AX5051_FECSTATUS
+_AX5051_FIFOTHRESH
+_AX5051_FREQA3NB
+_AX5051_PLLLOOPNB
+_XPAGE
+G$AX5051_CRCINIT3$0$0
+G$WTCNTB0$0$0
+G$WTCNTA1$0$0
+G$B$0$0
+_ADCTUNE2
+_FRCOSCCONFIG
+_AX5051_FSKDEV0
+_AX5051_TRKPHASEHI
+_AX5051_MODULATORMISCNB
+_RADIOACC
+_F0
+G$AX5051_TRKFREQHINB$0$0
+G$AX5051_SILICONREVISION$0$0
+G$WTCNTB1$0$0
+_LPOSCCONFIG
+_AX5051_ADCMISC
+_AX5051_FSKDEV1
+_AX5051_IFMODE
+_AX5051_VREG
+_T0PERIOD0
+_F1
+_PINA_0
+G$AX5051_TRKAMPLITUDELONB$0$0
+G$AX5051_AGCDECAYNB$0$0
+G$AC$0$0
+_DMA0CONFIG
+_SCRATCH0
+_AX5051_FSKDEV2
+_AX5051_TXPWRNB
+_T0PERIOD1
+_T1PERIOD0
+_PINA_1
+_PINB_0
+G$AX5051_FIFOTHRESHNB$0$0
+G$AX5051_FECSTATUSNB$0$0
+G$AX5051_TIMINGGAINLO$0$0
+G$E2IE$0$0
+_DMA1CONFIG
+_SCRATCH1
+_AX5051_CICDECLO
+_ADCCH0CONFIG
+_PINR
+_RADIODATA0
+_T1PERIOD1
+_T2PERIOD0
+_PINA_2
+_PINB_1
+_PINC_0
+G$AX5051_TRKPHASEHINB$0$0
+G$AX5051_FSKDEV0NB$0$0
+G$AX5051_FREQUENCYGAIN2$0$0
+G$AX5051_AGCATTACK$0$0
+G$EA$0$0
+G$T0CLKSRC$0$0
+G$PORTA$0$0
+_FRCOSCKFILT
+_PINCHGA
+_SCRATCH2
+_AX5051_FIFOCONTROL2
+_AX5051_TRKAMPLITUDEHINB
+_PSW
+_ADCCH1CONFIG
+_CLKCON
+_RADIOADDR0
+_RADIODATA1
+_T2PERIOD1
+_U0CTRL
+_PINA_3
+_PINB_2
+_PINC_1
+G$AX5051_VREGNB$0$0
+G$AX5051_IFMODENB$0$0
+G$AX5051_FSKDEV1NB$0$0
+G$AX5051_ADCMISCNB$0$0
+G$AX5051_RFMISC$0$0
+G$AX5051_FRAMING$0$0
+G$AX5051_AMPLITUDEGAIN$0$0
+G$T1CLKSRC$0$0
+G$T0PERIOD$0$0
+G$SPSTATUS$0$0
+G$PORTB$0$0
+G$ACC$0$0
+_PINCHGB
+_LPOSCKFILT
+_SCRATCH3
+_AX5051_TIMINGGAINHI
+_AX5051_TXDSPMODE
+_AX5051_PINCFG1NB
+_ADCCH2CONFIG
+_RADIOADDR1
+_RADIODATA2
+_U1CTRL
+_PINA_4
+_PINB_3
+_PINC_2
+G$AX5051_FSKDEV2NB$0$0
+G$AX5051_FIFOCONTROL$0$0
+G$T2CLKSRC$0$0
+G$T1PERIOD$0$0
+G$SPMODE$0$0
+G$NVSTATUS$0$0
+G$PORTC$0$0
+_PINCHGC
+_RADIOFSTATADDR0
+_AX5051_IRQINVERSIONNB
+_AX5051_PINCFG2NB
+_AX5051_PLLRNGCLKNB
+_ADCCH3CONFIG
+_RADIODATA3
+_WTCFGA
+_PINA_5
+_PINB_4
+_PINC_3
+G$AX5051_CICDECLONB$0$0
+G$OSCFORCERUN$0$0
+G$T2PERIOD$0$0
+G$RADIODATA$0$0
+_RADIOFSTATADDR1
+_AX5051_TRKFREQLO
+_AX5051_PINCFG3NB
+_WTCFGB
+_PINA_6
+_PINB_5
+_PINC_4
+G$AX5051_FIFOCONTROL2NB$0$0
+G$AX5051_ENCODING$0$0
+G$RADIOADDR$0$0
+G$ADCCLKSRC$0$0
+_INTCHGA
+_SILICONREV
+_AX5051_AGCCOUNTERNB
+_ADCCONV
+_NVDATA
+_U0SHREG
+_PINA_7
+_PINB_6
+_PINC_5
+G$AX5051_TXDSPMODENB$0$0
+G$AX5051_TIMINGGAINHINB$0$0
+G$AX5051_TXBITRATEHI$0$0
+G$AX5051_SCRATCH$0$0
+G$PINSEL$0$0
+G$WTEVTA0$0$0
+_INTCHGB
+_AX5051_CRCINIT0
+_AX5051_MODULATION
+_AX5051_CICDECHINB
+_NVADDR
+_U1SHREG
+_WDTCFG
+_PINB_7
+_PINC_6
+.__.ABS.
+G$RADIOFSTATADDR$0$0
+G$WTEVTB0$0$0
+G$WTEVTA1$0$0
+_INTCHGC
+_OSCCALIB
+_AX5051_CRCINIT1
+_AX5051_TRKPHASELO
+_AX5051_FECMEMNB
+_AX5051_FIFOCOUNTNB
+_PINC_7
+G$AX5051_TRKFREQLONB$0$0
+G$FRCOSCREF0$0$0
+G$DMA0ADDR0$0$0
+G$WTEVTC0$0$0
+G$WTEVTB1$0$0
+G$NVKEY$0$0
+G$DPH1$0$0
+_AX5051_CRCINIT2
+_AX5051_FIFODATA
+_AX5051_PLLRANGINGNB
+_WTCNTA0
+G$AX5051_FECSYNC$0$0
+G$LPOSCREF0$0$0
+G$FRCOSCREF1$0$0
+G$DMA1ADDR0$0$0
+G$DMA0ADDR1$0$0
+G$WTEVTD0$0$0
+G$WTEVTC1$0$0
+G$IE$0$0
+_AX5051_CRCINIT3
+_B
+_WTCNTA1
+_WTCNTB0
+G$AX5051_MODULATIONNB$0$0
+G$AX5051_CRCINIT0NB$0$0
+G$AX5051_DSPMODE$0$0
+G$LPOSCREF1$0$0
+G$DMA1ADDR1$0$0
+G$WTEVTD1$0$0
+G$DBGLNKBUF$0$0
+_AX5051_SILICONREVISION
+_AX5051_TRKFREQHINB
+_WTCNTB1
+G$AX5051_TRKPHASELONB$0$0
+G$AX5051_CRCINIT1NB$0$0
+G$AX5051_XTALCAP$0$0
+G$AX5051_CICSHIFT$0$0
+G$P$0$0
+G$E2IP$0$0
+_AX5051_AGCDECAYNB
+_AX5051_TRKAMPLITUDELONB
+_AC
+G$AX5051_FIFODATANB$0$0
+G$AX5051_CRCINIT2NB$0$0
+G$AX5051_IFFREQHI$0$0
+G$AX5051_FEC$0$0
+G$B_0$0$0
+G$WTCNTA$0$0
+G$CODECONFIG$0$0
+G$DPL1$0$0
+_AX5051_TIMINGGAINLO
+_AX5051_FECSTATUSNB
+_AX5051_FIFOTHRESHNB
+_E2IE
+G$AX5051_CRCINIT3NB$0$0
+G$B_1$0$0
+G$WTCNTB$0$0
+_AX5051_AGCATTACK
+_AX5051_FREQUENCYGAIN2
+_AX5051_FSKDEV0NB
+_AX5051_TRKPHASEHINB
+_PORTA
+_T0CLKSRC
+_EA
+G$AX5051_SILICONREVISIONNB$0$0
+G$AX5051_PHASEGAIN$0$0
+G$B_2$0$0
+G$WTCNTR1$0$0
+G$EIE$0$0
+_AX5051_AMPLITUDEGAIN
+_AX5051_FRAMING
+_AX5051_RFMISC
+_AX5051_ADCMISCNB
+_AX5051_FSKDEV1NB
+_AX5051_IFMODENB
+_AX5051_VREGNB
+_ACC
+_PORTB
+_SPSTATUS
+_T0PERIOD
+_T1CLKSRC
+G$AX5051_TXBITRATEMID$0$0
+G$AX5051_FREQUENCYGAIN$0$0
+G$E2IE_0$0$0
+G$B_3$0$0
+G$IC0CAPT0$0$0
+G$_XPAGE$0$0
+_AX5051_FIFOCONTROL
+_AX5051_FSKDEV2NB
+_PORTC
+_NVSTATUS
+_SPMODE
+_T1PERIOD
+_T2CLKSRC
+G$AX5051_TIMINGGAINLONB$0$0
+G$AX5051_TXBITRATELO$0$0
+G$AX5051_AGCTARGET$0$0
+G$PORTA_0$0$0
+G$RS0$0$0
+G$E2IE_1$0$0
+G$B_4$0$0
+G$IC1CAPT0$0$0
+G$IC0CAPT1$0$0
+_OSCFORCERUN
+_AX5051_CICDECLONB
+_RADIODATA
+_T2PERIOD
+G$AX5051_FREQUENCYGAIN2NB$0$0
+G$AX5051_AGCATTACKNB$0$0
+G$GPIOENABLE$0$0
+G$ADCCH0VAL0$0$0
+G$PORTB_0$0$0
+G$PORTA_1$0$0
+G$RS1$0$0
+G$E2IE_2$0$0
+G$B_5$0$0
+G$ACC_0$0$0
+G$IC1CAPT1$0$0
+G$CLKSTAT$0$0
+_AX5051_ENCODING
+_AX5051_FIFOCONTROL2NB
+_ADCCLKSRC
+_RADIOADDR
+G$AX5051_RFMISCNB$0$0
+G$AX5051_FRAMINGNB$0$0
+G$AX5051_AMPLITUDEGAINNB$0$0
+G$FRCOSCPER0$0$0
+G$ADCCH1VAL0$0$0
+G$ADCCH0VAL1$0$0
+G$PORTC_0$0$0
+G$PORTB_1$0$0
+G$PORTA_2$0$0
+G$E2IE_3$0$0
+G$B_6$0$0
+G$ACC_1$0$0
+G$PORTR$0$0
+_PINSEL
+_AX5051_SCRATCH
+_AX5051_TXBITRATEHI
+_AX5051_TIMINGGAINHINB
+_AX5051_TXDSPMODENB
+_WTEVTA0
+G$AX5051_FIFOCONTROLNB$0$0
+G$AX5051_IRQREQUEST$0$0
+G$LPOSCPER0$0$0
+G$FRCOSCPER1$0$0
+G$ADCCH2VAL0$0$0
+G$ADCCH1VAL1$0$0
+G$PORTC_1$0$0
+G$PORTB_2$0$0
+G$PORTA_3$0$0
+G$E2IE_4$0$0
+G$B_7$0$0
+G$ACC_2$0$0
+_RADIOFSTATADDR
+_WTEVTA1
+_WTEVTB0
+G$AX5051_RXMISC$0$0
+G$LPOSCPER1$0$0
+G$ADCCH3VAL0$0$0
+G$ADCCH2VAL1$0$0
+G$PORTC_2$0$0
+G$PORTB_3$0$0
+G$PORTA_4$0$0
+G$E2IE_5$0$0
+G$ACC_3$0$0
+G$T0CNT0$0$0
+G$IP$0$0
+_DMA0ADDR0
+_FRCOSCREF0
+_AX5051_TRKFREQLONB
+_DPH1
+_NVKEY
+_WTEVTB1
+_WTEVTC0
+G$AX5051_ENCODINGNB$0$0
+G$AX5051_DATARATEHI$0$0
+G$RADIOFDATAADDR0$0$0
+G$OSCRUN$0$0
+G$OSCREADY$0$0
+G$ADCCH3VAL1$0$0
+G$PORTC_3$0$0
+G$PORTB_4$0$0
+G$PORTA_5$0$0
+G$E2IE_6$0$0
+G$ACC_4$0$0
+G$T1CNT0$0$0
+G$T0CNT1$0$0
+_DMA0ADDR1
+_DMA1ADDR0
+_FRCOSCREF1
+_LPOSCREF0
+_AX5051_FECSYNC
+_IE
+_WTEVTC1
+_WTEVTD0
+G$AX5051_TXBITRATEHINB$0$0
+G$AX5051_SCRATCHNB$0$0
+G$AX5051_IRQMASK$0$0
+G$AX5051_IFFREQLO$0$0
+G$RADIOFDATAADDR1$0$0
+G$PORTC_4$0$0
+G$PORTB_5$0$0
+G$PORTA_6$0$0
+G$E2IE_7$0$0
+G$ACC_5$0$0
+G$WTEVTA$0$0
+G$T2CNT0$0$0
+G$T1CNT1$0$0
+G$RADIOSTAT0$0$0
+_DMA1ADDR1
+_LPOSCREF1
+_AX5051_DSPMODE
+_AX5051_CRCINIT0NB
+_AX5051_MODULATIONNB
+_DBGLNKBUF
+_WTEVTD1
+G$AX5051_PLLVCOI$0$0
+G$PORTC_5$0$0
+G$PORTB_6$0$0
+G$PORTA_7$0$0
+G$CY$0$0
+G$ACC_6$0$0
+G$WTEVTB$0$0
+G$T2CNT1$0$0
+G$SPSHREG$0$0
+G$RADIOSTAT1$0$0
+G$DPH$0$0
+_AX5051_CICSHIFT
+_AX5051_XTALCAP
+_AX5051_CRCINIT1NB
+_AX5051_TRKPHASELONB
+_E2IP
+_P
+G$EXTIRQ$0$0
+G$FRCOSCREF$0$0
+G$DMA0ADDR$0$0
+G$PORTC_6$0$0
+G$PORTB_7$0$0
+G$IE_0$0$0
+G$ACC_7$0$0
+G$WTEVTC$0$0
+_AX5051_FEC
+_AX5051_IFFREQHI
+_AX5051_CRCINIT2NB
+_AX5051_FIFODATANB
+_DPL1
+_CODECONFIG
+_WTCNTA
+_B_0
+G$AX5051_FECSYNCNB$0$0
+G$XTALOSC$0$0
+G$LPOSCREF$0$0
+G$FRCOSCFREQ0$0$0
+G$DMA1ADDR$0$0
+G$PORTC_7$0$0
+G$IE_1$0$0
+G$WTEVTD$0$0
+G$EIP$0$0
+_AX5051_CRCINIT3NB
+_WTCNTB
+_B_1
+G$AX5051_DSPMODENB$0$0
+G$LPOSCFREQ0$0$0
+G$FRCOSCFREQ1$0$0
+G$IE_2$0$0
+G$E2IP_0$0$0
+_AX5051_PHASEGAIN
+_AX5051_SILICONREVISIONNB
+_EIE
+_WTCNTR1
+_B_2
+G$AX5051_XTALCAPNB$0$0
+G$AX5051_CICSHIFTNB$0$0
+G$AX5051_REF$0$0
+G$LPOSCFREQ1$0$0
+G$PALTRADIO$0$0
+G$IE_3$0$0
+G$E2IP_1$0$0
+G$IC0STATUS$0$0
+G$DIRA$0$0
+G$DPL$0$0
+_AX5051_FREQUENCYGAIN
+_AX5051_TXBITRATEMID
+__XPAGE
+_IC0CAPT0
+_B_3
+_E2IE_0
+G$AX5051_IFFREQHINB$0$0
+G$AX5051_FECNB$0$0
+G$AX5051_XTALOSC$0$0
+G$AX5051_PWRMODE$0$0
+G$AX5051_FREQ0$0$0
+G$MISCCTRL$0$0
+G$IE_4$0$0
+G$E2IP_2$0$0
+G$OC0COMP0$0$0
+G$IC1STATUS$0$0
+G$IC0MODE$0$0
+G$DIRB$0$0
+G$ANALOGCOMP$0$0
+_AX5051_AGCTARGET
+_AX5051_TXBITRATELO
+_AX5051_TIMINGGAINLONB
+_IC0CAPT1
+_IC1CAPT0
+_B_4
+_E2IE_1
+_RS0
+_PORTA_0
+G$AX5051_FREQA0$0$0
+G$AX5051_FREQ1$0$0
+G$IE_5$0$0
+G$EIE_0$0$0
+G$E2IP_3$0$0
+G$OC1COMP0$0$0
+G$OC0COMP1$0$0
+G$IC1MODE$0$0
+G$DIRC$0$0
+_ADCCH0VAL0
+_GPIOENABLE
+_AX5051_AGCATTACKNB
+_AX5051_FREQUENCYGAIN2NB
+_CLKSTAT
+_IC1CAPT1
+_ACC_0
+_B_5
+_E2IE_2
+_RS1
+_PORTA_1
+_PORTB_0
+G$AX5051_PHASEGAINNB$0$0
+G$AX5051_FREQA1$0$0
+G$AX5051_FREQ2$0$0
+G$XTALAMPL$0$0
+G$IE_6$0$0
+G$EIE_1$0$0
+G$E2IP_4$0$0
+G$OC1COMP1$0$0
+G$SP$0$0
+_ADCCH0VAL1
+_ADCCH1VAL0
+_FRCOSCPER0
+_AX5051_AMPLITUDEGAINNB
+_AX5051_FRAMINGNB
+_AX5051_RFMISCNB
+_PORTR
+_ACC_1
+_B_6
+_E2IE_3
+_PORTA_2
+_PORTB_1
+_PORTC_0
+G$AX5051_TXBITRATEMIDNB$0$0
+G$AX5051_FREQUENCYGAINNB$0$0
+G$AX5051_FREQA2$0$0
+G$AX5051_FREQ3$0$0
+G$AX5051_DATARATELO$0$0
+G$IE_7$0$0
+G$EIE_2$0$0
+G$E2IP_5$0$0
+G$IC0CAPT$0$0
+_ADCCH1VAL1
+_ADCCH2VAL0
+_FRCOSCPER1
+_LPOSCPER0
+_AX5051_IRQREQUEST
+_AX5051_FIFOCONTROLNB
+_ACC_2
+_B_7
+_E2IE_4
+_PORTA_3
+_PORTB_2
+_PORTC_1
+G$AX5051_TXBITRATELONB$0$0
+G$AX5051_AGCTARGETNB$0$0
+G$AX5051_PLLLOOP$0$0
+G$AX5051_FREQA3$0$0
+G$OV$0$0
+G$EIE_3$0$0
+G$E2IP_6$0$0
+G$SPCLKSRC$0$0
+G$IC1CAPT$0$0
+_ADCCH2VAL1
+_ADCCH3VAL0
+_LPOSCPER1
+_AX5051_RXMISC
+_IP
+_T0CNT0
+_ACC_3
+_E2IE_5
+_PORTA_4
+_PORTB_3
+_PORTC_2
+G$AX5051_MODULATORMISC$0$0
+G$ADCCH0VAL$0$0
+G$EIE_4$0$0
+G$E2IP_7$0$0
+G$OC0STATUS$0$0
+_ADCCH3VAL1
+_OSCREADY
+_OSCRUN
+_RADIOFDATAADDR0
+_AX5051_DATARATEHI
+_AX5051_ENCODINGNB
+_T0CNT1
+_T1CNT0
+_ACC_4
+_E2IE_6
+_PORTA_5
+_PORTB_4
+_PORTC_3
+G$FRCOSCPER$0$0
+G$ADCCH1VAL$0$0
+G$EIE_5$0$0
+G$WTSTAT$0$0
+G$OC1STATUS$0$0
+G$OC0MODE$0$0
+G$DPS$0$0
+_RADIOFDATAADDR1
+_AX5051_IFFREQLO
+_AX5051_IRQMASK
+_AX5051_SCRATCHNB
+_AX5051_TXBITRATEHINB
+_RADIOSTAT0
+_T1CNT1
+_T2CNT0
+_WTEVTA
+_ACC_5
+_E2IE_7
+_PORTA_6
+_PORTB_5
+_PORTC_4
+G$AX5051_IRQREQUESTNB$0$0
+G$AX5051_TXPWR$0$0
+G$LPOSCPER$0$0
+G$ADCCH2VAL$0$0
+G$IP_0$0$0
+G$EIE_6$0$0
+G$T0STATUS$0$0
+G$OC1MODE$0$0
+G$PINA$0$0
+_AX5051_PLLVCOI
+_DPH
+_RADIOSTAT1
+_SPSHREG
+_T2CNT1
+_WTEVTB
+_ACC_6
+_CY
+_PORTA_7
+_PORTB_6
+_PORTC_5
+G$AX5051_RXMISCNB$0$0
+G$RADIOMUX$0$0
+G$ADCCH3VAL$0$0
+G$IP_1$0$0
+G$EIE_7$0$0
+G$U0STATUS$0$0
+G$T1STATUS$0$0
+G$T0MODE$0$0
+G$T0CNT$0$0
+G$OC0PIN$0$0
+G$PINB$0$0
+_DMA0ADDR
+_FRCOSCREF
+_EXTIRQ
+_WTEVTC
+_ACC_7
+_IE_0
+_PORTB_7
+_PORTC_6
+G$AX5051_DATARATEHINB$0$0
+G$AX5051_TRKAMPLITUDEHI$0$0
+G$RADIOFDATAADDR$0$0
+G$FRCOSCKFILT0$0$0
+G$IP_2$0$0
+G$WTIRQEN$0$0
+G$U1STATUS$0$0
+G$U0MODE$0$0
+G$T2STATUS$0$0
+G$T1MODE$0$0
+G$T1CNT$0$0
+G$OC1PIN$0$0
+G$PINC$0$0
+G$DPTR0$0$0
+_DMA1ADDR
+_FRCOSCFREQ0
+_LPOSCREF
+_XTALOSC
+_AX5051_FECSYNCNB
+_EIP
+_WTEVTD
+_IE_1
+_PORTC_7
+G$AX5051_IRQMASKNB$0$0
+G$AX5051_IFFREQLONB$0$0
+G$AX5051_PINCFG1$0$0
+G$LPOSCKFILT0$0$0
+G$FRCOSCKFILT1$0$0
+G$IP_3$0$0
+G$U1MODE$0$0
+G$T2MODE$0$0
+G$T2CNT$0$0
+G$RADIOSTAT$0$0
+G$DPTR1$0$0
+_FRCOSCFREQ1
+_LPOSCFREQ0
+_AX5051_DSPMODENB
+_E2IP_0
+_IE_2
+G$AX5051_PLLVCOINB$0$0
+G$AX5051_PLLRNGCLK$0$0
+G$AX5051_PINCFG2$0$0
+G$AX5051_IRQINVERSION$0$0
+G$LPOSCKFILT1$0$0
+G$IP_4$0$0
+_PALTRADIO
+_LPOSCFREQ1
+_AX5051_REF
+_AX5051_CICSHIFTNB
+_AX5051_XTALCAPNB
+_DPL
+_DIRA
+_IC0STATUS
+_E2IP_1
+_IE_3
+A$ax5051wrfifo$1700
+A$ax5051wrfifo$1701
+A$ax5051wrfifo$1702
+A$ax5051wrfifo$1650
+A$ax5051wrfifo$1660
+A$ax5051wrfifo$1651
+A$ax5051wrfifo$1670
+A$ax5051wrfifo$1652
+A$ax5051wrfifo$1643
+A$ax5051wrfifo$1680
+A$ax5051wrfifo$1671
+A$ax5051wrfifo$1653
+A$ax5051wrfifo$1644
+A$ax5051wrfifo$1690
+A$ax5051wrfifo$1681
+A$ax5051wrfifo$1672
+A$ax5051wrfifo$1663
+A$ax5051wrfifo$1645
+A$ax5051wrfifo$1691
+A$ax5051wrfifo$1682
+A$ax5051wrfifo$1673
+A$ax5051wrfifo$1664
+A$ax5051wrfifo$1655
+A$ax5051wrfifo$1646
+A$ax5051wrfifo$1692
+A$ax5051wrfifo$1683
+A$ax5051wrfifo$1674
+A$ax5051wrfifo$1665
+A$ax5051wrfifo$1656
+A$ax5051wrfifo$1647
+A$ax5051wrfifo$1684
+A$ax5051wrfifo$1675
+A$ax5051wrfifo$1666
+A$ax5051wrfifo$1657
+A$ax5051wrfifo$1648
+A$ax5051wrfifo$1694
+A$ax5051wrfifo$1667
+A$ax5051wrfifo$1658
+A$ax5051wrfifo$1649
+A$ax5051wrfifo$1695
+A$ax5051wrfifo$1686
+A$ax5051wrfifo$1677
+A$ax5051wrfifo$1696
+A$ax5051wrfifo$1687
+A$ax5051wrfifo$1678
+A$ax5051wrfifo$1669
+A$ax5051wrfifo$1697
+A$ax5051wrfifo$1688
+A$ax5051wrfifo$1679
+A$ax5051wrfifo$1698
+A$ax5051wrfifo$1689
+A$ax5051wrfifo$1699
+C$ax5051wrfifo.c$10$0$0
+C$ax5051wrfifo.c$75$1$66
+C$ax5051wrfifo.c$76$1$66
+G$ax5051_writefifo$0$0
+_ax5051_writefifo
+XG$ax5051_writefifo$0$0
+
+
+
+ax5051regs 5544037
+.__.ABS.
+
+
+
+ax8052regs 5545075
+.__.ABS.
+
+
+
+
+
+
+
+lcdinit
+
+;!FILE libmflarge/lcdinit.asm
+XH3
+H 1B areas 3B7 global symbols
+M lcdinit
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
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+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 3 flags 40 addr 0
+S Llcdinit.lcd_writecmd$cmd$1$57 Def000001
+S Llcdinit.lcd_write$v$1$54 Def000000
+S Llcdinit.lcd_writedata$d$1$59 Def000002
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 121 flags 20 addr 0
+S A$lcdinit$1546 Def00010B
+S A$lcdinit$1528 Def0000F3
+S A$lcdinit$1483 Def0000BA
+S A$lcdinit$1474 Def0000B3
+S A$lcdinit$1465 Def0000AB
+S A$lcdinit$1456 Def0000A2
+S A$lcdinit$1429 Def000096
+S A$lcdinit$1393 Def000081
+S A$lcdinit$1339 Def00005C
+S A$lcdinit$1294 Def000038
+S A$lcdinit$1285 Def00002E
+S A$lcdinit$1267 Def000029
+S C$lcdinit.c$116$1$66 Def000117
+S C$lcdinit.c$107$1$66 Def0000FC
+S A$lcdinit$1556 Def000117
+S A$lcdinit$1529 Def0000F6
+S A$lcdinit$1493 Def0000C6
+S A$lcdinit$1367 Def00006F
+S A$lcdinit$1358 Def000065
+S A$lcdinit$1295 Def00003B
+S A$lcdinit$1286 Def000030
+S A$lcdinit$1268 Def00002B
+S C$lcdinit.c$117$1$66 Def00011D
+S C$lcdinit.c$108$1$66 Def000102
+S A$lcdinit$1557 Def00011A
+S A$lcdinit$1539 Def000102
+S A$lcdinit$1494 Def0000C9
+S A$lcdinit$1368 Def000072
+S A$lcdinit$1359 Def000067
+S A$lcdinit$1296 Def00003C
+S A$lcdinit$1287 Def000032
+S XG$lcd_writedata$0$0 Def00007A
+S A$lcdinit$1549 Def00010E
+S A$lcdinit$1486 Def0000BD
+S A$lcdinit$1477 Def0000B5
+S A$lcdinit$1468 Def0000AE
+S A$lcdinit$1459 Def0000A5
+S A$lcdinit$1387 Def00007B
+S A$lcdinit$1369 Def000073
+S A$lcdinit$1288 Def000035
+S A$lcdinit$1487 Def0000C0
+S A$lcdinit$1199 Def000000
+S G$lcd_writecmd$0$0 Def00004F
+S C$lcdinit.c$10$3$50 Def00000A
+S A$lcdinit$1497 Def0000CC
+S C$lcdinit.c$21$1$52 Def000025
+S C$lcdinit.c$22$1$52 Def00002D
+S C$lcdinit.c$20$2$53 Def000023
+S C$lcdinit.c$24$1$52 Def00002E
+S C$lcdinit.c$51$1$62 Def00007B
+S G$lcd_waitshort$0$0 Def00001D
+S G$lcd_waitlong$0$0 Def000000
+S C$lcdinit.c$52$1$62 Def00007E
+S C$lcdinit.c$45$1$60 Def00006D
+S C$lcdinit.c$30$2$56 Def00003E
+S C$lcdinit.c$60$1$64 Def000088
+S C$lcdinit.c$53$1$62 Def000081
+S C$lcdinit.c$46$1$60 Def00006F
+S C$lcdinit.c$33$1$55 Def000044
+S C$lcdinit.c$13$1$48 Def000012
+S C$lcdinit.c$11$2$49 Def00000C
+S C$lcdinit.c$61$1$64 Def00008A
+S C$lcdinit.c$47$1$60 Def00007A
+S C$lcdinit.c$40$1$58 Def000059
+S C$lcdinit.c$34$1$55 Def00004A
+S C$lcdinit.c$19$1$52 Def000023
+S C$lcdinit.c$14$1$48 Def00001C
+S C$lcdinit.c$12$2$49 Def000010
+S C$lcdinit.c$62$1$64 Def00008D
+S C$lcdinit.c$55$1$62 Def000082
+S C$lcdinit.c$41$1$58 Def000064
+S C$lcdinit.c$35$1$55 Def00004E
+S C$lcdinit.c$26$1$55 Def000036
+S C$lcdinit.c$63$1$64 Def000090
+S C$lcdinit.c$49$1$60 Def00007B
+S C$lcdinit.c$27$1$55 Def000038
+S C$lcdinit.c$16$1$48 Def00001D
+S C$lcdinit.c$80$1$66 Def0000B3
+S C$lcdinit.c$64$1$64 Def000093
+S C$lcdinit.c$43$1$58 Def000065
+S C$lcdinit.c$37$1$55 Def00004F
+S G$lcd_write$0$0 Def00002E
+S _lcd_writecmd Def00004F
+S C$lcdinit.c$90$1$66 Def0000CC
+S C$lcdinit.c$81$1$66 Def0000B5
+S C$lcdinit.c$72$1$66 Def00009C
+S C$lcdinit.c$65$1$64 Def000096
+S C$lcdinit.c$18$1$48 Def000021
+S C$lcdinit.c$82$1$66 Def0000B8
+S C$lcdinit.c$73$1$66 Def00009F
+S C$lcdinit.c$66$1$64 Def000099
+S C$lcdinit.c$29$2$55 Def00003E
+S C$lcdinit.c$92$1$66 Def0000CF
+S C$lcdinit.c$74$1$66 Def0000A2
+S C$lcdinit.c$67$1$64 Def00009B
+S C$lcdinit.c$58$1$64 Def000082
+S C$lcdinit.c$93$1$66 Def0000D5
+S C$lcdinit.c$84$1$66 Def0000BA
+S C$lcdinit.c$75$1$66 Def0000A5
+S C$lcdinit.c$59$1$64 Def000085
+S C$lcdinit.c$76$1$66 Def0000A8
+S C$lcdinit.c$69$1$64 Def00009C
+S C$lcdinit.c$39$1$58 Def000057
+S C$lcdinit.c$95$1$66 Def0000D8
+S C$lcdinit.c$86$1$66 Def0000BD
+S C$lcdinit.c$77$1$66 Def0000AB
+S _lcd_waitshort Def00001D
+S _lcd_waitlong Def000000
+S C$lcdinit.c$96$1$66 Def0000DE
+S C$lcdinit.c$87$1$66 Def0000C3
+S C$lcdinit.c$78$1$66 Def0000AE
+S C$lcdinit.c$79$1$66 Def0000B1
+S C$lcdinit.c$98$1$66 Def0000E1
+S C$lcdinit.c$89$1$66 Def0000C6
+S G$lcd_init$0$0 Def00009C
+S C$lcdinit.c$99$1$66 Def0000E7
+S XG$lcd_writecmd$0$0 Def000064
+S _lcd_write Def00002E
+S G$lcd_portinit$0$0 Def000082
+S C$lcdinit.c$7$1$48 Def000008
+S C$lcdinit.c$4$0$0 Def000000
+S C$lcdinit.c$8$2$48 Def000008
+S XG$lcd_waitshort$0$0 Def00002D
+S XG$lcd_waitlong$0$0 Def00001C
+S C$lcdinit.c$6$1$0 Def000006
+S C$lcdinit.c$9$2$49 Def00000A
+S G$lcd_portoff$0$0 Def00007B
+S _lcd_init Def00009C
+S XG$lcd_write$0$0 Def00004E
+S G$lcd_writedata$0$0 Def000065
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+S XG$lcd_init$0$0 Def000120
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+S A$lcdinit$1200 Def000002
+S A$lcdinit$1210 Def000008
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+S A$lcdinit$1230 Def000013
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+S _lcd_writedata Def000065
+S A$lcdinit$1501 Def0000D2
+S A$lcdinit$1420 Def00008D
+S A$lcdinit$1411 Def000085
+S A$lcdinit$1330 Def000051
+S A$lcdinit$1312 Def00004A
+S A$lcdinit$1303 Def000040
+S A$lcdinit$1231 Def000014
+S A$lcdinit$1222 Def00000E
+S A$lcdinit$1204 Def000006
+S A$lcdinit$1511 Def0000DE
+S A$lcdinit$1340 Def00005D
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+S A$lcdinit$1313 Def00004C
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+S A$lcdinit$1250 Def00001D
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+S A$lcdinit$1260 Def000023
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+S A$lcdinit$1233 Def000018
+S A$lcdinit$1522 Def0000ED
+S A$lcdinit$1504 Def0000D5
+S A$lcdinit$1450 Def00009C
+S A$lcdinit$1432 Def000099
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+S A$lcdinit$1360 Def000069
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+S A$lcdinit$1261 Def000024
+S A$lcdinit$1234 Def00001A
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+S A$lcdinit$1216 Def00000A
+S C$lcdinit.c$110$1$66 Def000105
+S C$lcdinit.c$101$1$66 Def0000EA
+S A$lcdinit$1550 Def000111
+S A$lcdinit$1532 Def0000F9
+S A$lcdinit$1514 Def0000E1
+S A$lcdinit$1370 Def000075
+S A$lcdinit$1361 Def00006C
+S A$lcdinit$1316 Def00004E
+S A$lcdinit$1307 Def000044
+S A$lcdinit$1271 Def00002D
+S A$lcdinit$1226 Def000011
+S A$lcdinit$1217 Def00000B
+S C$lcdinit.c$111$1$66 Def00010B
+S C$lcdinit.c$102$1$66 Def0000F0
+S A$lcdinit$1560 Def00011D
+S A$lcdinit$1542 Def000105
+S A$lcdinit$1515 Def0000E4
+S A$lcdinit$1371 Def000078
+S A$lcdinit$1335 Def000057
+S A$lcdinit$1308 Def000047
+S A$lcdinit$1254 Def000021
+S C$lcdinit.c$121$1$66 Def000120
+S A$lcdinit$1543 Def000108
+S A$lcdinit$1525 Def0000F0
+S A$lcdinit$1507 Def0000D8
+S A$lcdinit$1480 Def0000B8
+S A$lcdinit$1471 Def0000B1
+S A$lcdinit$1462 Def0000A8
+S A$lcdinit$1453 Def00009F
+S A$lcdinit$1435 Def00009B
+S A$lcdinit$1426 Def000093
+S A$lcdinit$1417 Def00008A
+S A$lcdinit$1408 Def000082
+S A$lcdinit$1390 Def00007E
+S A$lcdinit$1345 Def000064
+S A$lcdinit$1309 Def000049
+S A$lcdinit$1291 Def000036
+S A$lcdinit$1264 Def000025
+S A$lcdinit$1237 Def00001C
+S C$lcdinit.c$113$1$66 Def00010E
+S C$lcdinit.c$104$1$66 Def0000F3
+S XG$lcd_portoff$0$0 Def000081
+S A$lcdinit$1553 Def000114
+S A$lcdinit$1535 Def0000FC
+S A$lcdinit$1508 Def0000DB
+S A$lcdinit$1490 Def0000C3
+S A$lcdinit$1364 Def00006D
+S A$lcdinit$1265 Def000026
+S A$lcdinit$1229 Def000012
+S C$lcdinit.c$114$1$66 Def000114
+S C$lcdinit.c$105$1$66 Def0000F9
+S A$lcdinit$1563 Def000120
+S A$lcdinit$1536 Def0000FF
+S A$lcdinit$1518 Def0000E7
+S A$lcdinit$1374 Def00007A
+S A$lcdinit$1338 Def000059
+S A$lcdinit$1329 Def00004F
+S A$lcdinit$1266 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0B
+T 00 00 00
+R 00 00 00 0B
+T 00 00 01
+R 00 00 00 0B
+T 00 00 01
+R 00 00 00 0B
+T 00 00 02
+R 00 00 00 0B
+T 00 00 02
+R 00 00 00 0B
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 C0 07 C0 06 C0 05 7F 40
+R 00 00 00 17
+T 00 00 08
+R 00 00 00 17
+T 00 00 08 7E 00
+R 00 00 00 17
+T 00 00 0A
+R 00 00 00 17
+T 00 00 0A EE 14 FD FE 70 FA EF 14 FE FF 70 F2 D0
+R 00 00 00 17
+T 00 00 17 05 D0 06 D0 07 22
+R 00 00 00 17
+T 00 00 1D
+R 00 00 00 17
+T 00 00 1D C0 07 C0 06 7F 00
+R 00 00 00 17
+T 00 00 23
+R 00 00 00 17
+T 00 00 23 EF 14 FE FF 70 FA D0 06 D0 07 22
+R 00 00 00 17
+T 00 00 2E
+R 00 00 00 17
+T 00 00 2E C0 07 E5 82 90 00 00 F0 C2 90 90 00 00
+R 00 00 00 17 00 08 00 0B 00 0E 00 0B
+T 00 00 3B E0 F5 DE
+R 00 00 00 17
+T 00 00 3E
+R 00 00 00 17
+T 00 00 3E E5 DD FF 30 E0 FA 90 00 00 E5 DE F0 D2
+R 00 00 00 17 00 0A 00 0B
+T 00 00 4B 90 D0 07 22
+R 00 00 00 17
+T 00 00 4F
+R 00 00 00 17
+T 00 00 4F C0 07 E5 82 90 00 01 F0 C2 88 90 00 01
+R 00 00 00 17 00 08 00 0B 00 0E 00 0B
+T 00 00 5C E0 F5 82 12 00 2E D0 07 22
+R 00 00 00 17 00 07 00 17
+T 00 00 65
+R 00 00 00 17
+T 00 00 65 C0 07 E5 82 90 00 02 F0 D2 88 90 00 02
+R 00 00 00 17 00 08 00 0B 00 0E 00 0B
+T 00 00 72 E0 F5 82 12 00 2E D0 07 22
+R 00 00 00 17 00 07 00 17
+T 00 00 7B
+R 00 00 00 17
+T 00 00 7B 75 DF 07 75 DC 00 22
+R 00 00 00 17
+T 00 00 82
+R 00 00 00 17
+T 00 00 82 43 8A 03 53 88 FE D2 89 43 8B 07 43 90
+R 00 00 00 17
+T 00 00 8F 03 53 90 FB 75 DF D8 75 DC 01 E5 DE 22
+R 00 00 00 17
+T 00 00 9C
+R 00 00 00 17
+T 00 00 9C 43 8A 03 53 88 FC 43 8B 07 43 90 03 53
+R 00 00 00 17
+T 00 00 A9 90 FB 75 DF D8 75 DC 01 E5 DE C2 89 12
+R 00 00 00 17
+T 00 00 B6 00 00 D2 89 12 00 00 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 08 00 17
+T 00 00 C1 00 4F 12 00 00 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 CA 00 4F 12 00 1D 75 82 30 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 D3 00 4F 12 00 1D 75 82 39 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 DC 00 4F 12 00 1D 75 82 14 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 E5 00 4F 12 00 1D 75 82 56 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 EE 00 4F 12 00 1D 75 82 6D 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 00 F7 00 4F 12 00 1D 75 82 78 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 01 00 00 4F 12 00 1D 75 82 0C 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 01 09 00 4F 12 00 1D 75 82 06 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 01 12 00 4F 12 00 1D 75 82 01 12
+R 00 00 00 17 00 03 00 17 00 06 00 17
+T 00 01 1B 00 4F 12 00 00 22
+R 00 00 00 17 00 03 00 17 00 06 00 17
+
+
+M:lcdinit
+F:G$lcd_waitlong$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_waitshort$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_write$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_writecmd$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_writedata$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_portoff$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_portinit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$lcd_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdinit.lcd_init$x$1$66({1}SC:U),R,0,0,[]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Llcdinit.lcd_write$v$1$54({1}SC:U),F,0,0
+S:Llcdinit.lcd_writecmd$cmd$1$57({1}SC:U),F,0,0
+S:Llcdinit.lcd_writedata$d$1$59({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdsetpos
+
+;!FILE libmflarge/lcdsetpos.asm
+XH3
+H 1A areas 14 global symbols
+M lcdsetpos
+O -mmcs51 --model-large
+S _lcd_writecmd Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 1 flags 40 addr 0
+S Llcdsetpos.lcd_setpos$v$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 15 flags 20 addr 0
+S G$lcd_setpos$0$0 Def000000
+S C$lcdsetpos.c$5$1$48 Def000008
+S C$lcdsetpos.c$6$1$48 Def000014
+S C$lcdsetpos.c$3$0$0 Def000000
+S _lcd_setpos Def000000
+S XG$lcd_setpos$0$0 Def000014
+S A$lcdsetpos$120 Def000008
+S A$lcdsetpos$121 Def000009
+S A$lcdsetpos$122 Def00000A
+S A$lcdsetpos$123 Def00000D
+S A$lcdsetpos$114 Def000000
+S A$lcdsetpos$124 Def00000F
+S A$lcdsetpos$115 Def000002
+S A$lcdsetpos$125 Def000012
+S A$lcdsetpos$116 Def000004
+S A$lcdsetpos$117 Def000007
+S A$lcdsetpos$128 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 E5 82 90 00 00 F0 E0 FF 43 07 80
+R 00 00 00 16 00 08 00 0A
+T 00 00 0D 8F 82 12 00 00 D0 07 22
+R 00 00 00 16 02 06 00 00
+
+
+M:lcdsetpos
+F:G$lcd_setpos$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdsetpos.lcd_setpos$v$1$47({1}SC:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrstr
+
+;!FILE libmflarge/lcdwrstr.asm
+XH3
+H 1A areas 4A global symbols
+M lcdwrstr
+O -mmcs51 --model-large
+S _lcd_writecmd Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+S __gptrget Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 3 flags 40 addr 0
+S Llcdwrstr.lcd_writestr$ch$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 59 flags 20 addr 0
+S XG$lcd_writestr$0$0 Def000058
+S A$lcdwrstr$120 Def000006
+S A$lcdwrstr$130 Def000014
+S A$lcdwrstr$121 Def000009
+S C$lcdwrstr.c$10$3$50 Def00003B
+S A$lcdwrstr$140 Def00001B
+S A$lcdwrstr$131 Def000015
+S A$lcdwrstr$122 Def00000A
+S A$lcdwrstr$150 Def00002E
+S A$lcdwrstr$141 Def00001D
+S A$lcdwrstr$132 Def000016
+S A$lcdwrstr$123 Def00000B
+S A$lcdwrstr$160 Def000036
+S A$lcdwrstr$151 Def00002F
+S A$lcdwrstr$142 Def00001F
+S A$lcdwrstr$133 Def000017
+S A$lcdwrstr$124 Def00000C
+S C$lcdwrstr.c$12$3$51 Def000043
+S A$lcdwrstr$152 Def000030
+S A$lcdwrstr$143 Def000021
+S A$lcdwrstr$134 Def000018
+S A$lcdwrstr$125 Def00000D
+S A$lcdwrstr$180 Def00004D
+S A$lcdwrstr$153 Def000031
+S A$lcdwrstr$144 Def000024
+S A$lcdwrstr$135 Def000019
+S A$lcdwrstr$126 Def00000E
+S A$lcdwrstr$117 Def000000
+S A$lcdwrstr$181 Def000050
+S A$lcdwrstr$172 Def000043
+S A$lcdwrstr$163 Def000038
+S A$lcdwrstr$154 Def000032
+S A$lcdwrstr$145 Def000025
+S A$lcdwrstr$136 Def00001A
+S A$lcdwrstr$127 Def00000F
+S A$lcdwrstr$118 Def000002
+S A$lcdwrstr$191 Def000058
+S A$lcdwrstr$182 Def000051
+S A$lcdwrstr$173 Def000045
+S A$lcdwrstr$155 Def000033
+S A$lcdwrstr$146 Def000026
+S A$lcdwrstr$128 Def000010
+S A$lcdwrstr$119 Def000004
+S A$lcdwrstr$183 Def000052
+S A$lcdwrstr$156 Def000034
+S A$lcdwrstr$147 Def000028
+S A$lcdwrstr$129 Def000013
+S A$lcdwrstr$184 Def000053
+S A$lcdwrstr$166 Def00003B
+S A$lcdwrstr$148 Def00002A
+S A$lcdwrstr$185 Def000054
+S A$lcdwrstr$167 Def00003E
+S A$lcdwrstr$149 Def00002D
+S A$lcdwrstr$186 Def000055
+S A$lcdwrstr$177 Def000048
+S A$lcdwrstr$168 Def000041
+S A$lcdwrstr$159 Def000035
+S C$lcdwrstr.c$16$1$48 Def000058
+S C$lcdwrstr.c$14$2$49 Def000048
+S A$lcdwrstr$187 Def000056
+S A$lcdwrstr$178 Def00004B
+S A$lcdwrstr$188 Def000057
+S G$lcd_writestr$0$0 Def000000
+S C$lcdwrstr.c$3$0$0 Def000000
+S C$lcdwrstr.c$6$2$49 Def00001B
+S C$lcdwrstr.c$7$2$49 Def000035
+S C$lcdwrstr.c$9$2$49 Def000038
+S _lcd_writestr Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF F0 AE 83 E5 82 90 00 00 F0 EE A3 F0
+R 00 00 00 16 00 0A 00 0A
+T 00 00 0D EF A3 F0 90 00 00 E0 FD A3 E0 FE A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 1A FF
+R 00 00 00 16
+T 00 00 1B
+R 00 00 00 16
+T 00 00 1B 8D 82 8E 83 8F F0 12 00 00 FC A3 AD 82
+R 00 00 00 16 02 0A 00 04
+T 00 00 28 AE 83 90 00 00 ED F0 EE A3 F0 EF A3 F0
+R 00 00 00 16 00 06 00 0A
+T 00 00 35 EC 60 15 BC 0A 08 75 82 C0 12 00 00 80
+R 00 00 00 16 02 0D 00 00
+T 00 00 42 05
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 8C 82 12 00 00
+R 00 00 00 16 02 06 00 03
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 12 00 00 80 CE
+R 00 00 00 16 02 04 00 01
+T 00 00 4D
+R 00 00 00 16
+T 00 00 4D 90 00 00 ED F0 EE A3 F0 EF A3 F0 22
+R 00 00 00 16 00 04 00 0A
+
+
+M:lcdwrstr
+F:G$lcd_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrstr.lcd_writestr$c$2$49({1}SC:S),R,0,0,[r4]
+S:Llcdwrstr.lcd_writestr$ch$1$47({3}DG,SC:S),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdclear
+
+;!FILE libmflarge/lcdclear.asm
+XH3
+H 1A areas 3C global symbols
+M lcdclear
+O -mmcs51 --model-large
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 2 flags 40 addr 0
+S Llcdclear.lcd_clear$len$1$47 Def000000
+S _lcd_clear_PARM_2 Def000000
+S Llcdclear.lcd_clear$pos$1$47 Def000001
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 40 flags 20 addr 0
+S XG$lcd_clear$0$0 Def00003F
+S A$lcdclear$130 Def00000A
+S A$lcdclear$140 Def000015
+S A$lcdclear$122 Def000000
+S A$lcdclear$123 Def000002
+S A$lcdclear$133 Def00000D
+S A$lcdclear$124 Def000005
+S A$lcdclear$161 Def000025
+S A$lcdclear$152 Def00001F
+S A$lcdclear$134 Def000010
+S A$lcdclear$162 Def000026
+S A$lcdclear$144 Def000017
+S A$lcdclear$135 Def000011
+S C$lcdclear.c$10$1$48 Def00001A
+S A$lcdclear$190 Def00003F
+S A$lcdclear$163 Def000027
+S A$lcdclear$136 Def000012
+S A$lcdclear$127 Def000006
+S C$lcdclear.c$11$1$48 Def00001F
+S A$lcdclear$182 Def000037
+S A$lcdclear$173 Def00002F
+S A$lcdclear$164 Def000028
+S A$lcdclear$137 Def000013
+S A$lcdclear$128 Def000007
+S C$lcdclear.c$12$1$48 Def000021
+S A$lcdclear$183 Def00003A
+S A$lcdclear$174 Def000032
+S A$lcdclear$156 Def000021
+S A$lcdclear$147 Def00001A
+S A$lcdclear$129 Def000008
+S C$lcdclear.c$13$1$48 Def000025
+S A$lcdclear$175 Def000033
+S A$lcdclear$157 Def000023
+S C$lcdclear.c$14$1$48 Def00002A
+S A$lcdclear$167 Def00002A
+S A$lcdclear$158 Def000024
+S A$lcdclear$149 Def00001D
+S C$lcdclear.c$15$1$48 Def00002F
+S A$lcdclear$186 Def00003D
+S A$lcdclear$168 Def00002D
+S A$lcdclear$169 Def00002E
+S A$lcdclear$179 Def000034
+S C$lcdclear.c$18$1$48 Def00003D
+S C$lcdclear.c$16$2$49 Def000034
+S C$lcdclear.c$19$1$48 Def00003F
+S C$lcdclear.c$17$2$49 Def000037
+S G$lcd_clear$0$0 Def000000
+S C$lcdclear.c$6$1$48 Def000006
+S C$lcdclear.c$3$0$0 Def000000
+S C$lcdclear.c$7$1$48 Def00000D
+S C$lcdclear.c$8$1$48 Def000015
+S C$lcdclear.c$9$1$48 Def000017
+S _lcd_clear Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 90 00 01 F0 E0 FF F5 82 12 00 00
+R 00 00 00 16 00 06 00 0A 02 0E 00 00
+T 00 00 0D 90 00 00 E0 FE E0 70 02 80 28
+R 00 00 00 16 00 04 00 0A
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 53 07 3F BF 10 00
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 40 02 80 1E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 74 10 C3 9F FF C3 9E 50 05 90 00 00 EF
+R 00 00 00 16 00 0D 00 0A
+T 00 00 2E F0
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 90 00 00 E0 FF
+R 00 00 00 16 00 04 00 0A
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 12 00 00 75 82 20 12 00 00 DF F5
+R 00 00 00 16 02 04 00 01 02 0A 00 03
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F 22
+R 00 00 00 16
+
+
+M:lcdclear
+F:G$lcd_clear$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdclear.lcd_clear$x$1$48({1}SC:U),R,0,0,[r7]
+S:Llcdclear.lcd_clear$len$1$47({1}SC:U),F,0,0
+S:Llcdclear.lcd_clear$pos$1$47({1}SC:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdclrdisp
+
+;!FILE libmflarge/lcdclrdisp.asm
+XH3
+H 1A areas B global symbols
+M lcdclrdisp
+O -mmcs51 --model-large
+S _lcd_writecmd Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S A$lcdclrdisp$111 Def000000
+S A$lcdclrdisp$112 Def000003
+S A$lcdclrdisp$115 Def000006
+S C$lcdclrdisp.c$5$1$48 Def000000
+S C$lcdclrdisp.c$6$1$48 Def000006
+S C$lcdclrdisp.c$3$0$0 Def000000
+S G$lcd_cleardisplay$0$0 Def000000
+S _lcd_cleardisplay Def000000
+S XG$lcd_cleardisplay$0$0 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 82 01 12 00 00 22
+R 00 00 00 16 02 07 00 00
+
+
+M:lcdclrdisp
+F:G$lcd_cleardisplay$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwru16
+
+;!FILE libmflarge/lcdwru16.asm
+XH3
+H 1A areas 60 global symbols
+M lcdwru16
+O -mmcs51 --model-large
+S __divuint Ref000000
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S Llcdwru16.lcd_writeu16$val$1$47 Def000002
+S _lcd_writeu16_PARM_2 Def000000
+S _lcd_writeu16_PARM_3 Def000001
+S Llcdwru16.lcd_writeu16$pos$1$47 Def000001
+S Llcdwru16.lcd_writeu16$nrdig$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 75 flags 20 addr 0
+S XG$lcd_writeu16$0$0 Def000074
+S A$lcdwru16$220 Def000074
+S A$lcdwru16$202 Def000064
+S A$lcdwru16$130 Def000007
+S A$lcdwru16$212 Def000070
+S A$lcdwru16$203 Def000066
+S A$lcdwru16$140 Def000013
+S A$lcdwru16$131 Def000008
+S A$lcdwru16$204 Def000067
+S A$lcdwru16$150 Def00001D
+S A$lcdwru16$141 Def000014
+S A$lcdwru16$132 Def000009
+S A$lcdwru16$205 Def000068
+S A$lcdwru16$160 Def000029
+S A$lcdwru16$151 Def00001E
+S A$lcdwru16$133 Def00000A
+S A$lcdwru16$215 Def000071
+S A$lcdwru16$206 Def00006A
+S A$lcdwru16$170 Def00003D
+S A$lcdwru16$161 Def00002A
+S A$lcdwru16$152 Def00001F
+S A$lcdwru16$143 Def000015
+S A$lcdwru16$216 Def000072
+S A$lcdwru16$180 Def00004B
+S A$lcdwru16$171 Def00003F
+S A$lcdwru16$162 Def00002B
+S A$lcdwru16$153 Def000020
+S A$lcdwru16$144 Def000016
+S A$lcdwru16$190 Def000059
+S A$lcdwru16$181 Def00004E
+S A$lcdwru16$172 Def000041
+S A$lcdwru16$163 Def00002D
+S A$lcdwru16$136 Def00000B
+S A$lcdwru16$127 Def000000
+S A$lcdwru16$209 Def00006D
+S A$lcdwru16$191 Def00005A
+S A$lcdwru16$182 Def00004F
+S A$lcdwru16$173 Def000043
+S A$lcdwru16$164 Def00002F
+S A$lcdwru16$137 Def00000E
+S A$lcdwru16$128 Def000002
+S C$lcdwru16.c$10$2$49 Def000061
+S A$lcdwru16$192 Def00005B
+S A$lcdwru16$183 Def000050
+S A$lcdwru16$174 Def000046
+S A$lcdwru16$165 Def000031
+S A$lcdwru16$156 Def000022
+S A$lcdwru16$147 Def000018
+S A$lcdwru16$138 Def00000F
+S A$lcdwru16$129 Def000004
+S C$lcdwru16.c$11$2$49 Def000064
+S A$lcdwru16$184 Def000051
+S A$lcdwru16$175 Def000047
+S A$lcdwru16$166 Def000033
+S A$lcdwru16$157 Def000025
+S A$lcdwru16$148 Def00001B
+S A$lcdwru16$139 Def000010
+S C$lcdwru16.c$12$2$49 Def00006D
+S A$lcdwru16$185 Def000052
+S A$lcdwru16$176 Def000049
+S A$lcdwru16$167 Def000035
+S A$lcdwru16$158 Def000027
+S A$lcdwru16$149 Def00001C
+S C$lcdwru16.c$13$2$49 Def000070
+S A$lcdwru16$195 Def00005C
+S A$lcdwru16$186 Def000053
+S A$lcdwru16$177 Def00004A
+S A$lcdwru16$168 Def000038
+S A$lcdwru16$159 Def000028
+S C$lcdwru16.c$16$1$48 Def000074
+S C$lcdwru16.c$14$2$49 Def000071
+S A$lcdwru16$196 Def00005E
+S A$lcdwru16$187 Def000054
+S A$lcdwru16$169 Def00003A
+S A$lcdwru16$188 Def000057
+S A$lcdwru16$189 Def000058
+S A$lcdwru16$199 Def000061
+S G$lcd_writeu16$0$0 Def000000
+S C$lcdwru16.c$5$1$48 Def00000B
+S C$lcdwru16.c$3$0$0 Def000000
+S C$lcdwru16.c$7$1$48 Def000022
+S C$lcdwru16.c$6$2$48 Def000018
+S C$lcdwru16.c$8$2$49 Def00004B
+S C$lcdwru16.c$9$2$49 Def00005C
+S _lcd_writeu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 83 E5 82 90 00 02 F0 EF A3 F0 90
+R 00 00 00 16 00 08 00 0A
+T 00 00 0C 00 01 E0 FF 90 00 00 E0 FE
+R 00 00 00 16 00 03 00 0A 00 08 00 0A
+T 00 00 15
+R 00 00 00 16
+T 00 00 15 EE 60 5C 90 00 02 E0 FC A3 E0 FD 8C 03
+R 00 00 00 16 00 07 00 0A
+T 00 00 22 90 00 00 74 0A F0 E4 A3 F0 8C 82 8D 83
+R 00 00 00 16 02 04 00 04
+T 00 00 2F C0 07 C0 06 C0 03 12 00 00 E5 82 85 83
+R 00 00 00 16 02 0A 00 00
+T 00 00 3C F0 D0 03 D0 06 D0 07 90 00 02 F0 E5 F0
+R 00 00 00 16 00 0B 00 0A
+T 00 00 49 A3 F0 90 00 02 E0 FC A3 E0 FD EC 75 F0
+R 00 00 00 16 00 06 00 0A
+T 00 00 56 0A A4 D3 9B F4 FB 8F 82 12 00 00 12
+R 00 00 00 16 02 0C 00 01
+T 00 00 62 00 00 74 30 2B FB F5 82 12 00 00 12
+R 00 00 00 16 02 03 00 02 02 0C 00 05
+T 00 00 6E 00 00 1F 1E 80 A1
+R 00 00 00 16 02 03 00 02
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 22
+R 00 00 00 16
+
+
+M:lcdwru16
+F:G$lcd_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwru16.lcd_writeu16$v1$2$49({1}SC:U),R,0,0,[r3]
+S:Llcdwru16.lcd_writeu16$nrdig$1$47({1}SC:U),F,0,0
+S:Llcdwru16.lcd_writeu16$pos$1$47({1}SC:U),F,0,0
+S:Llcdwru16.lcd_writeu16$val$1$47({2}SI:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwru32
+
+;!FILE libmflarge/lcdwru32.asm
+XH3
+H 1A areas 84 global symbols
+M lcdwru32
+O -mmcs51 --model-large
+S __divulong_PARM_2 Ref000000
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 6 flags 40 addr 0
+S Llcdwru32.lcd_writeu32$val$1$47 Def000002
+S _lcd_writeu32_PARM_2 Def000000
+S _lcd_writeu32_PARM_3 Def000001
+S Llcdwru32.lcd_writeu32$pos$1$47 Def000001
+S Llcdwru32.lcd_writeu32$nrdig$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 9A flags 20 addr 0
+S XG$lcd_writeu32$0$0 Def000099
+S A$lcdwru32$200 Def000062
+S A$lcdwru32$210 Def00006A
+S A$lcdwru32$201 Def000063
+S A$lcdwru32$220 Def000076
+S A$lcdwru32$211 Def00006D
+S A$lcdwru32$202 Def000064
+S A$lcdwru32$130 Def000006
+S A$lcdwru32$221 Def000077
+S A$lcdwru32$212 Def00006E
+S A$lcdwru32$203 Def000065
+S A$lcdwru32$140 Def000012
+S A$lcdwru32$131 Def000007
+S A$lcdwru32$240 Def00008C
+S A$lcdwru32$231 Def000081
+S A$lcdwru32$222 Def000078
+S A$lcdwru32$213 Def00006F
+S A$lcdwru32$204 Def000066
+S A$lcdwru32$150 Def00001E
+S A$lcdwru32$141 Def000013
+S A$lcdwru32$132 Def00000A
+S A$lcdwru32$241 Def00008D
+S A$lcdwru32$232 Def000083
+S A$lcdwru32$223 Def000079
+S A$lcdwru32$214 Def000070
+S A$lcdwru32$205 Def000067
+S A$lcdwru32$160 Def000028
+S A$lcdwru32$142 Def000014
+S A$lcdwru32$133 Def00000B
+S A$lcdwru32$251 Def000096
+S A$lcdwru32$242 Def00008F
+S A$lcdwru32$224 Def00007C
+S A$lcdwru32$215 Def000071
+S A$lcdwru32$206 Def000068
+S A$lcdwru32$161 Def000029
+S A$lcdwru32$152 Def00001F
+S A$lcdwru32$134 Def00000C
+S A$lcdwru32$252 Def000097
+S A$lcdwru32$225 Def00007D
+S A$lcdwru32$216 Def000072
+S A$lcdwru32$207 Def000069
+S A$lcdwru32$180 Def00003E
+S A$lcdwru32$171 Def000032
+S A$lcdwru32$162 Def00002A
+S A$lcdwru32$153 Def000020
+S A$lcdwru32$135 Def00000D
+S A$lcdwru32$235 Def000086
+S A$lcdwru32$226 Def00007E
+S A$lcdwru32$217 Def000073
+S A$lcdwru32$190 Def000051
+S A$lcdwru32$181 Def00003F
+S A$lcdwru32$172 Def000035
+S A$lcdwru32$163 Def00002B
+S A$lcdwru32$145 Def000015
+S A$lcdwru32$136 Def00000E
+S A$lcdwru32$127 Def000000
+S A$lcdwru32$245 Def000092
+S A$lcdwru32$227 Def00007F
+S A$lcdwru32$218 Def000074
+S A$lcdwru32$191 Def000053
+S A$lcdwru32$182 Def000041
+S A$lcdwru32$173 Def000037
+S A$lcdwru32$164 Def00002C
+S A$lcdwru32$146 Def000018
+S A$lcdwru32$137 Def00000F
+S A$lcdwru32$128 Def000002
+S C$lcdwru32.c$10$2$49 Def000086
+S A$lcdwru32$228 Def000080
+S A$lcdwru32$219 Def000075
+S A$lcdwru32$192 Def000055
+S A$lcdwru32$183 Def000043
+S A$lcdwru32$174 Def000038
+S A$lcdwru32$165 Def00002D
+S A$lcdwru32$156 Def000022
+S A$lcdwru32$147 Def000019
+S A$lcdwru32$138 Def000010
+S A$lcdwru32$129 Def000004
+S C$lcdwru32.c$11$2$49 Def000089
+S A$lcdwru32$256 Def000099
+S A$lcdwru32$238 Def000089
+S A$lcdwru32$193 Def000056
+S A$lcdwru32$184 Def000045
+S A$lcdwru32$175 Def000039
+S A$lcdwru32$166 Def00002E
+S A$lcdwru32$157 Def000025
+S A$lcdwru32$148 Def00001A
+S A$lcdwru32$139 Def000011
+S C$lcdwru32.c$12$2$49 Def000092
+S A$lcdwru32$248 Def000095
+S A$lcdwru32$239 Def00008B
+S A$lcdwru32$194 Def000058
+S A$lcdwru32$185 Def000046
+S A$lcdwru32$176 Def00003A
+S A$lcdwru32$167 Def00002F
+S A$lcdwru32$158 Def000026
+S A$lcdwru32$149 Def00001D
+S C$lcdwru32.c$13$2$49 Def000095
+S A$lcdwru32$195 Def00005A
+S A$lcdwru32$186 Def000048
+S A$lcdwru32$177 Def00003B
+S A$lcdwru32$168 Def000030
+S A$lcdwru32$159 Def000027
+S C$lcdwru32.c$16$1$48 Def000099
+S C$lcdwru32.c$14$2$49 Def000096
+S A$lcdwru32$196 Def00005C
+S A$lcdwru32$187 Def00004A
+S A$lcdwru32$178 Def00003C
+S A$lcdwru32$197 Def00005F
+S A$lcdwru32$188 Def00004C
+S A$lcdwru32$179 Def00003D
+S A$lcdwru32$198 Def000060
+S A$lcdwru32$189 Def00004F
+S A$lcdwru32$199 Def000061
+S G$lcd_writeu32$0$0 Def000000
+S C$lcdwru32.c$5$1$48 Def000015
+S C$lcdwru32.c$3$0$0 Def000000
+S C$lcdwru32.c$7$1$48 Def000032
+S C$lcdwru32.c$6$2$48 Def000022
+S C$lcdwru32.c$8$2$49 Def00006A
+S C$lcdwru32.c$9$2$49 Def000081
+S _lcd_writeu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 02 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 01 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A 90 00 00 E0 FE
+R 00 00 00 16 00 04 00 0A
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F EE 60 77 90 00 02 E0 FA A3 E0 FB A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 2C FC A3 E0 FD 8A 01 90 00 00 74 0A F0 E4
+R 00 00 00 16 02 0A 00 00
+T 00 00 39 A3 F0 A3 F0 A3 F0 8A 82 8B 83 8C F0 ED
+R 00 00 00 16
+T 00 00 46 C0 07 C0 06 C0 01 12 00 00 AA 82 AB 83
+R 00 00 00 16 02 0A 00 04
+T 00 00 53 AC F0 FD D0 01 D0 06 D0 07 90 00 02 EA
+R 00 00 00 16 00 0D 00 0A
+T 00 00 60 F0 EB A3 F0 EC A3 F0 ED A3 F0 90 00 02
+R 00 00 00 16 00 0E 00 0A
+T 00 00 6D E0 FA A3 E0 FB A3 E0 FC A3 E0 FD EA 75
+R 00 00 00 16
+T 00 00 7A F0 0A A4 D3 99 F4 F9 8F 82 12 00 00 12
+R 00 00 00 16 02 0D 00 01
+T 00 00 87 00 00 74 30 29 F9 F5 82 12 00 00 12
+R 00 00 00 16 02 03 00 02 02 0C 00 05
+T 00 00 93 00 00 1F 1E 80 86
+R 00 00 00 16 02 03 00 02
+T 00 00 99
+R 00 00 00 16
+T 00 00 99 22
+R 00 00 00 16
+
+
+M:lcdwru32
+F:G$lcd_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwru32.lcd_writeu32$v1$2$49({1}SC:U),R,0,0,[r1]
+S:Llcdwru32.lcd_writeu32$nrdig$1$47({1}SC:U),F,0,0
+S:Llcdwru32.lcd_writeu32$pos$1$47({1}SC:U),F,0,0
+S:Llcdwru32.lcd_writeu32$val$1$47({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrhexu16
+
+;!FILE libmflarge/lcdwrhexu16.asm
+XH3
+H 1A areas 54 global symbols
+M lcdwrhexu16
+O -mmcs51 --model-large
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S _lcd_writehexu16_PARM_2 Def000000
+S _lcd_writehexu16_PARM_3 Def000001
+S Llcdwrhexu16.lcd_writehexu16$val$1$47 Def000002
+S Llcdwrhexu16.lcd_writehexu16$pos$1$47 Def000001
+S Llcdwrhexu16.lcd_writehexu16$nrdig$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 5D flags 20 addr 0
+S XG$lcd_writehexu16$0$0 Def00005C
+S A$lcdwrhexu16$200 Def000052
+S A$lcdwrhexu16$210 Def00005A
+S A$lcdwrhexu16$130 Def000007
+S A$lcdwrhexu16$203 Def000055
+S A$lcdwrhexu16$140 Def000013
+S A$lcdwrhexu16$131 Def000008
+S A$lcdwrhexu16$150 Def00001D
+S A$lcdwrhexu16$141 Def000014
+S A$lcdwrhexu16$132 Def000009
+S A$lcdwrhexu16$214 Def00005C
+S A$lcdwrhexu16$160 Def000027
+S A$lcdwrhexu16$151 Def00001E
+S A$lcdwrhexu16$133 Def00000A
+S A$lcdwrhexu16$206 Def000058
+S A$lcdwrhexu16$170 Def000034
+S A$lcdwrhexu16$161 Def000028
+S A$lcdwrhexu16$143 Def000015
+S A$lcdwrhexu16$171 Def000035
+S A$lcdwrhexu16$162 Def00002A
+S A$lcdwrhexu16$144 Def000016
+S A$lcdwrhexu16$190 Def000046
+S A$lcdwrhexu16$163 Def00002B
+S A$lcdwrhexu16$154 Def00001F
+S A$lcdwrhexu16$136 Def00000B
+S A$lcdwrhexu16$127 Def000000
+S A$lcdwrhexu16$209 Def000059
+S A$lcdwrhexu16$182 Def00003E
+S A$lcdwrhexu16$164 Def00002C
+S A$lcdwrhexu16$155 Def000021
+S A$lcdwrhexu16$137 Def00000E
+S A$lcdwrhexu16$128 Def000002
+S C$lcdwrhexu16.c$10$2$49 Def00003E
+S A$lcdwrhexu16$183 Def000040
+S A$lcdwrhexu16$174 Def000036
+S A$lcdwrhexu16$165 Def00002D
+S A$lcdwrhexu16$156 Def000022
+S A$lcdwrhexu16$147 Def000018
+S A$lcdwrhexu16$138 Def00000F
+S A$lcdwrhexu16$129 Def000004
+S C$lcdwrhexu16.c$11$2$49 Def000044
+S A$lcdwrhexu16$193 Def000049
+S A$lcdwrhexu16$184 Def000042
+S A$lcdwrhexu16$166 Def00002E
+S A$lcdwrhexu16$157 Def000023
+S A$lcdwrhexu16$148 Def00001B
+S A$lcdwrhexu16$139 Def000010
+S C$lcdwrhexu16.c$12$2$49 Def000049
+S A$lcdwrhexu16$185 Def000043
+S A$lcdwrhexu16$167 Def000031
+S A$lcdwrhexu16$158 Def000024
+S A$lcdwrhexu16$149 Def00001C
+S C$lcdwrhexu16.c$13$2$49 Def00004C
+S A$lcdwrhexu16$177 Def000039
+S A$lcdwrhexu16$168 Def000032
+S A$lcdwrhexu16$159 Def000026
+S C$lcdwrhexu16.c$14$2$49 Def000055
+S A$lcdwrhexu16$196 Def00004C
+S A$lcdwrhexu16$169 Def000033
+S C$lcdwrhexu16.c$15$2$49 Def000058
+S A$lcdwrhexu16$197 Def00004E
+S A$lcdwrhexu16$179 Def00003C
+S C$lcdwrhexu16.c$18$1$48 Def00005C
+S C$lcdwrhexu16.c$16$2$49 Def000059
+S A$lcdwrhexu16$198 Def00004F
+S A$lcdwrhexu16$189 Def000044
+S A$lcdwrhexu16$199 Def000050
+S G$lcd_writehexu16$0$0 Def000000
+S C$lcdwrhexu16.c$5$1$48 Def00000B
+S C$lcdwrhexu16.c$3$0$0 Def000000
+S C$lcdwrhexu16.c$6$2$48 Def000018
+S C$lcdwrhexu16.c$7$2$49 Def00001F
+S C$lcdwrhexu16.c$8$2$49 Def000036
+S C$lcdwrhexu16.c$9$2$49 Def000039
+S _lcd_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 83 E5 82 90 00 02 F0 EF A3 F0 90
+R 00 00 00 16 00 08 00 0A
+T 00 00 0C 00 01 E0 FF 90 00 00 E0 FE
+R 00 00 00 16 00 03 00 0A 00 08 00 0A
+T 00 00 15
+R 00 00 00 16
+T 00 00 15 EE 60 44 90 00 02 E0 FC A3 E0 8C 03 C4
+R 00 00 00 16 00 07 00 0A
+T 00 00 22 CC C4 54 0F 6C CC 54 0F CC 6C CC FD 90
+R 00 00 00 16
+T 00 00 2F 00 02 EC F0 ED A3 F0 53 03 0F BB 0A 00
+R 00 00 00 16 00 03 00 0A
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 40 06 8B 05 74 07 2D FB
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 8F 82 12 00 00 12 00 00 74 30 2B FB F5
+R 00 00 00 16 02 06 00 00 02 09 00 01
+T 00 00 51 82 12 00 00 12 00 00 1F 1E 80 B9
+R 00 00 00 16 02 05 00 03 02 08 00 01
+T 00 00 5C
+R 00 00 00 16
+T 00 00 5C 22
+R 00 00 00 16
+
+
+M:lcdwrhexu16
+F:G$lcd_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrhexu16.lcd_writehexu16$v1$2$49({1}SC:U),R,0,0,[r3]
+S:Llcdwrhexu16.lcd_writehexu16$nrdig$1$47({1}SC:U),F,0,0
+S:Llcdwrhexu16.lcd_writehexu16$pos$1$47({1}SC:U),F,0,0
+S:Llcdwrhexu16.lcd_writehexu16$val$1$47({2}SI:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcdwrhexu32
+
+;!FILE libmflarge/lcdwrhexu32.asm
+XH3
+H 1A areas 7C global symbols
+M lcdwrhexu32
+O -mmcs51 --model-large
+S _lcd_setpos Ref000000
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 6 flags 40 addr 0
+S _lcd_writehexu32_PARM_2 Def000000
+S Llcdwrhexu32.lcd_writehexu32$val$1$47 Def000002
+S _lcd_writehexu32_PARM_3 Def000001
+S Llcdwrhexu32.lcd_writehexu32$pos$1$47 Def000001
+S Llcdwrhexu32.lcd_writehexu32$nrdig$1$47 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 89 flags 20 addr 0
+S XG$lcd_writehexu32$0$0 Def000088
+S A$lcdwrhexu32$200 Def000054
+S A$lcdwrhexu32$210 Def000060
+S A$lcdwrhexu32$201 Def000057
+S A$lcdwrhexu32$211 Def000061
+S A$lcdwrhexu32$202 Def000058
+S A$lcdwrhexu32$130 Def000006
+S A$lcdwrhexu32$230 Def000072
+S A$lcdwrhexu32$203 Def000059
+S A$lcdwrhexu32$140 Def000012
+S A$lcdwrhexu32$131 Def000007
+S A$lcdwrhexu32$240 Def00007E
+S A$lcdwrhexu32$222 Def00006A
+S A$lcdwrhexu32$204 Def00005A
+S A$lcdwrhexu32$150 Def00001E
+S A$lcdwrhexu32$141 Def000013
+S A$lcdwrhexu32$132 Def00000A
+S A$lcdwrhexu32$250 Def000086
+S A$lcdwrhexu32$223 Def00006C
+S A$lcdwrhexu32$214 Def000062
+S A$lcdwrhexu32$205 Def00005B
+S A$lcdwrhexu32$160 Def000028
+S A$lcdwrhexu32$142 Def000014
+S A$lcdwrhexu32$133 Def00000B
+S A$lcdwrhexu32$233 Def000075
+S A$lcdwrhexu32$224 Def00006E
+S A$lcdwrhexu32$206 Def00005C
+S A$lcdwrhexu32$161 Def000029
+S A$lcdwrhexu32$152 Def00001F
+S A$lcdwrhexu32$134 Def00000C
+S A$lcdwrhexu32$243 Def000081
+S A$lcdwrhexu32$225 Def00006F
+S A$lcdwrhexu32$207 Def00005D
+S A$lcdwrhexu32$180 Def00003D
+S A$lcdwrhexu32$171 Def000032
+S A$lcdwrhexu32$162 Def00002A
+S A$lcdwrhexu32$153 Def000020
+S A$lcdwrhexu32$135 Def00000D
+S A$lcdwrhexu32$217 Def000065
+S A$lcdwrhexu32$208 Def00005E
+S A$lcdwrhexu32$190 Def000048
+S A$lcdwrhexu32$181 Def00003E
+S A$lcdwrhexu32$172 Def000033
+S A$lcdwrhexu32$163 Def00002B
+S A$lcdwrhexu32$145 Def000015
+S A$lcdwrhexu32$136 Def00000E
+S A$lcdwrhexu32$127 Def000000
+S A$lcdwrhexu32$254 Def000088
+S A$lcdwrhexu32$236 Def000078
+S A$lcdwrhexu32$209 Def00005F
+S A$lcdwrhexu32$191 Def000049
+S A$lcdwrhexu32$182 Def00003F
+S A$lcdwrhexu32$173 Def000034
+S A$lcdwrhexu32$164 Def00002C
+S A$lcdwrhexu32$146 Def000018
+S A$lcdwrhexu32$137 Def00000F
+S A$lcdwrhexu32$128 Def000002
+S C$lcdwrhexu32.c$10$2$49 Def00006A
+S A$lcdwrhexu32$246 Def000084
+S A$lcdwrhexu32$237 Def00007A
+S A$lcdwrhexu32$219 Def000068
+S A$lcdwrhexu32$192 Def00004A
+S A$lcdwrhexu32$183 Def000040
+S A$lcdwrhexu32$174 Def000035
+S A$lcdwrhexu32$165 Def00002D
+S A$lcdwrhexu32$156 Def000022
+S A$lcdwrhexu32$147 Def000019
+S A$lcdwrhexu32$138 Def000010
+S A$lcdwrhexu32$129 Def000004
+S C$lcdwrhexu32.c$11$2$49 Def000070
+S A$lcdwrhexu32$238 Def00007B
+S A$lcdwrhexu32$229 Def000070
+S A$lcdwrhexu32$193 Def00004C
+S A$lcdwrhexu32$184 Def000041
+S A$lcdwrhexu32$175 Def000036
+S A$lcdwrhexu32$166 Def00002E
+S A$lcdwrhexu32$157 Def000025
+S A$lcdwrhexu32$148 Def00001A
+S A$lcdwrhexu32$139 Def000011
+S C$lcdwrhexu32.c$12$2$49 Def000075
+S A$lcdwrhexu32$239 Def00007C
+S A$lcdwrhexu32$194 Def00004D
+S A$lcdwrhexu32$185 Def000042
+S A$lcdwrhexu32$176 Def000038
+S A$lcdwrhexu32$167 Def00002F
+S A$lcdwrhexu32$158 Def000026
+S A$lcdwrhexu32$149 Def00001D
+S C$lcdwrhexu32.c$13$2$49 Def000078
+S A$lcdwrhexu32$249 Def000085
+S A$lcdwrhexu32$195 Def00004E
+S A$lcdwrhexu32$186 Def000044
+S A$lcdwrhexu32$177 Def000039
+S A$lcdwrhexu32$168 Def000030
+S A$lcdwrhexu32$159 Def000027
+S C$lcdwrhexu32.c$14$2$49 Def000081
+S A$lcdwrhexu32$196 Def000050
+S A$lcdwrhexu32$187 Def000045
+S A$lcdwrhexu32$178 Def00003A
+S C$lcdwrhexu32.c$15$2$49 Def000084
+S A$lcdwrhexu32$197 Def000051
+S A$lcdwrhexu32$188 Def000046
+S A$lcdwrhexu32$179 Def00003C
+S C$lcdwrhexu32.c$18$1$48 Def000088
+S C$lcdwrhexu32.c$16$2$49 Def000085
+S A$lcdwrhexu32$198 Def000052
+S A$lcdwrhexu32$189 Def000047
+S A$lcdwrhexu32$199 Def000053
+S G$lcd_writehexu32$0$0 Def000000
+S C$lcdwrhexu32.c$5$1$48 Def000015
+S C$lcdwrhexu32.c$3$0$0 Def000000
+S C$lcdwrhexu32.c$6$2$48 Def000022
+S C$lcdwrhexu32.c$7$2$49 Def000032
+S C$lcdwrhexu32.c$8$2$49 Def000062
+S C$lcdwrhexu32.c$9$2$49 Def000065
+S _lcd_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 02 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 01 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A 90 00 00 E0 FE
+R 00 00 00 16 00 04 00 0A
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F EE 60 66 90 00 02 E0 FA A3 E0 FB A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 2C FC A3 E0 FD 8A 01 EB C4 CA C4 54 0F 6A
+R 00 00 00 16
+T 00 00 39 CA 54 0F CA 6A CA FB EC C4 54 F0 4B FB
+R 00 00 00 16
+T 00 00 46 ED C4 CC C4 54 0F 6C CC 54 0F CC 6C CC
+R 00 00 00 16
+T 00 00 53 FD 90 00 02 EA F0 EB A3 F0 EC A3 F0 ED
+R 00 00 00 16 00 05 00 0A
+T 00 00 60 A3 F0 53 01 0F B9 0A 00
+R 00 00 00 16
+T 00 00 68
+R 00 00 00 16
+T 00 00 68 40 06 89 05 74 07 2D F9
+R 00 00 00 16
+T 00 00 70
+R 00 00 00 16
+T 00 00 70 8F 82 12 00 00 12 00 00 74 30 29 F9 F5
+R 00 00 00 16 02 06 00 00 02 09 00 01
+T 00 00 7D 82 12 00 00 12 00 00 1F 1E 80 97
+R 00 00 00 16 02 05 00 03 02 08 00 01
+T 00 00 88
+R 00 00 00 16
+T 00 00 88 22
+R 00 00 00 16
+
+
+M:lcdwrhexu32
+F:G$lcd_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcdwrhexu32.lcd_writehexu32$v1$2$49({1}SC:U),R,0,0,[r1]
+S:Llcdwrhexu32.lcd_writehexu32$nrdig$1$47({1}SC:U),F,0,0
+S:Llcdwrhexu32.lcd_writehexu32$pos$1$47({1}SC:U),F,0,0
+S:Llcdwrhexu32.lcd_writehexu32$val$1$47({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrnum16
+
+;!FILE libmflarge/lcduwrnum16.asm
+XH3
+H 1A areas CE global symbols
+M lcduwrnum16
+O -mmcs51 --model-large
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _bp Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11C flags 20 addr 0
+S C$lcduwrnum16.c$8$0$0 Def000000
+S G$lcd_writenum16$0$0 Def000000
+S _lcd_writenum16 Def000000
+S XG$lcd_writenum16$0$0 Def00011B
+S A$lcduwrnum16$300 Def0000CA
+S A$lcduwrnum16$120 Def000000
+S A$lcduwrnum16$310 Def0000D0
+S A$lcduwrnum16$220 Def000068
+S A$lcduwrnum16$211 Def000061
+S A$lcduwrnum16$202 Def000058
+S A$lcduwrnum16$130 Def00000D
+S A$lcduwrnum16$121 Def000002
+S C$lcduwrnum16.c$30$1$50 Def00006A
+S A$lcduwrnum16$311 Def0000D1
+S A$lcduwrnum16$203 Def000059
+S A$lcduwrnum16$140 Def000018
+S A$lcduwrnum16$122 Def000005
+S C$lcduwrnum16.c$31$1$50 Def00006C
+S C$lcduwrnum16.c$22$1$50 Def000051
+S A$lcduwrnum16$330 Def0000E2
+S A$lcduwrnum16$303 Def0000CD
+S A$lcduwrnum16$240 Def00007A
+S A$lcduwrnum16$231 Def00006E
+S A$lcduwrnum16$150 Def000026
+S A$lcduwrnum16$141 Def00001A
+S A$lcduwrnum16$123 Def000007
+S C$lcduwrnum16.c$23$1$50 Def000057
+S C$lcduwrnum16.c$20$2$52 Def00004F
+S A$lcduwrnum16$340 Def0000ED
+S A$lcduwrnum16$331 Def0000E5
+S A$lcduwrnum16$322 Def0000DA
+S A$lcduwrnum16$250 Def00008C
+S A$lcduwrnum16$241 Def00007C
+S A$lcduwrnum16$232 Def000070
+S A$lcduwrnum16$223 Def00006A
+S A$lcduwrnum16$160 Def000033
+S A$lcduwrnum16$151 Def000028
+S A$lcduwrnum16$142 Def00001B
+S A$lcduwrnum16$133 Def00000F
+S A$lcduwrnum16$124 Def000009
+S C$lcduwrnum16.c$24$1$50 Def000058
+S A$lcduwrnum16$350 Def0000FC
+S A$lcduwrnum16$341 Def0000EE
+S A$lcduwrnum16$314 Def0000D4
+S A$lcduwrnum16$260 Def000099
+S A$lcduwrnum16$251 Def00008D
+S A$lcduwrnum16$242 Def00007E
+S A$lcduwrnum16$233 Def000072
+S A$lcduwrnum16$215 Def000062
+S A$lcduwrnum16$206 Def00005C
+S A$lcduwrnum16$170 Def00003B
+S A$lcduwrnum16$161 Def000034
+S A$lcduwrnum16$152 Def000029
+S A$lcduwrnum16$134 Def000011
+S C$lcduwrnum16.c$16$1$50 Def00001D
+S A$lcduwrnum16$360 Def00010C
+S A$lcduwrnum16$351 Def0000FD
+S A$lcduwrnum16$342 Def0000F0
+S A$lcduwrnum16$315 Def0000D5
+S A$lcduwrnum16$306 Def0000CE
+S A$lcduwrnum16$270 Def0000A5
+S A$lcduwrnum16$261 Def00009C
+S A$lcduwrnum16$252 Def00008F
+S A$lcduwrnum16$243 Def00007F
+S A$lcduwrnum16$234 Def000073
+S A$lcduwrnum16$207 Def00005D
+S A$lcduwrnum16$180 Def000049
+S A$lcduwrnum16$171 Def00003D
+S A$lcduwrnum16$162 Def000035
+S A$lcduwrnum16$153 Def00002A
+S A$lcduwrnum16$135 Def000013
+S A$lcduwrnum16$352 Def000100
+S A$lcduwrnum16$343 Def0000F2
+S A$lcduwrnum16$334 Def0000E8
+S A$lcduwrnum16$325 Def0000DD
+S A$lcduwrnum16$244 Def000081
+S A$lcduwrnum16$208 Def00005F
+S A$lcduwrnum16$181 Def00004A
+S A$lcduwrnum16$163 Def000036
+S A$lcduwrnum16$154 Def00002B
+S A$lcduwrnum16$145 Def00001D
+S A$lcduwrnum16$136 Def000014
+S A$lcduwrnum16$127 Def00000B
+S A$lcduwrnum16$371 Def000114
+S A$lcduwrnum16$344 Def0000F3
+S A$lcduwrnum16$326 Def0000DE
+S A$lcduwrnum16$290 Def0000BA
+S A$lcduwrnum16$281 Def0000AF
+S A$lcduwrnum16$263 Def00009E
+S A$lcduwrnum16$245 Def000082
+S A$lcduwrnum16$227 Def00006C
+S A$lcduwrnum16$218 Def000065
+S A$lcduwrnum16$182 Def00004B
+S A$lcduwrnum16$164 Def000037
+S A$lcduwrnum16$155 Def00002D
+S A$lcduwrnum16$146 Def00001E
+S C$lcduwrnum16.c$64$1$50 Def00010D
+S C$lcduwrnum16.c$51$3$61 Def0000D4
+S C$lcduwrnum16.c$50$2$54 Def0000D0
+S C$lcduwrnum16.c$32$2$54 Def00006E
+S C$lcduwrnum16.c$28$1$50 Def000062
+S C$lcduwrnum16.c$19$1$50 Def00003F
+S C$lcduwrnum16.c$17$2$51 Def000030
+S A$lcduwrnum16$372 Def000116
+S A$lcduwrnum16$345 Def0000F4
+S A$lcduwrnum16$318 Def0000D8
+S A$lcduwrnum16$273 Def0000A7
+S A$lcduwrnum16$264 Def00009F
+S A$lcduwrnum16$255 Def000091
+S A$lcduwrnum16$246 Def000084
+S A$lcduwrnum16$237 Def000075
+S A$lcduwrnum16$219 Def000066
+S A$lcduwrnum16$192 Def000051
+S A$lcduwrnum16$183 Def00004C
+S A$lcduwrnum16$165 Def000038
+S A$lcduwrnum16$147 Def000021
+S C$lcduwrnum16.c$65$1$50 Def000114
+S C$lcduwrnum16.c$60$2$54 Def0000FC
+S C$lcduwrnum16.c$52$3$61 Def0000D8
+S C$lcduwrnum16.c$33$2$54 Def000075
+S C$lcduwrnum16.c$29$1$50 Def000065
+S C$lcduwrnum16.c$25$2$53 Def00005C
+S C$lcduwrnum16.c$18$2$51 Def00003B
+S A$lcduwrnum16$373 Def000119
+S A$lcduwrnum16$364 Def00010D
+S A$lcduwrnum16$355 Def000103
+S A$lcduwrnum16$346 Def0000F6
+S A$lcduwrnum16$274 Def0000A8
+S A$lcduwrnum16$256 Def000093
+S A$lcduwrnum16$247 Def000087
+S A$lcduwrnum16$238 Def000077
+S A$lcduwrnum16$193 Def000052
+S A$lcduwrnum16$184 Def00004D
+S A$lcduwrnum16$175 Def00003F
+S A$lcduwrnum16$166 Def000039
+S A$lcduwrnum16$148 Def000023
+S A$lcduwrnum16$139 Def000016
+S C$lcduwrnum16.c$66$1$50 Def00011B
+S C$lcduwrnum16.c$53$3$61 Def0000DA
+S C$lcduwrnum16.c$34$2$54 Def000091
+S C$lcduwrnum16.c$26$2$53 Def000061
+S C$lcduwrnum16.c$10$1$0 Def00000B
+S A$lcduwrnum16$365 Def00010F
+S A$lcduwrnum16$356 Def000106
+S A$lcduwrnum16$347 Def0000F9
+S A$lcduwrnum16$338 Def0000E9
+S A$lcduwrnum16$329 Def0000E0
+S A$lcduwrnum16$293 Def0000BD
+S A$lcduwrnum16$284 Def0000B1
+S A$lcduwrnum16$257 Def000095
+S A$lcduwrnum16$248 Def000089
+S A$lcduwrnum16$239 Def000079
+S A$lcduwrnum16$194 Def000054
+S A$lcduwrnum16$176 Def000040
+S A$lcduwrnum16$167 Def00003A
+S A$lcduwrnum16$158 Def000030
+S A$lcduwrnum16$149 Def000025
+S C$lcduwrnum16.c$54$3$61 Def0000DD
+S A$lcduwrnum16$357 Def000109
+S A$lcduwrnum16$339 Def0000EB
+S A$lcduwrnum16$294 Def0000BE
+S A$lcduwrnum16$267 Def0000A2
+S A$lcduwrnum16$258 Def000096
+S A$lcduwrnum16$249 Def00008A
+S A$lcduwrnum16$195 Def000055
+S A$lcduwrnum16$177 Def000043
+S A$lcduwrnum16$159 Def000032
+S C$lcduwrnum16.c$44$6$60 Def0000C4
+S C$lcduwrnum16.c$12$1$0 Def00000D
+S A$lcduwrnum16$376 Def00011B
+S A$lcduwrnum16$367 Def000111
+S A$lcduwrnum16$295 Def0000C1
+S A$lcduwrnum16$277 Def0000AB
+S A$lcduwrnum16$268 Def0000A3
+S A$lcduwrnum16$259 Def000097
+S A$lcduwrnum16$178 Def000044
+S C$lcduwrnum16.c$42$4$56 Def0000B4
+S C$lcduwrnum16.c$40$5$57 Def0000B1
+S C$lcduwrnum16.c$35$3$55 Def0000A2
+S C$lcduwrnum16.c$13$1$0 Def00000F
+S A$lcduwrnum16$278 Def0000AC
+S A$lcduwrnum16$269 Def0000A4
+S A$lcduwrnum16$188 Def00004F
+S A$lcduwrnum16$179 Def000047
+S C$lcduwrnum16.c$62$3$65 Def00010C
+S C$lcduwrnum16.c$43$4$56 Def0000BD
+S C$lcduwrnum16.c$14$1$0 Def000016
+S A$lcduwrnum16$288 Def0000B4
+S A$lcduwrnum16$198 Def000057
+S C$lcduwrnum16.c$61$4$66 Def000103
+S C$lcduwrnum16.c$56$4$62 Def0000E8
+S C$lcduwrnum16.c$37$3$55 Def0000A7
+S A$lcduwrnum16$298 Def0000C4
+S A$lcduwrnum16$289 Def0000B7
+S C$lcduwrnum16.c$55$5$63 Def0000E0
+S A$lcduwrnum16$299 Def0000C7
+S C$lcduwrnum16.c$59$2$54 Def0000E9
+S C$lcduwrnum16.c$47$4$56 Def0000CE
+S C$lcduwrnum16.c$38$4$56 Def0000AB
+S C$lcduwrnum16.c$45$5$59 Def0000CD
+S C$lcduwrnum16.c$39$5$57 Def0000AF
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 C0 82 C0 83
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 03
+T 00 00 09 05 81 7D 00 7C 05 E5 00 00 00 24 FC F8
+R 00 00 00 16 F1 23 0A 00 03
+T 00 00 14 86 03 E5 00 00 00 24 FD F8 86 02 EB 30
+R 00 00 00 16 F1 23 06 00 03
+T 00 00 1F E0 1E C0 04 A8 00 00 00 08 86 04 08 E6
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 2A FF D0 04 30 E7 0F A8 00 00 00 08 C3 E4
+R 00 00 00 16 F1 23 0A 00 03
+T 00 00 35 96 F6 08 E4 96 F6 7D 2D 80 12
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F EB 20 E2 0C EB 30 E1 0A A8 00 00 00 08
+R 00 00 00 16 F1 23 0C 00 03
+T 00 00 4A E6 08 46 60 02
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F 7D 2B
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 ED 60 04 EA 60 01 1A
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 30 E4 06 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 53 03 3F EA 24 FA 50 02 8A 04
+R 00 00 00 16
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C 8C 07
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E E5 00 00 00 24 03 F8 A6 07 E5 00 00 00
+R 00 00 00 16 F1 23 04 00 03 F1 23 0D 00 03
+T 00 00 77 24 03 FE C0 06 A8 00 00 00 08 86 82 08
+R 00 00 00 16 F1 23 09 00 03
+T 00 00 82 86 83 12 00 00 A8 00 00 00 08 A6 82 08
+R 00 00 00 16 02 06 00 02 F1 23 09 00 03
+T 00 00 8D A6 83 15 81 E5 00 00 00 24 03 F8 E6 70
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 98 37 BF 01 02 80 32
+R 00 00 00 16
+T 00 00 9E
+R 00 00 00 16
+T 00 00 9E EB 20 E7 2E C3 EA 9F 40 66 EB 20 E3 25
+R 00 00 00 16
+T 00 00 AB EB 20 E6 05 8F 02 43 03 40
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 75 82 20 12 00 00 12 00 00 EB 30 E4 4C
+R 00 00 00 16 02 07 00 04 02 0A 00 00
+T 00 00 C1 BF 04 49 75 82 20 12 00 00 12 00 00 0A
+R 00 00 00 16 02 0A 00 04 02 0D 00 00
+T 00 00 CE 80 3D
+R 00 00 00 16
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 EB 20 E7 15 EB 20 E6 02 8F 02
+R 00 00 00 16
+T 00 00 DA
+R 00 00 00 16
+T 00 00 DA 43 03 C8 ED 60 09 8D 82 12 00 00 12
+R 00 00 00 16 02 0C 00 04
+T 00 00 E6 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 E9
+R 00 00 00 16
+T 00 00 E9 E5 00 00 00 24 03 F8 86 06 74 30 2E FE
+R 00 00 00 16 F1 23 04 00 03
+T 00 00 F4 F5 82 12 00 00 12 00 00 EB 30 E4 0D BF
+R 00 00 00 16 02 06 00 04 02 09 00 00
+T 00 01 01 04 0A 75 82 27 12 00 00 12 00 00 0A
+R 00 00 00 16 02 09 00 04 02 0C 00 00
+T 00 01 0D
+R 00 00 00 16
+T 00 01 0D DF 02 80 03
+R 00 00 00 16
+T 00 01 11
+R 00 00 00 16
+T 00 01 11 02 00 6E
+R 00 00 00 16 00 04 00 16
+T 00 01 14
+R 00 00 00 16
+T 00 01 14 8A 82 85 00 00 00 81 D0 00 00 00 22
+R 00 00 00 16 F1 23 06 00 03 F1 23 0B 00 03
+
+
+M:lcduwrnum16
+F:G$lcd_writenum16$0$0({2}DF,SC:U),Z,0,3,0,0,0
+S:Llcduwrnum16.lcd_writenum16$nrdig1$1$49({1}SC:U),B,1,-3
+S:Llcduwrnum16.lcd_writenum16$flags1$1$49({1}SC:U),B,1,-4
+S:Llcduwrnum16.lcd_writenum16$val$1$49({2}SI:U),B,1,1
+S:Llcduwrnum16.lcd_writenum16$ch$1$50({1}SC:S),R,0,0,[r5]
+S:Llcduwrnum16.lcd_writenum16$d$1$50({1}SC:U),B,1,3
+S:Llcduwrnum16.lcd_writenum16$cnt$1$50({1}SC:U),R,0,0,[r4]
+S:Llcduwrnum16.lcd_writenum16$flags$1$50({1}SC:U),R,0,0,[r3]
+S:Llcduwrnum16.lcd_writenum16$nrdig$1$50({1}SC:U),R,0,0,[r2]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrnum32
+
+;!FILE libmflarge/lcduwrnum32.asm
+XH3
+H 1A areas 116 global symbols
+M lcduwrnum32
+O -mmcs51 --model-large
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Llcduwrnum32.lcd_writenum32$flags$1$50 Def000003
+S Llcduwrnum32.lcd_writenum32$d$1$50 Def000001
+S Llcduwrnum32.lcd_writenum32$cnt$1$50 Def000002
+S Llcduwrnum32.lcd_writenum32$ch$1$50 Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 6 flags 40 addr 0
+S Llcduwrnum32.lcd_writenum32$nrdig1$1$49 Def000000
+S _lcd_writenum32_PARM_2 Def000000
+S _lcd_writenum32_PARM_3 Def000001
+S Llcduwrnum32.lcd_writenum32$flags1$1$49 Def000001
+S Llcduwrnum32.lcd_writenum32$val$1$49 Def000002
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 17F flags 20 addr 0
+S C$lcduwrnum32.c$8$0$0 Def000000
+S G$lcd_writenum32$0$0 Def000000
+S _lcd_writenum32 Def000000
+S XG$lcd_writenum32$0$0 Def00017E
+S A$lcduwrnum32$210 Def000054
+S A$lcduwrnum32$201 Def000049
+S A$lcduwrnum32$310 Def0000B2
+S A$lcduwrnum32$220 Def00005C
+S A$lcduwrnum32$211 Def000055
+S A$lcduwrnum32$202 Def00004C
+S A$lcduwrnum32$401 Def00012B
+S A$lcduwrnum32$320 Def0000BC
+S A$lcduwrnum32$311 Def0000B3
+S A$lcduwrnum32$302 Def0000AB
+S A$lcduwrnum32$230 Def00006E
+S A$lcduwrnum32$221 Def00005F
+S A$lcduwrnum32$212 Def000056
+S A$lcduwrnum32$203 Def00004D
+S C$lcduwrnum32.c$22$1$50 Def000082
+S A$lcduwrnum32$420 Def00013A
+S A$lcduwrnum32$330 Def0000CF
+S A$lcduwrnum32$321 Def0000BD
+S A$lcduwrnum32$312 Def0000B4
+S A$lcduwrnum32$240 Def00007B
+S A$lcduwrnum32$231 Def00006F
+S A$lcduwrnum32$213 Def000057
+S A$lcduwrnum32$204 Def00004E
+S A$lcduwrnum32$150 Def00000C
+S C$lcduwrnum32.c$32$1$50 Def0000A1
+S C$lcduwrnum32.c$23$1$50 Def000089
+S C$lcduwrnum32.c$20$2$52 Def00007F
+S A$lcduwrnum32$412 Def000133
+S A$lcduwrnum32$340 Def0000DD
+S A$lcduwrnum32$331 Def0000D1
+S A$lcduwrnum32$322 Def0000BF
+S A$lcduwrnum32$313 Def0000B5
+S A$lcduwrnum32$250 Def000084
+S A$lcduwrnum32$241 Def00007D
+S A$lcduwrnum32$232 Def000071
+S A$lcduwrnum32$214 Def000058
+S A$lcduwrnum32$205 Def00004F
+S A$lcduwrnum32$151 Def00000D
+S C$lcduwrnum32.c$33$1$50 Def0000A4
+S C$lcduwrnum32.c$24$1$50 Def00008A
+S A$lcduwrnum32$440 Def000151
+S A$lcduwrnum32$413 Def000135
+S A$lcduwrnum32$404 Def00012C
+S A$lcduwrnum32$350 Def0000E9
+S A$lcduwrnum32$341 Def0000DE
+S A$lcduwrnum32$332 Def0000D2
+S A$lcduwrnum32$323 Def0000C1
+S A$lcduwrnum32$314 Def0000B6
+S A$lcduwrnum32$260 Def00008C
+S A$lcduwrnum32$251 Def000086
+S A$lcduwrnum32$233 Def000072
+S A$lcduwrnum32$215 Def000059
+S A$lcduwrnum32$206 Def000050
+S A$lcduwrnum32$161 Def000015
+S A$lcduwrnum32$152 Def00000E
+S A$lcduwrnum32$143 Def000000
+S C$lcduwrnum32.c$70$1$50 Def00017E
+S C$lcduwrnum32.c$34$1$50 Def0000A9
+S C$lcduwrnum32.c$30$2$53 Def0000A0
+S C$lcduwrnum32.c$16$1$50 Def000026
+S A$lcduwrnum32$450 Def000163
+S A$lcduwrnum32$441 Def000153
+S A$lcduwrnum32$432 Def00014A
+S A$lcduwrnum32$423 Def00013D
+S A$lcduwrnum32$360 Def0000F5
+S A$lcduwrnum32$342 Def0000DF
+S A$lcduwrnum32$333 Def0000D4
+S A$lcduwrnum32$324 Def0000C3
+S A$lcduwrnum32$315 Def0000B7
+S A$lcduwrnum32$306 Def0000AD
+S A$lcduwrnum32$252 Def000087
+S A$lcduwrnum32$234 Def000073
+S A$lcduwrnum32$225 Def000061
+S A$lcduwrnum32$216 Def00005A
+S A$lcduwrnum32$207 Def000051
+S A$lcduwrnum32$180 Def00002D
+S A$lcduwrnum32$153 Def00000F
+S A$lcduwrnum32$144 Def000002
+S C$lcduwrnum32.c$35$1$50 Def0000AB
+S A$lcduwrnum32$451 Def000166
+S A$lcduwrnum32$442 Def000156
+S A$lcduwrnum32$424 Def00013F
+S A$lcduwrnum32$352 Def0000EB
+S A$lcduwrnum32$343 Def0000E0
+S A$lcduwrnum32$334 Def0000D7
+S A$lcduwrnum32$325 Def0000C5
+S A$lcduwrnum32$316 Def0000B8
+S A$lcduwrnum32$235 Def000075
+S A$lcduwrnum32$226 Def000063
+S A$lcduwrnum32$217 Def00005B
+S A$lcduwrnum32$208 Def000052
+S A$lcduwrnum32$190 Def000039
+S A$lcduwrnum32$181 Def000030
+S A$lcduwrnum32$172 Def000021
+S A$lcduwrnum32$154 Def000010
+S A$lcduwrnum32$145 Def000004
+S A$lcduwrnum32$416 Def000138
+S A$lcduwrnum32$380 Def00010A
+S A$lcduwrnum32$353 Def0000ED
+S A$lcduwrnum32$344 Def0000E1
+S A$lcduwrnum32$335 Def0000D8
+S A$lcduwrnum32$326 Def0000C7
+S A$lcduwrnum32$317 Def0000B9
+S A$lcduwrnum32$290 Def0000A1
+S A$lcduwrnum32$281 Def00009B
+S A$lcduwrnum32$272 Def000095
+S A$lcduwrnum32$263 Def00008F
+S A$lcduwrnum32$245 Def00007F
+S A$lcduwrnum32$236 Def000076
+S A$lcduwrnum32$227 Def000066
+S A$lcduwrnum32$209 Def000053
+S A$lcduwrnum32$191 Def00003A
+S A$lcduwrnum32$182 Def000031
+S A$lcduwrnum32$173 Def000024
+S A$lcduwrnum32$164 Def000018
+S A$lcduwrnum32$155 Def000011
+S A$lcduwrnum32$146 Def000006
+S C$lcduwrnum32.c$19$1$50 Def000061
+S C$lcduwrnum32.c$17$2$51 Def000049
+S A$lcduwrnum32$462 Def000174
+S A$lcduwrnum32$453 Def000168
+S A$lcduwrnum32$408 Def00012E
+S A$lcduwrnum32$390 Def00011D
+S A$lcduwrnum32$381 Def00010D
+S A$lcduwrnum32$372 Def000102
+S A$lcduwrnum32$336 Def0000D9
+S A$lcduwrnum32$327 Def0000C8
+S A$lcduwrnum32$318 Def0000BA
+S A$lcduwrnum32$309 Def0000AF
+S A$lcduwrnum32$282 Def00009C
+S A$lcduwrnum32$273 Def000096
+S A$lcduwrnum32$264 Def000090
+S A$lcduwrnum32$255 Def000089
+S A$lcduwrnum32$237 Def000077
+S A$lcduwrnum32$228 Def000068
+S A$lcduwrnum32$192 Def00003B
+S A$lcduwrnum32$183 Def000032
+S A$lcduwrnum32$174 Def000025
+S A$lcduwrnum32$156 Def000012
+S A$lcduwrnum32$147 Def000007
+S C$lcduwrnum32.c$25$2$53 Def00008F
+S C$lcduwrnum32.c$18$2$51 Def00005C
+S A$lcduwrnum32$445 Def000159
+S A$lcduwrnum32$436 Def00014B
+S A$lcduwrnum32$427 Def000141
+S A$lcduwrnum32$409 Def000130
+S A$lcduwrnum32$364 Def0000F8
+S A$lcduwrnum32$337 Def0000DA
+S A$lcduwrnum32$328 Def0000CB
+S A$lcduwrnum32$319 Def0000BB
+S A$lcduwrnum32$283 Def00009E
+S A$lcduwrnum32$274 Def000098
+S A$lcduwrnum32$265 Def000092
+S A$lcduwrnum32$238 Def000079
+S A$lcduwrnum32$229 Def00006B
+S A$lcduwrnum32$193 Def00003D
+S A$lcduwrnum32$184 Def000033
+S A$lcduwrnum32$157 Def000013
+S A$lcduwrnum32$148 Def00000A
+S C$lcduwrnum32.c$60$4$62 Def00014A
+S C$lcduwrnum32.c$41$3$55 Def0000F8
+S C$lcduwrnum32.c$26$2$53 Def000094
+S C$lcduwrnum32.c$10$1$0 Def000015
+S A$lcduwrnum32$473 Def00017C
+S A$lcduwrnum32$446 Def00015B
+S A$lcduwrnum32$437 Def00014D
+S A$lcduwrnum32$428 Def000144
+S A$lcduwrnum32$392 Def00011F
+S A$lcduwrnum32$365 Def0000FA
+S A$lcduwrnum32$356 Def0000F0
+S A$lcduwrnum32$347 Def0000E2
+S A$lcduwrnum32$338 Def0000DB
+S A$lcduwrnum32$329 Def0000CD
+S A$lcduwrnum32$293 Def0000A4
+S A$lcduwrnum32$239 Def00007A
+S A$lcduwrnum32$194 Def00003F
+S A$lcduwrnum32$185 Def000034
+S A$lcduwrnum32$167 Def00001B
+S A$lcduwrnum32$158 Def000014
+S A$lcduwrnum32$149 Def00000B
+S C$lcduwrnum32.c$27$2$53 Def000095
+S A$lcduwrnum32$447 Def00015E
+S A$lcduwrnum32$438 Def00014F
+S A$lcduwrnum32$429 Def000147
+S A$lcduwrnum32$384 Def000110
+S A$lcduwrnum32$375 Def000104
+S A$lcduwrnum32$357 Def0000F1
+S A$lcduwrnum32$348 Def0000E4
+S A$lcduwrnum32$339 Def0000DC
+S A$lcduwrnum32$294 Def0000A5
+S A$lcduwrnum32$249 Def000082
+S A$lcduwrnum32$195 Def000041
+S A$lcduwrnum32$186 Def000035
+S A$lcduwrnum32$177 Def000026
+S A$lcduwrnum32$168 Def00001E
+S C$lcduwrnum32.c$68$1$50 Def000175
+S C$lcduwrnum32.c$63$2$54 Def00014B
+S C$lcduwrnum32.c$55$3$61 Def000133
+S C$lcduwrnum32.c$54$2$54 Def00012E
+S C$lcduwrnum32.c$36$2$54 Def0000AD
+S C$lcduwrnum32.c$28$2$53 Def00009A
+S C$lcduwrnum32.c$12$1$0 Def000018
+S A$lcduwrnum32$466 Def000175
+S A$lcduwrnum32$457 Def00016B
+S A$lcduwrnum32$448 Def000161
+S A$lcduwrnum32$439 Def000150
+S A$lcduwrnum32$385 Def000112
+S A$lcduwrnum32$358 Def0000F2
+S A$lcduwrnum32$349 Def0000E6
+S A$lcduwrnum32$295 Def0000A7
+S A$lcduwrnum32$286 Def0000A0
+S A$lcduwrnum32$277 Def00009A
+S A$lcduwrnum32$268 Def000094
+S A$lcduwrnum32$259 Def00008A
+S A$lcduwrnum32$196 Def000043
+S A$lcduwrnum32$187 Def000036
+S A$lcduwrnum32$178 Def000028
+S A$lcduwrnum32$169 Def00001F
+S C$lcduwrnum32.c$69$1$50 Def00017C
+S C$lcduwrnum32.c$64$2$54 Def000159
+S C$lcduwrnum32.c$56$3$61 Def000138
+S C$lcduwrnum32.c$51$4$56 Def00012C
+S C$lcduwrnum32.c$42$4$56 Def0000FD
+S C$lcduwrnum32.c$37$2$54 Def0000AF
+S C$lcduwrnum32.c$29$2$53 Def00009B
+S C$lcduwrnum32.c$13$1$0 Def00001B
+S A$lcduwrnum32$476 Def00017E
+S A$lcduwrnum32$467 Def000177
+S A$lcduwrnum32$458 Def00016E
+S A$lcduwrnum32$386 Def000115
+S A$lcduwrnum32$368 Def0000FD
+S A$lcduwrnum32$359 Def0000F3
+S A$lcduwrnum32$197 Def000044
+S A$lcduwrnum32$188 Def000037
+S A$lcduwrnum32$179 Def00002B
+S C$lcduwrnum32.c$57$3$61 Def00013A
+S C$lcduwrnum32.c$38$2$54 Def0000E2
+S C$lcduwrnum32.c$14$1$0 Def000021
+S A$lcduwrnum32$459 Def000171
+S A$lcduwrnum32$396 Def000122
+S A$lcduwrnum32$387 Def000118
+S A$lcduwrnum32$369 Def0000FF
+S A$lcduwrnum32$198 Def000046
+S A$lcduwrnum32$189 Def000038
+S C$lcduwrnum32.c$58$3$61 Def00013D
+S A$lcduwrnum32$469 Def000179
+S A$lcduwrnum32$397 Def000125
+S A$lcduwrnum32$379 Def000107
+S A$lcduwrnum32$298 Def0000A9
+S C$lcduwrnum32.c$43$5$57 Def000102
+S A$lcduwrnum32$398 Def000128
+S A$lcduwrnum32$389 Def00011A
+S C$lcduwrnum32.c$65$3$65 Def00016B
+S C$lcduwrnum32.c$46$4$56 Def000107
+S C$lcduwrnum32.c$44$5$57 Def000104
+S C$lcduwrnum32.c$39$3$55 Def0000F0
+S C$lcduwrnum32.c$66$3$65 Def000174
+S C$lcduwrnum32.c$47$4$56 Def000110
+S C$lcduwrnum32.c$59$5$63 Def000141
+S C$lcduwrnum32.c$48$5$59 Def000122
+S C$lcduwrnum32.c$49$5$59 Def00012B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
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+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 02 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 75 00 00 00 00
+R 00 00 00 16 F1 21 0C 00 05
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+R 00 00 00 16 F1 21 04 00 05 00 09 00 0A
+T 00 00 20 00 00 03 90 00 00 E0 FC E5
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+T 00 00 61
+R 00 00 00 16
+T 00 00 61 E5 00 00 03 20 E2 19 E5 00 00 03 30 E1
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 00 6A 17 90 00 02 E0 F5 F0 A3 E0 42 F0 A3 E0
+R 00 00 00 16 00 05 00 0A
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+R 00 00 00 16 F1 01 09 00 05
+T 00 00 C3 8B 83 8D F0 EE 12 00 00 AA 82 AB 83 AD
+R 00 00 00 16 02 09 00 02
+T 00 00 D0 F0 FE 15 81 90 00 02 EA F0 EB A3 F0 ED
+R 00 00 00 16 00 08 00 0A
+T 00 00 DD A3 F0 EE A3 F0 E5 00 00 01 70 48 BF 01
+R 00 00 00 16 F1 21 09 00 05
+T 00 00 E8 02 80 43
+R 00 00 00 16
+T 00 00 EB
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+R 00 00 00 16 F1 21 04 00 05
+T 00 00 F6 01 75
+R 00 00 00 16 00 03 00 16
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+T 00 00 F8 E5 00 00 03 20 E3 31 E5 00 00 03 20 E6
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 01 01 05 8F 04 43 00 00 03 40
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+T 00 01 07 75 82 20 12 00 00 12 00 00 E5
+R 00 00 00 16 02 07 00 03 02 0A 00 00
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+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 01 2E
+R 00 00 00 16
+T 00 01 2E E5 00 00 03 20 E7 18 E5 00 00 03 20 E6
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 01 37 02 8F 04
+R 00 00 00 16
+T 00 01 3A
+R 00 00 00 16
+T 00 01 3A 43 00 00 03 C8 E5 00 00 00 60 0A 85
+R 00 00 00 16 F1 21 04 00 05 F1 21 09 00 05
+T 00 01 42 00 00 00 82 12 00 00 12
+R 00 00 00 16 F1 21 03 00 05 02 08 00 03
+T 00 01 48 00 00 0C
+R 00 00 00 16 02 03 00 00
+T 00 01 4B
+R 00 00 00 16
+T 00 01 4B AE 00 00 01 74 30 2E FE F5 82 12 00 00
+R 00 00 00 16 F1 21 04 00 05 02 0E 00 03
+T 00 01 56 12 00 00 E5 00 00 03 30 E4 17 BF 04 02
+R 00 00 00 16 02 04 00 00 F1 21 07 00 05
+T 00 01 61 80 08
+R 00 00 00 16
+T 00 01 63
+R 00 00 00 16
+T 00 01 63 BF 07 02 80 03
+R 00 00 00 16
+T 00 01 68
+R 00 00 00 16
+T 00 01 68 BF 0A 0A
+R 00 00 00 16
+T 00 01 6B
+R 00 00 00 16
+T 00 01 6B 75 82 27 12 00 00 12 00 00 0C
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 01 75
+R 00 00 00 16
+T 00 01 75 DF 02 80 03
+R 00 00 00 16
+T 00 01 79
+R 00 00 00 16
+T 00 01 79 02 00 AD
+R 00 00 00 16 00 04 00 16
+T 00 01 7C
+R 00 00 00 16
+T 00 01 7C 8C 82 22
+R 00 00 00 16
+
+
+M:lcduwrnum32
+F:G$lcd_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$ch$1$50({1}SC:S),E,0,0
+S:Llcduwrnum32.lcd_writenum32$d$1$50({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$cnt$1$50({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$flags$1$50({1}SC:U),E,0,0
+S:Llcduwrnum32.lcd_writenum32$nrdig$1$50({1}SC:U),R,0,0,[r4]
+S:Llcduwrnum32.lcd_writenum32$nrdig1$1$49({1}SC:U),F,0,0
+S:Llcduwrnum32.lcd_writenum32$flags1$1$49({1}SC:U),F,0,0
+S:Llcduwrnum32.lcd_writenum32$val$1$49({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrhex16
+
+;!FILE libmflarge/lcduwrhex16.asm
+XH3
+H 1A areas F6 global symbols
+M lcduwrhex16
+O -mmcs51 --model-large
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _bp Ref000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 154 flags 20 addr 0
+S _lcd_writehex16 Def000000
+S XG$lcd_writehex16$0$0 Def000153
+S A$lcduwrhex16$300 Def0000C7
+S A$lcduwrhex16$120 Def000002
+S A$lcduwrhex16$400 Def000134
+S A$lcduwrhex16$301 Def0000C9
+S A$lcduwrhex16$220 Def000074
+S A$lcduwrhex16$211 Def00006E
+S A$lcduwrhex16$202 Def000063
+S A$lcduwrhex16$121 Def000005
+S C$lcduwrhex16.c$30$1$50 Def000081
+S A$lcduwrhex16$410 Def000144
+S A$lcduwrhex16$401 Def000135
+S A$lcduwrhex16$311 Def0000D3
+S A$lcduwrhex16$302 Def0000CA
+S A$lcduwrhex16$221 Def000076
+S A$lcduwrhex16$203 Def000065
+S A$lcduwrhex16$122 Def000007
+S C$lcduwrhex16.c$31$1$50 Def000083
+S C$lcduwrhex16.c$22$1$50 Def000063
+S A$lcduwrhex16$402 Def000138
+S A$lcduwrhex16$321 Def0000DC
+S A$lcduwrhex16$312 Def0000D4
+S A$lcduwrhex16$240 Def000083
+S A$lcduwrhex16$231 Def00007C
+S A$lcduwrhex16$204 Def000067
+S A$lcduwrhex16$150 Def000028
+S A$lcduwrhex16$141 Def00001B
+S A$lcduwrhex16$132 Def000012
+S A$lcduwrhex16$123 Def000009
+S C$lcduwrhex16.c$23$1$50 Def00006E
+S C$lcduwrhex16.c$20$2$52 Def00005C
+S A$lcduwrhex16$421 Def00014C
+S A$lcduwrhex16$322 Def0000DD
+S A$lcduwrhex16$250 Def00008E
+S A$lcduwrhex16$232 Def00007D
+S A$lcduwrhex16$205 Def000068
+S A$lcduwrhex16$151 Def00002A
+S A$lcduwrhex16$142 Def00001D
+S C$lcduwrhex16.c$24$1$50 Def00006F
+S A$lcduwrhex16$422 Def00014E
+S A$lcduwrhex16$341 Def0000F2
+S A$lcduwrhex16$332 Def0000E6
+S A$lcduwrhex16$260 Def00009B
+S A$lcduwrhex16$251 Def00008F
+S A$lcduwrhex16$233 Def00007F
+S A$lcduwrhex16$224 Def000078
+S A$lcduwrhex16$215 Def00006F
+S A$lcduwrhex16$206 Def000069
+S A$lcduwrhex16$170 Def000041
+S A$lcduwrhex16$152 Def00002B
+S A$lcduwrhex16$143 Def00001F
+S C$lcduwrhex16.c$70$1$50 Def000145
+S C$lcduwrhex16.c$16$1$50 Def000022
+S A$lcduwrhex16$423 Def000151
+S A$lcduwrhex16$414 Def000145
+S A$lcduwrhex16$405 Def00013B
+S A$lcduwrhex16$351 Def000102
+S A$lcduwrhex16$342 Def0000F3
+S A$lcduwrhex16$315 Def0000D7
+S A$lcduwrhex16$306 Def0000CB
+S A$lcduwrhex16$270 Def0000A9
+S A$lcduwrhex16$261 Def00009D
+S A$lcduwrhex16$252 Def000090
+S A$lcduwrhex16$216 Def000070
+S A$lcduwrhex16$207 Def00006B
+S A$lcduwrhex16$171 Def000042
+S A$lcduwrhex16$162 Def000038
+S A$lcduwrhex16$153 Def00002D
+S A$lcduwrhex16$144 Def000020
+S A$lcduwrhex16$135 Def000014
+S A$lcduwrhex16$126 Def00000B
+S C$lcduwrhex16.c$71$1$50 Def00014C
+S A$lcduwrhex16$415 Def000147
+S A$lcduwrhex16$406 Def00013E
+S A$lcduwrhex16$370 Def00010F
+S A$lcduwrhex16$343 Def0000F6
+S A$lcduwrhex16$325 Def0000E0
+S A$lcduwrhex16$316 Def0000D8
+S A$lcduwrhex16$307 Def0000CC
+S A$lcduwrhex16$271 Def0000AA
+S A$lcduwrhex16$262 Def00009F
+S A$lcduwrhex16$253 Def000092
+S A$lcduwrhex16$244 Def000085
+S A$lcduwrhex16$208 Def00006C
+S A$lcduwrhex16$190 Def000059
+S A$lcduwrhex16$163 Def00003A
+S A$lcduwrhex16$154 Def00002E
+S A$lcduwrhex16$136 Def000016
+S A$lcduwrhex16$127 Def00000D
+S C$lcduwrhex16.c$72$1$50 Def000153
+S C$lcduwrhex16.c$40$2$54 Def0000CB
+S A$lcduwrhex16$407 Def000141
+S A$lcduwrhex16$380 Def00011A
+S A$lcduwrhex16$362 Def000109
+S A$lcduwrhex16$326 Def0000E1
+S A$lcduwrhex16$317 Def0000D9
+S A$lcduwrhex16$308 Def0000CE
+S A$lcduwrhex16$272 Def0000AB
+S A$lcduwrhex16$263 Def0000A0
+S A$lcduwrhex16$254 Def000093
+S A$lcduwrhex16$245 Def000087
+S A$lcduwrhex16$236 Def000081
+S A$lcduwrhex16$191 Def00005A
+S A$lcduwrhex16$182 Def00004C
+S A$lcduwrhex16$164 Def00003B
+S A$lcduwrhex16$155 Def000030
+S A$lcduwrhex16$137 Def000018
+S A$lcduwrhex16$128 Def00000F
+S A$lcduwrhex16$119 Def000000
+S C$lcduwrhex16.c$32$2$54 Def000085
+S C$lcduwrhex16.c$28$1$50 Def000079
+S C$lcduwrhex16.c$19$1$50 Def00004C
+S C$lcduwrhex16.c$17$2$51 Def000038
+S A$lcduwrhex16$426 Def000153
+S A$lcduwrhex16$417 Def000149
+S A$lcduwrhex16$381 Def00011C
+S A$lcduwrhex16$363 Def00010A
+S A$lcduwrhex16$354 Def000103
+S A$lcduwrhex16$336 Def0000E9
+S A$lcduwrhex16$318 Def0000DA
+S A$lcduwrhex16$309 Def0000D1
+S A$lcduwrhex16$291 Def0000BD
+S A$lcduwrhex16$282 Def0000B4
+S A$lcduwrhex16$273 Def0000AC
+S A$lcduwrhex16$264 Def0000A2
+S A$lcduwrhex16$255 Def000094
+S A$lcduwrhex16$246 Def000089
+S A$lcduwrhex16$228 Def000079
+S A$lcduwrhex16$219 Def000073
+S A$lcduwrhex16$183 Def00004D
+S A$lcduwrhex16$174 Def000043
+S A$lcduwrhex16$165 Def00003C
+S A$lcduwrhex16$156 Def000031
+S A$lcduwrhex16$147 Def000022
+S A$lcduwrhex16$138 Def000019
+S A$lcduwrhex16$129 Def000010
+S C$lcduwrhex16.c$60$3$62 Def000112
+S C$lcduwrhex16.c$51$5$60 Def000102
+S C$lcduwrhex16.c$33$2$54 Def0000B1
+S C$lcduwrhex16.c$29$1$50 Def00007C
+S C$lcduwrhex16.c$25$2$53 Def000073
+S C$lcduwrhex16.c$18$2$51 Def000043
+S A$lcduwrhex16$382 Def00011E
+S A$lcduwrhex16$373 Def000112
+S A$lcduwrhex16$346 Def0000F9
+S A$lcduwrhex16$337 Def0000EC
+S A$lcduwrhex16$292 Def0000BF
+S A$lcduwrhex16$274 Def0000AD
+S A$lcduwrhex16$265 Def0000A3
+S A$lcduwrhex16$256 Def000095
+S A$lcduwrhex16$247 Def00008A
+S A$lcduwrhex16$184 Def000050
+S A$lcduwrhex16$175 Def000045
+S A$lcduwrhex16$166 Def00003D
+S A$lcduwrhex16$157 Def000032
+S A$lcduwrhex16$148 Def000023
+S C$lcduwrhex16.c$50$6$61 Def0000F9
+S C$lcduwrhex16.c$34$2$54 Def0000B4
+S C$lcduwrhex16.c$26$2$53 Def000078
+S C$lcduwrhex16.c$10$1$0 Def00000B
+S A$lcduwrhex16$392 Def000128
+S A$lcduwrhex16$383 Def00011F
+S A$lcduwrhex16$374 Def000114
+S A$lcduwrhex16$347 Def0000FC
+S A$lcduwrhex16$338 Def0000EF
+S A$lcduwrhex16$329 Def0000E4
+S A$lcduwrhex16$293 Def0000C1
+S A$lcduwrhex16$284 Def0000B7
+S A$lcduwrhex16$266 Def0000A5
+S A$lcduwrhex16$257 Def000097
+S A$lcduwrhex16$248 Def00008D
+S A$lcduwrhex16$185 Def000051
+S A$lcduwrhex16$176 Def000047
+S A$lcduwrhex16$167 Def00003E
+S A$lcduwrhex16$158 Def000033
+S A$lcduwrhex16$149 Def000026
+S C$lcduwrhex16.c$41$3$56 Def0000D7
+S A$lcduwrhex16$393 Def00012A
+S A$lcduwrhex16$384 Def000121
+S A$lcduwrhex16$375 Def000116
+S A$lcduwrhex16$366 Def00010D
+S A$lcduwrhex16$348 Def0000FF
+S A$lcduwrhex16$294 Def0000C2
+S A$lcduwrhex16$276 Def0000AE
+S A$lcduwrhex16$258 Def000098
+S A$lcduwrhex16$195 Def00005C
+S A$lcduwrhex16$186 Def000054
+S A$lcduwrhex16$177 Def000048
+S A$lcduwrhex16$168 Def00003F
+S A$lcduwrhex16$159 Def000035
+S C$lcduwrhex16.c$12$1$0 Def000012
+S A$lcduwrhex16$394 Def00012B
+S A$lcduwrhex16$385 Def000124
+S A$lcduwrhex16$376 Def000117
+S A$lcduwrhex16$358 Def000105
+S A$lcduwrhex16$295 Def0000C3
+S A$lcduwrhex16$268 Def0000A7
+S A$lcduwrhex16$259 Def000099
+S A$lcduwrhex16$196 Def00005E
+S A$lcduwrhex16$187 Def000056
+S A$lcduwrhex16$178 Def00004A
+S A$lcduwrhex16$169 Def000040
+S C$lcduwrhex16.c$62$4$63 Def000127
+S C$lcduwrhex16.c$43$3$56 Def0000DC
+S C$lcduwrhex16.c$35$3$55 Def0000B9
+S C$lcduwrhex16.c$13$1$0 Def000014
+S A$lcduwrhex16$395 Def00012C
+S A$lcduwrhex16$377 Def000118
+S A$lcduwrhex16$359 Def000106
+S A$lcduwrhex16$287 Def0000B9
+S A$lcduwrhex16$269 Def0000A8
+S A$lcduwrhex16$197 Def000060
+S A$lcduwrhex16$188 Def000057
+S C$lcduwrhex16.c$65$2$54 Def000128
+S C$lcduwrhex16.c$61$5$64 Def00011A
+S C$lcduwrhex16.c$56$2$54 Def000105
+S C$lcduwrhex16.c$36$3$55 Def0000BD
+S C$lcduwrhex16.c$14$1$0 Def00001B
+S A$lcduwrhex16$396 Def00012E
+S A$lcduwrhex16$288 Def0000BA
+S A$lcduwrhex16$279 Def0000B1
+S A$lcduwrhex16$198 Def000061
+S A$lcduwrhex16$189 Def000058
+S C$lcduwrhex16.c$66$2$54 Def000134
+S C$lcduwrhex16.c$57$3$62 Def000109
+S A$lcduwrhex16$397 Def000131
+S A$lcduwrhex16$388 Def000127
+S C$lcduwrhex16.c$58$3$62 Def00010D
+S C$lcduwrhex16.c$53$4$57 Def000103
+S C$lcduwrhex16.c$44$4$57 Def0000E0
+S C$lcduwrhex16.c$38$3$55 Def0000C5
+S A$lcduwrhex16$299 Def0000C5
+S C$lcduwrhex16.c$59$3$62 Def00010F
+S C$lcduwrhex16.c$45$5$58 Def0000E4
+S C$lcduwrhex16.c$48$4$57 Def0000E9
+S C$lcduwrhex16.c$46$5$58 Def0000E6
+S C$lcduwrhex16.c$68$3$66 Def000144
+S C$lcduwrhex16.c$49$4$57 Def0000F2
+S C$lcduwrhex16.c$67$4$67 Def00013B
+S C$lcduwrhex16.c$8$0$0 Def000000
+S G$lcd_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 C0 82 C0 83
+R 00 00 00 16 F1 23 04 00 02 F1 23 09 00 02
+T 00 00 09 05 81 E5 00 00 00 24 03 F8 76 00 7C 04
+R 00 00 00 16 F1 23 06 00 02
+T 00 00 14 E5 00 00 00 24 FC F8 86 03 E5 00 00 00
+R 00 00 00 16 F1 23 04 00 02 F1 23 0D 00 02
+T 00 00 1D 24 FD F8 86 02 EB 30 E0 26 C0 04 A8
+R 00 00 00 16
+T 00 00 29 00 00 00 08 86 04 08 86 05 E4 FE FF D0
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 34 04 30 E7 14 A8 00 00 00 08 C3 E4 96 F6
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 3F 08 E4 96 F6 E5 00 00 00 24 03 F8 76 2D
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 4A 80 17
+R 00 00 00 16
+T 00 00 4C
+R 00 00 00 16
+T 00 00 4C EB 20 E2 0C EB 30 E1 0F A8 00 00 00 08
+R 00 00 00 16 F1 23 0C 00 02
+T 00 00 57 E6 08 46 60 07
+R 00 00 00 16
+T 00 00 5C
+R 00 00 00 16
+T 00 00 5C E5 00 00 00 24 03 F8 76 2B
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 E5 00 00 00 24 03 F8 E6 60 04 EA 60 01
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 6E 1A
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F EB 30 E4 06 EA 24 FB 50 01 1A
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 53 03 3F EA 24 FB 50 02 8A 04
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 8C 07
+R 00 00 00 16
+T 00 00 85
+R 00 00 00 16
+T 00 00 85 8F 05 7E 00 1D BD FF 01 1E
+R 00 00 00 16
+T 00 00 8E
+R 00 00 00 16
+T 00 00 8E EE CD 25 E0 CD 33 CD 25 E0 CD 33 8D F0
+R 00 00 00 16
+T 00 00 9B 05 F0 A8 00 00 00 08 86 05 08 86 06 80
+R 00 00 00 16 F1 23 06 00 02
+T 00 00 A6 07
+R 00 00 00 16
+T 00 00 A7
+R 00 00 00 16
+T 00 00 A7 C3 EE 13 FE ED 13 FD
+R 00 00 00 16
+T 00 00 AE
+R 00 00 00 16
+T 00 00 AE D5 F0 F6 53 05 0F BD 0A 00
+R 00 00 00 16
+T 00 00 B7
+R 00 00 00 16
+T 00 00 B7 40 12 EB 30 E5 08 8D 06 74 27 2E FD 80
+R 00 00 00 16
+T 00 00 C4 06
+R 00 00 00 16
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 8D 06 74 07 2E FD
+R 00 00 00 16
+T 00 00 CB
+R 00 00 00 16
+T 00 00 CB ED 70 37 BF 01 02 80 32
+R 00 00 00 16
+T 00 00 D3
+R 00 00 00 16
+T 00 00 D3 EB 20 E7 2E C3 EA 9F 40 69 EB 20 E3 25
+R 00 00 00 16
+T 00 00 E0 EB 20 E6 05 8F 02 43 03 40
+R 00 00 00 16
+T 00 00 E9
+R 00 00 00 16
+T 00 00 E9 75 82 20 12 00 00 12 00 00 EB 30 E4 4F
+R 00 00 00 16 02 07 00 03 02 0A 00 00
+T 00 00 F6 BF 05 4C 75 82 20 12 00 00 12 00 00 0A
+R 00 00 00 16 02 0A 00 03 02 0D 00 00
+T 00 01 03 80 40
+R 00 00 00 16
+T 00 01 05
+R 00 00 00 16
+T 00 01 05 EB 20 E7 1F EB 20 E6 02 8F 02
+R 00 00 00 16
+T 00 01 0F
+R 00 00 00 16
+T 00 01 0F 43 03 C8 E5 00 00 00 24 03 F8 E6 60 0E
+R 00 00 00 16 F1 23 07 00 02
+T 00 01 1A E5 00 00 00 24 03 F8 86 82 12 00 00 12
+R 00 00 00 16 F1 23 04 00 02 02 0D 00 03
+T 00 01 25 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 01 28
+R 00 00 00 16
+T 00 01 28 74 30 2D FD F5 82 12 00 00 12 00 00 EB
+R 00 00 00 16 02 0A 00 03 02 0D 00 00
+T 00 01 35 30 E4 0D BF 05 0A 75 82 27 12 00 00 12
+R 00 00 00 16 02 0D 00 03
+T 00 01 42 00 00 0A
+R 00 00 00 16 02 03 00 00
+T 00 01 45
+R 00 00 00 16
+T 00 01 45 DF 02 80 03
+R 00 00 00 16
+T 00 01 49
+R 00 00 00 16
+T 00 01 49 02 00 85
+R 00 00 00 16 00 04 00 16
+T 00 01 4C
+R 00 00 00 16
+T 00 01 4C 8A 82 85 00 00 00 81 D0 00 00 00 22
+R 00 00 00 16 F1 23 06 00 02 F1 23 0B 00 02
+
+
+M:lcduwrhex16
+F:G$lcd_writehex16$0$0({2}DF,SC:U),Z,0,3,0,0,0
+S:Llcduwrhex16.lcd_writehex16$nrdig1$1$49({1}SC:U),B,1,-3
+S:Llcduwrhex16.lcd_writehex16$flags1$1$49({1}SC:U),B,1,-4
+S:Llcduwrhex16.lcd_writehex16$val$1$49({2}SI:U),B,1,1
+S:Llcduwrhex16.lcd_writehex16$ch$1$50({1}SC:S),B,1,3
+S:Llcduwrhex16.lcd_writehex16$d$1$50({1}SC:U),R,0,0,[r5]
+S:Llcduwrhex16.lcd_writehex16$cnt$1$50({1}SC:U),R,0,0,[r4]
+S:Llcduwrhex16.lcd_writehex16$flags$1$50({1}SC:U),R,0,0,[r3]
+S:Llcduwrhex16.lcd_writehex16$nrdig$1$50({1}SC:U),R,0,0,[r2]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+lcduwrhex32
+
+;!FILE libmflarge/lcduwrhex32.asm
+XH3
+H 1A areas 125 global symbols
+M lcduwrhex32
+O -mmcs51 --model-large
+S _lcd_waitshort Ref000000
+S .__.ABS. Def000000
+S _lcd_writedata Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 5 flags 0 addr 0
+S Llcduwrhex32.lcd_writehex32$d$1$50 Def000001
+S Llcduwrhex32.lcd_writehex32$cnt$1$50 Def000002
+S Llcduwrhex32.lcd_writehex32$ch$1$50 Def000000
+S Llcduwrhex32.lcd_writehex32$flags$1$50 Def000003
+S Llcduwrhex32.lcd_writehex32$nrdig$1$50 Def000004
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 6 flags 40 addr 0
+S Llcduwrhex32.lcd_writehex32$flags1$1$49 Def000001
+S _lcd_writehex32_PARM_2 Def000000
+S _lcd_writehex32_PARM_3 Def000001
+S Llcduwrhex32.lcd_writehex32$val$1$49 Def000002
+S Llcduwrhex32.lcd_writehex32$nrdig1$1$49 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 195 flags 20 addr 0
+S _lcd_writehex32 Def000000
+S XG$lcd_writehex32$0$0 Def000194
+S A$lcduwrhex32$200 Def000046
+S A$lcduwrhex32$210 Def000052
+S A$lcduwrhex32$400 Def000129
+S A$lcduwrhex32$310 Def0000BC
+S A$lcduwrhex32$211 Def000053
+S C$lcduwrhex32.c$30$1$50 Def00009D
+S A$lcduwrhex32$410 Def000137
+S A$lcduwrhex32$320 Def0000CA
+S A$lcduwrhex32$311 Def0000BD
+S A$lcduwrhex32$302 Def0000B0
+S A$lcduwrhex32$230 Def000068
+S A$lcduwrhex32$212 Def000054
+S A$lcduwrhex32$203 Def000049
+S C$lcduwrhex32.c$31$1$50 Def00009F
+S C$lcduwrhex32.c$22$1$50 Def000082
+S A$lcduwrhex32$420 Def000148
+S A$lcduwrhex32$411 Def00013A
+S A$lcduwrhex32$330 Def0000D8
+S A$lcduwrhex32$321 Def0000CC
+S A$lcduwrhex32$312 Def0000BF
+S A$lcduwrhex32$303 Def0000B2
+S A$lcduwrhex32$240 Def000079
+S A$lcduwrhex32$231 Def00006B
+S A$lcduwrhex32$222 Def00005C
+S A$lcduwrhex32$213 Def000055
+S A$lcduwrhex32$204 Def00004C
+S A$lcduwrhex32$150 Def00000A
+S C$lcduwrhex32.c$32$1$50 Def0000B0
+S C$lcduwrhex32.c$23$1$50 Def000089
+S C$lcduwrhex32.c$20$2$52 Def00007F
+S A$lcduwrhex32$412 Def00013C
+S A$lcduwrhex32$340 Def0000E1
+S A$lcduwrhex32$331 Def0000D9
+S A$lcduwrhex32$322 Def0000CE
+S A$lcduwrhex32$313 Def0000C0
+S A$lcduwrhex32$304 Def0000B4
+S A$lcduwrhex32$241 Def00007A
+S A$lcduwrhex32$232 Def00006E
+S A$lcduwrhex32$223 Def00005F
+S A$lcduwrhex32$214 Def000056
+S A$lcduwrhex32$205 Def00004D
+S A$lcduwrhex32$160 Def000014
+S A$lcduwrhex32$151 Def00000B
+S C$lcduwrhex32.c$24$1$50 Def00008A
+S A$lcduwrhex32$431 Def000150
+S A$lcduwrhex32$404 Def00012C
+S A$lcduwrhex32$350 Def0000EE
+S A$lcduwrhex32$341 Def0000E4
+S A$lcduwrhex32$332 Def0000DA
+S A$lcduwrhex32$323 Def0000D0
+S A$lcduwrhex32$314 Def0000C1
+S A$lcduwrhex32$305 Def0000B6
+S A$lcduwrhex32$251 Def000082
+S A$lcduwrhex32$242 Def00007B
+S A$lcduwrhex32$233 Def00006F
+S A$lcduwrhex32$215 Def000057
+S A$lcduwrhex32$206 Def00004E
+S A$lcduwrhex32$170 Def00001E
+S A$lcduwrhex32$152 Def00000C
+S C$lcduwrhex32.c$70$1$50 Def00018A
+S C$lcduwrhex32.c$16$1$50 Def000026
+S A$lcduwrhex32$432 Def000152
+S A$lcduwrhex32$423 Def000149
+S A$lcduwrhex32$405 Def00012F
+S A$lcduwrhex32$360 Def0000FB
+S A$lcduwrhex32$351 Def0000F0
+S A$lcduwrhex32$333 Def0000DB
+S A$lcduwrhex32$324 Def0000D2
+S A$lcduwrhex32$315 Def0000C2
+S A$lcduwrhex32$306 Def0000B7
+S A$lcduwrhex32$270 Def000094
+S A$lcduwrhex32$261 Def00008A
+S A$lcduwrhex32$252 Def000084
+S A$lcduwrhex32$243 Def00007D
+S A$lcduwrhex32$234 Def000071
+S A$lcduwrhex32$216 Def000058
+S A$lcduwrhex32$207 Def00004F
+S A$lcduwrhex32$180 Def000028
+S A$lcduwrhex32$171 Def00001F
+S A$lcduwrhex32$153 Def00000D
+S C$lcduwrhex32.c$71$1$50 Def000192
+S A$lcduwrhex32$460 Def000170
+S A$lcduwrhex32$451 Def000167
+S A$lcduwrhex32$442 Def00015A
+S A$lcduwrhex32$415 Def00013F
+S A$lcduwrhex32$406 Def000132
+S A$lcduwrhex32$361 Def0000FC
+S A$lcduwrhex32$334 Def0000DC
+S A$lcduwrhex32$316 Def0000C4
+S A$lcduwrhex32$307 Def0000BA
+S A$lcduwrhex32$262 Def00008C
+S A$lcduwrhex32$253 Def000086
+S A$lcduwrhex32$235 Def000072
+S A$lcduwrhex32$217 Def000059
+S A$lcduwrhex32$208 Def000050
+S A$lcduwrhex32$190 Def000037
+S A$lcduwrhex32$181 Def00002B
+S A$lcduwrhex32$163 Def000015
+S A$lcduwrhex32$154 Def00000E
+S A$lcduwrhex32$145 Def000000
+S C$lcduwrhex32.c$72$1$50 Def000194
+S C$lcduwrhex32.c$40$2$54 Def000107
+S A$lcduwrhex32$470 Def000180
+S A$lcduwrhex32$461 Def000173
+S A$lcduwrhex32$443 Def00015C
+S A$lcduwrhex32$416 Def000142
+S A$lcduwrhex32$380 Def000114
+S A$lcduwrhex32$362 Def0000FE
+S A$lcduwrhex32$344 Def0000E6
+S A$lcduwrhex32$335 Def0000DD
+S A$lcduwrhex32$326 Def0000D4
+S A$lcduwrhex32$317 Def0000C5
+S A$lcduwrhex32$290 Def0000A5
+S A$lcduwrhex32$254 Def000087
+S A$lcduwrhex32$236 Def000073
+S A$lcduwrhex32$227 Def000061
+S A$lcduwrhex32$218 Def00005A
+S A$lcduwrhex32$209 Def000051
+S A$lcduwrhex32$191 Def000038
+S A$lcduwrhex32$182 Def00002D
+S A$lcduwrhex32$155 Def00000F
+S A$lcduwrhex32$146 Def000002
+S C$lcduwrhex32.c$28$1$50 Def000095
+S C$lcduwrhex32.c$19$1$50 Def000061
+S C$lcduwrhex32.c$17$2$51 Def000049
+S A$lcduwrhex32$480 Def00018D
+S A$lcduwrhex32$471 Def000183
+S A$lcduwrhex32$435 Def000155
+S A$lcduwrhex32$417 Def000145
+S A$lcduwrhex32$390 Def00011F
+S A$lcduwrhex32$354 Def0000F2
+S A$lcduwrhex32$336 Def0000DE
+S A$lcduwrhex32$327 Def0000D5
+S A$lcduwrhex32$318 Def0000C6
+S A$lcduwrhex32$309 Def0000BB
+S A$lcduwrhex32$291 Def0000A6
+S A$lcduwrhex32$282 Def00009D
+S A$lcduwrhex32$237 Def000075
+S A$lcduwrhex32$228 Def000063
+S A$lcduwrhex32$219 Def00005B
+S A$lcduwrhex32$192 Def000039
+S A$lcduwrhex32$183 Def000030
+S A$lcduwrhex32$174 Def000021
+S A$lcduwrhex32$156 Def000010
+S A$lcduwrhex32$147 Def000004
+S C$lcduwrhex32.c$60$3$62 Def00015A
+S C$lcduwrhex32.c$51$5$60 Def000148
+S C$lcduwrhex32.c$33$2$54 Def0000E6
+S C$lcduwrhex32.c$29$1$50 Def000098
+S C$lcduwrhex32.c$25$2$53 Def00008F
+S C$lcduwrhex32.c$18$2$51 Def00005C
+S A$lcduwrhex32$472 Def000186
+S A$lcduwrhex32$427 Def00014B
+S A$lcduwrhex32$409 Def000135
+S A$lcduwrhex32$373 Def000107
+S A$lcduwrhex32$355 Def0000F4
+S A$lcduwrhex32$337 Def0000DF
+S A$lcduwrhex32$328 Def0000D6
+S A$lcduwrhex32$319 Def0000C8
+S A$lcduwrhex32$292 Def0000A7
+S A$lcduwrhex32$274 Def000095
+S A$lcduwrhex32$265 Def00008F
+S A$lcduwrhex32$247 Def00007F
+S A$lcduwrhex32$238 Def000076
+S A$lcduwrhex32$229 Def000066
+S A$lcduwrhex32$193 Def00003A
+S A$lcduwrhex32$184 Def000031
+S A$lcduwrhex32$175 Def000024
+S A$lcduwrhex32$166 Def000018
+S A$lcduwrhex32$157 Def000011
+S A$lcduwrhex32$148 Def000006
+S C$lcduwrhex32.c$50$6$61 Def00013F
+S C$lcduwrhex32.c$34$2$54 Def0000E9
+S C$lcduwrhex32.c$26$2$53 Def000094
+S C$lcduwrhex32.c$10$1$0 Def000015
+S A$lcduwrhex32$482 Def00018F
+S A$lcduwrhex32$464 Def000176
+S A$lcduwrhex32$455 Def000168
+S A$lcduwrhex32$446 Def00015E
+S A$lcduwrhex32$428 Def00014D
+S A$lcduwrhex32$383 Def000117
+S A$lcduwrhex32$374 Def000109
+S A$lcduwrhex32$347 Def0000E9
+S A$lcduwrhex32$338 Def0000E0
+S A$lcduwrhex32$329 Def0000D7
+S A$lcduwrhex32$293 Def0000A8
+S A$lcduwrhex32$266 Def000090
+S A$lcduwrhex32$257 Def000089
+S A$lcduwrhex32$239 Def000077
+S A$lcduwrhex32$194 Def00003B
+S A$lcduwrhex32$185 Def000032
+S A$lcduwrhex32$176 Def000025
+S A$lcduwrhex32$158 Def000012
+S A$lcduwrhex32$149 Def000007
+S C$lcduwrhex32.c$41$3$56 Def000117
+S A$lcduwrhex32$465 Def000178
+S A$lcduwrhex32$456 Def00016A
+S A$lcduwrhex32$447 Def000161
+S A$lcduwrhex32$393 Def000122
+S A$lcduwrhex32$384 Def000118
+S A$lcduwrhex32$375 Def00010B
+S A$lcduwrhex32$366 Def000100
+S A$lcduwrhex32$348 Def0000EA
+S A$lcduwrhex32$294 Def0000A9
+S A$lcduwrhex32$267 Def000092
+S A$lcduwrhex32$195 Def00003D
+S A$lcduwrhex32$186 Def000033
+S A$lcduwrhex32$159 Def000013
+S C$lcduwrhex32.c$12$1$0 Def000018
+S A$lcduwrhex32$475 Def000189
+S A$lcduwrhex32$466 Def00017B
+S A$lcduwrhex32$457 Def00016C
+S A$lcduwrhex32$448 Def000164
+S A$lcduwrhex32$439 Def000157
+S A$lcduwrhex32$394 Def000124
+S A$lcduwrhex32$385 Def000119
+S A$lcduwrhex32$376 Def00010D
+S A$lcduwrhex32$367 Def000102
+S A$lcduwrhex32$358 Def0000F7
+S A$lcduwrhex32$349 Def0000EC
+S A$lcduwrhex32$295 Def0000AA
+S A$lcduwrhex32$286 Def00009F
+S A$lcduwrhex32$277 Def000098
+S A$lcduwrhex32$196 Def00003F
+S A$lcduwrhex32$187 Def000034
+S A$lcduwrhex32$169 Def00001B
+S C$lcduwrhex32.c$62$4$63 Def000167
+S C$lcduwrhex32.c$43$3$56 Def00011D
+S C$lcduwrhex32.c$35$3$55 Def0000F2
+S C$lcduwrhex32.c$13$1$0 Def00001B
+S A$lcduwrhex32$467 Def00017D
+S A$lcduwrhex32$458 Def00016D
+S A$lcduwrhex32$386 Def00011B
+S A$lcduwrhex32$377 Def000110
+S A$lcduwrhex32$368 Def000104
+S A$lcduwrhex32$359 Def0000F9
+S A$lcduwrhex32$296 Def0000AB
+S A$lcduwrhex32$287 Def0000A2
+S A$lcduwrhex32$278 Def000099
+S A$lcduwrhex32$197 Def000041
+S A$lcduwrhex32$188 Def000035
+S A$lcduwrhex32$179 Def000026
+S C$lcduwrhex32.c$65$2$54 Def000168
+S C$lcduwrhex32.c$61$5$64 Def00015E
+S C$lcduwrhex32.c$56$2$54 Def00014B
+S C$lcduwrhex32.c$36$3$55 Def0000F7
+S C$lcduwrhex32.c$14$1$0 Def000021
+S A$lcduwrhex32$486 Def000192
+S A$lcduwrhex32$459 Def00016E
+S A$lcduwrhex32$369 Def000105
+S A$lcduwrhex32$297 Def0000AC
+S A$lcduwrhex32$288 Def0000A3
+S A$lcduwrhex32$279 Def00009B
+S A$lcduwrhex32$198 Def000043
+S A$lcduwrhex32$189 Def000036
+S C$lcduwrhex32.c$66$2$54 Def000176
+S C$lcduwrhex32.c$57$3$62 Def000150
+S A$lcduwrhex32$397 Def000127
+S A$lcduwrhex32$379 Def000112
+S A$lcduwrhex32$298 Def0000AD
+S A$lcduwrhex32$289 Def0000A4
+S A$lcduwrhex32$199 Def000044
+S C$lcduwrhex32.c$58$3$62 Def000155
+S C$lcduwrhex32.c$53$4$57 Def000149
+S C$lcduwrhex32.c$44$4$57 Def000122
+S C$lcduwrhex32.c$38$3$55 Def000100
+S A$lcduwrhex32$479 Def00018A
+S A$lcduwrhex32$389 Def00011D
+S C$lcduwrhex32.c$59$3$62 Def000157
+S A$lcduwrhex32$489 Def000194
+S C$lcduwrhex32.c$45$5$58 Def000127
+S C$lcduwrhex32.c$48$4$57 Def00012C
+S C$lcduwrhex32.c$46$5$58 Def000129
+S C$lcduwrhex32.c$68$3$66 Def000189
+S C$lcduwrhex32.c$49$4$57 Def000135
+S C$lcduwrhex32.c$67$4$67 Def000180
+S C$lcduwrhex32.c$8$0$0 Def000000
+S G$lcd_writehex32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 04
+R 00 00 00 05
+T 00 00 04
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 02
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 02 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 75 00 00 00 00
+R 00 00 00 16 F1 21 0C 00 05
+T 00 00 18 75 00 00 02 08 90 00 01 E0 F5
+R 00 00 00 16 F1 21 04 00 05 00 09 00 0A
+T 00 00 20 00 00 03 90 00 00 E0 FC E5
+R 00 00 00 16 F1 21 03 00 05 00 07 00 0A
+T 00 00 27 00 00 03 30 E0 36 C0 04 90 00 02 E0 F8
+R 00 00 00 16 F1 21 03 00 05 00 0C 00 0A
+T 00 00 32 A3 E0 F9 A3 E0 FA A3 E0 FB 88 04 89 05
+R 00 00 00 16
+T 00 00 3F 8A 06 8B 07 EF D0 04 30 E7 18 90 00 02
+R 00 00 00 16 00 0E 00 0A
+T 00 00 4C C3 E4 98 F0 E4 99 A3 F0 E4 9A A3 F0 E4
+R 00 00 00 16
+T 00 00 59 9B A3 F0 75 00 00 00 2D 80 21
+R 00 00 00 16 F1 21 07 00 05
+T 00 00 61
+R 00 00 00 16
+T 00 00 61 E5 00 00 03 20 E2 19 E5 00 00 03 30 E1
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 00 6A 17 90 00 02 E0 F5 F0 A3 E0 42 F0 A3 E0
+R 00 00 00 16 00 05 00 0A
+T 00 00 77 42 F0 A3 E0 45 F0 60 03
+R 00 00 00 16
+T 00 00 7F
+R 00 00 00 16
+T 00 00 7F 75 00 00 00 2B
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 82
+R 00 00 00 16
+T 00 00 82 E5 00 00 00 60 04 EC 60 01 1C
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A E5 00 00 03 30 E4 06 EC 24 FB 50 01 1C
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 95
+R 00 00 00 16
+T 00 00 95 53 00 00 03 3F EC 24 F7 50 02 8C
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 9E 00 00 02
+R 00 00 00 16 F1 21 03 00 05
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F 90 00 02 E0 FB A3 E0 FD A3 E0 FE A3 E0
+R 00 00 00 16 00 04 00 0A
+T 00 00 AC FF 85 00 00 02 00 00 04
+R 00 00 00 16 F1 21 05 00 05 F1 21 08 00 05
+T 00 00 B0
+R 00 00 00 16
+T 00 00 B0 C0 04 A8 00 00 04 79 00 18 B8 FF 01 19
+R 00 00 00 16 F1 21 06 00 05
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB E9 C8 25 E0 C8 33 C8 25 E0 C8 33 88 F0
+R 00 00 00 16
+T 00 00 C8 05 F0 A8 03 A9 05 AA 06 AC 07 80 0D
+R 00 00 00 16
+T 00 00 D4
+R 00 00 00 16
+T 00 00 D4 C3 EC 13 FC EA 13 FA E9 13 F9 E8 13 F8
+R 00 00 00 16
+T 00 00 E1
+R 00 00 00 16
+T 00 00 E1 D5 F0 F0 88 00 00 01 53 00 00 01 0F C3
+R 00 00 00 16 F1 21 07 00 05 F1 21 0B 00 05
+T 00 00 EA E5 00 00 01 94 0A D0 04 40 15 E5
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 F3 00 00 03 30 E5 09 AA 00 00 01 74 27 2A
+R 00 00 00 16 F1 21 03 00 05 F1 21 0A 00 05
+T 00 00 FC F5 00 00 01 80 07
+R 00 00 00 16 F1 21 04 00 05
+T 00 01 00
+R 00 00 00 16
+T 00 01 00 AA 00 00 01 74 07 2A F5 00 00 01
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 01 07
+R 00 00 00 16
+T 00 01 07 E5 00 00 01 70 40 74 01 B5 00 00 04 02
+R 00 00 00 16 F1 21 04 00 05 F1 21 0C 00 05
+T 00 01 10 80 39
+R 00 00 00 16
+T 00 01 12
+R 00 00 00 16
+T 00 01 12 E5 00 00 03 20 E7 34 C3 EC 95 00 00 04
+R 00 00 00 16 F1 21 04 00 05 F1 21 0D 00 05
+T 00 01 1B 40 6D E5 00 00 03 20 E3 29 E5 00 00 03
+R 00 00 00 16 F1 21 06 00 05 F1 21 0D 00 05
+T 00 01 24 20 E6 05 AC 00 00 04 43 00 00 03 40
+R 00 00 00 16 F1 21 07 00 05 F1 21 0B 00 05
+T 00 01 2C
+R 00 00 00 16
+T 00 01 2C 75 82 20 12 00 00 12 00 00 E5
+R 00 00 00 16 02 07 00 02 02 0A 00 00
+T 00 01 36 00 00 03 30 E4 50 74 05 B5 00 00 04 4B
+R 00 00 00 16 F1 21 03 00 05 F1 21 0C 00 05
+T 00 01 3F 75 82 20 12 00 00 12 00 00 0C 80 3F
+R 00 00 00 16 02 07 00 02 02 0A 00 00
+T 00 01 4B
+R 00 00 00 16
+T 00 01 4B E5 00 00 03 20 E7 18 E5 00 00 03 20 E6
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 01 54 02 AC 00 00 04
+R 00 00 00 16 F1 21 05 00 05
+T 00 01 57
+R 00 00 00 16
+T 00 01 57 43 00 00 03 C8 E5 00 00 00 60 0A 85
+R 00 00 00 16 F1 21 04 00 05 F1 21 09 00 05
+T 00 01 5F 00 00 00 82 12 00 00 12
+R 00 00 00 16 F1 21 03 00 05 02 08 00 02
+T 00 01 65 00 00 0C
+R 00 00 00 16 02 03 00 00
+T 00 01 68
+R 00 00 00 16
+T 00 01 68 AA 00 00 01 74 30 2A FA F5 82 12 00 00
+R 00 00 00 16 F1 21 04 00 05 02 0E 00 02
+T 00 01 73 12 00 00 E5 00 00 03 30 E4 0F 74 05 B5
+R 00 00 00 16 02 04 00 00 F1 21 07 00 05
+T 00 01 7E 00 00 04 0A 75 82 27 12 00 00 12
+R 00 00 00 16 F1 21 03 00 05 02 0B 00 02
+T 00 01 87 00 00 0C
+R 00 00 00 16 02 03 00 00
+T 00 01 8A
+R 00 00 00 16
+T 00 01 8A D5 00 00 04 02 80 03
+R 00 00 00 16 F1 21 04 00 05
+T 00 01 8F
+R 00 00 00 16
+T 00 01 8F 02 00 B0
+R 00 00 00 16 00 04 00 16
+T 00 01 92
+R 00 00 00 16
+T 00 01 92 8C 82 22
+R 00 00 00 16
+
+
+M:lcduwrhex32
+F:G$lcd_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$ch$1$50({1}SC:S),E,0,0
+S:Llcduwrhex32.lcd_writehex32$d$1$50({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$cnt$1$50({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$flags$1$50({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$nrdig$1$50({1}SC:U),E,0,0
+S:Llcduwrhex32.lcd_writehex32$nrdig1$1$49({1}SC:U),F,0,0
+S:Llcduwrhex32.lcd_writehex32$flags1$1$49({1}SC:U),F,0,0
+S:Llcduwrhex32.lcd_writehex32$val$1$49({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$lcd_waitlong$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_waitshort$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_write$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writecmd$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writedata$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portoff$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_portinit$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_init$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_setpos$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_cleardisplay$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_clear$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$lcd_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$lcd_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglink
+
+;!FILE libmflarge/dbglink.asm
+XH3
+H 23 areas 432 global symbols
+M dbglink
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S _dbglink_rxbuffer Ref000000
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _dbglink_txbuffer Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fdbglink$dbglink_fiforxrd$0$0 Def000001
+S Fdbglink$dbglink_fifotxrd$0$0 Def000003
+S Fdbglink$dbglink_fiforxwr$0$0 Def000000
+S Fdbglink$dbglink_fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$dbglink.c$55$1$62 Def000000
+S C$dbglink.c$56$1$62 Def000022
+S C$dbglink.c$32$1$59 Def000000
+S G$dbglink_poll$0$0 Def000022
+S C$dbglink.c$83$1$64 Def000022
+S C$dbglink.c$58$1$62 Def000022
+S C$dbglink.c$36$1$59 Def000000
+S _dbglink_poll Def000022
+S G$dbglink_irq$0$0 Def000000
+S XFdbglink$dummy0$0$0 Def000000
+S _dbglink_irq Def000000
+S A$dbglink$1230 Def00000A
+S A$dbglink$1240 Def000021
+S A$dbglink$1231 Def00000C
+S A$dbglink$1232 Def00000F
+S A$dbglink$1260 Def000026
+S A$dbglink$1233 Def000012
+S A$dbglink$1261 Def000027
+S A$dbglink$1234 Def000015
+S A$dbglink$1225 Def000000
+S A$dbglink$1262 Def000029
+S A$dbglink$1235 Def000017
+S A$dbglink$1226 Def000002
+S A$dbglink$1263 Def00002B
+S A$dbglink$1236 Def000019
+S A$dbglink$1227 Def000004
+S A$dbglink$1264 Def00002E
+S A$dbglink$1237 Def00001B
+S A$dbglink$1228 Def000006
+S XG$dbglink_irq$0$0 Def000022
+S A$dbglink$1265 Def000030
+S A$dbglink$1238 Def00001D
+S A$dbglink$1229 Def000008
+S A$dbglink$1266 Def000031
+S A$dbglink$1239 Def00001F
+S A$dbglink$1267 Def000032
+S A$dbglink$1258 Def000022
+S A$dbglink$1268 Def000034
+S A$dbglink$1259 Def000024
+S A$dbglink$1269 Def000036
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4E flags 20 addr 0
+S C$dbglink.c$960$1$98 Def00003B
+S XG$dbglink_txpoke$0$0 Def000016
+S C$dbglink.c$349$1$88 Def000007
+S C$dbglink.c$961$1$98 Def000047
+S G$dbglink_init$0$0 Def00003B
+S C$dbglink.c$398$1$94 Def00002C
+S C$dbglink.c$962$1$98 Def00004A
+S C$dbglink.c$399$1$94 Def00003B
+S C$dbglink.c$31$1$59 Def000000
+S C$dbglink.c$963$1$98 Def00004D
+S XG$dbglink_rxbuffersize$0$0 Def000000
+S C$dbglink.c$958$1$96 Def00003B
+S XG$dbglink_txpokehex$0$0 Def00002C
+S C$dbglink.c$19$0$0 Def000000
+S Fdbglink$dummy0$0$0 Def000000
+S _dbglink_init Def00003B
+S XFdbglink$wtimer_cansleep_dummy$0$0 Def00003B
+S G$dbglink_txidle$0$0 Def00002C
+S XG$dbglink_init$0$0 Def00004D
+S G$dbglink_rxpeek$0$0 Def000000
+S _dbglink_txidle Def00002C
+S G$dbglink_txpoke$0$0 Def000007
+S _dbglink_rxpeek Def000000
+S A$dbglink$1701 Def000000
+S G$dbglink_txpokehex$0$0 Def000016
+S A$dbglink$1702 Def000003
+S A$dbglink$1730 Def00000E
+S A$dbglink$1703 Def000004
+S XG$dbglink_txidle$0$0 Def00003B
+S A$dbglink$1731 Def000011
+S A$dbglink$1704 Def000006
+S A$dbglink$1732 Def000012
+S A$dbglink$1760 Def00001E
+S A$dbglink$1733 Def000013
+S C$dbglink.c$401$1$94 Def00003B
+S A$dbglink$1761 Def000020
+S A$dbglink$1734 Def000015
+S A$dbglink$1725 Def000007
+S A$dbglink$1852 Def00004A
+S A$dbglink$1843 Def00003B
+S A$dbglink$1762 Def000022
+S A$dbglink$1726 Def000009
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+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglink$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fdbglink$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnktxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M dbglnktxbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _dbglink_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$dbglnktxbuf.c$5$1$59 Def000000
+S C$dbglnktxbuf.c$5$0$0 Def000000
+S Fdbglnktxbuf$dbglink_define_txbuffer$0$0 Def000000
+S XFdbglnktxbuf$dbglink_define_txbuffer$0$0 Def000000
+A DBGLINK0 size 0 flags 20 addr 0
+A DBGLINK1 size 2 flags 20 addr 0
+A DBGLINK2 size 0 flags 20 addr 0
+A DBGLINK3 size 0 flags 20 addr 0
+A DBGLINK4 size 1 flags 20 addr 0
+A DBGLINK5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:dbglnktxbuf
+F:Fdbglnktxbuf$dbglink_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglnktxbuf$dbglink_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkrxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M dbglnkrxbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _dbglink_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$dbglnkrxbuf.c$5$1$59 Def000000
+S C$dbglnkrxbuf.c$5$0$0 Def000000
+S Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0 Def000000
+S XFdbglnkrxbuf$dbglink_define_rxbuffer$0$0 Def000000
+A DBGLINK0 size 0 flags 20 addr 0
+A DBGLINK1 size 0 flags 20 addr 0
+A DBGLINK2 size 2 flags 20 addr 0
+A DBGLINK3 size 0 flags 20 addr 0
+A DBGLINK4 size 0 flags 20 addr 0
+A DBGLINK5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:dbglnkrxbuf
+F:Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
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+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fdbglnkrxbuf$dbglink_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnktx
+
+;!FILE libmflarge/dbglnktx.asm
+XH3
+H 1A areas 327 global symbols
+M dbglnktx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _dbglink_poll Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S _dbglink_txadvance Ref000000
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _dbglink_txidle Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S _dbglink_txfree Ref000000
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _dbglink_txpoke Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$dbglnktx.c$50$1$62 Def000052
+S C$dbglnktx.c$33$2$60 Def000023
+S C$dbglnktx.c$52$1$62 Def000053
+S C$dbglnktx.c$42$2$63 Def000037
+S C$dbglnktx.c$43$2$63 Def000039
+S C$dbglnktx.c$28$2$60 Def00000D
+S C$dbglnktx.c$29$2$60 Def00000F
+S _dbglink_tx Def000053
+S C$dbglnktx.c$45$2$63 Def000040
+S C$dbglnktx.c$54$1$65 Def000057
+S C$dbglnktx.c$46$2$63 Def000047
+S XG$dbglink_wait_txfree$0$0 Def000031
+S C$dbglnktx.c$55$1$65 Def00005D
+S C$dbglnktx.c$47$2$63 Def00004A
+S C$dbglnktx.c$49$1$62 Def00004F
+S C$dbglnktx.c$24$0$0 Def000000
+S C$dbglnktx.c$56$1$65 Def000067
+S C$dbglnktx.c$35$1$59 Def000028
+S C$dbglnktx.c$26$1$59 Def000008
+S C$dbglnktx.c$57$1$65 Def00006F
+S C$dbglnktx.c$36$1$59 Def000031
+S XG$dbglink_wait_txdone$0$0 Def000052
+S C$dbglnktx.c$38$1$59 Def000032
+S XG$dbglink_tx$0$0 Def00006F
+S A$dbglnktx$1300 Def000055
+S A$dbglnktx$1201 Def00000D
+S A$dbglnktx$1310 Def000065
+S A$dbglnktx$1230 Def00002D
+S A$dbglnktx$1221 Def000023
+S A$dbglnktx$1212 Def000019
+S A$dbglnktx$1303 Def000057
+S A$dbglnktx$1231 Def00002F
+S A$dbglnktx$1222 Def000024
+S A$dbglnktx$1213 Def00001C
+S A$dbglnktx$1204 Def00000F
+S A$dbglnktx$1313 Def000067
+S A$dbglnktx$1304 Def00005A
+S A$dbglnktx$1223 Def000026
+S A$dbglnktx$1214 Def00001E
+S A$dbglnktx$1205 Def000012
+S G$dbglink_wait_txfree$0$0 Def000000
+S A$dbglnktx$1314 Def00006A
+S A$dbglnktx$1251 Def000032
+S A$dbglnktx$1206 Def000014
+S A$dbglnktx$1315 Def00006D
+S A$dbglnktx$1252 Def000034
+S A$dbglnktx$1234 Def000031
+S A$dbglnktx$1207 Def000015
+S A$dbglnktx$1307 Def00005D
+S A$dbglnktx$1262 Def000039
+S A$dbglnktx$1253 Def000036
+S A$dbglnktx$1217 Def000020
+S A$dbglnktx$1208 Def000016
+S A$dbglnktx$1190 Def000006
+S A$dbglnktx$1308 Def00005F
+S A$dbglnktx$1272 Def000047
+S A$dbglnktx$1263 Def00003C
+S A$dbglnktx$1227 Def000028
+S A$dbglnktx$1209 Def000017
+S G$dbglink_wait_txdone$0$0 Def000032
+S A$dbglnktx$1318 Def00006F
+S A$dbglnktx$1309 Def000062
+S A$dbglnktx$1282 Def00004F
+S A$dbglnktx$1264 Def00003E
+S A$dbglnktx$1228 Def000029
+S A$dbglnktx$1283 Def000050
+S A$dbglnktx$1229 Def00002B
+S A$dbglnktx$1193 Def000008
+S A$dbglnktx$1194 Def00000A
+S A$dbglnktx$1276 Def00004A
+S A$dbglnktx$1267 Def000040
+S A$dbglnktx$1195 Def00000C
+S A$dbglnktx$1286 Def000052
+S A$dbglnktx$1277 Def00004B
+S A$dbglnktx$1268 Def000043
+S A$dbglnktx$1259 Def000037
+S A$dbglnktx$1187 Def000000
+S A$dbglnktx$1278 Def00004D
+S A$dbglnktx$1269 Def000045
+S A$dbglnktx$1188 Def000002
+S G$dbglink_tx$0$0 Def000053
+S A$dbglnktx$1189 Def000004
+S _dbglink_wait_txfree Def000000
+S A$dbglnktx$1299 Def000053
+S C$dbglnktx.c$31$2$60 Def000019
+S C$dbglnktx.c$40$1$62 Def000032
+S C$dbglnktx.c$32$2$60 Def000020
+S _dbglink_wait_txdone Def000032
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 01 83
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 00 C2 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 01 67 02 0D 00 C2
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 7F
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A EF 42 A8 80 E8
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 02 24 02 0E 00 F5
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:dbglnktx
+F:G$dbglink_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_wait_txfree$v$1$58({1}SC:U),R,0,0,[r7]
+S:Ldbglnktx.dbglink_wait_txfree$iesave$1$59({1}SC:U),R,0,0,[r6]
+F:G$dbglink_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_wait_txdone$iesave$1$62({1}SC:U),R,0,0,[r7]
+F:G$dbglink_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnktx.dbglink_tx$v$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
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+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkrx
+
+;!FILE libmflarge/dbglnkrx.asm
+XH3
+H 1A areas 309 global symbols
+M dbglnkrx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _dbglink_poll Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S _dbglink_rxadvance Ref000000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S _dbglink_rxpeek Ref000000
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S _dbglink_rxcount Ref000000
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$dbglnkrx.c$43$1$62 Def000042
+S _dbglink_wait_rxcount Def000000
+S C$dbglnkrx.c$44$1$62 Def000048
+S C$dbglnkrx.c$45$1$62 Def00004C
+S C$dbglnkrx.c$28$2$60 Def00000D
+S C$dbglnkrx.c$29$2$60 Def00000F
+S _dbglink_rx Def000032
+S C$dbglnkrx.c$24$0$0 Def000000
+S C$dbglnkrx.c$35$1$59 Def000028
+S C$dbglnkrx.c$26$1$59 Def000008
+S C$dbglnkrx.c$36$1$59 Def000031
+S C$dbglnkrx.c$38$1$59 Def000032
+S XG$dbglink_wait_rxcount$0$0 Def000031
+S XG$dbglink_rx$0$0 Def00004C
+S A$dbglnkrx$1210 Def000019
+S A$dbglnkrx$1220 Def000024
+S A$dbglnkrx$1211 Def00001C
+S A$dbglnkrx$1202 Def00000F
+S A$dbglnkrx$1221 Def000026
+S A$dbglnkrx$1212 Def00001E
+S A$dbglnkrx$1203 Def000012
+S A$dbglnkrx$1204 Def000014
+S A$dbglnkrx$1250 Def000034
+S A$dbglnkrx$1232 Def000031
+S A$dbglnkrx$1205 Def000015
+S A$dbglnkrx$1260 Def000045
+S A$dbglnkrx$1251 Def000037
+S A$dbglnkrx$1215 Def000020
+S A$dbglnkrx$1206 Def000016
+S A$dbglnkrx$1225 Def000028
+S A$dbglnkrx$1207 Def000017
+S A$dbglnkrx$1226 Def000029
+S A$dbglnkrx$1263 Def000048
+S A$dbglnkrx$1254 Def00003A
+S A$dbglnkrx$1227 Def00002B
+S A$dbglnkrx$1191 Def000008
+S A$dbglnkrx$1264 Def00004A
+S A$dbglnkrx$1255 Def00003D
+S A$dbglnkrx$1228 Def00002D
+S A$dbglnkrx$1219 Def000023
+S A$dbglnkrx$1192 Def00000A
+S A$dbglnkrx$1256 Def000040
+S A$dbglnkrx$1247 Def000032
+S A$dbglnkrx$1229 Def00002F
+S A$dbglnkrx$1193 Def00000C
+S A$dbglnkrx$1185 Def000000
+S G$dbglink_wait_rxcount$0$0 Def000000
+S A$dbglnkrx$1267 Def00004C
+S A$dbglnkrx$1186 Def000002
+S A$dbglnkrx$1259 Def000042
+S A$dbglnkrx$1187 Def000004
+S A$dbglnkrx$1188 Def000006
+S G$dbglink_rx$0$0 Def000032
+S A$dbglnkrx$1199 Def00000D
+S C$dbglnkrx.c$31$2$60 Def000019
+S C$dbglnkrx.c$32$2$60 Def000020
+S C$dbglnkrx.c$41$1$62 Def000034
+S C$dbglnkrx.c$33$2$60 Def000023
+S C$dbglnkrx.c$42$1$62 Def00003A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 01 C1
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 00 C2 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 01 8B 02 0B 00 E9
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:dbglnkrx
+F:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkrx.dbglink_wait_rxcount$v$1$58({1}SC:U),R,0,0,[r7]
+S:Ldbglnkrx.dbglink_wait_rxcount$iesave$1$59({1}SC:U),R,0,0,[r6]
+F:G$dbglink_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkrx.dbglink_rx$x$1$62({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
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+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhexu16
+
+;!FILE libmflarge/dbglnkwrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M dbglnkwrhexu16
+O -mmcs51 --model-large
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S _bp Ref000000
+S _dbglink_txpokehex Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S G$dbglink_writehexu16$0$0 Def000000
+S A$dbglnkwrhexu16$122 Def000009
+S A$dbglnkwrhexu16$150 Def000028
+S A$dbglnkwrhexu16$141 Def00001B
+S A$dbglnkwrhexu16$132 Def000015
+S A$dbglnkwrhexu16$123 Def00000B
+S A$dbglnkwrhexu16$160 Def000034
+S A$dbglnkwrhexu16$151 Def000029
+S A$dbglnkwrhexu16$142 Def00001D
+S A$dbglnkwrhexu16$124 Def00000D
+S A$dbglnkwrhexu16$152 Def00002A
+S A$dbglnkwrhexu16$143 Def00001F
+S A$dbglnkwrhexu16$134 Def000017
+S A$dbglnkwrhexu16$125 Def00000E
+S A$dbglnkwrhexu16$116 Def000000
+S A$dbglnkwrhexu16$153 Def00002C
+S A$dbglnkwrhexu16$144 Def000021
+S A$dbglnkwrhexu16$135 Def000018
+S A$dbglnkwrhexu16$117 Def000002
+S A$dbglnkwrhexu16$154 Def00002D
+S A$dbglnkwrhexu16$145 Def000024
+S A$dbglnkwrhexu16$118 Def000005
+S C$dbglnkwrhexu16.c$25$2$60 Def00001A
+S A$dbglnkwrhexu16$164 Def000036
+S A$dbglnkwrhexu16$155 Def00002E
+S A$dbglnkwrhexu16$128 Def000010
+S A$dbglnkwrhexu16$119 Def000007
+S C$dbglnkwrhexu16.c$26$2$60 Def00001B
+S A$dbglnkwrhexu16$165 Def000038
+S A$dbglnkwrhexu16$156 Def000030
+S A$dbglnkwrhexu16$138 Def00001A
+S A$dbglnkwrhexu16$129 Def000012
+S C$dbglnkwrhexu16.c$27$2$60 Def000026
+S A$dbglnkwrhexu16$166 Def00003B
+S A$dbglnkwrhexu16$157 Def000031
+S A$dbglnkwrhexu16$148 Def000026
+S C$dbglnkwrhexu16.c$30$1$59 Def00003D
+S A$dbglnkwrhexu16$158 Def000032
+S A$dbglnkwrhexu16$149 Def000027
+S A$dbglnkwrhexu16$159 Def000033
+S C$dbglnkwrhexu16.c$23$1$59 Def000010
+S C$dbglnkwrhexu16.c$21$1$0 Def000009
+S A$dbglnkwrhexu16$169 Def00003D
+S C$dbglnkwrhexu16.c$24$1$59 Def000015
+S _dbglink_writehexu16 Def000000
+S C$dbglnkwrhexu16.c$29$1$59 Def000036
+S C$dbglnkwrhexu16.c$19$0$0 Def000000
+S XG$dbglink_writehexu16$0$0 Def00003D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 02 F1 23 09 00 02
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 02
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 04
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 03
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 00 F1 23 09 00 02
+
+
+M:dbglnkwrhexu16
+F:G$dbglink_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwrhexu16.dbglink_writehexu16$nrdig$1$58({1}SC:U),B,1,-3
+S:Ldbglnkwrhexu16.dbglink_writehexu16$val$1$58({2}SI:U),R,0,0,[r6,r7]
+S:Ldbglnkwrhexu16.dbglink_writehexu16$nrdig1$1$59({1}SC:U),R,0,0,[r5]
+S:Ldbglnkwrhexu16.dbglink_writehexu16$digit$1$59({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhexu32
+
+;!FILE libmflarge/dbglnkwrhexu32.asm
+XH3
+H 1A areas 6A global symbols
+M dbglnkwrhexu32
+O -mmcs51 --model-large
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S _dbglink_txpokehex Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S _dbglink_writehexu32_PARM_2 Def000000
+S Ldbglnkwrhexu32.dbglink_writehexu32$val$1$58 Def000001
+S Ldbglnkwrhexu32.dbglink_writehexu32$nrdig$1$58 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 76 flags 20 addr 0
+S A$dbglnkwrhexu32$200 Def000058
+S A$dbglnkwrhexu32$210 Def000065
+S A$dbglnkwrhexu32$201 Def000059
+S A$dbglnkwrhexu32$211 Def000066
+S A$dbglnkwrhexu32$202 Def00005A
+S A$dbglnkwrhexu32$130 Def00000C
+S G$dbglink_writehexu32$0$0 Def000000
+S A$dbglnkwrhexu32$212 Def000067
+S A$dbglnkwrhexu32$203 Def00005C
+S A$dbglnkwrhexu32$131 Def00000D
+S A$dbglnkwrhexu32$213 Def000068
+S A$dbglnkwrhexu32$204 Def00005D
+S A$dbglnkwrhexu32$150 Def00001F
+S A$dbglnkwrhexu32$141 Def000015
+S A$dbglnkwrhexu32$132 Def00000E
+S A$dbglnkwrhexu32$123 Def000000
+S A$dbglnkwrhexu32$223 Def000070
+S A$dbglnkwrhexu32$214 Def000069
+S A$dbglnkwrhexu32$205 Def00005E
+S A$dbglnkwrhexu32$160 Def000028
+S A$dbglnkwrhexu32$142 Def000018
+S A$dbglnkwrhexu32$133 Def00000F
+S A$dbglnkwrhexu32$124 Def000002
+S A$dbglnkwrhexu32$224 Def000072
+S A$dbglnkwrhexu32$215 Def00006A
+S A$dbglnkwrhexu32$206 Def00005F
+S A$dbglnkwrhexu32$170 Def000032
+S A$dbglnkwrhexu32$161 Def000029
+S A$dbglnkwrhexu32$152 Def000021
+S A$dbglnkwrhexu32$134 Def000010
+S A$dbglnkwrhexu32$125 Def000004
+S A$dbglnkwrhexu32$216 Def00006B
+S A$dbglnkwrhexu32$207 Def000060
+S A$dbglnkwrhexu32$180 Def000040
+S A$dbglnkwrhexu32$171 Def000033
+S A$dbglnkwrhexu32$162 Def00002A
+S A$dbglnkwrhexu32$153 Def000022
+S A$dbglnkwrhexu32$135 Def000011
+S A$dbglnkwrhexu32$126 Def000006
+S A$dbglnkwrhexu32$217 Def00006C
+S A$dbglnkwrhexu32$208 Def000063
+S A$dbglnkwrhexu32$190 Def00004C
+S A$dbglnkwrhexu32$181 Def000041
+S A$dbglnkwrhexu32$172 Def000035
+S A$dbglnkwrhexu32$163 Def00002B
+S A$dbglnkwrhexu32$145 Def000019
+S A$dbglnkwrhexu32$136 Def000012
+S A$dbglnkwrhexu32$127 Def000007
+S C$dbglnkwrhexu32.c$25$2$60 Def000024
+S A$dbglnkwrhexu32$227 Def000075
+S A$dbglnkwrhexu32$218 Def00006D
+S A$dbglnkwrhexu32$209 Def000064
+S A$dbglnkwrhexu32$191 Def00004D
+S A$dbglnkwrhexu32$182 Def000042
+S A$dbglnkwrhexu32$173 Def000037
+S A$dbglnkwrhexu32$164 Def00002C
+S A$dbglnkwrhexu32$146 Def00001A
+S A$dbglnkwrhexu32$137 Def000013
+S A$dbglnkwrhexu32$128 Def00000A
+S C$dbglnkwrhexu32.c$26$2$60 Def000025
+S A$dbglnkwrhexu32$219 Def00006E
+S A$dbglnkwrhexu32$192 Def00004E
+S A$dbglnkwrhexu32$183 Def000044
+S A$dbglnkwrhexu32$174 Def000039
+S A$dbglnkwrhexu32$165 Def00002D
+S A$dbglnkwrhexu32$156 Def000024
+S A$dbglnkwrhexu32$147 Def00001C
+S A$dbglnkwrhexu32$138 Def000014
+S A$dbglnkwrhexu32$129 Def00000B
+S C$dbglnkwrhexu32.c$27$2$60 Def00003E
+S A$dbglnkwrhexu32$193 Def000050
+S A$dbglnkwrhexu32$184 Def000045
+S A$dbglnkwrhexu32$175 Def00003C
+S A$dbglnkwrhexu32$166 Def00002E
+S C$dbglnkwrhexu32.c$30$1$59 Def000075
+S A$dbglnkwrhexu32$194 Def000051
+S A$dbglnkwrhexu32$185 Def000046
+S A$dbglnkwrhexu32$167 Def00002F
+S A$dbglnkwrhexu32$195 Def000052
+S A$dbglnkwrhexu32$186 Def000048
+S A$dbglnkwrhexu32$168 Def000030
+S A$dbglnkwrhexu32$159 Def000025
+S C$dbglnkwrhexu32.c$23$1$59 Def000019
+S C$dbglnkwrhexu32.c$21$1$0 Def000015
+S A$dbglnkwrhexu32$196 Def000053
+S A$dbglnkwrhexu32$187 Def000049
+S A$dbglnkwrhexu32$178 Def00003E
+S A$dbglnkwrhexu32$169 Def000031
+S C$dbglnkwrhexu32.c$24$1$59 Def00001F
+S _dbglink_writehexu32 Def000000
+S A$dbglnkwrhexu32$197 Def000054
+S A$dbglnkwrhexu32$188 Def00004A
+S A$dbglnkwrhexu32$179 Def00003F
+S A$dbglnkwrhexu32$198 Def000055
+S A$dbglnkwrhexu32$189 Def00004B
+S A$dbglnkwrhexu32$199 Def000056
+S C$dbglnkwrhexu32.c$29$1$59 Def000070
+S C$dbglnkwrhexu32.c$19$0$0 Def000000
+S XG$dbglink_writehexu32$0$0 Def000075
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 03
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 4C 1E 90 00 01 E0 FA A3 E0 FB A3
+R 00 00 00 16 00 08 00 0A
+T 00 00 2E E0 FC A3 E0 FD 8A 01 C0 01 8E 82 12
+R 00 00 00 16
+T 00 00 3A 00 00 15 81 EB C4 CA C4 54 0F 6A CA 54
+R 00 00 00 16 02 03 00 02
+T 00 00 47 0F CA 6A CA FB EC C4 54 F0 4B FB ED C4
+R 00 00 00 16
+T 00 00 54 CC C4 54 0F 6C CC 54 0F CC 6C CC FD 90
+R 00 00 00 16
+T 00 00 61 00 01 EA F0 EB A3 F0 EC A3 F0 ED A3 F0
+R 00 00 00 16 00 03 00 0A
+T 00 00 6E 80 B1
+R 00 00 00 16
+T 00 00 70
+R 00 00 00 16
+T 00 00 70 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 00
+
+
+M:dbglnkwrhexu32
+F:G$dbglink_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Ldbglnkwrhexu32.dbglink_writehexu32$nrdig1$1$59({1}SC:U),R,0,0,[r7]
+S:Ldbglnkwrhexu32.dbglink_writehexu32$digit$1$59({1}SC:U),R,0,0,[r6]
+S:Ldbglnkwrhexu32.dbglink_writehexu32$nrdig$1$58({1}SC:U),F,0,0
+S:Ldbglnkwrhexu32.dbglink_writehexu32$val$1$58({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrstr
+
+;!FILE libmflarge/dbglnkwrstr.asm
+XH3
+H 1A areas 51 global symbols
+M dbglnkwrstr
+O -mmcs51 --model-large
+S _dbglink_txadvance Ref000000
+S _dbglink_txbufptr Ref000000
+S .__.ABS. Def000000
+S _dbglink_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S C$dbglnkwrstr.c$102$1$59 Def000000
+S C$dbglnkwrstr.c$103$1$59 Def000076
+S A$dbglnkwrstr$120 Def00000A
+S A$dbglnkwrstr$130 Def000018
+S A$dbglnkwrstr$121 Def00000D
+S G$dbglink_writestr$0$0 Def000000
+S A$dbglnkwrstr$140 Def000025
+S A$dbglnkwrstr$131 Def000019
+S A$dbglnkwrstr$113 Def000000
+S A$dbglnkwrstr$150 Def00002F
+S A$dbglnkwrstr$141 Def000026
+S A$dbglnkwrstr$132 Def00001A
+S A$dbglnkwrstr$123 Def000010
+S A$dbglnkwrstr$114 Def000002
+S A$dbglnkwrstr$160 Def000040
+S A$dbglnkwrstr$151 Def000031
+S A$dbglnkwrstr$142 Def000027
+S A$dbglnkwrstr$133 Def00001B
+S A$dbglnkwrstr$124 Def000011
+S A$dbglnkwrstr$115 Def000004
+S A$dbglnkwrstr$170 Def000054
+S A$dbglnkwrstr$161 Def000042
+S A$dbglnkwrstr$152 Def000032
+S A$dbglnkwrstr$143 Def000029
+S A$dbglnkwrstr$134 Def00001D
+S A$dbglnkwrstr$125 Def000012
+S A$dbglnkwrstr$116 Def000005
+S A$dbglnkwrstr$180 Def000064
+S A$dbglnkwrstr$171 Def000055
+S A$dbglnkwrstr$162 Def000044
+S A$dbglnkwrstr$153 Def000033
+S A$dbglnkwrstr$144 Def00002B
+S A$dbglnkwrstr$135 Def00001F
+S A$dbglnkwrstr$117 Def000006
+S A$dbglnkwrstr$190 Def000071
+S A$dbglnkwrstr$181 Def000065
+S A$dbglnkwrstr$172 Def000056
+S A$dbglnkwrstr$163 Def000046
+S A$dbglnkwrstr$154 Def000035
+S A$dbglnkwrstr$191 Def000073
+S A$dbglnkwrstr$182 Def000066
+S A$dbglnkwrstr$173 Def000058
+S A$dbglnkwrstr$164 Def000049
+S A$dbglnkwrstr$155 Def000036
+S A$dbglnkwrstr$128 Def000014
+S A$dbglnkwrstr$119 Def000007
+S A$dbglnkwrstr$183 Def000068
+S A$dbglnkwrstr$174 Def00005B
+S A$dbglnkwrstr$165 Def00004C
+S A$dbglnkwrstr$156 Def000038
+S A$dbglnkwrstr$147 Def00002D
+S A$dbglnkwrstr$138 Def000021
+S A$dbglnkwrstr$129 Def000016
+S A$dbglnkwrstr$184 Def00006A
+S A$dbglnkwrstr$175 Def00005D
+S A$dbglnkwrstr$166 Def00004E
+S A$dbglnkwrstr$157 Def00003A
+S A$dbglnkwrstr$148 Def00002E
+S A$dbglnkwrstr$139 Def000023
+S A$dbglnkwrstr$185 Def00006B
+S A$dbglnkwrstr$167 Def000051
+S A$dbglnkwrstr$195 Def000076
+S A$dbglnkwrstr$186 Def00006C
+S A$dbglnkwrstr$177 Def00005F
+S A$dbglnkwrstr$159 Def00003D
+S A$dbglnkwrstr$178 Def000061
+S A$dbglnkwrstr$169 Def000053
+S _dbglink_writestr Def000000
+S A$dbglnkwrstr$188 Def00006E
+S A$dbglnkwrstr$179 Def000063
+S A$dbglnkwrstr$189 Def00006F
+S C$dbglnkwrstr.c$27$0$0 Def000000
+S XG$dbglink_writestr$0$0 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 05
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 04
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 00
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 03
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 07 02 08 00 03
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 01
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 00
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:dbglnkwrstr
+F:G$dbglink_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwrstr.dbglink_writestr$ch$1$58({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwru16
+
+;!FILE libmflarge/dbglnkwru16.asm
+XH3
+H 1A areas 4A global symbols
+M dbglnkwru16
+O -mmcs51 --model-large
+S __divuint Ref000000
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _bp Ref000000
+S _dbglink_txpoke Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 60 flags 20 addr 0
+S A$dbglnkwru16$120 Def000007
+S A$dbglnkwru16$130 Def000012
+S G$dbglink_writeu16$0$0 Def000000
+S A$dbglnkwru16$150 Def000029
+S A$dbglnkwru16$123 Def000009
+S A$dbglnkwru16$151 Def00002B
+S A$dbglnkwru16$142 Def00001C
+S A$dbglnkwru16$133 Def000015
+S A$dbglnkwru16$124 Def00000B
+S A$dbglnkwru16$161 Def00003C
+S A$dbglnkwru16$152 Def00002D
+S A$dbglnkwru16$143 Def00001F
+S A$dbglnkwru16$125 Def00000D
+S A$dbglnkwru16$180 Def000051
+S A$dbglnkwru16$162 Def00003E
+S A$dbglnkwru16$153 Def00002F
+S A$dbglnkwru16$144 Def000021
+S A$dbglnkwru16$135 Def000017
+S A$dbglnkwru16$126 Def00000E
+S A$dbglnkwru16$117 Def000000
+S A$dbglnkwru16$181 Def000054
+S A$dbglnkwru16$172 Def000048
+S A$dbglnkwru16$163 Def00003F
+S A$dbglnkwru16$154 Def000032
+S A$dbglnkwru16$145 Def000022
+S A$dbglnkwru16$136 Def000018
+S A$dbglnkwru16$118 Def000002
+S A$dbglnkwru16$191 Def00005F
+S A$dbglnkwru16$182 Def000056
+S A$dbglnkwru16$164 Def000042
+S A$dbglnkwru16$155 Def000034
+S A$dbglnkwru16$146 Def000023
+S A$dbglnkwru16$119 Def000005
+S A$dbglnkwru16$165 Def000043
+S A$dbglnkwru16$156 Def000036
+S A$dbglnkwru16$147 Def000024
+S A$dbglnkwru16$129 Def000010
+S C$dbglnkwru16.c$27$2$60 Def00003C
+S A$dbglnkwru16$175 Def000049
+S A$dbglnkwru16$166 Def000044
+S A$dbglnkwru16$157 Def000038
+S A$dbglnkwru16$148 Def000025
+S A$dbglnkwru16$139 Def00001A
+S C$dbglnkwru16.c$28$2$60 Def000048
+S A$dbglnkwru16$176 Def00004B
+S A$dbglnkwru16$167 Def000045
+S A$dbglnkwru16$158 Def00003A
+S A$dbglnkwru16$149 Def000027
+S C$dbglnkwru16.c$31$1$59 Def000058
+S C$dbglnkwru16.c$29$2$60 Def000049
+S A$dbglnkwru16$186 Def000058
+S A$dbglnkwru16$177 Def00004C
+S A$dbglnkwru16$168 Def000046
+S C$dbglnkwru16.c$32$1$59 Def00005F
+S C$dbglnkwru16.c$23$1$59 Def000010
+S C$dbglnkwru16.c$21$1$0 Def000009
+S A$dbglnkwru16$187 Def00005A
+S A$dbglnkwru16$178 Def00004D
+S A$dbglnkwru16$169 Def000047
+S C$dbglnkwru16.c$24$1$59 Def000015
+S _dbglink_writeu16 Def000000
+S A$dbglnkwru16$188 Def00005D
+S A$dbglnkwru16$179 Def00004F
+S C$dbglnkwru16.c$26$1$59 Def00001C
+S C$dbglnkwru16.c$25$2$59 Def00001A
+S C$dbglnkwru16.c$19$0$0 Def000000
+S XG$dbglink_writeu16$0$0 Def00005F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 06
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3E 8E 03 90 00 00 74 0A F0 E4 A3
+R 00 00 00 16 02 09 00 03
+T 00 00 24 F0 8E 82 8F 83 C0 05 C0 04 C0 03 12
+R 00 00 00 16
+T 00 00 30 00 00 AE 82 AF 83 D0 03 D0 04 D0 05 8E
+R 00 00 00 16 02 03 00 00
+T 00 00 3D 02 EA 75 F0 0A A4 FA EB C3 9A FB 1C 74
+R 00 00 00 16
+T 00 00 4A 30 2B FB C0 03 8C 82 12 00 00 15 81 80
+R 00 00 00 16 02 0B 00 05
+T 00 00 57 BF
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 01 F1 23 09 00 04
+
+
+M:dbglnkwru16
+F:G$dbglink_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldbglnkwru16.dbglink_writeu16$nrdig$1$58({1}SC:U),B,1,-3
+S:Ldbglnkwru16.dbglink_writeu16$val$1$58({2}SI:U),R,0,0,[r6,r7]
+S:Ldbglnkwru16.dbglink_writeu16$nrdig1$1$59({1}SC:U),R,0,0,[r5]
+S:Ldbglnkwru16.dbglink_writeu16$digit$1$59({1}SC:U),R,0,0,[r4]
+S:Ldbglnkwru16.dbglink_writeu16$v1$2$60({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwru32
+
+;!FILE libmflarge/dbglnkwru32.asm
+XH3
+H 1A areas 80 global symbols
+M dbglnkwru32
+O -mmcs51 --model-large
+S __divulong_PARM_2 Ref000000
+S _dbglink_txadvance Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _dbglink_txpoke Ref000000
+S _dbglink_wait_txfree Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S Ldbglnkwru32.dbglink_writeu32$nrdig$1$58 Def000000
+S Ldbglnkwru32.dbglink_writeu32$val$1$58 Def000001
+S _dbglink_writeu32_PARM_2 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 99 flags 20 addr 0
+S A$dbglnkwru32$200 Def000063
+S A$dbglnkwru32$201 Def000064
+S A$dbglnkwru32$220 Def000077
+S A$dbglnkwru32$211 Def00006C
+S A$dbglnkwru32$202 Def000065
+S A$dbglnkwru32$130 Def00000B
+S G$dbglink_writeu32$0$0 Def000000
+S A$dbglnkwru32$221 Def000078
+S A$dbglnkwru32$212 Def00006F
+S A$dbglnkwru32$203 Def000066
+S A$dbglnkwru32$131 Def00000C
+S A$dbglnkwru32$240 Def00008C
+S A$dbglnkwru32$222 Def000079
+S A$dbglnkwru32$213 Def000070
+S A$dbglnkwru32$204 Def000067
+S A$dbglnkwru32$132 Def00000D
+S A$dbglnkwru32$250 Def000098
+S A$dbglnkwru32$241 Def00008F
+S A$dbglnkwru32$232 Def000083
+S A$dbglnkwru32$223 Def00007A
+S A$dbglnkwru32$214 Def000071
+S A$dbglnkwru32$205 Def000068
+S A$dbglnkwru32$160 Def000029
+S A$dbglnkwru32$151 Def00001F
+S A$dbglnkwru32$142 Def000015
+S A$dbglnkwru32$133 Def00000E
+S A$dbglnkwru32$124 Def000000
+S A$dbglnkwru32$242 Def000091
+S A$dbglnkwru32$224 Def00007B
+S A$dbglnkwru32$215 Def000072
+S A$dbglnkwru32$206 Def000069
+S A$dbglnkwru32$161 Def00002A
+S A$dbglnkwru32$143 Def000018
+S A$dbglnkwru32$134 Def00000F
+S A$dbglnkwru32$125 Def000002
+S A$dbglnkwru32$225 Def00007E
+S A$dbglnkwru32$216 Def000073
+S A$dbglnkwru32$207 Def00006A
+S A$dbglnkwru32$180 Def00003F
+S A$dbglnkwru32$162 Def00002B
+S A$dbglnkwru32$153 Def000021
+S A$dbglnkwru32$135 Def000010
+S A$dbglnkwru32$126 Def000004
+S A$dbglnkwru32$235 Def000084
+S A$dbglnkwru32$226 Def00007F
+S A$dbglnkwru32$217 Def000074
+S A$dbglnkwru32$208 Def00006B
+S A$dbglnkwru32$190 Def000051
+S A$dbglnkwru32$181 Def000040
+S A$dbglnkwru32$172 Def000034
+S A$dbglnkwru32$163 Def00002C
+S A$dbglnkwru32$154 Def000022
+S A$dbglnkwru32$136 Def000011
+S A$dbglnkwru32$127 Def000006
+S A$dbglnkwru32$236 Def000086
+S A$dbglnkwru32$227 Def000080
+S A$dbglnkwru32$218 Def000075
+S A$dbglnkwru32$191 Def000053
+S A$dbglnkwru32$182 Def000041
+S A$dbglnkwru32$173 Def000037
+S A$dbglnkwru32$164 Def00002D
+S A$dbglnkwru32$146 Def000019
+S A$dbglnkwru32$137 Def000012
+S A$dbglnkwru32$128 Def000007
+S A$dbglnkwru32$246 Def000093
+S A$dbglnkwru32$237 Def000087
+S A$dbglnkwru32$228 Def000081
+S A$dbglnkwru32$219 Def000076
+S A$dbglnkwru32$192 Def000055
+S A$dbglnkwru32$183 Def000043
+S A$dbglnkwru32$174 Def000039
+S A$dbglnkwru32$165 Def00002E
+S A$dbglnkwru32$147 Def00001A
+S A$dbglnkwru32$138 Def000013
+S A$dbglnkwru32$129 Def00000A
+S C$dbglnkwru32.c$27$2$60 Def00006C
+S A$dbglnkwru32$247 Def000095
+S A$dbglnkwru32$238 Def000088
+S A$dbglnkwru32$229 Def000082
+S A$dbglnkwru32$193 Def000057
+S A$dbglnkwru32$184 Def000045
+S A$dbglnkwru32$175 Def00003A
+S A$dbglnkwru32$166 Def00002F
+S A$dbglnkwru32$157 Def000024
+S A$dbglnkwru32$148 Def00001C
+S A$dbglnkwru32$139 Def000014
+S C$dbglnkwru32.c$28$2$60 Def000083
+S A$dbglnkwru32$239 Def00008A
+S A$dbglnkwru32$194 Def000058
+S A$dbglnkwru32$185 Def000047
+S A$dbglnkwru32$176 Def00003B
+S A$dbglnkwru32$167 Def000030
+S A$dbglnkwru32$158 Def000027
+S C$dbglnkwru32.c$31$1$59 Def000093
+S C$dbglnkwru32.c$29$2$60 Def000084
+S A$dbglnkwru32$195 Def00005A
+S A$dbglnkwru32$186 Def000048
+S A$dbglnkwru32$177 Def00003C
+S A$dbglnkwru32$168 Def000031
+S A$dbglnkwru32$159 Def000028
+S C$dbglnkwru32.c$32$1$59 Def000098
+S C$dbglnkwru32.c$23$1$59 Def000019
+S C$dbglnkwru32.c$21$1$0 Def000015
+S A$dbglnkwru32$196 Def00005C
+S A$dbglnkwru32$187 Def00004A
+S A$dbglnkwru32$178 Def00003D
+S A$dbglnkwru32$169 Def000032
+S C$dbglnkwru32.c$24$1$59 Def00001F
+S _dbglink_writeu32 Def000000
+S A$dbglnkwru32$197 Def00005E
+S A$dbglnkwru32$188 Def00004C
+S A$dbglnkwru32$179 Def00003E
+S A$dbglnkwru32$198 Def000061
+S A$dbglnkwru32$189 Def00004E
+S C$dbglnkwru32.c$26$1$59 Def000034
+S C$dbglnkwru32.c$25$2$59 Def000024
+S A$dbglnkwru32$199 Def000062
+S C$dbglnkwru32.c$19$0$0 Def000000
+S XG$dbglink_writeu32$0$0 Def000098
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 05
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 6F 90 00 01 E0 FA A3 E0 FB A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 2E FC A3 E0 FD 8A 01 90 00 00 74 0A F0 E4
+R 00 00 00 16 02 0A 00 00
+T 00 00 3B A3 F0 A3 F0 A3 F0 8A 82 8B 83 8C F0 ED
+R 00 00 00 16
+T 00 00 48 C0 07 C0 06 C0 01 12 00 00 AA 82 AB 83
+R 00 00 00 16 02 0A 00 03
+T 00 00 55 AC F0 FD D0 01 D0 06 D0 07 90 00 01 EA
+R 00 00 00 16 00 0D 00 0A
+T 00 00 62 F0 EB A3 F0 EC A3 F0 ED A3 F0 90 00 01
+R 00 00 00 16 00 0E 00 0A
+T 00 00 6F E0 FA A3 E0 FB A3 E0 FC A3 E0 FD EA 75
+R 00 00 00 16
+T 00 00 7C F0 0A A4 D3 99 F4 F9 1E 74 30 29 F9 C0
+R 00 00 00 16
+T 00 00 89 01 8E 82 12 00 00 15 81 80 8E
+R 00 00 00 16 02 07 00 04
+T 00 00 93
+R 00 00 00 16
+T 00 00 93 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 01
+
+
+M:dbglnkwru32
+F:G$dbglink_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Ldbglnkwru32.dbglink_writeu32$nrdig1$1$59({1}SC:U),R,0,0,[r7]
+S:Ldbglnkwru32.dbglink_writeu32$digit$1$59({1}SC:U),R,0,0,[r6]
+S:Ldbglnkwru32.dbglink_writeu32$v1$2$60({1}SC:U),R,0,0,[r1]
+S:Ldbglnkwru32.dbglink_writeu32$nrdig$1$58({1}SC:U),F,0,0
+S:Ldbglnkwru32.dbglink_writeu32$val$1$58({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrnum16
+
+;!FILE libmflarge/dbglnkwrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M dbglnkwrnum16
+O -mmcs51 --model-large
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S XG$dbglink_writenum16$0$0 Def0000F6
+S C$dbglnkwrnum16.c$240$1$61 Def000000
+S C$dbglnkwrnum16.c$241$1$61 Def0000F6
+S A$dbglnkwrnum16$200 Def000059
+S A$dbglnkwrnum16$300 Def0000D9
+S A$dbglnkwrnum16$210 Def000065
+S A$dbglnkwrnum16$201 Def00005A
+S A$dbglnkwrnum16$120 Def000005
+S A$dbglnkwrnum16$310 Def0000ED
+S A$dbglnkwrnum16$301 Def0000DC
+S A$dbglnkwrnum16$220 Def000070
+S A$dbglnkwrnum16$211 Def000066
+S A$dbglnkwrnum16$202 Def00005C
+S A$dbglnkwrnum16$121 Def000006
+S G$dbglink_writenum16$0$0 Def000000
+S A$dbglnkwrnum16$311 Def0000EF
+S A$dbglnkwrnum16$302 Def0000DD
+S A$dbglnkwrnum16$230 Def000080
+S A$dbglnkwrnum16$203 Def00005D
+S A$dbglnkwrnum16$140 Def000014
+S A$dbglnkwrnum16$122 Def000007
+S A$dbglnkwrnum16$312 Def0000F1
+S A$dbglnkwrnum16$303 Def0000DF
+S A$dbglnkwrnum16$240 Def000090
+S A$dbglnkwrnum16$231 Def000082
+S A$dbglnkwrnum16$213 Def000068
+S A$dbglnkwrnum16$204 Def00005E
+S A$dbglnkwrnum16$150 Def000026
+S A$dbglnkwrnum16$141 Def000016
+S A$dbglnkwrnum16$132 Def00000F
+S A$dbglnkwrnum16$123 Def000009
+S A$dbglnkwrnum16$241 Def000092
+S A$dbglnkwrnum16$205 Def000060
+S A$dbglnkwrnum16$142 Def000019
+S A$dbglnkwrnum16$314 Def0000F3
+S A$dbglnkwrnum16$305 Def0000E1
+S A$dbglnkwrnum16$242 Def000095
+S A$dbglnkwrnum16$233 Def000084
+S A$dbglnkwrnum16$224 Def000072
+S A$dbglnkwrnum16$215 Def00006B
+S A$dbglnkwrnum16$152 Def000028
+S A$dbglnkwrnum16$143 Def00001A
+S A$dbglnkwrnum16$125 Def00000B
+S A$dbglnkwrnum16$306 Def0000E3
+S A$dbglnkwrnum16$270 Def0000AE
+S A$dbglnkwrnum16$261 Def0000A4
+S A$dbglnkwrnum16$243 Def000098
+S A$dbglnkwrnum16$234 Def000087
+S A$dbglnkwrnum16$225 Def000074
+S A$dbglnkwrnum16$162 Def000036
+S A$dbglnkwrnum16$153 Def00002B
+S A$dbglnkwrnum16$144 Def00001B
+S A$dbglnkwrnum16$126 Def00000C
+S A$dbglnkwrnum16$117 Def000000
+S A$dbglnkwrnum16$316 Def0000F4
+S A$dbglnkwrnum16$307 Def0000E5
+S A$dbglnkwrnum16$280 Def0000BE
+S A$dbglnkwrnum16$244 Def00009A
+S A$dbglnkwrnum16$235 Def000088
+S A$dbglnkwrnum16$226 Def000076
+S A$dbglnkwrnum16$217 Def00006E
+S A$dbglnkwrnum16$208 Def000063
+S A$dbglnkwrnum16$163 Def000037
+S A$dbglnkwrnum16$154 Def00002E
+S A$dbglnkwrnum16$145 Def00001D
+S A$dbglnkwrnum16$118 Def000002
+S A$dbglnkwrnum16$308 Def0000E7
+S A$dbglnkwrnum16$290 Def0000C7
+S A$dbglnkwrnum16$281 Def0000C0
+S A$dbglnkwrnum16$272 Def0000B0
+S A$dbglnkwrnum16$263 Def0000A7
+S A$dbglnkwrnum16$245 Def00009C
+S A$dbglnkwrnum16$236 Def00008A
+S A$dbglnkwrnum16$227 Def000078
+S A$dbglnkwrnum16$218 Def00006F
+S A$dbglnkwrnum16$209 Def000064
+S A$dbglnkwrnum16$182 Def000047
+S A$dbglnkwrnum16$173 Def00003E
+S A$dbglnkwrnum16$164 Def000039
+S A$dbglnkwrnum16$155 Def000030
+S A$dbglnkwrnum16$146 Def00001F
+S A$dbglnkwrnum16$128 Def00000D
+S A$dbglnkwrnum16$119 Def000004
+S A$dbglnkwrnum16$309 Def0000EA
+S A$dbglnkwrnum16$291 Def0000C9
+S A$dbglnkwrnum16$282 Def0000C2
+S A$dbglnkwrnum16$273 Def0000B1
+S A$dbglnkwrnum16$255 Def00009F
+S A$dbglnkwrnum16$228 Def00007B
+S A$dbglnkwrnum16$192 Def00004E
+S A$dbglnkwrnum16$183 Def000048
+S A$dbglnkwrnum16$174 Def000041
+S A$dbglnkwrnum16$165 Def00003A
+S A$dbglnkwrnum16$156 Def000032
+S A$dbglnkwrnum16$147 Def000020
+S A$dbglnkwrnum16$292 Def0000CB
+S A$dbglnkwrnum16$265 Def0000AA
+S A$dbglnkwrnum16$247 Def00009E
+S A$dbglnkwrnum16$238 Def00008C
+S A$dbglnkwrnum16$229 Def00007E
+S A$dbglnkwrnum16$193 Def00004F
+S A$dbglnkwrnum16$184 Def000049
+S A$dbglnkwrnum16$175 Def000042
+S A$dbglnkwrnum16$166 Def00003C
+S A$dbglnkwrnum16$148 Def000022
+S A$dbglnkwrnum16$139 Def000011
+S A$dbglnkwrnum16$293 Def0000CC
+S A$dbglnkwrnum16$284 Def0000C4
+S A$dbglnkwrnum16$275 Def0000B3
+S A$dbglnkwrnum16$266 Def0000AB
+S A$dbglnkwrnum16$257 Def0000A1
+S A$dbglnkwrnum16$239 Def00008E
+S A$dbglnkwrnum16$185 Def00004A
+S A$dbglnkwrnum16$176 Def000044
+S A$dbglnkwrnum16$167 Def00003D
+S A$dbglnkwrnum16$158 Def000034
+S A$dbglnkwrnum16$149 Def000024
+S A$dbglnkwrnum16$294 Def0000CE
+S A$dbglnkwrnum16$276 Def0000B5
+S A$dbglnkwrnum16$258 Def0000A3
+S A$dbglnkwrnum16$195 Def000050
+S A$dbglnkwrnum16$186 Def00004C
+S A$dbglnkwrnum16$177 Def000046
+S A$dbglnkwrnum16$295 Def0000D0
+S A$dbglnkwrnum16$277 Def0000B7
+S A$dbglnkwrnum16$196 Def000052
+S A$dbglnkwrnum16$187 Def00004D
+S _dbglink_writenum16 Def000000
+S A$dbglnkwrnum16$296 Def0000D3
+S A$dbglnkwrnum16$278 Def0000B9
+S A$dbglnkwrnum16$269 Def0000AC
+S A$dbglnkwrnum16$197 Def000054
+S A$dbglnkwrnum16$297 Def0000D5
+S A$dbglnkwrnum16$279 Def0000BB
+S A$dbglnkwrnum16$198 Def000057
+S C$dbglnkwrnum16.c$25$0$0 Def000000
+S A$dbglnkwrnum16$298 Def0000D7
+S A$dbglnkwrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrnum16
+F:G$dbglink_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrnum16.dbglink_writenum16$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrnum16.dbglink_writenum16$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrnum16.dbglink_writenum16$val$1$60({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrnum32
+
+;!FILE libmflarge/dbglnkwrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M dbglnkwrnum32
+O -mmcs51 --model-large
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S XG$dbglink_writenum32$0$0 Def000128
+S A$dbglnkwrnum32$200 Def00005A
+S C$dbglnkwrnum32.c$276$1$61 Def000000
+S A$dbglnkwrnum32$300 Def0000D4
+S A$dbglnkwrnum32$210 Def000062
+S A$dbglnkwrnum32$201 Def00005C
+S A$dbglnkwrnum32$120 Def000005
+S C$dbglnkwrnum32.c$277$1$61 Def000128
+S A$dbglnkwrnum32$310 Def0000DD
+S A$dbglnkwrnum32$301 Def0000D5
+S A$dbglnkwrnum32$220 Def00006A
+S A$dbglnkwrnum32$211 Def000063
+S A$dbglnkwrnum32$130 Def000010
+S A$dbglnkwrnum32$121 Def000007
+S G$dbglink_writenum32$0$0 Def000000
+S A$dbglnkwrnum32$311 Def0000DF
+S A$dbglnkwrnum32$230 Def00007B
+S A$dbglnkwrnum32$221 Def00006C
+S A$dbglnkwrnum32$122 Def000008
+S A$dbglnkwrnum32$330 Def0000FA
+S A$dbglnkwrnum32$312 Def0000E1
+S A$dbglnkwrnum32$240 Def000087
+S A$dbglnkwrnum32$231 Def00007C
+S A$dbglnkwrnum32$222 Def00006E
+S A$dbglnkwrnum32$150 Def000024
+S A$dbglnkwrnum32$141 Def000014
+S A$dbglnkwrnum32$123 Def000009
+S A$dbglnkwrnum32$340 Def00010D
+S A$dbglnkwrnum32$331 Def0000FD
+S A$dbglnkwrnum32$313 Def0000E3
+S A$dbglnkwrnum32$304 Def0000D6
+S A$dbglnkwrnum32$250 Def000092
+S A$dbglnkwrnum32$241 Def000088
+S A$dbglnkwrnum32$232 Def00007E
+S A$dbglnkwrnum32$223 Def00006F
+S A$dbglnkwrnum32$160 Def000030
+S A$dbglnkwrnum32$151 Def000026
+S A$dbglnkwrnum32$142 Def000017
+S A$dbglnkwrnum32$124 Def00000A
+S A$dbglnkwrnum32$350 Def00011F
+S A$dbglnkwrnum32$341 Def00010F
+S A$dbglnkwrnum32$332 Def0000FF
+S A$dbglnkwrnum32$314 Def0000E5
+S A$dbglnkwrnum32$305 Def0000D8
+S A$dbglnkwrnum32$260 Def0000A2
+S A$dbglnkwrnum32$233 Def00007F
+S A$dbglnkwrnum32$224 Def000072
+S A$dbglnkwrnum32$206 Def00005D
+S A$dbglnkwrnum32$161 Def000033
+S A$dbglnkwrnum32$152 Def000027
+S A$dbglnkwrnum32$143 Def000018
+S A$dbglnkwrnum32$134 Def000012
+S A$dbglnkwrnum32$125 Def00000C
+S A$dbglnkwrnum32$116 Def000000
+S A$dbglnkwrnum32$351 Def000121
+S A$dbglnkwrnum32$342 Def000111
+S A$dbglnkwrnum32$333 Def000101
+S A$dbglnkwrnum32$324 Def0000EF
+S A$dbglnkwrnum32$315 Def0000E8
+S A$dbglnkwrnum32$270 Def0000B4
+S A$dbglnkwrnum32$261 Def0000A4
+S A$dbglnkwrnum32$243 Def00008A
+S A$dbglnkwrnum32$234 Def000080
+S A$dbglnkwrnum32$225 Def000073
+S A$dbglnkwrnum32$216 Def000064
+S A$dbglnkwrnum32$207 Def00005E
+S A$dbglnkwrnum32$162 Def000036
+S A$dbglnkwrnum32$153 Def000028
+S A$dbglnkwrnum32$144 Def00001B
+S A$dbglnkwrnum32$117 Def000001
+S A$dbglnkwrnum32$352 Def000123
+S A$dbglnkwrnum32$325 Def0000F1
+S A$dbglnkwrnum32$316 Def0000EA
+S A$dbglnkwrnum32$307 Def0000DA
+S A$dbglnkwrnum32$280 Def0000C6
+S A$dbglnkwrnum32$235 Def000082
+S A$dbglnkwrnum32$226 Def000075
+S A$dbglnkwrnum32$208 Def00005F
+S A$dbglnkwrnum32$190 Def00004E
+S A$dbglnkwrnum32$172 Def000040
+S A$dbglnkwrnum32$163 Def000038
+S A$dbglnkwrnum32$154 Def000029
+S A$dbglnkwrnum32$145 Def00001C
+S A$dbglnkwrnum32$127 Def00000E
+S A$dbglnkwrnum32$335 Def000103
+S A$dbglnkwrnum32$326 Def0000F3
+S A$dbglnkwrnum32$317 Def0000EC
+S A$dbglnkwrnum32$308 Def0000DB
+S A$dbglnkwrnum32$290 Def0000C9
+S A$dbglnkwrnum32$263 Def0000A6
+S A$dbglnkwrnum32$254 Def000094
+S A$dbglnkwrnum32$245 Def00008D
+S A$dbglnkwrnum32$227 Def000077
+S A$dbglnkwrnum32$218 Def000066
+S A$dbglnkwrnum32$209 Def000060
+S A$dbglnkwrnum32$191 Def000050
+S A$dbglnkwrnum32$173 Def000041
+S A$dbglnkwrnum32$164 Def00003A
+S A$dbglnkwrnum32$155 Def00002A
+S A$dbglnkwrnum32$146 Def00001D
+S A$dbglnkwrnum32$128 Def00000F
+S A$dbglnkwrnum32$119 Def000003
+S A$dbglnkwrnum32$354 Def000125
+S A$dbglnkwrnum32$345 Def000113
+S A$dbglnkwrnum32$336 Def000106
+S A$dbglnkwrnum32$327 Def0000F5
+S A$dbglnkwrnum32$282 Def0000C8
+S A$dbglnkwrnum32$273 Def0000B6
+S A$dbglnkwrnum32$264 Def0000A9
+S A$dbglnkwrnum32$255 Def000096
+S A$dbglnkwrnum32$228 Def000079
+S A$dbglnkwrnum32$219 Def000068
+S A$dbglnkwrnum32$174 Def000043
+S A$dbglnkwrnum32$165 Def00003B
+S A$dbglnkwrnum32$156 Def00002B
+S A$dbglnkwrnum32$147 Def00001F
+S A$dbglnkwrnum32$346 Def000115
+S A$dbglnkwrnum32$337 Def000107
+S A$dbglnkwrnum32$328 Def0000F6
+S A$dbglnkwrnum32$319 Def0000EE
+S A$dbglnkwrnum32$292 Def0000CB
+S A$dbglnkwrnum32$274 Def0000B8
+S A$dbglnkwrnum32$265 Def0000AA
+S A$dbglnkwrnum32$256 Def000098
+S A$dbglnkwrnum32$247 Def000090
+S A$dbglnkwrnum32$238 Def000085
+S A$dbglnkwrnum32$193 Def000051
+S A$dbglnkwrnum32$175 Def000044
+S A$dbglnkwrnum32$166 Def00003C
+S A$dbglnkwrnum32$157 Def00002C
+S A$dbglnkwrnum32$148 Def000021
+S A$dbglnkwrnum32$356 Def000126
+S A$dbglnkwrnum32$347 Def000117
+S A$dbglnkwrnum32$338 Def000109
+S A$dbglnkwrnum32$329 Def0000F8
+S A$dbglnkwrnum32$293 Def0000CD
+S A$dbglnkwrnum32$275 Def0000BA
+S A$dbglnkwrnum32$266 Def0000AC
+S A$dbglnkwrnum32$257 Def00009A
+S A$dbglnkwrnum32$248 Def000091
+S A$dbglnkwrnum32$239 Def000086
+S A$dbglnkwrnum32$194 Def000052
+S A$dbglnkwrnum32$176 Def000046
+S A$dbglnkwrnum32$158 Def00002E
+S A$dbglnkwrnum32$149 Def000022
+S A$dbglnkwrnum32$348 Def000119
+S A$dbglnkwrnum32$339 Def00010B
+S A$dbglnkwrnum32$276 Def0000BC
+S A$dbglnkwrnum32$267 Def0000AE
+S A$dbglnkwrnum32$258 Def00009D
+S A$dbglnkwrnum32$195 Def000054
+S A$dbglnkwrnum32$177 Def000047
+S A$dbglnkwrnum32$168 Def00003E
+S A$dbglnkwrnum32$349 Def00011C
+S A$dbglnkwrnum32$277 Def0000BF
+S A$dbglnkwrnum32$268 Def0000B0
+S A$dbglnkwrnum32$259 Def0000A0
+S A$dbglnkwrnum32$196 Def000056
+S A$dbglnkwrnum32$187 Def000048
+S _dbglink_writenum32 Def000000
+S A$dbglnkwrnum32$296 Def0000CE
+S A$dbglnkwrnum32$278 Def0000C2
+S A$dbglnkwrnum32$269 Def0000B2
+S A$dbglnkwrnum32$188 Def00004B
+S A$dbglnkwrnum32$279 Def0000C4
+S A$dbglnkwrnum32$198 Def000057
+S A$dbglnkwrnum32$189 Def00004C
+S C$dbglnkwrnum32.c$25$0$0 Def000000
+S A$dbglnkwrnum32$298 Def0000D1
+S A$dbglnkwrnum32$199 Def000058
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:dbglnkwrnum32
+F:G$dbglink_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrnum32.dbglink_writenum32$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrnum32.dbglink_writenum32$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrnum32.dbglink_writenum32$val$1$60({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhex16
+
+;!FILE libmflarge/dbglnkwrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M dbglnkwrhex16
+O -mmcs51 --model-large
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S C$dbglnkwrhex16.c$264$1$61 Def000000
+S C$dbglnkwrhex16.c$265$1$61 Def000111
+S A$dbglnkwrhex16$200 Def000058
+S A$dbglnkwrhex16$201 Def000059
+S A$dbglnkwrhex16$120 Def000005
+S A$dbglnkwrhex16$310 Def0000DB
+S A$dbglnkwrhex16$301 Def0000CB
+S A$dbglnkwrhex16$220 Def000069
+S A$dbglnkwrhex16$211 Def000063
+S A$dbglnkwrhex16$202 Def00005B
+S A$dbglnkwrhex16$121 Def000006
+S G$dbglink_writehex16$0$0 Def000000
+S A$dbglnkwrhex16$320 Def0000E4
+S A$dbglnkwrhex16$311 Def0000DD
+S A$dbglnkwrhex16$302 Def0000CC
+S A$dbglnkwrhex16$230 Def000075
+S A$dbglnkwrhex16$221 Def00006B
+S A$dbglnkwrhex16$203 Def00005D
+S A$dbglnkwrhex16$140 Def000014
+S A$dbglnkwrhex16$122 Def000007
+S A$dbglnkwrhex16$330 Def0000F7
+S A$dbglnkwrhex16$321 Def0000E6
+S A$dbglnkwrhex16$240 Def000081
+S A$dbglnkwrhex16$231 Def000077
+S A$dbglnkwrhex16$150 Def000026
+S A$dbglnkwrhex16$141 Def000016
+S A$dbglnkwrhex16$132 Def00000F
+S A$dbglnkwrhex16$123 Def000009
+S A$dbglnkwrhex16$340 Def00010A
+S A$dbglnkwrhex16$331 Def0000F8
+S A$dbglnkwrhex16$322 Def0000E7
+S A$dbglnkwrhex16$313 Def0000DF
+S A$dbglnkwrhex16$304 Def0000CE
+S A$dbglnkwrhex16$232 Def000078
+S A$dbglnkwrhex16$223 Def00006D
+S A$dbglnkwrhex16$205 Def00005F
+S A$dbglnkwrhex16$142 Def000019
+S A$dbglnkwrhex16$341 Def00010C
+S A$dbglnkwrhex16$332 Def0000FA
+S A$dbglnkwrhex16$323 Def0000E9
+S A$dbglnkwrhex16$305 Def0000D0
+S A$dbglnkwrhex16$260 Def00009D
+S A$dbglnkwrhex16$242 Def000083
+S A$dbglnkwrhex16$233 Def000079
+S A$dbglnkwrhex16$224 Def00006F
+S A$dbglnkwrhex16$152 Def000028
+S A$dbglnkwrhex16$143 Def00001A
+S A$dbglnkwrhex16$125 Def00000B
+S A$dbglnkwrhex16$324 Def0000EB
+S A$dbglnkwrhex16$306 Def0000D2
+S A$dbglnkwrhex16$270 Def0000AD
+S A$dbglnkwrhex16$234 Def00007B
+S A$dbglnkwrhex16$225 Def000072
+S A$dbglnkwrhex16$207 Def000060
+S A$dbglnkwrhex16$162 Def000036
+S A$dbglnkwrhex16$153 Def00002B
+S A$dbglnkwrhex16$144 Def00001B
+S A$dbglnkwrhex16$126 Def00000C
+S A$dbglnkwrhex16$117 Def000000
+S A$dbglnkwrhex16$343 Def00010E
+S A$dbglnkwrhex16$334 Def0000FC
+S A$dbglnkwrhex16$325 Def0000EE
+S A$dbglnkwrhex16$307 Def0000D4
+S A$dbglnkwrhex16$271 Def0000B0
+S A$dbglnkwrhex16$262 Def00009F
+S A$dbglnkwrhex16$253 Def00008D
+S A$dbglnkwrhex16$244 Def000086
+S A$dbglnkwrhex16$208 Def000062
+S A$dbglnkwrhex16$163 Def000037
+S A$dbglnkwrhex16$154 Def00002E
+S A$dbglnkwrhex16$145 Def00001D
+S A$dbglnkwrhex16$118 Def000002
+S A$dbglnkwrhex16$335 Def0000FE
+S A$dbglnkwrhex16$326 Def0000F0
+S A$dbglnkwrhex16$308 Def0000D6
+S A$dbglnkwrhex16$290 Def0000BF
+S A$dbglnkwrhex16$272 Def0000B3
+S A$dbglnkwrhex16$263 Def0000A2
+S A$dbglnkwrhex16$254 Def00008F
+S A$dbglnkwrhex16$227 Def000074
+S A$dbglnkwrhex16$218 Def000065
+S A$dbglnkwrhex16$182 Def000047
+S A$dbglnkwrhex16$173 Def00003E
+S A$dbglnkwrhex16$164 Def000039
+S A$dbglnkwrhex16$155 Def000030
+S A$dbglnkwrhex16$146 Def00001F
+S A$dbglnkwrhex16$128 Def00000D
+S A$dbglnkwrhex16$119 Def000004
+S A$dbglnkwrhex16$345 Def00010F
+S A$dbglnkwrhex16$336 Def000100
+S A$dbglnkwrhex16$327 Def0000F2
+S A$dbglnkwrhex16$318 Def0000E0
+S A$dbglnkwrhex16$309 Def0000D9
+S A$dbglnkwrhex16$273 Def0000B5
+S A$dbglnkwrhex16$264 Def0000A3
+S A$dbglnkwrhex16$255 Def000091
+S A$dbglnkwrhex16$246 Def000089
+S A$dbglnkwrhex16$237 Def00007E
+S A$dbglnkwrhex16$219 Def000067
+S A$dbglnkwrhex16$192 Def00004E
+S A$dbglnkwrhex16$183 Def000048
+S A$dbglnkwrhex16$174 Def000041
+S A$dbglnkwrhex16$165 Def00003A
+S A$dbglnkwrhex16$156 Def000032
+S A$dbglnkwrhex16$147 Def000020
+S A$dbglnkwrhex16$337 Def000102
+S A$dbglnkwrhex16$319 Def0000E2
+S A$dbglnkwrhex16$292 Def0000C2
+S A$dbglnkwrhex16$274 Def0000B7
+S A$dbglnkwrhex16$265 Def0000A5
+S A$dbglnkwrhex16$256 Def000093
+S A$dbglnkwrhex16$247 Def00008A
+S A$dbglnkwrhex16$238 Def00007F
+S A$dbglnkwrhex16$193 Def00004F
+S A$dbglnkwrhex16$184 Def000049
+S A$dbglnkwrhex16$175 Def000042
+S A$dbglnkwrhex16$166 Def00003C
+S A$dbglnkwrhex16$148 Def000022
+S A$dbglnkwrhex16$139 Def000011
+S A$dbglnkwrhex16$338 Def000105
+S A$dbglnkwrhex16$329 Def0000F4
+S A$dbglnkwrhex16$284 Def0000BA
+S A$dbglnkwrhex16$257 Def000096
+S A$dbglnkwrhex16$239 Def000080
+S A$dbglnkwrhex16$194 Def000050
+S A$dbglnkwrhex16$185 Def00004A
+S A$dbglnkwrhex16$176 Def000044
+S A$dbglnkwrhex16$167 Def00003D
+S A$dbglnkwrhex16$158 Def000034
+S A$dbglnkwrhex16$149 Def000024
+S A$dbglnkwrhex16$339 Def000108
+S A$dbglnkwrhex16$294 Def0000C5
+S A$dbglnkwrhex16$276 Def0000B9
+S A$dbglnkwrhex16$267 Def0000A7
+S A$dbglnkwrhex16$258 Def000099
+S A$dbglnkwrhex16$249 Def00008B
+S A$dbglnkwrhex16$195 Def000051
+S A$dbglnkwrhex16$186 Def00004C
+S A$dbglnkwrhex16$177 Def000046
+S A$dbglnkwrhex16$295 Def0000C6
+S A$dbglnkwrhex16$286 Def0000BC
+S A$dbglnkwrhex16$268 Def0000A9
+S A$dbglnkwrhex16$259 Def00009B
+S A$dbglnkwrhex16$196 Def000052
+S A$dbglnkwrhex16$187 Def00004D
+S _dbglink_writehex16 Def000000
+S A$dbglnkwrhex16$287 Def0000BE
+S A$dbglnkwrhex16$269 Def0000AB
+S A$dbglnkwrhex16$197 Def000054
+S A$dbglnkwrhex16$198 Def000056
+S C$dbglnkwrhex16.c$25$0$0 Def000000
+S A$dbglnkwrhex16$298 Def0000C7
+S A$dbglnkwrhex16$299 Def0000C9
+S XG$dbglink_writehex16$0$0 Def000111
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrhex16
+F:G$dbglink_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrhex16.dbglink_writehex16$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrhex16.dbglink_writehex16$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrhex16.dbglink_writehex16$val$1$60({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+dbglnkwrhex32
+
+;!FILE libmflarge/dbglnkwrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M dbglnkwrhex32
+O -mmcs51 --model-large
+S _dbglink_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S C$dbglnkwrhex32.c$282$1$61 Def000000
+S C$dbglnkwrhex32.c$283$1$61 Def000127
+S A$dbglnkwrhex32$210 Def000062
+S A$dbglnkwrhex32$120 Def000005
+S A$dbglnkwrhex32$310 Def0000D5
+S A$dbglnkwrhex32$220 Def00006F
+S A$dbglnkwrhex32$211 Def000063
+S A$dbglnkwrhex32$202 Def000058
+S A$dbglnkwrhex32$130 Def000010
+S A$dbglnkwrhex32$121 Def000007
+S G$dbglink_writehex32$0$0 Def000000
+S A$dbglnkwrhex32$221 Def000070
+S A$dbglnkwrhex32$212 Def000065
+S A$dbglnkwrhex32$203 Def000059
+S A$dbglnkwrhex32$122 Def000008
+S A$dbglnkwrhex32$330 Def0000F1
+S A$dbglnkwrhex32$321 Def0000E1
+S A$dbglnkwrhex32$312 Def0000D8
+S A$dbglnkwrhex32$240 Def00007F
+S A$dbglnkwrhex32$231 Def000079
+S A$dbglnkwrhex32$222 Def000072
+S A$dbglnkwrhex32$213 Def000067
+S A$dbglnkwrhex32$204 Def00005A
+S A$dbglnkwrhex32$150 Def000024
+S A$dbglnkwrhex32$141 Def000014
+S A$dbglnkwrhex32$123 Def000009
+S A$dbglnkwrhex32$340 Def0000FA
+S A$dbglnkwrhex32$331 Def0000F3
+S A$dbglnkwrhex32$322 Def0000E2
+S A$dbglnkwrhex32$304 Def0000D0
+S A$dbglnkwrhex32$250 Def00008B
+S A$dbglnkwrhex32$241 Def000081
+S A$dbglnkwrhex32$223 Def000073
+S A$dbglnkwrhex32$205 Def00005B
+S A$dbglnkwrhex32$160 Def000030
+S A$dbglnkwrhex32$151 Def000026
+S A$dbglnkwrhex32$142 Def000017
+S A$dbglnkwrhex32$124 Def00000A
+S A$dbglnkwrhex32$350 Def00010D
+S A$dbglnkwrhex32$341 Def0000FC
+S A$dbglnkwrhex32$314 Def0000DB
+S A$dbglnkwrhex32$260 Def000097
+S A$dbglnkwrhex32$251 Def00008D
+S A$dbglnkwrhex32$215 Def000069
+S A$dbglnkwrhex32$206 Def00005C
+S A$dbglnkwrhex32$161 Def000033
+S A$dbglnkwrhex32$152 Def000027
+S A$dbglnkwrhex32$143 Def000018
+S A$dbglnkwrhex32$134 Def000012
+S A$dbglnkwrhex32$125 Def00000C
+S A$dbglnkwrhex32$116 Def000000
+S A$dbglnkwrhex32$360 Def000120
+S A$dbglnkwrhex32$351 Def00010E
+S A$dbglnkwrhex32$342 Def0000FD
+S A$dbglnkwrhex32$333 Def0000F5
+S A$dbglnkwrhex32$324 Def0000E4
+S A$dbglnkwrhex32$315 Def0000DC
+S A$dbglnkwrhex32$306 Def0000D2
+S A$dbglnkwrhex32$252 Def00008E
+S A$dbglnkwrhex32$243 Def000083
+S A$dbglnkwrhex32$225 Def000075
+S A$dbglnkwrhex32$216 Def00006A
+S A$dbglnkwrhex32$207 Def00005E
+S A$dbglnkwrhex32$162 Def000036
+S A$dbglnkwrhex32$153 Def000028
+S A$dbglnkwrhex32$144 Def00001B
+S A$dbglnkwrhex32$117 Def000001
+S A$dbglnkwrhex32$361 Def000122
+S A$dbglnkwrhex32$352 Def000110
+S A$dbglnkwrhex32$343 Def0000FF
+S A$dbglnkwrhex32$325 Def0000E6
+S A$dbglnkwrhex32$307 Def0000D4
+S A$dbglnkwrhex32$280 Def0000B3
+S A$dbglnkwrhex32$262 Def000099
+S A$dbglnkwrhex32$253 Def00008F
+S A$dbglnkwrhex32$244 Def000085
+S A$dbglnkwrhex32$217 Def00006C
+S A$dbglnkwrhex32$208 Def000060
+S A$dbglnkwrhex32$172 Def000040
+S A$dbglnkwrhex32$163 Def000038
+S A$dbglnkwrhex32$154 Def000029
+S A$dbglnkwrhex32$145 Def00001C
+S A$dbglnkwrhex32$127 Def00000E
+S A$dbglnkwrhex32$344 Def000101
+S A$dbglnkwrhex32$326 Def0000E8
+S A$dbglnkwrhex32$290 Def0000C3
+S A$dbglnkwrhex32$254 Def000091
+S A$dbglnkwrhex32$245 Def000088
+S A$dbglnkwrhex32$227 Def000076
+S A$dbglnkwrhex32$218 Def00006D
+S A$dbglnkwrhex32$173 Def000041
+S A$dbglnkwrhex32$164 Def00003A
+S A$dbglnkwrhex32$155 Def00002A
+S A$dbglnkwrhex32$146 Def00001D
+S A$dbglnkwrhex32$128 Def00000F
+S A$dbglnkwrhex32$119 Def000003
+S A$dbglnkwrhex32$363 Def000124
+S A$dbglnkwrhex32$354 Def000112
+S A$dbglnkwrhex32$345 Def000104
+S A$dbglnkwrhex32$327 Def0000EA
+S A$dbglnkwrhex32$318 Def0000DD
+S A$dbglnkwrhex32$291 Def0000C6
+S A$dbglnkwrhex32$282 Def0000B5
+S A$dbglnkwrhex32$273 Def0000A3
+S A$dbglnkwrhex32$264 Def00009C
+S A$dbglnkwrhex32$228 Def000078
+S A$dbglnkwrhex32$192 Def000051
+S A$dbglnkwrhex32$183 Def000048
+S A$dbglnkwrhex32$174 Def000043
+S A$dbglnkwrhex32$165 Def00003B
+S A$dbglnkwrhex32$156 Def00002B
+S A$dbglnkwrhex32$147 Def00001F
+S A$dbglnkwrhex32$355 Def000114
+S A$dbglnkwrhex32$346 Def000106
+S A$dbglnkwrhex32$328 Def0000EC
+S A$dbglnkwrhex32$319 Def0000DF
+S A$dbglnkwrhex32$292 Def0000C9
+S A$dbglnkwrhex32$283 Def0000B8
+S A$dbglnkwrhex32$274 Def0000A5
+S A$dbglnkwrhex32$247 Def00008A
+S A$dbglnkwrhex32$238 Def00007B
+S A$dbglnkwrhex32$193 Def000052
+S A$dbglnkwrhex32$184 Def00004B
+S A$dbglnkwrhex32$175 Def000044
+S A$dbglnkwrhex32$166 Def00003C
+S A$dbglnkwrhex32$157 Def00002C
+S A$dbglnkwrhex32$148 Def000021
+S A$dbglnkwrhex32$365 Def000125
+S A$dbglnkwrhex32$356 Def000116
+S A$dbglnkwrhex32$347 Def000108
+S A$dbglnkwrhex32$338 Def0000F6
+S A$dbglnkwrhex32$329 Def0000EF
+S A$dbglnkwrhex32$293 Def0000CB
+S A$dbglnkwrhex32$284 Def0000B9
+S A$dbglnkwrhex32$275 Def0000A7
+S A$dbglnkwrhex32$266 Def00009F
+S A$dbglnkwrhex32$257 Def000094
+S A$dbglnkwrhex32$239 Def00007D
+S A$dbglnkwrhex32$194 Def000053
+S A$dbglnkwrhex32$185 Def00004C
+S A$dbglnkwrhex32$176 Def000046
+S A$dbglnkwrhex32$158 Def00002E
+S A$dbglnkwrhex32$149 Def000022
+S A$dbglnkwrhex32$357 Def000118
+S A$dbglnkwrhex32$339 Def0000F8
+S A$dbglnkwrhex32$294 Def0000CD
+S A$dbglnkwrhex32$285 Def0000BB
+S A$dbglnkwrhex32$276 Def0000A9
+S A$dbglnkwrhex32$267 Def0000A0
+S A$dbglnkwrhex32$258 Def000095
+S A$dbglnkwrhex32$195 Def000054
+S A$dbglnkwrhex32$186 Def00004E
+S A$dbglnkwrhex32$177 Def000047
+S A$dbglnkwrhex32$168 Def00003E
+S A$dbglnkwrhex32$358 Def00011B
+S A$dbglnkwrhex32$349 Def00010A
+S A$dbglnkwrhex32$277 Def0000AC
+S A$dbglnkwrhex32$259 Def000096
+S A$dbglnkwrhex32$196 Def000056
+S A$dbglnkwrhex32$187 Def000050
+S _dbglink_writehex32 Def000000
+S A$dbglnkwrhex32$359 Def00011E
+S A$dbglnkwrhex32$296 Def0000CF
+S A$dbglnkwrhex32$287 Def0000BD
+S A$dbglnkwrhex32$278 Def0000AF
+S A$dbglnkwrhex32$269 Def0000A1
+S A$dbglnkwrhex32$197 Def000057
+S A$dbglnkwrhex32$288 Def0000BF
+S A$dbglnkwrhex32$279 Def0000B1
+S C$dbglnkwrhex32.c$25$0$0 Def000000
+S A$dbglnkwrhex32$289 Def0000C1
+S XG$dbglink_writehex32$0$0 Def000127
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:dbglnkwrhex32
+F:G$dbglink_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Ldbglnkwrhex32.dbglink_writehex32$nrdig1$1$60({1}SC:U),B,1,-3
+S:Ldbglnkwrhex32.dbglink_writehex32$flags1$1$60({1}SC:U),B,1,-4
+S:Ldbglnkwrhex32.dbglink_writehex32$val$1$60({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+crc8ccitt
+
+;!FILE libmflarge/crc8ccitt.asm
+XH3
+H 1A areas 320 global symbols
+M crc8ccitt
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 72 flags 20 addr 0
+S C$crc8ccitt.c$7$0$0 Def000000
+S _crc8_ccitt Def000014
+S G$crc8_ccitt_byte$0$0 Def000000
+S XG$crc8_ccitt$0$0 Def000072
+S A$crc8ccitt$1220 Def00001D
+S A$crc8ccitt$1221 Def000020
+S A$crc8ccitt$1212 Def000014
+S A$crc8ccitt$1231 Def00002D
+S A$crc8ccitt$1222 Def000023
+S A$crc8ccitt$1213 Def000016
+S A$crc8ccitt$1250 Def000042
+S A$crc8ccitt$1232 Def00002E
+S A$crc8ccitt$1223 Def000025
+S A$crc8ccitt$1214 Def000017
+S _crc8_ccitt_byte Def000000
+S A$crc8ccitt$1260 Def00004E
+S A$crc8ccitt$1251 Def000044
+S A$crc8ccitt$1242 Def00003A
+S A$crc8ccitt$1233 Def00002F
+S A$crc8ccitt$1215 Def000018
+S A$crc8ccitt$1270 Def00005A
+S A$crc8ccitt$1261 Def00004F
+S A$crc8ccitt$1243 Def00003B
+S A$crc8ccitt$1234 Def000031
+S A$crc8ccitt$1216 Def000019
+S A$crc8ccitt$1180 Def000005
+S A$crc8ccitt$1280 Def000064
+S A$crc8ccitt$1271 Def00005B
+S A$crc8ccitt$1262 Def000050
+S A$crc8ccitt$1253 Def000046
+S A$crc8ccitt$1244 Def00003C
+S A$crc8ccitt$1226 Def000028
+S A$crc8ccitt$1217 Def00001A
+S A$crc8ccitt$1190 Def000013
+S A$crc8ccitt$1181 Def000007
+S A$crc8ccitt$1290 Def00006F
+S A$crc8ccitt$1281 Def000065
+S A$crc8ccitt$1272 Def00005D
+S A$crc8ccitt$1254 Def000048
+S A$crc8ccitt$1245 Def00003D
+S A$crc8ccitt$1236 Def000033
+S A$crc8ccitt$1227 Def000029
+S A$crc8ccitt$1218 Def00001B
+S A$crc8ccitt$1291 Def000071
+S A$crc8ccitt$1282 Def000066
+S A$crc8ccitt$1264 Def000052
+S A$crc8ccitt$1255 Def000049
+S A$crc8ccitt$1246 Def00003E
+S A$crc8ccitt$1237 Def000035
+S A$crc8ccitt$1228 Def00002A
+S A$crc8ccitt$1219 Def00001C
+S A$crc8ccitt$1183 Def000009
+S C$crc8ccitt.c$105$1$65 Def000014
+S A$crc8ccitt$1283 Def000068
+S A$crc8ccitt$1265 Def000053
+S A$crc8ccitt$1256 Def00004B
+S A$crc8ccitt$1238 Def000036
+S A$crc8ccitt$1229 Def00002B
+S A$crc8ccitt$1184 Def00000A
+S C$crc8ccitt.c$106$1$65 Def000072
+S A$crc8ccitt$1275 Def00005F
+S A$crc8ccitt$1266 Def000054
+S A$crc8ccitt$1248 Def000040
+S A$crc8ccitt$1239 Def000038
+S A$crc8ccitt$1185 Def00000B
+S A$crc8ccitt$1176 Def000000
+S A$crc8ccitt$1285 Def00006A
+S A$crc8ccitt$1276 Def000060
+S A$crc8ccitt$1267 Def000056
+S A$crc8ccitt$1249 Def000041
+S A$crc8ccitt$1186 Def00000D
+S A$crc8ccitt$1177 Def000002
+S A$crc8ccitt$1286 Def00006C
+S A$crc8ccitt$1277 Def000061
+S A$crc8ccitt$1259 Def00004D
+S A$crc8ccitt$1178 Def000003
+S A$crc8ccitt$1287 Def00006D
+S A$crc8ccitt$1278 Def000062
+S A$crc8ccitt$1269 Def000058
+S A$crc8ccitt$1188 Def00000F
+S A$crc8ccitt$1179 Def000004
+S A$crc8ccitt$1189 Def000011
+S XG$crc8_ccitt_byte$0$0 Def000014
+S C$crc8ccitt.c$25$1$63 Def000000
+S C$crc8ccitt.c$26$1$63 Def000014
+S C$crc8ccitt.c$28$1$63 Def000014
+S G$crc8_ccitt$0$0 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 E6 65 82 78 08
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F D8 F8 F5 82 22
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 A8 81 18 18 E6 FA 18 E6 FB 20 F7 1A 30
+R 00 00 00 16
+T 00 00 21 F6 2A A8 82 20 F5 37
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6B 7C 08
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 33
+R 00 00 00 16
+T 00 00 33 DC F8 FB DA F0 80 35
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A E4 93 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 46
+R 00 00 00 16
+T 00 00 46 DC F8 FB DA EF 80 22
+R 00 00 00 16
+T 00 00 4D
+R 00 00 00 16
+T 00 00 4D E0 A3 6B 7C 08
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 DC F8 FB DA F0 80 10
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E2 08 6B 7C 08
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C3 33 50 02 64 07
+R 00 00 00 16
+T 00 00 6A
+R 00 00 00 16
+T 00 00 6A DC F8 FB DA F0
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 8B 82 22
+R 00 00 00 16
+
+
+M:crc8ccitt
+F:G$crc8_ccitt_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccitt.crc8_ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8ccitt.crc8_ccitt_byte$crc$1$62({1}SC:U),R,0,0,[]
+F:G$crc8_ccitt$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccitt.crc8_ccitt$len$1$64({1}SC:U),B,1,-3
+S:Lcrc8ccitt.crc8_ccitt$init$1$64({1}SC:U),B,1,-4
+S:Lcrc8ccitt.crc8_ccitt$buf$1$64({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
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+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewire
+
+;!FILE libmflarge/crc8onewire.asm
+XH3
+H 1A areas 320 global symbols
+M crc8onewire
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
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+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
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+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
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+S _LPOSCPER0 Def007068
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+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
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+S _ADCCH3VAL0 Def007026
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+S _T0CNT0 Def00009C
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+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
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+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
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+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
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+S G$ADCCH1VAL$0$0 Def007022
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+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
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+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
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+S G$T0STATUS$0$0 Def00009B
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+S G$FRCOSCKFILT1$0$0 Def007073
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+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
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+S G$IP_4$0$0 Def0000BC
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+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
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+
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+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tccitt
+
+;!FILE libmflarge/crc8tccitt.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tccitt
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc8ccitt_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S G$crc_crc8ccitt_byte$0$0 Def000000
+S _crc_crc8ccitt_byte Def000000
+S A$crc8tccitt$110 Def000005
+S A$crc8tccitt$111 Def000006
+S A$crc8tccitt$112 Def000008
+S A$crc8tccitt$113 Def00000B
+S A$crc8tccitt$114 Def00000C
+S A$crc8tccitt$115 Def00000E
+S A$crc8tccitt$107 Def000000
+S XG$crc_crc8ccitt_byte$0$0 Def00000F
+S A$crc8tccitt$108 Def000002
+S A$crc8tccitt$109 Def000004
+S C$crc8tccitt.c$23$1$63 Def000000
+S C$crc8tccitt.c$24$1$63 Def00000F
+S C$crc8tccitt.c$9$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 01
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tccitt
+F:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tccitt.crc_crc8ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tccitt.crc_crc8ccitt_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tccittmsb
+
+;!FILE libmflarge/crc8tccittmsb.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tccittmsb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc8ccitt_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tccittmsb$110 Def000005
+S A$crc8tccittmsb$111 Def000006
+S A$crc8tccittmsb$112 Def000008
+S A$crc8tccittmsb$113 Def00000B
+S A$crc8tccittmsb$114 Def00000C
+S A$crc8tccittmsb$115 Def00000E
+S A$crc8tccittmsb$107 Def000000
+S A$crc8tccittmsb$108 Def000002
+S A$crc8tccittmsb$109 Def000004
+S C$crc8tccittmsb.c$23$1$63 Def000000
+S C$crc8tccittmsb.c$24$1$63 Def00000F
+S G$crc_crc8ccitt_msb_byte$0$0 Def000000
+S _crc_crc8ccitt_msb_byte Def000000
+S C$crc8tccittmsb.c$9$0$0 Def000000
+S XG$crc_crc8ccitt_msb_byte$0$0 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 01
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tccittmsb
+F:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tccittmsb.crc_crc8ccitt_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tccittmsb.crc_crc8ccitt_msb_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tonewire
+
+;!FILE libmflarge/crc8tonewire.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tonewire
+O -mmcs51 --model-large
+S _crc_crc8onewire_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tonewire$109 Def000004
+S C$crc8tonewire.c$23$1$63 Def000000
+S C$crc8tonewire.c$24$1$63 Def00000F
+S C$crc8tonewire.c$9$0$0 Def000000
+S G$crc_crc8onewire_byte$0$0 Def000000
+S _crc_crc8onewire_byte Def000000
+S A$crc8tonewire$110 Def000005
+S A$crc8tonewire$111 Def000006
+S A$crc8tonewire$112 Def000008
+S A$crc8tonewire$113 Def00000B
+S A$crc8tonewire$114 Def00000C
+S A$crc8tonewire$115 Def00000E
+S A$crc8tonewire$107 Def000000
+S XG$crc_crc8onewire_byte$0$0 Def00000F
+S A$crc8tonewire$108 Def000002
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 00
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tonewire
+F:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tonewire.crc_crc8onewire_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tonewire.crc_crc8onewire_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8tonewiremsb
+
+;!FILE libmflarge/crc8tonewiremsb.asm
+XH3
+H 1A areas 11 global symbols
+M crc8tonewiremsb
+O -mmcs51 --model-large
+S _crc_crc8onewire_msbtable Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S A$crc8tonewiremsb$107 Def000000
+S A$crc8tonewiremsb$108 Def000002
+S A$crc8tonewiremsb$109 Def000004
+S C$crc8tonewiremsb.c$23$1$63 Def000000
+S C$crc8tonewiremsb.c$24$1$63 Def00000F
+S G$crc_crc8onewire_msb_byte$0$0 Def000000
+S _crc_crc8onewire_msb_byte Def000000
+S C$crc8tonewiremsb.c$9$0$0 Def000000
+S XG$crc_crc8onewire_msb_byte$0$0 Def00000F
+S A$crc8tonewiremsb$110 Def000005
+S A$crc8tonewiremsb$111 Def000006
+S A$crc8tonewiremsb$112 Def000008
+S A$crc8tonewiremsb$113 Def00000B
+S A$crc8tonewiremsb$114 Def00000C
+S A$crc8tonewiremsb$115 Def00000E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 90 00 00 93 F5
+R 00 00 00 16 02 0C 00 00
+T 00 00 0D 82 22
+R 00 00 00 16
+
+
+M:crc8tonewiremsb
+F:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8tonewiremsb.crc_crc8onewire_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc8tonewiremsb.crc_crc8onewire_msb_byte$crc$1$62({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittb
+
+;!FILE libmflarge/crc8ccittb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8ccittb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc8ccitt_table Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S A$crc8ccittb$110 Def000004
+S A$crc8ccittb$120 Def00000E
+S A$crc8ccittb$111 Def000005
+S A$crc8ccittb$121 Def000010
+S A$crc8ccittb$112 Def000006
+S A$crc8ccittb$140 Def000029
+S A$crc8ccittb$131 Def00001F
+S A$crc8ccittb$122 Def000011
+S A$crc8ccittb$113 Def000007
+S A$crc8ccittb$141 Def00002B
+S A$crc8ccittb$132 Def000020
+S A$crc8ccittb$123 Def000013
+S A$crc8ccittb$114 Def000008
+S A$crc8ccittb$160 Def000040
+S A$crc8ccittb$151 Def000035
+S A$crc8ccittb$115 Def000009
+S XG$crc_crc8ccitt$0$0 Def000069
+S A$crc8ccittb$170 Def00004E
+S A$crc8ccittb$152 Def000037
+S A$crc8ccittb$143 Def00002D
+S A$crc8ccittb$134 Def000021
+S A$crc8ccittb$125 Def000014
+S A$crc8ccittb$116 Def00000A
+S A$crc8ccittb$180 Def00005A
+S A$crc8ccittb$171 Def000050
+S A$crc8ccittb$162 Def000042
+S A$crc8ccittb$144 Def00002E
+S A$crc8ccittb$135 Def000022
+S A$crc8ccittb$126 Def000017
+S A$crc8ccittb$117 Def00000B
+S A$crc8ccittb$108 Def000000
+S A$crc8ccittb$181 Def00005D
+S A$crc8ccittb$163 Def000043
+S A$crc8ccittb$154 Def000039
+S A$crc8ccittb$136 Def000025
+S A$crc8ccittb$127 Def00001A
+S A$crc8ccittb$118 Def00000C
+S A$crc8ccittb$109 Def000002
+S A$crc8ccittb$182 Def00005E
+S A$crc8ccittb$173 Def000052
+S A$crc8ccittb$164 Def000046
+S A$crc8ccittb$155 Def00003B
+S A$crc8ccittb$146 Def00002F
+S A$crc8ccittb$137 Def000026
+S A$crc8ccittb$128 Def00001C
+S A$crc8ccittb$119 Def00000D
+S A$crc8ccittb$174 Def000053
+S A$crc8ccittb$165 Def000047
+S A$crc8ccittb$147 Def000030
+S C$crc8ccittb.c$10$0$0 Def000000
+S A$crc8ccittb$184 Def00005F
+S A$crc8ccittb$175 Def000054
+S A$crc8ccittb$157 Def00003C
+S A$crc8ccittb$148 Def000033
+S A$crc8ccittb$139 Def000027
+S A$crc8ccittb$185 Def000061
+S A$crc8ccittb$176 Def000055
+S A$crc8ccittb$167 Def000048
+S A$crc8ccittb$158 Def00003D
+S A$crc8ccittb$149 Def000034
+S A$crc8ccittb$186 Def000063
+S A$crc8ccittb$177 Def000057
+S A$crc8ccittb$168 Def00004A
+S A$crc8ccittb$159 Def00003E
+S A$crc8ccittb$187 Def000065
+S A$crc8ccittb$169 Def00004C
+S A$crc8ccittb$188 Def000067
+S A$crc8ccittb$179 Def000059
+S C$crc8ccittb.c$96$1$63 Def000000
+S C$crc8ccittb.c$97$1$63 Def000069
+S G$crc_crc8ccitt$0$0 Def000000
+S _crc_crc8ccitt Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 01
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 01
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 01
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 01
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8ccittb
+F:G$crc_crc8ccitt$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccittb.crc_crc8ccitt$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8ccittb.crc_crc8ccitt$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8ccittb.crc_crc8ccitt$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittmsbb
+
+;!FILE libmflarge/crc8ccittmsbb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8ccittmsbb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc8ccitt_msbtable Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S A$crc8ccittmsbb$110 Def000004
+S A$crc8ccittmsbb$120 Def00000E
+S A$crc8ccittmsbb$111 Def000005
+S A$crc8ccittmsbb$121 Def000010
+S A$crc8ccittmsbb$112 Def000006
+S A$crc8ccittmsbb$140 Def000029
+S A$crc8ccittmsbb$131 Def00001F
+S A$crc8ccittmsbb$122 Def000011
+S A$crc8ccittmsbb$113 Def000007
+S A$crc8ccittmsbb$141 Def00002B
+S A$crc8ccittmsbb$132 Def000020
+S A$crc8ccittmsbb$123 Def000013
+S A$crc8ccittmsbb$114 Def000008
+S A$crc8ccittmsbb$160 Def000040
+S A$crc8ccittmsbb$151 Def000035
+S A$crc8ccittmsbb$115 Def000009
+S A$crc8ccittmsbb$170 Def00004E
+S A$crc8ccittmsbb$152 Def000037
+S A$crc8ccittmsbb$143 Def00002D
+S A$crc8ccittmsbb$134 Def000021
+S A$crc8ccittmsbb$125 Def000014
+S A$crc8ccittmsbb$116 Def00000A
+S A$crc8ccittmsbb$180 Def00005A
+S A$crc8ccittmsbb$171 Def000050
+S A$crc8ccittmsbb$162 Def000042
+S A$crc8ccittmsbb$144 Def00002E
+S A$crc8ccittmsbb$135 Def000022
+S A$crc8ccittmsbb$126 Def000017
+S A$crc8ccittmsbb$117 Def00000B
+S A$crc8ccittmsbb$108 Def000000
+S A$crc8ccittmsbb$181 Def00005D
+S A$crc8ccittmsbb$163 Def000043
+S A$crc8ccittmsbb$154 Def000039
+S A$crc8ccittmsbb$136 Def000025
+S A$crc8ccittmsbb$127 Def00001A
+S A$crc8ccittmsbb$118 Def00000C
+S A$crc8ccittmsbb$109 Def000002
+S A$crc8ccittmsbb$182 Def00005E
+S A$crc8ccittmsbb$173 Def000052
+S A$crc8ccittmsbb$164 Def000046
+S A$crc8ccittmsbb$155 Def00003B
+S A$crc8ccittmsbb$146 Def00002F
+S A$crc8ccittmsbb$137 Def000026
+S A$crc8ccittmsbb$128 Def00001C
+S A$crc8ccittmsbb$119 Def00000D
+S A$crc8ccittmsbb$174 Def000053
+S A$crc8ccittmsbb$165 Def000047
+S A$crc8ccittmsbb$147 Def000030
+S C$crc8ccittmsbb.c$10$0$0 Def000000
+S A$crc8ccittmsbb$184 Def00005F
+S A$crc8ccittmsbb$175 Def000054
+S A$crc8ccittmsbb$157 Def00003C
+S A$crc8ccittmsbb$148 Def000033
+S A$crc8ccittmsbb$139 Def000027
+S A$crc8ccittmsbb$185 Def000061
+S A$crc8ccittmsbb$176 Def000055
+S A$crc8ccittmsbb$167 Def000048
+S A$crc8ccittmsbb$158 Def00003D
+S A$crc8ccittmsbb$149 Def000034
+S G$crc_crc8ccitt_msb$0$0 Def000000
+S A$crc8ccittmsbb$186 Def000063
+S A$crc8ccittmsbb$177 Def000057
+S A$crc8ccittmsbb$168 Def00004A
+S A$crc8ccittmsbb$159 Def00003E
+S A$crc8ccittmsbb$187 Def000065
+S A$crc8ccittmsbb$169 Def00004C
+S A$crc8ccittmsbb$188 Def000067
+S A$crc8ccittmsbb$179 Def000059
+S C$crc8ccittmsbb.c$96$1$63 Def000000
+S C$crc8ccittmsbb.c$97$1$63 Def000069
+S _crc_crc8ccitt_msb Def000000
+S XG$crc_crc8ccitt_msb$0$0 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 01
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 01
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 01
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 01
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8ccittmsbb
+F:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8ccittmsbb.crc_crc8ccitt_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewireb
+
+;!FILE libmflarge/crc8onewireb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8onewireb
+O -mmcs51 --model-large
+S _crc_crc8onewire_table Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S G$crc_crc8onewire$0$0 Def000000
+S _crc_crc8onewire Def000000
+S A$crc8onewireb$110 Def000004
+S A$crc8onewireb$120 Def00000E
+S A$crc8onewireb$111 Def000005
+S A$crc8onewireb$121 Def000010
+S A$crc8onewireb$112 Def000006
+S A$crc8onewireb$140 Def000029
+S A$crc8onewireb$131 Def00001F
+S A$crc8onewireb$122 Def000011
+S A$crc8onewireb$113 Def000007
+S A$crc8onewireb$141 Def00002B
+S A$crc8onewireb$132 Def000020
+S A$crc8onewireb$123 Def000013
+S A$crc8onewireb$114 Def000008
+S A$crc8onewireb$160 Def000040
+S A$crc8onewireb$151 Def000035
+S A$crc8onewireb$115 Def000009
+S XG$crc_crc8onewire$0$0 Def000069
+S A$crc8onewireb$170 Def00004E
+S A$crc8onewireb$152 Def000037
+S A$crc8onewireb$143 Def00002D
+S A$crc8onewireb$134 Def000021
+S A$crc8onewireb$125 Def000014
+S A$crc8onewireb$116 Def00000A
+S A$crc8onewireb$180 Def00005A
+S A$crc8onewireb$171 Def000050
+S A$crc8onewireb$162 Def000042
+S A$crc8onewireb$144 Def00002E
+S A$crc8onewireb$135 Def000022
+S A$crc8onewireb$126 Def000017
+S A$crc8onewireb$117 Def00000B
+S A$crc8onewireb$108 Def000000
+S A$crc8onewireb$181 Def00005D
+S A$crc8onewireb$163 Def000043
+S A$crc8onewireb$154 Def000039
+S A$crc8onewireb$136 Def000025
+S A$crc8onewireb$127 Def00001A
+S A$crc8onewireb$118 Def00000C
+S A$crc8onewireb$109 Def000002
+S A$crc8onewireb$182 Def00005E
+S A$crc8onewireb$173 Def000052
+S A$crc8onewireb$164 Def000046
+S A$crc8onewireb$155 Def00003B
+S A$crc8onewireb$146 Def00002F
+S A$crc8onewireb$137 Def000026
+S A$crc8onewireb$128 Def00001C
+S A$crc8onewireb$119 Def00000D
+S A$crc8onewireb$174 Def000053
+S A$crc8onewireb$165 Def000047
+S A$crc8onewireb$147 Def000030
+S C$crc8onewireb.c$10$0$0 Def000000
+S A$crc8onewireb$184 Def00005F
+S A$crc8onewireb$175 Def000054
+S A$crc8onewireb$157 Def00003C
+S A$crc8onewireb$148 Def000033
+S A$crc8onewireb$139 Def000027
+S A$crc8onewireb$185 Def000061
+S A$crc8onewireb$176 Def000055
+S A$crc8onewireb$167 Def000048
+S A$crc8onewireb$158 Def00003D
+S A$crc8onewireb$149 Def000034
+S A$crc8onewireb$186 Def000063
+S A$crc8onewireb$177 Def000057
+S A$crc8onewireb$168 Def00004A
+S A$crc8onewireb$159 Def00003E
+S A$crc8onewireb$187 Def000065
+S A$crc8onewireb$169 Def00004C
+S A$crc8onewireb$188 Def000067
+S A$crc8onewireb$179 Def000059
+S C$crc8onewireb.c$96$1$63 Def000000
+S C$crc8onewireb.c$97$1$63 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 00
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 00
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 00
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 00
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8onewireb
+F:G$crc_crc8onewire$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewireb.crc_crc8onewire$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8onewireb.crc_crc8onewire$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8onewireb.crc_crc8onewire$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiremsbb
+
+;!FILE libmflarge/crc8onewiremsbb.asm
+XH3
+H 1A areas 4D global symbols
+M crc8onewiremsbb
+O -mmcs51 --model-large
+S _crc_crc8onewire_msbtable Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 69 flags 20 addr 0
+S _crc_crc8onewire_msb Def000000
+S XG$crc_crc8onewire_msb$0$0 Def000069
+S A$crc8onewiremsbb$110 Def000004
+S A$crc8onewiremsbb$120 Def00000E
+S A$crc8onewiremsbb$111 Def000005
+S A$crc8onewiremsbb$121 Def000010
+S A$crc8onewiremsbb$112 Def000006
+S A$crc8onewiremsbb$140 Def000029
+S A$crc8onewiremsbb$131 Def00001F
+S A$crc8onewiremsbb$122 Def000011
+S A$crc8onewiremsbb$113 Def000007
+S A$crc8onewiremsbb$141 Def00002B
+S A$crc8onewiremsbb$132 Def000020
+S A$crc8onewiremsbb$123 Def000013
+S A$crc8onewiremsbb$114 Def000008
+S A$crc8onewiremsbb$160 Def000040
+S A$crc8onewiremsbb$151 Def000035
+S A$crc8onewiremsbb$115 Def000009
+S A$crc8onewiremsbb$170 Def00004E
+S A$crc8onewiremsbb$152 Def000037
+S A$crc8onewiremsbb$143 Def00002D
+S A$crc8onewiremsbb$134 Def000021
+S A$crc8onewiremsbb$125 Def000014
+S A$crc8onewiremsbb$116 Def00000A
+S A$crc8onewiremsbb$180 Def00005A
+S A$crc8onewiremsbb$171 Def000050
+S A$crc8onewiremsbb$162 Def000042
+S A$crc8onewiremsbb$144 Def00002E
+S A$crc8onewiremsbb$135 Def000022
+S A$crc8onewiremsbb$126 Def000017
+S A$crc8onewiremsbb$117 Def00000B
+S A$crc8onewiremsbb$108 Def000000
+S A$crc8onewiremsbb$181 Def00005D
+S A$crc8onewiremsbb$163 Def000043
+S A$crc8onewiremsbb$154 Def000039
+S A$crc8onewiremsbb$136 Def000025
+S A$crc8onewiremsbb$127 Def00001A
+S A$crc8onewiremsbb$118 Def00000C
+S A$crc8onewiremsbb$109 Def000002
+S A$crc8onewiremsbb$182 Def00005E
+S A$crc8onewiremsbb$173 Def000052
+S A$crc8onewiremsbb$164 Def000046
+S A$crc8onewiremsbb$155 Def00003B
+S A$crc8onewiremsbb$146 Def00002F
+S A$crc8onewiremsbb$137 Def000026
+S A$crc8onewiremsbb$128 Def00001C
+S A$crc8onewiremsbb$119 Def00000D
+S A$crc8onewiremsbb$174 Def000053
+S A$crc8onewiremsbb$165 Def000047
+S A$crc8onewiremsbb$147 Def000030
+S C$crc8onewiremsbb.c$10$0$0 Def000000
+S A$crc8onewiremsbb$184 Def00005F
+S A$crc8onewiremsbb$175 Def000054
+S A$crc8onewiremsbb$157 Def00003C
+S A$crc8onewiremsbb$148 Def000033
+S A$crc8onewiremsbb$139 Def000027
+S A$crc8onewiremsbb$185 Def000061
+S A$crc8onewiremsbb$176 Def000055
+S A$crc8onewiremsbb$167 Def000048
+S A$crc8onewiremsbb$158 Def00003D
+S A$crc8onewiremsbb$149 Def000034
+S G$crc_crc8onewire_msb$0$0 Def000000
+S A$crc8onewiremsbb$186 Def000063
+S A$crc8onewiremsbb$177 Def000057
+S A$crc8onewiremsbb$168 Def00004A
+S A$crc8onewiremsbb$159 Def00003E
+S A$crc8onewiremsbb$187 Def000065
+S A$crc8onewiremsbb$169 Def00004C
+S A$crc8onewiremsbb$188 Def000067
+S A$crc8onewiremsbb$179 Def000059
+S C$crc8onewiremsbb.c$96$1$63 Def000000
+S C$crc8onewiremsbb.c$97$1$63 Def000069
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FC F8 E6 FC 08 E6 FA 08 E6 FB
+R 00 00 00 16
+T 00 00 0D 4A 60 29 EA 60 01 0B
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 20 00 00 00 3B 30 00 00 00 22 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 1D 00 00 00 0E
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F E6 08 6C 90 00 00 93 FC DA F6 DB F4 80
+R 00 00 00 16 02 07 00 00
+T 00 00 2C 0C
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08 6C 90 00 00 93 FC DA F6 DB F4
+R 00 00 00 16 02 07 00 00
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 8C 82 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C E0 A3 A8 82 A9 83 6C 90 00 00 93 FC 89
+R 00 00 00 16 02 0B 00 00
+T 00 00 49 83 88 82 DA EE DB EC 80 E7
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 E4 93 A3 A8 82 A9 83 6C 90 00 00 93 FC
+R 00 00 00 16 02 0C 00 00
+T 00 00 5F 89 83 88 82 DA ED DB EB 80 D0
+R 00 00 00 16
+
+
+M:crc8onewiremsbb
+F:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$crc$1$62({1}SC:U),B,1,-5
+S:Lcrc8onewiremsbb.crc_crc8onewire_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccitttable
+
+XH3
+H 1A areas 3 global symbols
+M crc8ccitttable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S G$crc_crc8ccitt_table$0$0 Def000000
+S _crc_crc8ccitt_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 91 E3 72 07 96 E4 75 0E 9F ED 7C 09
+R 00 00 00 17
+T 00 00 0D 98 EA 7B 1C 8D FF 6E 1B 8A F8 69 12 83
+R 00 00 00 17
+T 00 00 1A F1 60 15 84 F6 67 38 A9 DB 4A 3F AE DC
+R 00 00 00 17
+T 00 00 27 4D 36 A7 D5 44 31 A0 D2 43 24 B5 C7 56
+R 00 00 00 17
+T 00 00 34 23 B2 C0 51 2A BB C9 58 2D BC CE 5F 70
+R 00 00 00 17
+T 00 00 41 E1 93 02 77 E6 94 05 7E EF 9D 0C 79 E8
+R 00 00 00 17
+T 00 00 4E 9A 0B 6C FD 8F 1E 6B FA 88 19 62 F3 81
+R 00 00 00 17
+T 00 00 5B 10 65 F4 86 17 48 D9 AB 3A 4F DE AC 3D
+R 00 00 00 17
+T 00 00 68 46 D7 A5 34 41 D0 A2 33 54 C5 B7 26 53
+R 00 00 00 17
+T 00 00 75 C2 B0 21 5A CB B9 28 5D CC BE 2F E0 71
+R 00 00 00 17
+T 00 00 82 03 92 E7 76 04 95 EE 7F 0D 9C E9 78 0A
+R 00 00 00 17
+T 00 00 8F 9B FC 6D 1F 8E FB 6A 18 89 F2 63 11 80
+R 00 00 00 17
+T 00 00 9C F5 64 16 87 D8 49 3B AA DF 4E 3C AD D6
+R 00 00 00 17
+T 00 00 A9 47 35 A4 D1 40 32 A3 C4 55 27 B6 C3 52
+R 00 00 00 17
+T 00 00 B6 20 B1 CA 5B 29 B8 CD 5C 2E BF 90 01 73
+R 00 00 00 17
+T 00 00 C3 E2 97 06 74 E5 9E 0F 7D EC 99 08 7A EB
+R 00 00 00 17
+T 00 00 D0 8C 1D 6F FE 8B 1A 68 F9 82 13 61 F0 85
+R 00 00 00 17
+T 00 00 DD 14 66 F7 A8 39 4B DA AF 3E 4C DD A6 37
+R 00 00 00 17
+T 00 00 EA 45 D4 A1 30 42 D3 B4 25 57 C6 B3 22 50
+R 00 00 00 17
+T 00 00 F7 C1 BA 2B 59 C8 BD 2C 5E CF
+R 00 00 00 17
+
+
+M:crc8ccitttable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiretable
+
+XH3
+H 1A areas 3 global symbols
+M crc8onewiretable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _crc_crc8onewire_table Def000000
+S G$crc_crc8onewire_table$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 5E BC E2 61 3F DD 83 C2 9C 7E 20 A3
+R 00 00 00 17
+T 00 00 0D FD 1F 41 9D C3 21 7F FC A2 40 1E 5F 01
+R 00 00 00 17
+T 00 00 1A E3 BD 3E 60 82 DC 23 7D 9F C1 42 1C FE
+R 00 00 00 17
+T 00 00 27 A0 E1 BF 5D 03 80 DE 3C 62 BE E0 02 5C
+R 00 00 00 17
+T 00 00 34 DF 81 63 3D 7C 22 C0 9E 1D 43 A1 FF 46
+R 00 00 00 17
+T 00 00 41 18 FA A4 27 79 9B C5 84 DA 38 66 E5 BB
+R 00 00 00 17
+T 00 00 4E 59 07 DB 85 67 39 BA E4 06 58 19 47 A5
+R 00 00 00 17
+T 00 00 5B FB 78 26 C4 9A 65 3B D9 87 04 5A B8 E6
+R 00 00 00 17
+T 00 00 68 A7 F9 1B 45 C6 98 7A 24 F8 A6 44 1A 99
+R 00 00 00 17
+T 00 00 75 C7 25 7B 3A 64 86 D8 5B 05 E7 B9 8C D2
+R 00 00 00 17
+T 00 00 82 30 6E ED B3 51 0F 4E 10 F2 AC 2F 71 93
+R 00 00 00 17
+T 00 00 8F CD 11 4F AD F3 70 2E CC 92 D3 8D 6F 31
+R 00 00 00 17
+T 00 00 9C B2 EC 0E 50 AF F1 13 4D CE 90 72 2C 6D
+R 00 00 00 17
+T 00 00 A9 33 D1 8F 0C 52 B0 EE 32 6C 8E D0 53 0D
+R 00 00 00 17
+T 00 00 B6 EF B1 F0 AE 4C 12 91 CF 2D 73 CA 94 76
+R 00 00 00 17
+T 00 00 C3 28 AB F5 17 49 08 56 B4 EA 69 37 D5 8B
+R 00 00 00 17
+T 00 00 D0 57 09 EB B5 36 68 8A D4 95 CB 29 77 F4
+R 00 00 00 17
+T 00 00 DD AA 48 16 E9 B7 55 0B 88 D6 34 6A 2B 75
+R 00 00 00 17
+T 00 00 EA 97 C9 4A 14 F6 A8 74 2A C8 96 15 4B A9
+R 00 00 00 17
+T 00 00 F7 F7 B6 E8 0A 54 D7 89 6B 35
+R 00 00 00 17
+
+
+M:crc8onewiretable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8ccittmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc8ccittmsbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S G$crc_crc8ccitt_msbtable$0$0 Def000000
+S _crc_crc8ccitt_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 07 0E 09 1C 1B 12 15 38 3F 36 31 24
+R 00 00 00 17
+T 00 00 0D 23 2A 2D 70 77 7E 79 6C 6B 62 65 48 4F
+R 00 00 00 17
+T 00 00 1A 46 41 54 53 5A 5D E0 E7 EE E9 FC FB F2
+R 00 00 00 17
+T 00 00 27 F5 D8 DF D6 D1 C4 C3 CA CD 90 97 9E 99
+R 00 00 00 17
+T 00 00 34 8C 8B 82 85 A8 AF A6 A1 B4 B3 BA BD C7
+R 00 00 00 17
+T 00 00 41 C0 C9 CE DB DC D5 D2 FF F8 F1 F6 E3 E4
+R 00 00 00 17
+T 00 00 4E ED EA B7 B0 B9 BE AB AC A5 A2 8F 88 81
+R 00 00 00 17
+T 00 00 5B 86 93 94 9D 9A 27 20 29 2E 3B 3C 35 32
+R 00 00 00 17
+T 00 00 68 1F 18 11 16 03 04 0D 0A 57 50 59 5E 4B
+R 00 00 00 17
+T 00 00 75 4C 45 42 6F 68 61 66 73 74 7D 7A 89 8E
+R 00 00 00 17
+T 00 00 82 87 80 95 92 9B 9C B1 B6 BF B8 AD AA A3
+R 00 00 00 17
+T 00 00 8F A4 F9 FE F7 F0 E5 E2 EB EC C1 C6 CF C8
+R 00 00 00 17
+T 00 00 9C DD DA D3 D4 69 6E 67 60 75 72 7B 7C 51
+R 00 00 00 17
+T 00 00 A9 56 5F 58 4D 4A 43 44 19 1E 17 10 05 02
+R 00 00 00 17
+T 00 00 B6 0B 0C 21 26 2F 28 3D 3A 33 34 4E 49 40
+R 00 00 00 17
+T 00 00 C3 47 52 55 5C 5B 76 71 78 7F 6A 6D 64 63
+R 00 00 00 17
+T 00 00 D0 3E 39 30 37 22 25 2C 2B 06 01 08 0F 1A
+R 00 00 00 17
+T 00 00 DD 1D 14 13 AE A9 A0 A7 B2 B5 BC BB 96 91
+R 00 00 00 17
+T 00 00 EA 98 9F 8A 8D 84 83 DE D9 D0 D7 C2 C5 CC
+R 00 00 00 17
+T 00 00 F7 CB E6 E1 E8 EF FA FD F4 F3
+R 00 00 00 17
+
+
+M:crc8ccittmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc8onewiremsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc8onewiremsbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _crc_crc8onewire_msbtable Def000000
+S G$crc_crc8onewire_msbtable$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 31 62 53 C4 F5 A6 97 B9 88 DB EA 7D
+R 00 00 00 17
+T 00 00 0D 4C 1F 2E 43 72 21 10 87 B6 E5 D4 FA CB
+R 00 00 00 17
+T 00 00 1A 98 A9 3E 0F 5C 6D 86 B7 E4 D5 42 73 20
+R 00 00 00 17
+T 00 00 27 11 3F 0E 5D 6C FB CA 99 A8 C5 F4 A7 96
+R 00 00 00 17
+T 00 00 34 01 30 63 52 7C 4D 1E 2F B8 89 DA EB 3D
+R 00 00 00 17
+T 00 00 41 0C 5F 6E F9 C8 9B AA 84 B5 E6 D7 40 71
+R 00 00 00 17
+T 00 00 4E 22 13 7E 4F 1C 2D BA 8B D8 E9 C7 F6 A5
+R 00 00 00 17
+T 00 00 5B 94 03 32 61 50 BB 8A D9 E8 7F 4E 1D 2C
+R 00 00 00 17
+T 00 00 68 02 33 60 51 C6 F7 A4 95 F8 C9 9A AB 3C
+R 00 00 00 17
+T 00 00 75 0D 5E 6F 41 70 23 12 85 B4 E7 D6 7A 4B
+R 00 00 00 17
+T 00 00 82 18 29 BE 8F DC ED C3 F2 A1 90 07 36 65
+R 00 00 00 17
+T 00 00 8F 54 39 08 5B 6A FD CC 9F AE 80 B1 E2 D3
+R 00 00 00 17
+T 00 00 9C 44 75 26 17 FC CD 9E AF 38 09 5A 6B 45
+R 00 00 00 17
+T 00 00 A9 74 27 16 81 B0 E3 D2 BF 8E DD EC 7B 4A
+R 00 00 00 17
+T 00 00 B6 19 28 06 37 64 55 C2 F3 A0 91 47 76 25
+R 00 00 00 17
+T 00 00 C3 14 83 B2 E1 D0 FE CF 9C AD 3A 0B 58 69
+R 00 00 00 17
+T 00 00 D0 04 35 66 57 C0 F1 A2 93 BD 8C DF EE 79
+R 00 00 00 17
+T 00 00 DD 48 1B 2A C1 F0 A3 92 05 34 67 56 78 49
+R 00 00 00 17
+T 00 00 EA 1A 2B BC 8D DE EF 82 B3 E0 D1 46 77 24
+R 00 00 00 17
+T 00 00 F7 15 3B 0A 59 68 FF CE 9D AC
+R 00 00 00 17
+
+
+M:crc8onewiremsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccitt
+
+;!FILE libmflarge/crcccitt.asm
+XH3
+H 1A areas 23 global symbols
+M crcccitt
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_ccitt_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crcccitt.c$9$0$0 Def000000
+S G$crc_ccitt_byte$0$0 Def000000
+S _crc_ccitt_byte Def000000
+S A$crcccitt$110 Def000005
+S A$crcccitt$120 Def000011
+S A$crcccitt$111 Def000006
+S A$crcccitt$130 Def00001F
+S A$crcccitt$121 Def000013
+S A$crcccitt$112 Def000008
+S XG$crc_ccitt_byte$0$0 Def000025
+S A$crcccitt$131 Def000020
+S A$crcccitt$122 Def000015
+S A$crcccitt$113 Def000009
+S A$crcccitt$132 Def000022
+S A$crcccitt$123 Def000016
+S A$crcccitt$114 Def00000A
+S A$crcccitt$133 Def000024
+S A$crcccitt$124 Def000018
+S A$crcccitt$115 Def00000B
+S A$crcccitt$125 Def000019
+S A$crcccitt$116 Def00000C
+S A$crcccitt$107 Def000000
+S A$crcccitt$126 Def00001A
+S A$crcccitt$117 Def00000D
+S A$crcccitt$108 Def000002
+S A$crcccitt$127 Def00001B
+S A$crcccitt$118 Def00000E
+S A$crcccitt$109 Def000004
+S C$crcccitt.c$41$1$63 Def000000
+S A$crcccitt$128 Def00001C
+S A$crcccitt$119 Def000010
+S C$crcccitt.c$42$1$63 Def000025
+S A$crcccitt$129 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crcccitt
+F:G$crc_ccitt_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccitt.crc_ccitt_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrcccitt.crc_ccitt_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittmsb
+
+;!FILE libmflarge/crcccittmsb.asm
+XH3
+H 1A areas 23 global symbols
+M crcccittmsb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_ccitt_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S _crc_ccitt_msb_byte Def000000
+S XG$crc_ccitt_msb_byte$0$0 Def000025
+S C$crcccittmsb.c$9$0$0 Def000000
+S A$crcccittmsb$110 Def000005
+S A$crcccittmsb$120 Def000011
+S A$crcccittmsb$111 Def000006
+S A$crcccittmsb$130 Def00001F
+S A$crcccittmsb$121 Def000013
+S A$crcccittmsb$112 Def000008
+S A$crcccittmsb$131 Def000020
+S A$crcccittmsb$122 Def000014
+S A$crcccittmsb$113 Def000009
+S A$crcccittmsb$132 Def000022
+S A$crcccittmsb$123 Def000016
+S A$crcccittmsb$114 Def00000A
+S A$crcccittmsb$133 Def000024
+S A$crcccittmsb$124 Def000017
+S A$crcccittmsb$115 Def00000B
+S A$crcccittmsb$125 Def000019
+S A$crcccittmsb$116 Def00000C
+S A$crcccittmsb$107 Def000000
+S A$crcccittmsb$126 Def00001B
+S A$crcccittmsb$117 Def00000D
+S A$crcccittmsb$108 Def000002
+S A$crcccittmsb$127 Def00001C
+S A$crcccittmsb$118 Def00000E
+S A$crcccittmsb$109 Def000004
+S C$crcccittmsb.c$41$1$63 Def000000
+S A$crcccittmsb$128 Def00001D
+S A$crcccittmsb$119 Def000010
+S C$crcccittmsb.c$42$1$63 Def000025
+S G$crc_ccitt_msb_byte$0$0 Def000000
+S A$crcccittmsb$129 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 01 F1 83 0D 00 01
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crcccittmsb
+F:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittmsb.crc_ccitt_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrcccittmsb.crc_ccitt_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansi
+
+;!FILE libmflarge/crc16ansi.asm
+XH3
+H 1A areas 23 global symbols
+M crc16ansi
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc16_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crc16ansi.c$9$0$0 Def000000
+S G$crc_crc16_byte$0$0 Def000000
+S A$crc16ansi$110 Def000005
+S A$crc16ansi$120 Def000011
+S A$crc16ansi$111 Def000006
+S A$crc16ansi$130 Def00001F
+S A$crc16ansi$121 Def000013
+S A$crc16ansi$112 Def000008
+S A$crc16ansi$131 Def000020
+S A$crc16ansi$122 Def000015
+S A$crc16ansi$113 Def000009
+S _crc_crc16_byte Def000000
+S A$crc16ansi$132 Def000022
+S A$crc16ansi$123 Def000016
+S A$crc16ansi$114 Def00000A
+S A$crc16ansi$133 Def000024
+S A$crc16ansi$124 Def000018
+S A$crc16ansi$115 Def00000B
+S A$crc16ansi$125 Def000019
+S A$crc16ansi$116 Def00000C
+S A$crc16ansi$107 Def000000
+S A$crc16ansi$126 Def00001A
+S A$crc16ansi$117 Def00000D
+S A$crc16ansi$108 Def000002
+S A$crc16ansi$127 Def00001B
+S A$crc16ansi$118 Def00000E
+S A$crc16ansi$109 Def000004
+S C$crc16ansi.c$41$1$63 Def000000
+S A$crc16ansi$128 Def00001C
+S A$crc16ansi$119 Def000010
+S C$crc16ansi.c$42$1$63 Def000025
+S A$crc16ansi$129 Def00001D
+S XG$crc_crc16_byte$0$0 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crc16ansi
+F:G$crc_crc16_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansi.crc_crc16_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16ansi.crc_crc16_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansimsb
+
+;!FILE libmflarge/crc16ansimsb.asm
+XH3
+H 1A areas 23 global symbols
+M crc16ansimsb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc16_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S C$crc16ansimsb.c$9$0$0 Def000000
+S _crc_crc16_msb_byte Def000000
+S XG$crc_crc16_msb_byte$0$0 Def000025
+S A$crc16ansimsb$110 Def000005
+S A$crc16ansimsb$120 Def000011
+S A$crc16ansimsb$111 Def000006
+S A$crc16ansimsb$130 Def00001F
+S A$crc16ansimsb$121 Def000013
+S A$crc16ansimsb$112 Def000008
+S A$crc16ansimsb$131 Def000020
+S A$crc16ansimsb$122 Def000014
+S A$crc16ansimsb$113 Def000009
+S A$crc16ansimsb$132 Def000022
+S A$crc16ansimsb$123 Def000016
+S A$crc16ansimsb$114 Def00000A
+S A$crc16ansimsb$133 Def000024
+S A$crc16ansimsb$124 Def000017
+S A$crc16ansimsb$115 Def00000B
+S A$crc16ansimsb$125 Def000019
+S A$crc16ansimsb$116 Def00000C
+S A$crc16ansimsb$107 Def000000
+S A$crc16ansimsb$126 Def00001B
+S A$crc16ansimsb$117 Def00000D
+S A$crc16ansimsb$108 Def000002
+S A$crc16ansimsb$127 Def00001C
+S A$crc16ansimsb$118 Def00000E
+S A$crc16ansimsb$109 Def000004
+S C$crc16ansimsb.c$41$1$63 Def000000
+S A$crc16ansimsb$128 Def00001D
+S A$crc16ansimsb$119 Def000010
+S C$crc16ansimsb.c$42$1$63 Def000025
+S A$crc16ansimsb$129 Def00001E
+S G$crc_crc16_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 01 F1 83 0D 00 01
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crc16ansimsb
+F:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansimsb.crc_crc16_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16ansimsb.crc_crc16_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnp
+
+;!FILE libmflarge/crc16dnp.asm
+XH3
+H 1A areas 23 global symbols
+M crc16dnp
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc16dnp_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$crc16dnp$132 Def000022
+S A$crc16dnp$123 Def000016
+S A$crc16dnp$114 Def00000A
+S A$crc16dnp$133 Def000024
+S A$crc16dnp$124 Def000018
+S A$crc16dnp$115 Def00000B
+S A$crc16dnp$125 Def000019
+S A$crc16dnp$116 Def00000C
+S A$crc16dnp$107 Def000000
+S A$crc16dnp$126 Def00001A
+S A$crc16dnp$117 Def00000D
+S A$crc16dnp$108 Def000002
+S A$crc16dnp$127 Def00001B
+S A$crc16dnp$118 Def00000E
+S A$crc16dnp$109 Def000004
+S C$crc16dnp.c$41$1$63 Def000000
+S A$crc16dnp$128 Def00001C
+S A$crc16dnp$119 Def000010
+S C$crc16dnp.c$42$1$63 Def000025
+S A$crc16dnp$129 Def00001D
+S C$crc16dnp.c$9$0$0 Def000000
+S G$crc_crc16dnp_byte$0$0 Def000000
+S _crc_crc16dnp_byte Def000000
+S XG$crc_crc16dnp_byte$0$0 Def000025
+S A$crc16dnp$110 Def000005
+S A$crc16dnp$120 Def000011
+S A$crc16dnp$111 Def000006
+S A$crc16dnp$130 Def00001F
+S A$crc16dnp$121 Def000013
+S A$crc16dnp$112 Def000008
+S A$crc16dnp$131 Def000020
+S A$crc16dnp$122 Def000015
+S A$crc16dnp$113 Def000009
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 82 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A F5 82 74 00 00 00 3B
+R 00 00 00 16 F1 03 05 00 01 F1 83 0C 00 01
+T 00 00 16 C5 83 FA E4 93 6A FA 74 01 93 F5 83 8A
+R 00 00 00 16
+T 00 00 23 82 22
+R 00 00 00 16
+
+
+M:crc16dnp
+F:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnp.crc_crc16dnp_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16dnp.crc_crc16dnp_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpmsb
+
+;!FILE libmflarge/crc16dnpmsb.asm
+XH3
+H 1A areas 23 global symbols
+M crc16dnpmsb
+O -mmcs51 --model-large
+S _crc_crc16dnp_msbtable Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$crc16dnpmsb$130 Def00001F
+S A$crc16dnpmsb$121 Def000013
+S A$crc16dnpmsb$112 Def000008
+S A$crc16dnpmsb$131 Def000020
+S A$crc16dnpmsb$122 Def000014
+S A$crc16dnpmsb$113 Def000009
+S A$crc16dnpmsb$132 Def000022
+S A$crc16dnpmsb$123 Def000016
+S A$crc16dnpmsb$114 Def00000A
+S A$crc16dnpmsb$133 Def000024
+S A$crc16dnpmsb$124 Def000017
+S A$crc16dnpmsb$115 Def00000B
+S A$crc16dnpmsb$125 Def000019
+S A$crc16dnpmsb$116 Def00000C
+S A$crc16dnpmsb$107 Def000000
+S A$crc16dnpmsb$126 Def00001B
+S A$crc16dnpmsb$117 Def00000D
+S A$crc16dnpmsb$108 Def000002
+S A$crc16dnpmsb$127 Def00001C
+S A$crc16dnpmsb$118 Def00000E
+S A$crc16dnpmsb$109 Def000004
+S C$crc16dnpmsb.c$41$1$63 Def000000
+S A$crc16dnpmsb$128 Def00001D
+S A$crc16dnpmsb$119 Def000010
+S C$crc16dnpmsb.c$42$1$63 Def000025
+S A$crc16dnpmsb$129 Def00001E
+S _crc_crc16dnp_msb_byte Def000000
+S XG$crc_crc16dnp_msb_byte$0$0 Def000025
+S C$crc16dnpmsb.c$9$0$0 Def000000
+S A$crc16dnpmsb$110 Def000005
+S A$crc16dnpmsb$120 Def000011
+S A$crc16dnpmsb$111 Def000006
+S G$crc_crc16dnp_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 65 83 C3 33 FA E4 33
+R 00 00 00 16
+T 00 00 0D FB 74 00 00 00 2A C5 82 FA 74 00 00 00
+R 00 00 00 16 F1 03 05 00 00 F1 83 0D 00 00
+T 00 00 16 3B F5 83 74 01 93 6A FA E4 93 F5 82 8A
+R 00 00 00 16
+T 00 00 23 83 22
+R 00 00 00 16
+
+
+M:crc16dnpmsb
+F:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpmsb.crc_crc16dnp_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc16dnpmsb.crc_crc16dnp_msb_byte$crc$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansi
+
+;!FILE libmflarge/crc32ansi.asm
+XH3
+H 1A areas 2C global symbols
+M crc32ansi
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc32_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$crc32ansi.c$9$0$0 Def000000
+S G$crc_crc32_byte$0$0 Def000000
+S A$crc32ansi$110 Def000005
+S A$crc32ansi$120 Def000013
+S A$crc32ansi$111 Def000006
+S A$crc32ansi$130 Def000021
+S A$crc32ansi$121 Def000015
+S A$crc32ansi$112 Def000007
+S A$crc32ansi$140 Def000030
+S A$crc32ansi$131 Def000022
+S A$crc32ansi$122 Def000017
+S A$crc32ansi$113 Def000009
+S _crc_crc32_byte Def000000
+S A$crc32ansi$141 Def000032
+S A$crc32ansi$132 Def000023
+S A$crc32ansi$123 Def000019
+S A$crc32ansi$114 Def00000A
+S A$crc32ansi$142 Def000033
+S A$crc32ansi$133 Def000025
+S A$crc32ansi$124 Def00001A
+S A$crc32ansi$115 Def00000B
+S A$crc32ansi$134 Def000026
+S A$crc32ansi$125 Def00001B
+S A$crc32ansi$116 Def00000C
+S A$crc32ansi$107 Def000000
+S A$crc32ansi$135 Def000027
+S A$crc32ansi$126 Def00001C
+S A$crc32ansi$117 Def00000E
+S A$crc32ansi$108 Def000001
+S A$crc32ansi$136 Def000029
+S A$crc32ansi$127 Def00001D
+S A$crc32ansi$118 Def000010
+S A$crc32ansi$109 Def000003
+S C$crc32ansi.c$50$1$63 Def000000
+S A$crc32ansi$137 Def00002A
+S A$crc32ansi$128 Def00001E
+S A$crc32ansi$119 Def000012
+S C$crc32ansi.c$51$1$63 Def000034
+S A$crc32ansi$138 Def00002C
+S A$crc32ansi$129 Def000020
+S A$crc32ansi$139 Def00002E
+S XG$crc_crc32_byte$0$0 Def000034
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FC E5 81 24 FE F8 E6 65 82 23 23 FB 54
+R 00 00 00 16
+T 00 00 0D FC 24 00 00 00 F5 82 EB 54 03 34
+R 00 00 00 16 F1 03 05 00 01
+T 00 00 16 00 00 00 C5 83 FA E4 93 6A FA 74 02 93
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 21 6C FB 74 03 93 FC 74 01 93 65 F0 F5 83
+R 00 00 00 16
+T 00 00 2E 8A 82 8B F0 EC 22
+R 00 00 00 16
+
+
+M:crc32ansi
+F:G$crc_crc32_byte$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansi.crc_crc32_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc32ansi.crc_crc32_byte$crc$1$62({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansimsb
+
+;!FILE libmflarge/crc32ansimsb.asm
+XH3
+H 1A areas 2D global symbols
+M crc32ansimsb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_crc32_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$crc32ansimsb.c$9$0$0 Def000000
+S _crc_crc32_msb_byte Def000000
+S XG$crc_crc32_msb_byte$0$0 Def000034
+S A$crc32ansimsb$110 Def000005
+S A$crc32ansimsb$120 Def000012
+S A$crc32ansimsb$111 Def000006
+S A$crc32ansimsb$130 Def000021
+S A$crc32ansimsb$121 Def000013
+S A$crc32ansimsb$112 Def000007
+S A$crc32ansimsb$140 Def00002E
+S A$crc32ansimsb$131 Def000022
+S A$crc32ansimsb$122 Def000015
+S A$crc32ansimsb$113 Def000008
+S A$crc32ansimsb$141 Def000030
+S A$crc32ansimsb$132 Def000023
+S A$crc32ansimsb$123 Def000017
+S A$crc32ansimsb$114 Def000009
+S A$crc32ansimsb$142 Def000032
+S A$crc32ansimsb$133 Def000024
+S A$crc32ansimsb$124 Def000019
+S A$crc32ansimsb$115 Def00000A
+S A$crc32ansimsb$143 Def000033
+S A$crc32ansimsb$134 Def000026
+S A$crc32ansimsb$125 Def00001A
+S A$crc32ansimsb$116 Def00000B
+S A$crc32ansimsb$107 Def000000
+S A$crc32ansimsb$135 Def000027
+S A$crc32ansimsb$126 Def00001C
+S A$crc32ansimsb$117 Def00000D
+S A$crc32ansimsb$108 Def000001
+S A$crc32ansimsb$136 Def000029
+S A$crc32ansimsb$127 Def00001D
+S A$crc32ansimsb$118 Def00000F
+S A$crc32ansimsb$109 Def000003
+S A$crc32ansimsb$137 Def00002A
+S A$crc32ansimsb$128 Def00001E
+S A$crc32ansimsb$119 Def000011
+S C$crc32ansimsb.c$51$1$63 Def000000
+S A$crc32ansimsb$138 Def00002B
+S A$crc32ansimsb$129 Def00001F
+S C$crc32ansimsb.c$52$1$63 Def000034
+S A$crc32ansimsb$139 Def00002C
+S G$crc_crc32_msb_byte$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FA E5 81 24 FE F8 E6 6A 23 23 FB 54 FC
+R 00 00 00 16
+T 00 00 0D 24 00 00 00 C5 82 FA EB 54 03 34
+R 00 00 00 16 F1 03 04 00 01
+T 00 00 16 00 00 00 C5 83 FB 74 01 93 6A FA 74 02
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 21 93 6B FB 74 03 93 65 F0 FC E4 93 F5 82
+R 00 00 00 16
+T 00 00 2E 8A 83 8B F0 EC 22
+R 00 00 00 16
+
+
+M:crc32ansimsb
+F:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansimsb.crc_crc32_msb_byte$c$1$62({1}SC:U),B,1,-3
+S:Lcrc32ansimsb.crc_crc32_msb_byte$crc$1$62({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittb
+
+;!FILE libmflarge/crcccittb.asm
+XH3
+H 1A areas 81 global symbols
+M crcccittb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _crc_ccitt_table Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S G$crc_ccitt$0$0 Def000000
+S C$crcccittb.c$228$1$63 Def000000
+S A$crcccittb$200 Def00007C
+S A$crcccittb$110 Def000004
+S C$crcccittb.c$229$1$63 Def0000B6
+S A$crcccittb$210 Def000089
+S A$crcccittb$201 Def00007D
+S A$crcccittb$120 Def00000E
+S A$crcccittb$111 Def000005
+S _crc_ccitt Def000000
+S A$crcccittb$220 Def000095
+S A$crcccittb$211 Def00008B
+S A$crcccittb$202 Def00007E
+S A$crcccittb$130 Def00001D
+S A$crcccittb$121 Def00000F
+S A$crcccittb$112 Def000006
+S A$crcccittb$230 Def0000A6
+S A$crcccittb$221 Def000096
+S A$crcccittb$203 Def00007F
+S A$crcccittb$140 Def000028
+S A$crcccittb$131 Def00001F
+S A$crcccittb$122 Def000010
+S A$crcccittb$113 Def000007
+S A$crcccittb$240 Def0000B4
+S A$crcccittb$231 Def0000A7
+S A$crcccittb$222 Def000098
+S A$crcccittb$213 Def00008D
+S A$crcccittb$204 Def000081
+S A$crcccittb$150 Def000038
+S A$crcccittb$141 Def00002A
+S A$crcccittb$123 Def000011
+S A$crcccittb$114 Def000008
+S A$crcccittb$232 Def0000A8
+S A$crcccittb$223 Def00009A
+S A$crcccittb$214 Def00008E
+S A$crcccittb$205 Def000082
+S A$crcccittb$151 Def00003A
+S A$crcccittb$142 Def00002C
+S A$crcccittb$124 Def000013
+S A$crcccittb$115 Def000009
+S A$crcccittb$233 Def0000AA
+S A$crcccittb$224 Def00009C
+S A$crcccittb$215 Def00008F
+S A$crcccittb$170 Def000054
+S A$crcccittb$161 Def000044
+S A$crcccittb$152 Def00003B
+S A$crcccittb$143 Def00002E
+S A$crcccittb$134 Def000022
+S A$crcccittb$125 Def000014
+S A$crcccittb$116 Def00000A
+S A$crcccittb$234 Def0000AB
+S A$crcccittb$225 Def00009E
+S A$crcccittb$216 Def000090
+S A$crcccittb$207 Def000083
+S A$crcccittb$171 Def000055
+S A$crcccittb$162 Def000045
+S A$crcccittb$144 Def000030
+S A$crcccittb$135 Def000023
+S A$crcccittb$126 Def000016
+S A$crcccittb$117 Def00000B
+S A$crcccittb$108 Def000000
+S A$crcccittb$226 Def0000A0
+S A$crcccittb$217 Def000092
+S A$crcccittb$208 Def000085
+S A$crcccittb$190 Def00006B
+S A$crcccittb$181 Def000060
+S A$crcccittb$172 Def000056
+S A$crcccittb$163 Def000046
+S A$crcccittb$154 Def00003C
+S A$crcccittb$145 Def000032
+S A$crcccittb$118 Def00000C
+S A$crcccittb$109 Def000002
+S A$crcccittb$236 Def0000AC
+S A$crcccittb$227 Def0000A2
+S A$crcccittb$209 Def000087
+S A$crcccittb$191 Def00006C
+S A$crcccittb$182 Def000062
+S A$crcccittb$173 Def000057
+S A$crcccittb$164 Def000048
+S A$crcccittb$155 Def00003E
+S A$crcccittb$146 Def000034
+S A$crcccittb$137 Def000024
+S A$crcccittb$128 Def000017
+S A$crcccittb$119 Def00000D
+S A$crcccittb$237 Def0000AE
+S A$crcccittb$228 Def0000A4
+S A$crcccittb$219 Def000094
+S A$crcccittb$192 Def00006D
+S A$crcccittb$183 Def000064
+S A$crcccittb$174 Def000058
+S A$crcccittb$165 Def00004A
+S A$crcccittb$156 Def000040
+S A$crcccittb$147 Def000035
+S A$crcccittb$138 Def000025
+S A$crcccittb$129 Def00001A
+S C$crcccittb.c$10$0$0 Def000000
+S A$crcccittb$238 Def0000B0
+S A$crcccittb$229 Def0000A5
+S A$crcccittb$193 Def00006F
+S A$crcccittb$175 Def00005A
+S A$crcccittb$166 Def00004C
+S A$crcccittb$148 Def000036
+S A$crcccittb$139 Def000026
+S A$crcccittb$239 Def0000B2
+S A$crcccittb$194 Def000071
+S A$crcccittb$185 Def000065
+S A$crcccittb$176 Def00005B
+S A$crcccittb$167 Def00004E
+S A$crcccittb$158 Def000042
+S A$crcccittb$149 Def000037
+S A$crcccittb$195 Def000073
+S A$crcccittb$186 Def000066
+S A$crcccittb$168 Def000050
+S A$crcccittb$159 Def000043
+S XG$crc_ccitt$0$0 Def0000B6
+S A$crcccittb$196 Def000075
+S A$crcccittb$187 Def000067
+S A$crcccittb$178 Def00005C
+S A$crcccittb$169 Def000052
+S A$crcccittb$197 Def000077
+S A$crcccittb$188 Def000069
+S A$crcccittb$179 Def00005E
+S A$crcccittb$198 Def000079
+S A$crcccittb$199 Def00007B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 01
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 01
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 01
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 01
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 01 F1 83 0B 00 01
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 01 F1 83 0C 00 01
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crcccittb
+F:G$crc_ccitt$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittb.crc_ccitt$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrcccittb.crc_ccitt$crc$1$62({2}SI:U),B,1,-6
+S:Lcrcccittb.crc_ccitt$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccittmsbb
+
+;!FILE libmflarge/crcccittmsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crcccittmsbb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _crc_ccitt_msbtable Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S C$crcccittmsbb.c$228$1$63 Def000000
+S A$crcccittmsbb$200 Def00007D
+S A$crcccittmsbb$110 Def000004
+S C$crcccittmsbb.c$229$1$63 Def0000B6
+S A$crcccittmsbb$210 Def000089
+S A$crcccittmsbb$201 Def00007E
+S A$crcccittmsbb$120 Def00000E
+S A$crcccittmsbb$111 Def000005
+S A$crcccittmsbb$220 Def000095
+S A$crcccittmsbb$211 Def00008B
+S A$crcccittmsbb$202 Def00007F
+S A$crcccittmsbb$130 Def00001D
+S A$crcccittmsbb$121 Def00000F
+S A$crcccittmsbb$112 Def000006
+S A$crcccittmsbb$230 Def0000A7
+S A$crcccittmsbb$221 Def000096
+S A$crcccittmsbb$203 Def000080
+S A$crcccittmsbb$140 Def000028
+S A$crcccittmsbb$131 Def00001F
+S A$crcccittmsbb$122 Def000010
+S A$crcccittmsbb$113 Def000007
+S A$crcccittmsbb$240 Def0000B4
+S A$crcccittmsbb$231 Def0000A8
+S A$crcccittmsbb$222 Def000098
+S A$crcccittmsbb$213 Def00008D
+S A$crcccittmsbb$204 Def000081
+S A$crcccittmsbb$150 Def000039
+S A$crcccittmsbb$141 Def00002A
+S A$crcccittmsbb$123 Def000011
+S A$crcccittmsbb$114 Def000008
+S A$crcccittmsbb$232 Def0000A9
+S A$crcccittmsbb$223 Def00009A
+S A$crcccittmsbb$214 Def00008E
+S A$crcccittmsbb$205 Def000082
+S A$crcccittmsbb$151 Def00003A
+S A$crcccittmsbb$142 Def00002C
+S A$crcccittmsbb$124 Def000013
+S A$crcccittmsbb$115 Def000009
+S A$crcccittmsbb$233 Def0000AA
+S A$crcccittmsbb$224 Def00009C
+S A$crcccittmsbb$215 Def00008F
+S A$crcccittmsbb$170 Def000054
+S A$crcccittmsbb$161 Def000044
+S A$crcccittmsbb$152 Def00003B
+S A$crcccittmsbb$143 Def00002E
+S A$crcccittmsbb$134 Def000022
+S A$crcccittmsbb$125 Def000014
+S A$crcccittmsbb$116 Def00000A
+S A$crcccittmsbb$234 Def0000AB
+S A$crcccittmsbb$225 Def00009E
+S A$crcccittmsbb$216 Def000090
+S A$crcccittmsbb$207 Def000083
+S A$crcccittmsbb$171 Def000056
+S A$crcccittmsbb$162 Def000045
+S A$crcccittmsbb$144 Def000030
+S A$crcccittmsbb$135 Def000023
+S A$crcccittmsbb$126 Def000016
+S A$crcccittmsbb$117 Def00000B
+S A$crcccittmsbb$108 Def000000
+S A$crcccittmsbb$226 Def0000A0
+S A$crcccittmsbb$217 Def000092
+S A$crcccittmsbb$208 Def000085
+S A$crcccittmsbb$190 Def00006B
+S A$crcccittmsbb$181 Def000060
+S A$crcccittmsbb$172 Def000057
+S A$crcccittmsbb$163 Def000046
+S A$crcccittmsbb$154 Def00003C
+S A$crcccittmsbb$145 Def000032
+S A$crcccittmsbb$118 Def00000C
+S A$crcccittmsbb$109 Def000002
+S A$crcccittmsbb$236 Def0000AC
+S A$crcccittmsbb$227 Def0000A2
+S A$crcccittmsbb$209 Def000087
+S A$crcccittmsbb$191 Def00006C
+S A$crcccittmsbb$182 Def000062
+S A$crcccittmsbb$173 Def000058
+S A$crcccittmsbb$164 Def000048
+S A$crcccittmsbb$155 Def00003E
+S A$crcccittmsbb$146 Def000034
+S A$crcccittmsbb$137 Def000024
+S A$crcccittmsbb$128 Def000017
+S A$crcccittmsbb$119 Def00000D
+S A$crcccittmsbb$237 Def0000AE
+S A$crcccittmsbb$228 Def0000A4
+S A$crcccittmsbb$219 Def000094
+S A$crcccittmsbb$192 Def00006D
+S A$crcccittmsbb$183 Def000064
+S A$crcccittmsbb$174 Def000059
+S A$crcccittmsbb$165 Def00004A
+S A$crcccittmsbb$156 Def000040
+S A$crcccittmsbb$147 Def000036
+S A$crcccittmsbb$138 Def000025
+S A$crcccittmsbb$129 Def00001A
+S C$crcccittmsbb.c$10$0$0 Def000000
+S A$crcccittmsbb$238 Def0000B0
+S A$crcccittmsbb$229 Def0000A6
+S A$crcccittmsbb$193 Def00006F
+S A$crcccittmsbb$175 Def00005A
+S A$crcccittmsbb$166 Def00004C
+S A$crcccittmsbb$148 Def000037
+S A$crcccittmsbb$139 Def000026
+S A$crcccittmsbb$239 Def0000B2
+S A$crcccittmsbb$194 Def000071
+S A$crcccittmsbb$185 Def000065
+S A$crcccittmsbb$176 Def00005B
+S A$crcccittmsbb$167 Def00004E
+S A$crcccittmsbb$158 Def000042
+S A$crcccittmsbb$149 Def000038
+S A$crcccittmsbb$195 Def000073
+S A$crcccittmsbb$186 Def000066
+S A$crcccittmsbb$168 Def000050
+S A$crcccittmsbb$159 Def000043
+S A$crcccittmsbb$196 Def000075
+S A$crcccittmsbb$187 Def000067
+S A$crcccittmsbb$178 Def00005C
+S A$crcccittmsbb$169 Def000052
+S A$crcccittmsbb$197 Def000077
+S A$crcccittmsbb$188 Def000069
+S A$crcccittmsbb$179 Def00005E
+S A$crcccittmsbb$198 Def000079
+S A$crcccittmsbb$199 Def00007B
+S G$crc_ccitt_msb$0$0 Def000000
+S _crc_ccitt_msb Def000000
+S XG$crc_ccitt_msb$0$0 Def0000B6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 02
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 02
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 02
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 02
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 02 F1 83 0B 00 02
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 02 F1 83 0C 00 02
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crcccittmsbb
+F:G$crc_ccitt_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrcccittmsbb.crc_ccitt_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrcccittmsbb.crc_ccitt_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrcccittmsbb.crc_ccitt_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansib
+
+;!FILE libmflarge/crc16ansib.asm
+XH3
+H 1A areas 81 global symbols
+M crc16ansib
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S C$crc16ansib.c$228$1$63 Def000000
+S A$crc16ansib$200 Def00007C
+S A$crc16ansib$110 Def000004
+S C$crc16ansib.c$229$1$63 Def0000B6
+S A$crc16ansib$210 Def000089
+S A$crc16ansib$201 Def00007D
+S A$crc16ansib$120 Def00000E
+S A$crc16ansib$111 Def000005
+S A$crc16ansib$220 Def000095
+S A$crc16ansib$211 Def00008B
+S A$crc16ansib$202 Def00007E
+S A$crc16ansib$130 Def00001D
+S A$crc16ansib$121 Def00000F
+S A$crc16ansib$112 Def000006
+S G$crc_crc16$0$0 Def000000
+S A$crc16ansib$230 Def0000A6
+S A$crc16ansib$221 Def000096
+S A$crc16ansib$203 Def00007F
+S A$crc16ansib$140 Def000028
+S A$crc16ansib$131 Def00001F
+S A$crc16ansib$122 Def000010
+S A$crc16ansib$113 Def000007
+S A$crc16ansib$240 Def0000B4
+S A$crc16ansib$231 Def0000A7
+S A$crc16ansib$222 Def000098
+S A$crc16ansib$213 Def00008D
+S A$crc16ansib$204 Def000081
+S A$crc16ansib$150 Def000038
+S A$crc16ansib$141 Def00002A
+S A$crc16ansib$123 Def000011
+S A$crc16ansib$114 Def000008
+S A$crc16ansib$232 Def0000A8
+S A$crc16ansib$223 Def00009A
+S A$crc16ansib$214 Def00008E
+S A$crc16ansib$205 Def000082
+S A$crc16ansib$151 Def00003A
+S A$crc16ansib$142 Def00002C
+S A$crc16ansib$124 Def000013
+S A$crc16ansib$115 Def000009
+S A$crc16ansib$233 Def0000AA
+S A$crc16ansib$224 Def00009C
+S A$crc16ansib$215 Def00008F
+S A$crc16ansib$170 Def000054
+S A$crc16ansib$161 Def000044
+S A$crc16ansib$152 Def00003B
+S A$crc16ansib$143 Def00002E
+S A$crc16ansib$134 Def000022
+S A$crc16ansib$125 Def000014
+S A$crc16ansib$116 Def00000A
+S A$crc16ansib$234 Def0000AB
+S A$crc16ansib$225 Def00009E
+S A$crc16ansib$216 Def000090
+S A$crc16ansib$207 Def000083
+S A$crc16ansib$171 Def000055
+S A$crc16ansib$162 Def000045
+S A$crc16ansib$144 Def000030
+S A$crc16ansib$135 Def000023
+S A$crc16ansib$126 Def000016
+S A$crc16ansib$117 Def00000B
+S A$crc16ansib$108 Def000000
+S A$crc16ansib$226 Def0000A0
+S A$crc16ansib$217 Def000092
+S A$crc16ansib$208 Def000085
+S A$crc16ansib$190 Def00006B
+S A$crc16ansib$181 Def000060
+S A$crc16ansib$172 Def000056
+S A$crc16ansib$163 Def000046
+S A$crc16ansib$154 Def00003C
+S A$crc16ansib$145 Def000032
+S A$crc16ansib$118 Def00000C
+S A$crc16ansib$109 Def000002
+S A$crc16ansib$236 Def0000AC
+S A$crc16ansib$227 Def0000A2
+S A$crc16ansib$209 Def000087
+S A$crc16ansib$191 Def00006C
+S A$crc16ansib$182 Def000062
+S A$crc16ansib$173 Def000057
+S A$crc16ansib$164 Def000048
+S A$crc16ansib$155 Def00003E
+S A$crc16ansib$146 Def000034
+S A$crc16ansib$137 Def000024
+S A$crc16ansib$128 Def000017
+S A$crc16ansib$119 Def00000D
+S A$crc16ansib$237 Def0000AE
+S A$crc16ansib$228 Def0000A4
+S A$crc16ansib$219 Def000094
+S A$crc16ansib$192 Def00006D
+S A$crc16ansib$183 Def000064
+S A$crc16ansib$174 Def000058
+S A$crc16ansib$165 Def00004A
+S A$crc16ansib$156 Def000040
+S A$crc16ansib$147 Def000035
+S A$crc16ansib$138 Def000025
+S A$crc16ansib$129 Def00001A
+S C$crc16ansib.c$10$0$0 Def000000
+S A$crc16ansib$238 Def0000B0
+S A$crc16ansib$229 Def0000A5
+S A$crc16ansib$193 Def00006F
+S A$crc16ansib$175 Def00005A
+S A$crc16ansib$166 Def00004C
+S A$crc16ansib$148 Def000036
+S A$crc16ansib$139 Def000026
+S A$crc16ansib$239 Def0000B2
+S A$crc16ansib$194 Def000071
+S A$crc16ansib$185 Def000065
+S A$crc16ansib$176 Def00005B
+S A$crc16ansib$167 Def00004E
+S A$crc16ansib$158 Def000042
+S A$crc16ansib$149 Def000037
+S A$crc16ansib$195 Def000073
+S A$crc16ansib$186 Def000066
+S A$crc16ansib$168 Def000050
+S A$crc16ansib$159 Def000043
+S A$crc16ansib$196 Def000075
+S A$crc16ansib$187 Def000067
+S A$crc16ansib$178 Def00005C
+S A$crc16ansib$169 Def000052
+S _crc_crc16 Def000000
+S A$crc16ansib$197 Def000077
+S A$crc16ansib$188 Def000069
+S A$crc16ansib$179 Def00005E
+S A$crc16ansib$198 Def000079
+S A$crc16ansib$199 Def00007B
+S XG$crc_crc16$0$0 Def0000B6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16ansib
+F:G$crc_crc16$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansib.crc_crc16$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16ansib.crc_crc16$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16ansib.crc_crc16$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16ansimsbb
+
+;!FILE libmflarge/crc16ansimsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16ansimsbb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S XG$crc_crc16_msb$0$0 Def0000B6
+S C$crc16ansimsbb.c$228$1$63 Def000000
+S A$crc16ansimsbb$200 Def00007D
+S A$crc16ansimsbb$110 Def000004
+S C$crc16ansimsbb.c$229$1$63 Def0000B6
+S A$crc16ansimsbb$210 Def000089
+S A$crc16ansimsbb$201 Def00007E
+S A$crc16ansimsbb$120 Def00000E
+S A$crc16ansimsbb$111 Def000005
+S A$crc16ansimsbb$220 Def000095
+S A$crc16ansimsbb$211 Def00008B
+S A$crc16ansimsbb$202 Def00007F
+S A$crc16ansimsbb$130 Def00001D
+S A$crc16ansimsbb$121 Def00000F
+S A$crc16ansimsbb$112 Def000006
+S A$crc16ansimsbb$230 Def0000A7
+S A$crc16ansimsbb$221 Def000096
+S A$crc16ansimsbb$203 Def000080
+S A$crc16ansimsbb$140 Def000028
+S A$crc16ansimsbb$131 Def00001F
+S A$crc16ansimsbb$122 Def000010
+S A$crc16ansimsbb$113 Def000007
+S A$crc16ansimsbb$240 Def0000B4
+S A$crc16ansimsbb$231 Def0000A8
+S A$crc16ansimsbb$222 Def000098
+S A$crc16ansimsbb$213 Def00008D
+S A$crc16ansimsbb$204 Def000081
+S A$crc16ansimsbb$150 Def000039
+S A$crc16ansimsbb$141 Def00002A
+S A$crc16ansimsbb$123 Def000011
+S A$crc16ansimsbb$114 Def000008
+S A$crc16ansimsbb$232 Def0000A9
+S A$crc16ansimsbb$223 Def00009A
+S A$crc16ansimsbb$214 Def00008E
+S A$crc16ansimsbb$205 Def000082
+S A$crc16ansimsbb$151 Def00003A
+S A$crc16ansimsbb$142 Def00002C
+S A$crc16ansimsbb$124 Def000013
+S A$crc16ansimsbb$115 Def000009
+S A$crc16ansimsbb$233 Def0000AA
+S A$crc16ansimsbb$224 Def00009C
+S A$crc16ansimsbb$215 Def00008F
+S A$crc16ansimsbb$170 Def000054
+S A$crc16ansimsbb$161 Def000044
+S A$crc16ansimsbb$152 Def00003B
+S A$crc16ansimsbb$143 Def00002E
+S A$crc16ansimsbb$134 Def000022
+S A$crc16ansimsbb$125 Def000014
+S A$crc16ansimsbb$116 Def00000A
+S A$crc16ansimsbb$234 Def0000AB
+S A$crc16ansimsbb$225 Def00009E
+S A$crc16ansimsbb$216 Def000090
+S A$crc16ansimsbb$207 Def000083
+S A$crc16ansimsbb$171 Def000056
+S A$crc16ansimsbb$162 Def000045
+S A$crc16ansimsbb$144 Def000030
+S A$crc16ansimsbb$135 Def000023
+S A$crc16ansimsbb$126 Def000016
+S A$crc16ansimsbb$117 Def00000B
+S A$crc16ansimsbb$108 Def000000
+S A$crc16ansimsbb$226 Def0000A0
+S A$crc16ansimsbb$217 Def000092
+S A$crc16ansimsbb$208 Def000085
+S A$crc16ansimsbb$190 Def00006B
+S A$crc16ansimsbb$181 Def000060
+S A$crc16ansimsbb$172 Def000057
+S A$crc16ansimsbb$163 Def000046
+S A$crc16ansimsbb$154 Def00003C
+S A$crc16ansimsbb$145 Def000032
+S A$crc16ansimsbb$118 Def00000C
+S A$crc16ansimsbb$109 Def000002
+S A$crc16ansimsbb$236 Def0000AC
+S A$crc16ansimsbb$227 Def0000A2
+S A$crc16ansimsbb$209 Def000087
+S A$crc16ansimsbb$191 Def00006C
+S A$crc16ansimsbb$182 Def000062
+S A$crc16ansimsbb$173 Def000058
+S A$crc16ansimsbb$164 Def000048
+S A$crc16ansimsbb$155 Def00003E
+S A$crc16ansimsbb$146 Def000034
+S A$crc16ansimsbb$137 Def000024
+S A$crc16ansimsbb$128 Def000017
+S A$crc16ansimsbb$119 Def00000D
+S A$crc16ansimsbb$237 Def0000AE
+S A$crc16ansimsbb$228 Def0000A4
+S A$crc16ansimsbb$219 Def000094
+S A$crc16ansimsbb$192 Def00006D
+S A$crc16ansimsbb$183 Def000064
+S A$crc16ansimsbb$174 Def000059
+S A$crc16ansimsbb$165 Def00004A
+S A$crc16ansimsbb$156 Def000040
+S A$crc16ansimsbb$147 Def000036
+S A$crc16ansimsbb$138 Def000025
+S A$crc16ansimsbb$129 Def00001A
+S C$crc16ansimsbb.c$10$0$0 Def000000
+S A$crc16ansimsbb$238 Def0000B0
+S A$crc16ansimsbb$229 Def0000A6
+S A$crc16ansimsbb$193 Def00006F
+S A$crc16ansimsbb$175 Def00005A
+S A$crc16ansimsbb$166 Def00004C
+S A$crc16ansimsbb$148 Def000037
+S A$crc16ansimsbb$139 Def000026
+S A$crc16ansimsbb$239 Def0000B2
+S A$crc16ansimsbb$194 Def000071
+S A$crc16ansimsbb$185 Def000065
+S A$crc16ansimsbb$176 Def00005B
+S A$crc16ansimsbb$167 Def00004E
+S A$crc16ansimsbb$158 Def000042
+S A$crc16ansimsbb$149 Def000038
+S A$crc16ansimsbb$195 Def000073
+S A$crc16ansimsbb$186 Def000066
+S A$crc16ansimsbb$168 Def000050
+S A$crc16ansimsbb$159 Def000043
+S A$crc16ansimsbb$196 Def000075
+S A$crc16ansimsbb$187 Def000067
+S A$crc16ansimsbb$178 Def00005C
+S A$crc16ansimsbb$169 Def000052
+S A$crc16ansimsbb$197 Def000077
+S A$crc16ansimsbb$188 Def000069
+S A$crc16ansimsbb$179 Def00005E
+S A$crc16ansimsbb$198 Def000079
+S A$crc16ansimsbb$199 Def00007B
+S G$crc_crc16_msb$0$0 Def000000
+S _crc_crc16_msb Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16ansimsbb
+F:G$crc_crc16_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16ansimsbb.crc_crc16_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16ansimsbb.crc_crc16_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16ansimsbb.crc_crc16_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpb
+
+;!FILE libmflarge/crc16dnpb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16dnpb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc16dnp_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S G$crc_crc16dnp$0$0 Def000000
+S _crc_crc16dnp Def000000
+S C$crc16dnpb.c$228$1$63 Def000000
+S A$crc16dnpb$200 Def00007C
+S A$crc16dnpb$110 Def000004
+S C$crc16dnpb.c$229$1$63 Def0000B6
+S A$crc16dnpb$210 Def000089
+S A$crc16dnpb$201 Def00007D
+S A$crc16dnpb$120 Def00000E
+S A$crc16dnpb$111 Def000005
+S A$crc16dnpb$220 Def000095
+S A$crc16dnpb$211 Def00008B
+S A$crc16dnpb$202 Def00007E
+S A$crc16dnpb$130 Def00001D
+S A$crc16dnpb$121 Def00000F
+S A$crc16dnpb$112 Def000006
+S A$crc16dnpb$230 Def0000A6
+S A$crc16dnpb$221 Def000096
+S A$crc16dnpb$203 Def00007F
+S A$crc16dnpb$140 Def000028
+S A$crc16dnpb$131 Def00001F
+S A$crc16dnpb$122 Def000010
+S A$crc16dnpb$113 Def000007
+S A$crc16dnpb$240 Def0000B4
+S A$crc16dnpb$231 Def0000A7
+S A$crc16dnpb$222 Def000098
+S A$crc16dnpb$213 Def00008D
+S A$crc16dnpb$204 Def000081
+S A$crc16dnpb$150 Def000038
+S A$crc16dnpb$141 Def00002A
+S A$crc16dnpb$123 Def000011
+S A$crc16dnpb$114 Def000008
+S A$crc16dnpb$232 Def0000A8
+S A$crc16dnpb$223 Def00009A
+S A$crc16dnpb$214 Def00008E
+S A$crc16dnpb$205 Def000082
+S A$crc16dnpb$151 Def00003A
+S A$crc16dnpb$142 Def00002C
+S A$crc16dnpb$124 Def000013
+S A$crc16dnpb$115 Def000009
+S XG$crc_crc16dnp$0$0 Def0000B6
+S A$crc16dnpb$233 Def0000AA
+S A$crc16dnpb$224 Def00009C
+S A$crc16dnpb$215 Def00008F
+S A$crc16dnpb$170 Def000054
+S A$crc16dnpb$161 Def000044
+S A$crc16dnpb$152 Def00003B
+S A$crc16dnpb$143 Def00002E
+S A$crc16dnpb$134 Def000022
+S A$crc16dnpb$125 Def000014
+S A$crc16dnpb$116 Def00000A
+S A$crc16dnpb$234 Def0000AB
+S A$crc16dnpb$225 Def00009E
+S A$crc16dnpb$216 Def000090
+S A$crc16dnpb$207 Def000083
+S A$crc16dnpb$171 Def000055
+S A$crc16dnpb$162 Def000045
+S A$crc16dnpb$144 Def000030
+S A$crc16dnpb$135 Def000023
+S A$crc16dnpb$126 Def000016
+S A$crc16dnpb$117 Def00000B
+S A$crc16dnpb$108 Def000000
+S A$crc16dnpb$226 Def0000A0
+S A$crc16dnpb$217 Def000092
+S A$crc16dnpb$208 Def000085
+S A$crc16dnpb$190 Def00006B
+S A$crc16dnpb$181 Def000060
+S A$crc16dnpb$172 Def000056
+S A$crc16dnpb$163 Def000046
+S A$crc16dnpb$154 Def00003C
+S A$crc16dnpb$145 Def000032
+S A$crc16dnpb$118 Def00000C
+S A$crc16dnpb$109 Def000002
+S A$crc16dnpb$236 Def0000AC
+S A$crc16dnpb$227 Def0000A2
+S A$crc16dnpb$209 Def000087
+S A$crc16dnpb$191 Def00006C
+S A$crc16dnpb$182 Def000062
+S A$crc16dnpb$173 Def000057
+S A$crc16dnpb$164 Def000048
+S A$crc16dnpb$155 Def00003E
+S A$crc16dnpb$146 Def000034
+S A$crc16dnpb$137 Def000024
+S A$crc16dnpb$128 Def000017
+S A$crc16dnpb$119 Def00000D
+S A$crc16dnpb$237 Def0000AE
+S A$crc16dnpb$228 Def0000A4
+S A$crc16dnpb$219 Def000094
+S A$crc16dnpb$192 Def00006D
+S A$crc16dnpb$183 Def000064
+S A$crc16dnpb$174 Def000058
+S A$crc16dnpb$165 Def00004A
+S A$crc16dnpb$156 Def000040
+S A$crc16dnpb$147 Def000035
+S A$crc16dnpb$138 Def000025
+S A$crc16dnpb$129 Def00001A
+S C$crc16dnpb.c$10$0$0 Def000000
+S A$crc16dnpb$238 Def0000B0
+S A$crc16dnpb$229 Def0000A5
+S A$crc16dnpb$193 Def00006F
+S A$crc16dnpb$175 Def00005A
+S A$crc16dnpb$166 Def00004C
+S A$crc16dnpb$148 Def000036
+S A$crc16dnpb$139 Def000026
+S A$crc16dnpb$239 Def0000B2
+S A$crc16dnpb$194 Def000071
+S A$crc16dnpb$185 Def000065
+S A$crc16dnpb$176 Def00005B
+S A$crc16dnpb$167 Def00004E
+S A$crc16dnpb$158 Def000042
+S A$crc16dnpb$149 Def000037
+S A$crc16dnpb$195 Def000073
+S A$crc16dnpb$186 Def000066
+S A$crc16dnpb$168 Def000050
+S A$crc16dnpb$159 Def000043
+S A$crc16dnpb$196 Def000075
+S A$crc16dnpb$187 Def000067
+S A$crc16dnpb$178 Def00005C
+S A$crc16dnpb$169 Def000052
+S A$crc16dnpb$197 Def000077
+S A$crc16dnpb$188 Def000069
+S A$crc16dnpb$179 Def00005E
+S A$crc16dnpb$198 Def000079
+S A$crc16dnpb$199 Def00007B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 38 74 01 93 FD DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6C 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 04
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 E4 93 6D FC
+R 00 00 00 16 F1 83 07 00 04
+T 00 00 58 74 01 93 FD DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6C 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 04 F1 83 0B 00 04
+T 00 00 7B E4 93 6D FC 74 01 93 FD 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6C 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 A3 83 E4 93 6D FC 74 01 93 FD 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16dnpb
+F:G$crc_crc16dnp$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpb.crc_crc16dnp$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16dnpb.crc_crc16dnp$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16dnpb.crc_crc16dnp$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc16dnpmsbb
+
+;!FILE libmflarge/crc16dnpmsbb.asm
+XH3
+H 1A areas 81 global symbols
+M crc16dnpmsbb
+O -mmcs51 --model-large
+S _crc_crc16dnp_msbtable Ref000000
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size B6 flags 20 addr 0
+S XG$crc_crc16dnp_msb$0$0 Def0000B6
+S C$crc16dnpmsbb.c$228$1$63 Def000000
+S A$crc16dnpmsbb$200 Def00007D
+S A$crc16dnpmsbb$110 Def000004
+S C$crc16dnpmsbb.c$229$1$63 Def0000B6
+S A$crc16dnpmsbb$210 Def000089
+S A$crc16dnpmsbb$201 Def00007E
+S A$crc16dnpmsbb$120 Def00000E
+S A$crc16dnpmsbb$111 Def000005
+S A$crc16dnpmsbb$220 Def000095
+S A$crc16dnpmsbb$211 Def00008B
+S A$crc16dnpmsbb$202 Def00007F
+S A$crc16dnpmsbb$130 Def00001D
+S A$crc16dnpmsbb$121 Def00000F
+S A$crc16dnpmsbb$112 Def000006
+S A$crc16dnpmsbb$230 Def0000A7
+S A$crc16dnpmsbb$221 Def000096
+S A$crc16dnpmsbb$203 Def000080
+S A$crc16dnpmsbb$140 Def000028
+S A$crc16dnpmsbb$131 Def00001F
+S A$crc16dnpmsbb$122 Def000010
+S A$crc16dnpmsbb$113 Def000007
+S A$crc16dnpmsbb$240 Def0000B4
+S A$crc16dnpmsbb$231 Def0000A8
+S A$crc16dnpmsbb$222 Def000098
+S A$crc16dnpmsbb$213 Def00008D
+S A$crc16dnpmsbb$204 Def000081
+S A$crc16dnpmsbb$150 Def000039
+S A$crc16dnpmsbb$141 Def00002A
+S A$crc16dnpmsbb$123 Def000011
+S A$crc16dnpmsbb$114 Def000008
+S A$crc16dnpmsbb$232 Def0000A9
+S A$crc16dnpmsbb$223 Def00009A
+S A$crc16dnpmsbb$214 Def00008E
+S A$crc16dnpmsbb$205 Def000082
+S A$crc16dnpmsbb$151 Def00003A
+S A$crc16dnpmsbb$142 Def00002C
+S A$crc16dnpmsbb$124 Def000013
+S A$crc16dnpmsbb$115 Def000009
+S A$crc16dnpmsbb$233 Def0000AA
+S A$crc16dnpmsbb$224 Def00009C
+S A$crc16dnpmsbb$215 Def00008F
+S A$crc16dnpmsbb$170 Def000054
+S A$crc16dnpmsbb$161 Def000044
+S A$crc16dnpmsbb$152 Def00003B
+S A$crc16dnpmsbb$143 Def00002E
+S A$crc16dnpmsbb$134 Def000022
+S A$crc16dnpmsbb$125 Def000014
+S A$crc16dnpmsbb$116 Def00000A
+S A$crc16dnpmsbb$234 Def0000AB
+S A$crc16dnpmsbb$225 Def00009E
+S A$crc16dnpmsbb$216 Def000090
+S A$crc16dnpmsbb$207 Def000083
+S A$crc16dnpmsbb$171 Def000056
+S A$crc16dnpmsbb$162 Def000045
+S A$crc16dnpmsbb$144 Def000030
+S A$crc16dnpmsbb$135 Def000023
+S A$crc16dnpmsbb$126 Def000016
+S A$crc16dnpmsbb$117 Def00000B
+S A$crc16dnpmsbb$108 Def000000
+S A$crc16dnpmsbb$226 Def0000A0
+S A$crc16dnpmsbb$217 Def000092
+S A$crc16dnpmsbb$208 Def000085
+S A$crc16dnpmsbb$190 Def00006B
+S A$crc16dnpmsbb$181 Def000060
+S A$crc16dnpmsbb$172 Def000057
+S A$crc16dnpmsbb$163 Def000046
+S A$crc16dnpmsbb$154 Def00003C
+S A$crc16dnpmsbb$145 Def000032
+S A$crc16dnpmsbb$118 Def00000C
+S A$crc16dnpmsbb$109 Def000002
+S A$crc16dnpmsbb$236 Def0000AC
+S A$crc16dnpmsbb$227 Def0000A2
+S A$crc16dnpmsbb$209 Def000087
+S A$crc16dnpmsbb$191 Def00006C
+S A$crc16dnpmsbb$182 Def000062
+S A$crc16dnpmsbb$173 Def000058
+S A$crc16dnpmsbb$164 Def000048
+S A$crc16dnpmsbb$155 Def00003E
+S A$crc16dnpmsbb$146 Def000034
+S A$crc16dnpmsbb$137 Def000024
+S A$crc16dnpmsbb$128 Def000017
+S A$crc16dnpmsbb$119 Def00000D
+S A$crc16dnpmsbb$237 Def0000AE
+S A$crc16dnpmsbb$228 Def0000A4
+S A$crc16dnpmsbb$219 Def000094
+S A$crc16dnpmsbb$192 Def00006D
+S A$crc16dnpmsbb$183 Def000064
+S A$crc16dnpmsbb$174 Def000059
+S A$crc16dnpmsbb$165 Def00004A
+S A$crc16dnpmsbb$156 Def000040
+S A$crc16dnpmsbb$147 Def000036
+S A$crc16dnpmsbb$138 Def000025
+S A$crc16dnpmsbb$129 Def00001A
+S C$crc16dnpmsbb.c$10$0$0 Def000000
+S A$crc16dnpmsbb$238 Def0000B0
+S A$crc16dnpmsbb$229 Def0000A6
+S A$crc16dnpmsbb$193 Def00006F
+S A$crc16dnpmsbb$175 Def00005A
+S A$crc16dnpmsbb$166 Def00004C
+S A$crc16dnpmsbb$148 Def000037
+S A$crc16dnpmsbb$139 Def000026
+S A$crc16dnpmsbb$239 Def0000B2
+S A$crc16dnpmsbb$194 Def000071
+S A$crc16dnpmsbb$185 Def000065
+S A$crc16dnpmsbb$176 Def00005B
+S A$crc16dnpmsbb$167 Def00004E
+S A$crc16dnpmsbb$158 Def000042
+S A$crc16dnpmsbb$149 Def000038
+S G$crc_crc16dnp_msb$0$0 Def000000
+S A$crc16dnpmsbb$195 Def000073
+S A$crc16dnpmsbb$186 Def000066
+S A$crc16dnpmsbb$168 Def000050
+S A$crc16dnpmsbb$159 Def000043
+S A$crc16dnpmsbb$196 Def000075
+S A$crc16dnpmsbb$187 Def000067
+S A$crc16dnpmsbb$178 Def00005C
+S A$crc16dnpmsbb$169 Def000052
+S A$crc16dnpmsbb$197 Def000077
+S A$crc16dnpmsbb$188 Def000069
+S A$crc16dnpmsbb$179 Def00005E
+S A$crc16dnpmsbb$198 Def000079
+S A$crc16dnpmsbb$199 Def00007B
+S _crc_crc16dnp_msb Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FB F8 E6 FC 08 E6 FD 08 E6 FA
+R 00 00 00 16
+T 00 00 0D 08 E6 FB 4A 60 4D EA 60 01 0B
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 20 00 00 00 73 30 00 00 00 48 A8 82 20
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 20 00 00 00 20
+R 00 00 00 16 F1 23 03 00 02
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 E6 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 00
+T 00 00 2D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 00
+T 00 00 38 FD E4 93 FC DA E4 DB E2 80 1E
+R 00 00 00 16
+T 00 00 42
+R 00 00 00 16
+T 00 00 42 E2 08 6D 23 F5 82 54 FE 24 00 00 00 C5
+R 00 00 00 16 F1 03 0C 00 00
+T 00 00 4D 82 54 01 34 00 00 00 F5 83 74 01 93 6C
+R 00 00 00 16 F1 83 07 00 00
+T 00 00 58 FD E4 93 FC DA E4 DB E2
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 E0 A3 A8 82 A9 83 6D 23 F5 82 54 FE 24
+R 00 00 00 16
+T 00 00 72 00 00 00 C5 82 54 01 34 00 00 00 F5 83
+R 00 00 00 16 F1 03 03 00 00 F1 83 0B 00 00
+T 00 00 7B 74 01 93 6C FD E4 93 FC 89 83 88 82 DA
+R 00 00 00 16
+T 00 00 88 DC DB DA 80 D3
+R 00 00 00 16
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D E4 93 A3 A8 82 A9 83 6D 23 F5 82 54 FE
+R 00 00 00 16
+T 00 00 9A 24 00 00 00 C5 82 54 01 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 00 F1 83 0C 00 00
+T 00 00 A3 83 74 01 93 6C FD E4 93 FC 89 83 88 82
+R 00 00 00 16
+T 00 00 B0 DA DB DB D9 80 AA
+R 00 00 00 16
+
+
+M:crc16dnpmsbb
+F:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$crc$1$62({2}SI:U),B,1,-6
+S:Lcrc16dnpmsbb.crc_crc16dnp_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansib
+
+;!FILE libmflarge/crc32ansib.asm
+XH3
+H 1A areas AE global symbols
+M crc32ansib
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc32_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size ED flags 20 addr 0
+S A$crc32ansib$200 Def000077
+S A$crc32ansib$110 Def000004
+S A$crc32ansib$120 Def00000E
+S A$crc32ansib$111 Def000005
+S A$crc32ansib$220 Def00008E
+S A$crc32ansib$211 Def000084
+S A$crc32ansib$202 Def000078
+S A$crc32ansib$130 Def000019
+S A$crc32ansib$121 Def00000F
+S A$crc32ansib$112 Def000006
+S G$crc_crc32$0$0 Def000000
+S A$crc32ansib$230 Def00009F
+S A$crc32ansib$221 Def00008F
+S A$crc32ansib$203 Def00007A
+S A$crc32ansib$140 Def000028
+S A$crc32ansib$131 Def00001A
+S A$crc32ansib$122 Def000010
+S A$crc32ansib$113 Def000007
+S A$crc32ansib$240 Def0000AB
+S A$crc32ansib$231 Def0000A0
+S A$crc32ansib$222 Def000091
+S A$crc32ansib$213 Def000086
+S A$crc32ansib$150 Def000035
+S A$crc32ansib$141 Def000029
+S A$crc32ansib$132 Def00001C
+S A$crc32ansib$123 Def000011
+S A$crc32ansib$114 Def000008
+S A$crc32ansib$250 Def0000B9
+S A$crc32ansib$241 Def0000AD
+S A$crc32ansib$232 Def0000A1
+S A$crc32ansib$223 Def000093
+S A$crc32ansib$214 Def000087
+S A$crc32ansib$205 Def00007C
+S A$crc32ansib$160 Def000043
+S A$crc32ansib$151 Def000037
+S A$crc32ansib$124 Def000012
+S A$crc32ansib$115 Def000009
+S A$crc32ansib$260 Def0000C5
+S A$crc32ansib$251 Def0000BA
+S A$crc32ansib$242 Def0000AE
+S A$crc32ansib$233 Def0000A3
+S A$crc32ansib$224 Def000095
+S A$crc32ansib$215 Def000088
+S A$crc32ansib$206 Def00007E
+S A$crc32ansib$170 Def00004F
+S A$crc32ansib$161 Def000044
+S A$crc32ansib$152 Def000039
+S A$crc32ansib$143 Def00002A
+S A$crc32ansib$134 Def00001D
+S A$crc32ansib$125 Def000013
+S A$crc32ansib$116 Def00000A
+S A$crc32ansib$270 Def0000D5
+S A$crc32ansib$261 Def0000C7
+S A$crc32ansib$252 Def0000BB
+S A$crc32ansib$234 Def0000A4
+S A$crc32ansib$225 Def000097
+S A$crc32ansib$216 Def00008A
+S A$crc32ansib$207 Def000080
+S A$crc32ansib$180 Def00005A
+S A$crc32ansib$171 Def000051
+S A$crc32ansib$162 Def000046
+S A$crc32ansib$153 Def00003B
+S A$crc32ansib$144 Def00002B
+S A$crc32ansib$135 Def000020
+S A$crc32ansib$126 Def000014
+S A$crc32ansib$117 Def00000B
+S A$crc32ansib$108 Def000000
+S A$crc32ansib$280 Def0000E2
+S A$crc32ansib$271 Def0000D7
+S A$crc32ansib$262 Def0000C9
+S A$crc32ansib$253 Def0000BC
+S A$crc32ansib$244 Def0000AF
+S A$crc32ansib$235 Def0000A5
+S A$crc32ansib$226 Def000099
+S A$crc32ansib$208 Def000082
+S A$crc32ansib$190 Def00006A
+S A$crc32ansib$181 Def00005C
+S A$crc32ansib$163 Def000047
+S A$crc32ansib$154 Def00003C
+S A$crc32ansib$145 Def00002C
+S A$crc32ansib$136 Def000023
+S A$crc32ansib$127 Def000015
+S A$crc32ansib$118 Def00000C
+S A$crc32ansib$109 Def000002
+S A$crc32ansib$272 Def0000D8
+S A$crc32ansib$263 Def0000CB
+S A$crc32ansib$254 Def0000BE
+S A$crc32ansib$245 Def0000B1
+S A$crc32ansib$236 Def0000A6
+S A$crc32ansib$227 Def00009B
+S A$crc32ansib$218 Def00008C
+S A$crc32ansib$209 Def000083
+S A$crc32ansib$191 Def00006C
+S A$crc32ansib$182 Def00005E
+S A$crc32ansib$173 Def000053
+S A$crc32ansib$164 Def000048
+S A$crc32ansib$155 Def00003D
+S A$crc32ansib$146 Def00002D
+S A$crc32ansib$137 Def000025
+S A$crc32ansib$128 Def000016
+S A$crc32ansib$119 Def00000D
+S A$crc32ansib$282 Def0000E3
+S A$crc32ansib$273 Def0000D9
+S A$crc32ansib$264 Def0000CD
+S A$crc32ansib$246 Def0000B3
+S A$crc32ansib$237 Def0000A8
+S A$crc32ansib$228 Def00009D
+S A$crc32ansib$219 Def00008D
+S A$crc32ansib$192 Def00006D
+S A$crc32ansib$183 Def000060
+S A$crc32ansib$174 Def000054
+S A$crc32ansib$165 Def000049
+S A$crc32ansib$156 Def00003E
+S A$crc32ansib$147 Def00002F
+S A$crc32ansib$129 Def000017
+S C$crc32ansib.c$10$0$0 Def000000
+S A$crc32ansib$283 Def0000E5
+S A$crc32ansib$274 Def0000DA
+S A$crc32ansib$265 Def0000CF
+S A$crc32ansib$256 Def0000C0
+S A$crc32ansib$247 Def0000B5
+S A$crc32ansib$238 Def0000A9
+S A$crc32ansib$229 Def00009E
+S A$crc32ansib$193 Def00006E
+S A$crc32ansib$184 Def000062
+S A$crc32ansib$166 Def00004B
+S A$crc32ansib$157 Def00003F
+S A$crc32ansib$148 Def000031
+S A$crc32ansib$284 Def0000E7
+S A$crc32ansib$275 Def0000DC
+S A$crc32ansib$266 Def0000D1
+S A$crc32ansib$257 Def0000C1
+S A$crc32ansib$248 Def0000B7
+S A$crc32ansib$239 Def0000AA
+S A$crc32ansib$194 Def00006F
+S A$crc32ansib$185 Def000064
+S A$crc32ansib$176 Def000055
+S A$crc32ansib$167 Def00004C
+S A$crc32ansib$158 Def000041
+S A$crc32ansib$149 Def000033
+S A$crc32ansib$285 Def0000E9
+S A$crc32ansib$276 Def0000DD
+S A$crc32ansib$267 Def0000D2
+S A$crc32ansib$258 Def0000C2
+S A$crc32ansib$195 Def000071
+S A$crc32ansib$186 Def000066
+S A$crc32ansib$177 Def000056
+S A$crc32ansib$159 Def000042
+S A$crc32ansib$286 Def0000EB
+S A$crc32ansib$277 Def0000DE
+S A$crc32ansib$268 Def0000D3
+S A$crc32ansib$259 Def0000C3
+S A$crc32ansib$196 Def000072
+S A$crc32ansib$187 Def000067
+S A$crc32ansib$178 Def000057
+S A$crc32ansib$169 Def00004D
+S _crc_crc32 Def000000
+S A$crc32ansib$278 Def0000DF
+S A$crc32ansib$269 Def0000D4
+S A$crc32ansib$197 Def000073
+S A$crc32ansib$188 Def000068
+S A$crc32ansib$179 Def000058
+S A$crc32ansib$279 Def0000E1
+S A$crc32ansib$198 Def000074
+S A$crc32ansib$189 Def000069
+S A$crc32ansib$199 Def000076
+S XG$crc_crc32$0$0 Def0000ED
+S C$crc32ansib.c$311$1$63 Def000000
+S C$crc32ansib.c$312$1$63 Def0000ED
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 F9 F8 E6 FC 08 E6 FD 08 E6 FE
+R 00 00 00 16
+T 00 00 0D 08 E6 FF 08 E6 FA 08 E6 FB 4A 60 63 EA
+R 00 00 00 16
+T 00 00 1A 60 01 0B
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 20 00 00 00 64 30 00 00 00 63 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 26 00 00 00 2B
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6C 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 33 C5 82 54 03 34 00 00 00 F5 83 E4 93 6D
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 3E FC 74 01 93 6E FD 74 02 93 6F FE 74 03
+R 00 00 00 16
+T 00 00 4B 93 FF DA D9 DB D7 80 29
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 E2 08 6C 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 5E C5 82 54 03 34 00 00 00 F5 83 E4 93 6D
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 69 FC 74 01 93 6E FD 74 02 93 6F FE 74 03
+R 00 00 00 16
+T 00 00 76 93 FF DA D9 DB D7
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C 8C 82 8D 83 8E F0 EF 22
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 80 33
+R 00 00 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 E0 A3 A8 82 A9 83 6C 23 23 F5 82 54 FC
+R 00 00 00 16
+T 00 00 93 24 00 00 00 C5 82 54 03 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 9C 83 E4 93 6D FC 74 01 93 6E FD 74 02 93
+R 00 00 00 16
+T 00 00 A9 6F FE 74 03 93 FF 89 83 88 82 DA D1 DB
+R 00 00 00 16
+T 00 00 B6 CF 80 C3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 E4 93 A3 A8 82 A9 83 6C 23 23 F5 82 54
+R 00 00 00 16
+T 00 00 C6 FC 24 00 00 00 C5 82 54 03 34 00 00 00
+R 00 00 00 16 F1 03 05 00 04 F1 83 0D 00 04
+T 00 00 CF F5 83 E4 93 6D FC 74 01 93 6E FD 74 02
+R 00 00 00 16
+T 00 00 DC 93 6F FE 74 03 93 FF 89 83 88 82 DA D0
+R 00 00 00 16
+T 00 00 E9 DB CE 80 8F
+R 00 00 00 16
+
+
+M:crc32ansib
+F:G$crc_crc32$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansib.crc_crc32$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc32ansib.crc_crc32$crc$1$62({4}SL:U),B,1,-8
+S:Lcrc32ansib.crc_crc32$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crc32ansimsbb
+
+;!FILE libmflarge/crc32ansimsbb.asm
+XH3
+H 1A areas AE global symbols
+M crc32ansimsbb
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+S _crc_crc32_msbtable Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size ED flags 20 addr 0
+S XG$crc_crc32_msb$0$0 Def0000ED
+S C$crc32ansimsbb.c$312$1$63 Def0000ED
+S A$crc32ansimsbb$200 Def000077
+S A$crc32ansimsbb$110 Def000004
+S A$crc32ansimsbb$120 Def00000E
+S A$crc32ansimsbb$111 Def000005
+S A$crc32ansimsbb$220 Def00008E
+S A$crc32ansimsbb$211 Def000084
+S A$crc32ansimsbb$202 Def000078
+S A$crc32ansimsbb$130 Def000019
+S A$crc32ansimsbb$121 Def00000F
+S A$crc32ansimsbb$112 Def000006
+S A$crc32ansimsbb$230 Def0000A0
+S A$crc32ansimsbb$221 Def00008F
+S A$crc32ansimsbb$203 Def00007A
+S A$crc32ansimsbb$140 Def000028
+S A$crc32ansimsbb$131 Def00001A
+S A$crc32ansimsbb$122 Def000010
+S A$crc32ansimsbb$113 Def000007
+S A$crc32ansimsbb$240 Def0000AC
+S A$crc32ansimsbb$231 Def0000A1
+S A$crc32ansimsbb$222 Def000091
+S A$crc32ansimsbb$213 Def000086
+S A$crc32ansimsbb$150 Def000035
+S A$crc32ansimsbb$141 Def000029
+S A$crc32ansimsbb$132 Def00001C
+S A$crc32ansimsbb$123 Def000011
+S A$crc32ansimsbb$114 Def000008
+S A$crc32ansimsbb$250 Def0000B9
+S A$crc32ansimsbb$241 Def0000AD
+S A$crc32ansimsbb$232 Def0000A2
+S A$crc32ansimsbb$223 Def000093
+S A$crc32ansimsbb$214 Def000087
+S A$crc32ansimsbb$205 Def00007C
+S A$crc32ansimsbb$160 Def000044
+S A$crc32ansimsbb$151 Def000037
+S A$crc32ansimsbb$124 Def000012
+S A$crc32ansimsbb$115 Def000009
+S A$crc32ansimsbb$260 Def0000C5
+S A$crc32ansimsbb$251 Def0000BA
+S A$crc32ansimsbb$242 Def0000AE
+S A$crc32ansimsbb$233 Def0000A4
+S A$crc32ansimsbb$224 Def000095
+S A$crc32ansimsbb$215 Def000088
+S A$crc32ansimsbb$206 Def00007E
+S A$crc32ansimsbb$170 Def00004F
+S A$crc32ansimsbb$161 Def000045
+S A$crc32ansimsbb$152 Def000039
+S A$crc32ansimsbb$143 Def00002A
+S A$crc32ansimsbb$134 Def00001D
+S A$crc32ansimsbb$125 Def000013
+S A$crc32ansimsbb$116 Def00000A
+S A$crc32ansimsbb$270 Def0000D6
+S A$crc32ansimsbb$261 Def0000C7
+S A$crc32ansimsbb$252 Def0000BB
+S A$crc32ansimsbb$234 Def0000A5
+S A$crc32ansimsbb$225 Def000097
+S A$crc32ansimsbb$216 Def00008A
+S A$crc32ansimsbb$207 Def000080
+S A$crc32ansimsbb$180 Def00005A
+S A$crc32ansimsbb$171 Def000051
+S A$crc32ansimsbb$162 Def000047
+S A$crc32ansimsbb$153 Def00003B
+S A$crc32ansimsbb$144 Def00002B
+S A$crc32ansimsbb$135 Def000020
+S A$crc32ansimsbb$126 Def000014
+S A$crc32ansimsbb$117 Def00000B
+S A$crc32ansimsbb$108 Def000000
+S A$crc32ansimsbb$280 Def0000E2
+S A$crc32ansimsbb$271 Def0000D8
+S A$crc32ansimsbb$262 Def0000C9
+S A$crc32ansimsbb$253 Def0000BC
+S A$crc32ansimsbb$244 Def0000AF
+S A$crc32ansimsbb$235 Def0000A6
+S A$crc32ansimsbb$226 Def000099
+S A$crc32ansimsbb$208 Def000082
+S A$crc32ansimsbb$190 Def00006B
+S A$crc32ansimsbb$181 Def00005C
+S A$crc32ansimsbb$163 Def000048
+S A$crc32ansimsbb$154 Def00003D
+S A$crc32ansimsbb$145 Def00002C
+S A$crc32ansimsbb$136 Def000023
+S A$crc32ansimsbb$127 Def000015
+S A$crc32ansimsbb$118 Def00000C
+S A$crc32ansimsbb$109 Def000002
+S A$crc32ansimsbb$272 Def0000D9
+S A$crc32ansimsbb$263 Def0000CB
+S A$crc32ansimsbb$254 Def0000BE
+S A$crc32ansimsbb$245 Def0000B1
+S A$crc32ansimsbb$236 Def0000A7
+S A$crc32ansimsbb$227 Def00009B
+S A$crc32ansimsbb$218 Def00008C
+S A$crc32ansimsbb$209 Def000083
+S A$crc32ansimsbb$191 Def00006D
+S A$crc32ansimsbb$182 Def00005E
+S A$crc32ansimsbb$173 Def000053
+S A$crc32ansimsbb$164 Def000049
+S A$crc32ansimsbb$155 Def00003E
+S A$crc32ansimsbb$146 Def00002D
+S A$crc32ansimsbb$137 Def000025
+S A$crc32ansimsbb$128 Def000016
+S A$crc32ansimsbb$119 Def00000D
+S A$crc32ansimsbb$282 Def0000E3
+S A$crc32ansimsbb$273 Def0000DA
+S A$crc32ansimsbb$264 Def0000CD
+S A$crc32ansimsbb$246 Def0000B3
+S A$crc32ansimsbb$237 Def0000A9
+S A$crc32ansimsbb$228 Def00009D
+S A$crc32ansimsbb$219 Def00008D
+S A$crc32ansimsbb$192 Def00006E
+S A$crc32ansimsbb$183 Def000060
+S A$crc32ansimsbb$174 Def000054
+S A$crc32ansimsbb$165 Def00004A
+S A$crc32ansimsbb$156 Def00003F
+S A$crc32ansimsbb$147 Def00002F
+S A$crc32ansimsbb$129 Def000017
+S C$crc32ansimsbb.c$10$0$0 Def000000
+S A$crc32ansimsbb$283 Def0000E5
+S A$crc32ansimsbb$274 Def0000DB
+S A$crc32ansimsbb$265 Def0000CF
+S A$crc32ansimsbb$256 Def0000C0
+S A$crc32ansimsbb$247 Def0000B5
+S A$crc32ansimsbb$238 Def0000AA
+S A$crc32ansimsbb$229 Def00009F
+S A$crc32ansimsbb$193 Def00006F
+S A$crc32ansimsbb$184 Def000062
+S A$crc32ansimsbb$166 Def00004B
+S A$crc32ansimsbb$157 Def000040
+S A$crc32ansimsbb$148 Def000031
+S A$crc32ansimsbb$284 Def0000E7
+S A$crc32ansimsbb$275 Def0000DD
+S A$crc32ansimsbb$266 Def0000D1
+S A$crc32ansimsbb$257 Def0000C1
+S A$crc32ansimsbb$248 Def0000B7
+S A$crc32ansimsbb$239 Def0000AB
+S A$crc32ansimsbb$194 Def000070
+S A$crc32ansimsbb$185 Def000064
+S A$crc32ansimsbb$176 Def000055
+S A$crc32ansimsbb$167 Def00004C
+S A$crc32ansimsbb$158 Def000042
+S A$crc32ansimsbb$149 Def000033
+S A$crc32ansimsbb$285 Def0000E9
+S A$crc32ansimsbb$276 Def0000DE
+S A$crc32ansimsbb$267 Def0000D3
+S A$crc32ansimsbb$258 Def0000C2
+S A$crc32ansimsbb$195 Def000072
+S A$crc32ansimsbb$186 Def000066
+S A$crc32ansimsbb$177 Def000056
+S A$crc32ansimsbb$159 Def000043
+S A$crc32ansimsbb$286 Def0000EB
+S A$crc32ansimsbb$277 Def0000DF
+S A$crc32ansimsbb$268 Def0000D4
+S A$crc32ansimsbb$259 Def0000C3
+S A$crc32ansimsbb$196 Def000073
+S A$crc32ansimsbb$187 Def000068
+S A$crc32ansimsbb$178 Def000057
+S A$crc32ansimsbb$169 Def00004D
+S A$crc32ansimsbb$278 Def0000E0
+S A$crc32ansimsbb$269 Def0000D5
+S A$crc32ansimsbb$197 Def000074
+S A$crc32ansimsbb$188 Def000069
+S A$crc32ansimsbb$179 Def000058
+S A$crc32ansimsbb$279 Def0000E1
+S A$crc32ansimsbb$198 Def000075
+S A$crc32ansimsbb$189 Def00006A
+S A$crc32ansimsbb$199 Def000076
+S G$crc_crc32_msb$0$0 Def000000
+S _crc_crc32_msb Def000000
+S C$crc32ansimsbb.c$311$1$63 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 F9 F8 E6 FC 08 E6 FD 08 E6 FE
+R 00 00 00 16
+T 00 00 0D 08 E6 FF 08 E6 FA 08 E6 FB 4A 60 63 EA
+R 00 00 00 16
+T 00 00 1A 60 01 0B
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 20 00 00 00 64 30 00 00 00 63 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 26 00 00 00 2B
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 E6 08 6F 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 33 C5 82 54 03 34 00 00 00 F5 83 74 03 93
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 3E 6E FF 74 02 93 6D FE 74 01 93 6C FD E4
+R 00 00 00 16
+T 00 00 4B 93 FC DA D9 DB D7 80 29
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 E2 08 6F 23 23 F5 82 54 FC 24 00 00 00
+R 00 00 00 16 F1 03 0D 00 04
+T 00 00 5E C5 82 54 03 34 00 00 00 F5 83 74 03 93
+R 00 00 00 16 F1 83 08 00 04
+T 00 00 69 6E FF 74 02 93 6D FE 74 01 93 6C FD E4
+R 00 00 00 16
+T 00 00 76 93 FC DA D9 DB D7
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C 8C 82 8D 83 8E F0 EF 22
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 80 33
+R 00 00 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 E0 A3 A8 82 A9 83 6F 23 23 F5 82 54 FC
+R 00 00 00 16
+T 00 00 93 24 00 00 00 C5 82 54 03 34 00 00 00 F5
+R 00 00 00 16 F1 03 04 00 04 F1 83 0C 00 04
+T 00 00 9C 83 74 03 93 6E FF 74 02 93 6D FE 74 01
+R 00 00 00 16
+T 00 00 A9 93 6C FD E4 93 FC 89 83 88 82 DA D1 DB
+R 00 00 00 16
+T 00 00 B6 CF 80 C3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 E4 93 A3 A8 82 A9 83 6F 23 23 F5 82 54
+R 00 00 00 16
+T 00 00 C6 FC 24 00 00 00 C5 82 54 03 34 00 00 00
+R 00 00 00 16 F1 03 05 00 04 F1 83 0D 00 04
+T 00 00 CF F5 83 74 03 93 6E FF 74 02 93 6D FE 74
+R 00 00 00 16
+T 00 00 DC 01 93 6C FD E4 93 FC 89 83 88 82 DA D0
+R 00 00 00 16
+T 00 00 E9 DB CE 80 8F
+R 00 00 00 16
+
+
+M:crc32ansimsbb
+F:G$crc_crc32_msb$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lcrc32ansimsbb.crc_crc32_msb$buflen$1$62({2}SI:U),B,1,-4
+S:Lcrc32ansimsbb.crc_crc32_msb$crc$1$62({4}SL:U),B,1,-8
+S:Lcrc32ansimsbb.crc_crc32_msb$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+crcccitttable
+
+XH3
+H 1A areas 3 global symbols
+M crcccitttable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_ccitt_table$0$0 Def000000
+S _crc_ccitt_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 89 11 12 23 9B 32 24 46 AD 57 36
+R 00 00 00 17
+T 00 00 0D 65 BF 74 48 8C C1 9D 5A AF D3 BE 6C CA
+R 00 00 00 17
+T 00 00 1A E5 DB 7E E9 F7 F8 81 10 08 01 93 33 1A
+R 00 00 00 17
+T 00 00 27 22 A5 56 2C 47 B7 75 3E 64 C9 9C 40 8D
+R 00 00 00 17
+T 00 00 34 DB BF 52 AE ED DA 64 CB FF F9 76 E8 02
+R 00 00 00 17
+T 00 00 41 21 8B 30 10 02 99 13 26 67 AF 76 34 44
+R 00 00 00 17
+T 00 00 4E BD 55 4A AD C3 BC 58 8E D1 9F 6E EB E7
+R 00 00 00 17
+T 00 00 5B FA 7C C8 F5 D9 83 31 0A 20 91 12 18 03
+R 00 00 00 17
+T 00 00 68 A7 77 2E 66 B5 54 3C 45 CB BD 42 AC D9
+R 00 00 00 17
+T 00 00 75 9E 50 8F EF FB 66 EA FD D8 74 C9 04 42
+R 00 00 00 17
+T 00 00 82 8D 53 16 61 9F 70 20 04 A9 15 32 27 BB
+R 00 00 00 17
+T 00 00 8F 36 4C CE C5 DF 5E ED D7 FC 68 88 E1 99
+R 00 00 00 17
+T 00 00 9C 7A AB F3 BA 85 52 0C 43 97 71 1E 60 A1
+R 00 00 00 17
+T 00 00 A9 14 28 05 B3 37 3A 26 CD DE 44 CF DF FD
+R 00 00 00 17
+T 00 00 B6 56 EC E9 98 60 89 FB BB 72 AA 06 63 8F
+R 00 00 00 17
+T 00 00 C3 72 14 40 9D 51 22 25 AB 34 30 06 B9 17
+R 00 00 00 17
+T 00 00 D0 4E EF C7 FE 5C CC D5 DD 6A A9 E3 B8 78
+R 00 00 00 17
+T 00 00 DD 8A F1 9B 87 73 0E 62 95 50 1C 41 A3 35
+R 00 00 00 17
+T 00 00 EA 2A 24 B1 16 38 07 CF FF 46 EE DD DC 54
+R 00 00 00 17
+T 00 00 F7 CD EB B9 62 A8 F9 9A 70 8B 08 84 81 95
+R 00 00 00 17
+T 00 01 04 1A A7 93 B6 2C C2 A5 D3 3E E1 B7 F0 40
+R 00 00 00 17
+T 00 01 11 08 C9 19 52 2B DB 3A 64 4E ED 5F 76 6D
+R 00 00 00 17
+T 00 01 1E FF 7C 89 94 00 85 9B B7 12 A6 AD D2 24
+R 00 00 00 17
+T 00 01 2B C3 BF F1 36 E0 C1 18 48 09 D3 3B 5A 2A
+R 00 00 00 17
+T 00 01 38 E5 5E 6C 4F F7 7D 7E 6C 0A A5 83 B4 18
+R 00 00 00 17
+T 00 01 45 86 91 97 2E E3 A7 F2 3C C0 B5 D1 42 29
+R 00 00 00 17
+T 00 01 52 CB 38 50 0A D9 1B 66 6F EF 7E 74 4C FD
+R 00 00 00 17
+T 00 01 5F 5D 8B B5 02 A4 99 96 10 87 AF F3 26 E2
+R 00 00 00 17
+T 00 01 6C BD D0 34 C1 C3 39 4A 28 D1 1A 58 0B E7
+R 00 00 00 17
+T 00 01 79 7F 6E 6E F5 5C 7C 4D 0C C6 85 D7 1E E5
+R 00 00 00 17
+T 00 01 86 97 F4 28 80 A1 91 3A A3 B3 B2 44 4A CD
+R 00 00 00 17
+T 00 01 93 5B 56 69 DF 78 60 0C E9 1D 72 2F FB 3E
+R 00 00 00 17
+T 00 01 A0 8D D6 04 C7 9F F5 16 E4 A9 90 20 81 BB
+R 00 00 00 17
+T 00 01 AD B3 32 A2 C5 5A 4C 4B D7 79 5E 68 E1 1C
+R 00 00 00 17
+T 00 01 BA 68 0D F3 3F 7A 2E 0E E7 87 F6 1C C4 95
+R 00 00 00 17
+T 00 01 C7 D5 2A A1 A3 B0 38 82 B1 93 46 6B CF 7A
+R 00 00 00 17
+T 00 01 D4 54 48 DD 59 62 2D EB 3C 70 0E F9 1F 8F
+R 00 00 00 17
+T 00 01 E1 F7 06 E6 9D D4 14 C5 AB B1 22 A0 B9 92
+R 00 00 00 17
+T 00 01 EE 30 83 C7 7B 4E 6A D5 58 5C 49 E3 3D 6A
+R 00 00 00 17
+T 00 01 FB 2C F1 1E 78 0F
+R 00 00 00 17
+
+
+M:crcccitttable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16table
+
+XH3
+H 1A areas 3 global symbols
+M crc16table
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16_table$0$0 Def000000
+S _crc_crc16_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 C1 C0 81 C1 40 01 01 C3 C0 03 80
+R 00 00 00 17
+T 00 00 0D 02 41 C2 01 C6 C0 06 80 07 41 C7 00 05
+R 00 00 00 17
+T 00 00 1A C1 C5 81 C4 40 04 01 CC C0 0C 80 0D 41
+R 00 00 00 17
+T 00 00 27 CD 00 0F C1 CF 81 CE 40 0E 00 0A C1 CA
+R 00 00 00 17
+T 00 00 34 81 CB 40 0B 01 C9 C0 09 80 08 41 C8 01
+R 00 00 00 17
+T 00 00 41 D8 C0 18 80 19 41 D9 00 1B C1 DB 81 DA
+R 00 00 00 17
+T 00 00 4E 40 1A 00 1E C1 DE 81 DF 40 1F 01 DD C0
+R 00 00 00 17
+T 00 00 5B 1D 80 1C 41 DC 00 14 C1 D4 81 D5 40 15
+R 00 00 00 17
+T 00 00 68 01 D7 C0 17 80 16 41 D6 01 D2 C0 12 80
+R 00 00 00 17
+T 00 00 75 13 41 D3 00 11 C1 D1 81 D0 40 10 01 F0
+R 00 00 00 17
+T 00 00 82 C0 30 80 31 41 F1 00 33 C1 F3 81 F2 40
+R 00 00 00 17
+T 00 00 8F 32 00 36 C1 F6 81 F7 40 37 01 F5 C0 35
+R 00 00 00 17
+T 00 00 9C 80 34 41 F4 00 3C C1 FC 81 FD 40 3D 01
+R 00 00 00 17
+T 00 00 A9 FF C0 3F 80 3E 41 FE 01 FA C0 3A 80 3B
+R 00 00 00 17
+T 00 00 B6 41 FB 00 39 C1 F9 81 F8 40 38 00 28 C1
+R 00 00 00 17
+T 00 00 C3 E8 81 E9 40 29 01 EB C0 2B 80 2A 41 EA
+R 00 00 00 17
+T 00 00 D0 01 EE C0 2E 80 2F 41 EF 00 2D C1 ED 81
+R 00 00 00 17
+T 00 00 DD EC 40 2C 01 E4 C0 24 80 25 41 E5 00 27
+R 00 00 00 17
+T 00 00 EA C1 E7 81 E6 40 26 00 22 C1 E2 81 E3 40
+R 00 00 00 17
+T 00 00 F7 23 01 E1 C0 21 80 20 41 E0 01 A0 C0 60
+R 00 00 00 17
+T 00 01 04 80 61 41 A1 00 63 C1 A3 81 A2 40 62 00
+R 00 00 00 17
+T 00 01 11 66 C1 A6 81 A7 40 67 01 A5 C0 65 80 64
+R 00 00 00 17
+T 00 01 1E 41 A4 00 6C C1 AC 81 AD 40 6D 01 AF C0
+R 00 00 00 17
+T 00 01 2B 6F 80 6E 41 AE 01 AA C0 6A 80 6B 41 AB
+R 00 00 00 17
+T 00 01 38 00 69 C1 A9 81 A8 40 68 00 78 C1 B8 81
+R 00 00 00 17
+T 00 01 45 B9 40 79 01 BB C0 7B 80 7A 41 BA 01 BE
+R 00 00 00 17
+T 00 01 52 C0 7E 80 7F 41 BF 00 7D C1 BD 81 BC 40
+R 00 00 00 17
+T 00 01 5F 7C 01 B4 C0 74 80 75 41 B5 00 77 C1 B7
+R 00 00 00 17
+T 00 01 6C 81 B6 40 76 00 72 C1 B2 81 B3 40 73 01
+R 00 00 00 17
+T 00 01 79 B1 C0 71 80 70 41 B0 00 50 C1 90 81 91
+R 00 00 00 17
+T 00 01 86 40 51 01 93 C0 53 80 52 41 92 01 96 C0
+R 00 00 00 17
+T 00 01 93 56 80 57 41 97 00 55 C1 95 81 94 40 54
+R 00 00 00 17
+T 00 01 A0 01 9C C0 5C 80 5D 41 9D 00 5F C1 9F 81
+R 00 00 00 17
+T 00 01 AD 9E 40 5E 00 5A C1 9A 81 9B 40 5B 01 99
+R 00 00 00 17
+T 00 01 BA C0 59 80 58 41 98 01 88 C0 48 80 49 41
+R 00 00 00 17
+T 00 01 C7 89 00 4B C1 8B 81 8A 40 4A 00 4E C1 8E
+R 00 00 00 17
+T 00 01 D4 81 8F 40 4F 01 8D C0 4D 80 4C 41 8C 00
+R 00 00 00 17
+T 00 01 E1 44 C1 84 81 85 40 45 01 87 C0 47 80 46
+R 00 00 00 17
+T 00 01 EE 41 86 01 82 C0 42 80 43 41 83 00 41 C1
+R 00 00 00 17
+T 00 01 FB 81 81 80 40 40
+R 00 00 00 17
+
+
+M:crc16table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16dnptable
+
+XH3
+H 1A areas 3 global symbols
+M crc16dnptable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16dnp_table$0$0 Def000000
+S _crc_crc16dnp_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 5E 36 BC 6C E2 5A 78 D9 26 EF C4
+R 00 00 00 17
+T 00 00 0D B5 9A 83 89 FF D7 C9 35 93 6B A5 F1 26
+R 00 00 00 17
+T 00 00 1A AF 10 4D 4A 13 7C 6B B2 35 84 D7 DE 89
+R 00 00 00 17
+T 00 00 27 E8 13 6B 4D 5D AF 07 F1 31 E2 4D BC 7B
+R 00 00 00 17
+T 00 00 34 5E 21 00 17 9A 94 C4 A2 26 F8 78 CE AF
+R 00 00 00 17
+T 00 00 41 29 F1 1F 13 45 4D 73 D7 F0 89 C6 6B 9C
+R 00 00 00 17
+T 00 00 4E 35 AA 26 D6 78 E0 9A BA C4 8C 5E 0F 00
+R 00 00 00 17
+T 00 00 5B 39 E2 63 BC 55 C4 9B 9A AD 78 F7 26 C1
+R 00 00 00 17
+T 00 00 68 BC 42 E2 74 00 2E 5E 18 4D 64 13 52 F1
+R 00 00 00 17
+T 00 00 75 08 AF 3E 35 BD 6B 8B 89 D1 D7 E7 5E 53
+R 00 00 00 17
+T 00 00 82 00 65 E2 3F BC 09 26 8A 78 BC 9A E6 C4
+R 00 00 00 17
+T 00 00 8F D0 D7 AC 89 9A 6B C0 35 F6 AF 75 F1 43
+R 00 00 00 17
+T 00 00 9C 13 19 4D 2F 35 E1 6B D7 89 8D D7 BB 4D
+R 00 00 00 17
+T 00 00 A9 38 13 0E F1 54 AF 62 BC 1E E2 28 00 72
+R 00 00 00 17
+T 00 00 B6 5E 44 C4 C7 9A F1 78 AB 26 9D F1 7A AF
+R 00 00 00 17
+T 00 00 C3 4C 4D 16 13 20 89 A3 D7 95 35 CF 6B F9
+R 00 00 00 17
+T 00 00 D0 78 85 26 B3 C4 E9 9A DF 00 5C 5E 6A BC
+R 00 00 00 17
+T 00 00 DD 30 E2 06 9A C8 C4 FE 26 A4 78 92 E2 11
+R 00 00 00 17
+T 00 00 EA BC 27 5E 7D 00 4B 13 37 4D 01 AF 5B F1
+R 00 00 00 17
+T 00 00 F7 6D 6B EE 35 D8 D7 82 89 B4 BC A6 E2 90
+R 00 00 00 17
+T 00 01 04 00 CA 5E FC C4 7F 9A 49 78 13 26 25 35
+R 00 00 00 17
+T 00 01 11 59 6B 6F 89 35 D7 03 4D 80 13 B6 F1 EC
+R 00 00 00 17
+T 00 01 1E AF DA D7 14 89 22 6B 78 35 4E AF CD F1
+R 00 00 00 17
+T 00 01 2B FB 13 A1 4D 97 5E EB 00 DD E2 87 BC B1
+R 00 00 00 17
+T 00 01 38 26 32 78 04 9A 5E C4 68 13 8F 4D B9 AF
+R 00 00 00 17
+T 00 01 45 E3 F1 D5 6B 56 35 60 D7 3A 89 0C 9A 70
+R 00 00 00 17
+T 00 01 52 C4 46 26 1C 78 2A E2 A9 BC 9F 5E C5 00
+R 00 00 00 17
+T 00 01 5F F3 78 3D 26 0B C4 51 9A 67 00 E4 5E D2
+R 00 00 00 17
+T 00 01 6C BC 88 E2 BE F1 C2 AF F4 4D AE 13 98 89
+R 00 00 00 17
+T 00 01 79 1B D7 2D 35 77 6B 41 E2 F5 BC C3 5E 99
+R 00 00 00 17
+T 00 01 86 00 AF 9A 2C C4 1A 26 40 78 76 6B 0A 35
+R 00 00 00 17
+T 00 01 93 3C D7 66 89 50 13 D3 4D E5 AF BF F1 89
+R 00 00 00 17
+T 00 01 A0 89 47 D7 71 35 2B 6B 1D F1 9E AF A8 4D
+R 00 00 00 17
+T 00 01 AD F2 13 C4 00 B8 5E 8E BC D4 E2 E2 78 61
+R 00 00 00 17
+T 00 01 BA 26 57 C4 0D 9A 3B 4D DC 13 EA F1 B0 AF
+R 00 00 00 17
+T 00 01 C7 86 35 05 6B 33 89 69 D7 5F C4 23 9A 15
+R 00 00 00 17
+T 00 01 D4 78 4F 26 79 BC FA E2 CC 00 96 5E A0 26
+R 00 00 00 17
+T 00 01 E1 6E 78 58 9A 02 C4 34 5E B7 00 81 E2 DB
+R 00 00 00 17
+T 00 01 EE BC ED AF 91 F1 A7 13 FD 4D CB D7 48 89
+R 00 00 00 17
+T 00 01 FB 7E 6B 24 35 12
+R 00 00 00 17
+
+
+M:crc16dnptable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crcccittmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crcccittmsbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_ccitt_msbtable$0$0 Def000000
+S _crc_ccitt_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 21 10 42 20 63 30 84 40 A5 50 C6
+R 00 00 00 17
+T 00 00 0D 60 E7 70 08 81 29 91 4A A1 6B B1 8C C1
+R 00 00 00 17
+T 00 00 1A AD D1 CE E1 EF F1 31 12 10 02 73 32 52
+R 00 00 00 17
+T 00 00 27 22 B5 52 94 42 F7 72 D6 62 39 93 18 83
+R 00 00 00 17
+T 00 00 34 7B B3 5A A3 BD D3 9C C3 FF F3 DE E3 62
+R 00 00 00 17
+T 00 00 41 24 43 34 20 04 01 14 E6 64 C7 74 A4 44
+R 00 00 00 17
+T 00 00 4E 85 54 6A A5 4B B5 28 85 09 95 EE E5 CF
+R 00 00 00 17
+T 00 00 5B F5 AC C5 8D D5 53 36 72 26 11 16 30 06
+R 00 00 00 17
+T 00 00 68 D7 76 F6 66 95 56 B4 46 5B B7 7A A7 19
+R 00 00 00 17
+T 00 00 75 97 38 87 DF F7 FE E7 9D D7 BC C7 C4 48
+R 00 00 00 17
+T 00 00 82 E5 58 86 68 A7 78 40 08 61 18 02 28 23
+R 00 00 00 17
+T 00 00 8F 38 CC C9 ED D9 8E E9 AF F9 48 89 69 99
+R 00 00 00 17
+T 00 00 9C 0A A9 2B B9 F5 5A D4 4A B7 7A 96 6A 71
+R 00 00 00 17
+T 00 00 A9 1A 50 0A 33 3A 12 2A FD DB DC CB BF FB
+R 00 00 00 17
+T 00 00 B6 9E EB 79 9B 58 8B 3B BB 1A AB A6 6C 87
+R 00 00 00 17
+T 00 00 C3 7C E4 4C C5 5C 22 2C 03 3C 60 0C 41 1C
+R 00 00 00 17
+T 00 00 D0 AE ED 8F FD EC CD CD DD 2A AD 0B BD 68
+R 00 00 00 17
+T 00 00 DD 8D 49 9D 97 7E B6 6E D5 5E F4 4E 13 3E
+R 00 00 00 17
+T 00 00 EA 32 2E 51 1E 70 0E 9F FF BE EF DD DF FC
+R 00 00 00 17
+T 00 00 F7 CF 1B BF 3A AF 59 9F 78 8F 88 91 A9 81
+R 00 00 00 17
+T 00 01 04 CA B1 EB A1 0C D1 2D C1 4E F1 6F E1 80
+R 00 00 00 17
+T 00 01 11 10 A1 00 C2 30 E3 20 04 50 25 40 46 70
+R 00 00 00 17
+T 00 01 1E 67 60 B9 83 98 93 FB A3 DA B3 3D C3 1C
+R 00 00 00 17
+T 00 01 2B D3 7F E3 5E F3 B1 02 90 12 F3 22 D2 32
+R 00 00 00 17
+T 00 01 38 35 42 14 52 77 62 56 72 EA B5 CB A5 A8
+R 00 00 00 17
+T 00 01 45 95 89 85 6E F5 4F E5 2C D5 0D C5 E2 34
+R 00 00 00 17
+T 00 01 52 C3 24 A0 14 81 04 66 74 47 64 24 54 05
+R 00 00 00 17
+T 00 01 5F 44 DB A7 FA B7 99 87 B8 97 5F E7 7E F7
+R 00 00 00 17
+T 00 01 6C 1D C7 3C D7 D3 26 F2 36 91 06 B0 16 57
+R 00 00 00 17
+T 00 01 79 66 76 76 15 46 34 56 4C D9 6D C9 0E F9
+R 00 00 00 17
+T 00 01 86 2F E9 C8 99 E9 89 8A B9 AB A9 44 58 65
+R 00 00 00 17
+T 00 01 93 48 06 78 27 68 C0 18 E1 08 82 38 A3 28
+R 00 00 00 17
+T 00 01 A0 7D CB 5C DB 3F EB 1E FB F9 8B D8 9B BB
+R 00 00 00 17
+T 00 01 AD AB 9A BB 75 4A 54 5A 37 6A 16 7A F1 0A
+R 00 00 00 17
+T 00 01 BA D0 1A B3 2A 92 3A 2E FD 0F ED 6C DD 4D
+R 00 00 00 17
+T 00 01 C7 CD AA BD 8B AD E8 9D C9 8D 26 7C 07 6C
+R 00 00 00 17
+T 00 01 D4 64 5C 45 4C A2 3C 83 2C E0 1C C1 0C 1F
+R 00 00 00 17
+T 00 01 E1 EF 3E FF 5D CF 7C DF 9B AF BA BF D9 8F
+R 00 00 00 17
+T 00 01 EE F8 9F 17 6E 36 7E 55 4E 74 5E 93 2E B2
+R 00 00 00 17
+T 00 01 FB 3E D1 0E F0 1E
+R 00 00 00 17
+
+
+M:crcccittmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16msbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc16msbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$crc_crc16_msbtable$0$0 Def000000
+S _crc_crc16_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 05 80 0F 80 0A 00 1B 80 1E 00 14
+R 00 00 00 17
+T 00 00 0D 00 11 80 33 80 36 00 3C 00 39 80 28 00
+R 00 00 00 17
+T 00 00 1A 2D 80 27 80 22 00 63 80 66 00 6C 00 69
+R 00 00 00 17
+T 00 00 27 80 78 00 7D 80 77 80 72 00 50 00 55 80
+R 00 00 00 17
+T 00 00 34 5F 80 5A 00 4B 80 4E 00 44 00 41 80 C3
+R 00 00 00 17
+T 00 00 41 80 C6 00 CC 00 C9 80 D8 00 DD 80 D7 80
+R 00 00 00 17
+T 00 00 4E D2 00 F0 00 F5 80 FF 80 FA 00 EB 80 EE
+R 00 00 00 17
+T 00 00 5B 00 E4 00 E1 80 A0 00 A5 80 AF 80 AA 00
+R 00 00 00 17
+T 00 00 68 BB 80 BE 00 B4 00 B1 80 93 80 96 00 9C
+R 00 00 00 17
+T 00 00 75 00 99 80 88 00 8D 80 87 80 82 00 83 81
+R 00 00 00 17
+T 00 00 82 86 01 8C 01 89 81 98 01 9D 81 97 81 92
+R 00 00 00 17
+T 00 00 8F 01 B0 01 B5 81 BF 81 BA 01 AB 81 AE 01
+R 00 00 00 17
+T 00 00 9C A4 01 A1 81 E0 01 E5 81 EF 81 EA 01 FB
+R 00 00 00 17
+T 00 00 A9 81 FE 01 F4 01 F1 81 D3 81 D6 01 DC 01
+R 00 00 00 17
+T 00 00 B6 D9 81 C8 01 CD 81 C7 81 C2 01 40 01 45
+R 00 00 00 17
+T 00 00 C3 81 4F 81 4A 01 5B 81 5E 01 54 01 51 81
+R 00 00 00 17
+T 00 00 D0 73 81 76 01 7C 01 79 81 68 01 6D 81 67
+R 00 00 00 17
+T 00 00 DD 81 62 01 23 81 26 01 2C 01 29 81 38 01
+R 00 00 00 17
+T 00 00 EA 3D 81 37 81 32 01 10 01 15 81 1F 81 1A
+R 00 00 00 17
+T 00 00 F7 01 0B 81 0E 01 04 01 01 81 03 83 06 03
+R 00 00 00 17
+T 00 01 04 0C 03 09 83 18 03 1D 83 17 83 12 03 30
+R 00 00 00 17
+T 00 01 11 03 35 83 3F 83 3A 03 2B 83 2E 03 24 03
+R 00 00 00 17
+T 00 01 1E 21 83 60 03 65 83 6F 83 6A 03 7B 83 7E
+R 00 00 00 17
+T 00 01 2B 03 74 03 71 83 53 83 56 03 5C 03 59 83
+R 00 00 00 17
+T 00 01 38 48 03 4D 83 47 83 42 03 C0 03 C5 83 CF
+R 00 00 00 17
+T 00 01 45 83 CA 03 DB 83 DE 03 D4 03 D1 83 F3 83
+R 00 00 00 17
+T 00 01 52 F6 03 FC 03 F9 83 E8 03 ED 83 E7 83 E2
+R 00 00 00 17
+T 00 01 5F 03 A3 83 A6 03 AC 03 A9 83 B8 03 BD 83
+R 00 00 00 17
+T 00 01 6C B7 83 B2 03 90 03 95 83 9F 83 9A 03 8B
+R 00 00 00 17
+T 00 01 79 83 8E 03 84 03 81 83 80 02 85 82 8F 82
+R 00 00 00 17
+T 00 01 86 8A 02 9B 82 9E 02 94 02 91 82 B3 82 B6
+R 00 00 00 17
+T 00 01 93 02 BC 02 B9 82 A8 02 AD 82 A7 82 A2 02
+R 00 00 00 17
+T 00 01 A0 E3 82 E6 02 EC 02 E9 82 F8 02 FD 82 F7
+R 00 00 00 17
+T 00 01 AD 82 F2 02 D0 02 D5 82 DF 82 DA 02 CB 82
+R 00 00 00 17
+T 00 01 BA CE 02 C4 02 C1 82 43 82 46 02 4C 02 49
+R 00 00 00 17
+T 00 01 C7 82 58 02 5D 82 57 82 52 02 70 02 75 82
+R 00 00 00 17
+T 00 01 D4 7F 82 7A 02 6B 82 6E 02 64 02 61 82 20
+R 00 00 00 17
+T 00 01 E1 02 25 82 2F 82 2A 02 3B 82 3E 02 34 02
+R 00 00 00 17
+T 00 01 EE 31 82 13 82 16 02 1C 02 19 82 08 02 0D
+R 00 00 00 17
+T 00 01 FB 82 07 82 02 02
+R 00 00 00 17
+
+
+M:crc16msbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc16dnpmsbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc16dnpmsbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S _crc_crc16dnp_msbtable Def000000
+S G$crc_crc16dnp_msbtable$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 65 3D CA 7A AF 47 94 F5 F1 C8 5E
+R 00 00 00 17
+T 00 00 0D 8F 3B B2 4D D6 28 EB 87 AC E2 91 D9 23
+R 00 00 00 17
+T 00 00 1A BC 1E 13 59 76 64 FF 91 9A AC 35 EB 50
+R 00 00 00 17
+T 00 00 27 D6 6B 64 0E 59 A1 1E C4 23 B2 47 D7 7A
+R 00 00 00 17
+T 00 00 34 78 3D 1D 00 26 B2 43 8F EC C8 89 F5 9B
+R 00 00 00 17
+T 00 00 41 1E FE 23 51 64 34 59 0F EB 6A D6 C5 91
+R 00 00 00 17
+T 00 00 4E A0 AC D6 C8 B3 F5 1C B2 79 8F 42 3D 27
+R 00 00 00 17
+T 00 00 5B 00 88 47 ED 7A 64 8F 01 B2 AE F5 CB C8
+R 00 00 00 17
+T 00 00 68 F0 7A 95 47 3A 00 5F 3D 29 59 4C 64 E3
+R 00 00 00 17
+T 00 00 75 23 86 1E BD AC D8 91 77 D6 12 EB 36 3D
+R 00 00 00 17
+T 00 00 82 53 00 FC 47 99 7A A2 C8 C7 F5 68 B2 0D
+R 00 00 00 17
+T 00 00 8F 8F 7B EB 1E D6 B1 91 D4 AC EF 1E 8A 23
+R 00 00 00 17
+T 00 00 9C 25 64 40 59 C9 AC AC 91 03 D6 66 EB 5D
+R 00 00 00 17
+T 00 00 A9 59 38 64 97 23 F2 1E 84 7A E1 47 4E 00
+R 00 00 00 17
+T 00 00 B6 2B 3D 10 8F 75 B2 DA F5 BF C8 AD 23 C8
+R 00 00 00 17
+T 00 00 C3 1E 67 59 02 64 39 D6 5C EB F3 AC 96 91
+R 00 00 00 17
+T 00 00 D0 E0 F5 85 C8 2A 8F 4F B2 74 00 11 3D BE
+R 00 00 00 17
+T 00 00 DD 7A DB 47 52 B2 37 8F 98 C8 FD F5 C6 47
+R 00 00 00 17
+T 00 00 EA A3 7A 0C 3D 69 00 1F 64 7A 59 D5 1E B0
+R 00 00 00 17
+T 00 00 F7 23 8B 91 EE AC 41 EB 24 D6 6C 7A 09 47
+R 00 00 00 17
+T 00 01 04 A6 00 C3 3D F8 8F 9D B2 32 F5 57 C8 21
+R 00 00 00 17
+T 00 01 11 AC 44 91 EB D6 8E EB B5 59 D0 64 7F 23
+R 00 00 00 17
+T 00 01 1E 1A 1E 93 EB F6 D6 59 91 3C AC 07 1E 62
+R 00 00 00 17
+T 00 01 2B 23 CD 64 A8 59 DE 3D BB 00 14 47 71 7A
+R 00 00 00 17
+T 00 01 38 4A C8 2F F5 80 B2 E5 8F F7 64 92 59 3D
+R 00 00 00 17
+T 00 01 45 1E 58 23 63 91 06 AC A9 EB CC D6 BA B2
+R 00 00 00 17
+T 00 01 52 DF 8F 70 C8 15 F5 2E 47 4B 7A E4 3D 81
+R 00 00 00 17
+T 00 01 5F 00 08 F5 6D C8 C2 8F A7 B2 9C 00 F9 3D
+R 00 00 00 17
+T 00 01 6C 56 7A 33 47 45 23 20 1E 8F 59 EA 64 D1
+R 00 00 00 17
+T 00 01 79 D6 B4 EB 1B AC 7E 91 5A 47 3F 7A 90 3D
+R 00 00 00 17
+T 00 01 86 F5 00 CE B2 AB 8F 04 C8 61 F5 17 91 72
+R 00 00 00 17
+T 00 01 93 AC DD EB B8 D6 83 64 E6 59 49 1E 2C 23
+R 00 00 00 17
+T 00 01 A0 A5 D6 C0 EB 6F AC 0A 91 31 23 54 1E FB
+R 00 00 00 17
+T 00 01 AD 59 9E 64 E8 00 8D 3D 22 7A 47 47 7C F5
+R 00 00 00 17
+T 00 01 BA 19 C8 B6 8F D3 B2 C1 59 A4 64 0B 23 6E
+R 00 00 00 17
+T 00 01 C7 1E 55 AC 30 91 9F D6 FA EB 8C 8F E9 B2
+R 00 00 00 17
+T 00 01 D4 46 F5 23 C8 18 7A 7D 47 D2 00 B7 3D 3E
+R 00 00 00 17
+T 00 01 E1 C8 5B F5 F4 B2 91 8F AA 3D CF 00 60 47
+R 00 00 00 17
+T 00 01 EE 05 7A 73 1E 16 23 B9 64 DC 59 E7 EB 82
+R 00 00 00 17
+T 00 01 FB D6 2D 91 48 AC
+R 00 00 00 17
+
+
+M:crc16dnpmsbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+crc32table
+
+XH3
+H 1A areas 3 global symbols
+M crc32table
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 400 flags 20 addr 0
+S G$crc_crc32_table$0$0 Def000000
+S _crc_crc32_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 00 00 96 30 07 77 2C 61 0E EE BA
+R 00 00 00 17
+T 00 00 0D 51 09 99 19 C4 6D 07 8F F4 6A 70 35 A5
+R 00 00 00 17
+T 00 00 1A 63 E9 A3 95 64 9E 32 88 DB 0E A4 B8 DC
+R 00 00 00 17
+T 00 00 27 79 1E E9 D5 E0 88 D9 D2 97 2B 4C B6 09
+R 00 00 00 17
+T 00 00 34 BD 7C B1 7E 07 2D B8 E7 91 1D BF 90 64
+R 00 00 00 17
+T 00 00 41 10 B7 1D F2 20 B0 6A 48 71 B9 F3 DE 41
+R 00 00 00 17
+T 00 00 4E BE 84 7D D4 DA 1A EB E4 DD 6D 51 B5 D4
+R 00 00 00 17
+T 00 00 5B F4 C7 85 D3 83 56 98 6C 13 C0 A8 6B 64
+R 00 00 00 17
+T 00 00 68 7A F9 62 FD EC C9 65 8A 4F 5C 01 14 D9
+R 00 00 00 17
+T 00 00 75 6C 06 63 63 3D 0F FA F5 0D 08 8D C8 20
+R 00 00 00 17
+T 00 00 82 6E 3B 5E 10 69 4C E4 41 60 D5 72 71 67
+R 00 00 00 17
+T 00 00 8F A2 D1 E4 03 3C 47 D4 04 4B FD 85 0D D2
+R 00 00 00 17
+T 00 00 9C 6B B5 0A A5 FA A8 B5 35 6C 98 B2 42 D6
+R 00 00 00 17
+T 00 00 A9 C9 BB DB 40 F9 BC AC E3 6C D8 32 75 5C
+R 00 00 00 17
+T 00 00 B6 DF 45 CF 0D D6 DC 59 3D D1 AB AC 30 D9
+R 00 00 00 17
+T 00 00 C3 26 3A 00 DE 51 80 51 D7 C8 16 61 D0 BF
+R 00 00 00 17
+T 00 00 D0 B5 F4 B4 21 23 C4 B3 56 99 95 BA CF 0F
+R 00 00 00 17
+T 00 00 DD A5 BD B8 9E B8 02 28 08 88 05 5F B2 D9
+R 00 00 00 17
+T 00 00 EA 0C C6 24 E9 0B B1 87 7C 6F 2F 11 4C 68
+R 00 00 00 17
+T 00 00 F7 58 AB 1D 61 C1 3D 2D 66 B6 90 41 DC 76
+R 00 00 00 17
+T 00 01 04 06 71 DB 01 BC 20 D2 98 2A 10 D5 EF 89
+R 00 00 00 17
+T 00 01 11 85 B1 71 1F B5 B6 06 A5 E4 BF 9F 33 D4
+R 00 00 00 17
+T 00 01 1E B8 E8 A2 C9 07 78 34 F9 00 0F 8E A8 09
+R 00 00 00 17
+T 00 01 2B 96 18 98 0E E1 BB 0D 6A 7F 2D 3D 6D 08
+R 00 00 00 17
+T 00 01 38 97 6C 64 91 01 5C 63 E6 F4 51 6B 6B 62
+R 00 00 00 17
+T 00 01 45 61 6C 1C D8 30 65 85 4E 00 62 F2 ED 95
+R 00 00 00 17
+T 00 01 52 06 6C 7B A5 01 1B C1 F4 08 82 57 C4 0F
+R 00 00 00 17
+T 00 01 5F F5 C6 D9 B0 65 50 E9 B7 12 EA B8 BE 8B
+R 00 00 00 17
+T 00 01 6C 7C 88 B9 FC DF 1D DD 62 49 2D DA 15 F3
+R 00 00 00 17
+T 00 01 79 7C D3 8C 65 4C D4 FB 58 61 B2 4D CE 51
+R 00 00 00 17
+T 00 01 86 B5 3A 74 00 BC A3 E2 30 BB D4 41 A5 DF
+R 00 00 00 17
+T 00 01 93 4A D7 95 D8 3D 6D C4 D1 A4 FB F4 D6 D3
+R 00 00 00 17
+T 00 01 A0 6A E9 69 43 FC D9 6E 34 46 88 67 AD D0
+R 00 00 00 17
+T 00 01 AD B8 60 DA 73 2D 04 44 E5 1D 03 33 5F 4C
+R 00 00 00 17
+T 00 01 BA 0A AA C9 7C 0D DD 3C 71 05 50 AA 41 02
+R 00 00 00 17
+T 00 01 C7 27 10 10 0B BE 86 20 0C C9 25 B5 68 57
+R 00 00 00 17
+T 00 01 D4 B3 85 6F 20 09 D4 66 B9 9F E4 61 CE 0E
+R 00 00 00 17
+T 00 01 E1 F9 DE 5E 98 C9 D9 29 22 98 D0 B0 B4 A8
+R 00 00 00 17
+T 00 01 EE D7 C7 17 3D B3 59 81 0D B4 2E 3B 5C BD
+R 00 00 00 17
+T 00 01 FB B7 AD 6C BA C0 20 83 B8 ED B6 B3 BF 9A
+R 00 00 00 17
+T 00 02 08 0C E2 B6 03 9A D2 B1 74 39 47 D5 EA AF
+R 00 00 00 17
+T 00 02 15 77 D2 9D 15 26 DB 04 83 16 DC 73 12 0B
+R 00 00 00 17
+T 00 02 22 63 E3 84 3B 64 94 3E 6A 6D 0D A8 5A 6A
+R 00 00 00 17
+T 00 02 2F 7A 0B CF 0E E4 9D FF 09 93 27 AE 00 0A
+R 00 00 00 17
+T 00 02 3C B1 9E 07 7D 44 93 0F F0 D2 A3 08 87 68
+R 00 00 00 17
+T 00 02 49 F2 01 1E FE C2 06 69 5D 57 62 F7 CB 67
+R 00 00 00 17
+T 00 02 56 65 80 71 36 6C 19 E7 06 6B 6E 76 1B D4
+R 00 00 00 17
+T 00 02 63 FE E0 2B D3 89 5A 7A DA 10 CC 4A DD 67
+R 00 00 00 17
+T 00 02 70 6F DF B9 F9 F9 EF BE 8E 43 BE B7 17 D5
+R 00 00 00 17
+T 00 02 7D 8E B0 60 E8 A3 D6 D6 7E 93 D1 A1 C4 C2
+R 00 00 00 17
+T 00 02 8A D8 38 52 F2 DF 4F F1 67 BB D1 67 57 BC
+R 00 00 00 17
+T 00 02 97 A6 DD 06 B5 3F 4B 36 B2 48 DA 2B 0D D8
+R 00 00 00 17
+T 00 02 A4 4C 1B 0A AF F6 4A 03 36 60 7A 04 41 C3
+R 00 00 00 17
+T 00 02 B1 EF 60 DF 55 DF 67 A8 EF 8E 6E 31 79 BE
+R 00 00 00 17
+T 00 02 BE 69 46 8C B3 61 CB 1A 83 66 BC A0 D2 6F
+R 00 00 00 17
+T 00 02 CB 25 36 E2 68 52 95 77 0C CC 03 47 0B BB
+R 00 00 00 17
+T 00 02 D8 B9 16 02 22 2F 26 05 55 BE 3B BA C5 28
+R 00 00 00 17
+T 00 02 E5 0B BD B2 92 5A B4 2B 04 6A B3 5C A7 FF
+R 00 00 00 17
+T 00 02 F2 D7 C2 31 CF D0 B5 8B 9E D9 2C 1D AE DE
+R 00 00 00 17
+T 00 02 FF 5B B0 C2 64 9B 26 F2 63 EC 9C A3 6A 75
+R 00 00 00 17
+T 00 03 0C 0A 93 6D 02 A9 06 09 9C 3F 36 0E EB 85
+R 00 00 00 17
+T 00 03 19 67 07 72 13 57 00 05 82 4A BF 95 14 7A
+R 00 00 00 17
+T 00 03 26 B8 E2 AE 2B B1 7B 38 1B B6 0C 9B 8E D2
+R 00 00 00 17
+T 00 03 33 92 0D BE D5 E5 B7 EF DC 7C 21 DF DB 0B
+R 00 00 00 17
+T 00 03 40 D4 D2 D3 86 42 E2 D4 F1 F8 B3 DD 68 6E
+R 00 00 00 17
+T 00 03 4D 83 DA 1F CD 16 BE 81 5B 26 B9 F6 E1 77
+R 00 00 00 17
+T 00 03 5A B0 6F 77 47 B7 18 E6 5A 08 88 70 6A 0F
+R 00 00 00 17
+T 00 03 67 FF CA 3B 06 66 5C 0B 01 11 FF 9E 65 8F
+R 00 00 00 17
+T 00 03 74 69 AE 62 F8 D3 FF 6B 61 45 CF 6C 16 78
+R 00 00 00 17
+T 00 03 81 E2 0A A0 EE D2 0D D7 54 83 04 4E C2 B3
+R 00 00 00 17
+T 00 03 8E 03 39 61 26 67 A7 F7 16 60 D0 4D 47 69
+R 00 00 00 17
+T 00 03 9B 49 DB 77 6E 3E 4A 6A D1 AE DC 5A D6 D9
+R 00 00 00 17
+T 00 03 A8 66 0B DF 40 F0 3B D8 37 53 AE BC A9 C5
+R 00 00 00 17
+T 00 03 B5 9E BB DE 7F CF B2 47 E9 FF B5 30 1C F2
+R 00 00 00 17
+T 00 03 C2 BD BD 8A C2 BA CA 30 93 B3 53 A6 A3 B4
+R 00 00 00 17
+T 00 03 CF 24 05 36 D0 BA 93 06 D7 CD 29 57 DE 54
+R 00 00 00 17
+T 00 03 DC BF 67 D9 23 2E 7A 66 B3 B8 4A 61 C4 02
+R 00 00 00 17
+T 00 03 E9 1B 68 5D 94 2B 6F 2A 37 BE 0B B4 A1 8E
+R 00 00 00 17
+T 00 03 F6 0C C3 1B DF 05 5A 8D EF 02 2D
+R 00 00 00 17
+
+
+M:crc32table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+
+
+
+
+crc32msbtable
+
+XH3
+H 1A areas 3 global symbols
+M crc32msbtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 400 flags 20 addr 0
+S G$crc_crc32_msbtable$0$0 Def000000
+S _crc_crc32_msbtable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 00 00 B7 1D C1 04 6E 3B 82 09 D9
+R 00 00 00 17
+T 00 00 0D 26 43 0D DC 76 04 13 6B 6B C5 17 B2 4D
+R 00 00 00 17
+T 00 00 1A 86 1A 05 50 47 1E B8 ED 08 26 0F F0 C9
+R 00 00 00 17
+T 00 00 27 22 D6 D6 8A 2F 61 CB 4B 2B 64 9B 0C 35
+R 00 00 00 17
+T 00 00 34 D3 86 CD 31 0A A0 8E 3C BD BD 4F 38 70
+R 00 00 00 17
+T 00 00 41 DB 11 4C C7 C6 D0 48 1E E0 93 45 A9 FD
+R 00 00 00 17
+T 00 00 4E 52 41 AC AD 15 5F 1B B0 D4 5B C2 96 97
+R 00 00 00 17
+T 00 00 5B 56 75 8B 56 52 C8 36 19 6A 7F 2B D8 6E
+R 00 00 00 17
+T 00 00 68 A6 0D 9B 63 11 10 5A 67 14 40 1D 79 A3
+R 00 00 00 17
+T 00 00 75 5D DC 7D 7A 7B 9F 70 CD 66 5E 74 E0 B6
+R 00 00 00 17
+T 00 00 82 23 98 57 AB E2 9C 8E 8D A1 91 39 90 60
+R 00 00 00 17
+T 00 00 8F 95 3C C0 27 8B 8B DD E6 8F 52 FB A5 82
+R 00 00 00 17
+T 00 00 9C E5 E6 64 86 58 5B 2B BE EF 46 EA BA 36
+R 00 00 00 17
+T 00 00 A9 60 A9 B7 81 7D 68 B3 84 2D 2F AD 33 30
+R 00 00 00 17
+T 00 00 B6 EE A9 EA 16 AD A4 5D 0B 6C A0 90 6D 32
+R 00 00 00 17
+T 00 00 C3 D4 27 70 F3 D0 FE 56 B0 DD 49 4B 71 D9
+R 00 00 00 17
+T 00 00 D0 4C 1B 36 C7 FB 06 F7 C3 22 20 B4 CE 95
+R 00 00 00 17
+T 00 00 DD 3D 75 CA 28 80 3A F2 9F 9D FB F6 46 BB
+R 00 00 00 17
+T 00 00 EA B8 FB F1 A6 79 FF F4 F6 3E E1 43 EB FF
+R 00 00 00 17
+T 00 00 F7 E5 9A CD BC E8 2D D0 7D EC 77 70 86 34
+R 00 00 00 17
+T 00 01 04 C0 6D 47 30 19 4B 04 3D AE 56 C5 39 AB
+R 00 00 00 17
+T 00 01 11 06 82 27 1C 1B 43 23 C5 3D 00 2E 72 20
+R 00 00 00 17
+T 00 01 1E C1 2A CF 9D 8E 12 78 80 4F 16 A1 A6 0C
+R 00 00 00 17
+T 00 01 2B 1B 16 BB CD 1F 13 EB 8A 01 A4 F6 4B 05
+R 00 00 00 17
+T 00 01 38 7D D0 08 08 CA CD C9 0C 07 AB 97 78 B0
+R 00 00 00 17
+T 00 01 45 B6 56 7C 69 90 15 71 DE 8D D4 75 DB DD
+R 00 00 00 17
+T 00 01 52 93 6B 6C C0 52 6F B5 E6 11 62 02 FB D0
+R 00 00 00 17
+T 00 01 5F 66 BF 46 9F 5E 08 5B 5E 5A D1 7D 1D 57
+R 00 00 00 17
+T 00 01 6C 66 60 DC 53 63 30 9B 4D D4 2D 5A 49 0D
+R 00 00 00 17
+T 00 01 79 0B 19 44 BA 16 D8 40 97 C6 A5 AC 20 DB
+R 00 00 00 17
+T 00 01 86 64 A8 F9 FD 27 A5 4E E0 E6 A1 4B B0 A1
+R 00 00 00 17
+T 00 01 93 BF FC AD 60 BB 25 8B 23 B6 92 96 E2 B2
+R 00 00 00 17
+T 00 01 A0 2F 2B AD 8A 98 36 6C 8E 41 10 2F 83 F6
+R 00 00 00 17
+T 00 01 AD 0D EE 87 F3 5D A9 99 44 40 68 9D 9D 66
+R 00 00 00 17
+T 00 01 BA 2B 90 2A 7B EA 94 E7 1D B4 E0 50 00 75
+R 00 00 00 17
+T 00 01 C7 E4 89 26 36 E9 3E 3B F7 ED 3B 6B B0 F3
+R 00 00 00 17
+T 00 01 D4 8C 76 71 F7 55 50 32 FA E2 4D F3 FE 5F
+R 00 00 00 17
+T 00 01 E1 F0 BC C6 E8 ED 7D C2 31 CB 3E CF 86 D6
+R 00 00 00 17
+T 00 01 EE FF CB 83 86 B8 D5 34 9B 79 D1 ED BD 3A
+R 00 00 00 17
+T 00 01 FB DC 5A A0 FB D8 EE E0 0C 69 59 FD CD 6D
+R 00 00 00 17
+T 00 02 08 80 DB 8E 60 37 C6 4F 64 32 96 08 7A 85
+R 00 00 00 17
+T 00 02 15 8B C9 7E 5C AD 8A 73 EB B0 4B 77 56 0D
+R 00 00 00 17
+T 00 02 22 04 4F E1 10 C5 4B 38 36 86 46 8F 2B 47
+R 00 00 00 17
+T 00 02 2F 42 8A 7B 00 5C 3D 66 C1 58 E4 40 82 55
+R 00 00 00 17
+T 00 02 3C 53 5D 43 51 9E 3B 1D 25 29 26 DC 21 F0
+R 00 00 00 17
+T 00 02 49 00 9F 2C 47 1D 5E 28 42 4D 19 36 F5 50
+R 00 00 00 17
+T 00 02 56 D8 32 2C 76 9B 3F 9B 6B 5A 3B 26 D6 15
+R 00 00 00 17
+T 00 02 63 03 91 CB D4 07 48 ED 97 0A FF F0 56 0E
+R 00 00 00 17
+T 00 02 70 FA A0 11 10 4D BD D0 14 94 9B 93 19 23
+R 00 00 00 17
+T 00 02 7D 86 52 1D 0E 56 2F F1 B9 4B EE F5 60 6D
+R 00 00 00 17
+T 00 02 8A AD F8 D7 70 6C FC D2 20 2B E2 65 3D EA
+R 00 00 00 17
+T 00 02 97 E6 BC 1B A9 EB 0B 06 68 EF B6 BB 27 D7
+R 00 00 00 17
+T 00 02 A4 01 A6 E6 D3 D8 80 A5 DE 6F 9D 64 DA 6A
+R 00 00 00 17
+T 00 02 B1 CD 23 C4 DD D0 E2 C0 04 F6 A1 CD B3 EB
+R 00 00 00 17
+T 00 02 BE 60 C9 7E 8D 3E BD C9 90 FF B9 10 B6 BC
+R 00 00 00 17
+T 00 02 CB B4 A7 AB 7D B0 A2 FB 3A AE 15 E6 FB AA
+R 00 00 00 17
+T 00 02 D8 CC C0 B8 A7 7B DD 79 A3 C6 60 36 9B 71
+R 00 00 00 17
+T 00 02 E5 7D F7 9F A8 5B B4 92 1F 46 75 96 1A 16
+R 00 00 00 17
+T 00 02 F2 32 88 AD 0B F3 8C 74 2D B0 81 C3 30 71
+R 00 00 00 17
+T 00 02 FF 85 99 90 8A 5D 2E 8D 4B 59 F7 AB 08 54
+R 00 00 00 17
+T 00 03 0C 40 B6 C9 50 45 E6 8E 4E F2 FB 4F 4A 2B
+R 00 00 00 17
+T 00 03 19 DD 0C 47 9C C0 CD 43 21 7D 82 7B 96 60
+R 00 00 00 17
+T 00 03 26 43 7F 4F 46 00 72 F8 5B C1 76 FD 0B 86
+R 00 00 00 17
+T 00 03 33 68 4A 16 47 6C 93 30 04 61 24 2D C5 65
+R 00 00 00 17
+T 00 03 40 E9 4B 9B 11 5E 56 5A 15 87 70 19 18 30
+R 00 00 00 17
+T 00 03 4D 6D D8 1C 35 3D 9F 02 82 20 5E 06 5B 06
+R 00 00 00 17
+T 00 03 5A 1D 0B EC 1B DC 0F 51 A6 93 37 E6 BB 52
+R 00 00 00 17
+T 00 03 67 33 3F 9D 11 3E 88 80 D0 3A 8D D0 97 24
+R 00 00 00 17
+T 00 03 74 3A CD 56 20 E3 EB 15 2D 54 F6 D4 29 79
+R 00 00 00 17
+T 00 03 81 26 A9 C5 CE 3B 68 C1 17 1D 2B CC A0 00
+R 00 00 00 17
+T 00 03 8E EA C8 A5 50 AD D6 12 4D 6C D2 CB 6B 2F
+R 00 00 00 17
+T 00 03 9B DF 7C 76 EE DB C1 CB A1 E3 76 D6 60 E7
+R 00 00 00 17
+T 00 03 A8 AF F0 23 EA 18 ED E2 EE 1D BD A5 F0 AA
+R 00 00 00 17
+T 00 03 B5 A0 64 F4 73 86 27 F9 C4 9B E6 FD 09 FD
+R 00 00 00 17
+T 00 03 C2 B8 89 BE E0 79 8D 67 C6 3A 80 D0 DB FB
+R 00 00 00 17
+T 00 03 CF 84 D5 8B BC 9A 62 96 7D 9E BB B0 3E 93
+R 00 00 00 17
+T 00 03 DC 0C AD FF 97 B1 10 B0 AF 06 0D 71 AB DF
+R 00 00 00 17
+T 00 03 E9 2B 32 A6 68 36 F3 A2 6D 66 B4 BC DA 7B
+R 00 00 00 17
+T 00 03 F6 75 B8 03 5D 36 B5 B4 40 F7 B1
+R 00 00 00 17
+
+
+M:crc32msbtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+
+
+
+
+pn9
+
+;!FILE libmflarge/pn9.asm
+XH3
+H 1A areas 24 global symbols
+M pn9
+O -mmcs51 --model-large
+S _pn9_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2A flags 20 addr 0
+S C$pn9.c$5$1$63 Def000004
+S C$pn9.c$6$1$63 Def000007
+S C$pn9.c$7$1$63 Def000029
+S C$pn9.c$3$0$0 Def000000
+S G$pn9_advance$0$0 Def000000
+S _pn9_advance Def000000
+S A$pn9$110 Def000000
+S A$pn9$120 Def00000C
+S A$pn9$111 Def000002
+S XG$pn9_advance$0$0 Def000029
+S A$pn9$130 Def00001A
+S A$pn9$121 Def00000E
+S A$pn9$131 Def00001C
+S A$pn9$122 Def000010
+S A$pn9$132 Def00001D
+S A$pn9$123 Def000011
+S A$pn9$114 Def000004
+S A$pn9$142 Def000029
+S A$pn9$133 Def00001E
+S A$pn9$124 Def000013
+S A$pn9$134 Def00001F
+S A$pn9$125 Def000015
+S A$pn9$135 Def000020
+S A$pn9$126 Def000016
+S A$pn9$117 Def000007
+S A$pn9$136 Def000022
+S A$pn9$127 Def000017
+S A$pn9$118 Def000009
+S A$pn9$137 Def000023
+S A$pn9$128 Def000018
+S A$pn9$119 Def00000B
+S A$pn9$138 Def000025
+S A$pn9$129 Def000019
+S A$pn9$139 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 53 07 01 8F 04 7D 00 EE 24
+R 00 00 00 16
+T 00 00 0D 00 00 00 F5 82 EF 34 00 00 00 F5 83 E4
+R 00 00 00 16 F1 03 03 00 00 F1 83 0A 00 00
+T 00 00 16 93 FF E4 CF 25 E0 CF 33 FE EF 62 04 EE
+R 00 00 00 16
+T 00 00 23 62 05 8C 82 8D 83 22
+R 00 00 00 16
+
+
+M:pn9
+F:G$pn9_advance$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9.pn9_advance$pn9$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9table
+
+XH3
+H 1A areas 3 global symbols
+M pn9table
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$pn9_table$0$0 Def000000
+S _pn9_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 11 22 33 44 55 66 77 88 99 AA BB CC
+R 00 00 00 17
+T 00 00 0D DD EE FF 10 01 32 23 54 45 76 67 98 89
+R 00 00 00 17
+T 00 00 1A BA AB DC CD FE EF 31 20 13 02 75 64 57
+R 00 00 00 17
+T 00 00 27 46 B9 A8 9B 8A FD EC DF CE 21 30 03 12
+R 00 00 00 17
+T 00 00 34 65 74 47 56 A9 B8 8B 9A ED FC CF DE 62
+R 00 00 00 17
+T 00 00 41 73 40 51 26 37 04 15 EA FB C8 D9 AE BF
+R 00 00 00 17
+T 00 00 4E 8C 9D 72 63 50 41 36 27 14 05 FA EB D8
+R 00 00 00 17
+T 00 00 5B C9 BE AF 9C 8D 53 42 71 60 17 06 35 24
+R 00 00 00 17
+T 00 00 68 DB CA F9 E8 9F 8E BD AC 43 52 61 70 07
+R 00 00 00 17
+T 00 00 75 16 25 34 CB DA E9 F8 8F 9E AD BC C4 D5
+R 00 00 00 17
+T 00 00 82 E6 F7 80 91 A2 B3 4C 5D 6E 7F 08 19 2A
+R 00 00 00 17
+T 00 00 8F 3B D4 C5 F6 E7 90 81 B2 A3 5C 4D 7E 6F
+R 00 00 00 17
+T 00 00 9C 18 09 3A 2B F5 E4 D7 C6 B1 A0 93 82 7D
+R 00 00 00 17
+T 00 00 A9 6C 5F 4E 39 28 1B 0A E5 F4 C7 D6 A1 B0
+R 00 00 00 17
+T 00 00 B6 83 92 6D 7C 4F 5E 29 38 0B 1A A6 B7 84
+R 00 00 00 17
+T 00 00 C3 95 E2 F3 C0 D1 2E 3F 0C 1D 6A 7B 48 59
+R 00 00 00 17
+T 00 00 D0 B6 A7 94 85 F2 E3 D0 C1 3E 2F 1C 0D 7A
+R 00 00 00 17
+T 00 00 DD 6B 58 49 97 86 B5 A4 D3 C2 F1 E0 1F 0E
+R 00 00 00 17
+T 00 00 EA 3D 2C 5B 4A 79 68 87 96 A5 B4 C3 D2 E1
+R 00 00 00 17
+T 00 00 F7 F0 0F 1E 2D 3C 4B 5A 69 78 88 99 AA BB
+R 00 00 00 17
+T 00 01 04 CC DD EE FF 00 11 22 33 44 55 66 77 98
+R 00 00 00 17
+T 00 01 11 89 BA AB DC CD FE EF 10 01 32 23 54 45
+R 00 00 00 17
+T 00 01 1E 76 67 B9 A8 9B 8A FD EC DF CE 31 20 13
+R 00 00 00 17
+T 00 01 2B 02 75 64 57 46 A9 B8 8B 9A ED FC CF DE
+R 00 00 00 17
+T 00 01 38 21 30 03 12 65 74 47 56 EA FB C8 D9 AE
+R 00 00 00 17
+T 00 01 45 BF 8C 9D 62 73 40 51 26 37 04 15 FA EB
+R 00 00 00 17
+T 00 01 52 D8 C9 BE AF 9C 8D 72 63 50 41 36 27 14
+R 00 00 00 17
+T 00 01 5F 05 DB CA F9 E8 9F 8E BD AC 53 42 71 60
+R 00 00 00 17
+T 00 01 6C 17 06 35 24 CB DA E9 F8 8F 9E AD BC 43
+R 00 00 00 17
+T 00 01 79 52 61 70 07 16 25 34 4C 5D 6E 7F 08 19
+R 00 00 00 17
+T 00 01 86 2A 3B C4 D5 E6 F7 80 91 A2 B3 5C 4D 7E
+R 00 00 00 17
+T 00 01 93 6F 18 09 3A 2B D4 C5 F6 E7 90 81 B2 A3
+R 00 00 00 17
+T 00 01 A0 7D 6C 5F 4E 39 28 1B 0A F5 E4 D7 C6 B1
+R 00 00 00 17
+T 00 01 AD A0 93 82 6D 7C 4F 5E 29 38 0B 1A E5 F4
+R 00 00 00 17
+T 00 01 BA C7 D6 A1 B0 83 92 2E 3F 0C 1D 6A 7B 48
+R 00 00 00 17
+T 00 01 C7 59 A6 B7 84 95 E2 F3 C0 D1 3E 2F 1C 0D
+R 00 00 00 17
+T 00 01 D4 7A 6B 58 49 B6 A7 94 85 F2 E3 D0 C1 1F
+R 00 00 00 17
+T 00 01 E1 0E 3D 2C 5B 4A 79 68 97 86 B5 A4 D3 C2
+R 00 00 00 17
+T 00 01 EE F1 E0 0F 1E 2D 3C 4B 5A 69 78 87 96 A5
+R 00 00 00 17
+T 00 01 FB B4 C3 D2 E1 F0
+R 00 00 00 17
+
+
+M:pn9table
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+
+
+
+
+pn9bit
+
+;!FILE libmflarge/pn9bit.asm
+XH3
+H 1A areas 12 global symbols
+M pn9bit
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11 flags 20 addr 0
+S _pn9_advance_bit Def000000
+S C$pn9bit.c$5$0$0 Def000000
+S XG$pn9_advance_bit$0$0 Def000011
+S A$pn9bit$110 Def000009
+S A$pn9bit$112 Def00000A
+S A$pn9bit$113 Def00000C
+S A$pn9bit$114 Def00000D
+S A$pn9bit$105 Def000000
+S A$pn9bit$115 Def00000E
+S A$pn9bit$106 Def000002
+S C$pn9bit.c$20$1$63 Def000000
+S A$pn9bit$116 Def000010
+S A$pn9bit$107 Def000003
+S C$pn9bit.c$21$1$63 Def000011
+S A$pn9bit$108 Def000005
+S A$pn9bit$109 Def000006
+S G$pn9_advance_bit$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 13 E5 82 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A F5 82 E4 33 F5 83 22
+R 00 00 00 16
+
+
+M:pn9bit
+F:G$pn9_advance_bit$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9bit.pn9_advance_bit$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9bits
+
+;!FILE libmflarge/pn9bits.asm
+XH3
+H 1A areas 21 global symbols
+M pn9bits
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 26 flags 20 addr 0
+S C$pn9bits.c$5$0$0 Def000000
+S XG$pn9_advance_bits$0$0 Def000026
+S A$pn9bits$110 Def000006
+S A$pn9bits$120 Def000011
+S A$pn9bits$111 Def000007
+S A$pn9bits$130 Def00001F
+S A$pn9bits$121 Def000013
+S A$pn9bits$112 Def000008
+S A$pn9bits$131 Def000021
+S A$pn9bits$122 Def000014
+S A$pn9bits$113 Def000009
+S A$pn9bits$132 Def000022
+S A$pn9bits$114 Def00000A
+S A$pn9bits$133 Def000023
+S A$pn9bits$124 Def000016
+S A$pn9bits$115 Def00000B
+S A$pn9bits$106 Def000000
+S A$pn9bits$125 Def000017
+S A$pn9bits$116 Def00000D
+S A$pn9bits$107 Def000002
+S A$pn9bits$135 Def000025
+S A$pn9bits$126 Def00001A
+S A$pn9bits$117 Def00000E
+S A$pn9bits$108 Def000004
+S A$pn9bits$118 Def000010
+S A$pn9bits$109 Def000005
+S G$pn9_advance_bits$0$0 Def000000
+S A$pn9bits$128 Def00001B
+S A$pn9bits$129 Def00001D
+S C$pn9bits.c$36$1$63 Def000000
+S C$pn9bits.c$37$1$63 Def000026
+S _pn9_advance_bits Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 FA 08 E6 FB 4A 60 18
+R 00 00 00 16
+T 00 00 0D EA 60 01 0B
+R 00 00 00 16
+T 00 00 11
+R 00 00 00 16
+T 00 00 11 E5 83 13 E5 82
+R 00 00 00 16
+T 00 00 16
+R 00 00 00 16
+T 00 00 16 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 1B
+R 00 00 00 16
+T 00 00 1B DA F9 DB F7 F5 82 E4 33 F5 83
+R 00 00 00 16
+T 00 00 25
+R 00 00 00 16
+T 00 00 25 22
+R 00 00 00 16
+
+
+M:pn9bits
+F:G$pn9_advance_bits$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9bits.pn9_advance_bits$bits$1$62({2}SI:U),B,1,-4
+S:Lpn9bits.pn9_advance_bits$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9byte
+
+;!FILE libmflarge/pn9byte.asm
+XH3
+H 1A areas 27 global symbols
+M pn9byte
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S C$pn9byte.c$5$0$0 Def000000
+S XG$pn9_advance_byte$0$0 Def000034
+S A$pn9byte$110 Def000009
+S A$pn9byte$120 Def000014
+S A$pn9byte$130 Def000022
+S A$pn9byte$121 Def000015
+S A$pn9byte$112 Def00000A
+S A$pn9byte$140 Def00002D
+S A$pn9byte$122 Def000018
+S A$pn9byte$113 Def00000B
+S A$pn9byte$141 Def00002F
+S A$pn9byte$132 Def000023
+S A$pn9byte$114 Def00000E
+S A$pn9byte$105 Def000000
+S A$pn9byte$142 Def000030
+S A$pn9byte$133 Def000024
+S A$pn9byte$124 Def000019
+S A$pn9byte$106 Def000002
+S A$pn9byte$143 Def000031
+S A$pn9byte$134 Def000027
+S A$pn9byte$125 Def00001A
+S A$pn9byte$116 Def00000F
+S A$pn9byte$107 Def000003
+S A$pn9byte$144 Def000033
+S A$pn9byte$126 Def00001D
+S A$pn9byte$117 Def000010
+S A$pn9byte$108 Def000005
+S A$pn9byte$136 Def000028
+S A$pn9byte$118 Def000013
+S A$pn9byte$109 Def000006
+S C$pn9byte.c$41$1$63 Def000000
+S G$pn9_advance_byte$0$0 Def000000
+S A$pn9byte$137 Def000029
+S A$pn9byte$128 Def00001E
+S C$pn9byte.c$42$1$63 Def000034
+S A$pn9byte$138 Def00002C
+S A$pn9byte$129 Def00001F
+S _pn9_advance_byte Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 13 E5 82 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D F5 82 E4 33 F5 83 22
+R 00 00 00 16
+
+
+M:pn9byte
+F:G$pn9_advance_byte$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9byte.pn9_advance_byte$pn9$1$62({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn9buf
+
+;!FILE libmflarge/pn9buf.asm
+XH3
+H 1A areas BF global symbols
+M pn9buf
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 112 flags 20 addr 0
+S A$pn9buf$298 Def0000E8
+S A$pn9buf$289 Def0000DC
+S A$pn9buf$199 Def00006E
+S G$pn9_buffer$0$0 Def000000
+S C$pn9buf.c$5$0$0 Def000000
+S _pn9_buffer Def000000
+S XG$pn9_buffer$0$0 Def000112
+S C$pn9buf.c$203$1$63 Def000000
+S C$pn9buf.c$204$1$63 Def000112
+S A$pn9buf$200 Def00006F
+S A$pn9buf$110 Def000002
+S A$pn9buf$300 Def0000E9
+S A$pn9buf$210 Def00007B
+S A$pn9buf$201 Def000070
+S A$pn9buf$120 Def00000D
+S A$pn9buf$111 Def000004
+S A$pn9buf$310 Def0000F7
+S A$pn9buf$301 Def0000EA
+S A$pn9buf$211 Def00007E
+S A$pn9buf$202 Def000071
+S A$pn9buf$130 Def000019
+S A$pn9buf$121 Def00000E
+S A$pn9buf$112 Def000005
+S A$pn9buf$320 Def000102
+S A$pn9buf$302 Def0000ED
+S A$pn9buf$230 Def000094
+S A$pn9buf$221 Def000089
+S A$pn9buf$203 Def000074
+S A$pn9buf$140 Def000027
+S A$pn9buf$122 Def00000F
+S A$pn9buf$113 Def000006
+S A$pn9buf$330 Def00010F
+S A$pn9buf$321 Def000103
+S A$pn9buf$312 Def0000F8
+S A$pn9buf$231 Def000097
+S A$pn9buf$222 Def00008A
+S A$pn9buf$213 Def00007F
+S A$pn9buf$150 Def000032
+S A$pn9buf$141 Def000028
+S A$pn9buf$132 Def00001A
+S A$pn9buf$123 Def000010
+S A$pn9buf$114 Def000007
+S A$pn9buf$322 Def000106
+S A$pn9buf$313 Def0000F9
+S A$pn9buf$304 Def0000EE
+S A$pn9buf$250 Def0000AB
+S A$pn9buf$241 Def0000A2
+S A$pn9buf$223 Def00008D
+S A$pn9buf$214 Def000080
+S A$pn9buf$205 Def000075
+S A$pn9buf$160 Def000040
+S A$pn9buf$151 Def000033
+S A$pn9buf$142 Def000029
+S A$pn9buf$133 Def00001D
+S A$pn9buf$124 Def000011
+S A$pn9buf$115 Def000008
+S A$pn9buf$314 Def0000FC
+S A$pn9buf$305 Def0000EF
+S A$pn9buf$251 Def0000AE
+S A$pn9buf$242 Def0000A3
+S A$pn9buf$233 Def000098
+S A$pn9buf$215 Def000083
+S A$pn9buf$206 Def000076
+S A$pn9buf$170 Def00004B
+S A$pn9buf$152 Def000036
+S A$pn9buf$143 Def00002A
+S A$pn9buf$134 Def000020
+S A$pn9buf$125 Def000012
+S A$pn9buf$116 Def000009
+S A$pn9buf$324 Def000107
+S A$pn9buf$306 Def0000F2
+S A$pn9buf$270 Def0000C4
+S A$pn9buf$261 Def0000B9
+S A$pn9buf$243 Def0000A4
+S A$pn9buf$234 Def000099
+S A$pn9buf$225 Def00008E
+S A$pn9buf$207 Def000079
+S A$pn9buf$180 Def000057
+S A$pn9buf$171 Def00004C
+S A$pn9buf$162 Def000041
+S A$pn9buf$144 Def00002B
+S A$pn9buf$135 Def000022
+S A$pn9buf$126 Def000013
+S A$pn9buf$117 Def00000A
+S A$pn9buf$325 Def000108
+S A$pn9buf$316 Def0000FD
+S A$pn9buf$271 Def0000C7
+S A$pn9buf$262 Def0000BA
+S A$pn9buf$253 Def0000AF
+S A$pn9buf$244 Def0000A5
+S A$pn9buf$235 Def00009A
+S A$pn9buf$226 Def00008F
+S A$pn9buf$217 Def000084
+S A$pn9buf$181 Def000058
+S A$pn9buf$172 Def00004F
+S A$pn9buf$163 Def000042
+S A$pn9buf$154 Def000037
+S A$pn9buf$145 Def00002C
+S A$pn9buf$127 Def000014
+S A$pn9buf$118 Def00000B
+S A$pn9buf$109 Def000000
+S A$pn9buf$326 Def000109
+S A$pn9buf$317 Def0000FE
+S A$pn9buf$308 Def0000F3
+S A$pn9buf$290 Def0000DD
+S A$pn9buf$281 Def0000D2
+S A$pn9buf$263 Def0000BD
+S A$pn9buf$254 Def0000B0
+S A$pn9buf$245 Def0000A6
+S A$pn9buf$236 Def00009B
+S A$pn9buf$227 Def000092
+S A$pn9buf$218 Def000085
+S A$pn9buf$209 Def00007A
+S A$pn9buf$191 Def000065
+S A$pn9buf$182 Def000059
+S A$pn9buf$164 Def000045
+S A$pn9buf$155 Def000038
+S A$pn9buf$146 Def00002D
+S A$pn9buf$128 Def000016
+S A$pn9buf$119 Def00000C
+S A$pn9buf$327 Def00010A
+S A$pn9buf$318 Def000101
+S A$pn9buf$309 Def0000F4
+S A$pn9buf$291 Def0000DE
+S A$pn9buf$282 Def0000D3
+S A$pn9buf$273 Def0000C8
+S A$pn9buf$255 Def0000B3
+S A$pn9buf$246 Def0000A7
+S A$pn9buf$237 Def00009C
+S A$pn9buf$219 Def000088
+S A$pn9buf$183 Def00005B
+S A$pn9buf$174 Def000050
+S A$pn9buf$156 Def00003B
+S A$pn9buf$147 Def00002E
+S A$pn9buf$138 Def000025
+S A$pn9buf$129 Def000017
+S A$pn9buf$328 Def00010B
+S A$pn9buf$292 Def0000DF
+S A$pn9buf$283 Def0000D4
+S A$pn9buf$274 Def0000C9
+S A$pn9buf$265 Def0000BE
+S A$pn9buf$247 Def0000A8
+S A$pn9buf$238 Def00009E
+S A$pn9buf$229 Def000093
+S A$pn9buf$193 Def000068
+S A$pn9buf$175 Def000051
+S A$pn9buf$166 Def000046
+S A$pn9buf$148 Def000031
+S A$pn9buf$139 Def000026
+S A$pn9buf$329 Def00010D
+S A$pn9buf$293 Def0000E0
+S A$pn9buf$284 Def0000D5
+S A$pn9buf$275 Def0000CC
+S A$pn9buf$266 Def0000BF
+S A$pn9buf$257 Def0000B4
+S A$pn9buf$248 Def0000A9
+S A$pn9buf$239 Def0000A0
+S A$pn9buf$194 Def000069
+S A$pn9buf$185 Def00005D
+S A$pn9buf$176 Def000054
+S A$pn9buf$167 Def000047
+S A$pn9buf$158 Def00003C
+S A$pn9buf$294 Def0000E3
+S A$pn9buf$285 Def0000D6
+S A$pn9buf$267 Def0000C2
+S A$pn9buf$258 Def0000B5
+S A$pn9buf$249 Def0000AA
+S A$pn9buf$195 Def00006A
+S A$pn9buf$186 Def00005F
+S A$pn9buf$168 Def00004A
+S A$pn9buf$159 Def00003D
+S A$pn9buf$286 Def0000D8
+S A$pn9buf$277 Def0000CD
+S A$pn9buf$259 Def0000B8
+S A$pn9buf$196 Def00006B
+S A$pn9buf$187 Def000061
+S A$pn9buf$178 Def000055
+S A$pn9buf$296 Def0000E4
+S A$pn9buf$287 Def0000DA
+S A$pn9buf$278 Def0000CE
+S A$pn9buf$269 Def0000C3
+S A$pn9buf$197 Def00006C
+S A$pn9buf$179 Def000056
+S A$pn9buf$297 Def0000E5
+S A$pn9buf$279 Def0000D1
+S A$pn9buf$198 Def00006D
+S A$pn9buf$189 Def000062
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FA F8 E6 FF 08 E6 FC 08 E6 FD
+R 00 00 00 16
+T 00 00 0D 08 E6 FA 08 E6 FB 4A 60 47 EA 60 01 0B
+R 00 00 00 16
+T 00 00 1A
+R 00 00 00 16
+T 00 00 1A 20 00 00 00 45 30 00 00 00 45 A8 82 20
+R 00 00 00 16 F1 23 04 00 03 F1 23 09 00 02
+T 00 00 23 00 00 00 43
+R 00 00 00 16 F1 23 03 00 01
+T 00 00 25
+R 00 00 00 16
+T 00 00 25 E6 6C 6F F6 08 ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 41
+R 00 00 00 16
+T 00 00 41 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 46
+R 00 00 00 16
+T 00 00 46 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 4B
+R 00 00 00 16
+T 00 00 4B 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 50
+R 00 00 00 16
+T 00 00 50 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 FC E4 33 FD DA CA DB C8
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D 8C 82 8D 83 22
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 02 00 DC
+R 00 00 00 16 00 04 00 16
+T 00 00 65
+R 00 00 00 16
+T 00 00 65 02 00 A2
+R 00 00 00 16 00 04 00 16
+T 00 00 68
+R 00 00 00 16
+T 00 00 68 E2 6C 6F F2 08 ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 7A
+R 00 00 00 16
+T 00 00 7A 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 7F
+R 00 00 00 16
+T 00 00 7F 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 8E
+R 00 00 00 16
+T 00 00 8E 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 93
+R 00 00 00 16
+T 00 00 93 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 98
+R 00 00 00 16
+T 00 00 98 FC E4 33 FD DA CA DB C8 80 BB
+R 00 00 00 16
+T 00 00 A2
+R 00 00 00 16
+T 00 00 A2 E0 6C 6F F0 A3 ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 AF
+R 00 00 00 16
+T 00 00 AF 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 B9
+R 00 00 00 16
+T 00 00 B9 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 BE
+R 00 00 00 16
+T 00 00 BE 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 C3
+R 00 00 00 16
+T 00 00 C3 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 C8
+R 00 00 00 16
+T 00 00 C8 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 CD
+R 00 00 00 16
+T 00 00 CD 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 D2
+R 00 00 00 16
+T 00 00 D2 FC E4 33 FD DA CA DB C8 80 81
+R 00 00 00 16
+T 00 00 DC
+R 00 00 00 16
+T 00 00 DC ED 13 EC 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 E4
+R 00 00 00 16
+T 00 00 E4 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 E9
+R 00 00 00 16
+T 00 00 E9 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 EE
+R 00 00 00 16
+T 00 00 EE 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 F3
+R 00 00 00 16
+T 00 00 F3 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 F8
+R 00 00 00 16
+T 00 00 F8 13 30 E4 01 B3
+R 00 00 00 16
+T 00 00 FD
+R 00 00 00 16
+T 00 00 FD 13 30 E4 01 B3
+R 00 00 00 16
+T 00 01 02
+R 00 00 00 16
+T 00 01 02 13 30 E4 01 B3
+R 00 00 00 16
+T 00 01 07
+R 00 00 00 16
+T 00 01 07 FC E4 33 FD DA CF DB CD 02 00 5D
+R 00 00 00 16 00 0C 00 16
+
+
+M:pn9buf
+F:G$pn9_buffer$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn9buf.pn9_buffer$buflen$1$62({2}SI:U),B,1,-4
+S:Lpn9buf.pn9_buffer$pn9$1$62({2}SI:U),B,1,-6
+S:Lpn9buf.pn9_buffer$xor$1$62({1}SC:U),B,1,-7
+S:Lpn9buf.pn9_buffer$buf$1$62({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15advtable
+
+XH3
+H 1A areas 3 global symbols
+M pn15advtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 200 flags 20 addr 0
+S G$pn15_adv_table$0$0 Def000000
+S _pn15_adv_table Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 00 81 7F 01 7F 80 00 01 7E 80 01 00
+R 00 00 00 17
+T 00 00 0D 01 81 7E 01 7C 80 03 00 03 81 7C 00 02
+R 00 00 00 17
+T 00 00 1A 81 7D 01 7D 80 02 01 78 80 07 00 07 81
+R 00 00 00 17
+T 00 00 27 78 00 06 81 79 01 79 80 06 00 04 81 7B
+R 00 00 00 17
+T 00 00 34 01 7B 80 04 01 7A 80 05 00 05 81 7A 01
+R 00 00 00 17
+T 00 00 41 70 80 0F 00 0F 81 70 00 0E 81 71 01 71
+R 00 00 00 17
+T 00 00 4E 80 0E 00 0C 81 73 01 73 80 0C 01 72 80
+R 00 00 00 17
+T 00 00 5B 0D 00 0D 81 72 00 08 81 77 01 77 80 08
+R 00 00 00 17
+T 00 00 68 01 76 80 09 00 09 81 76 01 74 80 0B 00
+R 00 00 00 17
+T 00 00 75 0B 81 74 00 0A 81 75 01 75 80 0A 01 60
+R 00 00 00 17
+T 00 00 82 80 1F 00 1F 81 60 00 1E 81 61 01 61 80
+R 00 00 00 17
+T 00 00 8F 1E 00 1C 81 63 01 63 80 1C 01 62 80 1D
+R 00 00 00 17
+T 00 00 9C 00 1D 81 62 00 18 81 67 01 67 80 18 01
+R 00 00 00 17
+T 00 00 A9 66 80 19 00 19 81 66 01 64 80 1B 00 1B
+R 00 00 00 17
+T 00 00 B6 81 64 00 1A 81 65 01 65 80 1A 00 10 81
+R 00 00 00 17
+T 00 00 C3 6F 01 6F 80 10 01 6E 80 11 00 11 81 6E
+R 00 00 00 17
+T 00 00 D0 01 6C 80 13 00 13 81 6C 00 12 81 6D 01
+R 00 00 00 17
+T 00 00 DD 6D 80 12 01 68 80 17 00 17 81 68 00 16
+R 00 00 00 17
+T 00 00 EA 81 69 01 69 80 16 00 14 81 6B 01 6B 80
+R 00 00 00 17
+T 00 00 F7 14 01 6A 80 15 00 15 81 6A 01 40 80 3F
+R 00 00 00 17
+T 00 01 04 00 3F 81 40 00 3E 81 41 01 41 80 3E 00
+R 00 00 00 17
+T 00 01 11 3C 81 43 01 43 80 3C 01 42 80 3D 00 3D
+R 00 00 00 17
+T 00 01 1E 81 42 00 38 81 47 01 47 80 38 01 46 80
+R 00 00 00 17
+T 00 01 2B 39 00 39 81 46 01 44 80 3B 00 3B 81 44
+R 00 00 00 17
+T 00 01 38 00 3A 81 45 01 45 80 3A 00 30 81 4F 01
+R 00 00 00 17
+T 00 01 45 4F 80 30 01 4E 80 31 00 31 81 4E 01 4C
+R 00 00 00 17
+T 00 01 52 80 33 00 33 81 4C 00 32 81 4D 01 4D 80
+R 00 00 00 17
+T 00 01 5F 32 01 48 80 37 00 37 81 48 00 36 81 49
+R 00 00 00 17
+T 00 01 6C 01 49 80 36 00 34 81 4B 01 4B 80 34 01
+R 00 00 00 17
+T 00 01 79 4A 80 35 00 35 81 4A 00 20 81 5F 01 5F
+R 00 00 00 17
+T 00 01 86 80 20 01 5E 80 21 00 21 81 5E 01 5C 80
+R 00 00 00 17
+T 00 01 93 23 00 23 81 5C 00 22 81 5D 01 5D 80 22
+R 00 00 00 17
+T 00 01 A0 01 58 80 27 00 27 81 58 00 26 81 59 01
+R 00 00 00 17
+T 00 01 AD 59 80 26 00 24 81 5B 01 5B 80 24 01 5A
+R 00 00 00 17
+T 00 01 BA 80 25 00 25 81 5A 01 50 80 2F 00 2F 81
+R 00 00 00 17
+T 00 01 C7 50 00 2E 81 51 01 51 80 2E 00 2C 81 53
+R 00 00 00 17
+T 00 01 D4 01 53 80 2C 01 52 80 2D 00 2D 81 52 00
+R 00 00 00 17
+T 00 01 E1 28 81 57 01 57 80 28 01 56 80 29 00 29
+R 00 00 00 17
+T 00 01 EE 81 56 01 54 80 2B 00 2B 81 54 00 2A 81
+R 00 00 00 17
+T 00 01 FB 55 01 55 80 2A
+R 00 00 00 17
+
+
+M:pn15advtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+
+
+
+
+pn15outtable
+
+XH3
+H 1A areas 3 global symbols
+M pn15outtable
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 100 flags 20 addr 0
+S _pn15_out_table Def000000
+S G$pn15_out_table$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 00 FF FE 01 FC 03 02 FD F8 07 06 F9 04
+R 00 00 00 17
+T 00 00 0D FB FA 05 F0 0F 0E F1 0C F3 F2 0D 08 F7
+R 00 00 00 17
+T 00 00 1A F6 09 F4 0B 0A F5 E0 1F 1E E1 1C E3 E2
+R 00 00 00 17
+T 00 00 27 1D 18 E7 E6 19 E4 1B 1A E5 10 EF EE 11
+R 00 00 00 17
+T 00 00 34 EC 13 12 ED E8 17 16 E9 14 EB EA 15 C0
+R 00 00 00 17
+T 00 00 41 3F 3E C1 3C C3 C2 3D 38 C7 C6 39 C4 3B
+R 00 00 00 17
+T 00 00 4E 3A C5 30 CF CE 31 CC 33 32 CD C8 37 36
+R 00 00 00 17
+T 00 00 5B C9 34 CB CA 35 20 DF DE 21 DC 23 22 DD
+R 00 00 00 17
+T 00 00 68 D8 27 26 D9 24 DB DA 25 D0 2F 2E D1 2C
+R 00 00 00 17
+T 00 00 75 D3 D2 2D 28 D7 D6 29 D4 2B 2A D5 80 7F
+R 00 00 00 17
+T 00 00 82 7E 81 7C 83 82 7D 78 87 86 79 84 7B 7A
+R 00 00 00 17
+T 00 00 8F 85 70 8F 8E 71 8C 73 72 8D 88 77 76 89
+R 00 00 00 17
+T 00 00 9C 74 8B 8A 75 60 9F 9E 61 9C 63 62 9D 98
+R 00 00 00 17
+T 00 00 A9 67 66 99 64 9B 9A 65 90 6F 6E 91 6C 93
+R 00 00 00 17
+T 00 00 B6 92 6D 68 97 96 69 94 6B 6A 95 40 BF BE
+R 00 00 00 17
+T 00 00 C3 41 BC 43 42 BD B8 47 46 B9 44 BB BA 45
+R 00 00 00 17
+T 00 00 D0 B0 4F 4E B1 4C B3 B2 4D 48 B7 B6 49 B4
+R 00 00 00 17
+T 00 00 DD 4B 4A B5 A0 5F 5E A1 5C A3 A2 5D 58 A7
+R 00 00 00 17
+T 00 00 EA A6 59 A4 5B 5A A5 50 AF AE 51 AC 53 52
+R 00 00 00 17
+T 00 00 F7 AD A8 57 56 A9 54 AB AA 55
+R 00 00 00 17
+
+
+M:pn15outtable
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15adv
+
+;!FILE libmflarge/pn15adv.asm
+XH3
+H 1A areas 28 global symbols
+M pn15adv
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S _pn15_adv_table Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2D flags 20 addr 0
+S G$pn15_advance$0$0 Def000000
+S _pn15_advance Def000000
+S A$pn15adv$110 Def000000
+S A$pn15adv$120 Def00000B
+S A$pn15adv$111 Def000002
+S A$pn15adv$130 Def000019
+S A$pn15adv$121 Def00000C
+S A$pn15adv$140 Def000025
+S A$pn15adv$131 Def00001B
+S A$pn15adv$122 Def00000E
+S A$pn15adv$141 Def000026
+S A$pn15adv$132 Def00001C
+S A$pn15adv$123 Def00000F
+S A$pn15adv$114 Def000004
+S A$pn15adv$142 Def000028
+S A$pn15adv$133 Def00001D
+S A$pn15adv$124 Def000010
+S A$pn15adv$143 Def00002A
+S A$pn15adv$134 Def00001E
+S A$pn15adv$125 Def000011
+S XG$pn15_advance$0$0 Def00002C
+S A$pn15adv$135 Def00001F
+S A$pn15adv$126 Def000012
+S A$pn15adv$117 Def000007
+S A$pn15adv$136 Def000020
+S A$pn15adv$127 Def000014
+S A$pn15adv$118 Def000009
+S A$pn15adv$146 Def00002C
+S A$pn15adv$137 Def000021
+S A$pn15adv$128 Def000016
+S A$pn15adv$119 Def00000A
+S A$pn15adv$138 Def000022
+S A$pn15adv$129 Def000017
+S A$pn15adv$139 Def000023
+S C$pn15adv.c$5$1$63 Def000004
+S C$pn15adv.c$6$1$63 Def000007
+S C$pn15adv.c$7$1$63 Def00002C
+S C$pn15adv.c$3$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 53 07 7F 8F 04 E4 FD CE 25
+R 00 00 00 16
+T 00 00 0D E0 CE 33 FF EE 24 00 00 00 F5 82 EF 34
+R 00 00 00 16 F1 03 09 00 01
+T 00 00 18 00 00 00 F5 83 E4 93 FE A3 E4 93 FF EE
+R 00 00 00 16 F1 83 03 00 01
+T 00 00 23 62 04 EF 62 05 8C 82 8D 83 22
+R 00 00 00 16
+
+
+M:pn15adv
+F:G$pn15_advance$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lpn15adv.pn15_advance$pn15$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+pn15out
+
+;!FILE libmflarge/pn15out.asm
+XH3
+H 1A areas 14 global symbols
+M pn15out
+O -mmcs51 --model-large
+S _pn15_out_table Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13 flags 20 addr 0
+S A$pn15out$119 Def00000C
+S C$pn15out.c$5$1$63 Def000002
+S C$pn15out.c$6$1$63 Def000010
+S C$pn15out.c$3$0$0 Def000000
+S G$pn15_output$0$0 Def000000
+S _pn15_output Def000000
+S A$pn15out$110 Def000000
+S A$pn15out$120 Def00000E
+S A$pn15out$121 Def00000F
+S A$pn15out$113 Def000002
+S A$pn15out$114 Def000004
+S A$pn15out$124 Def000010
+S A$pn15out$115 Def000005
+S A$pn15out$125 Def000012
+S A$pn15out$116 Def000007
+S A$pn15out$117 Def000009
+S A$pn15out$118 Def00000A
+S XG$pn15_output$0$0 Def000010
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 7F 00 EE 24 00 00 00 F5 82 EF 34
+R 00 00 00 16 F1 03 09 00 00
+T 00 00 0B 00 00 00 F5 83 E4 93 F5 82 22
+R 00 00 00 16 F1 83 03 00 00
+
+
+M:pn15out
+F:G$pn15_output$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lpn15out.pn15_output$pn15$1$62({2}SI:U),R,0,0,[r6,r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+
+
+
+
+rev8
+
+;!FILE libmflarge/rev8.asm
+XH3
+H 1A areas 2A global symbols
+M rev8
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2E flags 20 addr 0
+S G$rev8$0$0 Def000000
+S A$rev8$120 Def00000C
+S A$rev8$130 Def000018
+S A$rev8$121 Def00000E
+S A$rev8$112 Def000000
+S A$rev8$140 Def000022
+S A$rev8$131 Def000019
+S A$rev8$113 Def000002
+S A$rev8$150 Def00002B
+S A$rev8$141 Def000023
+S A$rev8$132 Def00001A
+S A$rev8$114 Def000003
+S _rev8 Def000000
+S A$rev8$151 Def00002D
+S A$rev8$142 Def000026
+S A$rev8$133 Def00001C
+S A$rev8$124 Def00000F
+S A$rev8$115 Def000004
+S A$rev8$143 Def000027
+S A$rev8$134 Def00001E
+S A$rev8$125 Def000010
+S A$rev8$116 Def000006
+S A$rev8$144 Def000028
+S A$rev8$126 Def000011
+S A$rev8$117 Def000007
+S A$rev8$145 Def00002A
+S A$rev8$127 Def000012
+S A$rev8$118 Def00000A
+S A$rev8$137 Def00001F
+S A$rev8$128 Def000014
+S A$rev8$119 Def00000B
+S A$rev8$138 Def000020
+S A$rev8$129 Def000015
+S A$rev8$139 Def000021
+S XG$rev8$0$0 Def00002B
+S C$rev8.c$5$1$28 Def000000
+S C$rev8.c$6$1$28 Def00000F
+S C$rev8.c$7$1$28 Def00001F
+S C$rev8.c$8$1$28 Def00002B
+S C$rev8.c$3$0$0 Def000000
+S C$rev8.c$9$1$28 Def00002B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF C4 54 0F FE 53 06 0F EF C4 54
+R 00 00 00 16
+T 00 00 0D F0 4E FF 03 03 54 3F FE 53 06 33 EF 2F
+R 00 00 00 16
+T 00 00 1A 25 E0 54 CC 4E FF C3 13 FE 53 06 55 EF
+R 00 00 00 16
+T 00 00 27 2F 54 AA 4E F5 82 22
+R 00 00 00 16
+
+
+M:rev8
+F:G$rev8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lrev8.rev8$x$1$27({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight8
+
+;!FILE libmflarge/hweight8.asm
+XH3
+H 1A areas 1C global symbols
+M hweight8
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$hweight8$110 Def000007
+S A$hweight8$120 Def000019
+S A$hweight8$111 Def000009
+S A$hweight8$121 Def00001B
+S A$hweight8$112 Def00000B
+S A$hweight8$122 Def00001D
+S A$hweight8$113 Def00000D
+S A$hweight8$123 Def00001E
+S A$hweight8$114 Def00000F
+S _hweight8 Def000000
+S A$hweight8$124 Def000020
+S A$hweight8$115 Def000011
+S A$hweight8$106 Def000000
+S A$hweight8$125 Def000022
+S A$hweight8$116 Def000012
+S A$hweight8$107 Def000002
+S A$hweight8$126 Def000024
+S A$hweight8$117 Def000013
+S A$hweight8$108 Def000004
+S C$hweight8.c$30$1$28 Def000000
+S A$hweight8$118 Def000015
+S A$hweight8$109 Def000006
+S C$hweight8.c$31$1$28 Def000025
+S A$hweight8$119 Def000017
+S XG$hweight8$0$0 Def000025
+S C$hweight8.c$5$0$0 Def000000
+S G$hweight8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 54 55 C5 82 03 54 55 25 82 F5 82
+R 00 00 00 16
+T 00 00 0D 54 33 C5 82 03 03 54 33 25 82 F5 82 54
+R 00 00 00 16
+T 00 00 1A 0F C5 82 C4 54 0F 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight8
+F:G$hweight8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight8.hweight8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight16
+
+;!FILE libmflarge/hweight16.asm
+XH3
+H 1A areas 11 global symbols
+M hweight16
+O -mmcs51 --model-large
+S _hweight8 Ref000000
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13 flags 20 addr 0
+S C$hweight16.c$19$1$28 Def000013
+S XG$hweight16$0$0 Def000013
+S C$hweight16.c$5$0$0 Def000000
+S G$hweight16$0$0 Def000000
+S A$hweight16$110 Def000009
+S A$hweight16$111 Def00000C
+S A$hweight16$112 Def00000E
+S A$hweight16$113 Def000010
+S A$hweight16$114 Def000012
+S _hweight16 Def000000
+S A$hweight16$106 Def000000
+S A$hweight16$107 Def000003
+S A$hweight16$108 Def000005
+S A$hweight16$109 Def000007
+S C$hweight16.c$18$1$28 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 12 00 00 E5 82 C5 83 F5 82 12 00 00 E5
+R 00 00 00 16 02 04 00 00 02 0D 00 00
+T 00 00 0D 83 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight16
+F:G$hweight16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight16.hweight16$x$1$27({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+hweight32
+
+;!FILE libmflarge/hweight32.asm
+XH3
+H 1A areas 17 global symbols
+M hweight32
+O -mmcs51 --model-large
+S _hweight8 Ref000000
+S .__.ABS. Def000000
+S _hweight16 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1F flags 20 addr 0
+S XG$hweight32$0$0 Def00001F
+S C$hweight32.c$5$0$0 Def000000
+S G$hweight32$0$0 Def000000
+S A$hweight32$110 Def000009
+S A$hweight32$111 Def00000C
+S A$hweight32$112 Def00000E
+S A$hweight32$113 Def000010
+S A$hweight32$114 Def000012
+S _hweight32 Def000000
+S A$hweight32$115 Def000015
+S A$hweight32$106 Def000000
+S A$hweight32$116 Def000018
+S A$hweight32$107 Def000002
+S A$hweight32$117 Def00001A
+S A$hweight32$108 Def000005
+S A$hweight32$118 Def00001C
+S A$hweight32$109 Def000007
+S A$hweight32$119 Def00001E
+S C$hweight32.c$23$1$28 Def000000
+S C$hweight32.c$24$1$28 Def00001F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 E0 12 00 00 F5 83 D0 82 12 00 00 E5
+R 00 00 00 16 02 06 00 02 02 0D 00 00
+T 00 00 0D 83 25 82 F5 83 85 F0 82 12 00 00 E5 83
+R 00 00 00 16 02 0C 00 00
+T 00 00 1A 25 82 F5 82 22
+R 00 00 00 16
+
+
+M:hweight32
+F:G$hweight32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lhweight32.hweight32$x$1$27({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext12
+
+;!FILE libmflarge/signext12.asm
+XH3
+H 1A areas 13 global symbols
+M signext12
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 14 flags 20 addr 0
+S A$signext12$110 Def000008
+S A$signext12$111 Def000009
+S A$signext12$112 Def00000A
+S A$signext12$113 Def00000C
+S A$signext12$114 Def00000E
+S A$signext12$115 Def00000F
+S A$signext12$106 Def000000
+S A$signext12$116 Def000011
+S A$signext12$107 Def000002
+S A$signext12$117 Def000013
+S A$signext12$108 Def000004
+S XG$signextend12$0$0 Def000014
+S C$signext12.c$21$1$28 Def000000
+S A$signext12$109 Def000006
+S C$signext12.c$22$1$28 Def000014
+S C$signext12.c$5$0$0 Def000000
+S G$signextend12$0$0 Def000000
+S _signextend12 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F F5 83 54 08 F4 04 45 83 F5
+R 00 00 00 16
+T 00 00 0D 83 33 95 E0 F5 F0 22
+R 00 00 00 16
+
+
+M:signext12
+F:G$signextend12$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext12.signextend12$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext16
+
+;!FILE libmflarge/signext16.asm
+XH3
+H 1A areas C global symbols
+M signext16
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 8 flags 20 addr 0
+S A$signext16$110 Def000007
+S A$signext16$106 Def000000
+S A$signext16$107 Def000002
+S A$signext16$108 Def000003
+S XG$signextend16$0$0 Def000008
+S A$signext16$109 Def000005
+S C$signext16.c$14$1$28 Def000000
+S C$signext16.c$15$1$28 Def000008
+S C$signext16.c$5$0$0 Def000000
+S G$signextend16$0$0 Def000000
+S _signextend16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 33 95 E0 F5 F0 22
+R 00 00 00 16
+
+
+M:signext16
+F:G$signextend16$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext16.signextend16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext20
+
+;!FILE libmflarge/signext20.asm
+XH3
+H 1A areas 12 global symbols
+M signext20
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 12 flags 20 addr 0
+S A$signext20$111 Def000009
+S A$signext20$112 Def00000A
+S A$signext20$113 Def00000C
+S A$signext20$114 Def00000E
+S A$signext20$115 Def00000F
+S A$signext20$106 Def000000
+S A$signext20$116 Def000011
+S A$signext20$107 Def000002
+S C$signext20.c$20$1$28 Def000000
+S A$signext20$108 Def000004
+S XG$signextend20$0$0 Def000012
+S C$signext20.c$21$1$28 Def000012
+S A$signext20$109 Def000006
+S C$signext20.c$5$0$0 Def000000
+S G$signextend20$0$0 Def000000
+S _signextend20 Def000000
+S A$signext20$110 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 F0 54 0F F5 F0 54 08 F4 04 45 F0 F5
+R 00 00 00 16
+T 00 00 0D F0 33 95 E0 22
+R 00 00 00 16
+
+
+M:signext20
+F:G$signextend20$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext20.signextend20$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+signext24
+
+;!FILE libmflarge/signext24.asm
+XH3
+H 1A areas B global symbols
+M signext24
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 6 flags 20 addr 0
+S A$signext24$106 Def000000
+S A$signext24$107 Def000002
+S A$signext24$108 Def000003
+S XG$signextend24$0$0 Def000006
+S A$signext24$109 Def000005
+S C$signext24.c$13$1$28 Def000000
+S C$signext24.c$14$1$28 Def000006
+S C$signext24.c$5$0$0 Def000000
+S G$signextend24$0$0 Def000000
+S _signextend24 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 F0 33 95 E0 22
+R 00 00 00 16
+
+
+M:signext24
+F:G$signextend24$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsignext24.signextend24$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+chksgnlim16
+
+;!FILE libmflarge/chksgnlim16.asm
+XH3
+H 1A areas 20 global symbols
+M chksgnlim16
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S A$chksgnlim16$120 Def00000C
+S A$chksgnlim16$130 Def00001A
+S A$chksgnlim16$121 Def00000E
+S A$chksgnlim16$140 Def000026
+S A$chksgnlim16$131 Def00001B
+S A$chksgnlim16$122 Def00000F
+S A$chksgnlim16$132 Def00001C
+S A$chksgnlim16$123 Def000010
+S A$chksgnlim16$114 Def000000
+S A$chksgnlim16$133 Def00001E
+S A$chksgnlim16$124 Def000012
+S A$chksgnlim16$115 Def000002
+S A$chksgnlim16$125 Def000013
+S A$chksgnlim16$116 Def000004
+S A$chksgnlim16$135 Def00001F
+S A$chksgnlim16$126 Def000015
+S A$chksgnlim16$117 Def000006
+S A$chksgnlim16$136 Def000020
+S A$chksgnlim16$118 Def000007
+S A$chksgnlim16$137 Def000021
+S A$chksgnlim16$128 Def000017
+S A$chksgnlim16$119 Def000009
+S A$chksgnlim16$138 Def000022
+S A$chksgnlim16$129 Def000018
+S C$chksgnlim16.c$42$1$28 Def000000
+S A$chksgnlim16$139 Def000024
+S C$chksgnlim16.c$43$1$28 Def000027
+S G$checksignedlimit16$0$0 Def000000
+S _checksignedlimit16 Def000000
+S C$chksgnlim16.c$5$0$0 Def000000
+S XG$checksignedlimit16$0$0 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 E5 81 24 FC F8 E5 83 30 E7 0B E5
+R 00 00 00 16
+T 00 00 0D 82 26 08 E5 83 36 64 80 80 08
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 D3 E5 82 96 08 E5 83 96
+R 00 00 00 16
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F 33 E4 33 F5 82 D0 00 22
+R 00 00 00 16
+
+
+M:chksgnlim16
+F:G$checksignedlimit16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lchksgnlim16.checksignedlimit16$lim$1$27({2}SI:S),B,1,-4
+S:Lchksgnlim16.checksignedlimit16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sgnlim16
+
+;!FILE libmflarge/sgnlim16.asm
+XH3
+H 1A areas 2B global symbols
+M sgnlim16
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 37 flags 20 addr 0
+S A$sgnlim16$120 Def00000C
+S A$sgnlim16$130 Def00001A
+S A$sgnlim16$121 Def00000E
+S A$sgnlim16$140 Def000026
+S A$sgnlim16$131 Def00001B
+S A$sgnlim16$122 Def00000F
+S A$sgnlim16$141 Def000028
+S A$sgnlim16$132 Def00001D
+S A$sgnlim16$123 Def000010
+S A$sgnlim16$114 Def000000
+S A$sgnlim16$151 Def000034
+S A$sgnlim16$142 Def000029
+S A$sgnlim16$133 Def00001E
+S A$sgnlim16$124 Def000012
+S A$sgnlim16$115 Def000002
+S A$sgnlim16$152 Def000036
+S A$sgnlim16$143 Def00002C
+S A$sgnlim16$134 Def00001F
+S A$sgnlim16$125 Def000013
+S A$sgnlim16$116 Def000004
+S A$sgnlim16$144 Def00002D
+S A$sgnlim16$126 Def000016
+S A$sgnlim16$117 Def000006
+S G$signedlimit16$0$0 Def000000
+S A$sgnlim16$145 Def00002E
+S A$sgnlim16$136 Def000021
+S A$sgnlim16$127 Def000017
+S A$sgnlim16$118 Def000007
+S A$sgnlim16$146 Def00002F
+S A$sgnlim16$137 Def000022
+S A$sgnlim16$128 Def000018
+S A$sgnlim16$119 Def000009
+S A$sgnlim16$147 Def000031
+S A$sgnlim16$138 Def000024
+S A$sgnlim16$129 Def000019
+S A$sgnlim16$139 Def000025
+S A$sgnlim16$149 Def000032
+S C$sgnlim16.c$53$1$28 Def000000
+S C$sgnlim16.c$54$1$28 Def000037
+S _signedlimit16 Def000000
+S C$sgnlim16.c$5$0$0 Def000000
+S XG$signedlimit16$0$0 Def000037
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 E5 81 24 FC F8 E5 83 30 E7 15 E5
+R 00 00 00 16
+T 00 00 0D 82 26 08 E5 83 36 30 E7 1E 18 C3 E4 96
+R 00 00 00 16
+T 00 00 1A 08 F5 82 E4 96 80 11
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 D3 E5 82 96 08 E5 83 96 20 E7 08 18 E6
+R 00 00 00 16
+T 00 00 2E 08 F5 82 E6
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 F5 83
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 D0 00 22
+R 00 00 00 16
+
+
+M:sgnlim16
+F:G$signedlimit16$0$0({2}DF,SI:S),Z,0,0,0,0,0
+S:Lsgnlim16.signedlimit16$lim$1$27({2}SI:S),B,1,-4
+S:Lsgnlim16.signedlimit16$x$1$27({2}SI:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+chksgnlim32
+
+;!FILE libmflarge/chksgnlim32.asm
+XH3
+H 1A areas 2F global symbols
+M chksgnlim32
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 39 flags 20 addr 0
+S A$chksgnlim32$120 Def00000A
+S A$chksgnlim32$130 Def000019
+S A$chksgnlim32$121 Def00000B
+S A$chksgnlim32$140 Def000025
+S A$chksgnlim32$131 Def00001A
+S A$chksgnlim32$122 Def00000E
+S A$chksgnlim32$150 Def000030
+S A$chksgnlim32$141 Def000027
+S A$chksgnlim32$132 Def00001B
+S A$chksgnlim32$123 Def000010
+S A$chksgnlim32$114 Def000000
+S A$chksgnlim32$151 Def000031
+S A$chksgnlim32$142 Def000028
+S A$chksgnlim32$133 Def00001C
+S A$chksgnlim32$124 Def000011
+S A$chksgnlim32$115 Def000002
+S A$chksgnlim32$152 Def000032
+S A$chksgnlim32$143 Def000029
+S A$chksgnlim32$134 Def00001E
+S A$chksgnlim32$125 Def000012
+S A$chksgnlim32$116 Def000004
+S A$chksgnlim32$153 Def000034
+S A$chksgnlim32$144 Def00002B
+S A$chksgnlim32$126 Def000014
+S A$chksgnlim32$117 Def000005
+S A$chksgnlim32$154 Def000036
+S A$chksgnlim32$145 Def00002C
+S A$chksgnlim32$136 Def000020
+S A$chksgnlim32$127 Def000015
+S A$chksgnlim32$118 Def000007
+S A$chksgnlim32$155 Def000038
+S A$chksgnlim32$146 Def00002D
+S A$chksgnlim32$137 Def000021
+S A$chksgnlim32$128 Def000016
+S A$chksgnlim32$119 Def000009
+S A$chksgnlim32$147 Def00002E
+S A$chksgnlim32$138 Def000023
+S A$chksgnlim32$129 Def000018
+S A$chksgnlim32$139 Def000024
+S A$chksgnlim32$149 Def00002F
+S G$checksignedlimit32$0$0 Def000000
+S C$chksgnlim32.c$57$1$28 Def000000
+S C$chksgnlim32.c$58$1$28 Def000039
+S _checksignedlimit32 Def000000
+S C$chksgnlim32.c$5$0$0 Def000000
+S XG$checksignedlimit32$0$0 Def000039
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 C0 01 F9 E5 81 24 F9 F8 E9 30 E7
+R 00 00 00 16
+T 00 00 0D 12 E5 82 26 08 E5 83 36 08 E5 F0 36 08
+R 00 00 00 16
+T 00 00 1A E9 36 64 80 80 0F
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 D3 E5 82 96 08 E5 83 96 08 E5 F0 96 08
+R 00 00 00 16
+T 00 00 2D E9 96
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 33 E4 33 F5 82 D0 01 D0 00 22
+R 00 00 00 16
+
+
+M:chksgnlim32
+F:G$checksignedlimit32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lchksgnlim32.checksignedlimit32$lim$1$27({4}SL:S),B,1,-6
+S:Lchksgnlim32.checksignedlimit32$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sgnlim32
+
+;!FILE libmflarge/sgnlim32.asm
+XH3
+H 1A areas 4D global symbols
+M sgnlim32
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 60 flags 20 addr 0
+S A$sgnlim32$120 Def00000A
+S A$sgnlim32$130 Def000019
+S A$sgnlim32$121 Def00000B
+S A$sgnlim32$140 Def000025
+S A$sgnlim32$131 Def00001A
+S A$sgnlim32$122 Def00000E
+S A$sgnlim32$150 Def000032
+S A$sgnlim32$141 Def000026
+S A$sgnlim32$132 Def00001B
+S A$sgnlim32$123 Def000010
+S A$sgnlim32$114 Def000000
+S A$sgnlim32$160 Def00003E
+S A$sgnlim32$151 Def000033
+S A$sgnlim32$142 Def000028
+S A$sgnlim32$133 Def00001C
+S A$sgnlim32$124 Def000011
+S A$sgnlim32$115 Def000002
+S A$sgnlim32$170 Def00004B
+S A$sgnlim32$161 Def00003F
+S A$sgnlim32$152 Def000034
+S A$sgnlim32$143 Def000029
+S A$sgnlim32$134 Def00001F
+S A$sgnlim32$125 Def000012
+S A$sgnlim32$116 Def000004
+S A$sgnlim32$180 Def000058
+S A$sgnlim32$171 Def00004C
+S A$sgnlim32$162 Def000041
+S A$sgnlim32$144 Def00002A
+S A$sgnlim32$135 Def000020
+S A$sgnlim32$126 Def000014
+S A$sgnlim32$117 Def000005
+S G$signedlimit32$0$0 Def000000
+S A$sgnlim32$172 Def00004D
+S A$sgnlim32$163 Def000042
+S A$sgnlim32$154 Def000036
+S A$sgnlim32$145 Def00002B
+S A$sgnlim32$136 Def000021
+S A$sgnlim32$127 Def000015
+S A$sgnlim32$118 Def000007
+S A$sgnlim32$182 Def00005A
+S A$sgnlim32$173 Def00004F
+S A$sgnlim32$164 Def000043
+S A$sgnlim32$155 Def000037
+S A$sgnlim32$146 Def00002D
+S A$sgnlim32$137 Def000022
+S A$sgnlim32$128 Def000016
+S A$sgnlim32$119 Def000009
+S A$sgnlim32$174 Def000050
+S A$sgnlim32$165 Def000044
+S A$sgnlim32$156 Def000039
+S A$sgnlim32$147 Def00002E
+S A$sgnlim32$138 Def000023
+S A$sgnlim32$129 Def000018
+S A$sgnlim32$184 Def00005B
+S A$sgnlim32$175 Def000051
+S A$sgnlim32$166 Def000045
+S A$sgnlim32$157 Def00003A
+S A$sgnlim32$148 Def00002F
+S A$sgnlim32$139 Def000024
+S A$sgnlim32$185 Def00005D
+S A$sgnlim32$176 Def000053
+S A$sgnlim32$167 Def000048
+S A$sgnlim32$158 Def00003B
+S A$sgnlim32$149 Def000030
+S A$sgnlim32$186 Def00005F
+S A$sgnlim32$177 Def000054
+S A$sgnlim32$168 Def000049
+S A$sgnlim32$159 Def00003D
+S A$sgnlim32$178 Def000055
+S A$sgnlim32$169 Def00004A
+S A$sgnlim32$179 Def000057
+S C$sgnlim32.c$87$1$28 Def000000
+S _signedlimit32 Def000000
+S C$sgnlim32.c$88$1$28 Def000060
+S C$sgnlim32.c$5$0$0 Def000000
+S XG$signedlimit32$0$0 Def000060
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 C0 01 F9 E5 81 24 F9 F8 E9 30 E7
+R 00 00 00 16
+T 00 00 0D 28 E5 82 26 08 E5 83 36 08 E5 F0 36 08
+R 00 00 00 16
+T 00 00 1A E9 36 30 E7 3B 18 18 18 C3 E4 96 08 F5
+R 00 00 00 16
+T 00 00 27 82 E4 96 08 F5 83 E4 96 08 F5 F0 E4 96
+R 00 00 00 16
+T 00 00 34 80 25
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 D3 E5 82 96 08 E5 83 96 08 E5 F0 96 08
+R 00 00 00 16
+T 00 00 43 E9 96 20 E7 12 18 18 18 E6 08 F5 82 E6
+R 00 00 00 16
+T 00 00 50 08 F5 83 E6 08 F5 F0 E6 80 01
+R 00 00 00 16
+T 00 00 5A
+R 00 00 00 16
+T 00 00 5A E9
+R 00 00 00 16
+T 00 00 5B
+R 00 00 00 16
+T 00 00 5B D0 01 D0 00 22
+R 00 00 00 16
+
+
+M:sgnlim32
+F:G$signedlimit32$0$0({2}DF,SL:S),Z,0,0,0,0,0
+S:Lsgnlim32.signedlimit32$lim$1$27({4}SL:S),B,1,-6
+S:Lsgnlim32.signedlimit32$x$1$27({4}SL:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+grayenc8
+
+;!FILE libmflarge/grayenc8.asm
+XH3
+H 1A areas C global symbols
+M grayenc8
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S A$grayenc8$105 Def000000
+S A$grayenc8$106 Def000002
+S A$grayenc8$107 Def000003
+S A$grayenc8$108 Def000004
+S A$grayenc8$109 Def000006
+S C$grayenc8.c$13$1$28 Def000000
+S C$grayenc8.c$14$1$28 Def000007
+S G$gray_encode8$0$0 Def000000
+S _gray_encode8 Def000000
+S C$grayenc8.c$5$0$0 Def000000
+S XG$gray_encode8$0$0 Def000007
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 C3 13 62 82 22
+R 00 00 00 16
+
+
+M:grayenc8
+F:G$gray_encode8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lgrayenc8.gray_encode8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+graydec8
+
+;!FILE libmflarge/graydec8.asm
+XH3
+H 1A areas 24 global symbols
+M graydec8
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 32 flags 20 addr 0
+S C$graydec8.c$37$1$28 Def000000
+S C$graydec8.c$38$1$28 Def000032
+S G$gray_decode8$0$0 Def000000
+S _gray_decode8 Def000000
+S C$graydec8.c$5$0$0 Def000000
+S XG$gray_decode8$0$0 Def000032
+S A$graydec8$110 Def000009
+S A$graydec8$120 Def00001A
+S A$graydec8$111 Def00000A
+S A$graydec8$130 Def00002C
+S A$graydec8$121 Def00001C
+S A$graydec8$112 Def00000C
+S A$graydec8$131 Def00002D
+S A$graydec8$122 Def00001E
+S A$graydec8$113 Def00000E
+S A$graydec8$132 Def00002F
+S A$graydec8$123 Def00001F
+S A$graydec8$114 Def000010
+S A$graydec8$105 Def000000
+S A$graydec8$133 Def000031
+S A$graydec8$124 Def000021
+S A$graydec8$115 Def000011
+S A$graydec8$106 Def000002
+S A$graydec8$125 Def000023
+S A$graydec8$116 Def000013
+S A$graydec8$107 Def000003
+S A$graydec8$126 Def000025
+S A$graydec8$117 Def000015
+S A$graydec8$108 Def000005
+S A$graydec8$127 Def000026
+S A$graydec8$118 Def000017
+S A$graydec8$109 Def000007
+S A$graydec8$128 Def000028
+S A$graydec8$119 Def000018
+S A$graydec8$129 Def00002A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
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+R 00 00 00 16
+T 00 00 27 02 62 82 E5 82 03 54 01 62 82 22
+R 00 00 00 16
+
+
+M:graydec8
+F:G$gray_decode8$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lgraydec8.gray_decode8$x$1$27({1}SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+fmemset
+
+;!FILE libmflarge/fmemset.asm
+XH3
+H 1A areas 2F1 global symbols
+M fmemset
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S A$fmemset$1221 Def00002F
+S A$fmemset$1203 Def000017
+S A$fmemset$1222 Def000031
+S A$fmemset$1213 Def000026
+S A$fmemset$1204 Def00001A
+S A$fmemset$1223 Def000033
+S A$fmemset$1214 Def000027
+S A$fmemset$1205 Def00001C
+S A$fmemset$1215 Def000028
+S A$fmemset$1216 Def00002A
+S A$fmemset$1207 Def00001F
+S G$fmemset$0$0 Def000000
+S A$fmemset$1217 Def00002C
+S A$fmemset$1208 Def000020
+S A$fmemset$1190 Def00000A
+S A$fmemset$1209 Def000021
+S A$fmemset$1191 Def00000B
+S A$fmemset$1219 Def00002D
+S A$fmemset$1192 Def00000C
+S A$fmemset$1183 Def000000
+S A$fmemset$1193 Def00000E
+S A$fmemset$1184 Def000002
+S A$fmemset$1194 Def00000F
+S A$fmemset$1185 Def000003
+S A$fmemset$1186 Def000004
+S A$fmemset$1196 Def000011
+S A$fmemset$1187 Def000006
+S A$fmemset$1188 Def000007
+S A$fmemset$1198 Def000012
+S A$fmemset$1189 Def000009
+S _fmemset Def000000
+S C$fmemset.c$60$1$28 Def000000
+S C$fmemset.c$10$0$0 Def000000
+S C$fmemset.c$61$1$28 Def000034
+S XG$fmemset$0$0 Def000034
+S A$fmemset$1210 Def000023
+S A$fmemset$1201 Def000013
+S A$fmemset$1220 Def00002E
+S A$fmemset$1211 Def000025
+S A$fmemset$1202 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 81 18 18 86 05 18 86 07 18 E6 FE 70
+R 00 00 00 16
+T 00 00 0D 04 4F 70 02
+R 00 00 00 16
+T 00 00 11
+R 00 00 00 16
+T 00 00 11 22
+R 00 00 00 16
+T 00 00 12
+R 00 00 00 16
+T 00 00 12 0F
+R 00 00 00 16
+T 00 00 13
+R 00 00 00 16
+T 00 00 13 ED 20 F7 FA 30 F6 13 A8 82 20 F5 07
+R 00 00 00 16
+T 00 00 1F
+R 00 00 00 16
+T 00 00 1F F6 08 DE FC DF FA 22
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 F2 08 DE FC DF FA 22
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D F0 A3 DE FC DF FA 22
+R 00 00 00 16
+
+
+M:fmemset
+F:G$fmemset$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lfmemset.fmemset$c$1$27({1}SC:S),B,1,-3
+S:Lfmemset.fmemset$n$1$27({2}SI:U),B,1,-5
+S:Lfmemset.fmemset$p$1$27({3}DG,SV:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+fmemcpy
+
+;!FILE libmflarge/fmemcpy.asm
+XH3
+H 1A areas 35F global symbols
+M fmemcpy
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
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+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
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+A BSEG size 0 flags 80 addr 0
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+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E6 flags 20 addr 0
+S A$fmemcpy$1320 Def0000C5
+S A$fmemcpy$1302 Def0000AA
+S A$fmemcpy$1230 Def000042
+S A$fmemcpy$1221 Def000038
+S A$fmemcpy$1212 Def000029
+S A$fmemcpy$1330 Def0000D2
+S A$fmemcpy$1321 Def0000C7
+S A$fmemcpy$1312 Def0000B8
+S A$fmemcpy$1303 Def0000AB
+S A$fmemcpy$1240 Def00004F
+S A$fmemcpy$1231 Def000044
+S A$fmemcpy$1222 Def000039
+S A$fmemcpy$1340 Def0000DC
+S A$fmemcpy$1322 Def0000C9
+S A$fmemcpy$1313 Def0000BB
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+S A$fmemcpy$1232 Def000046
+S A$fmemcpy$1223 Def00003B
+S A$fmemcpy$1214 Def00002C
+S A$fmemcpy$1205 Def000019
+S A$fmemcpy$1341 Def0000DD
+S A$fmemcpy$1332 Def0000D3
+S A$fmemcpy$1314 Def0000BE
+S A$fmemcpy$1305 Def0000AD
+S A$fmemcpy$1260 Def000069
+S A$fmemcpy$1251 Def00005A
+S A$fmemcpy$1242 Def000050
+S A$fmemcpy$1224 Def00003D
+S A$fmemcpy$1215 Def00002F
+S A$fmemcpy$1206 Def00001A
+S A$fmemcpy$1342 Def0000DE
+S A$fmemcpy$1333 Def0000D4
+S A$fmemcpy$1324 Def0000CA
+S A$fmemcpy$1306 Def0000AF
+S A$fmemcpy$1261 Def00006B
+S A$fmemcpy$1252 Def00005D
+S A$fmemcpy$1243 Def000051
+S A$fmemcpy$1234 Def000047
+S A$fmemcpy$1216 Def000032
+S A$fmemcpy$1207 Def00001D
+S G$fmemcpy$0$0 Def000000
+S A$fmemcpy$1343 Def0000DF
+S A$fmemcpy$1334 Def0000D5
+S A$fmemcpy$1325 Def0000CB
+S A$fmemcpy$1316 Def0000C1
+S A$fmemcpy$1307 Def0000B1
+S A$fmemcpy$1280 Def000085
+S A$fmemcpy$1271 Def000075
+S A$fmemcpy$1253 Def000060
+S A$fmemcpy$1244 Def000052
+S A$fmemcpy$1235 Def000048
+S A$fmemcpy$1226 Def00003E
+S A$fmemcpy$1208 Def000020
+S A$fmemcpy$1190 Def00000A
+S A$fmemcpy$1344 Def0000E0
+S A$fmemcpy$1335 Def0000D6
+S A$fmemcpy$1326 Def0000CC
+S A$fmemcpy$1317 Def0000C2
+S A$fmemcpy$1308 Def0000B3
+S A$fmemcpy$1281 Def000086
+S A$fmemcpy$1272 Def000077
+S A$fmemcpy$1263 Def00006C
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+S A$fmemcpy$1236 Def000049
+S A$fmemcpy$1227 Def00003F
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+S A$fmemcpy$1191 Def00000C
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+S A$fmemcpy$1318 Def0000C3
+S A$fmemcpy$1309 Def0000B5
+S A$fmemcpy$1291 Def000096
+S A$fmemcpy$1282 Def000089
+S A$fmemcpy$1273 Def000079
+S A$fmemcpy$1264 Def00006D
+S A$fmemcpy$1255 Def000063
+S A$fmemcpy$1246 Def000054
+S A$fmemcpy$1237 Def00004A
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+S A$fmemcpy$1192 Def00000D
+S A$fmemcpy$1183 Def000000
+S A$fmemcpy$1346 Def0000E3
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+S A$fmemcpy$1328 Def0000CE
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+S A$fmemcpy$1292 Def000098
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+S A$fmemcpy$1274 Def00007B
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+S A$fmemcpy$1256 Def000064
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+S A$fmemcpy$1293 Def00009A
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+S A$fmemcpy$1185 Def000003
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+S A$fmemcpy$1267 Def000070
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+S A$fmemcpy$1195 Def000011
+S A$fmemcpy$1186 Def000004
+S A$fmemcpy$1295 Def00009E
+S A$fmemcpy$1286 Def00008F
+S A$fmemcpy$1268 Def000072
+S A$fmemcpy$1259 Def000067
+S A$fmemcpy$1196 Def000012
+S A$fmemcpy$1187 Def000006
+S A$fmemcpy$1296 Def0000A0
+S A$fmemcpy$1287 Def000091
+S A$fmemcpy$1278 Def000081
+S A$fmemcpy$1269 Def000074
+S A$fmemcpy$1197 Def000014
+S A$fmemcpy$1188 Def000007
+S A$fmemcpy$1288 Def000093
+S A$fmemcpy$1279 Def000084
+S A$fmemcpy$1198 Def000015
+S A$fmemcpy$1189 Def000009
+S C$fmemcpy.c$184$1$28 Def000000
+S A$fmemcpy$1298 Def0000A2
+S A$fmemcpy$1289 Def000095
+S C$fmemcpy.c$185$1$28 Def0000E6
+S A$fmemcpy$1299 Def0000A5
+S _fmemcpy Def000000
+S C$fmemcpy.c$10$0$0 Def000000
+S XG$fmemcpy$0$0 Def0000E6
+S A$fmemcpy$1200 Def000017
+S A$fmemcpy$1300 Def0000A6
+S A$fmemcpy$1210 Def000024
+S A$fmemcpy$1310 Def0000B7
+S A$fmemcpy$1301 Def0000A7
+S A$fmemcpy$1220 Def000037
+S A$fmemcpy$1211 Def000026
+S A$fmemcpy$1202 Def000018
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+
+
+M:fmemcpy
+F:G$fmemcpy$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lfmemcpy.fmemcpy$s$1$27({3}DG,SV:S),B,1,-5
+S:Lfmemcpy.fmemcpy$n$1$27({2}SI:U),B,1,-7
+S:Lfmemcpy.fmemcpy$d$1$27({3}DG,SV:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+delay
+
+;!FILE libmflarge/delay.asm
+XH3
+H 1A areas 11 global symbols
+M delay
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 14 flags 20 addr 0
+S C$delay.c$9$0$0 Def000000
+S G$delay$0$0 Def000000
+S A$delay$110 Def000007
+S A$delay$112 Def000008
+S A$delay$114 Def00000A
+S A$delay$105 Def000000
+S _delay Def000000
+S A$delay$115 Def00000D
+S A$delay$106 Def000002
+S A$delay$116 Def000010
+S A$delay$107 Def000004
+S A$delay$117 Def000013
+S A$delay$109 Def000006
+S C$delay.c$23$1$28 Def000000
+S C$delay.c$24$1$28 Def000014
+S XG$delay$0$0 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 60 02 05 83
+R 00 00 00 16
+T 00 00 06
+R 00 00 00 16
+T 00 00 06 00 00
+R 00 00 00 16
+T 00 00 08
+R 00 00 00 16
+T 00 00 08 74 03
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A D5 E0 FD D5 82 F6 D5 83 F5 22
+R 00 00 00 16
+
+
+M:delay
+F:G$delay$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Ldelay.delay$us$1$27({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+random
+
+;!FILE libmflarge/random.asm
+XH3
+H 1A areas 1F global symbols
+M random
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 2 flags 0 addr 0
+S G$random_seed$0$0 Def000000
+S _random_seed Def000000
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2B flags 20 addr 0
+S G$random$0$0 Def000000
+S A$random$120 Def00000C
+S A$random$130 Def000020
+S A$random$121 Def00000E
+S A$random$131 Def000022
+S A$random$122 Def000010
+S A$random$132 Def000024
+S A$random$123 Def000012
+S A$random$114 Def000000
+S _random Def000000
+S A$random$133 Def000027
+S A$random$124 Def000015
+S A$random$115 Def000002
+S A$random$134 Def000029
+S A$random$125 Def000016
+S A$random$116 Def000005
+S A$random$126 Def000018
+S A$random$117 Def000006
+S A$random$127 Def00001A
+S A$random$118 Def000008
+S A$random$137 Def00002A
+S A$random$128 Def00001C
+S A$random$119 Def00000A
+S A$random$129 Def00001F
+S C$random.c$11$0$0 Def000000
+S C$random.c$35$1$28 Def000000
+S C$random.c$36$1$28 Def00002A
+S XG$random$0$0 Def00002A
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 00 00 00 75 F0 D5 A4 24 9D F5 82 E5
+R 00 00 00 16 F1 21 04 00 05
+T 00 00 0B F0 34 00 F5 83 E5 00 00 00 75 F0 6F A4
+R 00 00 00 16 F1 21 09 00 05
+T 00 00 16 25 83 F5 83 E5 00 00 01 75 F0 D5 A4 25
+R 00 00 00 16 F1 21 08 00 05
+T 00 00 21 83 F5 83 85 82 00 00 00 F5 00 00 01 22
+R 00 00 00 16 F1 21 08 00 05 F1 21 0C 00 05
+T 00 00 2A 22
+R 00 00 00 16
+
+
+M:random
+F:G$random$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sleep
+
+;!FILE libmflarge/sleep.asm
+XH3
+H 1A areas 2E3 global symbols
+M sleep
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S XG$enter_sleep$0$0 Def000025
+S G$enter_sleep$0$0 Def000000
+S A$sleep$1180 Def000011
+S A$sleep$1171 Def000000
+S A$sleep$1190 Def000022
+S A$sleep$1181 Def000012
+S A$sleep$1172 Def000003
+S A$sleep$1182 Def000014
+S A$sleep$1173 Def000004
+S A$sleep$1183 Def000015
+S A$sleep$1174 Def000006
+S A$sleep$1184 Def000016
+S A$sleep$1175 Def000007
+S A$sleep$1185 Def000017
+S A$sleep$1176 Def000009
+S A$sleep$1186 Def000019
+S A$sleep$1177 Def00000A
+S A$sleep$1187 Def00001B
+S A$sleep$1178 Def00000C
+S A$sleep$1188 Def00001D
+S A$sleep$1179 Def00000E
+S A$sleep$1189 Def00001F
+S _enter_sleep Def000000
+S C$sleep.c$33$1$28 Def000000
+S C$sleep.c$10$0$0 Def000000
+S C$sleep.c$34$1$28 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 F5 98 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 0C F0 78 FF F6 18 F6 E5 87 54
+R 00 00 00 16
+T 00 00 1A 0C 44 02 F5 87 75 97 D3 02 E0 47
+R 00 00 00 16
+
+
+M:sleep
+F:G$enter_sleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
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+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+deepsleep
+
+;!FILE libmflarge/deepsleep.asm
+XH3
+H 1A areas 2DE global symbols
+M deepsleep
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1C flags 20 addr 0
+S G$enter_deepsleep$0$0 Def000000
+S A$deepsleep$1180 Def000010
+S A$deepsleep$1171 Def000000
+S A$deepsleep$1181 Def000011
+S A$deepsleep$1172 Def000003
+S A$deepsleep$1182 Def000012
+S A$deepsleep$1173 Def000004
+S A$deepsleep$1183 Def000013
+S A$deepsleep$1174 Def000006
+S A$deepsleep$1184 Def000016
+S A$deepsleep$1175 Def000007
+S A$deepsleep$1185 Def000019
+S A$deepsleep$1176 Def000009
+S A$deepsleep$1177 Def00000A
+S A$deepsleep$1178 Def00000D
+S A$deepsleep$1179 Def00000E
+S _enter_deepsleep Def000000
+S C$deepsleep.c$10$0$0 Def000000
+S XG$enter_deepsleep$0$0 Def00001C
+S C$deepsleep.c$28$1$28 Def000000
+S C$deepsleep.c$29$1$28 Def00001C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 90 70 0C
+R 00 00 00 16
+T 00 00 0D F0 78 FF F6 18 F6 75 87 03 75 97 D3 02
+R 00 00 00 16
+T 00 00 1A E0 47
+R 00 00 00 16
+
+
+M:deepsleep
+F:G$enter_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+sleepcont
+
+;!FILE libmflarge/sleepcont.asm
+XH3
+H 1A areas 2F9 global symbols
+M sleepcont
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S __sdcc_external_startup Ref000000
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 1A flags 20 addr 0
+S A$sleepcont$1220 Def000002
+S A$sleepcont$1230 Def000011
+S A$sleepcont$1221 Def000004
+S A$sleepcont$1231 Def000014
+S A$sleepcont$1222 Def000007
+S A$sleepcont$1232 Def000015
+S A$sleepcont$1223 Def000008
+S A$sleepcont$1233 Def000017
+S A$sleepcont$1224 Def000009
+S A$sleepcont$1225 Def00000A
+S A$sleepcont$1226 Def00000B
+S A$sleepcont$1228 Def00000D
+S A$sleepcont$1219 Def000000
+S XFsleepcont$dummy$0$0 Def00001A
+S A$sleepcont$1229 Def000010
+S C$sleepcont.c$72$1$30 Def00001A
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2A flags 20 addr 0
+S _enter_sleep_cont Def000000
+S Fsleepcont$dummy$0$0 Def00002A
+S XG$enter_sleep_cont$0$0 Def00002A
+S A$sleepcont$1180 Def000011
+S A$sleepcont$1171 Def000000
+S A$sleepcont$1190 Def000022
+S A$sleepcont$1181 Def000012
+S A$sleepcont$1172 Def000003
+S A$sleepcont$1191 Def000024
+S A$sleepcont$1182 Def000014
+S A$sleepcont$1173 Def000004
+S A$sleepcont$1192 Def000027
+S A$sleepcont$1183 Def000016
+S A$sleepcont$1174 Def000006
+S A$sleepcont$1184 Def000017
+S A$sleepcont$1175 Def000007
+S A$sleepcont$1185 Def000019
+S A$sleepcont$1176 Def000009
+S A$sleepcont$1186 Def00001A
+S A$sleepcont$1177 Def00000A
+S A$sleepcont$1187 Def00001C
+S A$sleepcont$1178 Def00000C
+S A$sleepcont$1188 Def00001E
+S A$sleepcont$1179 Def00000E
+S A$sleepcont$1189 Def000020
+S C$sleepcont.c$71$1$30 Def00002A
+S C$sleepcont.c$41$1$28 Def00002A
+S C$sleepcont.c$13$0$0 Def000000
+S C$sleepcont.c$38$1$28 Def000000
+S C$sleepcont.c$39$1$28 Def00002A
+S G$enter_sleep_cont$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 70 44 E0 54 BF F0 C2 AF E4 F5 98 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 0C F0 78 FF 76 BE 18 76 37 18
+R 00 00 00 16
+T 00 00 1A A6 81 E5 87 54 0C 44 02 F5 87 75 97 D3
+R 00 00 00 16
+T 00 00 27 02 E0 47
+R 00 00 00 16
+T 00 00 2A
+R 00 00 00 16
+T 00 00 00 78 FF E5 87 20 E6 06 E4 F6 18 F6 80 0D
+R 00 00 00 0F
+T 00 00 0D
+R 00 00 00 0F
+T 00 00 0D B6 BE 0A 18 B6 37 06 18 86 81 02 00 00
+R 00 00 00 0F 02 0E 00 AE
+T 00 00 1A
+R 00 00 00 0F
+
+
+M:sleepcont
+F:G$enter_sleep_cont$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fsleepcont$dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:Fsleepcont$dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+standby
+
+;!FILE libmflarge/standby.asm
+XH3
+H 1A areas 2DA global symbols
+M standby
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F flags 20 addr 0
+S G$enter_standby$0$0 Def000000
+S A$standby$1180 Def00000D
+S A$standby$1171 Def000000
+S A$standby$1181 Def00000E
+S A$standby$1172 Def000002
+S A$standby$1173 Def000004
+S A$standby$1174 Def000006
+S A$standby$1175 Def000008
+S A$standby$1176 Def000009
+S A$standby$1177 Def00000A
+S A$standby$1178 Def00000B
+S A$standby$1179 Def00000C
+S _enter_standby Def000000
+S C$standby.c$24$1$28 Def000000
+S C$standby.c$10$0$0 Def000000
+S C$standby.c$25$1$28 Def00000F
+S XG$enter_standby$0$0 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 87 54 0C 44 01 F5 87 00 22 00 00 00
+R 00 00 00 16
+T 00 00 0D 00 00
+R 00 00 00 16
+
+
+M:standby
+F:G$enter_standby$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+resetcpu
+
+;!FILE libmflarge/resetcpu.asm
+XH3
+H 1A areas 2D9 global symbols
+M resetcpu
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E flags 20 addr 0
+S A$resetcpu$1182 Def000005
+S A$resetcpu$1192 Def00000D
+S A$resetcpu$1183 Def000006
+S A$resetcpu$1186 Def000007
+S A$resetcpu$1178 Def000000
+S A$resetcpu$1189 Def00000A
+S C$resetcpu.c$12$1$28 Def000000
+S C$resetcpu.c$13$1$28 Def000002
+S C$resetcpu.c$14$1$28 Def000007
+S C$resetcpu.c$10$0$0 Def000000
+S C$resetcpu.c$17$1$28 Def00000A
+S C$resetcpu.c$18$1$28 Def00000D
+S G$reset_cpu$0$0 Def000000
+S _reset_cpu Def000000
+S XG$reset_cpu$0$0 Def00000D
+S A$resetcpu$1181 Def000002
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 AF 90 70 0C E4 F0 75 97 D3 02 E0 47
+R 00 00 00 16
+T 00 00 0D 22
+R 00 00 00 16
+
+
+M:resetcpu
+F:G$reset_cpu$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+flashunlock
+
+;!FILE libmflarge/flashunlock.asm
+XH3
+H 1B areas 2DD global symbols
+M flashunlock
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S Fflashunlock$flash_deviceid$0$0 Def00FC06
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 11 flags 20 addr 0
+S G$flash_unlock$0$0 Def000000
+S C$flashunlock.c$6$1$35 Def000000
+S C$flashunlock.c$7$1$35 Def000005
+S C$flashunlock.c$8$1$35 Def000007
+S C$flashunlock.c$9$1$35 Def00000A
+S C$flashunlock.c$4$0$0 Def000000
+S _flash_unlock Def000000
+S XG$flash_unlock$0$0 Def000010
+S A$flashunlock$1201 Def000010
+S A$flashunlock$1191 Def000007
+S A$flashunlock$1183 Def000000
+S A$flashunlock$1184 Def000002
+S A$flashunlock$1194 Def00000A
+S A$flashunlock$1185 Def000004
+S A$flashunlock$1197 Def00000D
+S A$flashunlock$1188 Def000005
+S A$flashunlock$1198 Def00000E
+S C$flashunlock.c$10$1$35 Def00000D
+S C$flashunlock.c$11$1$35 Def000010
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 74 80 55 A8 FF C2 AF 75 96 41 75 96 78
+R 00 00 00 17
+T 00 00 0D EF 42 A8 22
+R 00 00 00 17
+
+
+M:flashunlock
+F:G$flash_unlock$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashunlock$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashlock
+
+;!FILE libmflarge/flashlock.asm
+XH3
+H 1A areas 2D2 global symbols
+M flashlock
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S Fflashlock$flash_deviceid$0$0 Def00FC06
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4 flags 20 addr 0
+S XG$flash_lock$0$0 Def000003
+S A$flashlock$1180 Def000000
+S A$flashlock$1183 Def000003
+S G$flash_lock$0$0 Def000000
+S C$flashlock.c$6$1$35 Def000000
+S C$flashlock.c$7$1$35 Def000003
+S C$flashlock.c$4$0$0 Def000000
+S _flash_lock Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 96 00 22
+R 00 00 00 16
+
+
+M:flashlock
+F:G$flash_lock$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
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+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashwait
+
+;!FILE libmflarge/flashwait.asm
+XH3
+H 1B areas 2FD global symbols
+M flashwait
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S Fflashwait$flash_deviceid$0$0 Def00FC06
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 2 flags 40 addr 0
+S Lflashwait.flash_wait$timeout$1$34 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 33 flags 20 addr 0
+S C$flashwait.c$8$1$0 Def000013
+S _flash_wait Def000000
+S XG$flash_wait$0$0 Def000032
+S A$flashwait$1200 Def000011
+S A$flashwait$1201 Def000012
+S A$flashwait$1220 Def000019
+S A$flashwait$1211 Def000016
+S A$flashwait$1230 Def000023
+S A$flashwait$1221 Def00001A
+S A$flashwait$1240 Def00002B
+S A$flashwait$1233 Def000026
+S A$flashwait$1224 Def00001D
+S A$flashwait$1206 Def000013
+S A$flashwait$1252 Def000032
+S A$flashwait$1243 Def00002D
+S A$flashwait$1234 Def000029
+S A$flashwait$1225 Def000020
+S A$flashwait$1207 Def000014
+S A$flashwait$1208 Def000015
+S A$flashwait$1190 Def000007
+S A$flashwait$1191 Def000008
+S A$flashwait$1219 Def000017
+S A$flashwait$1192 Def000009
+S A$flashwait$1229 Def000022
+S A$flashwait$1193 Def00000A
+S A$flashwait$1248 Def00002F
+S A$flashwait$1196 Def00000B
+S A$flashwait$1187 Def000000
+S A$flashwait$1197 Def00000E
+S A$flashwait$1188 Def000002
+S A$flashwait$1198 Def00000F
+S A$flashwait$1189 Def000004
+S A$flashwait$1199 Def000010
+S C$flashwait.c$10$1$35 Def000016
+S C$flashwait.c$21$1$35 Def00002F
+S C$flashwait.c$22$1$35 Def00002F
+S C$flashwait.c$20$2$36 Def00002D
+S C$flashwait.c$23$1$35 Def000032
+S C$flashwait.c$12$2$36 Def000017
+S C$flashwait.c$13$3$37 Def000017
+S C$flashwait.c$14$3$37 Def000017
+S C$flashwait.c$15$3$37 Def00001D
+S C$flashwait.c$16$3$37 Def000022
+S C$flashwait.c$19$2$36 Def00002B
+S C$flashwait.c$17$3$37 Def000026
+S C$flashwait.c$18$3$37 Def00002B
+S G$flash_wait$0$0 Def000000
+S C$flashwait.c$9$1$35 Def000013
+S C$flashwait.c$4$0$0 Def000000
+S C$flashwait.c$7$1$0 Def00000B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0B
+T 00 00 00
+R 00 00 00 0B
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 AF 83 E5 82 90 00 00 F0 EF A3 F0 90
+R 00 00 00 17 00 08 00 0B
+T 00 00 0C 00 00 E0 FE A3 E0 FD ED 04 FF 0E
+R 00 00 00 17 00 03 00 0B
+T 00 00 17
+R 00 00 00 17
+T 00 00 17 E5 91 FD 20 E1 05 75 82 FE 80 10
+R 00 00 00 17
+T 00 00 22
+R 00 00 00 17
+T 00 00 22 ED 20 E0 05 75 82 00 80 07
+R 00 00 00 17
+T 00 00 2B
+R 00 00 00 17
+T 00 00 2B DE EA DF E8 75 82 FF
+R 00 00 00 17
+T 00 00 32
+R 00 00 00 17
+T 00 00 32 22
+R 00 00 00 17
+
+
+M:flashwait
+F:G$flash_wait$0$0({2}DF,SC:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
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+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashpgerase
+
+;!FILE libmflarge/flashpgerase.asm
+XH3
+H 1A areas 2E8 global symbols
+M flashpgerase
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S _flash_wait Ref000000
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S Fflashpgerase$flash_deviceid$0$0 Def00FC06
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 2 flags 40 addr 0
+S Lflashpgerase.flash_pageerase$pgaddr$1$34 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 21 flags 20 addr 0
+S A$flashpgerase$1202 Def000015
+S A$flashpgerase$1212 Def000020
+S XG$flash_pageerase$0$0 Def000020
+S A$flashpgerase$1205 Def000017
+S A$flashpgerase$1208 Def00001A
+S A$flashpgerase$1190 Def00000A
+S A$flashpgerase$1209 Def00001D
+S A$flashpgerase$1193 Def00000B
+S A$flashpgerase$1184 Def000000
+S A$flashpgerase$1194 Def00000E
+S A$flashpgerase$1185 Def000002
+S A$flashpgerase$1195 Def00000F
+S A$flashpgerase$1186 Def000004
+S A$flashpgerase$1196 Def000010
+S A$flashpgerase$1187 Def000007
+S A$flashpgerase$1197 Def000011
+S A$flashpgerase$1188 Def000008
+S A$flashpgerase$1198 Def000012
+S A$flashpgerase$1189 Def000009
+S A$flashpgerase$1199 Def000013
+S C$flashpgerase.c$10$1$35 Def000020
+S C$flashpgerase.c$6$1$35 Def00000B
+S C$flashpgerase.c$7$1$35 Def000015
+S C$flashpgerase.c$8$1$35 Def000017
+S C$flashpgerase.c$9$1$35 Def00001A
+S C$flashpgerase.c$4$0$0 Def000000
+S G$flash_pageerase$0$0 Def000000
+S _flash_pageerase Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 83 E5 82 90 00 00 F0 EF A3 F0 90
+R 00 00 00 16 00 08 00 0A
+T 00 00 0C 00 00 E0 FE A3 E0 FF 8E 92 8F 93 75 91
+R 00 00 00 16 00 03 00 0A
+T 00 00 19 20 90 FF FF 12 00 00 22
+R 00 00 00 16 02 08 00 18
+
+
+M:flashpgerase
+F:G$flash_pageerase$0$0({2}DF,SC:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashpgerase$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:Lflashpgerase.flash_pageerase$pgaddr$1$34({2}SI:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashwrite
+
+;!FILE libmflarge/flashwrite.asm
+XH3
+H 1A areas 2F4 global symbols
+M flashwrite
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S _flash_wait Ref000000
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S Fflashwrite$flash_deviceid$0$0 Def00FC06
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
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+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
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+S _PORTA_5 Def000085
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+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashread
+
+;!FILE libmflarge/flashread.asm
+XH3
+H 1A areas 23 global symbols
+M flashread
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S Fflashread$flash_deviceid$0$0 Def00FC06
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 2 flags 40 addr 0
+S Lflashread.flash_read$raddr$1$34 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 25 flags 20 addr 0
+S A$flashread$120 Def000008
+S A$flashread$130 Def000012
+S A$flashread$121 Def000009
+S A$flashread$140 Def00001E
+S A$flashread$131 Def000013
+S A$flashread$122 Def00000A
+S A$flashread$141 Def00001F
+S A$flashread$132 Def000016
+S A$flashread$133 Def000018
+S A$flashread$125 Def00000B
+S A$flashread$116 Def000000
+S A$flashread$144 Def000020
+S A$flashread$126 Def00000E
+S A$flashread$117 Def000002
+S A$flashread$145 Def000022
+S A$flashread$136 Def00001A
+S A$flashread$127 Def00000F
+S A$flashread$118 Def000004
+S A$flashread$146 Def000024
+S A$flashread$137 Def00001B
+S A$flashread$128 Def000010
+S A$flashread$119 Def000007
+S A$flashread$138 Def00001C
+S A$flashread$129 Def000011
+S A$flashread$139 Def00001D
+S C$flashread.c$5$1$35 Def00000B
+S G$flash_read$0$0 Def000000
+S C$flashread.c$6$1$35 Def00001A
+S C$flashread.c$7$1$35 Def000020
+S C$flashread.c$3$0$0 Def000000
+S _flash_read Def000000
+S XG$flash_read$0$0 Def000020
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 83 E5 82 90 00 00 F0 EF A3 F0 90
+R 00 00 00 16 00 08 00 0A
+T 00 00 0C 00 00 E0 FE A3 E0 FF 53 06 FE 8E 82 8F
+R 00 00 00 16 00 03 00 0A
+T 00 00 19 83 E4 93 FE A3 E4 93 8E 82 F5 83 22
+R 00 00 00 16
+
+
+M:flashread
+F:G$flash_read$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fflashread$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:Lflashread.flash_read$raddr$1$34({2}SI:U),F,0,0
+S:Lflashread.flash_read$p$1$35({2}DC,SI:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_apply_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+flashcal
+
+;!FILE libmflarge/flashcal.asm
+XH3
+H 1A areas 3E0 global symbols
+M flashcal
+O -mmcs51 --model-large
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S _crc_crc8ccitt_msbtable Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _ADCCALG00GAIN0 Def007030
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$POWCTRL0$0$0 Def007F10
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG00GAIN1 Def007031
+S _ADCCALG01GAIN0 Def007032
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$POWCTRL1$0$0 Def007F11
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$ADCCALTEMPGAIN0$0$0 Def007038
+S G$REF$0$0 Def007F16
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$ADCCALTEMPGAIN1$0$0 Def007039
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
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+,0,0)({18}S:S$caltempgain$0$0({2}DA2d,SC:U),Z,0,0)({20}S:S$caltempoffs$0$0({2}DA2d,SC:U),Z,0,0)({22}S:S$frcoscfreq$0$0({2}DA2d,SC:U),Z,0,0)({24}S:S$lposcfreq$0$0({2}DA2d,SC:U),Z,0,0)({26}S:S$lposcfreq_fast$0$0({2}DA2d,SC:U),Z,0,0)({28}S:S$powctrl0$0$0({
+
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+1}SC:U),Z,0,0)({29}S:S$powctrl1$0$0({1}SC:U),Z,0,0)({30}S:S$ref$0$0({1}SC:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Fflashcal$flash_deviceid$0$0({6}DA6d,SC:U),F,0,0
+S:Fflashcal$flash_calsector$0$0({31}STcalsector:S),F,0,0
+S:G$REF$0$0({1}SC:U),F,0,0
+S:G$POWCTRL0$0$0({1}SC:U),F,0,0
+S:G$POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPGAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPGAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPOFFS0$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPOFFS1$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_irq$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_poll$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$dbglink_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_init$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_rx$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_tx$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$dbglink_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$dbglink_writeu32$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt$0$0({2}DF,SI:U),C,0,0
+S:G$crc_ccitt_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb_byte$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc16dnp_msb$0$0({2}DF,SI:U),C,0,0
+S:G$crc_crc32_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb_byte$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc32_msb$0$0({2}DF,SL:U),C,0,0
+S:G$crc_crc8ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8ccitt_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire$0$0({2}DF,SC:U),C,0,0
+S:G$crc_crc8onewire_msb$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_ccitt$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire_byte$0$0({2}DF,SC:U),C,0,0
+S:G$crc8_onewire$0$0({2}DF,SC:U),C,0,0
+S:G$pn9_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bit$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_bits$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_advance_byte$0$0({2}DF,SI:U),C,0,0
+S:G$pn9_buffer$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_advance$0$0({2}DF,SI:U),C,0,0
+S:G$pn15_output$0$0({2}DF,SC:U),C,0,0
+S:G$flash_unlock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_lock$0$0({2}DF,SV:S),C,0,0
+S:G$flash_wait$0$0({2}DF,SC:S),C,0,0
+S:G$flash_pageerase$0$0({2}DF,SC:S),C,0,0
+S:G$flash_write$0$0({2}DF,SC:S),C,0,0
+S:G$flash_read$0$0({2}DF,SI:U),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$crc_ccitt_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_ccitt_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc16dnp_msbtable$0$0({512}DA256d,SI:U),D,0,0
+S:G$crc_crc32_table$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc32_msbtable$0$0({1024}DA256d,SL:U),D,0,0
+S:G$crc_crc8ccitt_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8ccitt_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$crc_crc8onewire_msbtable$0$0({256}DA256d,SC:U),D,0,0
+S:G$pn9_table$0$0({512}DA512d,SC:U),D,0,0
+S:G$pn15_adv_table$0$0({512}DA256d,SI:U),D,0,0
+S:G$pn15_out_table$0$0({256}DA256d,SC:U),D,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+flashcsec
+
+XH3
+H 1A areas 2 global symbols
+M flashcsec
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+S Fflashcsec$flash_calsector$0$0 Def00FC00
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:flashcsec
+T:Fflashcsec$calsector[({0}S:S$id$0$0({5}DA5d,SC:U),Z,0,0)({5}S:S$len$0$0({1}SC:U),Z,0,0)({6}S:S$devid$0$0({6}DA6d,SC:U),Z,0,0)({12}S:S$calg00gain$0$0({2}DA2d,SC:U),Z,0,0)({14}S:S$calg01gain$0$0({2}DA2d,SC:U),Z,0,0)({16}S:S$calg10gain$0$0({2}DA2d,SC:U),
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+Z,0,0)({18}S:S$caltempgain$0$0({2}DA2d,SC:U),Z,0,0)({20}S:S$caltempoffs$0$0({2}DA2d,SC:U),Z,0,0)({22}S:S$frcoscfreq$0$0({2}DA2d,SC:U),Z,0,0)({24}S:S$lposcfreq$0$0({2}DA2d,SC:U),Z,0,0)({26}S:S$lposcfreq_fast$0$0({2}DA2d,SC:U),Z,0,0)({28}S:S$powctrl0$0$0(
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+{1}SC:U),Z,0,0)({29}S:S$powctrl1$0$0({1}SC:U),Z,0,0)({30}S:S$ref$0$0({1}SC:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fflashcsec$flash_calsector$0$0({31}STcalsector:S),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer0
+
+;!FILE libmflarge/uarttimer0.asm
+XH3
+H 1A areas 410 global symbols
+M uarttimer0
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 18C flags 20 addr 0
+S _uart_timer0_baud Def000000
+S C$uarttimer0.c$9$0$0 Def000000
+S XG$uart_timer0_baud$0$0 Def00018B
+S A$uarttimer0$1200 Def000014
+S A$uarttimer0$1300 Def00007C
+S A$uarttimer0$1210 Def00001E
+S A$uarttimer0$1201 Def000015
+S A$uarttimer0$1400 Def0000DC
+S A$uarttimer0$1310 Def000083
+S A$uarttimer0$1301 Def00007D
+S A$uarttimer0$1220 Def000029
+S A$uarttimer0$1202 Def000016
+S A$uarttimer0$1500 Def00015D
+S A$uarttimer0$1410 Def0000E8
+S A$uarttimer0$1401 Def0000DE
+S A$uarttimer0$1320 Def000090
+S A$uarttimer0$1311 Def000085
+S A$uarttimer0$1302 Def00007E
+S A$uarttimer0$1230 Def000033
+S A$uarttimer0$1221 Def00002A
+S A$uarttimer0$1510 Def000167
+S A$uarttimer0$1501 Def00015E
+S A$uarttimer0$1420 Def0000F2
+S A$uarttimer0$1411 Def0000E9
+S A$uarttimer0$1402 Def0000E0
+S A$uarttimer0$1330 Def00009C
+S A$uarttimer0$1321 Def000092
+S A$uarttimer0$1312 Def000087
+S A$uarttimer0$1240 Def00003B
+S A$uarttimer0$1231 Def000034
+S A$uarttimer0$1222 Def00002B
+S A$uarttimer0$1213 Def000020
+S A$uarttimer0$1520 Def00016F
+S A$uarttimer0$1511 Def000168
+S A$uarttimer0$1502 Def00015F
+S A$uarttimer0$1430 Def0000FD
+S A$uarttimer0$1421 Def0000F3
+S A$uarttimer0$1412 Def0000EA
+S A$uarttimer0$1403 Def0000E1
+S A$uarttimer0$1340 Def0000A6
+S A$uarttimer0$1331 Def00009D
+S A$uarttimer0$1322 Def000093
+S A$uarttimer0$1232 Def000035
+S A$uarttimer0$1223 Def00002C
+S A$uarttimer0$1214 Def000022
+S A$uarttimer0$1205 Def000017
+S A$uarttimer0$1530 Def00017A
+S A$uarttimer0$1521 Def000170
+S A$uarttimer0$1512 Def000169
+S A$uarttimer0$1503 Def000160
+S A$uarttimer0$1440 Def000109
+S A$uarttimer0$1431 Def0000FE
+S A$uarttimer0$1422 Def0000F4
+S A$uarttimer0$1413 Def0000EB
+S A$uarttimer0$1350 Def0000B1
+S A$uarttimer0$1341 Def0000A7
+S A$uarttimer0$1332 Def00009E
+S A$uarttimer0$1323 Def000094
+S A$uarttimer0$1314 Def000089
+S A$uarttimer0$1305 Def00007F
+S A$uarttimer0$1260 Def000051
+S A$uarttimer0$1251 Def000047
+S A$uarttimer0$1224 Def00002D
+S A$uarttimer0$1215 Def000024
+S A$uarttimer0$1206 Def000018
+S A$uarttimer0$1540 Def000186
+S A$uarttimer0$1522 Def000172
+S A$uarttimer0$1513 Def00016A
+S A$uarttimer0$1504 Def000161
+S A$uarttimer0$1450 Def000116
+S A$uarttimer0$1441 Def00010A
+S A$uarttimer0$1432 Def000101
+S A$uarttimer0$1423 Def0000F5
+S A$uarttimer0$1414 Def0000EC
+S A$uarttimer0$1405 Def0000E3
+S A$uarttimer0$1351 Def0000B2
+S A$uarttimer0$1342 Def0000A9
+S A$uarttimer0$1333 Def00009F
+S A$uarttimer0$1324 Def000096
+S A$uarttimer0$1270 Def00005D
+S A$uarttimer0$1261 Def000052
+S A$uarttimer0$1225 Def00002E
+S A$uarttimer0$1216 Def000025
+S A$uarttimer0$1207 Def000019
+S A$uarttimer0$1541 Def000187
+S A$uarttimer0$1523 Def000173
+S A$uarttimer0$1514 Def00016B
+S A$uarttimer0$1505 Def000162
+S A$uarttimer0$1460 Def000127
+S A$uarttimer0$1451 Def000117
+S A$uarttimer0$1442 Def00010B
+S A$uarttimer0$1433 Def000102
+S A$uarttimer0$1415 Def0000ED
+S A$uarttimer0$1406 Def0000E4
+S A$uarttimer0$1370 Def0000C1
+S A$uarttimer0$1361 Def0000B8
+S A$uarttimer0$1352 Def0000B3
+S A$uarttimer0$1343 Def0000AA
+S A$uarttimer0$1334 Def0000A0
+S A$uarttimer0$1325 Def000097
+S A$uarttimer0$1316 Def00008C
+S A$uarttimer0$1280 Def000068
+S A$uarttimer0$1271 Def00005E
+S A$uarttimer0$1262 Def000053
+S A$uarttimer0$1244 Def00003D
+S A$uarttimer0$1235 Def000037
+S A$uarttimer0$1226 Def00002F
+S A$uarttimer0$1217 Def000026
+S A$uarttimer0$1208 Def00001B
+S A$uarttimer0$1542 Def000189
+S A$uarttimer0$1533 Def00017C
+S A$uarttimer0$1515 Def00016C
+S A$uarttimer0$1506 Def000163
+S A$uarttimer0$1470 Def000137
+S A$uarttimer0$1461 Def000129
+S A$uarttimer0$1452 Def000119
+S A$uarttimer0$1443 Def00010C
+S A$uarttimer0$1434 Def000103
+S A$uarttimer0$1425 Def0000F6
+S A$uarttimer0$1416 Def0000EE
+S A$uarttimer0$1407 Def0000E5
+S A$uarttimer0$1380 Def0000CD
+S A$uarttimer0$1371 Def0000C3
+S A$uarttimer0$1353 Def0000B4
+S A$uarttimer0$1344 Def0000AB
+S A$uarttimer0$1335 Def0000A1
+S A$uarttimer0$1326 Def000098
+S A$uarttimer0$1290 Def000073
+S A$uarttimer0$1281 Def000069
+S A$uarttimer0$1272 Def00005F
+S A$uarttimer0$1263 Def000054
+S A$uarttimer0$1254 Def000049
+S A$uarttimer0$1245 Def00003E
+S A$uarttimer0$1236 Def000038
+S A$uarttimer0$1227 Def000030
+S A$uarttimer0$1218 Def000027
+S A$uarttimer0$1191 Def000009
+S A$uarttimer0$1182 Def000000
+S A$uarttimer0$1516 Def00016D
+S A$uarttimer0$1507 Def000164
+S A$uarttimer0$1480 Def000143
+S A$uarttimer0$1471 Def000139
+S A$uarttimer0$1462 Def00012A
+S A$uarttimer0$1453 Def00011A
+S A$uarttimer0$1444 Def00010D
+S A$uarttimer0$1435 Def000104
+S A$uarttimer0$1417 Def0000EF
+S A$uarttimer0$1408 Def0000E6
+S A$uarttimer0$1381 Def0000CE
+S A$uarttimer0$1372 Def0000C4
+S A$uarttimer0$1354 Def0000B5
+S A$uarttimer0$1345 Def0000AC
+S A$uarttimer0$1336 Def0000A2
+S A$uarttimer0$1327 Def000099
+S A$uarttimer0$1309 Def000082
+S A$uarttimer0$1291 Def000074
+S A$uarttimer0$1282 Def00006A
+S A$uarttimer0$1273 Def000060
+S A$uarttimer0$1264 Def000056
+S A$uarttimer0$1255 Def00004B
+S A$uarttimer0$1246 Def000040
+S A$uarttimer0$1237 Def00003A
+S A$uarttimer0$1228 Def000031
+S A$uarttimer0$1219 Def000028
+S A$uarttimer0$1192 Def00000A
+S A$uarttimer0$1183 Def000002
+S A$uarttimer0$1517 Def00016E
+S A$uarttimer0$1508 Def000165
+S A$uarttimer0$1490 Def000150
+S A$uarttimer0$1481 Def000144
+S A$uarttimer0$1472 Def00013A
+S A$uarttimer0$1463 Def00012C
+S A$uarttimer0$1454 Def00011C
+S A$uarttimer0$1445 Def00010E
+S A$uarttimer0$1436 Def000105
+S A$uarttimer0$1418 Def0000F0
+S A$uarttimer0$1409 Def0000E7
+S A$uarttimer0$1382 Def0000CF
+S A$uarttimer0$1373 Def0000C5
+S A$uarttimer0$1346 Def0000AD
+S A$uarttimer0$1337 Def0000A3
+S A$uarttimer0$1328 Def00009A
+S A$uarttimer0$1319 Def00008E
+S A$uarttimer0$1292 Def000075
+S A$uarttimer0$1283 Def00006B
+S A$uarttimer0$1274 Def000061
+S A$uarttimer0$1265 Def000057
+S A$uarttimer0$1256 Def00004D
+S A$uarttimer0$1247 Def000042
+S A$uarttimer0$1229 Def000032
+S A$uarttimer0$1193 Def00000C
+S A$uarttimer0$1184 Def000005
+S A$uarttimer0$1545 Def00018B
+S A$uarttimer0$1536 Def00017F
+S A$uarttimer0$1527 Def000175
+S A$uarttimer0$1509 Def000166
+S A$uarttimer0$1491 Def000152
+S A$uarttimer0$1482 Def000145
+S A$uarttimer0$1464 Def00012E
+S A$uarttimer0$1455 Def00011D
+S A$uarttimer0$1446 Def00010F
+S A$uarttimer0$1437 Def000106
+S A$uarttimer0$1428 Def0000F9
+S A$uarttimer0$1419 Def0000F1
+S A$uarttimer0$1392 Def0000D5
+S A$uarttimer0$1383 Def0000D0
+S A$uarttimer0$1374 Def0000C7
+S A$uarttimer0$1365 Def0000BB
+S A$uarttimer0$1347 Def0000AE
+S A$uarttimer0$1338 Def0000A4
+S A$uarttimer0$1329 Def00009B
+S A$uarttimer0$1293 Def000077
+S A$uarttimer0$1284 Def00006C
+S A$uarttimer0$1275 Def000062
+S A$uarttimer0$1266 Def000058
+S A$uarttimer0$1257 Def00004E
+S A$uarttimer0$1537 Def000181
+S A$uarttimer0$1528 Def000178
+S A$uarttimer0$1492 Def000153
+S A$uarttimer0$1483 Def000146
+S A$uarttimer0$1465 Def000130
+S A$uarttimer0$1456 Def00011E
+S A$uarttimer0$1447 Def000111
+S A$uarttimer0$1438 Def000107
+S A$uarttimer0$1429 Def0000FB
+S A$uarttimer0$1384 Def0000D1
+S A$uarttimer0$1375 Def0000C8
+S A$uarttimer0$1366 Def0000BC
+S A$uarttimer0$1357 Def0000B6
+S A$uarttimer0$1348 Def0000AF
+S A$uarttimer0$1339 Def0000A5
+S A$uarttimer0$1294 Def000078
+S A$uarttimer0$1285 Def00006D
+S A$uarttimer0$1276 Def000063
+S A$uarttimer0$1267 Def000059
+S A$uarttimer0$1258 Def00004F
+S A$uarttimer0$1249 Def000044
+S A$uarttimer0$1538 Def000183
+S A$uarttimer0$1529 Def000179
+S A$uarttimer0$1493 Def000155
+S A$uarttimer0$1484 Def000148
+S A$uarttimer0$1475 Def00013C
+S A$uarttimer0$1466 Def000131
+S A$uarttimer0$1457 Def000120
+S A$uarttimer0$1448 Def000113
+S A$uarttimer0$1439 Def000108
+S A$uarttimer0$1385 Def0000D2
+S A$uarttimer0$1376 Def0000C9
+S A$uarttimer0$1358 Def0000B7
+S A$uarttimer0$1349 Def0000B0
+S A$uarttimer0$1295 Def000079
+S A$uarttimer0$1286 Def00006E
+S A$uarttimer0$1277 Def000064
+S A$uarttimer0$1268 Def00005A
+S A$uarttimer0$1259 Def000050
+S A$uarttimer0$1187 Def000007
+S A$uarttimer0$1539 Def000184
+S A$uarttimer0$1485 Def000149
+S A$uarttimer0$1467 Def000133
+S A$uarttimer0$1458 Def000123
+S A$uarttimer0$1449 Def000114
+S A$uarttimer0$1386 Def0000D3
+S A$uarttimer0$1377 Def0000CA
+S A$uarttimer0$1296 Def00007A
+S A$uarttimer0$1287 Def000070
+S A$uarttimer0$1278 Def000065
+S A$uarttimer0$1269 Def00005B
+S A$uarttimer0$1197 Def00000F
+S A$uarttimer0$1486 Def00014A
+S A$uarttimer0$1477 Def00013E
+S A$uarttimer0$1468 Def000134
+S A$uarttimer0$1459 Def000125
+S A$uarttimer0$1378 Def0000CB
+S A$uarttimer0$1369 Def0000BF
+S A$uarttimer0$1288 Def000071
+S A$uarttimer0$1279 Def000067
+S A$uarttimer0$1198 Def000011
+S C$uarttimer0.c$12$1$31 Def000009
+S A$uarttimer0$1496 Def000157
+S A$uarttimer0$1487 Def00014C
+S A$uarttimer0$1478 Def000140
+S A$uarttimer0$1469 Def000136
+S A$uarttimer0$1379 Def0000CC
+S A$uarttimer0$1289 Def000072
+S A$uarttimer0$1199 Def000013
+S A$uarttimer0$1497 Def000159
+S A$uarttimer0$1488 Def00014D
+S A$uarttimer0$1479 Def000142
+S A$uarttimer0$1398 Def0000D8
+S A$uarttimer0$1389 Def0000D4
+S A$uarttimer0$1299 Def00007B
+S C$uarttimer0.c$13$2$31 Def00000F
+S A$uarttimer0$1498 Def00015B
+S A$uarttimer0$1489 Def00014E
+S A$uarttimer0$1399 Def0000DA
+S A$uarttimer0$1499 Def00015C
+S C$uarttimer0.c$43$1$31 Def000175
+S C$uarttimer0.c$34$1$31 Def0000D8
+S C$uarttimer0.c$20$3$34 Def000049
+S C$uarttimer0.c$14$2$32 Def000017
+S C$uarttimer0.c$44$1$31 Def00017C
+S C$uarttimer0.c$24$2$32 Def000082
+S C$uarttimer0.c$21$3$34 Def00007B
+S C$uarttimer0.c$45$1$31 Def00017F
+S C$uarttimer0.c$36$1$31 Def0000D8
+S C$uarttimer0.c$22$3$34 Def00007F
+S C$uarttimer0.c$46$1$31 Def00018B
+S C$uarttimer0.c$37$1$31 Def0000F9
+S C$uarttimer0.c$30$3$36 Def0000BF
+S C$uarttimer0.c$15$3$33 Def000020
+S C$uarttimer0.c$40$2$37 Def000157
+S C$uarttimer0.c$31$3$36 Def0000D4
+S C$uarttimer0.c$16$3$33 Def000037
+S C$uarttimer0.c$41$2$37 Def00016F
+S C$uarttimer0.c$39$1$31 Def00013C
+S C$uarttimer0.c$32$3$36 Def0000D5
+S C$uarttimer0.c$19$2$32 Def00003D
+S C$uarttimer0.c$17$3$33 Def00003B
+S C$uarttimer0.c$29$2$32 Def0000BB
+S C$uarttimer0.c$25$3$35 Def00008E
+S C$uarttimer0.c$26$3$35 Def0000B6
+S C$uarttimer0.c$11$1$0 Def000007
+S C$uarttimer0.c$27$3$35 Def0000B8
+S G$uart_timer0_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
+R 00 00 00 16
+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 BE 02 00
+R 00 00 00 16
+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 90 00 00
+R 00 00 00 16 F1 23 07 01 F7 02 0E 00 3A
+T 00 01 01 E6 F0 08 E6 A3 F0 08 E6 A3 F0 08 E6 A3
+R 00 00 00 16
+T 00 01 0E F0 E5 00 00 00 24 FA F8 86 82 08 86 83
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 19 08 86 F0 08 E6 C0 07 12 00 00 AB 82 AC
+R 00 00 00 16 02 0B 01 6F
+T 00 01 26 83 AD F0 FE D0 07 E5 00 00 00 24 FA F8
+R 00 00 00 16 F1 23 0A 01 F7
+T 00 01 31 A6 03 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 3E
+R 00 00 00 16
+T 00 01 3E E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 49 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 56 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 61 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 6E F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 75
+R 00 00 00 16
+T 00 01 75 53 07 07 EF 4E F5 9A 75 99 04 E5
+R 00 00 00 16
+T 00 01 80 00 00 00 24 FA F8 86 9E 08 86 9F D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 8A 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer0
+F:G$uart_timer0_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer0.uart_timer0_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer0.uart_timer0_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer0.uart_timer0_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer0.uart_timer0_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer0.uart_timer0_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer1
+
+;!FILE libmflarge/uarttimer1.asm
+XH3
+H 1A areas 410 global symbols
+M uarttimer1
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 18C flags 20 addr 0
+S _uart_timer1_baud Def000000
+S C$uarttimer1.c$9$0$0 Def000000
+S XG$uart_timer1_baud$0$0 Def00018B
+S A$uarttimer1$1200 Def000014
+S A$uarttimer1$1300 Def00007C
+S A$uarttimer1$1210 Def00001E
+S A$uarttimer1$1201 Def000015
+S A$uarttimer1$1400 Def0000DC
+S A$uarttimer1$1310 Def000083
+S A$uarttimer1$1301 Def00007D
+S A$uarttimer1$1220 Def000029
+S A$uarttimer1$1202 Def000016
+S A$uarttimer1$1500 Def00015D
+S A$uarttimer1$1410 Def0000E8
+S A$uarttimer1$1401 Def0000DE
+S A$uarttimer1$1320 Def000090
+S A$uarttimer1$1311 Def000085
+S A$uarttimer1$1302 Def00007E
+S A$uarttimer1$1230 Def000033
+S A$uarttimer1$1221 Def00002A
+S A$uarttimer1$1510 Def000167
+S A$uarttimer1$1501 Def00015E
+S A$uarttimer1$1420 Def0000F2
+S A$uarttimer1$1411 Def0000E9
+S A$uarttimer1$1402 Def0000E0
+S A$uarttimer1$1330 Def00009C
+S A$uarttimer1$1321 Def000092
+S A$uarttimer1$1312 Def000087
+S A$uarttimer1$1240 Def00003B
+S A$uarttimer1$1231 Def000034
+S A$uarttimer1$1222 Def00002B
+S A$uarttimer1$1213 Def000020
+S A$uarttimer1$1520 Def00016F
+S A$uarttimer1$1511 Def000168
+S A$uarttimer1$1502 Def00015F
+S A$uarttimer1$1430 Def0000FD
+S A$uarttimer1$1421 Def0000F3
+S A$uarttimer1$1412 Def0000EA
+S A$uarttimer1$1403 Def0000E1
+S A$uarttimer1$1340 Def0000A6
+S A$uarttimer1$1331 Def00009D
+S A$uarttimer1$1322 Def000093
+S A$uarttimer1$1232 Def000035
+S A$uarttimer1$1223 Def00002C
+S A$uarttimer1$1214 Def000022
+S A$uarttimer1$1205 Def000017
+S A$uarttimer1$1530 Def00017A
+S A$uarttimer1$1521 Def000170
+S A$uarttimer1$1512 Def000169
+S A$uarttimer1$1503 Def000160
+S A$uarttimer1$1440 Def000109
+S A$uarttimer1$1431 Def0000FE
+S A$uarttimer1$1422 Def0000F4
+S A$uarttimer1$1413 Def0000EB
+S A$uarttimer1$1350 Def0000B1
+S A$uarttimer1$1341 Def0000A7
+S A$uarttimer1$1332 Def00009E
+S A$uarttimer1$1323 Def000094
+S A$uarttimer1$1314 Def000089
+S A$uarttimer1$1305 Def00007F
+S A$uarttimer1$1260 Def000051
+S A$uarttimer1$1251 Def000047
+S A$uarttimer1$1224 Def00002D
+S A$uarttimer1$1215 Def000024
+S A$uarttimer1$1206 Def000018
+S A$uarttimer1$1540 Def000186
+S A$uarttimer1$1522 Def000172
+S A$uarttimer1$1513 Def00016A
+S A$uarttimer1$1504 Def000161
+S A$uarttimer1$1450 Def000116
+S A$uarttimer1$1441 Def00010A
+S A$uarttimer1$1432 Def000101
+S A$uarttimer1$1423 Def0000F5
+S A$uarttimer1$1414 Def0000EC
+S A$uarttimer1$1405 Def0000E3
+S A$uarttimer1$1351 Def0000B2
+S A$uarttimer1$1342 Def0000A9
+S A$uarttimer1$1333 Def00009F
+S A$uarttimer1$1324 Def000096
+S A$uarttimer1$1270 Def00005D
+S A$uarttimer1$1261 Def000052
+S A$uarttimer1$1225 Def00002E
+S A$uarttimer1$1216 Def000025
+S A$uarttimer1$1207 Def000019
+S A$uarttimer1$1541 Def000187
+S A$uarttimer1$1523 Def000173
+S A$uarttimer1$1514 Def00016B
+S A$uarttimer1$1505 Def000162
+S A$uarttimer1$1460 Def000127
+S A$uarttimer1$1451 Def000117
+S A$uarttimer1$1442 Def00010B
+S A$uarttimer1$1433 Def000102
+S A$uarttimer1$1415 Def0000ED
+S A$uarttimer1$1406 Def0000E4
+S A$uarttimer1$1370 Def0000C1
+S A$uarttimer1$1361 Def0000B8
+S A$uarttimer1$1352 Def0000B3
+S A$uarttimer1$1343 Def0000AA
+S A$uarttimer1$1334 Def0000A0
+S A$uarttimer1$1325 Def000097
+S A$uarttimer1$1316 Def00008C
+S A$uarttimer1$1280 Def000068
+S A$uarttimer1$1271 Def00005E
+S A$uarttimer1$1262 Def000053
+S A$uarttimer1$1244 Def00003D
+S A$uarttimer1$1235 Def000037
+S A$uarttimer1$1226 Def00002F
+S A$uarttimer1$1217 Def000026
+S A$uarttimer1$1208 Def00001B
+S A$uarttimer1$1542 Def000189
+S A$uarttimer1$1533 Def00017C
+S A$uarttimer1$1515 Def00016C
+S A$uarttimer1$1506 Def000163
+S A$uarttimer1$1470 Def000137
+S A$uarttimer1$1461 Def000129
+S A$uarttimer1$1452 Def000119
+S A$uarttimer1$1443 Def00010C
+S A$uarttimer1$1434 Def000103
+S A$uarttimer1$1425 Def0000F6
+S A$uarttimer1$1416 Def0000EE
+S A$uarttimer1$1407 Def0000E5
+S A$uarttimer1$1380 Def0000CD
+S A$uarttimer1$1371 Def0000C3
+S A$uarttimer1$1353 Def0000B4
+S A$uarttimer1$1344 Def0000AB
+S A$uarttimer1$1335 Def0000A1
+S A$uarttimer1$1326 Def000098
+S A$uarttimer1$1290 Def000073
+S A$uarttimer1$1281 Def000069
+S A$uarttimer1$1272 Def00005F
+S A$uarttimer1$1263 Def000054
+S A$uarttimer1$1254 Def000049
+S A$uarttimer1$1245 Def00003E
+S A$uarttimer1$1236 Def000038
+S A$uarttimer1$1227 Def000030
+S A$uarttimer1$1218 Def000027
+S A$uarttimer1$1191 Def000009
+S A$uarttimer1$1182 Def000000
+S A$uarttimer1$1516 Def00016D
+S A$uarttimer1$1507 Def000164
+S A$uarttimer1$1480 Def000143
+S A$uarttimer1$1471 Def000139
+S A$uarttimer1$1462 Def00012A
+S A$uarttimer1$1453 Def00011A
+S A$uarttimer1$1444 Def00010D
+S A$uarttimer1$1435 Def000104
+S A$uarttimer1$1417 Def0000EF
+S A$uarttimer1$1408 Def0000E6
+S A$uarttimer1$1381 Def0000CE
+S A$uarttimer1$1372 Def0000C4
+S A$uarttimer1$1354 Def0000B5
+S A$uarttimer1$1345 Def0000AC
+S A$uarttimer1$1336 Def0000A2
+S A$uarttimer1$1327 Def000099
+S A$uarttimer1$1309 Def000082
+S A$uarttimer1$1291 Def000074
+S A$uarttimer1$1282 Def00006A
+S A$uarttimer1$1273 Def000060
+S A$uarttimer1$1264 Def000056
+S A$uarttimer1$1255 Def00004B
+S A$uarttimer1$1246 Def000040
+S A$uarttimer1$1237 Def00003A
+S A$uarttimer1$1228 Def000031
+S A$uarttimer1$1219 Def000028
+S A$uarttimer1$1192 Def00000A
+S A$uarttimer1$1183 Def000002
+S A$uarttimer1$1517 Def00016E
+S A$uarttimer1$1508 Def000165
+S A$uarttimer1$1490 Def000150
+S A$uarttimer1$1481 Def000144
+S A$uarttimer1$1472 Def00013A
+S A$uarttimer1$1463 Def00012C
+S A$uarttimer1$1454 Def00011C
+S A$uarttimer1$1445 Def00010E
+S A$uarttimer1$1436 Def000105
+S A$uarttimer1$1418 Def0000F0
+S A$uarttimer1$1409 Def0000E7
+S A$uarttimer1$1382 Def0000CF
+S A$uarttimer1$1373 Def0000C5
+S A$uarttimer1$1346 Def0000AD
+S A$uarttimer1$1337 Def0000A3
+S A$uarttimer1$1328 Def00009A
+S A$uarttimer1$1319 Def00008E
+S A$uarttimer1$1292 Def000075
+S A$uarttimer1$1283 Def00006B
+S A$uarttimer1$1274 Def000061
+S A$uarttimer1$1265 Def000057
+S A$uarttimer1$1256 Def00004D
+S A$uarttimer1$1247 Def000042
+S A$uarttimer1$1229 Def000032
+S A$uarttimer1$1193 Def00000C
+S A$uarttimer1$1184 Def000005
+S A$uarttimer1$1545 Def00018B
+S A$uarttimer1$1536 Def00017F
+S A$uarttimer1$1527 Def000175
+S A$uarttimer1$1509 Def000166
+S A$uarttimer1$1491 Def000152
+S A$uarttimer1$1482 Def000145
+S A$uarttimer1$1464 Def00012E
+S A$uarttimer1$1455 Def00011D
+S A$uarttimer1$1446 Def00010F
+S A$uarttimer1$1437 Def000106
+S A$uarttimer1$1428 Def0000F9
+S A$uarttimer1$1419 Def0000F1
+S A$uarttimer1$1392 Def0000D5
+S A$uarttimer1$1383 Def0000D0
+S A$uarttimer1$1374 Def0000C7
+S A$uarttimer1$1365 Def0000BB
+S A$uarttimer1$1347 Def0000AE
+S A$uarttimer1$1338 Def0000A4
+S A$uarttimer1$1329 Def00009B
+S A$uarttimer1$1293 Def000077
+S A$uarttimer1$1284 Def00006C
+S A$uarttimer1$1275 Def000062
+S A$uarttimer1$1266 Def000058
+S A$uarttimer1$1257 Def00004E
+S A$uarttimer1$1537 Def000181
+S A$uarttimer1$1528 Def000178
+S A$uarttimer1$1492 Def000153
+S A$uarttimer1$1483 Def000146
+S A$uarttimer1$1465 Def000130
+S A$uarttimer1$1456 Def00011E
+S A$uarttimer1$1447 Def000111
+S A$uarttimer1$1438 Def000107
+S A$uarttimer1$1429 Def0000FB
+S A$uarttimer1$1384 Def0000D1
+S A$uarttimer1$1375 Def0000C8
+S A$uarttimer1$1366 Def0000BC
+S A$uarttimer1$1357 Def0000B6
+S A$uarttimer1$1348 Def0000AF
+S A$uarttimer1$1339 Def0000A5
+S A$uarttimer1$1294 Def000078
+S A$uarttimer1$1285 Def00006D
+S A$uarttimer1$1276 Def000063
+S A$uarttimer1$1267 Def000059
+S A$uarttimer1$1258 Def00004F
+S A$uarttimer1$1249 Def000044
+S A$uarttimer1$1538 Def000183
+S A$uarttimer1$1529 Def000179
+S A$uarttimer1$1493 Def000155
+S A$uarttimer1$1484 Def000148
+S A$uarttimer1$1475 Def00013C
+S A$uarttimer1$1466 Def000131
+S A$uarttimer1$1457 Def000120
+S A$uarttimer1$1448 Def000113
+S A$uarttimer1$1439 Def000108
+S A$uarttimer1$1385 Def0000D2
+S A$uarttimer1$1376 Def0000C9
+S A$uarttimer1$1358 Def0000B7
+S A$uarttimer1$1349 Def0000B0
+S A$uarttimer1$1295 Def000079
+S A$uarttimer1$1286 Def00006E
+S A$uarttimer1$1277 Def000064
+S A$uarttimer1$1268 Def00005A
+S A$uarttimer1$1259 Def000050
+S A$uarttimer1$1187 Def000007
+S A$uarttimer1$1539 Def000184
+S A$uarttimer1$1485 Def000149
+S A$uarttimer1$1467 Def000133
+S A$uarttimer1$1458 Def000123
+S A$uarttimer1$1449 Def000114
+S A$uarttimer1$1386 Def0000D3
+S A$uarttimer1$1377 Def0000CA
+S A$uarttimer1$1296 Def00007A
+S A$uarttimer1$1287 Def000070
+S A$uarttimer1$1278 Def000065
+S A$uarttimer1$1269 Def00005B
+S A$uarttimer1$1197 Def00000F
+S A$uarttimer1$1486 Def00014A
+S A$uarttimer1$1477 Def00013E
+S A$uarttimer1$1468 Def000134
+S A$uarttimer1$1459 Def000125
+S A$uarttimer1$1378 Def0000CB
+S A$uarttimer1$1369 Def0000BF
+S A$uarttimer1$1288 Def000071
+S A$uarttimer1$1279 Def000067
+S A$uarttimer1$1198 Def000011
+S C$uarttimer1.c$12$1$31 Def000009
+S A$uarttimer1$1496 Def000157
+S A$uarttimer1$1487 Def00014C
+S A$uarttimer1$1478 Def000140
+S A$uarttimer1$1469 Def000136
+S A$uarttimer1$1379 Def0000CC
+S A$uarttimer1$1289 Def000072
+S A$uarttimer1$1199 Def000013
+S A$uarttimer1$1497 Def000159
+S A$uarttimer1$1488 Def00014D
+S A$uarttimer1$1479 Def000142
+S A$uarttimer1$1398 Def0000D8
+S A$uarttimer1$1389 Def0000D4
+S A$uarttimer1$1299 Def00007B
+S C$uarttimer1.c$13$2$31 Def00000F
+S A$uarttimer1$1498 Def00015B
+S A$uarttimer1$1489 Def00014E
+S A$uarttimer1$1399 Def0000DA
+S A$uarttimer1$1499 Def00015C
+S C$uarttimer1.c$43$1$31 Def000175
+S C$uarttimer1.c$34$1$31 Def0000D8
+S C$uarttimer1.c$20$3$34 Def000049
+S C$uarttimer1.c$14$2$32 Def000017
+S C$uarttimer1.c$44$1$31 Def00017C
+S C$uarttimer1.c$24$2$32 Def000082
+S C$uarttimer1.c$21$3$34 Def00007B
+S C$uarttimer1.c$45$1$31 Def00017F
+S C$uarttimer1.c$36$1$31 Def0000D8
+S C$uarttimer1.c$22$3$34 Def00007F
+S C$uarttimer1.c$46$1$31 Def00018B
+S C$uarttimer1.c$37$1$31 Def0000F9
+S C$uarttimer1.c$30$3$36 Def0000BF
+S C$uarttimer1.c$15$3$33 Def000020
+S C$uarttimer1.c$40$2$37 Def000157
+S C$uarttimer1.c$31$3$36 Def0000D4
+S C$uarttimer1.c$16$3$33 Def000037
+S C$uarttimer1.c$41$2$37 Def00016F
+S C$uarttimer1.c$39$1$31 Def00013C
+S C$uarttimer1.c$32$3$36 Def0000D5
+S C$uarttimer1.c$19$2$32 Def00003D
+S C$uarttimer1.c$17$3$33 Def00003B
+S C$uarttimer1.c$29$2$32 Def0000BB
+S C$uarttimer1.c$25$3$35 Def00008E
+S C$uarttimer1.c$26$3$35 Def0000B6
+S C$uarttimer1.c$11$1$0 Def000007
+S C$uarttimer1.c$27$3$35 Def0000B8
+S G$uart_timer1_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
+R 00 00 00 16
+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 BE 02 00
+R 00 00 00 16
+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 90 00 00
+R 00 00 00 16 F1 23 07 01 F7 02 0E 00 3A
+T 00 01 01 E6 F0 08 E6 A3 F0 08 E6 A3 F0 08 E6 A3
+R 00 00 00 16
+T 00 01 0E F0 E5 00 00 00 24 FA F8 86 82 08 86 83
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 19 08 86 F0 08 E6 C0 07 12 00 00 AB 82 AC
+R 00 00 00 16 02 0B 01 6F
+T 00 01 26 83 AD F0 FE D0 07 E5 00 00 00 24 FA F8
+R 00 00 00 16 F1 23 0A 01 F7
+T 00 01 31 A6 03 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 3E
+R 00 00 00 16
+T 00 01 3E E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 49 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 56 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 61 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 6E F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 75
+R 00 00 00 16
+T 00 01 75 53 07 07 EF 4E F5 A2 75 A1 04 E5
+R 00 00 00 16
+T 00 01 80 00 00 00 24 FA F8 86 A6 08 86 A7 D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 8A 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer1
+F:G$uart_timer1_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer1.uart_timer1_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer1.uart_timer1_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer1.uart_timer1_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer1.uart_timer1_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer1.uart_timer1_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uarttimer2
+
+;!FILE libmflarge/uarttimer2.asm
+XH3
+H 1A areas 410 global symbols
+M uarttimer2
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 18C flags 20 addr 0
+S _uart_timer2_baud Def000000
+S C$uarttimer2.c$9$0$0 Def000000
+S XG$uart_timer2_baud$0$0 Def00018B
+S A$uarttimer2$1200 Def000014
+S A$uarttimer2$1300 Def00007C
+S A$uarttimer2$1210 Def00001E
+S A$uarttimer2$1201 Def000015
+S A$uarttimer2$1400 Def0000DC
+S A$uarttimer2$1310 Def000083
+S A$uarttimer2$1301 Def00007D
+S A$uarttimer2$1220 Def000029
+S A$uarttimer2$1202 Def000016
+S A$uarttimer2$1500 Def00015D
+S A$uarttimer2$1410 Def0000E8
+S A$uarttimer2$1401 Def0000DE
+S A$uarttimer2$1320 Def000090
+S A$uarttimer2$1311 Def000085
+S A$uarttimer2$1302 Def00007E
+S A$uarttimer2$1230 Def000033
+S A$uarttimer2$1221 Def00002A
+S A$uarttimer2$1510 Def000167
+S A$uarttimer2$1501 Def00015E
+S A$uarttimer2$1420 Def0000F2
+S A$uarttimer2$1411 Def0000E9
+S A$uarttimer2$1402 Def0000E0
+S A$uarttimer2$1330 Def00009C
+S A$uarttimer2$1321 Def000092
+S A$uarttimer2$1312 Def000087
+S A$uarttimer2$1240 Def00003B
+S A$uarttimer2$1231 Def000034
+S A$uarttimer2$1222 Def00002B
+S A$uarttimer2$1213 Def000020
+S A$uarttimer2$1520 Def00016F
+S A$uarttimer2$1511 Def000168
+S A$uarttimer2$1502 Def00015F
+S A$uarttimer2$1430 Def0000FD
+S A$uarttimer2$1421 Def0000F3
+S A$uarttimer2$1412 Def0000EA
+S A$uarttimer2$1403 Def0000E1
+S A$uarttimer2$1340 Def0000A6
+S A$uarttimer2$1331 Def00009D
+S A$uarttimer2$1322 Def000093
+S A$uarttimer2$1232 Def000035
+S A$uarttimer2$1223 Def00002C
+S A$uarttimer2$1214 Def000022
+S A$uarttimer2$1205 Def000017
+S A$uarttimer2$1530 Def00017A
+S A$uarttimer2$1521 Def000170
+S A$uarttimer2$1512 Def000169
+S A$uarttimer2$1503 Def000160
+S A$uarttimer2$1440 Def000109
+S A$uarttimer2$1431 Def0000FE
+S A$uarttimer2$1422 Def0000F4
+S A$uarttimer2$1413 Def0000EB
+S A$uarttimer2$1350 Def0000B1
+S A$uarttimer2$1341 Def0000A7
+S A$uarttimer2$1332 Def00009E
+S A$uarttimer2$1323 Def000094
+S A$uarttimer2$1314 Def000089
+S A$uarttimer2$1305 Def00007F
+S A$uarttimer2$1260 Def000051
+S A$uarttimer2$1251 Def000047
+S A$uarttimer2$1224 Def00002D
+S A$uarttimer2$1215 Def000024
+S A$uarttimer2$1206 Def000018
+S A$uarttimer2$1540 Def000186
+S A$uarttimer2$1522 Def000172
+S A$uarttimer2$1513 Def00016A
+S A$uarttimer2$1504 Def000161
+S A$uarttimer2$1450 Def000116
+S A$uarttimer2$1441 Def00010A
+S A$uarttimer2$1432 Def000101
+S A$uarttimer2$1423 Def0000F5
+S A$uarttimer2$1414 Def0000EC
+S A$uarttimer2$1405 Def0000E3
+S A$uarttimer2$1351 Def0000B2
+S A$uarttimer2$1342 Def0000A9
+S A$uarttimer2$1333 Def00009F
+S A$uarttimer2$1324 Def000096
+S A$uarttimer2$1270 Def00005D
+S A$uarttimer2$1261 Def000052
+S A$uarttimer2$1225 Def00002E
+S A$uarttimer2$1216 Def000025
+S A$uarttimer2$1207 Def000019
+S A$uarttimer2$1541 Def000187
+S A$uarttimer2$1523 Def000173
+S A$uarttimer2$1514 Def00016B
+S A$uarttimer2$1505 Def000162
+S A$uarttimer2$1460 Def000127
+S A$uarttimer2$1451 Def000117
+S A$uarttimer2$1442 Def00010B
+S A$uarttimer2$1433 Def000102
+S A$uarttimer2$1415 Def0000ED
+S A$uarttimer2$1406 Def0000E4
+S A$uarttimer2$1370 Def0000C1
+S A$uarttimer2$1361 Def0000B8
+S A$uarttimer2$1352 Def0000B3
+S A$uarttimer2$1343 Def0000AA
+S A$uarttimer2$1334 Def0000A0
+S A$uarttimer2$1325 Def000097
+S A$uarttimer2$1316 Def00008C
+S A$uarttimer2$1280 Def000068
+S A$uarttimer2$1271 Def00005E
+S A$uarttimer2$1262 Def000053
+S A$uarttimer2$1244 Def00003D
+S A$uarttimer2$1235 Def000037
+S A$uarttimer2$1226 Def00002F
+S A$uarttimer2$1217 Def000026
+S A$uarttimer2$1208 Def00001B
+S A$uarttimer2$1542 Def000189
+S A$uarttimer2$1533 Def00017C
+S A$uarttimer2$1515 Def00016C
+S A$uarttimer2$1506 Def000163
+S A$uarttimer2$1470 Def000137
+S A$uarttimer2$1461 Def000129
+S A$uarttimer2$1452 Def000119
+S A$uarttimer2$1443 Def00010C
+S A$uarttimer2$1434 Def000103
+S A$uarttimer2$1425 Def0000F6
+S A$uarttimer2$1416 Def0000EE
+S A$uarttimer2$1407 Def0000E5
+S A$uarttimer2$1380 Def0000CD
+S A$uarttimer2$1371 Def0000C3
+S A$uarttimer2$1353 Def0000B4
+S A$uarttimer2$1344 Def0000AB
+S A$uarttimer2$1335 Def0000A1
+S A$uarttimer2$1326 Def000098
+S A$uarttimer2$1290 Def000073
+S A$uarttimer2$1281 Def000069
+S A$uarttimer2$1272 Def00005F
+S A$uarttimer2$1263 Def000054
+S A$uarttimer2$1254 Def000049
+S A$uarttimer2$1245 Def00003E
+S A$uarttimer2$1236 Def000038
+S A$uarttimer2$1227 Def000030
+S A$uarttimer2$1218 Def000027
+S A$uarttimer2$1191 Def000009
+S A$uarttimer2$1182 Def000000
+S A$uarttimer2$1516 Def00016D
+S A$uarttimer2$1507 Def000164
+S A$uarttimer2$1480 Def000143
+S A$uarttimer2$1471 Def000139
+S A$uarttimer2$1462 Def00012A
+S A$uarttimer2$1453 Def00011A
+S A$uarttimer2$1444 Def00010D
+S A$uarttimer2$1435 Def000104
+S A$uarttimer2$1417 Def0000EF
+S A$uarttimer2$1408 Def0000E6
+S A$uarttimer2$1381 Def0000CE
+S A$uarttimer2$1372 Def0000C4
+S A$uarttimer2$1354 Def0000B5
+S A$uarttimer2$1345 Def0000AC
+S A$uarttimer2$1336 Def0000A2
+S A$uarttimer2$1327 Def000099
+S A$uarttimer2$1309 Def000082
+S A$uarttimer2$1291 Def000074
+S A$uarttimer2$1282 Def00006A
+S A$uarttimer2$1273 Def000060
+S A$uarttimer2$1264 Def000056
+S A$uarttimer2$1255 Def00004B
+S A$uarttimer2$1246 Def000040
+S A$uarttimer2$1237 Def00003A
+S A$uarttimer2$1228 Def000031
+S A$uarttimer2$1219 Def000028
+S A$uarttimer2$1192 Def00000A
+S A$uarttimer2$1183 Def000002
+S A$uarttimer2$1517 Def00016E
+S A$uarttimer2$1508 Def000165
+S A$uarttimer2$1490 Def000150
+S A$uarttimer2$1481 Def000144
+S A$uarttimer2$1472 Def00013A
+S A$uarttimer2$1463 Def00012C
+S A$uarttimer2$1454 Def00011C
+S A$uarttimer2$1445 Def00010E
+S A$uarttimer2$1436 Def000105
+S A$uarttimer2$1418 Def0000F0
+S A$uarttimer2$1409 Def0000E7
+S A$uarttimer2$1382 Def0000CF
+S A$uarttimer2$1373 Def0000C5
+S A$uarttimer2$1346 Def0000AD
+S A$uarttimer2$1337 Def0000A3
+S A$uarttimer2$1328 Def00009A
+S A$uarttimer2$1319 Def00008E
+S A$uarttimer2$1292 Def000075
+S A$uarttimer2$1283 Def00006B
+S A$uarttimer2$1274 Def000061
+S A$uarttimer2$1265 Def000057
+S A$uarttimer2$1256 Def00004D
+S A$uarttimer2$1247 Def000042
+S A$uarttimer2$1229 Def000032
+S A$uarttimer2$1193 Def00000C
+S A$uarttimer2$1184 Def000005
+S A$uarttimer2$1545 Def00018B
+S A$uarttimer2$1536 Def00017F
+S A$uarttimer2$1527 Def000175
+S A$uarttimer2$1509 Def000166
+S A$uarttimer2$1491 Def000152
+S A$uarttimer2$1482 Def000145
+S A$uarttimer2$1464 Def00012E
+S A$uarttimer2$1455 Def00011D
+S A$uarttimer2$1446 Def00010F
+S A$uarttimer2$1437 Def000106
+S A$uarttimer2$1428 Def0000F9
+S A$uarttimer2$1419 Def0000F1
+S A$uarttimer2$1392 Def0000D5
+S A$uarttimer2$1383 Def0000D0
+S A$uarttimer2$1374 Def0000C7
+S A$uarttimer2$1365 Def0000BB
+S A$uarttimer2$1347 Def0000AE
+S A$uarttimer2$1338 Def0000A4
+S A$uarttimer2$1329 Def00009B
+S A$uarttimer2$1293 Def000077
+S A$uarttimer2$1284 Def00006C
+S A$uarttimer2$1275 Def000062
+S A$uarttimer2$1266 Def000058
+S A$uarttimer2$1257 Def00004E
+S A$uarttimer2$1537 Def000181
+S A$uarttimer2$1528 Def000178
+S A$uarttimer2$1492 Def000153
+S A$uarttimer2$1483 Def000146
+S A$uarttimer2$1465 Def000130
+S A$uarttimer2$1456 Def00011E
+S A$uarttimer2$1447 Def000111
+S A$uarttimer2$1438 Def000107
+S A$uarttimer2$1429 Def0000FB
+S A$uarttimer2$1384 Def0000D1
+S A$uarttimer2$1375 Def0000C8
+S A$uarttimer2$1366 Def0000BC
+S A$uarttimer2$1357 Def0000B6
+S A$uarttimer2$1348 Def0000AF
+S A$uarttimer2$1339 Def0000A5
+S A$uarttimer2$1294 Def000078
+S A$uarttimer2$1285 Def00006D
+S A$uarttimer2$1276 Def000063
+S A$uarttimer2$1267 Def000059
+S A$uarttimer2$1258 Def00004F
+S A$uarttimer2$1249 Def000044
+S A$uarttimer2$1538 Def000183
+S A$uarttimer2$1529 Def000179
+S A$uarttimer2$1493 Def000155
+S A$uarttimer2$1484 Def000148
+S A$uarttimer2$1475 Def00013C
+S A$uarttimer2$1466 Def000131
+S A$uarttimer2$1457 Def000120
+S A$uarttimer2$1448 Def000113
+S A$uarttimer2$1439 Def000108
+S A$uarttimer2$1385 Def0000D2
+S A$uarttimer2$1376 Def0000C9
+S A$uarttimer2$1358 Def0000B7
+S A$uarttimer2$1349 Def0000B0
+S A$uarttimer2$1295 Def000079
+S A$uarttimer2$1286 Def00006E
+S A$uarttimer2$1277 Def000064
+S A$uarttimer2$1268 Def00005A
+S A$uarttimer2$1259 Def000050
+S A$uarttimer2$1187 Def000007
+S A$uarttimer2$1539 Def000184
+S A$uarttimer2$1485 Def000149
+S A$uarttimer2$1467 Def000133
+S A$uarttimer2$1458 Def000123
+S A$uarttimer2$1449 Def000114
+S A$uarttimer2$1386 Def0000D3
+S A$uarttimer2$1377 Def0000CA
+S A$uarttimer2$1296 Def00007A
+S A$uarttimer2$1287 Def000070
+S A$uarttimer2$1278 Def000065
+S A$uarttimer2$1269 Def00005B
+S A$uarttimer2$1197 Def00000F
+S A$uarttimer2$1486 Def00014A
+S A$uarttimer2$1477 Def00013E
+S A$uarttimer2$1468 Def000134
+S A$uarttimer2$1459 Def000125
+S A$uarttimer2$1378 Def0000CB
+S A$uarttimer2$1369 Def0000BF
+S A$uarttimer2$1288 Def000071
+S A$uarttimer2$1279 Def000067
+S A$uarttimer2$1198 Def000011
+S C$uarttimer2.c$12$1$31 Def000009
+S A$uarttimer2$1496 Def000157
+S A$uarttimer2$1487 Def00014C
+S A$uarttimer2$1478 Def000140
+S A$uarttimer2$1469 Def000136
+S A$uarttimer2$1379 Def0000CC
+S A$uarttimer2$1289 Def000072
+S A$uarttimer2$1199 Def000013
+S A$uarttimer2$1497 Def000159
+S A$uarttimer2$1488 Def00014D
+S A$uarttimer2$1479 Def000142
+S A$uarttimer2$1398 Def0000D8
+S A$uarttimer2$1389 Def0000D4
+S A$uarttimer2$1299 Def00007B
+S C$uarttimer2.c$13$2$31 Def00000F
+S A$uarttimer2$1498 Def00015B
+S A$uarttimer2$1489 Def00014E
+S A$uarttimer2$1399 Def0000DA
+S A$uarttimer2$1499 Def00015C
+S C$uarttimer2.c$43$1$31 Def000175
+S C$uarttimer2.c$34$1$31 Def0000D8
+S C$uarttimer2.c$20$3$34 Def000049
+S C$uarttimer2.c$14$2$32 Def000017
+S C$uarttimer2.c$44$1$31 Def00017C
+S C$uarttimer2.c$24$2$32 Def000082
+S C$uarttimer2.c$21$3$34 Def00007B
+S C$uarttimer2.c$45$1$31 Def00017F
+S C$uarttimer2.c$36$1$31 Def0000D8
+S C$uarttimer2.c$22$3$34 Def00007F
+S C$uarttimer2.c$46$1$31 Def00018B
+S C$uarttimer2.c$37$1$31 Def0000F9
+S C$uarttimer2.c$30$3$36 Def0000BF
+S C$uarttimer2.c$15$3$33 Def000020
+S C$uarttimer2.c$40$2$37 Def000157
+S C$uarttimer2.c$31$3$36 Def0000D4
+S C$uarttimer2.c$16$3$33 Def000037
+S C$uarttimer2.c$41$2$37 Def00016F
+S C$uarttimer2.c$39$1$31 Def00013C
+S C$uarttimer2.c$32$3$36 Def0000D5
+S C$uarttimer2.c$19$2$32 Def00003D
+S C$uarttimer2.c$17$3$33 Def00003B
+S C$uarttimer2.c$29$2$32 Def0000BB
+S C$uarttimer2.c$25$3$35 Def00008E
+S C$uarttimer2.c$26$3$35 Def0000B6
+S C$uarttimer2.c$11$1$0 Def000007
+S C$uarttimer2.c$27$3$35 Def0000B8
+S G$uart_timer2_baud$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AF 82 7E 1A
+R 00 00 00 16 F1 23 04 01 F7 F1 23 09 01 F7
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EE 70 03 02 00 D8
+R 00 00 00 16 00 07 00 16
+T 00 00 0F
+R 00 00 00 16
+T 00 00 0F E5 00 00 00 24 FA F8 08 08 08 E6 FD 70
+R 00 00 00 16 F1 23 04 01 F7
+T 00 00 1A 22 BE 08 00
+R 00 00 00 16
+T 00 00 1E
+R 00 00 00 16
+T 00 00 1E 40 1D E5 00 00 00 24 FA F8 08 08 E6 08
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 29 F6 18 18 E6 08 F6 18 18 E6 08 F6 18 76
+R 00 00 00 16
+T 00 00 36 00 EE 24 F8 FE 80 CC
+R 00 00 00 16
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D ED 54 F0 60 02 80 3E
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 BE 04 00
+R 00 00 00 16
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 40 39 E5 00 00 00 24 FA F8 08 08 08 E6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 52 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 5F 08 F6 18 18 E6 C4 54 0F 08 46 F6 18 E6
+R 00 00 00 16
+T 00 00 6C 18 C4 54 F0 C6 C4 C6 66 C6 54 F0 C6 66
+R 00 00 00 16
+T 00 00 79 08 F6 1E 1E 1E 1E 02 00 09
+R 00 00 00 16 00 0A 00 16
+T 00 00 82
+R 00 00 00 16
+T 00 00 82 ED 54 C0 60 02 80 32
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 BE 02 00
+R 00 00 00 16
+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C 40 2D E5 00 00 00 24 FA F8 E6 25 E0 F6
+R 00 00 00 16 F1 23 06 01 F7
+T 00 00 97 08 E6 33 F6 08 E6 33 F6 08 E6 33 F6 18
+R 00 00 00 16
+T 00 00 A4 18 18 E6 25 E0 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 B1 F6 08 E6 33 F6 1E 1E 02 00 09
+R 00 00 00 16 00 0B 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB ED 20 E7 19 E5 00 00 00 24 FA F8 E6 25
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 C6 E0 F6 08 E6 33 F6 08 E6 33 F6 08 E6 33
+R 00 00 00 16
+T 00 00 D3 F6 1E 02 00 09
+R 00 00 00 16 00 06 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 8E F0 05 F0 E5 00 00 00 24 F6 F8 80 13
+R 00 00 00 16 F1 23 08 01 F7
+T 00 00 E3
+R 00 00 00 16
+T 00 00 E3 C3 08 08 08 E6 13 F6 18 E6 13 F6 18 E6
+R 00 00 00 16
+T 00 00 F0 13 F6 18 E6 13 F6
+R 00 00 00 16
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 D5 F0 EA E5 00 00 00 24 F6 F8 90 00 00
+R 00 00 00 16 F1 23 07 01 F7 02 0E 00 3A
+T 00 01 01 E6 F0 08 E6 A3 F0 08 E6 A3 F0 08 E6 A3
+R 00 00 00 16
+T 00 01 0E F0 E5 00 00 00 24 FA F8 86 82 08 86 83
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 19 08 86 F0 08 E6 C0 07 12 00 00 AB 82 AC
+R 00 00 00 16 02 0B 01 6F
+T 00 01 26 83 AD F0 FE D0 07 E5 00 00 00 24 FA F8
+R 00 00 00 16 F1 23 0A 01 F7
+T 00 01 31 A6 03 08 A6 04 08 A6 05 08 A6 06 7E 38
+R 00 00 00 16
+T 00 01 3E
+R 00 00 00 16
+T 00 01 3E E5 00 00 00 24 FA F8 C3 08 E6 94 40 08
+R 00 00 00 16 F1 23 04 01 F7
+T 00 01 49 E6 94 00 08 E6 94 00 40 23 EE 54 F0 60
+R 00 00 00 16
+T 00 01 56 1E E5 00 00 00 24 FA F8 08 08 08 E6 C3
+R 00 00 00 16 F1 23 05 01 F7
+T 00 01 61 13 F6 18 E6 13 F6 18 E6 13 F6 18 E6 13
+R 00 00 00 16
+T 00 01 6E F6 EE 24 F8 FE 80 C9
+R 00 00 00 16
+T 00 01 75
+R 00 00 00 16
+T 00 01 75 53 07 07 EF 4E F5 AA 75 A9 04 E5
+R 00 00 00 16
+T 00 01 80 00 00 00 24 FA F8 86 AE 08 86 AF D0
+R 00 00 00 16 F1 23 03 01 F7
+T 00 01 8A 00 00 00 22
+R 00 00 00 16 F1 23 03 01 F7
+
+
+M:uarttimer2
+F:G$uart_timer2_baud$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luarttimer2.uart_timer2_baud$baud$1$30({4}SL:U),B,1,-6
+S:Luarttimer2.uart_timer2_baud$clkfreq$1$30({4}SL:U),B,1,-10
+S:Luarttimer2.uart_timer2_baud$clksrc$1$30({1}SC:U),R,0,0,[r7]
+S:Luarttimer2.uart_timer2_baud$sh$1$31({1}SC:U),R,0,0,[r6]
+S:Luarttimer2.uart_timer2_baud$bdhi$2$32({1}SC:U),R,0,0,[r5]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0init
+
+;!FILE libmflarge/uart0init.asm
+XH3
+H 23 areas 45A global symbols
+M uart0init
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S _uart0_rxbuffer Ref000000
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S _uart0_txbuffer Ref000000
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
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+A RSEG1 size 0 flags 8 addr 0
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+S Fuart0init$uart0_fiforxrd$0$0 Def000001
+S Fuart0init$uart0_fifotxrd$0$0 Def000003
+S Fuart0init$uart0_fiforxwr$0$0 Def000000
+S Fuart0init$uart0_fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 3 flags 40 addr 0
+S Luart0init.uart0_init$timernr$1$101 Def000002
+S Luart0init.uart0_init$stop$1$101 Def000001
+S Luart0init.uart0_init$wl$1$101 Def000000
+S _uart0_init_PARM_2 Def000000
+S _uart0_init_PARM_3 Def000001
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$uart0init.c$148$1$68 Def000022
+S XG$uart0_irq$0$0 Def000022
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+S _uart0_poll Def000022
+S XFuart0init$dummy0$0$0 Def000000
+S G$uart0_irq$0$0 Def000000
+S A$uart0init$1240 Def000008
+S C$uart0init.c$101$1$63 Def000000
+S A$uart0init$1250 Def00001F
+S A$uart0init$1241 Def00000A
+S A$uart0init$1251 Def000021
+S A$uart0init$1242 Def00000C
+S A$uart0init$1270 Def000024
+S A$uart0init$1243 Def00000F
+S A$uart0init$1280 Def000036
+S A$uart0init$1271 Def000026
+S A$uart0init$1244 Def000012
+S C$uart0init.c$120$1$66 Def000000
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+S A$uart0init$1245 Def000015
+S A$uart0init$1236 Def000000
+S C$uart0init.c$121$1$66 Def000022
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+S A$uart0init$1246 Def000017
+S A$uart0init$1237 Def000002
+S _uart0_irq Def000000
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+S A$uart0init$1238 Def000004
+S C$uart0init.c$123$1$66 Def000022
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+S A$uart0init$1248 Def00001B
+S A$uart0init$1239 Def000006
+S A$uart0init$1276 Def000030
+S A$uart0init$1249 Def00001D
+S A$uart0init$1277 Def000031
+S A$uart0init$1278 Def000032
+S A$uart0init$1269 Def000022
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+A GSINIT5 size 0 flags 20 addr 0
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+S C$uart0init.c$466$1$98 Def00002C
+S C$uart0init.c$467$1$98 Def000043
+S C$uart0init.c$469$1$98 Def000043
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+S C$uart0init.c$96$1$63 Def000000
+S Fuart0init$dummy0$0$0 Def000000
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+S C$uart0init.c$1036$1$102 Def000059
+S G$uart0_init$0$0 Def000043
+S C$uart0init.c$1037$1$102 Def00007E
+S C$uart0init.c$1038$1$102 Def000081
+S C$uart0init.c$1039$1$102 Def000087
+S XG$uart0_rxbuffersize$0$0 Def000000
+S XG$uart0_txpokehex$0$0 Def00002C
+S XFuart0init$wtimer_cansleep_dummy$0$0 Def000043
+S _uart0_init Def000043
+S C$uart0init.c$484$1$100 Def000043
+S C$uart0init.c$485$1$100 Def000043
+S G$uart0_txidle$0$0 Def00002C
+S XG$uart0_init$0$0 Def000087
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+S A$uart0init$1900 Def00007E
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+S A$uart0init$1713 Def000003
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+S G$uart0_txbufptr$0$0 Def0000BB
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+S _uart0_rxbufptr Def000099
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+S _uart0_txbufptr Def0000BB
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+S XG$uart0_rxcount$0$0 Def000046
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+S _uart0_txbuffersize Def000046
+S XG$uart0_txbuffersize$0$0 Def00004D
+S G$uart0_txfreelinear$0$0 Def000000
+S G$uart0_rxcountlinear$0$0 Def000025
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+S G$uart0_rxcount$0$0 Def000035
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+
+
+M:uart0init
+F:Fuart0init$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart0_irq$0$0({2}DF,SV:S),Z,0,0,1,11,0
+F:G$uart0_poll$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart0init$uart0_iocore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$uart0_rxadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_rxadvance$idx$1$71({1}SC:U),R,0,0,[]
+F:G$uart0_txadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txadvance$idx$1$73({1}SC:U),R,0,0,[]
+F:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_rxbufptr$idx$1$75({1}SC:U),R,0,0,[]
+F:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_txbufptr$idx$1$77({1}SC:U),R,0,0,[]
+F:G$uart0_txfreelinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_txfree$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxcountlinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxcount$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_txbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart0_rxpeek$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0init.uart0_rxpeek$idx$1$91({1}SC:U),R,0,0,[]
+F:G$uart0_txpoke$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txpoke$ch$1$93({1}SC:U),B,1,-3
+S:Luart0init.uart0_txpoke$idx$1$93({1}SC:U),R,0,0,[]
+F:G$uart0_txpokehex$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0init.uart0_txpokehex$ch$1$95({1}SC:U),B,1,-3
+S:Luart0init.uart0_txpokehex$idx$1$95({1}SC:U),R,0,0,[]
+F:G$uart0_txidle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart0init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart0_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart0init$uart0_fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart0init$uart0_fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart0_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart0_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:Luart0init.uart0_init$wl$1$101({1}SC:U),F,0,0
+S:Luart0init.uart0_init$stop$1$101({1}SC:U),F,0,0
+S:Luart0init.uart0_init$timernr$1$101({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0init$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fuart0init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1init
+
+;!FILE libmflarge/uart1init.asm
+XH3
+H 23 areas 45A global symbols
+M uart1init
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S _uart1_rxbuffer Ref000000
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S _uart1_txbuffer Ref000000
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart1init$uart1_fiforxrd$0$0 Def000001
+S Fuart1init$uart1_fifotxrd$0$0 Def000003
+S Fuart1init$uart1_fiforxwr$0$0 Def000000
+S Fuart1init$uart1_fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 3 flags 40 addr 0
+S _uart1_init_PARM_3 Def000001
+S Luart1init.uart1_init$timernr$1$101 Def000002
+S Luart1init.uart1_init$stop$1$101 Def000001
+S Luart1init.uart1_init$wl$1$101 Def000000
+S _uart1_init_PARM_2 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 37 flags 20 addr 0
+S C$uart1init.c$148$1$68 Def000022
+S XG$uart1_irq$0$0 Def000022
+S C$uart1init.c$97$1$63 Def000000
+S G$uart1_poll$0$0 Def000022
+S _uart1_poll Def000022
+S XFuart1init$dummy0$0$0 Def000000
+S G$uart1_irq$0$0 Def000000
+S A$uart1init$1240 Def000008
+S C$uart1init.c$101$1$63 Def000000
+S A$uart1init$1250 Def00001F
+S A$uart1init$1241 Def00000A
+S A$uart1init$1251 Def000021
+S A$uart1init$1242 Def00000C
+S A$uart1init$1270 Def000024
+S A$uart1init$1243 Def00000F
+S A$uart1init$1280 Def000036
+S A$uart1init$1271 Def000026
+S A$uart1init$1244 Def000012
+S C$uart1init.c$120$1$66 Def000000
+S A$uart1init$1272 Def000027
+S A$uart1init$1245 Def000015
+S A$uart1init$1236 Def000000
+S C$uart1init.c$121$1$66 Def000022
+S A$uart1init$1273 Def000029
+S A$uart1init$1246 Def000017
+S A$uart1init$1237 Def000002
+S _uart1_irq Def000000
+S A$uart1init$1274 Def00002B
+S A$uart1init$1247 Def000019
+S A$uart1init$1238 Def000004
+S C$uart1init.c$123$1$66 Def000022
+S A$uart1init$1275 Def00002E
+S A$uart1init$1248 Def00001B
+S A$uart1init$1239 Def000006
+S A$uart1init$1276 Def000030
+S A$uart1init$1249 Def00001D
+S A$uart1init$1277 Def000031
+S A$uart1init$1278 Def000032
+S A$uart1init$1269 Def000022
+S A$uart1init$1279 Def000034
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 88 flags 20 addr 0
+S A$uart1init$1894 Def000077
+S A$uart1init$1885 Def00006D
+S A$uart1init$1876 Def00005B
+S A$uart1init$1777 Def000028
+S A$uart1init$1768 Def00001A
+S Fuart1init$wtimer_cansleep_dummy$0$0 Def000043
+S C$uart1init.c$452$1$96 Def00002C
+S A$uart1init$1895 Def000079
+S A$uart1init$1886 Def00006E
+S A$uart1init$1877 Def00005D
+S A$uart1init$1868 Def00004D
+S A$uart1init$1796 Def00002C
+S A$uart1init$1778 Def000029
+S A$uart1init$1769 Def00001C
+S XG$uart1_txidle$0$0 Def000043
+S A$uart1init$1896 Def00007A
+S A$uart1init$1887 Def00006F
+S A$uart1init$1878 Def00005E
+S A$uart1init$1869 Def000050
+S A$uart1init$1797 Def00002E
+S C$uart1init.c$429$1$94 Def000007
+S A$uart1init$1897 Def00007C
+S A$uart1init$1879 Def000061
+S A$uart1init$1798 Def000031
+S A$uart1init$1889 Def000072
+S A$uart1init$1799 Def000033
+S C$uart1init.c$449$1$96 Def000016
+S XG$uart1_rxpeek$0$0 Def000007
+S _uart1_txpoke Def000007
+S C$uart1init.c$466$1$98 Def00002C
+S C$uart1init.c$467$1$98 Def000043
+S C$uart1init.c$469$1$98 Def000043
+S _uart1_txpokehex Def000016
+S C$uart1init.c$1033$1$100 Def000043
+S C$uart1init.c$96$1$63 Def000000
+S Fuart1init$dummy0$0$0 Def000000
+S C$uart1init.c$84$0$0 Def000000
+S C$uart1init.c$1035$1$102 Def00004D
+S XG$uart1_txpoke$0$0 Def000016
+S C$uart1init.c$1036$1$102 Def000059
+S G$uart1_init$0$0 Def000043
+S C$uart1init.c$1037$1$102 Def00007E
+S C$uart1init.c$1038$1$102 Def000081
+S C$uart1init.c$1039$1$102 Def000087
+S XG$uart1_rxbuffersize$0$0 Def000000
+S XG$uart1_txpokehex$0$0 Def00002C
+S XFuart1init$wtimer_cansleep_dummy$0$0 Def000043
+S _uart1_init Def000043
+S C$uart1init.c$484$1$100 Def000043
+S C$uart1init.c$485$1$100 Def000043
+S G$uart1_txidle$0$0 Def00002C
+S XG$uart1_init$0$0 Def000087
+S G$uart1_rxpeek$0$0 Def000000
+S A$uart1init$1800 Def000035
+S A$uart1init$1900 Def00007E
+S A$uart1init$1801 Def000037
+S C$uart1init.c$401$1$90 Def000000
+S A$uart1init$1802 Def000039
+S A$uart1init$1712 Def000000
+S _uart1_txidle Def00002C
+S A$uart1init$1713 Def000003
+S C$uart1init.c$403$1$90 Def000000
+S A$uart1init$1903 Def000081
+S A$uart1init$1804 Def00003B
+S A$uart1init$1741 Def00000E
+S A$uart1init$1714 Def000004
+S C$uart1init.c$411$1$92 Def000000
+S A$uart1init$1904 Def000083
+S A$uart1init$1805 Def00003E
+S A$uart1init$1742 Def000011
+S A$uart1init$1715 Def000006
+S C$uart1init.c$412$1$92 Def000007
+S A$uart1init$1905 Def000085
+S A$uart1init$1770 Def00001D
+S A$uart1init$1743 Def000012
+S A$uart1init$1870 Def000053
+S A$uart1init$1861 Def000043
+S A$uart1init$1807 Def00003F
+S A$uart1init$1771 Def00001E
+S A$uart1init$1744 Def000013
+S C$uart1init.c$430$1$94 Def000016
+S C$uart1init.c$414$1$92 Def000007
+S G$uart1_txpoke$0$0 Def000007
+S _uart1_rxpeek Def000000
+S A$uart1init$1880 Def000062
+S A$uart1init$1871 Def000056
+S A$uart1init$1862 Def000045
+S A$uart1init$1808 Def000042
+S A$uart1init$1772 Def000020
+S A$uart1init$1745 Def000015
+S A$uart1init$1736 Def000007
+S A$uart1init$1908 Def000087
+S A$uart1init$1890 Def000073
+S A$uart1init$1881 Def000064
+S A$uart1init$1863 Def000047
+S A$uart1init$1773 Def000022
+S A$uart1init$1737 Def000009
+S C$uart1init.c$432$1$94 Def000016
+S A$uart1init$1891 Def000074
+S A$uart1init$1882 Def000066
+S A$uart1init$1864 Def000049
+S A$uart1init$1774 Def000024
+S A$uart1init$1738 Def00000B
+S A$uart1init$1892 Def000075
+S A$uart1init$1883 Def000068
+S A$uart1init$1874 Def000059
+S A$uart1init$1865 Def00004C
+S A$uart1init$1766 Def000016
+S A$uart1init$1739 Def00000D
+S C$uart1init.c$450$1$96 Def00002C
+S A$uart1init$1893 Def000076
+S A$uart1init$1884 Def00006A
+S A$uart1init$1875 Def00005A
+S A$uart1init$1776 Def000026
+S A$uart1init$1767 Def000018
+S G$uart1_txpokehex$0$0 Def000016
+A UART1S0 size DD flags 20 addr 0
+S A$uart1init$1399 Def000070
+S Fuart1init$uart1_iocore$0$0 Def000000
+S C$uart1init.c$309$1$78 Def0000BB
+S C$uart1init.c$284$1$76 Def0000BB
+S C$uart1init.c$259$1$74 Def000099
+S C$uart1init.c$149$1$68 Def000000
+S XFuart1init$uart1_iocore$0$0 Def00005F
+S G$uart1_rxadvance$0$0 Def00005F
+S G$uart1_rxbufptr$0$0 Def000099
+S G$uart1_txadvance$0$0 Def00007C
+S G$uart1_txbufptr$0$0 Def0000BB
+S _uart1_rxadvance Def00005F
+S _uart1_rxbufptr Def000099
+S _uart1_txadvance Def00007C
+S _uart1_txbufptr Def0000BB
+S XG$uart1_poll$0$0 Def000000
+S A$uart1init$1400 Def000072
+S A$uart1init$1401 Def000074
+S A$uart1init$1320 Def00000E
+S A$uart1init$1510 Def0000C4
+S A$uart1init$1321 Def00000F
+S A$uart1init$1520 Def0000D5
+S A$uart1init$1511 Def0000C6
+S A$uart1init$1430 Def000081
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+S A$uart1init$1331 Def00001D
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+S C$uart1init.c$212$1$70 Def000000
+S A$uart1init$1521 Def0000D7
+S A$uart1init$1431 Def000083
+S A$uart1init$1404 Def000078
+S A$uart1init$1350 Def000043
+S A$uart1init$1341 Def00002F
+S A$uart1init$1332 Def000020
+S A$uart1init$1323 Def000013
+S A$uart1init$1314 Def000000
+S XG$uart1_rxadvance$0$0 Def00007C
+S C$uart1init.c$213$1$70 Def00005F
+S A$uart1init$1522 Def0000D8
+S A$uart1init$1513 Def0000C8
+S A$uart1init$1504 Def0000BB
+S A$uart1init$1441 Def000093
+S A$uart1init$1432 Def000085
+S A$uart1init$1360 Def000052
+S A$uart1init$1351 Def000045
+S A$uart1init$1342 Def000031
+S A$uart1init$1333 Def000023
+S A$uart1init$1324 Def000015
+S A$uart1init$1315 Def000002
+S XG$uart1_rxbufptr$0$0 Def0000BB
+S A$uart1init$1523 Def0000DA
+S A$uart1init$1514 Def0000CA
+S A$uart1init$1505 Def0000BD
+S A$uart1init$1442 Def000095
+S A$uart1init$1433 Def000087
+S A$uart1init$1406 Def00007B
+S A$uart1init$1361 Def000054
+S A$uart1init$1352 Def000046
+S A$uart1init$1343 Def000034
+S A$uart1init$1316 Def000005
+S XG$uart1_txadvance$0$0 Def000099
+S C$uart1init.c$215$1$70 Def00005F
+S A$uart1init$1524 Def0000DC
+S A$uart1init$1515 Def0000CC
+S A$uart1init$1470 Def0000A2
+S A$uart1init$1434 Def000089
+S A$uart1init$1362 Def000056
+S A$uart1init$1353 Def000048
+S A$uart1init$1344 Def000036
+S A$uart1init$1335 Def000025
+S A$uart1init$1326 Def000016
+S A$uart1init$1317 Def000008
+S A$uart1init$1516 Def0000CE
+S A$uart1init$1507 Def0000BE
+S A$uart1init$1480 Def0000B3
+S A$uart1init$1471 Def0000A4
+S A$uart1init$1444 Def000098
+S A$uart1init$1426 Def00007C
+S A$uart1init$1354 Def00004A
+S A$uart1init$1345 Def000039
+S A$uart1init$1336 Def000027
+S A$uart1init$1327 Def000018
+S A$uart1init$1318 Def00000A
+S A$uart1init$1508 Def0000C0
+S A$uart1init$1481 Def0000B5
+S A$uart1init$1436 Def00008B
+S A$uart1init$1427 Def00007E
+S A$uart1init$1391 Def000062
+S A$uart1init$1364 Def000057
+S A$uart1init$1355 Def00004B
+S A$uart1init$1346 Def00003C
+S A$uart1init$1337 Def000029
+S A$uart1init$1328 Def00001A
+S A$uart1init$1319 Def00000C
+S C$uart1init.c$234$1$72 Def00005F
+S A$uart1init$1518 Def0000D0
+S A$uart1init$1509 Def0000C2
+S A$uart1init$1482 Def0000B6
+S A$uart1init$1473 Def0000A6
+S A$uart1init$1464 Def000099
+S A$uart1init$1437 Def00008D
+S A$uart1init$1392 Def000064
+S A$uart1init$1365 Def000059
+S A$uart1init$1356 Def00004D
+S A$uart1init$1338 Def00002A
+S A$uart1init$1329 Def00001C
+S C$uart1init.c$235$1$72 Def00007C
+S A$uart1init$1519 Def0000D3
+S A$uart1init$1483 Def0000B8
+S A$uart1init$1474 Def0000A8
+S A$uart1init$1465 Def00009B
+S A$uart1init$1438 Def00008F
+S A$uart1init$1429 Def00007F
+S A$uart1init$1393 Def000066
+S A$uart1init$1366 Def00005C
+S A$uart1init$1357 Def00004F
+S A$uart1init$1348 Def00003E
+S A$uart1init$1339 Def00002D
+S A$uart1init$1484 Def0000BA
+S A$uart1init$1475 Def0000AA
+S A$uart1init$1439 Def000091
+S A$uart1init$1394 Def000068
+S A$uart1init$1349 Def000041
+S C$uart1init.c$237$1$72 Def00007C
+S C$uart1init.c$151$1$68 Def000000
+S A$uart1init$1476 Def0000AC
+S A$uart1init$1467 Def00009C
+S A$uart1init$1395 Def00006A
+S A$uart1init$1368 Def00005E
+S A$uart1init$1359 Def000050
+S A$uart1init$1468 Def00009E
+S A$uart1init$1396 Def00006C
+S A$uart1init$1478 Def0000AE
+S A$uart1init$1469 Def0000A0
+S A$uart1init$1388 Def00005F
+S C$uart1init.c$281$1$76 Def000099
+S C$uart1init.c$256$1$74 Def00007C
+S A$uart1init$1479 Def0000B1
+S A$uart1init$1398 Def00006E
+S A$uart1init$1389 Def000061
+S C$uart1init.c$282$1$76 Def0000BB
+S C$uart1init.c$257$1$74 Def000099
+A UART1S1 size 0 flags 20 addr 0
+A UART1S2 size 0 flags 20 addr 0
+A UART1S3 size 54 flags 20 addr 0
+S A$uart1init$1579 Def00001B
+S G$uart1_txbuffersize$0$0 Def000046
+S XG$uart1_txfreelinear$0$0 Def000014
+S A$uart1init$1688 Def000050
+S A$uart1init$1689 Def000051
+S C$uart1init.c$375$1$86 Def000035
+S C$uart1init.c$359$1$84 Def000025
+S C$uart1init.c$376$1$86 Def000046
+S XG$uart1_rxcountlinear$0$0 Def000035
+S XG$uart1_txfree$0$0 Def000025
+S C$uart1init.c$378$1$86 Def000046
+S C$uart1init.c$386$1$88 Def000046
+S C$uart1init.c$387$1$88 Def00004D
+S C$uart1init.c$389$1$88 Def00004D
+S XG$uart1_rxcount$0$0 Def000046
+S _uart1_rxbuffersize Def00004D
+S _uart1_txbuffersize Def000046
+S XG$uart1_txbuffersize$0$0 Def00004D
+S G$uart1_txfreelinear$0$0 Def000000
+S G$uart1_rxcountlinear$0$0 Def000025
+S G$uart1_txfree$0$0 Def000014
+S G$uart1_rxcount$0$0 Def000035
+S A$uart1init$1611 Def00002F
+S C$uart1init.c$400$1$90 Def00004D
+S A$uart1init$1612 Def000030
+S C$uart1init.c$330$1$80 Def000014
+S _uart1_txfreelinear Def000000
+S A$uart1init$1604 Def000025
+S A$uart1init$1550 Def00000B
+S A$uart1init$1641 Def000041
+S A$uart1init$1614 Def000032
+S A$uart1init$1605 Def000027
+S A$uart1init$1551 Def00000C
+S XG$uart1_txbufptr$0$0 Def000000
+S A$uart1init$1642 Def000043
+S A$uart1init$1633 Def000035
+S A$uart1init$1615 Def000034
+S A$uart1init$1606 Def000028
+S A$uart1init$1552 Def00000E
+S A$uart1init$1634 Def000037
+S A$uart1init$1607 Def00002A
+S A$uart1init$1580 Def00001D
+S A$uart1init$1544 Def000000
+S A$uart1init$1662 Def000046
+S A$uart1init$1644 Def000045
+S A$uart1init$1635 Def000038
+S A$uart1init$1608 Def00002C
+S A$uart1init$1581 Def00001F
+S A$uart1init$1554 Def00000F
+S A$uart1init$1545 Def000002
+S C$uart1init.c$310$1$78 Def000000
+S _uart1_rxcountlinear Def000025
+S _uart1_txfree Def000014
+S A$uart1init$1690 Def000053
+S A$uart1init$1663 Def000048
+S A$uart1init$1636 Def00003A
+S A$uart1init$1609 Def00002E
+S A$uart1init$1546 Def000003
+S C$uart1init.c$343$1$82 Def000014
+S C$uart1init.c$327$1$80 Def000000
+S A$uart1init$1637 Def00003C
+S A$uart1init$1583 Def000020
+S A$uart1init$1556 Def000011
+S A$uart1init$1547 Def000005
+S C$uart1init.c$360$1$84 Def000035
+S C$uart1init.c$344$1$82 Def000025
+S C$uart1init.c$328$1$80 Def000014
+S C$uart1init.c$312$1$78 Def000000
+S A$uart1init$1665 Def000049
+S A$uart1init$1638 Def00003E
+S A$uart1init$1584 Def000022
+S A$uart1init$1575 Def000014
+S A$uart1init$1557 Def000013
+S A$uart1init$1548 Def000007
+S A$uart1init$1666 Def00004A
+S A$uart1init$1639 Def000040
+S A$uart1init$1576 Def000016
+S A$uart1init$1549 Def000009
+S C$uart1init.c$362$1$84 Def000035
+S C$uart1init.c$346$1$82 Def000025
+S A$uart1init$1685 Def00004D
+S A$uart1init$1667 Def00004C
+S A$uart1init$1586 Def000024
+S A$uart1init$1577 Def000017
+S G$uart1_rxbuffersize$0$0 Def00004D
+S _uart1_rxcount Def000035
+S A$uart1init$1686 Def00004F
+S A$uart1init$1578 Def000019
+A UART1S4 size 0 flags 20 addr 0
+A UART1S5 size 0 flags 20 addr 0
+A WTCANSLP0 size 0 flags 20 addr 0
+A WTCANSLP1 size 8 flags 20 addr 0
+S A$uart1init$1830 Def000000
+S A$uart1init$1831 Def000003
+S A$uart1init$1832 Def000005
+S A$uart1init$1833 Def000007
+A WTCANSLP2 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
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+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 7F EC 07 D2 9D D0 06 D0 07 22
+R 00 00 00 16
+
+
+M:uart1init
+F:Fuart1init$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart1_irq$0$0({2}DF,SV:S),Z,0,0,1,12,0
+F:G$uart1_poll$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart1init$uart1_iocore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$uart1_rxadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_rxadvance$idx$1$71({1}SC:U),R,0,0,[]
+F:G$uart1_txadvance$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txadvance$idx$1$73({1}SC:U),R,0,0,[]
+F:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_rxbufptr$idx$1$75({1}SC:U),R,0,0,[]
+F:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_txbufptr$idx$1$77({1}SC:U),R,0,0,[]
+F:G$uart1_txfreelinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_txfree$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxcountlinear$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxcount$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_txbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxbuffersize$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$uart1_rxpeek$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1init.uart1_rxpeek$idx$1$91({1}SC:U),R,0,0,[]
+F:G$uart1_txpoke$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txpoke$ch$1$93({1}SC:U),B,1,-3
+S:Luart1init.uart1_txpoke$idx$1$93({1}SC:U),R,0,0,[]
+F:G$uart1_txpokehex$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1init.uart1_txpokehex$ch$1$95({1}SC:U),B,1,-3
+S:Luart1init.uart1_txpokehex$idx$1$95({1}SC:U),R,0,0,[]
+F:G$uart1_txidle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:Fuart1init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$uart1_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart1init$uart1_fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart1init$uart1_fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart1_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart1_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:Luart1init.uart1_init$wl$1$101({1}SC:U),F,0,0
+S:Luart1init.uart1_init$stop$1$101({1}SC:U),F,0,0
+S:Luart1init.uart1_init$timernr$1$101({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
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+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1init$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fuart1init$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0stop
+
+;!FILE libmflarge/uart0stop.asm
+XH3
+H 1A areas 2D9 global symbols
+M uart0stop
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart0stop$fiforxrd$0$0 Def000001
+S Fuart0stop$fifotxrd$0$0 Def000003
+S Fuart0stop$fiforxwr$0$0 Def000000
+S Fuart0stop$fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 9 flags 20 addr 0
+S A$uart0stop$1190 Def000000
+S A$uart0stop$1193 Def000002
+S A$uart0stop$1196 Def000005
+S A$uart0stop$1199 Def000008
+S C$uart0stop.c$76$1$63 Def000000
+S C$uart0stop.c$77$1$63 Def000002
+S C$uart0stop.c$78$1$63 Def000005
+S C$uart0stop.c$79$1$63 Def000008
+S C$uart0stop.c$74$0$0 Def000000
+S G$uart0_stop$0$0 Def000000
+S _uart0_stop Def000000
+S XG$uart0_stop$0$0 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 9C 75 E7 00 75 E4 00 22
+R 00 00 00 16
+
+
+M:uart0stop
+F:G$uart0_stop$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart0stop$fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart0stop$fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart0_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart0_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1stop
+
+;!FILE libmflarge/uart1stop.asm
+XH3
+H 1A areas 2D9 global symbols
+M uart1stop
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 4 flags 0 addr 0
+S Fuart1stop$fiforxrd$0$0 Def000001
+S Fuart1stop$fifotxrd$0$0 Def000003
+S Fuart1stop$fiforxwr$0$0 Def000000
+S Fuart1stop$fifotxwr$0$0 Def000002
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 9 flags 20 addr 0
+S A$uart1stop$1190 Def000000
+S A$uart1stop$1193 Def000002
+S A$uart1stop$1196 Def000005
+S A$uart1stop$1199 Def000008
+S C$uart1stop.c$76$1$63 Def000000
+S C$uart1stop.c$77$1$63 Def000002
+S C$uart1stop.c$78$1$63 Def000005
+S C$uart1stop.c$79$1$63 Def000008
+S C$uart1stop.c$74$0$0 Def000000
+S G$uart1_stop$0$0 Def000000
+S _uart1_stop Def000000
+S XG$uart1_stop$0$0 Def000008
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 01
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 02
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 03
+R 00 00 00 05
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C2 9D 75 EF 00 75 EC 00 22
+R 00 00 00 16
+
+
+M:uart1stop
+F:G$uart1_stop$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Fuart1stop$fiforxwr$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fiforxrd$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fifotxwr$0$0({1}SC:U),E,0,0
+S:Fuart1stop$fifotxrd$0$0({1}SC:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$uart1_rxbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$uart1_txbuffer$0$0({0}DA0d,SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer0_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer1_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart_timer2_baud$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0txbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart0txbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart0_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart0txbuf.c$5$1$60 Def000000
+S C$uart0txbuf.c$5$0$0 Def000000
+S Fuart0txbuf$uart0_define_txbuffer$0$0 Def000000
+S XFuart0txbuf$uart0_define_txbuffer$0$0 Def000000
+A UART0S0 size 0 flags 20 addr 0
+A UART0S1 size 2 flags 20 addr 0
+A UART0S2 size 0 flags 20 addr 0
+A UART0S3 size 0 flags 20 addr 0
+A UART0S4 size 1 flags 20 addr 0
+A UART0S5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:uart0txbuf
+F:Fuart0txbuf$uart0_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0txbuf$uart0_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1txbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart1txbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart1_txbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart1txbuf.c$5$1$60 Def000000
+S C$uart1txbuf.c$5$0$0 Def000000
+S Fuart1txbuf$uart1_define_txbuffer$0$0 Def000000
+S XFuart1txbuf$uart1_define_txbuffer$0$0 Def000000
+A UART1S0 size 0 flags 20 addr 0
+A UART1S1 size 2 flags 20 addr 0
+A UART1S2 size 0 flags 20 addr 0
+A UART1S3 size 0 flags 20 addr 0
+A UART1S4 size 1 flags 20 addr 0
+A UART1S5 size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 18
+T 00 00 00 40
+R 00 00 00 1B
+
+
+M:uart1txbuf
+F:Fuart1txbuf$uart1_define_txbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1txbuf$uart1_define_txbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0rxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart0rxbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart0_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart0rxbuf.c$5$1$60 Def000000
+S C$uart0rxbuf.c$5$0$0 Def000000
+S Fuart0rxbuf$uart0_define_rxbuffer$0$0 Def000000
+S XFuart0rxbuf$uart0_define_rxbuffer$0$0 Def000000
+A UART0S0 size 0 flags 20 addr 0
+A UART0S1 size 0 flags 20 addr 0
+A UART0S2 size 2 flags 20 addr 0
+A UART0S3 size 0 flags 20 addr 0
+A UART0S4 size 0 flags 20 addr 0
+A UART0S5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:uart0rxbuf
+F:Fuart0rxbuf$uart0_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
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+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart0rxbuf$uart0_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1rxbuf
+
+XH3
+H 20 areas 2CE global symbols
+M uart1rxbuf
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 40 flags 40 addr 0
+S _uart1_rxbuffer Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+S C$uart1rxbuf.c$5$1$60 Def000000
+S C$uart1rxbuf.c$5$0$0 Def000000
+S Fuart1rxbuf$uart1_define_rxbuffer$0$0 Def000000
+S XFuart1rxbuf$uart1_define_rxbuffer$0$0 Def000000
+A UART1S0 size 0 flags 20 addr 0
+A UART1S1 size 0 flags 20 addr 0
+A UART1S2 size 2 flags 20 addr 0
+A UART1S3 size 0 flags 20 addr 0
+A UART1S4 size 0 flags 20 addr 0
+A UART1S5 size 1 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00 C0 C1
+R 00 00 00 19
+T 00 00 00 40
+R 00 00 00 1C
+
+
+M:uart1rxbuf
+F:Fuart1rxbuf$uart1_define_rxbuffer$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+S:Fuart1rxbuf$uart1_define_rxbuffer$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0tx
+
+;!FILE libmflarge/uart0tx.asm
+XH3
+H 1A areas 327 global symbols
+M uart0tx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S _uart0_txpoke Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _uart0_poll Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S _uart0_txadvance Ref000000
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _uart0_txidle Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _uart0_txfree Ref000000
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$uart0tx.c$29$2$61 Def00000F
+S G$uart0_wait_txfree$0$0 Def000000
+S C$uart0tx.c$45$2$64 Def000040
+S C$uart0tx.c$54$1$66 Def000057
+S C$uart0tx.c$46$2$64 Def000047
+S C$uart0tx.c$24$0$0 Def000000
+S C$uart0tx.c$55$1$66 Def00005D
+S C$uart0tx.c$47$2$64 Def00004A
+S C$uart0tx.c$49$1$63 Def00004F
+S C$uart0tx.c$56$1$66 Def000067
+S G$uart0_wait_txdone$0$0 Def000032
+S C$uart0tx.c$57$1$66 Def00006F
+S G$uart0_tx$0$0 Def000053
+S _uart0_wait_txfree Def000000
+S _uart0_wait_txdone Def000032
+S _uart0_tx Def000053
+S XG$uart0_wait_txfree$0$0 Def000031
+S XG$uart0_wait_txdone$0$0 Def000052
+S XG$uart0_tx$0$0 Def00006F
+S A$uart0tx$1300 Def000055
+S A$uart0tx$1201 Def00000D
+S A$uart0tx$1310 Def000065
+S A$uart0tx$1230 Def00002D
+S A$uart0tx$1221 Def000023
+S A$uart0tx$1212 Def000019
+S A$uart0tx$1303 Def000057
+S A$uart0tx$1231 Def00002F
+S A$uart0tx$1222 Def000024
+S A$uart0tx$1213 Def00001C
+S A$uart0tx$1204 Def00000F
+S A$uart0tx$1313 Def000067
+S A$uart0tx$1304 Def00005A
+S A$uart0tx$1223 Def000026
+S A$uart0tx$1214 Def00001E
+S A$uart0tx$1205 Def000012
+S A$uart0tx$1314 Def00006A
+S A$uart0tx$1251 Def000032
+S A$uart0tx$1206 Def000014
+S A$uart0tx$1315 Def00006D
+S A$uart0tx$1252 Def000034
+S A$uart0tx$1234 Def000031
+S A$uart0tx$1207 Def000015
+S A$uart0tx$1307 Def00005D
+S A$uart0tx$1262 Def000039
+S A$uart0tx$1253 Def000036
+S A$uart0tx$1217 Def000020
+S A$uart0tx$1208 Def000016
+S A$uart0tx$1190 Def000006
+S A$uart0tx$1308 Def00005F
+S A$uart0tx$1272 Def000047
+S A$uart0tx$1263 Def00003C
+S A$uart0tx$1227 Def000028
+S A$uart0tx$1209 Def000017
+S A$uart0tx$1318 Def00006F
+S A$uart0tx$1309 Def000062
+S A$uart0tx$1282 Def00004F
+S A$uart0tx$1264 Def00003E
+S A$uart0tx$1228 Def000029
+S A$uart0tx$1283 Def000050
+S A$uart0tx$1229 Def00002B
+S A$uart0tx$1193 Def000008
+S A$uart0tx$1194 Def00000A
+S A$uart0tx$1276 Def00004A
+S A$uart0tx$1267 Def000040
+S A$uart0tx$1195 Def00000C
+S A$uart0tx$1286 Def000052
+S A$uart0tx$1277 Def00004B
+S A$uart0tx$1268 Def000043
+S A$uart0tx$1259 Def000037
+S A$uart0tx$1187 Def000000
+S A$uart0tx$1278 Def00004D
+S A$uart0tx$1269 Def000045
+S A$uart0tx$1188 Def000002
+S A$uart0tx$1189 Def000004
+S A$uart0tx$1299 Def000053
+S C$uart0tx.c$31$2$61 Def000019
+S C$uart0tx.c$40$1$63 Def000032
+S C$uart0tx.c$32$2$61 Def000020
+S C$uart0tx.c$50$1$63 Def000052
+S C$uart0tx.c$33$2$61 Def000023
+S C$uart0tx.c$35$1$60 Def000028
+S C$uart0tx.c$26$1$60 Def000008
+S C$uart0tx.c$36$1$60 Def000031
+S C$uart0tx.c$52$1$63 Def000053
+S C$uart0tx.c$42$2$64 Def000037
+S C$uart0tx.c$38$1$60 Def000032
+S C$uart0tx.c$43$2$64 Def000039
+S C$uart0tx.c$28$2$61 Def00000D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 62
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 5E 02 0A 00 80
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 02 23 02 0D 01 5E
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 80
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A EF 42 A8 80 E8
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 00 3A 02 0E 01 8B
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:uart0tx
+F:G$uart0_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_wait_txfree$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart0tx.uart0_wait_txfree$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart0_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_wait_txdone$iesave$1$63({1}SC:U),R,0,0,[r7]
+F:G$uart0_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0tx.uart0_tx$v$1$65({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$NVADDR$0$0({2}SI:U),I,0,0
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+S:G$NVDATA$0$0({2}SI:U),I,0,0
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+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$T0CNT$0$0({2}SI:U),I,0,0
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+S:G$T1CNT$0$0({2}SI:U),I,0,0
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+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
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+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
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+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
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+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
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+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
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+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
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+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
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+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
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+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
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+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
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+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1tx
+
+;!FILE libmflarge/uart1tx.asm
+XH3
+H 1A areas 327 global symbols
+M uart1tx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _uart1_txpoke Ref000000
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _uart1_poll Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S _uart1_txadvance Ref000000
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S _uart1_txidle Ref000000
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S _uart1_txfree Ref000000
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 70 flags 20 addr 0
+S C$uart1tx.c$43$2$64 Def000039
+S C$uart1tx.c$28$2$61 Def00000D
+S C$uart1tx.c$29$2$61 Def00000F
+S G$uart1_wait_txfree$0$0 Def000000
+S C$uart1tx.c$45$2$64 Def000040
+S C$uart1tx.c$54$1$66 Def000057
+S C$uart1tx.c$46$2$64 Def000047
+S C$uart1tx.c$24$0$0 Def000000
+S C$uart1tx.c$55$1$66 Def00005D
+S C$uart1tx.c$47$2$64 Def00004A
+S C$uart1tx.c$49$1$63 Def00004F
+S C$uart1tx.c$56$1$66 Def000067
+S G$uart1_wait_txdone$0$0 Def000032
+S C$uart1tx.c$57$1$66 Def00006F
+S G$uart1_tx$0$0 Def000053
+S _uart1_wait_txfree Def000000
+S _uart1_wait_txdone Def000032
+S _uart1_tx Def000053
+S XG$uart1_wait_txfree$0$0 Def000031
+S XG$uart1_wait_txdone$0$0 Def000052
+S XG$uart1_tx$0$0 Def00006F
+S A$uart1tx$1300 Def000055
+S A$uart1tx$1201 Def00000D
+S A$uart1tx$1310 Def000065
+S A$uart1tx$1230 Def00002D
+S A$uart1tx$1221 Def000023
+S A$uart1tx$1212 Def000019
+S A$uart1tx$1303 Def000057
+S A$uart1tx$1231 Def00002F
+S A$uart1tx$1222 Def000024
+S A$uart1tx$1213 Def00001C
+S A$uart1tx$1204 Def00000F
+S A$uart1tx$1313 Def000067
+S A$uart1tx$1304 Def00005A
+S A$uart1tx$1223 Def000026
+S A$uart1tx$1214 Def00001E
+S A$uart1tx$1205 Def000012
+S A$uart1tx$1314 Def00006A
+S A$uart1tx$1251 Def000032
+S A$uart1tx$1206 Def000014
+S A$uart1tx$1315 Def00006D
+S A$uart1tx$1252 Def000034
+S A$uart1tx$1234 Def000031
+S A$uart1tx$1207 Def000015
+S A$uart1tx$1307 Def00005D
+S A$uart1tx$1262 Def000039
+S A$uart1tx$1253 Def000036
+S A$uart1tx$1217 Def000020
+S A$uart1tx$1208 Def000016
+S A$uart1tx$1190 Def000006
+S A$uart1tx$1308 Def00005F
+S A$uart1tx$1272 Def000047
+S A$uart1tx$1263 Def00003C
+S A$uart1tx$1227 Def000028
+S A$uart1tx$1209 Def000017
+S A$uart1tx$1318 Def00006F
+S A$uart1tx$1309 Def000062
+S A$uart1tx$1282 Def00004F
+S A$uart1tx$1264 Def00003E
+S A$uart1tx$1228 Def000029
+S A$uart1tx$1283 Def000050
+S A$uart1tx$1229 Def00002B
+S A$uart1tx$1193 Def000008
+S A$uart1tx$1194 Def00000A
+S A$uart1tx$1276 Def00004A
+S A$uart1tx$1267 Def000040
+S A$uart1tx$1195 Def00000C
+S A$uart1tx$1286 Def000052
+S A$uart1tx$1277 Def00004B
+S A$uart1tx$1268 Def000043
+S A$uart1tx$1259 Def000037
+S A$uart1tx$1187 Def000000
+S A$uart1tx$1278 Def00004D
+S A$uart1tx$1269 Def000045
+S A$uart1tx$1188 Def000002
+S A$uart1tx$1189 Def000004
+S A$uart1tx$1299 Def000053
+S C$uart1tx.c$31$2$61 Def000019
+S C$uart1tx.c$40$1$63 Def000032
+S C$uart1tx.c$32$2$61 Def000020
+S C$uart1tx.c$50$1$63 Def000052
+S C$uart1tx.c$33$2$61 Def000023
+S C$uart1tx.c$35$1$60 Def000028
+S C$uart1tx.c$26$1$60 Def000008
+S C$uart1tx.c$36$1$60 Def000031
+S C$uart1tx.c$52$1$63 Def000053
+S C$uart1tx.c$42$2$64 Def000037
+S C$uart1tx.c$38$1$60 Def000032
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 71
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 63 02 0A 00 80
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 74 80 55 A8 FF
+R 00 00 00 16
+T 00 00 37
+R 00 00 00 16
+T 00 00 37 C2 AF 12 00 00 E5 82 70 0F 12 00 00 E5
+R 00 00 00 16 02 06 02 34 02 0D 01 63
+T 00 00 44 82 70 03 12 00 00
+R 00 00 00 16 02 07 00 80
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A EF 42 A8 80 E8
+R 00 00 00 16
+T 00 00 4F
+R 00 00 00 16
+T 00 00 4F EF 42 A8 22
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 C0 07 AF 82 75 82 01 12 00 00 C0 07 75
+R 00 00 00 16 00 0B 00 16
+T 00 00 60 82 00 12 00 00 15 81 75 82 01 12 00 00
+R 00 00 00 16 02 06 00 44 02 0E 01 97
+T 00 00 6D D0 07 22
+R 00 00 00 16
+
+
+M:uart1tx
+F:G$uart1_wait_txfree$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_wait_txfree$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart1tx.uart1_wait_txfree$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart1_wait_txdone$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_wait_txdone$iesave$1$63({1}SC:U),R,0,0,[r7]
+F:G$uart1_tx$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1tx.uart1_tx$v$1$65({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
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+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0rx
+
+;!FILE libmflarge/uart0rx.asm
+XH3
+H 1A areas 309 global symbols
+M uart0rx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _uart0_poll Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S _uart0_rxadvance Ref000000
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S _uart0_rxpeek Ref000000
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S _uart0_rxcount Ref000000
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$uart0rx.c$24$0$0 Def000000
+S G$uart0_wait_rxcount$0$0 Def000000
+S G$uart0_rx$0$0 Def000032
+S _uart0_wait_rxcount Def000000
+S _uart0_rx Def000032
+S XG$uart0_wait_rxcount$0$0 Def000031
+S XG$uart0_rx$0$0 Def00004C
+S A$uart0rx$1210 Def000019
+S A$uart0rx$1220 Def000024
+S A$uart0rx$1211 Def00001C
+S A$uart0rx$1202 Def00000F
+S A$uart0rx$1221 Def000026
+S A$uart0rx$1212 Def00001E
+S A$uart0rx$1203 Def000012
+S A$uart0rx$1204 Def000014
+S A$uart0rx$1250 Def000034
+S A$uart0rx$1232 Def000031
+S A$uart0rx$1205 Def000015
+S A$uart0rx$1260 Def000045
+S A$uart0rx$1251 Def000037
+S A$uart0rx$1215 Def000020
+S A$uart0rx$1206 Def000016
+S A$uart0rx$1225 Def000028
+S A$uart0rx$1207 Def000017
+S A$uart0rx$1226 Def000029
+S A$uart0rx$1263 Def000048
+S A$uart0rx$1254 Def00003A
+S A$uart0rx$1227 Def00002B
+S A$uart0rx$1191 Def000008
+S A$uart0rx$1264 Def00004A
+S A$uart0rx$1255 Def00003D
+S A$uart0rx$1228 Def00002D
+S A$uart0rx$1219 Def000023
+S A$uart0rx$1192 Def00000A
+S A$uart0rx$1256 Def000040
+S A$uart0rx$1247 Def000032
+S A$uart0rx$1229 Def00002F
+S A$uart0rx$1193 Def00000C
+S A$uart0rx$1185 Def000000
+S A$uart0rx$1267 Def00004C
+S A$uart0rx$1186 Def000002
+S A$uart0rx$1259 Def000042
+S A$uart0rx$1187 Def000004
+S A$uart0rx$1188 Def000006
+S A$uart0rx$1199 Def00000D
+S C$uart0rx.c$31$2$61 Def000019
+S C$uart0rx.c$32$2$61 Def000020
+S C$uart0rx.c$41$1$63 Def000034
+S C$uart0rx.c$33$2$61 Def000023
+S C$uart0rx.c$35$1$60 Def000028
+S C$uart0rx.c$26$1$60 Def000008
+S C$uart0rx.c$42$1$63 Def00003A
+S C$uart0rx.c$36$1$60 Def000031
+S C$uart0rx.c$43$1$63 Def000042
+S C$uart0rx.c$44$1$63 Def000048
+S C$uart0rx.c$38$1$60 Def000032
+S C$uart0rx.c$45$1$63 Def00004C
+S C$uart0rx.c$28$2$61 Def00000D
+S C$uart0rx.c$29$2$61 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 B8
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 5D 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 02 6F 02 0B 01 78
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:uart0rx
+F:G$uart0_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0rx.uart0_wait_rxcount$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart0rx.uart0_wait_rxcount$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart0_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0rx.uart0_rx$x$1$63({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
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+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$NVADDR$0$0({2}SI:U),I,0,0
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+S:G$NVDATA$0$0({2}SI:U),I,0,0
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+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
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+S:G$T1CNT0$0$0({1}SC:U),I,0,0
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+S:G$T1CNT$0$0({2}SI:U),I,0,0
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+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
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+S:G$PINA_7$0$0({1}SX:U),J,0,0
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+S:G$PINB_4$0$0({1}SX:U),J,0,0
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+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
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+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
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+S:G$PINC_7$0$0({1}SX:U),J,0,0
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+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
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+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
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+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
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+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
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+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
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+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
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+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
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+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
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+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
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+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1rx
+
+;!FILE libmflarge/uart1rx.asm
+XH3
+H 1A areas 309 global symbols
+M uart1rx
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _wtimer_standby Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _uart1_poll Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S _uart1_rxadvance Ref000000
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S _uart1_rxpeek Ref000000
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _uart1_rxcount Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 4D flags 20 addr 0
+S C$uart1rx.c$24$0$0 Def000000
+S G$uart1_wait_rxcount$0$0 Def000000
+S G$uart1_rx$0$0 Def000032
+S _uart1_wait_rxcount Def000000
+S _uart1_rx Def000032
+S XG$uart1_wait_rxcount$0$0 Def000031
+S XG$uart1_rx$0$0 Def00004C
+S A$uart1rx$1210 Def000019
+S A$uart1rx$1220 Def000024
+S A$uart1rx$1211 Def00001C
+S A$uart1rx$1202 Def00000F
+S A$uart1rx$1221 Def000026
+S A$uart1rx$1212 Def00001E
+S A$uart1rx$1203 Def000012
+S A$uart1rx$1204 Def000014
+S A$uart1rx$1250 Def000034
+S A$uart1rx$1232 Def000031
+S A$uart1rx$1205 Def000015
+S A$uart1rx$1260 Def000045
+S A$uart1rx$1251 Def000037
+S A$uart1rx$1215 Def000020
+S A$uart1rx$1206 Def000016
+S A$uart1rx$1225 Def000028
+S A$uart1rx$1207 Def000017
+S A$uart1rx$1226 Def000029
+S A$uart1rx$1263 Def000048
+S A$uart1rx$1254 Def00003A
+S A$uart1rx$1227 Def00002B
+S A$uart1rx$1191 Def000008
+S A$uart1rx$1264 Def00004A
+S A$uart1rx$1255 Def00003D
+S A$uart1rx$1228 Def00002D
+S A$uart1rx$1219 Def000023
+S A$uart1rx$1192 Def00000A
+S A$uart1rx$1256 Def000040
+S A$uart1rx$1247 Def000032
+S A$uart1rx$1229 Def00002F
+S A$uart1rx$1193 Def00000C
+S A$uart1rx$1185 Def000000
+S A$uart1rx$1267 Def00004C
+S A$uart1rx$1186 Def000002
+S A$uart1rx$1259 Def000042
+S A$uart1rx$1187 Def000004
+S A$uart1rx$1188 Def000006
+S A$uart1rx$1199 Def00000D
+S C$uart1rx.c$31$2$61 Def000019
+S C$uart1rx.c$32$2$61 Def000020
+S C$uart1rx.c$41$1$63 Def000034
+S C$uart1rx.c$33$2$61 Def000023
+S C$uart1rx.c$35$1$60 Def000028
+S C$uart1rx.c$26$1$60 Def000008
+S C$uart1rx.c$42$1$63 Def00003A
+S C$uart1rx.c$36$1$60 Def000031
+S C$uart1rx.c$43$1$63 Def000042
+S C$uart1rx.c$44$1$63 Def000048
+S C$uart1rx.c$38$1$60 Def000032
+S C$uart1rx.c$45$1$63 Def00004C
+S C$uart1rx.c$28$2$61 Def00000D
+S C$uart1rx.c$29$2$61 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 C0 06 C0 05 AF 82 74 80 55 A8 FE
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D C2 AF 12 00 00 AD 82 C3 ED 9F 50 0F 12
+R 00 00 00 16 02 06 02 C4
+T 00 00 1A 00 00 E5 82 70 03 12 00 00
+R 00 00 00 16 02 03 01 62 02 0A 00 7F
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EE 42 A8 80 E5
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EE 42 A8 D0 05 D0 06 D0 07 22
+R 00 00 00 16
+T 00 00 32
+R 00 00 00 16
+T 00 00 32 C0 07 75 82 01 12 00 00 75 82 00 12
+R 00 00 00 16 00 09 00 16
+T 00 00 3E 00 00 AF 82 75 82 01 12 00 00 8F 82 D0
+R 00 00 00 16 02 03 02 80 02 0B 01 81
+T 00 00 4B 07 22
+R 00 00 00 16
+
+
+M:uart1rx
+F:G$uart1_wait_rxcount$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1rx.uart1_wait_rxcount$v$1$59({1}SC:U),R,0,0,[r7]
+S:Luart1rx.uart1_wait_rxcount$iesave$1$60({1}SC:U),R,0,0,[r6]
+F:G$uart1_rx$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1rx.uart1_rx$x$1$63({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhexu16
+
+;!FILE libmflarge/uart0wrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M uart0wrhexu16
+O -mmcs51 --model-large
+S _uart0_txpokehex Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S XG$uart0_writehexu16$0$0 Def00003D
+S A$uart0wrhexu16$122 Def000009
+S C$uart0wrhexu16.c$30$1$60 Def00003D
+S A$uart0wrhexu16$150 Def000028
+S A$uart0wrhexu16$141 Def00001B
+S A$uart0wrhexu16$132 Def000015
+S A$uart0wrhexu16$123 Def00000B
+S A$uart0wrhexu16$160 Def000034
+S A$uart0wrhexu16$151 Def000029
+S A$uart0wrhexu16$142 Def00001D
+S A$uart0wrhexu16$124 Def00000D
+S C$uart0wrhexu16.c$23$1$60 Def000010
+S A$uart0wrhexu16$152 Def00002A
+S A$uart0wrhexu16$143 Def00001F
+S A$uart0wrhexu16$134 Def000017
+S A$uart0wrhexu16$125 Def00000E
+S A$uart0wrhexu16$116 Def000000
+S C$uart0wrhexu16.c$24$1$60 Def000015
+S A$uart0wrhexu16$153 Def00002C
+S A$uart0wrhexu16$144 Def000021
+S A$uart0wrhexu16$135 Def000018
+S A$uart0wrhexu16$117 Def000002
+S A$uart0wrhexu16$154 Def00002D
+S A$uart0wrhexu16$145 Def000024
+S A$uart0wrhexu16$118 Def000005
+S A$uart0wrhexu16$164 Def000036
+S A$uart0wrhexu16$155 Def00002E
+S A$uart0wrhexu16$128 Def000010
+S A$uart0wrhexu16$119 Def000007
+S C$uart0wrhexu16.c$25$2$61 Def00001A
+S A$uart0wrhexu16$165 Def000038
+S A$uart0wrhexu16$156 Def000030
+S A$uart0wrhexu16$138 Def00001A
+S A$uart0wrhexu16$129 Def000012
+S C$uart0wrhexu16.c$26$2$61 Def00001B
+S A$uart0wrhexu16$166 Def00003B
+S A$uart0wrhexu16$157 Def000031
+S A$uart0wrhexu16$148 Def000026
+S C$uart0wrhexu16.c$29$1$60 Def000036
+S C$uart0wrhexu16.c$27$2$61 Def000026
+S A$uart0wrhexu16$158 Def000032
+S A$uart0wrhexu16$149 Def000027
+S A$uart0wrhexu16$159 Def000033
+S C$uart0wrhexu16.c$21$1$0 Def000009
+S A$uart0wrhexu16$169 Def00003D
+S C$uart0wrhexu16.c$19$0$0 Def000000
+S G$uart0_writehexu16$0$0 Def000000
+S _uart0_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 01
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 03 F1 23 09 00 04
+
+
+M:uart0wrhexu16
+F:G$uart0_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wrhexu16.uart0_writehexu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart0wrhexu16.uart0_writehexu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart0wrhexu16.uart0_writehexu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart0wrhexu16.uart0_writehexu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhexu16
+
+;!FILE libmflarge/uart1wrhexu16.asm
+XH3
+H 1A areas 35 global symbols
+M uart1wrhexu16
+O -mmcs51 --model-large
+S _uart1_txpokehex Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
+S XG$uart1_writehexu16$0$0 Def00003D
+S A$uart1wrhexu16$122 Def000009
+S C$uart1wrhexu16.c$30$1$60 Def00003D
+S A$uart1wrhexu16$150 Def000028
+S A$uart1wrhexu16$141 Def00001B
+S A$uart1wrhexu16$132 Def000015
+S A$uart1wrhexu16$123 Def00000B
+S A$uart1wrhexu16$160 Def000034
+S A$uart1wrhexu16$151 Def000029
+S A$uart1wrhexu16$142 Def00001D
+S A$uart1wrhexu16$124 Def00000D
+S C$uart1wrhexu16.c$23$1$60 Def000010
+S A$uart1wrhexu16$152 Def00002A
+S A$uart1wrhexu16$143 Def00001F
+S A$uart1wrhexu16$134 Def000017
+S A$uart1wrhexu16$125 Def00000E
+S A$uart1wrhexu16$116 Def000000
+S C$uart1wrhexu16.c$24$1$60 Def000015
+S A$uart1wrhexu16$153 Def00002C
+S A$uart1wrhexu16$144 Def000021
+S A$uart1wrhexu16$135 Def000018
+S A$uart1wrhexu16$117 Def000002
+S A$uart1wrhexu16$154 Def00002D
+S A$uart1wrhexu16$145 Def000024
+S A$uart1wrhexu16$118 Def000005
+S A$uart1wrhexu16$164 Def000036
+S A$uart1wrhexu16$155 Def00002E
+S A$uart1wrhexu16$128 Def000010
+S A$uart1wrhexu16$119 Def000007
+S C$uart1wrhexu16.c$25$2$61 Def00001A
+S A$uart1wrhexu16$165 Def000038
+S A$uart1wrhexu16$156 Def000030
+S A$uart1wrhexu16$138 Def00001A
+S A$uart1wrhexu16$129 Def000012
+S C$uart1wrhexu16.c$26$2$61 Def00001B
+S A$uart1wrhexu16$166 Def00003B
+S A$uart1wrhexu16$157 Def000031
+S A$uart1wrhexu16$148 Def000026
+S C$uart1wrhexu16.c$29$1$60 Def000036
+S C$uart1wrhexu16.c$27$2$61 Def000026
+S A$uart1wrhexu16$158 Def000032
+S A$uart1wrhexu16$149 Def000027
+S A$uart1wrhexu16$159 Def000033
+S C$uart1wrhexu16.c$21$1$0 Def000009
+S A$uart1wrhexu16$169 Def00003D
+S C$uart1wrhexu16.c$19$0$0 Def000000
+S G$uart1_writehexu16$0$0 Def000000
+S _uart1_writehexu16 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 04
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 04
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 01
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 1C 1C 8E 03 C0 03 8C 82 12 00 00
+R 00 00 00 16 02 0E 00 00
+T 00 00 24 15 81 EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 16
+T 00 00 31 6E CE FF 80 E1
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 03 F1 23 09 00 04
+
+
+M:uart1wrhexu16
+F:G$uart1_writehexu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wrhexu16.uart1_writehexu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart1wrhexu16.uart1_writehexu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart1wrhexu16.uart1_writehexu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart1wrhexu16.uart1_writehexu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhexu32
+
+;!FILE libmflarge/uart0wrhexu32.asm
+XH3
+H 1A areas 6A global symbols
+M uart0wrhexu32
+O -mmcs51 --model-large
+S _uart0_txpokehex Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S Luart0wrhexu32.uart0_writehexu32$val$1$59 Def000001
+S _uart0_writehexu32_PARM_2 Def000000
+S Luart0wrhexu32.uart0_writehexu32$nrdig$1$59 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 76 flags 20 addr 0
+S XG$uart0_writehexu32$0$0 Def000075
+S A$uart0wrhexu32$200 Def000058
+S A$uart0wrhexu32$210 Def000065
+S A$uart0wrhexu32$201 Def000059
+S A$uart0wrhexu32$211 Def000066
+S A$uart0wrhexu32$202 Def00005A
+S A$uart0wrhexu32$130 Def00000C
+S A$uart0wrhexu32$212 Def000067
+S A$uart0wrhexu32$203 Def00005C
+S A$uart0wrhexu32$131 Def00000D
+S C$uart0wrhexu32.c$30$1$60 Def000075
+S A$uart0wrhexu32$213 Def000068
+S A$uart0wrhexu32$204 Def00005D
+S A$uart0wrhexu32$150 Def00001F
+S A$uart0wrhexu32$141 Def000015
+S A$uart0wrhexu32$132 Def00000E
+S A$uart0wrhexu32$123 Def000000
+S A$uart0wrhexu32$223 Def000070
+S A$uart0wrhexu32$214 Def000069
+S A$uart0wrhexu32$205 Def00005E
+S A$uart0wrhexu32$160 Def000028
+S A$uart0wrhexu32$142 Def000018
+S A$uart0wrhexu32$133 Def00000F
+S A$uart0wrhexu32$124 Def000002
+S C$uart0wrhexu32.c$23$1$60 Def000019
+S A$uart0wrhexu32$224 Def000072
+S A$uart0wrhexu32$215 Def00006A
+S A$uart0wrhexu32$206 Def00005F
+S A$uart0wrhexu32$170 Def000032
+S A$uart0wrhexu32$161 Def000029
+S A$uart0wrhexu32$152 Def000021
+S A$uart0wrhexu32$134 Def000010
+S A$uart0wrhexu32$125 Def000004
+S C$uart0wrhexu32.c$24$1$60 Def00001F
+S A$uart0wrhexu32$216 Def00006B
+S A$uart0wrhexu32$207 Def000060
+S A$uart0wrhexu32$180 Def000040
+S A$uart0wrhexu32$171 Def000033
+S A$uart0wrhexu32$162 Def00002A
+S A$uart0wrhexu32$153 Def000022
+S A$uart0wrhexu32$135 Def000011
+S A$uart0wrhexu32$126 Def000006
+S A$uart0wrhexu32$217 Def00006C
+S A$uart0wrhexu32$208 Def000063
+S A$uart0wrhexu32$190 Def00004C
+S A$uart0wrhexu32$181 Def000041
+S A$uart0wrhexu32$172 Def000035
+S A$uart0wrhexu32$163 Def00002B
+S A$uart0wrhexu32$145 Def000019
+S A$uart0wrhexu32$136 Def000012
+S A$uart0wrhexu32$127 Def000007
+S A$uart0wrhexu32$227 Def000075
+S A$uart0wrhexu32$218 Def00006D
+S A$uart0wrhexu32$209 Def000064
+S A$uart0wrhexu32$191 Def00004D
+S A$uart0wrhexu32$182 Def000042
+S A$uart0wrhexu32$173 Def000037
+S A$uart0wrhexu32$164 Def00002C
+S A$uart0wrhexu32$146 Def00001A
+S A$uart0wrhexu32$137 Def000013
+S A$uart0wrhexu32$128 Def00000A
+S C$uart0wrhexu32.c$25$2$61 Def000024
+S A$uart0wrhexu32$219 Def00006E
+S A$uart0wrhexu32$192 Def00004E
+S A$uart0wrhexu32$183 Def000044
+S A$uart0wrhexu32$174 Def000039
+S A$uart0wrhexu32$165 Def00002D
+S A$uart0wrhexu32$156 Def000024
+S A$uart0wrhexu32$147 Def00001C
+S A$uart0wrhexu32$138 Def000014
+S A$uart0wrhexu32$129 Def00000B
+S C$uart0wrhexu32.c$26$2$61 Def000025
+S A$uart0wrhexu32$193 Def000050
+S A$uart0wrhexu32$184 Def000045
+S A$uart0wrhexu32$175 Def00003C
+S A$uart0wrhexu32$166 Def00002E
+S C$uart0wrhexu32.c$29$1$60 Def000070
+S C$uart0wrhexu32.c$27$2$61 Def00003E
+S A$uart0wrhexu32$194 Def000051
+S A$uart0wrhexu32$185 Def000046
+S A$uart0wrhexu32$167 Def00002F
+S A$uart0wrhexu32$195 Def000052
+S A$uart0wrhexu32$186 Def000048
+S A$uart0wrhexu32$168 Def000030
+S A$uart0wrhexu32$159 Def000025
+S C$uart0wrhexu32.c$21$1$0 Def000015
+S A$uart0wrhexu32$196 Def000053
+S A$uart0wrhexu32$187 Def000049
+S A$uart0wrhexu32$178 Def00003E
+S A$uart0wrhexu32$169 Def000031
+S A$uart0wrhexu32$197 Def000054
+S A$uart0wrhexu32$188 Def00004A
+S A$uart0wrhexu32$179 Def00003F
+S A$uart0wrhexu32$198 Def000055
+S A$uart0wrhexu32$189 Def00004B
+S A$uart0wrhexu32$199 Def000056
+S C$uart0wrhexu32.c$19$0$0 Def000000
+S G$uart0_writehexu32$0$0 Def000000
+S _uart0_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 01
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 4C 1E 90 00 01 E0 FA A3 E0 FB A3
+R 00 00 00 16 00 08 00 0A
+T 00 00 2E E0 FC A3 E0 FD 8A 01 C0 01 8E 82 12
+R 00 00 00 16
+T 00 00 3A 00 00 15 81 EB C4 CA C4 54 0F 6A CA 54
+R 00 00 00 16 02 03 00 00
+T 00 00 47 0F CA 6A CA FB EC C4 54 F0 4B FB ED C4
+R 00 00 00 16
+T 00 00 54 CC C4 54 0F 6C CC 54 0F CC 6C CC FD 90
+R 00 00 00 16
+T 00 00 61 00 01 EA F0 EB A3 F0 EC A3 F0 ED A3 F0
+R 00 00 00 16 00 03 00 0A
+T 00 00 6E 80 B1
+R 00 00 00 16
+T 00 00 70
+R 00 00 00 16
+T 00 00 70 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 03
+
+
+M:uart0wrhexu32
+F:G$uart0_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart0wrhexu32.uart0_writehexu32$nrdig1$1$60({1}SC:U),R,0,0,[r7]
+S:Luart0wrhexu32.uart0_writehexu32$digit$1$60({1}SC:U),R,0,0,[r6]
+S:Luart0wrhexu32.uart0_writehexu32$nrdig$1$59({1}SC:U),F,0,0
+S:Luart0wrhexu32.uart0_writehexu32$val$1$59({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhexu32
+
+;!FILE libmflarge/uart1wrhexu32.asm
+XH3
+H 1A areas 6A global symbols
+M uart1wrhexu32
+O -mmcs51 --model-large
+S _uart1_txpokehex Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S Luart1wrhexu32.uart1_writehexu32$val$1$59 Def000001
+S _uart1_writehexu32_PARM_2 Def000000
+S Luart1wrhexu32.uart1_writehexu32$nrdig$1$59 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 76 flags 20 addr 0
+S XG$uart1_writehexu32$0$0 Def000075
+S A$uart1wrhexu32$200 Def000058
+S A$uart1wrhexu32$210 Def000065
+S A$uart1wrhexu32$201 Def000059
+S A$uart1wrhexu32$211 Def000066
+S A$uart1wrhexu32$202 Def00005A
+S A$uart1wrhexu32$130 Def00000C
+S A$uart1wrhexu32$212 Def000067
+S A$uart1wrhexu32$203 Def00005C
+S A$uart1wrhexu32$131 Def00000D
+S C$uart1wrhexu32.c$30$1$60 Def000075
+S A$uart1wrhexu32$213 Def000068
+S A$uart1wrhexu32$204 Def00005D
+S A$uart1wrhexu32$150 Def00001F
+S A$uart1wrhexu32$141 Def000015
+S A$uart1wrhexu32$132 Def00000E
+S A$uart1wrhexu32$123 Def000000
+S A$uart1wrhexu32$223 Def000070
+S A$uart1wrhexu32$214 Def000069
+S A$uart1wrhexu32$205 Def00005E
+S A$uart1wrhexu32$160 Def000028
+S A$uart1wrhexu32$142 Def000018
+S A$uart1wrhexu32$133 Def00000F
+S A$uart1wrhexu32$124 Def000002
+S C$uart1wrhexu32.c$23$1$60 Def000019
+S A$uart1wrhexu32$224 Def000072
+S A$uart1wrhexu32$215 Def00006A
+S A$uart1wrhexu32$206 Def00005F
+S A$uart1wrhexu32$170 Def000032
+S A$uart1wrhexu32$161 Def000029
+S A$uart1wrhexu32$152 Def000021
+S A$uart1wrhexu32$134 Def000010
+S A$uart1wrhexu32$125 Def000004
+S C$uart1wrhexu32.c$24$1$60 Def00001F
+S A$uart1wrhexu32$216 Def00006B
+S A$uart1wrhexu32$207 Def000060
+S A$uart1wrhexu32$180 Def000040
+S A$uart1wrhexu32$171 Def000033
+S A$uart1wrhexu32$162 Def00002A
+S A$uart1wrhexu32$153 Def000022
+S A$uart1wrhexu32$135 Def000011
+S A$uart1wrhexu32$126 Def000006
+S A$uart1wrhexu32$217 Def00006C
+S A$uart1wrhexu32$208 Def000063
+S A$uart1wrhexu32$190 Def00004C
+S A$uart1wrhexu32$181 Def000041
+S A$uart1wrhexu32$172 Def000035
+S A$uart1wrhexu32$163 Def00002B
+S A$uart1wrhexu32$145 Def000019
+S A$uart1wrhexu32$136 Def000012
+S A$uart1wrhexu32$127 Def000007
+S A$uart1wrhexu32$227 Def000075
+S A$uart1wrhexu32$218 Def00006D
+S A$uart1wrhexu32$209 Def000064
+S A$uart1wrhexu32$191 Def00004D
+S A$uart1wrhexu32$182 Def000042
+S A$uart1wrhexu32$173 Def000037
+S A$uart1wrhexu32$164 Def00002C
+S A$uart1wrhexu32$146 Def00001A
+S A$uart1wrhexu32$137 Def000013
+S A$uart1wrhexu32$128 Def00000A
+S C$uart1wrhexu32.c$25$2$61 Def000024
+S A$uart1wrhexu32$219 Def00006E
+S A$uart1wrhexu32$192 Def00004E
+S A$uart1wrhexu32$183 Def000044
+S A$uart1wrhexu32$174 Def000039
+S A$uart1wrhexu32$165 Def00002D
+S A$uart1wrhexu32$156 Def000024
+S A$uart1wrhexu32$147 Def00001C
+S A$uart1wrhexu32$138 Def000014
+S A$uart1wrhexu32$129 Def00000B
+S C$uart1wrhexu32.c$26$2$61 Def000025
+S A$uart1wrhexu32$193 Def000050
+S A$uart1wrhexu32$184 Def000045
+S A$uart1wrhexu32$175 Def00003C
+S A$uart1wrhexu32$166 Def00002E
+S C$uart1wrhexu32.c$29$1$60 Def000070
+S C$uart1wrhexu32.c$27$2$61 Def00003E
+S A$uart1wrhexu32$194 Def000051
+S A$uart1wrhexu32$185 Def000046
+S A$uart1wrhexu32$167 Def00002F
+S A$uart1wrhexu32$195 Def000052
+S A$uart1wrhexu32$186 Def000048
+S A$uart1wrhexu32$168 Def000030
+S A$uart1wrhexu32$159 Def000025
+S C$uart1wrhexu32.c$21$1$0 Def000015
+S A$uart1wrhexu32$196 Def000053
+S A$uart1wrhexu32$187 Def000049
+S A$uart1wrhexu32$178 Def00003E
+S A$uart1wrhexu32$169 Def000031
+S A$uart1wrhexu32$197 Def000054
+S A$uart1wrhexu32$188 Def00004A
+S A$uart1wrhexu32$179 Def00003F
+S A$uart1wrhexu32$198 Def000055
+S A$uart1wrhexu32$189 Def00004B
+S A$uart1wrhexu32$199 Def000056
+S C$uart1wrhexu32.c$19$0$0 Def000000
+S G$uart1_writehexu32$0$0 Def000000
+S _uart1_writehexu32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 01
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 4C 1E 90 00 01 E0 FA A3 E0 FB A3
+R 00 00 00 16 00 08 00 0A
+T 00 00 2E E0 FC A3 E0 FD 8A 01 C0 01 8E 82 12
+R 00 00 00 16
+T 00 00 3A 00 00 15 81 EB C4 CA C4 54 0F 6A CA 54
+R 00 00 00 16 02 03 00 00
+T 00 00 47 0F CA 6A CA FB EC C4 54 F0 4B FB ED C4
+R 00 00 00 16
+T 00 00 54 CC C4 54 0F 6C CC 54 0F CC 6C CC FD 90
+R 00 00 00 16
+T 00 00 61 00 01 EA F0 EB A3 F0 EC A3 F0 ED A3 F0
+R 00 00 00 16 00 03 00 0A
+T 00 00 6E 80 B1
+R 00 00 00 16
+T 00 00 70
+R 00 00 00 16
+T 00 00 70 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 03
+
+
+M:uart1wrhexu32
+F:G$uart1_writehexu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart1wrhexu32.uart1_writehexu32$nrdig1$1$60({1}SC:U),R,0,0,[r7]
+S:Luart1wrhexu32.uart1_writehexu32$digit$1$60({1}SC:U),R,0,0,[r6]
+S:Luart1wrhexu32.uart1_writehexu32$nrdig$1$59({1}SC:U),F,0,0
+S:Luart1wrhexu32.uart1_writehexu32$val$1$59({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrstr
+
+;!FILE libmflarge/uart0wrstr.asm
+XH3
+H 1A areas 51 global symbols
+M uart0wrstr
+O -mmcs51 --model-large
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart0_txadvance Ref000000
+S _uart0_txbufptr Ref000000
+S _uart0_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S A$uart0wrstr$120 Def00000A
+S A$uart0wrstr$130 Def000018
+S A$uart0wrstr$121 Def00000D
+S A$uart0wrstr$140 Def000025
+S A$uart0wrstr$131 Def000019
+S A$uart0wrstr$113 Def000000
+S A$uart0wrstr$150 Def00002F
+S A$uart0wrstr$141 Def000026
+S A$uart0wrstr$132 Def00001A
+S A$uart0wrstr$123 Def000010
+S A$uart0wrstr$114 Def000002
+S A$uart0wrstr$160 Def000040
+S A$uart0wrstr$151 Def000031
+S A$uart0wrstr$142 Def000027
+S A$uart0wrstr$133 Def00001B
+S A$uart0wrstr$124 Def000011
+S A$uart0wrstr$115 Def000004
+S A$uart0wrstr$170 Def000054
+S A$uart0wrstr$161 Def000042
+S A$uart0wrstr$152 Def000032
+S A$uart0wrstr$143 Def000029
+S A$uart0wrstr$134 Def00001D
+S A$uart0wrstr$125 Def000012
+S A$uart0wrstr$116 Def000005
+S A$uart0wrstr$180 Def000064
+S A$uart0wrstr$171 Def000055
+S A$uart0wrstr$162 Def000044
+S A$uart0wrstr$153 Def000033
+S A$uart0wrstr$144 Def00002B
+S A$uart0wrstr$135 Def00001F
+S A$uart0wrstr$117 Def000006
+S A$uart0wrstr$190 Def000071
+S A$uart0wrstr$181 Def000065
+S A$uart0wrstr$172 Def000056
+S A$uart0wrstr$163 Def000046
+S A$uart0wrstr$154 Def000035
+S A$uart0wrstr$191 Def000073
+S A$uart0wrstr$182 Def000066
+S A$uart0wrstr$173 Def000058
+S A$uart0wrstr$164 Def000049
+S A$uart0wrstr$155 Def000036
+S A$uart0wrstr$128 Def000014
+S A$uart0wrstr$119 Def000007
+S A$uart0wrstr$183 Def000068
+S A$uart0wrstr$174 Def00005B
+S A$uart0wrstr$165 Def00004C
+S A$uart0wrstr$156 Def000038
+S A$uart0wrstr$147 Def00002D
+S A$uart0wrstr$138 Def000021
+S A$uart0wrstr$129 Def000016
+S A$uart0wrstr$184 Def00006A
+S A$uart0wrstr$175 Def00005D
+S A$uart0wrstr$166 Def00004E
+S A$uart0wrstr$157 Def00003A
+S A$uart0wrstr$148 Def00002E
+S A$uart0wrstr$139 Def000023
+S A$uart0wrstr$185 Def00006B
+S A$uart0wrstr$167 Def000051
+S A$uart0wrstr$195 Def000076
+S A$uart0wrstr$186 Def00006C
+S A$uart0wrstr$177 Def00005F
+S A$uart0wrstr$159 Def00003D
+S A$uart0wrstr$178 Def000061
+S A$uart0wrstr$169 Def000053
+S A$uart0wrstr$188 Def00006E
+S A$uart0wrstr$179 Def000063
+S A$uart0wrstr$189 Def00006F
+S C$uart0wrstr.c$27$0$0 Def000000
+S G$uart0_writestr$0$0 Def000000
+S _uart0_writestr Def000000
+S XG$uart0_writestr$0$0 Def000076
+S C$uart0wrstr.c$102$1$60 Def000000
+S C$uart0wrstr.c$103$1$60 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 07 F1 23 09 00 06
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 05
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 02
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 04
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 00 02 08 00 04
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 03
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 02
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:uart0wrstr
+F:G$uart0_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wrstr.uart0_writestr$ch$1$59({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrstr
+
+;!FILE libmflarge/uart1wrstr.asm
+XH3
+H 1A areas 51 global symbols
+M uart1wrstr
+O -mmcs51 --model-large
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S _uart1_txadvance Ref000000
+S _uart1_txbufptr Ref000000
+S _uart1_txfreelinear Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 77 flags 20 addr 0
+S A$uart1wrstr$120 Def00000A
+S A$uart1wrstr$130 Def000018
+S A$uart1wrstr$121 Def00000D
+S A$uart1wrstr$140 Def000025
+S A$uart1wrstr$131 Def000019
+S A$uart1wrstr$113 Def000000
+S A$uart1wrstr$150 Def00002F
+S A$uart1wrstr$141 Def000026
+S A$uart1wrstr$132 Def00001A
+S A$uart1wrstr$123 Def000010
+S A$uart1wrstr$114 Def000002
+S A$uart1wrstr$160 Def000040
+S A$uart1wrstr$151 Def000031
+S A$uart1wrstr$142 Def000027
+S A$uart1wrstr$133 Def00001B
+S A$uart1wrstr$124 Def000011
+S A$uart1wrstr$115 Def000004
+S A$uart1wrstr$170 Def000054
+S A$uart1wrstr$161 Def000042
+S A$uart1wrstr$152 Def000032
+S A$uart1wrstr$143 Def000029
+S A$uart1wrstr$134 Def00001D
+S A$uart1wrstr$125 Def000012
+S A$uart1wrstr$116 Def000005
+S A$uart1wrstr$180 Def000064
+S A$uart1wrstr$171 Def000055
+S A$uart1wrstr$162 Def000044
+S A$uart1wrstr$153 Def000033
+S A$uart1wrstr$144 Def00002B
+S A$uart1wrstr$135 Def00001F
+S A$uart1wrstr$117 Def000006
+S A$uart1wrstr$190 Def000071
+S A$uart1wrstr$181 Def000065
+S A$uart1wrstr$172 Def000056
+S A$uart1wrstr$163 Def000046
+S A$uart1wrstr$154 Def000035
+S A$uart1wrstr$191 Def000073
+S A$uart1wrstr$182 Def000066
+S A$uart1wrstr$173 Def000058
+S A$uart1wrstr$164 Def000049
+S A$uart1wrstr$155 Def000036
+S A$uart1wrstr$128 Def000014
+S A$uart1wrstr$119 Def000007
+S A$uart1wrstr$183 Def000068
+S A$uart1wrstr$174 Def00005B
+S A$uart1wrstr$165 Def00004C
+S A$uart1wrstr$156 Def000038
+S A$uart1wrstr$147 Def00002D
+S A$uart1wrstr$138 Def000021
+S A$uart1wrstr$129 Def000016
+S A$uart1wrstr$184 Def00006A
+S A$uart1wrstr$175 Def00005D
+S A$uart1wrstr$166 Def00004E
+S A$uart1wrstr$157 Def00003A
+S A$uart1wrstr$148 Def00002E
+S A$uart1wrstr$139 Def000023
+S A$uart1wrstr$185 Def00006B
+S A$uart1wrstr$167 Def000051
+S A$uart1wrstr$195 Def000076
+S A$uart1wrstr$186 Def00006C
+S A$uart1wrstr$177 Def00005F
+S A$uart1wrstr$159 Def00003D
+S A$uart1wrstr$178 Def000061
+S A$uart1wrstr$169 Def000053
+S A$uart1wrstr$188 Def00006E
+S A$uart1wrstr$179 Def000063
+S A$uart1wrstr$189 Def00006F
+S C$uart1wrstr.c$27$0$0 Def000000
+S G$uart1_writestr$0$0 Def000000
+S _uart1_writestr Def000000
+S XG$uart1_writestr$0$0 Def000076
+S C$uart1wrstr.c$102$1$60 Def000000
+S C$uart1wrstr.c$103$1$60 Def000076
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 A8 82 AF 83 E4 FB FA
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 20 00 00 00 0A 30 00 00 00 14 20
+R 00 00 00 16 F1 23 04 00 07 F1 23 09 00 06
+T 00 00 0E 00 00 00 1D E6 08 80 1B
+R 00 00 00 16 F1 23 03 00 05
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 88 82 8F 83 E4 93 A3 A8 82 AF 83 80 0E
+R 00 00 00 16
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 88 82 8F 83 E0 A3 A8 82 AF 83 80 02
+R 00 00 00 16
+T 00 00 2D
+R 00 00 00 16
+T 00 00 2D E2 08
+R 00 00 00 16
+T 00 00 2F
+R 00 00 00 16
+T 00 00 2F 60 3D F9 EB 70 2A EA 60 05 F5 82 12
+R 00 00 00 16
+T 00 00 3B 00 00
+R 00 00 00 16 02 03 00 02
+T 00 00 3D
+R 00 00 00 16
+T 00 00 3D 12 00 00 E5 82 70 0F AC F0 75 82 01 12
+R 00 00 00 16 02 04 00 04
+T 00 00 4A 00 00 8C F0 12 00 00 E5 82
+R 00 00 00 16 02 03 00 00 02 08 00 04
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 FB E4 FA F5 82 12 00 00 AC 82 AD 83
+R 00 00 00 16 02 09 00 03
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 8C 82 8D 83 E9 F0 A3 AC 82 AD 83 0A 1B
+R 00 00 00 16
+T 00 00 6C 80 99
+R 00 00 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E EA 60 05 F5 82 12 00 00
+R 00 00 00 16 02 09 00 02
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 22
+R 00 00 00 16
+
+
+M:uart1wrstr
+F:G$uart1_writestr$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wrstr.uart1_writestr$ch$1$59({3}DG,SC:S),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wru16
+
+;!FILE libmflarge/uart0wru16.asm
+XH3
+H 1A areas 4A global symbols
+M uart0wru16
+O -mmcs51 --model-large
+S __divuint Ref000000
+S _uart0_txpoke Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _uart0_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 60 flags 20 addr 0
+S A$uart0wru16$120 Def000007
+S A$uart0wru16$130 Def000012
+S A$uart0wru16$150 Def000029
+S A$uart0wru16$123 Def000009
+S C$uart0wru16.c$31$1$60 Def000058
+S A$uart0wru16$151 Def00002B
+S A$uart0wru16$142 Def00001C
+S A$uart0wru16$133 Def000015
+S A$uart0wru16$124 Def00000B
+S C$uart0wru16.c$32$1$60 Def00005F
+S C$uart0wru16.c$23$1$60 Def000010
+S A$uart0wru16$161 Def00003C
+S A$uart0wru16$152 Def00002D
+S A$uart0wru16$143 Def00001F
+S A$uart0wru16$125 Def00000D
+S C$uart0wru16.c$24$1$60 Def000015
+S A$uart0wru16$180 Def000051
+S A$uart0wru16$162 Def00003E
+S A$uart0wru16$153 Def00002F
+S A$uart0wru16$144 Def000021
+S A$uart0wru16$135 Def000017
+S A$uart0wru16$126 Def00000E
+S A$uart0wru16$117 Def000000
+S A$uart0wru16$181 Def000054
+S A$uart0wru16$172 Def000048
+S A$uart0wru16$163 Def00003F
+S A$uart0wru16$154 Def000032
+S A$uart0wru16$145 Def000022
+S A$uart0wru16$136 Def000018
+S A$uart0wru16$118 Def000002
+S C$uart0wru16.c$26$1$60 Def00001C
+S C$uart0wru16.c$25$2$60 Def00001A
+S A$uart0wru16$191 Def00005F
+S A$uart0wru16$182 Def000056
+S A$uart0wru16$164 Def000042
+S A$uart0wru16$155 Def000034
+S A$uart0wru16$146 Def000023
+S A$uart0wru16$119 Def000005
+S A$uart0wru16$165 Def000043
+S A$uart0wru16$156 Def000036
+S A$uart0wru16$147 Def000024
+S A$uart0wru16$129 Def000010
+S A$uart0wru16$175 Def000049
+S A$uart0wru16$166 Def000044
+S A$uart0wru16$157 Def000038
+S A$uart0wru16$148 Def000025
+S A$uart0wru16$139 Def00001A
+S C$uart0wru16.c$27$2$61 Def00003C
+S A$uart0wru16$176 Def00004B
+S A$uart0wru16$167 Def000045
+S A$uart0wru16$158 Def00003A
+S A$uart0wru16$149 Def000027
+S C$uart0wru16.c$28$2$61 Def000048
+S A$uart0wru16$186 Def000058
+S A$uart0wru16$177 Def00004C
+S A$uart0wru16$168 Def000046
+S C$uart0wru16.c$29$2$61 Def000049
+S C$uart0wru16.c$21$1$0 Def000009
+S A$uart0wru16$187 Def00005A
+S A$uart0wru16$178 Def00004D
+S A$uart0wru16$169 Def000047
+S A$uart0wru16$188 Def00005D
+S A$uart0wru16$179 Def00004F
+S C$uart0wru16.c$19$0$0 Def000000
+S G$uart0_writeu16$0$0 Def000000
+S _uart0_writeu16 Def000000
+S XG$uart0_writeu16$0$0 Def00005F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 06
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 02
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3E 8E 03 90 00 00 74 0A F0 E4 A3
+R 00 00 00 16 02 09 00 04
+T 00 00 24 F0 8E 82 8F 83 C0 05 C0 04 C0 03 12
+R 00 00 00 16
+T 00 00 30 00 00 AE 82 AF 83 D0 03 D0 04 D0 05 8E
+R 00 00 00 16 02 03 00 00
+T 00 00 3D 02 EA 75 F0 0A A4 FA EB C3 9A FB 1C 74
+R 00 00 00 16
+T 00 00 4A 30 2B FB C0 03 8C 82 12 00 00 15 81 80
+R 00 00 00 16 02 0B 00 01
+T 00 00 57 BF
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 05 F1 23 09 00 06
+
+
+M:uart0wru16
+F:G$uart0_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart0wru16.uart0_writeu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart0wru16.uart0_writeu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart0wru16.uart0_writeu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart0wru16.uart0_writeu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:Luart0wru16.uart0_writeu16$v1$2$61({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wru16
+
+;!FILE libmflarge/uart1wru16.asm
+XH3
+H 1A areas 4A global symbols
+M uart1wru16
+O -mmcs51 --model-large
+S __divuint Ref000000
+S _uart1_txpoke Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divuint_PARM_2 Ref000000
+S _uart1_txadvance Ref000000
+S _bp Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 60 flags 20 addr 0
+S A$uart1wru16$120 Def000007
+S A$uart1wru16$130 Def000012
+S A$uart1wru16$150 Def000029
+S A$uart1wru16$123 Def000009
+S C$uart1wru16.c$31$1$60 Def000058
+S A$uart1wru16$151 Def00002B
+S A$uart1wru16$142 Def00001C
+S A$uart1wru16$133 Def000015
+S A$uart1wru16$124 Def00000B
+S C$uart1wru16.c$32$1$60 Def00005F
+S C$uart1wru16.c$23$1$60 Def000010
+S A$uart1wru16$161 Def00003C
+S A$uart1wru16$152 Def00002D
+S A$uart1wru16$143 Def00001F
+S A$uart1wru16$125 Def00000D
+S C$uart1wru16.c$24$1$60 Def000015
+S A$uart1wru16$180 Def000051
+S A$uart1wru16$162 Def00003E
+S A$uart1wru16$153 Def00002F
+S A$uart1wru16$144 Def000021
+S A$uart1wru16$135 Def000017
+S A$uart1wru16$126 Def00000E
+S A$uart1wru16$117 Def000000
+S A$uart1wru16$181 Def000054
+S A$uart1wru16$172 Def000048
+S A$uart1wru16$163 Def00003F
+S A$uart1wru16$154 Def000032
+S A$uart1wru16$145 Def000022
+S A$uart1wru16$136 Def000018
+S A$uart1wru16$118 Def000002
+S C$uart1wru16.c$26$1$60 Def00001C
+S C$uart1wru16.c$25$2$60 Def00001A
+S A$uart1wru16$191 Def00005F
+S A$uart1wru16$182 Def000056
+S A$uart1wru16$164 Def000042
+S A$uart1wru16$155 Def000034
+S A$uart1wru16$146 Def000023
+S A$uart1wru16$119 Def000005
+S A$uart1wru16$165 Def000043
+S A$uart1wru16$156 Def000036
+S A$uart1wru16$147 Def000024
+S A$uart1wru16$129 Def000010
+S A$uart1wru16$175 Def000049
+S A$uart1wru16$166 Def000044
+S A$uart1wru16$157 Def000038
+S A$uart1wru16$148 Def000025
+S A$uart1wru16$139 Def00001A
+S C$uart1wru16.c$27$2$61 Def00003C
+S A$uart1wru16$176 Def00004B
+S A$uart1wru16$167 Def000045
+S A$uart1wru16$158 Def00003A
+S A$uart1wru16$149 Def000027
+S C$uart1wru16.c$28$2$61 Def000048
+S A$uart1wru16$186 Def000058
+S A$uart1wru16$177 Def00004C
+S A$uart1wru16$168 Def000046
+S C$uart1wru16.c$29$2$61 Def000049
+S C$uart1wru16.c$21$1$0 Def000009
+S A$uart1wru16$187 Def00005A
+S A$uart1wru16$178 Def00004D
+S A$uart1wru16$169 Def000047
+S A$uart1wru16$188 Def00005D
+S A$uart1wru16$179 Def00004F
+S C$uart1wru16.c$19$0$0 Def000000
+S G$uart1_writeu16$0$0 Def000000
+S _uart1_writeu16 Def000000
+S XG$uart1_writeu16$0$0 Def00005F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 00 00 00 85 81 00 00 00 AE 82 AF 83
+R 00 00 00 16 F1 23 04 00 06 F1 23 09 00 06
+T 00 00 09 E5 00 00 00 24 FD F8 86 05 8D 82 12
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 13 00 00 8D 04
+R 00 00 00 16 02 03 00 02
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 EC 60 3E 8E 03 90 00 00 74 0A F0 E4 A3
+R 00 00 00 16 02 09 00 04
+T 00 00 24 F0 8E 82 8F 83 C0 05 C0 04 C0 03 12
+R 00 00 00 16
+T 00 00 30 00 00 AE 82 AF 83 D0 03 D0 04 D0 05 8E
+R 00 00 00 16 02 03 00 00
+T 00 00 3D 02 EA 75 F0 0A A4 FA EB C3 9A FB 1C 74
+R 00 00 00 16
+T 00 00 4A 30 2B FB C0 03 8C 82 12 00 00 15 81 80
+R 00 00 00 16 02 0B 00 01
+T 00 00 57 BF
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 8D 82 12 00 00 D0 00 00 00 22
+R 00 00 00 16 02 06 00 05 F1 23 09 00 06
+
+
+M:uart1wru16
+F:G$uart1_writeu16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Luart1wru16.uart1_writeu16$nrdig$1$59({1}SC:U),B,1,-3
+S:Luart1wru16.uart1_writeu16$val$1$59({2}SI:U),R,0,0,[r6,r7]
+S:Luart1wru16.uart1_writeu16$nrdig1$1$60({1}SC:U),R,0,0,[r5]
+S:Luart1wru16.uart1_writeu16$digit$1$60({1}SC:U),R,0,0,[r4]
+S:Luart1wru16.uart1_writeu16$v1$2$61({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wru32
+
+;!FILE libmflarge/uart0wru32.asm
+XH3
+H 1A areas 80 global symbols
+M uart0wru32
+O -mmcs51 --model-large
+S _uart0_txpoke Ref000000
+S __divulong_PARM_2 Ref000000
+S _uart0_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _uart0_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S Luart0wru32.uart0_writeu32$val$1$59 Def000001
+S _uart0_writeu32_PARM_2 Def000000
+S Luart0wru32.uart0_writeu32$nrdig$1$59 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 99 flags 20 addr 0
+S A$uart0wru32$200 Def000063
+S A$uart0wru32$201 Def000064
+S A$uart0wru32$220 Def000077
+S A$uart0wru32$211 Def00006C
+S A$uart0wru32$202 Def000065
+S A$uart0wru32$130 Def00000B
+S A$uart0wru32$221 Def000078
+S A$uart0wru32$212 Def00006F
+S A$uart0wru32$203 Def000066
+S A$uart0wru32$131 Def00000C
+S A$uart0wru32$240 Def00008C
+S A$uart0wru32$222 Def000079
+S A$uart0wru32$213 Def000070
+S A$uart0wru32$204 Def000067
+S A$uart0wru32$132 Def00000D
+S C$uart0wru32.c$31$1$60 Def000093
+S A$uart0wru32$250 Def000098
+S A$uart0wru32$241 Def00008F
+S A$uart0wru32$232 Def000083
+S A$uart0wru32$223 Def00007A
+S A$uart0wru32$214 Def000071
+S A$uart0wru32$205 Def000068
+S A$uart0wru32$160 Def000029
+S A$uart0wru32$151 Def00001F
+S A$uart0wru32$142 Def000015
+S A$uart0wru32$133 Def00000E
+S A$uart0wru32$124 Def000000
+S C$uart0wru32.c$32$1$60 Def000098
+S C$uart0wru32.c$23$1$60 Def000019
+S A$uart0wru32$242 Def000091
+S A$uart0wru32$224 Def00007B
+S A$uart0wru32$215 Def000072
+S A$uart0wru32$206 Def000069
+S A$uart0wru32$161 Def00002A
+S A$uart0wru32$143 Def000018
+S A$uart0wru32$134 Def00000F
+S A$uart0wru32$125 Def000002
+S C$uart0wru32.c$24$1$60 Def00001F
+S A$uart0wru32$225 Def00007E
+S A$uart0wru32$216 Def000073
+S A$uart0wru32$207 Def00006A
+S A$uart0wru32$180 Def00003F
+S A$uart0wru32$162 Def00002B
+S A$uart0wru32$153 Def000021
+S A$uart0wru32$135 Def000010
+S A$uart0wru32$126 Def000004
+S A$uart0wru32$235 Def000084
+S A$uart0wru32$226 Def00007F
+S A$uart0wru32$217 Def000074
+S A$uart0wru32$208 Def00006B
+S A$uart0wru32$190 Def000051
+S A$uart0wru32$181 Def000040
+S A$uart0wru32$172 Def000034
+S A$uart0wru32$163 Def00002C
+S A$uart0wru32$154 Def000022
+S A$uart0wru32$136 Def000011
+S A$uart0wru32$127 Def000006
+S C$uart0wru32.c$26$1$60 Def000034
+S C$uart0wru32.c$25$2$60 Def000024
+S A$uart0wru32$236 Def000086
+S A$uart0wru32$227 Def000080
+S A$uart0wru32$218 Def000075
+S A$uart0wru32$191 Def000053
+S A$uart0wru32$182 Def000041
+S A$uart0wru32$173 Def000037
+S A$uart0wru32$164 Def00002D
+S A$uart0wru32$146 Def000019
+S A$uart0wru32$137 Def000012
+S A$uart0wru32$128 Def000007
+S A$uart0wru32$246 Def000093
+S A$uart0wru32$237 Def000087
+S A$uart0wru32$228 Def000081
+S A$uart0wru32$219 Def000076
+S A$uart0wru32$192 Def000055
+S A$uart0wru32$183 Def000043
+S A$uart0wru32$174 Def000039
+S A$uart0wru32$165 Def00002E
+S A$uart0wru32$147 Def00001A
+S A$uart0wru32$138 Def000013
+S A$uart0wru32$129 Def00000A
+S A$uart0wru32$247 Def000095
+S A$uart0wru32$238 Def000088
+S A$uart0wru32$229 Def000082
+S A$uart0wru32$193 Def000057
+S A$uart0wru32$184 Def000045
+S A$uart0wru32$175 Def00003A
+S A$uart0wru32$166 Def00002F
+S A$uart0wru32$157 Def000024
+S A$uart0wru32$148 Def00001C
+S A$uart0wru32$139 Def000014
+S C$uart0wru32.c$27$2$61 Def00006C
+S A$uart0wru32$239 Def00008A
+S A$uart0wru32$194 Def000058
+S A$uart0wru32$185 Def000047
+S A$uart0wru32$176 Def00003B
+S A$uart0wru32$167 Def000030
+S A$uart0wru32$158 Def000027
+S C$uart0wru32.c$28$2$61 Def000083
+S A$uart0wru32$195 Def00005A
+S A$uart0wru32$186 Def000048
+S A$uart0wru32$177 Def00003C
+S A$uart0wru32$168 Def000031
+S A$uart0wru32$159 Def000028
+S C$uart0wru32.c$29$2$61 Def000084
+S C$uart0wru32.c$21$1$0 Def000015
+S A$uart0wru32$196 Def00005C
+S A$uart0wru32$187 Def00004A
+S A$uart0wru32$178 Def00003D
+S A$uart0wru32$169 Def000032
+S A$uart0wru32$197 Def00005E
+S A$uart0wru32$188 Def00004C
+S A$uart0wru32$179 Def00003E
+S A$uart0wru32$198 Def000061
+S A$uart0wru32$189 Def00004E
+S A$uart0wru32$199 Def000062
+S C$uart0wru32.c$19$0$0 Def000000
+S G$uart0_writeu32$0$0 Def000000
+S _uart0_writeu32 Def000000
+S XG$uart0_writeu32$0$0 Def000098
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 02
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 6F 90 00 01 E0 FA A3 E0 FB A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 2E FC A3 E0 FD 8A 01 90 00 00 74 0A F0 E4
+R 00 00 00 16 02 0A 00 01
+T 00 00 3B A3 F0 A3 F0 A3 F0 8A 82 8B 83 8C F0 ED
+R 00 00 00 16
+T 00 00 48 C0 07 C0 06 C0 01 12 00 00 AA 82 AB 83
+R 00 00 00 16 02 0A 00 04
+T 00 00 55 AC F0 FD D0 01 D0 06 D0 07 90 00 01 EA
+R 00 00 00 16 00 0D 00 0A
+T 00 00 62 F0 EB A3 F0 EC A3 F0 ED A3 F0 90 00 01
+R 00 00 00 16 00 0E 00 0A
+T 00 00 6F E0 FA A3 E0 FB A3 E0 FC A3 E0 FD EA 75
+R 00 00 00 16
+T 00 00 7C F0 0A A4 D3 99 F4 F9 1E 74 30 29 F9 C0
+R 00 00 00 16
+T 00 00 89 01 8E 82 12 00 00 15 81 80 8E
+R 00 00 00 16 02 07 00 00
+T 00 00 93
+R 00 00 00 16
+T 00 00 93 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 05
+
+
+M:uart0wru32
+F:G$uart0_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart0wru32.uart0_writeu32$nrdig1$1$60({1}SC:U),R,0,0,[r7]
+S:Luart0wru32.uart0_writeu32$digit$1$60({1}SC:U),R,0,0,[r6]
+S:Luart0wru32.uart0_writeu32$v1$2$61({1}SC:U),R,0,0,[r1]
+S:Luart0wru32.uart0_writeu32$nrdig$1$59({1}SC:U),F,0,0
+S:Luart0wru32.uart0_writeu32$val$1$59({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wru32
+
+;!FILE libmflarge/uart1wru32.asm
+XH3
+H 1A areas 80 global symbols
+M uart1wru32
+O -mmcs51 --model-large
+S __divulong_PARM_2 Ref000000
+S _uart1_txpoke Ref000000
+S _uart1_wait_txfree Ref000000
+S .__.ABS. Def000000
+S __divulong Ref000000
+S _uart1_txadvance Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 5 flags 40 addr 0
+S Luart1wru32.uart1_writeu32$val$1$59 Def000001
+S _uart1_writeu32_PARM_2 Def000000
+S Luart1wru32.uart1_writeu32$nrdig$1$59 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 99 flags 20 addr 0
+S A$uart1wru32$200 Def000063
+S A$uart1wru32$201 Def000064
+S A$uart1wru32$220 Def000077
+S A$uart1wru32$211 Def00006C
+S A$uart1wru32$202 Def000065
+S A$uart1wru32$130 Def00000B
+S A$uart1wru32$221 Def000078
+S A$uart1wru32$212 Def00006F
+S A$uart1wru32$203 Def000066
+S A$uart1wru32$131 Def00000C
+S A$uart1wru32$240 Def00008C
+S A$uart1wru32$222 Def000079
+S A$uart1wru32$213 Def000070
+S A$uart1wru32$204 Def000067
+S A$uart1wru32$132 Def00000D
+S C$uart1wru32.c$31$1$60 Def000093
+S A$uart1wru32$250 Def000098
+S A$uart1wru32$241 Def00008F
+S A$uart1wru32$232 Def000083
+S A$uart1wru32$223 Def00007A
+S A$uart1wru32$214 Def000071
+S A$uart1wru32$205 Def000068
+S A$uart1wru32$160 Def000029
+S A$uart1wru32$151 Def00001F
+S A$uart1wru32$142 Def000015
+S A$uart1wru32$133 Def00000E
+S A$uart1wru32$124 Def000000
+S C$uart1wru32.c$32$1$60 Def000098
+S C$uart1wru32.c$23$1$60 Def000019
+S A$uart1wru32$242 Def000091
+S A$uart1wru32$224 Def00007B
+S A$uart1wru32$215 Def000072
+S A$uart1wru32$206 Def000069
+S A$uart1wru32$161 Def00002A
+S A$uart1wru32$143 Def000018
+S A$uart1wru32$134 Def00000F
+S A$uart1wru32$125 Def000002
+S C$uart1wru32.c$24$1$60 Def00001F
+S A$uart1wru32$225 Def00007E
+S A$uart1wru32$216 Def000073
+S A$uart1wru32$207 Def00006A
+S A$uart1wru32$180 Def00003F
+S A$uart1wru32$162 Def00002B
+S A$uart1wru32$153 Def000021
+S A$uart1wru32$135 Def000010
+S A$uart1wru32$126 Def000004
+S A$uart1wru32$235 Def000084
+S A$uart1wru32$226 Def00007F
+S A$uart1wru32$217 Def000074
+S A$uart1wru32$208 Def00006B
+S A$uart1wru32$190 Def000051
+S A$uart1wru32$181 Def000040
+S A$uart1wru32$172 Def000034
+S A$uart1wru32$163 Def00002C
+S A$uart1wru32$154 Def000022
+S A$uart1wru32$136 Def000011
+S A$uart1wru32$127 Def000006
+S C$uart1wru32.c$26$1$60 Def000034
+S C$uart1wru32.c$25$2$60 Def000024
+S A$uart1wru32$236 Def000086
+S A$uart1wru32$227 Def000080
+S A$uart1wru32$218 Def000075
+S A$uart1wru32$191 Def000053
+S A$uart1wru32$182 Def000041
+S A$uart1wru32$173 Def000037
+S A$uart1wru32$164 Def00002D
+S A$uart1wru32$146 Def000019
+S A$uart1wru32$137 Def000012
+S A$uart1wru32$128 Def000007
+S A$uart1wru32$246 Def000093
+S A$uart1wru32$237 Def000087
+S A$uart1wru32$228 Def000081
+S A$uart1wru32$219 Def000076
+S A$uart1wru32$192 Def000055
+S A$uart1wru32$183 Def000043
+S A$uart1wru32$174 Def000039
+S A$uart1wru32$165 Def00002E
+S A$uart1wru32$147 Def00001A
+S A$uart1wru32$138 Def000013
+S A$uart1wru32$129 Def00000A
+S A$uart1wru32$247 Def000095
+S A$uart1wru32$238 Def000088
+S A$uart1wru32$229 Def000082
+S A$uart1wru32$193 Def000057
+S A$uart1wru32$184 Def000045
+S A$uart1wru32$175 Def00003A
+S A$uart1wru32$166 Def00002F
+S A$uart1wru32$157 Def000024
+S A$uart1wru32$148 Def00001C
+S A$uart1wru32$139 Def000014
+S C$uart1wru32.c$27$2$61 Def00006C
+S A$uart1wru32$239 Def00008A
+S A$uart1wru32$194 Def000058
+S A$uart1wru32$185 Def000047
+S A$uart1wru32$176 Def00003B
+S A$uart1wru32$167 Def000030
+S A$uart1wru32$158 Def000027
+S C$uart1wru32.c$28$2$61 Def000083
+S A$uart1wru32$195 Def00005A
+S A$uart1wru32$186 Def000048
+S A$uart1wru32$177 Def00003C
+S A$uart1wru32$168 Def000031
+S A$uart1wru32$159 Def000028
+S C$uart1wru32.c$29$2$61 Def000084
+S C$uart1wru32.c$21$1$0 Def000015
+S A$uart1wru32$196 Def00005C
+S A$uart1wru32$187 Def00004A
+S A$uart1wru32$178 Def00003D
+S A$uart1wru32$169 Def000032
+S A$uart1wru32$197 Def00005E
+S A$uart1wru32$188 Def00004C
+S A$uart1wru32$179 Def00003E
+S A$uart1wru32$198 Def000061
+S A$uart1wru32$189 Def00004E
+S A$uart1wru32$199 Def000062
+S C$uart1wru32.c$19$0$0 Def000000
+S G$uart1_writeu32$0$0 Def000000
+S _uart1_writeu32 Def000000
+S XG$uart1_writeu32$0$0 Def000098
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 01
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 01 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FF
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A F5 82 12 00 00 8F 06
+R 00 00 00 16 02 06 00 02
+T 00 00 21
+R 00 00 00 16
+T 00 00 21 EE 60 6F 90 00 01 E0 FA A3 E0 FB A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 2E FC A3 E0 FD 8A 01 90 00 00 74 0A F0 E4
+R 00 00 00 16 02 0A 00 00
+T 00 00 3B A3 F0 A3 F0 A3 F0 8A 82 8B 83 8C F0 ED
+R 00 00 00 16
+T 00 00 48 C0 07 C0 06 C0 01 12 00 00 AA 82 AB 83
+R 00 00 00 16 02 0A 00 04
+T 00 00 55 AC F0 FD D0 01 D0 06 D0 07 90 00 01 EA
+R 00 00 00 16 00 0D 00 0A
+T 00 00 62 F0 EB A3 F0 EC A3 F0 ED A3 F0 90 00 01
+R 00 00 00 16 00 0E 00 0A
+T 00 00 6F E0 FA A3 E0 FB A3 E0 FC A3 E0 FD EA 75
+R 00 00 00 16
+T 00 00 7C F0 0A A4 D3 99 F4 F9 1E 74 30 29 F9 C0
+R 00 00 00 16
+T 00 00 89 01 8E 82 12 00 00 15 81 80 8E
+R 00 00 00 16 02 07 00 01
+T 00 00 93
+R 00 00 00 16
+T 00 00 93 8F 82 12 00 00 22
+R 00 00 00 16 02 06 00 05
+
+
+M:uart1wru32
+F:G$uart1_writeu32$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Luart1wru32.uart1_writeu32$nrdig1$1$60({1}SC:U),R,0,0,[r7]
+S:Luart1wru32.uart1_writeu32$digit$1$60({1}SC:U),R,0,0,[r6]
+S:Luart1wru32.uart1_writeu32$v1$2$61({1}SC:U),R,0,0,[r1]
+S:Luart1wru32.uart1_writeu32$nrdig$1$59({1}SC:U),F,0,0
+S:Luart1wru32.uart1_writeu32$val$1$59({4}SL:U),F,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrnum16
+
+;!FILE libmflarge/uart0wrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M uart0wrnum16
+O -mmcs51 --model-large
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S G$uart0_writenum16$0$0 Def000000
+S _uart0_writenum16 Def000000
+S XG$uart0_writenum16$0$0 Def0000F6
+S C$uart0wrnum16.c$240$1$62 Def000000
+S C$uart0wrnum16.c$241$1$62 Def0000F6
+S A$uart0wrnum16$200 Def000059
+S A$uart0wrnum16$300 Def0000D9
+S A$uart0wrnum16$210 Def000065
+S A$uart0wrnum16$201 Def00005A
+S A$uart0wrnum16$120 Def000005
+S A$uart0wrnum16$310 Def0000ED
+S A$uart0wrnum16$301 Def0000DC
+S A$uart0wrnum16$220 Def000070
+S A$uart0wrnum16$211 Def000066
+S A$uart0wrnum16$202 Def00005C
+S A$uart0wrnum16$121 Def000006
+S A$uart0wrnum16$311 Def0000EF
+S A$uart0wrnum16$302 Def0000DD
+S A$uart0wrnum16$230 Def000080
+S A$uart0wrnum16$203 Def00005D
+S A$uart0wrnum16$140 Def000014
+S A$uart0wrnum16$122 Def000007
+S A$uart0wrnum16$312 Def0000F1
+S A$uart0wrnum16$303 Def0000DF
+S A$uart0wrnum16$240 Def000090
+S A$uart0wrnum16$231 Def000082
+S A$uart0wrnum16$213 Def000068
+S A$uart0wrnum16$204 Def00005E
+S A$uart0wrnum16$150 Def000026
+S A$uart0wrnum16$141 Def000016
+S A$uart0wrnum16$132 Def00000F
+S A$uart0wrnum16$123 Def000009
+S A$uart0wrnum16$241 Def000092
+S A$uart0wrnum16$205 Def000060
+S A$uart0wrnum16$142 Def000019
+S A$uart0wrnum16$314 Def0000F3
+S A$uart0wrnum16$305 Def0000E1
+S A$uart0wrnum16$242 Def000095
+S A$uart0wrnum16$233 Def000084
+S A$uart0wrnum16$224 Def000072
+S A$uart0wrnum16$215 Def00006B
+S A$uart0wrnum16$152 Def000028
+S A$uart0wrnum16$143 Def00001A
+S A$uart0wrnum16$125 Def00000B
+S A$uart0wrnum16$306 Def0000E3
+S A$uart0wrnum16$270 Def0000AE
+S A$uart0wrnum16$261 Def0000A4
+S A$uart0wrnum16$243 Def000098
+S A$uart0wrnum16$234 Def000087
+S A$uart0wrnum16$225 Def000074
+S A$uart0wrnum16$162 Def000036
+S A$uart0wrnum16$153 Def00002B
+S A$uart0wrnum16$144 Def00001B
+S A$uart0wrnum16$126 Def00000C
+S A$uart0wrnum16$117 Def000000
+S A$uart0wrnum16$316 Def0000F4
+S A$uart0wrnum16$307 Def0000E5
+S A$uart0wrnum16$280 Def0000BE
+S A$uart0wrnum16$244 Def00009A
+S A$uart0wrnum16$235 Def000088
+S A$uart0wrnum16$226 Def000076
+S A$uart0wrnum16$217 Def00006E
+S A$uart0wrnum16$208 Def000063
+S A$uart0wrnum16$163 Def000037
+S A$uart0wrnum16$154 Def00002E
+S A$uart0wrnum16$145 Def00001D
+S A$uart0wrnum16$118 Def000002
+S A$uart0wrnum16$308 Def0000E7
+S A$uart0wrnum16$290 Def0000C7
+S A$uart0wrnum16$281 Def0000C0
+S A$uart0wrnum16$272 Def0000B0
+S A$uart0wrnum16$263 Def0000A7
+S A$uart0wrnum16$245 Def00009C
+S A$uart0wrnum16$236 Def00008A
+S A$uart0wrnum16$227 Def000078
+S A$uart0wrnum16$218 Def00006F
+S A$uart0wrnum16$209 Def000064
+S A$uart0wrnum16$182 Def000047
+S A$uart0wrnum16$173 Def00003E
+S A$uart0wrnum16$164 Def000039
+S A$uart0wrnum16$155 Def000030
+S A$uart0wrnum16$146 Def00001F
+S A$uart0wrnum16$128 Def00000D
+S A$uart0wrnum16$119 Def000004
+S A$uart0wrnum16$309 Def0000EA
+S A$uart0wrnum16$291 Def0000C9
+S A$uart0wrnum16$282 Def0000C2
+S A$uart0wrnum16$273 Def0000B1
+S A$uart0wrnum16$255 Def00009F
+S A$uart0wrnum16$228 Def00007B
+S A$uart0wrnum16$192 Def00004E
+S A$uart0wrnum16$183 Def000048
+S A$uart0wrnum16$174 Def000041
+S A$uart0wrnum16$165 Def00003A
+S A$uart0wrnum16$156 Def000032
+S A$uart0wrnum16$147 Def000020
+S A$uart0wrnum16$292 Def0000CB
+S A$uart0wrnum16$265 Def0000AA
+S A$uart0wrnum16$247 Def00009E
+S A$uart0wrnum16$238 Def00008C
+S A$uart0wrnum16$229 Def00007E
+S A$uart0wrnum16$193 Def00004F
+S A$uart0wrnum16$184 Def000049
+S A$uart0wrnum16$175 Def000042
+S A$uart0wrnum16$166 Def00003C
+S A$uart0wrnum16$148 Def000022
+S A$uart0wrnum16$139 Def000011
+S A$uart0wrnum16$293 Def0000CC
+S A$uart0wrnum16$284 Def0000C4
+S A$uart0wrnum16$275 Def0000B3
+S A$uart0wrnum16$266 Def0000AB
+S A$uart0wrnum16$257 Def0000A1
+S A$uart0wrnum16$239 Def00008E
+S A$uart0wrnum16$185 Def00004A
+S A$uart0wrnum16$176 Def000044
+S A$uart0wrnum16$167 Def00003D
+S A$uart0wrnum16$158 Def000034
+S A$uart0wrnum16$149 Def000024
+S A$uart0wrnum16$294 Def0000CE
+S A$uart0wrnum16$276 Def0000B5
+S A$uart0wrnum16$258 Def0000A3
+S A$uart0wrnum16$195 Def000050
+S A$uart0wrnum16$186 Def00004C
+S A$uart0wrnum16$177 Def000046
+S A$uart0wrnum16$295 Def0000D0
+S A$uart0wrnum16$277 Def0000B7
+S A$uart0wrnum16$196 Def000052
+S A$uart0wrnum16$187 Def00004D
+S A$uart0wrnum16$296 Def0000D3
+S A$uart0wrnum16$278 Def0000B9
+S A$uart0wrnum16$269 Def0000AC
+S A$uart0wrnum16$197 Def000054
+S A$uart0wrnum16$297 Def0000D5
+S A$uart0wrnum16$279 Def0000BB
+S A$uart0wrnum16$198 Def000057
+S C$uart0wrnum16.c$25$0$0 Def000000
+S A$uart0wrnum16$298 Def0000D7
+S A$uart0wrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrnum16
+F:G$uart0_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrnum16.uart0_writenum16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrnum16.uart0_writenum16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrnum16.uart0_writenum16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrnum32
+
+;!FILE libmflarge/uart0wrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M uart0wrnum32
+O -mmcs51 --model-large
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S _uart0_writenum32 Def000000
+S XG$uart0_writenum32$0$0 Def000128
+S A$uart0wrnum32$200 Def00005A
+S A$uart0wrnum32$300 Def0000D4
+S A$uart0wrnum32$210 Def000062
+S A$uart0wrnum32$201 Def00005C
+S A$uart0wrnum32$120 Def000005
+S C$uart0wrnum32.c$276$1$62 Def000000
+S A$uart0wrnum32$310 Def0000DD
+S A$uart0wrnum32$301 Def0000D5
+S A$uart0wrnum32$220 Def00006A
+S A$uart0wrnum32$211 Def000063
+S A$uart0wrnum32$130 Def000010
+S A$uart0wrnum32$121 Def000007
+S C$uart0wrnum32.c$277$1$62 Def000128
+S A$uart0wrnum32$311 Def0000DF
+S A$uart0wrnum32$230 Def00007B
+S A$uart0wrnum32$221 Def00006C
+S A$uart0wrnum32$122 Def000008
+S A$uart0wrnum32$330 Def0000FA
+S A$uart0wrnum32$312 Def0000E1
+S A$uart0wrnum32$240 Def000087
+S A$uart0wrnum32$231 Def00007C
+S A$uart0wrnum32$222 Def00006E
+S A$uart0wrnum32$150 Def000024
+S A$uart0wrnum32$141 Def000014
+S A$uart0wrnum32$123 Def000009
+S A$uart0wrnum32$340 Def00010D
+S A$uart0wrnum32$331 Def0000FD
+S A$uart0wrnum32$313 Def0000E3
+S A$uart0wrnum32$304 Def0000D6
+S A$uart0wrnum32$250 Def000092
+S A$uart0wrnum32$241 Def000088
+S A$uart0wrnum32$232 Def00007E
+S A$uart0wrnum32$223 Def00006F
+S A$uart0wrnum32$160 Def000030
+S A$uart0wrnum32$151 Def000026
+S A$uart0wrnum32$142 Def000017
+S A$uart0wrnum32$124 Def00000A
+S A$uart0wrnum32$350 Def00011F
+S A$uart0wrnum32$341 Def00010F
+S A$uart0wrnum32$332 Def0000FF
+S A$uart0wrnum32$314 Def0000E5
+S A$uart0wrnum32$305 Def0000D8
+S A$uart0wrnum32$260 Def0000A2
+S A$uart0wrnum32$233 Def00007F
+S A$uart0wrnum32$224 Def000072
+S A$uart0wrnum32$206 Def00005D
+S A$uart0wrnum32$161 Def000033
+S A$uart0wrnum32$152 Def000027
+S A$uart0wrnum32$143 Def000018
+S A$uart0wrnum32$134 Def000012
+S A$uart0wrnum32$125 Def00000C
+S A$uart0wrnum32$116 Def000000
+S A$uart0wrnum32$351 Def000121
+S A$uart0wrnum32$342 Def000111
+S A$uart0wrnum32$333 Def000101
+S A$uart0wrnum32$324 Def0000EF
+S A$uart0wrnum32$315 Def0000E8
+S A$uart0wrnum32$270 Def0000B4
+S A$uart0wrnum32$261 Def0000A4
+S A$uart0wrnum32$243 Def00008A
+S A$uart0wrnum32$234 Def000080
+S A$uart0wrnum32$225 Def000073
+S A$uart0wrnum32$216 Def000064
+S A$uart0wrnum32$207 Def00005E
+S A$uart0wrnum32$162 Def000036
+S A$uart0wrnum32$153 Def000028
+S A$uart0wrnum32$144 Def00001B
+S A$uart0wrnum32$117 Def000001
+S A$uart0wrnum32$352 Def000123
+S A$uart0wrnum32$325 Def0000F1
+S A$uart0wrnum32$316 Def0000EA
+S A$uart0wrnum32$307 Def0000DA
+S A$uart0wrnum32$280 Def0000C6
+S A$uart0wrnum32$235 Def000082
+S A$uart0wrnum32$226 Def000075
+S A$uart0wrnum32$208 Def00005F
+S A$uart0wrnum32$190 Def00004E
+S A$uart0wrnum32$172 Def000040
+S A$uart0wrnum32$163 Def000038
+S A$uart0wrnum32$154 Def000029
+S A$uart0wrnum32$145 Def00001C
+S A$uart0wrnum32$127 Def00000E
+S A$uart0wrnum32$335 Def000103
+S A$uart0wrnum32$326 Def0000F3
+S A$uart0wrnum32$317 Def0000EC
+S A$uart0wrnum32$308 Def0000DB
+S A$uart0wrnum32$290 Def0000C9
+S A$uart0wrnum32$263 Def0000A6
+S A$uart0wrnum32$254 Def000094
+S A$uart0wrnum32$245 Def00008D
+S A$uart0wrnum32$227 Def000077
+S A$uart0wrnum32$218 Def000066
+S A$uart0wrnum32$209 Def000060
+S A$uart0wrnum32$191 Def000050
+S A$uart0wrnum32$173 Def000041
+S A$uart0wrnum32$164 Def00003A
+S A$uart0wrnum32$155 Def00002A
+S A$uart0wrnum32$146 Def00001D
+S A$uart0wrnum32$128 Def00000F
+S A$uart0wrnum32$119 Def000003
+S A$uart0wrnum32$354 Def000125
+S A$uart0wrnum32$345 Def000113
+S A$uart0wrnum32$336 Def000106
+S A$uart0wrnum32$327 Def0000F5
+S A$uart0wrnum32$282 Def0000C8
+S A$uart0wrnum32$273 Def0000B6
+S A$uart0wrnum32$264 Def0000A9
+S A$uart0wrnum32$255 Def000096
+S A$uart0wrnum32$228 Def000079
+S A$uart0wrnum32$219 Def000068
+S A$uart0wrnum32$174 Def000043
+S A$uart0wrnum32$165 Def00003B
+S A$uart0wrnum32$156 Def00002B
+S A$uart0wrnum32$147 Def00001F
+S A$uart0wrnum32$346 Def000115
+S A$uart0wrnum32$337 Def000107
+S A$uart0wrnum32$328 Def0000F6
+S A$uart0wrnum32$319 Def0000EE
+S A$uart0wrnum32$292 Def0000CB
+S A$uart0wrnum32$274 Def0000B8
+S A$uart0wrnum32$265 Def0000AA
+S A$uart0wrnum32$256 Def000098
+S A$uart0wrnum32$247 Def000090
+S A$uart0wrnum32$238 Def000085
+S A$uart0wrnum32$193 Def000051
+S A$uart0wrnum32$175 Def000044
+S A$uart0wrnum32$166 Def00003C
+S A$uart0wrnum32$157 Def00002C
+S A$uart0wrnum32$148 Def000021
+S A$uart0wrnum32$356 Def000126
+S A$uart0wrnum32$347 Def000117
+S A$uart0wrnum32$338 Def000109
+S A$uart0wrnum32$329 Def0000F8
+S A$uart0wrnum32$293 Def0000CD
+S A$uart0wrnum32$275 Def0000BA
+S A$uart0wrnum32$266 Def0000AC
+S A$uart0wrnum32$257 Def00009A
+S A$uart0wrnum32$248 Def000091
+S A$uart0wrnum32$239 Def000086
+S A$uart0wrnum32$194 Def000052
+S A$uart0wrnum32$176 Def000046
+S A$uart0wrnum32$158 Def00002E
+S A$uart0wrnum32$149 Def000022
+S A$uart0wrnum32$348 Def000119
+S A$uart0wrnum32$339 Def00010B
+S A$uart0wrnum32$276 Def0000BC
+S A$uart0wrnum32$267 Def0000AE
+S A$uart0wrnum32$258 Def00009D
+S A$uart0wrnum32$195 Def000054
+S A$uart0wrnum32$177 Def000047
+S A$uart0wrnum32$168 Def00003E
+S A$uart0wrnum32$349 Def00011C
+S A$uart0wrnum32$277 Def0000BF
+S A$uart0wrnum32$268 Def0000B0
+S A$uart0wrnum32$259 Def0000A0
+S A$uart0wrnum32$196 Def000056
+S A$uart0wrnum32$187 Def000048
+S A$uart0wrnum32$296 Def0000CE
+S A$uart0wrnum32$278 Def0000C2
+S A$uart0wrnum32$269 Def0000B2
+S A$uart0wrnum32$188 Def00004B
+S A$uart0wrnum32$279 Def0000C4
+S A$uart0wrnum32$198 Def000057
+S A$uart0wrnum32$189 Def00004C
+S C$uart0wrnum32.c$25$0$0 Def000000
+S A$uart0wrnum32$298 Def0000D1
+S A$uart0wrnum32$199 Def000058
+S G$uart0_writenum32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:uart0wrnum32
+F:G$uart0_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrnum32.uart0_writenum32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrnum32.uart0_writenum32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrnum32.uart0_writenum32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhex16
+
+;!FILE libmflarge/uart0wrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M uart0wrhex16
+O -mmcs51 --model-large
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S _uart0_writehex16 Def000000
+S XG$uart0_writehex16$0$0 Def000111
+S C$uart0wrhex16.c$264$1$62 Def000000
+S C$uart0wrhex16.c$265$1$62 Def000111
+S A$uart0wrhex16$200 Def000058
+S A$uart0wrhex16$201 Def000059
+S A$uart0wrhex16$120 Def000005
+S A$uart0wrhex16$310 Def0000DB
+S A$uart0wrhex16$301 Def0000CB
+S A$uart0wrhex16$220 Def000069
+S A$uart0wrhex16$211 Def000063
+S A$uart0wrhex16$202 Def00005B
+S A$uart0wrhex16$121 Def000006
+S A$uart0wrhex16$320 Def0000E4
+S A$uart0wrhex16$311 Def0000DD
+S A$uart0wrhex16$302 Def0000CC
+S A$uart0wrhex16$230 Def000075
+S A$uart0wrhex16$221 Def00006B
+S A$uart0wrhex16$203 Def00005D
+S A$uart0wrhex16$140 Def000014
+S A$uart0wrhex16$122 Def000007
+S A$uart0wrhex16$330 Def0000F7
+S A$uart0wrhex16$321 Def0000E6
+S A$uart0wrhex16$240 Def000081
+S A$uart0wrhex16$231 Def000077
+S A$uart0wrhex16$150 Def000026
+S A$uart0wrhex16$141 Def000016
+S A$uart0wrhex16$132 Def00000F
+S A$uart0wrhex16$123 Def000009
+S A$uart0wrhex16$340 Def00010A
+S A$uart0wrhex16$331 Def0000F8
+S A$uart0wrhex16$322 Def0000E7
+S A$uart0wrhex16$313 Def0000DF
+S A$uart0wrhex16$304 Def0000CE
+S A$uart0wrhex16$232 Def000078
+S A$uart0wrhex16$223 Def00006D
+S A$uart0wrhex16$205 Def00005F
+S A$uart0wrhex16$142 Def000019
+S A$uart0wrhex16$341 Def00010C
+S A$uart0wrhex16$332 Def0000FA
+S A$uart0wrhex16$323 Def0000E9
+S A$uart0wrhex16$305 Def0000D0
+S A$uart0wrhex16$260 Def00009D
+S A$uart0wrhex16$242 Def000083
+S A$uart0wrhex16$233 Def000079
+S A$uart0wrhex16$224 Def00006F
+S A$uart0wrhex16$152 Def000028
+S A$uart0wrhex16$143 Def00001A
+S A$uart0wrhex16$125 Def00000B
+S A$uart0wrhex16$324 Def0000EB
+S A$uart0wrhex16$306 Def0000D2
+S A$uart0wrhex16$270 Def0000AD
+S A$uart0wrhex16$234 Def00007B
+S A$uart0wrhex16$225 Def000072
+S A$uart0wrhex16$207 Def000060
+S A$uart0wrhex16$162 Def000036
+S A$uart0wrhex16$153 Def00002B
+S A$uart0wrhex16$144 Def00001B
+S A$uart0wrhex16$126 Def00000C
+S A$uart0wrhex16$117 Def000000
+S A$uart0wrhex16$343 Def00010E
+S A$uart0wrhex16$334 Def0000FC
+S A$uart0wrhex16$325 Def0000EE
+S A$uart0wrhex16$307 Def0000D4
+S A$uart0wrhex16$271 Def0000B0
+S A$uart0wrhex16$262 Def00009F
+S A$uart0wrhex16$253 Def00008D
+S A$uart0wrhex16$244 Def000086
+S A$uart0wrhex16$208 Def000062
+S A$uart0wrhex16$163 Def000037
+S A$uart0wrhex16$154 Def00002E
+S A$uart0wrhex16$145 Def00001D
+S A$uart0wrhex16$118 Def000002
+S A$uart0wrhex16$335 Def0000FE
+S A$uart0wrhex16$326 Def0000F0
+S A$uart0wrhex16$308 Def0000D6
+S A$uart0wrhex16$290 Def0000BF
+S A$uart0wrhex16$272 Def0000B3
+S A$uart0wrhex16$263 Def0000A2
+S A$uart0wrhex16$254 Def00008F
+S A$uart0wrhex16$227 Def000074
+S A$uart0wrhex16$218 Def000065
+S A$uart0wrhex16$182 Def000047
+S A$uart0wrhex16$173 Def00003E
+S A$uart0wrhex16$164 Def000039
+S A$uart0wrhex16$155 Def000030
+S A$uart0wrhex16$146 Def00001F
+S A$uart0wrhex16$128 Def00000D
+S A$uart0wrhex16$119 Def000004
+S A$uart0wrhex16$345 Def00010F
+S A$uart0wrhex16$336 Def000100
+S A$uart0wrhex16$327 Def0000F2
+S A$uart0wrhex16$318 Def0000E0
+S A$uart0wrhex16$309 Def0000D9
+S A$uart0wrhex16$273 Def0000B5
+S A$uart0wrhex16$264 Def0000A3
+S A$uart0wrhex16$255 Def000091
+S A$uart0wrhex16$246 Def000089
+S A$uart0wrhex16$237 Def00007E
+S A$uart0wrhex16$219 Def000067
+S A$uart0wrhex16$192 Def00004E
+S A$uart0wrhex16$183 Def000048
+S A$uart0wrhex16$174 Def000041
+S A$uart0wrhex16$165 Def00003A
+S A$uart0wrhex16$156 Def000032
+S A$uart0wrhex16$147 Def000020
+S A$uart0wrhex16$337 Def000102
+S A$uart0wrhex16$319 Def0000E2
+S A$uart0wrhex16$292 Def0000C2
+S A$uart0wrhex16$274 Def0000B7
+S A$uart0wrhex16$265 Def0000A5
+S A$uart0wrhex16$256 Def000093
+S A$uart0wrhex16$247 Def00008A
+S A$uart0wrhex16$238 Def00007F
+S A$uart0wrhex16$193 Def00004F
+S A$uart0wrhex16$184 Def000049
+S A$uart0wrhex16$175 Def000042
+S A$uart0wrhex16$166 Def00003C
+S A$uart0wrhex16$148 Def000022
+S A$uart0wrhex16$139 Def000011
+S A$uart0wrhex16$338 Def000105
+S A$uart0wrhex16$329 Def0000F4
+S A$uart0wrhex16$284 Def0000BA
+S A$uart0wrhex16$257 Def000096
+S A$uart0wrhex16$239 Def000080
+S A$uart0wrhex16$194 Def000050
+S A$uart0wrhex16$185 Def00004A
+S A$uart0wrhex16$176 Def000044
+S A$uart0wrhex16$167 Def00003D
+S A$uart0wrhex16$158 Def000034
+S A$uart0wrhex16$149 Def000024
+S A$uart0wrhex16$339 Def000108
+S A$uart0wrhex16$294 Def0000C5
+S A$uart0wrhex16$276 Def0000B9
+S A$uart0wrhex16$267 Def0000A7
+S A$uart0wrhex16$258 Def000099
+S A$uart0wrhex16$249 Def00008B
+S A$uart0wrhex16$195 Def000051
+S A$uart0wrhex16$186 Def00004C
+S A$uart0wrhex16$177 Def000046
+S A$uart0wrhex16$295 Def0000C6
+S A$uart0wrhex16$286 Def0000BC
+S A$uart0wrhex16$268 Def0000A9
+S A$uart0wrhex16$259 Def00009B
+S A$uart0wrhex16$196 Def000052
+S A$uart0wrhex16$187 Def00004D
+S A$uart0wrhex16$287 Def0000BE
+S A$uart0wrhex16$269 Def0000AB
+S A$uart0wrhex16$197 Def000054
+S A$uart0wrhex16$198 Def000056
+S C$uart0wrhex16.c$25$0$0 Def000000
+S A$uart0wrhex16$298 Def0000C7
+S A$uart0wrhex16$299 Def0000C9
+S G$uart0_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrhex16
+F:G$uart0_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrhex16.uart0_writehex16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrhex16.uart0_writehex16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrhex16.uart0_writehex16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart0wrhex32
+
+;!FILE libmflarge/uart0wrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M uart0wrhex32
+O -mmcs51 --model-large
+S _uart0_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S XG$uart0_writehex32$0$0 Def000127
+S C$uart0wrhex32.c$282$1$62 Def000000
+S C$uart0wrhex32.c$283$1$62 Def000127
+S A$uart0wrhex32$210 Def000062
+S A$uart0wrhex32$120 Def000005
+S A$uart0wrhex32$310 Def0000D5
+S A$uart0wrhex32$220 Def00006F
+S A$uart0wrhex32$211 Def000063
+S A$uart0wrhex32$202 Def000058
+S A$uart0wrhex32$130 Def000010
+S A$uart0wrhex32$121 Def000007
+S A$uart0wrhex32$221 Def000070
+S A$uart0wrhex32$212 Def000065
+S A$uart0wrhex32$203 Def000059
+S A$uart0wrhex32$122 Def000008
+S A$uart0wrhex32$330 Def0000F1
+S A$uart0wrhex32$321 Def0000E1
+S A$uart0wrhex32$312 Def0000D8
+S A$uart0wrhex32$240 Def00007F
+S A$uart0wrhex32$231 Def000079
+S A$uart0wrhex32$222 Def000072
+S A$uart0wrhex32$213 Def000067
+S A$uart0wrhex32$204 Def00005A
+S A$uart0wrhex32$150 Def000024
+S A$uart0wrhex32$141 Def000014
+S A$uart0wrhex32$123 Def000009
+S A$uart0wrhex32$340 Def0000FA
+S A$uart0wrhex32$331 Def0000F3
+S A$uart0wrhex32$322 Def0000E2
+S A$uart0wrhex32$304 Def0000D0
+S A$uart0wrhex32$250 Def00008B
+S A$uart0wrhex32$241 Def000081
+S A$uart0wrhex32$223 Def000073
+S A$uart0wrhex32$205 Def00005B
+S A$uart0wrhex32$160 Def000030
+S A$uart0wrhex32$151 Def000026
+S A$uart0wrhex32$142 Def000017
+S A$uart0wrhex32$124 Def00000A
+S A$uart0wrhex32$350 Def00010D
+S A$uart0wrhex32$341 Def0000FC
+S A$uart0wrhex32$314 Def0000DB
+S A$uart0wrhex32$260 Def000097
+S A$uart0wrhex32$251 Def00008D
+S A$uart0wrhex32$215 Def000069
+S A$uart0wrhex32$206 Def00005C
+S A$uart0wrhex32$161 Def000033
+S A$uart0wrhex32$152 Def000027
+S A$uart0wrhex32$143 Def000018
+S A$uart0wrhex32$134 Def000012
+S A$uart0wrhex32$125 Def00000C
+S A$uart0wrhex32$116 Def000000
+S A$uart0wrhex32$360 Def000120
+S A$uart0wrhex32$351 Def00010E
+S A$uart0wrhex32$342 Def0000FD
+S A$uart0wrhex32$333 Def0000F5
+S A$uart0wrhex32$324 Def0000E4
+S A$uart0wrhex32$315 Def0000DC
+S A$uart0wrhex32$306 Def0000D2
+S A$uart0wrhex32$252 Def00008E
+S A$uart0wrhex32$243 Def000083
+S A$uart0wrhex32$225 Def000075
+S A$uart0wrhex32$216 Def00006A
+S A$uart0wrhex32$207 Def00005E
+S A$uart0wrhex32$162 Def000036
+S A$uart0wrhex32$153 Def000028
+S A$uart0wrhex32$144 Def00001B
+S A$uart0wrhex32$117 Def000001
+S A$uart0wrhex32$361 Def000122
+S A$uart0wrhex32$352 Def000110
+S A$uart0wrhex32$343 Def0000FF
+S A$uart0wrhex32$325 Def0000E6
+S A$uart0wrhex32$307 Def0000D4
+S A$uart0wrhex32$280 Def0000B3
+S A$uart0wrhex32$262 Def000099
+S A$uart0wrhex32$253 Def00008F
+S A$uart0wrhex32$244 Def000085
+S A$uart0wrhex32$217 Def00006C
+S A$uart0wrhex32$208 Def000060
+S A$uart0wrhex32$172 Def000040
+S A$uart0wrhex32$163 Def000038
+S A$uart0wrhex32$154 Def000029
+S A$uart0wrhex32$145 Def00001C
+S A$uart0wrhex32$127 Def00000E
+S A$uart0wrhex32$344 Def000101
+S A$uart0wrhex32$326 Def0000E8
+S A$uart0wrhex32$290 Def0000C3
+S A$uart0wrhex32$254 Def000091
+S A$uart0wrhex32$245 Def000088
+S A$uart0wrhex32$227 Def000076
+S A$uart0wrhex32$218 Def00006D
+S A$uart0wrhex32$173 Def000041
+S A$uart0wrhex32$164 Def00003A
+S A$uart0wrhex32$155 Def00002A
+S A$uart0wrhex32$146 Def00001D
+S A$uart0wrhex32$128 Def00000F
+S A$uart0wrhex32$119 Def000003
+S A$uart0wrhex32$363 Def000124
+S A$uart0wrhex32$354 Def000112
+S A$uart0wrhex32$345 Def000104
+S A$uart0wrhex32$327 Def0000EA
+S A$uart0wrhex32$318 Def0000DD
+S A$uart0wrhex32$291 Def0000C6
+S A$uart0wrhex32$282 Def0000B5
+S A$uart0wrhex32$273 Def0000A3
+S A$uart0wrhex32$264 Def00009C
+S A$uart0wrhex32$228 Def000078
+S A$uart0wrhex32$192 Def000051
+S A$uart0wrhex32$183 Def000048
+S A$uart0wrhex32$174 Def000043
+S A$uart0wrhex32$165 Def00003B
+S A$uart0wrhex32$156 Def00002B
+S A$uart0wrhex32$147 Def00001F
+S A$uart0wrhex32$355 Def000114
+S A$uart0wrhex32$346 Def000106
+S A$uart0wrhex32$328 Def0000EC
+S A$uart0wrhex32$319 Def0000DF
+S A$uart0wrhex32$292 Def0000C9
+S A$uart0wrhex32$283 Def0000B8
+S A$uart0wrhex32$274 Def0000A5
+S A$uart0wrhex32$247 Def00008A
+S A$uart0wrhex32$238 Def00007B
+S A$uart0wrhex32$193 Def000052
+S A$uart0wrhex32$184 Def00004B
+S A$uart0wrhex32$175 Def000044
+S A$uart0wrhex32$166 Def00003C
+S A$uart0wrhex32$157 Def00002C
+S A$uart0wrhex32$148 Def000021
+S A$uart0wrhex32$365 Def000125
+S A$uart0wrhex32$356 Def000116
+S A$uart0wrhex32$347 Def000108
+S A$uart0wrhex32$338 Def0000F6
+S A$uart0wrhex32$329 Def0000EF
+S A$uart0wrhex32$293 Def0000CB
+S A$uart0wrhex32$284 Def0000B9
+S A$uart0wrhex32$275 Def0000A7
+S A$uart0wrhex32$266 Def00009F
+S A$uart0wrhex32$257 Def000094
+S A$uart0wrhex32$239 Def00007D
+S A$uart0wrhex32$194 Def000053
+S A$uart0wrhex32$185 Def00004C
+S A$uart0wrhex32$176 Def000046
+S A$uart0wrhex32$158 Def00002E
+S A$uart0wrhex32$149 Def000022
+S A$uart0wrhex32$357 Def000118
+S A$uart0wrhex32$339 Def0000F8
+S A$uart0wrhex32$294 Def0000CD
+S A$uart0wrhex32$285 Def0000BB
+S A$uart0wrhex32$276 Def0000A9
+S A$uart0wrhex32$267 Def0000A0
+S A$uart0wrhex32$258 Def000095
+S A$uart0wrhex32$195 Def000054
+S A$uart0wrhex32$186 Def00004E
+S A$uart0wrhex32$177 Def000047
+S A$uart0wrhex32$168 Def00003E
+S A$uart0wrhex32$358 Def00011B
+S A$uart0wrhex32$349 Def00010A
+S A$uart0wrhex32$277 Def0000AC
+S A$uart0wrhex32$259 Def000096
+S A$uart0wrhex32$196 Def000056
+S A$uart0wrhex32$187 Def000050
+S A$uart0wrhex32$359 Def00011E
+S A$uart0wrhex32$296 Def0000CF
+S A$uart0wrhex32$287 Def0000BD
+S A$uart0wrhex32$278 Def0000AF
+S A$uart0wrhex32$269 Def0000A1
+S A$uart0wrhex32$197 Def000057
+S A$uart0wrhex32$288 Def0000BF
+S A$uart0wrhex32$279 Def0000B1
+S C$uart0wrhex32.c$25$0$0 Def000000
+S A$uart0wrhex32$289 Def0000C1
+S G$uart0_writehex32$0$0 Def000000
+S _uart0_writehex32 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart0wrhex32
+F:G$uart0_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart0wrhex32.uart0_writehex32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart0wrhex32.uart0_writehex32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart0wrhex32.uart0_writehex32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart0_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart0_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart0_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart0_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrnum16
+
+;!FILE libmflarge/uart1wrnum16.asm
+XH3
+H 1A areas 94 global symbols
+M uart1wrnum16
+O -mmcs51 --model-large
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num16_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F6 flags 20 addr 0
+S G$uart1_writenum16$0$0 Def000000
+S _uart1_writenum16 Def000000
+S XG$uart1_writenum16$0$0 Def0000F6
+S C$uart1wrnum16.c$240$1$62 Def000000
+S C$uart1wrnum16.c$241$1$62 Def0000F6
+S A$uart1wrnum16$200 Def000059
+S A$uart1wrnum16$300 Def0000D9
+S A$uart1wrnum16$210 Def000065
+S A$uart1wrnum16$201 Def00005A
+S A$uart1wrnum16$120 Def000005
+S A$uart1wrnum16$310 Def0000ED
+S A$uart1wrnum16$301 Def0000DC
+S A$uart1wrnum16$220 Def000070
+S A$uart1wrnum16$211 Def000066
+S A$uart1wrnum16$202 Def00005C
+S A$uart1wrnum16$121 Def000006
+S A$uart1wrnum16$311 Def0000EF
+S A$uart1wrnum16$302 Def0000DD
+S A$uart1wrnum16$230 Def000080
+S A$uart1wrnum16$203 Def00005D
+S A$uart1wrnum16$140 Def000014
+S A$uart1wrnum16$122 Def000007
+S A$uart1wrnum16$312 Def0000F1
+S A$uart1wrnum16$303 Def0000DF
+S A$uart1wrnum16$240 Def000090
+S A$uart1wrnum16$231 Def000082
+S A$uart1wrnum16$213 Def000068
+S A$uart1wrnum16$204 Def00005E
+S A$uart1wrnum16$150 Def000026
+S A$uart1wrnum16$141 Def000016
+S A$uart1wrnum16$132 Def00000F
+S A$uart1wrnum16$123 Def000009
+S A$uart1wrnum16$241 Def000092
+S A$uart1wrnum16$205 Def000060
+S A$uart1wrnum16$142 Def000019
+S A$uart1wrnum16$314 Def0000F3
+S A$uart1wrnum16$305 Def0000E1
+S A$uart1wrnum16$242 Def000095
+S A$uart1wrnum16$233 Def000084
+S A$uart1wrnum16$224 Def000072
+S A$uart1wrnum16$215 Def00006B
+S A$uart1wrnum16$152 Def000028
+S A$uart1wrnum16$143 Def00001A
+S A$uart1wrnum16$125 Def00000B
+S A$uart1wrnum16$306 Def0000E3
+S A$uart1wrnum16$270 Def0000AE
+S A$uart1wrnum16$261 Def0000A4
+S A$uart1wrnum16$243 Def000098
+S A$uart1wrnum16$234 Def000087
+S A$uart1wrnum16$225 Def000074
+S A$uart1wrnum16$162 Def000036
+S A$uart1wrnum16$153 Def00002B
+S A$uart1wrnum16$144 Def00001B
+S A$uart1wrnum16$126 Def00000C
+S A$uart1wrnum16$117 Def000000
+S A$uart1wrnum16$316 Def0000F4
+S A$uart1wrnum16$307 Def0000E5
+S A$uart1wrnum16$280 Def0000BE
+S A$uart1wrnum16$244 Def00009A
+S A$uart1wrnum16$235 Def000088
+S A$uart1wrnum16$226 Def000076
+S A$uart1wrnum16$217 Def00006E
+S A$uart1wrnum16$208 Def000063
+S A$uart1wrnum16$163 Def000037
+S A$uart1wrnum16$154 Def00002E
+S A$uart1wrnum16$145 Def00001D
+S A$uart1wrnum16$118 Def000002
+S A$uart1wrnum16$308 Def0000E7
+S A$uart1wrnum16$290 Def0000C7
+S A$uart1wrnum16$281 Def0000C0
+S A$uart1wrnum16$272 Def0000B0
+S A$uart1wrnum16$263 Def0000A7
+S A$uart1wrnum16$245 Def00009C
+S A$uart1wrnum16$236 Def00008A
+S A$uart1wrnum16$227 Def000078
+S A$uart1wrnum16$218 Def00006F
+S A$uart1wrnum16$209 Def000064
+S A$uart1wrnum16$182 Def000047
+S A$uart1wrnum16$173 Def00003E
+S A$uart1wrnum16$164 Def000039
+S A$uart1wrnum16$155 Def000030
+S A$uart1wrnum16$146 Def00001F
+S A$uart1wrnum16$128 Def00000D
+S A$uart1wrnum16$119 Def000004
+S A$uart1wrnum16$309 Def0000EA
+S A$uart1wrnum16$291 Def0000C9
+S A$uart1wrnum16$282 Def0000C2
+S A$uart1wrnum16$273 Def0000B1
+S A$uart1wrnum16$255 Def00009F
+S A$uart1wrnum16$228 Def00007B
+S A$uart1wrnum16$192 Def00004E
+S A$uart1wrnum16$183 Def000048
+S A$uart1wrnum16$174 Def000041
+S A$uart1wrnum16$165 Def00003A
+S A$uart1wrnum16$156 Def000032
+S A$uart1wrnum16$147 Def000020
+S A$uart1wrnum16$292 Def0000CB
+S A$uart1wrnum16$265 Def0000AA
+S A$uart1wrnum16$247 Def00009E
+S A$uart1wrnum16$238 Def00008C
+S A$uart1wrnum16$229 Def00007E
+S A$uart1wrnum16$193 Def00004F
+S A$uart1wrnum16$184 Def000049
+S A$uart1wrnum16$175 Def000042
+S A$uart1wrnum16$166 Def00003C
+S A$uart1wrnum16$148 Def000022
+S A$uart1wrnum16$139 Def000011
+S A$uart1wrnum16$293 Def0000CC
+S A$uart1wrnum16$284 Def0000C4
+S A$uart1wrnum16$275 Def0000B3
+S A$uart1wrnum16$266 Def0000AB
+S A$uart1wrnum16$257 Def0000A1
+S A$uart1wrnum16$239 Def00008E
+S A$uart1wrnum16$185 Def00004A
+S A$uart1wrnum16$176 Def000044
+S A$uart1wrnum16$167 Def00003D
+S A$uart1wrnum16$158 Def000034
+S A$uart1wrnum16$149 Def000024
+S A$uart1wrnum16$294 Def0000CE
+S A$uart1wrnum16$276 Def0000B5
+S A$uart1wrnum16$258 Def0000A3
+S A$uart1wrnum16$195 Def000050
+S A$uart1wrnum16$186 Def00004C
+S A$uart1wrnum16$177 Def000046
+S A$uart1wrnum16$295 Def0000D0
+S A$uart1wrnum16$277 Def0000B7
+S A$uart1wrnum16$196 Def000052
+S A$uart1wrnum16$187 Def00004D
+S A$uart1wrnum16$296 Def0000D3
+S A$uart1wrnum16$278 Def0000B9
+S A$uart1wrnum16$269 Def0000AC
+S A$uart1wrnum16$197 Def000054
+S A$uart1wrnum16$297 Def0000D5
+S A$uart1wrnum16$279 Def0000BB
+S A$uart1wrnum16$198 Def000057
+S C$uart1wrnum16.c$25$0$0 Def000000
+S A$uart1wrnum16$298 Def0000D7
+S A$uart1wrnum16$289 Def0000C5
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 03
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FC 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB FC 74 04 C0 E0 12 00 00 15 81 EC 70
+R 00 00 00 16 02 0A 00 02
+T 00 00 5B 48 EB 14 60 44 20 00 00 00 41 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 66 40 37 20 00 00 00 39 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 6F FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 72
+R 00 00 00 16
+T 00 00 72 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 7F 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 8A 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 96 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 9F
+R 00 00 00 16
+T 00 00 9F DB AD 8A 82 22
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 AC
+R 00 00 00 16
+T 00 00 AC 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 B9 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 C5
+R 00 00 00 16
+T 00 00 C5 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 D1 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 00 DC EB 24 FC 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 00 E9 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrnum16
+F:G$uart1_writenum16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrnum16.uart1_writenum16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrnum16.uart1_writenum16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrnum16.uart1_writenum16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrnum32
+
+;!FILE libmflarge/uart1wrnum32.asm
+XH3
+H 1A areas B4 global symbols
+M uart1wrnum32
+O -mmcs51 --model-large
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _libmf_num32_digit Ref000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 128 flags 20 addr 0
+S _uart1_writenum32 Def000000
+S XG$uart1_writenum32$0$0 Def000128
+S A$uart1wrnum32$200 Def00005A
+S A$uart1wrnum32$300 Def0000D4
+S A$uart1wrnum32$210 Def000062
+S A$uart1wrnum32$201 Def00005C
+S A$uart1wrnum32$120 Def000005
+S C$uart1wrnum32.c$276$1$62 Def000000
+S A$uart1wrnum32$310 Def0000DD
+S A$uart1wrnum32$301 Def0000D5
+S A$uart1wrnum32$220 Def00006A
+S A$uart1wrnum32$211 Def000063
+S A$uart1wrnum32$130 Def000010
+S A$uart1wrnum32$121 Def000007
+S C$uart1wrnum32.c$277$1$62 Def000128
+S A$uart1wrnum32$311 Def0000DF
+S A$uart1wrnum32$230 Def00007B
+S A$uart1wrnum32$221 Def00006C
+S A$uart1wrnum32$122 Def000008
+S A$uart1wrnum32$330 Def0000FA
+S A$uart1wrnum32$312 Def0000E1
+S A$uart1wrnum32$240 Def000087
+S A$uart1wrnum32$231 Def00007C
+S A$uart1wrnum32$222 Def00006E
+S A$uart1wrnum32$150 Def000024
+S A$uart1wrnum32$141 Def000014
+S A$uart1wrnum32$123 Def000009
+S A$uart1wrnum32$340 Def00010D
+S A$uart1wrnum32$331 Def0000FD
+S A$uart1wrnum32$313 Def0000E3
+S A$uart1wrnum32$304 Def0000D6
+S A$uart1wrnum32$250 Def000092
+S A$uart1wrnum32$241 Def000088
+S A$uart1wrnum32$232 Def00007E
+S A$uart1wrnum32$223 Def00006F
+S A$uart1wrnum32$160 Def000030
+S A$uart1wrnum32$151 Def000026
+S A$uart1wrnum32$142 Def000017
+S A$uart1wrnum32$124 Def00000A
+S A$uart1wrnum32$350 Def00011F
+S A$uart1wrnum32$341 Def00010F
+S A$uart1wrnum32$332 Def0000FF
+S A$uart1wrnum32$314 Def0000E5
+S A$uart1wrnum32$305 Def0000D8
+S A$uart1wrnum32$260 Def0000A2
+S A$uart1wrnum32$233 Def00007F
+S A$uart1wrnum32$224 Def000072
+S A$uart1wrnum32$206 Def00005D
+S A$uart1wrnum32$161 Def000033
+S A$uart1wrnum32$152 Def000027
+S A$uart1wrnum32$143 Def000018
+S A$uart1wrnum32$134 Def000012
+S A$uart1wrnum32$125 Def00000C
+S A$uart1wrnum32$116 Def000000
+S A$uart1wrnum32$351 Def000121
+S A$uart1wrnum32$342 Def000111
+S A$uart1wrnum32$333 Def000101
+S A$uart1wrnum32$324 Def0000EF
+S A$uart1wrnum32$315 Def0000E8
+S A$uart1wrnum32$270 Def0000B4
+S A$uart1wrnum32$261 Def0000A4
+S A$uart1wrnum32$243 Def00008A
+S A$uart1wrnum32$234 Def000080
+S A$uart1wrnum32$225 Def000073
+S A$uart1wrnum32$216 Def000064
+S A$uart1wrnum32$207 Def00005E
+S A$uart1wrnum32$162 Def000036
+S A$uart1wrnum32$153 Def000028
+S A$uart1wrnum32$144 Def00001B
+S A$uart1wrnum32$117 Def000001
+S A$uart1wrnum32$352 Def000123
+S A$uart1wrnum32$325 Def0000F1
+S A$uart1wrnum32$316 Def0000EA
+S A$uart1wrnum32$307 Def0000DA
+S A$uart1wrnum32$280 Def0000C6
+S A$uart1wrnum32$235 Def000082
+S A$uart1wrnum32$226 Def000075
+S A$uart1wrnum32$208 Def00005F
+S A$uart1wrnum32$190 Def00004E
+S A$uart1wrnum32$172 Def000040
+S A$uart1wrnum32$163 Def000038
+S A$uart1wrnum32$154 Def000029
+S A$uart1wrnum32$145 Def00001C
+S A$uart1wrnum32$127 Def00000E
+S A$uart1wrnum32$335 Def000103
+S A$uart1wrnum32$326 Def0000F3
+S A$uart1wrnum32$317 Def0000EC
+S A$uart1wrnum32$308 Def0000DB
+S A$uart1wrnum32$290 Def0000C9
+S A$uart1wrnum32$263 Def0000A6
+S A$uart1wrnum32$254 Def000094
+S A$uart1wrnum32$245 Def00008D
+S A$uart1wrnum32$227 Def000077
+S A$uart1wrnum32$218 Def000066
+S A$uart1wrnum32$209 Def000060
+S A$uart1wrnum32$191 Def000050
+S A$uart1wrnum32$173 Def000041
+S A$uart1wrnum32$164 Def00003A
+S A$uart1wrnum32$155 Def00002A
+S A$uart1wrnum32$146 Def00001D
+S A$uart1wrnum32$128 Def00000F
+S A$uart1wrnum32$119 Def000003
+S A$uart1wrnum32$354 Def000125
+S A$uart1wrnum32$345 Def000113
+S A$uart1wrnum32$336 Def000106
+S A$uart1wrnum32$327 Def0000F5
+S A$uart1wrnum32$282 Def0000C8
+S A$uart1wrnum32$273 Def0000B6
+S A$uart1wrnum32$264 Def0000A9
+S A$uart1wrnum32$255 Def000096
+S A$uart1wrnum32$228 Def000079
+S A$uart1wrnum32$219 Def000068
+S A$uart1wrnum32$174 Def000043
+S A$uart1wrnum32$165 Def00003B
+S A$uart1wrnum32$156 Def00002B
+S A$uart1wrnum32$147 Def00001F
+S A$uart1wrnum32$346 Def000115
+S A$uart1wrnum32$337 Def000107
+S A$uart1wrnum32$328 Def0000F6
+S A$uart1wrnum32$319 Def0000EE
+S A$uart1wrnum32$292 Def0000CB
+S A$uart1wrnum32$274 Def0000B8
+S A$uart1wrnum32$265 Def0000AA
+S A$uart1wrnum32$256 Def000098
+S A$uart1wrnum32$247 Def000090
+S A$uart1wrnum32$238 Def000085
+S A$uart1wrnum32$193 Def000051
+S A$uart1wrnum32$175 Def000044
+S A$uart1wrnum32$166 Def00003C
+S A$uart1wrnum32$157 Def00002C
+S A$uart1wrnum32$148 Def000021
+S A$uart1wrnum32$356 Def000126
+S A$uart1wrnum32$347 Def000117
+S A$uart1wrnum32$338 Def000109
+S A$uart1wrnum32$329 Def0000F8
+S A$uart1wrnum32$293 Def0000CD
+S A$uart1wrnum32$275 Def0000BA
+S A$uart1wrnum32$266 Def0000AC
+S A$uart1wrnum32$257 Def00009A
+S A$uart1wrnum32$248 Def000091
+S A$uart1wrnum32$239 Def000086
+S A$uart1wrnum32$194 Def000052
+S A$uart1wrnum32$176 Def000046
+S A$uart1wrnum32$158 Def00002E
+S A$uart1wrnum32$149 Def000022
+S A$uart1wrnum32$348 Def000119
+S A$uart1wrnum32$339 Def00010B
+S A$uart1wrnum32$276 Def0000BC
+S A$uart1wrnum32$267 Def0000AE
+S A$uart1wrnum32$258 Def00009D
+S A$uart1wrnum32$195 Def000054
+S A$uart1wrnum32$177 Def000047
+S A$uart1wrnum32$168 Def00003E
+S A$uart1wrnum32$349 Def00011C
+S A$uart1wrnum32$277 Def0000BF
+S A$uart1wrnum32$268 Def0000B0
+S A$uart1wrnum32$259 Def0000A0
+S A$uart1wrnum32$196 Def000056
+S A$uart1wrnum32$187 Def000048
+S A$uart1wrnum32$296 Def0000CE
+S A$uart1wrnum32$278 Def0000C2
+S A$uart1wrnum32$269 Def0000B2
+S A$uart1wrnum32$188 Def00004B
+S A$uart1wrnum32$279 Def0000C4
+S A$uart1wrnum32$198 Def000057
+S A$uart1wrnum32$189 Def00004C
+S C$uart1wrnum32.c$25$0$0 Def000000
+S A$uart1wrnum32$298 Def0000D1
+S A$uart1wrnum32$199 Def000058
+S G$uart1_writenum32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 03
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 05 F1 23 09 00 04
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 12 EA 24 F6 50 01 1A
+R 00 00 00 16 F1 23 04 00 07
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 EA 24 F9 50 01 1A
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 EA 24 FC 50 01 1A
+R 00 00 00 16
+T 00 00 5D
+R 00 00 00 16
+T 00 00 5D C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 C0 03 E5 81 C0 F0 C0 E0 8F F0 EE 12
+R 00 00 00 16
+T 00 00 70 00 00 FE AF F0 15 81 D0 F0 D0 E0 FC 70
+R 00 00 00 16 02 03 00 02
+T 00 00 7D 50 EB 14 60 4C 20 00 00 00 49 EA C3 9B
+R 00 00 00 16 F1 23 09 00 09
+T 00 00 88 40 3F 20 00 00 00 41 20 00 00 00 04 EB
+R 00 00 00 16 F1 23 06 00 06 F1 23 0B 00 08
+T 00 00 91 FA D2 00 00 00
+R 00 00 00 16 F1 23 05 00 08
+T 00 00 94
+R 00 00 00 16
+T 00 00 94 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 A1 83 D0 82 D0 F0 30 00 00 00 20 EB 24 FC
+R 00 00 00 16 F1 23 09 00 07
+T 00 00 AC 60 08 24 FD 60 04 24 FD 70 13
+R 00 00 00 16
+T 00 00 B6
+R 00 00 00 16
+T 00 00 B6 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 C3 83 D0 82 D0 F0 0A
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 DB 99 8A 82 22
+R 00 00 00 16
+T 00 00 CE
+R 00 00 00 16
+T 00 00 CE 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 E3 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 EF
+R 00 00 00 16
+T 00 00 EF C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 FB 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 07
+T 00 01 06 EB 24 FC 60 08 24 FD 60 04 24 FD 70 B6
+R 00 00 00 16
+T 00 01 13
+R 00 00 00 16
+T 00 01 13 C0 F0 C0 82 C0 83 75 82 27 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 01 20 83 D0 82 D0 F0 0A 80 A1
+R 00 00 00 16
+
+
+M:uart1wrnum32
+F:G$uart1_writenum32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrnum32.uart1_writenum32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrnum32.uart1_writenum32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrnum32.uart1_writenum32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhex16
+
+;!FILE libmflarge/uart1wrhex16.asm
+XH3
+H 1A areas A4 global symbols
+M uart1wrhex16
+O -mmcs51 --model-large
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S _uart1_writehex16 Def000000
+S XG$uart1_writehex16$0$0 Def000111
+S C$uart1wrhex16.c$264$1$62 Def000000
+S C$uart1wrhex16.c$265$1$62 Def000111
+S A$uart1wrhex16$200 Def000058
+S A$uart1wrhex16$201 Def000059
+S A$uart1wrhex16$120 Def000005
+S A$uart1wrhex16$310 Def0000DB
+S A$uart1wrhex16$301 Def0000CB
+S A$uart1wrhex16$220 Def000069
+S A$uart1wrhex16$211 Def000063
+S A$uart1wrhex16$202 Def00005B
+S A$uart1wrhex16$121 Def000006
+S A$uart1wrhex16$320 Def0000E4
+S A$uart1wrhex16$311 Def0000DD
+S A$uart1wrhex16$302 Def0000CC
+S A$uart1wrhex16$230 Def000075
+S A$uart1wrhex16$221 Def00006B
+S A$uart1wrhex16$203 Def00005D
+S A$uart1wrhex16$140 Def000014
+S A$uart1wrhex16$122 Def000007
+S A$uart1wrhex16$330 Def0000F7
+S A$uart1wrhex16$321 Def0000E6
+S A$uart1wrhex16$240 Def000081
+S A$uart1wrhex16$231 Def000077
+S A$uart1wrhex16$150 Def000026
+S A$uart1wrhex16$141 Def000016
+S A$uart1wrhex16$132 Def00000F
+S A$uart1wrhex16$123 Def000009
+S A$uart1wrhex16$340 Def00010A
+S A$uart1wrhex16$331 Def0000F8
+S A$uart1wrhex16$322 Def0000E7
+S A$uart1wrhex16$313 Def0000DF
+S A$uart1wrhex16$304 Def0000CE
+S A$uart1wrhex16$232 Def000078
+S A$uart1wrhex16$223 Def00006D
+S A$uart1wrhex16$205 Def00005F
+S A$uart1wrhex16$142 Def000019
+S A$uart1wrhex16$341 Def00010C
+S A$uart1wrhex16$332 Def0000FA
+S A$uart1wrhex16$323 Def0000E9
+S A$uart1wrhex16$305 Def0000D0
+S A$uart1wrhex16$260 Def00009D
+S A$uart1wrhex16$242 Def000083
+S A$uart1wrhex16$233 Def000079
+S A$uart1wrhex16$224 Def00006F
+S A$uart1wrhex16$152 Def000028
+S A$uart1wrhex16$143 Def00001A
+S A$uart1wrhex16$125 Def00000B
+S A$uart1wrhex16$324 Def0000EB
+S A$uart1wrhex16$306 Def0000D2
+S A$uart1wrhex16$270 Def0000AD
+S A$uart1wrhex16$234 Def00007B
+S A$uart1wrhex16$225 Def000072
+S A$uart1wrhex16$207 Def000060
+S A$uart1wrhex16$162 Def000036
+S A$uart1wrhex16$153 Def00002B
+S A$uart1wrhex16$144 Def00001B
+S A$uart1wrhex16$126 Def00000C
+S A$uart1wrhex16$117 Def000000
+S A$uart1wrhex16$343 Def00010E
+S A$uart1wrhex16$334 Def0000FC
+S A$uart1wrhex16$325 Def0000EE
+S A$uart1wrhex16$307 Def0000D4
+S A$uart1wrhex16$271 Def0000B0
+S A$uart1wrhex16$262 Def00009F
+S A$uart1wrhex16$253 Def00008D
+S A$uart1wrhex16$244 Def000086
+S A$uart1wrhex16$208 Def000062
+S A$uart1wrhex16$163 Def000037
+S A$uart1wrhex16$154 Def00002E
+S A$uart1wrhex16$145 Def00001D
+S A$uart1wrhex16$118 Def000002
+S A$uart1wrhex16$335 Def0000FE
+S A$uart1wrhex16$326 Def0000F0
+S A$uart1wrhex16$308 Def0000D6
+S A$uart1wrhex16$290 Def0000BF
+S A$uart1wrhex16$272 Def0000B3
+S A$uart1wrhex16$263 Def0000A2
+S A$uart1wrhex16$254 Def00008F
+S A$uart1wrhex16$227 Def000074
+S A$uart1wrhex16$218 Def000065
+S A$uart1wrhex16$182 Def000047
+S A$uart1wrhex16$173 Def00003E
+S A$uart1wrhex16$164 Def000039
+S A$uart1wrhex16$155 Def000030
+S A$uart1wrhex16$146 Def00001F
+S A$uart1wrhex16$128 Def00000D
+S A$uart1wrhex16$119 Def000004
+S A$uart1wrhex16$345 Def00010F
+S A$uart1wrhex16$336 Def000100
+S A$uart1wrhex16$327 Def0000F2
+S A$uart1wrhex16$318 Def0000E0
+S A$uart1wrhex16$309 Def0000D9
+S A$uart1wrhex16$273 Def0000B5
+S A$uart1wrhex16$264 Def0000A3
+S A$uart1wrhex16$255 Def000091
+S A$uart1wrhex16$246 Def000089
+S A$uart1wrhex16$237 Def00007E
+S A$uart1wrhex16$219 Def000067
+S A$uart1wrhex16$192 Def00004E
+S A$uart1wrhex16$183 Def000048
+S A$uart1wrhex16$174 Def000041
+S A$uart1wrhex16$165 Def00003A
+S A$uart1wrhex16$156 Def000032
+S A$uart1wrhex16$147 Def000020
+S A$uart1wrhex16$337 Def000102
+S A$uart1wrhex16$319 Def0000E2
+S A$uart1wrhex16$292 Def0000C2
+S A$uart1wrhex16$274 Def0000B7
+S A$uart1wrhex16$265 Def0000A5
+S A$uart1wrhex16$256 Def000093
+S A$uart1wrhex16$247 Def00008A
+S A$uart1wrhex16$238 Def00007F
+S A$uart1wrhex16$193 Def00004F
+S A$uart1wrhex16$184 Def000049
+S A$uart1wrhex16$175 Def000042
+S A$uart1wrhex16$166 Def00003C
+S A$uart1wrhex16$148 Def000022
+S A$uart1wrhex16$139 Def000011
+S A$uart1wrhex16$338 Def000105
+S A$uart1wrhex16$329 Def0000F4
+S A$uart1wrhex16$284 Def0000BA
+S A$uart1wrhex16$257 Def000096
+S A$uart1wrhex16$239 Def000080
+S A$uart1wrhex16$194 Def000050
+S A$uart1wrhex16$185 Def00004A
+S A$uart1wrhex16$176 Def000044
+S A$uart1wrhex16$167 Def00003D
+S A$uart1wrhex16$158 Def000034
+S A$uart1wrhex16$149 Def000024
+S A$uart1wrhex16$339 Def000108
+S A$uart1wrhex16$294 Def0000C5
+S A$uart1wrhex16$276 Def0000B9
+S A$uart1wrhex16$267 Def0000A7
+S A$uart1wrhex16$258 Def000099
+S A$uart1wrhex16$249 Def00008B
+S A$uart1wrhex16$195 Def000051
+S A$uart1wrhex16$186 Def00004C
+S A$uart1wrhex16$177 Def000046
+S A$uart1wrhex16$295 Def0000C6
+S A$uart1wrhex16$286 Def0000BC
+S A$uart1wrhex16$268 Def0000A9
+S A$uart1wrhex16$259 Def00009B
+S A$uart1wrhex16$196 Def000052
+S A$uart1wrhex16$187 Def00004D
+S A$uart1wrhex16$287 Def0000BE
+S A$uart1wrhex16$269 Def0000AB
+S A$uart1wrhex16$197 Def000054
+S A$uart1wrhex16$198 Def000056
+S C$uart1wrhex16.c$25$0$0 Def000000
+S A$uart1wrhex16$298 Def0000C7
+S A$uart1wrhex16$299 Def0000C9
+S G$uart1_writehex16$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FD F8 E6 08 54 3F F5 F0 E6 FA
+R 00 00 00 16
+T 00 00 0D 78 00 7B 05 30 00 00 00 14 E5 83 30 E7
+R 00 00 00 16 F1 23 08 00 02
+T 00 00 18 0F C3 E4 95 82 F5 82 E4 95 83 F5 83 78
+R 00 00 00 16
+T 00 00 25 2D 80 0E
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 20 00 00 00 09 30 00 00 00 08 E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 31 82 60 02
+R 00 00 00 16
+T 00 00 34
+R 00 00 00 16
+T 00 00 34 78 2B
+R 00 00 00 16
+T 00 00 36
+R 00 00 00 16
+T 00 00 36 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 47
+R 00 00 00 16
+T 00 00 47 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E EB 14 C3 13 70 04 E5 82 80 08
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 14 70 04 E5 83 80 01
+R 00 00 00 16
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F E4
+R 00 00 00 16
+T 00 00 60
+R 00 00 00 16
+T 00 00 60 50 01 C4
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 6D
+R 00 00 00 16
+T 00 00 6D 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 74
+R 00 00 00 16
+T 00 00 74 FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 7F C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 88 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 8D
+R 00 00 00 16
+T 00 00 8D C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 9A 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 A5 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 B1 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 BA
+R 00 00 00 16
+T 00 00 BA DB 92 8A 82 22
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 C7
+R 00 00 00 16
+T 00 00 C7 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 D4 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 E0
+R 00 00 00 16
+T 00 00 E0 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 00 EC 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 00 F7 EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 04 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrhex16
+F:G$uart1_writehex16$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrhex16.uart1_writehex16$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrhex16.uart1_writehex16$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrhex16.uart1_writehex16$val$1$61({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+uart1wrhex32
+
+;!FILE libmflarge/uart1wrhex32.asm
+XH3
+H 1A areas B6 global symbols
+M uart1wrhex32
+O -mmcs51 --model-large
+S _uart1_tx Ref000000
+S .__.ABS. Def000000
+S _B_0 Ref000000
+S _B_1 Ref000000
+S _B_2 Ref000000
+S _B_3 Ref000000
+S _B_4 Ref000000
+S _B_5 Ref000000
+S _B_6 Ref000000
+S _B_7 Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 127 flags 20 addr 0
+S _uart1_writehex32 Def000000
+S XG$uart1_writehex32$0$0 Def000127
+S C$uart1wrhex32.c$282$1$62 Def000000
+S C$uart1wrhex32.c$283$1$62 Def000127
+S A$uart1wrhex32$210 Def000062
+S A$uart1wrhex32$120 Def000005
+S A$uart1wrhex32$310 Def0000D5
+S A$uart1wrhex32$220 Def00006F
+S A$uart1wrhex32$211 Def000063
+S A$uart1wrhex32$202 Def000058
+S A$uart1wrhex32$130 Def000010
+S A$uart1wrhex32$121 Def000007
+S A$uart1wrhex32$221 Def000070
+S A$uart1wrhex32$212 Def000065
+S A$uart1wrhex32$203 Def000059
+S A$uart1wrhex32$122 Def000008
+S A$uart1wrhex32$330 Def0000F1
+S A$uart1wrhex32$321 Def0000E1
+S A$uart1wrhex32$312 Def0000D8
+S A$uart1wrhex32$240 Def00007F
+S A$uart1wrhex32$231 Def000079
+S A$uart1wrhex32$222 Def000072
+S A$uart1wrhex32$213 Def000067
+S A$uart1wrhex32$204 Def00005A
+S A$uart1wrhex32$150 Def000024
+S A$uart1wrhex32$141 Def000014
+S A$uart1wrhex32$123 Def000009
+S A$uart1wrhex32$340 Def0000FA
+S A$uart1wrhex32$331 Def0000F3
+S A$uart1wrhex32$322 Def0000E2
+S A$uart1wrhex32$304 Def0000D0
+S A$uart1wrhex32$250 Def00008B
+S A$uart1wrhex32$241 Def000081
+S A$uart1wrhex32$223 Def000073
+S A$uart1wrhex32$205 Def00005B
+S A$uart1wrhex32$160 Def000030
+S A$uart1wrhex32$151 Def000026
+S A$uart1wrhex32$142 Def000017
+S A$uart1wrhex32$124 Def00000A
+S A$uart1wrhex32$350 Def00010D
+S A$uart1wrhex32$341 Def0000FC
+S A$uart1wrhex32$314 Def0000DB
+S A$uart1wrhex32$260 Def000097
+S A$uart1wrhex32$251 Def00008D
+S A$uart1wrhex32$215 Def000069
+S A$uart1wrhex32$206 Def00005C
+S A$uart1wrhex32$161 Def000033
+S A$uart1wrhex32$152 Def000027
+S A$uart1wrhex32$143 Def000018
+S A$uart1wrhex32$134 Def000012
+S A$uart1wrhex32$125 Def00000C
+S A$uart1wrhex32$116 Def000000
+S A$uart1wrhex32$360 Def000120
+S A$uart1wrhex32$351 Def00010E
+S A$uart1wrhex32$342 Def0000FD
+S A$uart1wrhex32$333 Def0000F5
+S A$uart1wrhex32$324 Def0000E4
+S A$uart1wrhex32$315 Def0000DC
+S A$uart1wrhex32$306 Def0000D2
+S A$uart1wrhex32$252 Def00008E
+S A$uart1wrhex32$243 Def000083
+S A$uart1wrhex32$225 Def000075
+S A$uart1wrhex32$216 Def00006A
+S A$uart1wrhex32$207 Def00005E
+S A$uart1wrhex32$162 Def000036
+S A$uart1wrhex32$153 Def000028
+S A$uart1wrhex32$144 Def00001B
+S A$uart1wrhex32$117 Def000001
+S A$uart1wrhex32$361 Def000122
+S A$uart1wrhex32$352 Def000110
+S A$uart1wrhex32$343 Def0000FF
+S A$uart1wrhex32$325 Def0000E6
+S A$uart1wrhex32$307 Def0000D4
+S A$uart1wrhex32$280 Def0000B3
+S A$uart1wrhex32$262 Def000099
+S A$uart1wrhex32$253 Def00008F
+S A$uart1wrhex32$244 Def000085
+S A$uart1wrhex32$217 Def00006C
+S A$uart1wrhex32$208 Def000060
+S A$uart1wrhex32$172 Def000040
+S A$uart1wrhex32$163 Def000038
+S A$uart1wrhex32$154 Def000029
+S A$uart1wrhex32$145 Def00001C
+S A$uart1wrhex32$127 Def00000E
+S A$uart1wrhex32$344 Def000101
+S A$uart1wrhex32$326 Def0000E8
+S A$uart1wrhex32$290 Def0000C3
+S A$uart1wrhex32$254 Def000091
+S A$uart1wrhex32$245 Def000088
+S A$uart1wrhex32$227 Def000076
+S A$uart1wrhex32$218 Def00006D
+S A$uart1wrhex32$173 Def000041
+S A$uart1wrhex32$164 Def00003A
+S A$uart1wrhex32$155 Def00002A
+S A$uart1wrhex32$146 Def00001D
+S A$uart1wrhex32$128 Def00000F
+S A$uart1wrhex32$119 Def000003
+S A$uart1wrhex32$363 Def000124
+S A$uart1wrhex32$354 Def000112
+S A$uart1wrhex32$345 Def000104
+S A$uart1wrhex32$327 Def0000EA
+S A$uart1wrhex32$318 Def0000DD
+S A$uart1wrhex32$291 Def0000C6
+S A$uart1wrhex32$282 Def0000B5
+S A$uart1wrhex32$273 Def0000A3
+S A$uart1wrhex32$264 Def00009C
+S A$uart1wrhex32$228 Def000078
+S A$uart1wrhex32$192 Def000051
+S A$uart1wrhex32$183 Def000048
+S A$uart1wrhex32$174 Def000043
+S A$uart1wrhex32$165 Def00003B
+S A$uart1wrhex32$156 Def00002B
+S A$uart1wrhex32$147 Def00001F
+S A$uart1wrhex32$355 Def000114
+S A$uart1wrhex32$346 Def000106
+S A$uart1wrhex32$328 Def0000EC
+S A$uart1wrhex32$319 Def0000DF
+S A$uart1wrhex32$292 Def0000C9
+S A$uart1wrhex32$283 Def0000B8
+S A$uart1wrhex32$274 Def0000A5
+S A$uart1wrhex32$247 Def00008A
+S A$uart1wrhex32$238 Def00007B
+S A$uart1wrhex32$193 Def000052
+S A$uart1wrhex32$184 Def00004B
+S A$uart1wrhex32$175 Def000044
+S A$uart1wrhex32$166 Def00003C
+S A$uart1wrhex32$157 Def00002C
+S A$uart1wrhex32$148 Def000021
+S A$uart1wrhex32$365 Def000125
+S A$uart1wrhex32$356 Def000116
+S A$uart1wrhex32$347 Def000108
+S A$uart1wrhex32$338 Def0000F6
+S A$uart1wrhex32$329 Def0000EF
+S A$uart1wrhex32$293 Def0000CB
+S A$uart1wrhex32$284 Def0000B9
+S A$uart1wrhex32$275 Def0000A7
+S A$uart1wrhex32$266 Def00009F
+S A$uart1wrhex32$257 Def000094
+S A$uart1wrhex32$239 Def00007D
+S A$uart1wrhex32$194 Def000053
+S A$uart1wrhex32$185 Def00004C
+S A$uart1wrhex32$176 Def000046
+S A$uart1wrhex32$158 Def00002E
+S A$uart1wrhex32$149 Def000022
+S A$uart1wrhex32$357 Def000118
+S A$uart1wrhex32$339 Def0000F8
+S A$uart1wrhex32$294 Def0000CD
+S A$uart1wrhex32$285 Def0000BB
+S A$uart1wrhex32$276 Def0000A9
+S A$uart1wrhex32$267 Def0000A0
+S A$uart1wrhex32$258 Def000095
+S A$uart1wrhex32$195 Def000054
+S A$uart1wrhex32$186 Def00004E
+S A$uart1wrhex32$177 Def000047
+S A$uart1wrhex32$168 Def00003E
+S A$uart1wrhex32$358 Def00011B
+S A$uart1wrhex32$349 Def00010A
+S A$uart1wrhex32$277 Def0000AC
+S A$uart1wrhex32$259 Def000096
+S A$uart1wrhex32$196 Def000056
+S A$uart1wrhex32$187 Def000050
+S A$uart1wrhex32$359 Def00011E
+S A$uart1wrhex32$296 Def0000CF
+S A$uart1wrhex32$287 Def0000BD
+S A$uart1wrhex32$278 Def0000AF
+S A$uart1wrhex32$269 Def0000A1
+S A$uart1wrhex32$197 Def000057
+S A$uart1wrhex32$288 Def0000BF
+S A$uart1wrhex32$279 Def0000B1
+S C$uart1wrhex32.c$25$0$0 Def000000
+S A$uart1wrhex32$289 Def0000C1
+S G$uart1_writehex32$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 FE AF F0 E5 81 24 FD F8 E6 08 54 3F F5
+R 00 00 00 16
+T 00 00 0D F0 E6 FA 78 00 7B 0A 30 00 00 00 19 EE
+R 00 00 00 16 F1 23 0B 00 02
+T 00 00 18 30 E7 15 C3 E4 95 82 F5 82 E4 95 83 F5
+R 00 00 00 16
+T 00 00 25 83 E4 9F FF E4 9E FE 78 2D 80 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 20 00 00 00 0B 30 00 00 00 0A E5 83 45
+R 00 00 00 16 F1 23 04 00 04 F1 23 09 00 03
+T 00 00 39 82 4F 4E 60 02
+R 00 00 00 16
+T 00 00 3E
+R 00 00 00 16
+T 00 00 3E 78 2B
+R 00 00 00 16
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 E8 60 05 EA 60 02 14 FA
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 30 00 00 00 06 EA 24 FB 50 01 1A
+R 00 00 00 16 F1 23 04 00 06
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 C3 EB 9A 50 02 EA FB
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58
+R 00 00 00 16
+T 00 00 58 EB 14 C3 13 70 04 E5 82 80 14
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 14 70 04 E5 83 80 0D
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 14 70 03 EF 80 07
+R 00 00 00 16
+T 00 00 6F
+R 00 00 00 16
+T 00 00 6F 14 70 03 EE 80 01
+R 00 00 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 E4
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 50 01 C4
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 54 0F 24 F6 40 04 24 0A 80 07
+R 00 00 00 16
+T 00 00 83
+R 00 00 00 16
+T 00 00 83 24 11 30 00 00 00 02 24 20
+R 00 00 00 16 F1 23 06 00 07
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A FC 70 48 EB 14 60 44 20 00 00 00 41 EA
+R 00 00 00 16 F1 23 0B 00 09
+T 00 00 95 C3 9B 40 37 20 00 00 00 39 20 00 00 00
+R 00 00 00 16 F1 23 08 00 05 F1 23 0D 00 08
+T 00 00 9E 04 EB FA D2 00 00 00
+R 00 00 00 16 F1 23 07 00 08
+T 00 00 A3
+R 00 00 00 16
+T 00 00 A3 C0 F0 C0 82 C0 83 75 82 20 12 00 00 D0
+R 00 00 00 16 02 0D 00 00
+T 00 00 B0 83 D0 82 D0 F0 30 00 00 00 18 EB 24 FB
+R 00 00 00 16 F1 23 09 00 06
+T 00 00 BB 70 13 C0 F0 C0 82 C0 83 75 82 20 12
+R 00 00 00 16
+T 00 00 C7 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 03 00 00
+T 00 00 D0
+R 00 00 00 16
+T 00 00 D0 DB 86 8A 82 22
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 20 00 00 00 1E 20 00 00 00 02 EB FA
+R 00 00 00 16 F1 23 04 00 09 F1 23 09 00 08
+T 00 00 DD
+R 00 00 00 16
+T 00 00 DD 74 C8 42 F0 E8 60 12 C0 F0 C0 82 C0 83
+R 00 00 00 16
+T 00 00 EA 88 82 12 00 00 D0 83 D0 82 D0 F0 0A
+R 00 00 00 16 02 06 00 00
+T 00 00 F6
+R 00 00 00 16
+T 00 00 F6 C0 F0 C0 82 C0 83 EC 24 30 F5 82 12
+R 00 00 00 16
+T 00 01 02 00 00 D0 83 D0 82 D0 F0 30 00 00 00 C3
+R 00 00 00 16 02 03 00 00 F1 23 0C 00 06
+T 00 01 0D EB 24 FB 70 BE C0 F0 C0 82 C0 83 75 82
+R 00 00 00 16
+T 00 01 1A 27 12 00 00 D0 83 D0 82 D0 F0 0A 80 A9
+R 00 00 00 16 02 05 00 00
+
+
+M:uart1wrhex32
+F:G$uart1_writehex32$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Luart1wrhex32.uart1_writehex32$nrdig1$1$61({1}SC:U),B,1,-3
+S:Luart1wrhex32.uart1_writehex32$flags1$1$61({1}SC:U),B,1,-4
+S:Luart1wrhex32.uart1_writehex32$val$1$61({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:G$uart1_irq$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_poll$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_txfreelinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txidle$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txfree$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbufptr$0$0({2}DF,DX,SC:U),C,0,0
+S:G$uart1_rxcountlinear$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxcount$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxbuffersize$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_rxpeek$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_txpoke$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txpokehex$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rxadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_txadvance$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_init$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_stop$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txdone$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_txfree$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_wait_rxcount$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_rx$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_tx$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writestr$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writenum16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehex16$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writenum32$0$0({2}DF,SC:U),C,0,0
+S:G$uart1_writehexu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writehexu32$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu16$0$0({2}DF,SV:S),C,0,0
+S:G$uart1_writeu32$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+adctemp
+
+;!FILE libmflarge/adctemp.asm
+XH3
+H 1A areas 33F global symbols
+M adctemp
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size AA flags 20 addr 0
+S C$adctemp.c$6$0$0 Def000000
+S G$adc_measure_temperature$0$0 Def000000
+S _adc_measure_temperature Def000000
+S A$adctemp$1200 Def000027
+S A$adctemp$1210 Def00003D
+S A$adctemp$1201 Def000029
+S A$adctemp$1301 Def0000A5
+S A$adctemp$1220 Def00004D
+S A$adctemp$1211 Def000040
+S A$adctemp$1202 Def00002C
+S A$adctemp$1302 Def0000A7
+S A$adctemp$1230 Def00005B
+S A$adctemp$1221 Def00004E
+S A$adctemp$1212 Def000042
+S A$adctemp$1203 Def00002E
+S A$adctemp$1240 Def00006B
+S A$adctemp$1231 Def00005E
+S A$adctemp$1222 Def00004F
+S A$adctemp$1213 Def000044
+S A$adctemp$1204 Def000031
+S A$adctemp$1250 Def000075
+S A$adctemp$1241 Def00006C
+S A$adctemp$1232 Def00005F
+S A$adctemp$1214 Def000046
+S A$adctemp$1205 Def000033
+S A$adctemp$1305 Def0000A9
+S A$adctemp$1260 Def00007F
+S A$adctemp$1251 Def000076
+S A$adctemp$1242 Def00006D
+S A$adctemp$1233 Def000060
+S A$adctemp$1215 Def000048
+S A$adctemp$1206 Def000036
+S A$adctemp$1261 Def000080
+S A$adctemp$1252 Def000077
+S A$adctemp$1243 Def00006E
+S A$adctemp$1234 Def000062
+S A$adctemp$1225 Def000051
+S A$adctemp$1216 Def000049
+S A$adctemp$1207 Def000039
+S A$adctemp$1180 Def000004
+S XG$adc_measure_temperature$0$0 Def0000A9
+S A$adctemp$1280 Def000093
+S A$adctemp$1271 Def000089
+S A$adctemp$1253 Def000078
+S A$adctemp$1244 Def00006F
+S A$adctemp$1235 Def000064
+S A$adctemp$1226 Def000053
+S A$adctemp$1217 Def00004A
+S A$adctemp$1190 Def000017
+S A$adctemp$1181 Def000006
+S A$adctemp$1290 Def00009B
+S A$adctemp$1281 Def000094
+S A$adctemp$1272 Def00008A
+S A$adctemp$1263 Def000083
+S A$adctemp$1245 Def000070
+S A$adctemp$1236 Def000067
+S A$adctemp$1227 Def000055
+S A$adctemp$1218 Def00004B
+S A$adctemp$1209 Def00003B
+S A$adctemp$1191 Def000018
+S A$adctemp$1182 Def000008
+S A$adctemp$1291 Def00009C
+S A$adctemp$1282 Def000095
+S A$adctemp$1273 Def00008B
+S A$adctemp$1264 Def000084
+S A$adctemp$1246 Def000071
+S A$adctemp$1237 Def000068
+S A$adctemp$1228 Def000057
+S A$adctemp$1219 Def00004C
+S A$adctemp$1192 Def000019
+S A$adctemp$1183 Def00000A
+S A$adctemp$1283 Def000096
+S A$adctemp$1274 Def00008C
+S A$adctemp$1265 Def000085
+S A$adctemp$1256 Def00007B
+S A$adctemp$1247 Def000072
+S A$adctemp$1238 Def000069
+S A$adctemp$1229 Def000059
+S A$adctemp$1193 Def00001A
+S A$adctemp$1184 Def00000C
+S C$adctemp.c$144$1$36 Def000000
+S A$adctemp$1293 Def00009F
+S A$adctemp$1275 Def00008D
+S A$adctemp$1266 Def000086
+S A$adctemp$1257 Def00007C
+S A$adctemp$1248 Def000073
+S A$adctemp$1239 Def00006A
+S A$adctemp$1194 Def00001B
+S A$adctemp$1185 Def00000E
+S C$adctemp.c$145$1$36 Def0000A9
+S A$adctemp$1294 Def0000A0
+S A$adctemp$1276 Def00008E
+S A$adctemp$1267 Def000087
+S A$adctemp$1258 Def00007D
+S A$adctemp$1249 Def000074
+S A$adctemp$1195 Def00001C
+S A$adctemp$1186 Def000011
+S A$adctemp$1295 Def0000A1
+S A$adctemp$1286 Def000097
+S A$adctemp$1268 Def000088
+S A$adctemp$1259 Def00007E
+S A$adctemp$1196 Def00001D
+S A$adctemp$1187 Def000013
+S A$adctemp$1178 Def000000
+S A$adctemp$1296 Def0000A2
+S A$adctemp$1287 Def000098
+S A$adctemp$1278 Def000091
+S A$adctemp$1197 Def00001F
+S A$adctemp$1188 Def000014
+S A$adctemp$1179 Def000001
+S A$adctemp$1297 Def0000A3
+S A$adctemp$1288 Def000099
+S A$adctemp$1279 Def000092
+S A$adctemp$1198 Def000022
+S A$adctemp$1189 Def000015
+S A$adctemp$1298 Def0000A4
+S A$adctemp$1289 Def00009A
+S A$adctemp$1199 Def000024
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E4 85 A8 F0 F5 A8 A8 98 F5 98 A9 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 90 70 28 74 01 F0 A3 74 06 F0 A3 E0
+R 00 00 00 16
+T 00 00 1A FA E4 F0 AB D1 75 D1 30 AC CA 75 CA D8
+R 00 00 00 16
+T 00 00 27 AD CB 75 CB D8 AE D2 75 D2 D8 AF D3 75
+R 00 00 00 16
+T 00 00 34 D3 D8 75 C9 01 D2 9E
+R 00 00 00 16
+T 00 00 3B
+R 00 00 00 16
+T 00 00 3B E5 C9 20 E7 11 E5 87 54 0C 44 01 F5 87
+R 00 00 00 16
+T 00 00 48 00 00 00 00 00 00 00 80 EA
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 8C CA 8D CB 8E D2 8F D3 8B D1 90 70 2A
+R 00 00 00 16
+T 00 00 5E EA F0 88 98 89 A0 90 70 22 E0 FA A3 E0
+R 00 00 00 16
+T 00 00 6B FB A3 E0 FC A3 E0 FD A3 E0 FE A3 E0 FF
+R 00 00 00 16
+T 00 00 78 85 F0 A8 EC C3 9A ED 9B 30 E7 06 EA CC
+R 00 00 00 16
+T 00 00 85 FA EB CD FB
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 EE C3 9C EF 9D 30 E7 06 EC CE FC ED CF
+R 00 00 00 16
+T 00 00 96 FD
+R 00 00 00 16
+T 00 00 97
+R 00 00 00 16
+T 00 00 97 EC C3 9A ED 9B 30 E7 06 EA CC FA EB CD
+R 00 00 00 16
+T 00 00 A4 FB
+R 00 00 00 16
+T 00 00 A5
+R 00 00 00 16
+T 00 00 A5 8C 82 8D 83 22
+R 00 00 00 16
+
+
+M:adctemp
+F:G$adc_measure_temperature$0$0({2}DF,SI:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccal
+
+;!FILE libmflarge/adccal.asm
+XH3
+H 1A areas 2D5 global symbols
+M adccal
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S _adc_calibrate_gain Ref000000
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _adc_calibrate_temp Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 7 flags 20 addr 0
+S G$adc_calibrate$0$0 Def000000
+S C$adccal.c$6$1$36 Def000000
+S C$adccal.c$7$1$36 Def000003
+S _adc_calibrate Def000000
+S C$adccal.c$8$1$36 Def000006
+S C$adccal.c$4$0$0 Def000000
+S XG$adc_calibrate$0$0 Def000006
+S A$adccal$1180 Def000000
+S A$adccal$1183 Def000003
+S A$adccal$1186 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 12 00 00 12 00 00 22
+R 00 00 00 16 02 04 00 7F 02 07 01 62
+
+
+M:adccal
+F:G$adc_calibrate$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccalg
+
+;!FILE libmflarge/adccalg.asm
+XH3
+H 1A areas 36E global symbols
+M adccalg
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S __divslong_PARM_2 Ref000000
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S __divslong Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _ADCCALG00GAIN0 Def007030
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG00GAIN1 Def007031
+S _ADCCALG01GAIN0 Def007032
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F9 flags 20 addr 0
+S _adc_calibrate_gain Def000000
+S A$adccalg$1300 Def00008F
+S A$adccalg$1210 Def00000C
+S A$adccalg$1310 Def00009B
+S A$adccalg$1301 Def000091
+S A$adccalg$1220 Def00001C
+S A$adccalg$1211 Def00000E
+S A$adccalg$1320 Def0000B1
+S A$adccalg$1311 Def00009D
+S A$adccalg$1230 Def000032
+S A$adccalg$1221 Def00001F
+S A$adccalg$1212 Def000010
+S A$adccalg$1330 Def0000C1
+S A$adccalg$1321 Def0000B3
+S A$adccalg$1312 Def00009F
+S A$adccalg$1240 Def000045
+S A$adccalg$1222 Def000022
+S A$adccalg$1213 Def000011
+S A$adccalg$1204 Def000000
+S A$adccalg$1340 Def0000D7
+S A$adccalg$1331 Def0000C3
+S A$adccalg$1322 Def0000B6
+S A$adccalg$1313 Def0000A0
+S A$adccalg$1250 Def000051
+S A$adccalg$1241 Def000046
+S A$adccalg$1232 Def000035
+S A$adccalg$1223 Def000025
+S A$adccalg$1214 Def000012
+S A$adccalg$1205 Def000001
+S A$adccalg$1350 Def0000EA
+S A$adccalg$1341 Def0000D8
+S A$adccalg$1332 Def0000C6
+S A$adccalg$1323 Def0000B7
+S A$adccalg$1314 Def0000A2
+S A$adccalg$1260 Def00005B
+S A$adccalg$1251 Def000052
+S A$adccalg$1242 Def000047
+S A$adccalg$1233 Def000037
+S A$adccalg$1224 Def000028
+S A$adccalg$1215 Def000013
+S A$adccalg$1206 Def000003
+S A$adccalg$1360 Def0000F8
+S A$adccalg$1351 Def0000ED
+S A$adccalg$1342 Def0000D9
+S A$adccalg$1333 Def0000C9
+S A$adccalg$1324 Def0000B8
+S A$adccalg$1315 Def0000A4
+S A$adccalg$1306 Def000093
+S A$adccalg$1270 Def000067
+S A$adccalg$1261 Def00005C
+S A$adccalg$1252 Def000053
+S A$adccalg$1243 Def000048
+S A$adccalg$1234 Def000039
+S A$adccalg$1225 Def00002A
+S A$adccalg$1216 Def000014
+S A$adccalg$1207 Def000005
+S A$adccalg$1352 Def0000EF
+S A$adccalg$1343 Def0000DB
+S A$adccalg$1334 Def0000CB
+S A$adccalg$1325 Def0000B9
+S A$adccalg$1316 Def0000A7
+S A$adccalg$1307 Def000095
+S A$adccalg$1280 Def000072
+S A$adccalg$1271 Def000068
+S A$adccalg$1262 Def00005E
+S A$adccalg$1253 Def000054
+S A$adccalg$1244 Def00004A
+S A$adccalg$1235 Def00003B
+S A$adccalg$1226 Def00002B
+S A$adccalg$1217 Def000015
+S A$adccalg$1208 Def000007
+S A$adccalg$1353 Def0000F1
+S A$adccalg$1344 Def0000DD
+S A$adccalg$1335 Def0000CE
+S A$adccalg$1326 Def0000BA
+S A$adccalg$1317 Def0000AA
+S A$adccalg$1308 Def000097
+S A$adccalg$1290 Def00007D
+S A$adccalg$1281 Def000073
+S A$adccalg$1272 Def000069
+S A$adccalg$1263 Def00005F
+S A$adccalg$1254 Def000055
+S A$adccalg$1245 Def00004B
+S A$adccalg$1236 Def00003D
+S A$adccalg$1227 Def00002E
+S A$adccalg$1218 Def000016
+S A$adccalg$1209 Def00000A
+S A$adccalg$1354 Def0000F4
+S A$adccalg$1345 Def0000DE
+S A$adccalg$1336 Def0000D0
+S A$adccalg$1327 Def0000BC
+S A$adccalg$1318 Def0000AC
+S A$adccalg$1309 Def000099
+S A$adccalg$1291 Def00007F
+S A$adccalg$1282 Def000074
+S A$adccalg$1273 Def00006B
+S A$adccalg$1264 Def000060
+S A$adccalg$1255 Def000057
+S A$adccalg$1246 Def00004C
+S A$adccalg$1237 Def00003F
+S A$adccalg$1228 Def00002F
+S A$adccalg$1219 Def000019
+S A$adccalg$1355 Def0000F5
+S A$adccalg$1346 Def0000E0
+S A$adccalg$1337 Def0000D2
+S A$adccalg$1328 Def0000BE
+S A$adccalg$1319 Def0000AF
+S A$adccalg$1292 Def000080
+S A$adccalg$1283 Def000075
+S A$adccalg$1274 Def00006C
+S A$adccalg$1265 Def000061
+S A$adccalg$1256 Def000058
+S A$adccalg$1247 Def00004D
+S A$adccalg$1238 Def000042
+S A$adccalg$1356 Def0000F6
+S A$adccalg$1347 Def0000E2
+S A$adccalg$1338 Def0000D5
+S A$adccalg$1329 Def0000BF
+S A$adccalg$1293 Def000081
+S A$adccalg$1284 Def000076
+S A$adccalg$1266 Def000062
+S A$adccalg$1248 Def00004E
+S XG$adc_calibrate_gain$0$0 Def0000F8
+S A$adccalg$1357 Def0000F7
+S A$adccalg$1348 Def0000E5
+S A$adccalg$1339 Def0000D6
+S A$adccalg$1285 Def000077
+S A$adccalg$1276 Def00006D
+S A$adccalg$1267 Def000063
+S A$adccalg$1258 Def000059
+S A$adccalg$1249 Def00004F
+S A$adccalg$1349 Def0000E8
+S A$adccalg$1295 Def000084
+S A$adccalg$1286 Def000079
+S A$adccalg$1277 Def00006E
+S A$adccalg$1268 Def000065
+S A$adccalg$1259 Def00005A
+S A$adccalg$1296 Def000087
+S A$adccalg$1287 Def00007A
+S A$adccalg$1278 Def00006F
+S A$adccalg$1269 Def000066
+S A$adccalg$1297 Def000089
+S A$adccalg$1288 Def00007B
+S A$adccalg$1279 Def000070
+S A$adccalg$1298 Def00008A
+S A$adccalg$1289 Def00007C
+S A$adccalg$1299 Def00008D
+S C$adccalg.c$178$1$36 Def000000
+S C$adccalg.c$179$1$36 Def0000F8
+S C$adccalg.c$13$0$0 Def000000
+S G$adc_calibrate_gain$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
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+R 00 00 00 16
+T 00 00 00 E4 C0 A8 F5 A8 C0 98 75 98 40 C0 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 F5 C9 F8 F9 FA FB FC FD 75 D1 28 75
+R 00 00 00 16
+T 00 00 1A CA E0 75 CB E8 75 D2 F0 75 D3 FF 90
+R 00 00 00 16
+T 00 00 26 70 29 74 F2 F0 90 70 20 E0 75 F0 10
+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
+T 00 00 4F 54 F0 4E 28 F8 EF 54 0F 39 F9 E0 A3 C4
+R 00 00 00 16
+T 00 00 5C 54 0F FE E0 A3 C4 FF 54 F0 4E 2A FA EF
+R 00 00 00 16
+T 00 00 69 54 0F 3B FB E0 A3 C4 54 0F FE E0 A3 C4
+R 00 00 00 16
+T 00 00 76 FF 54 F0 4E 2C FC EF 54 0F 3D FD D5 F0
+R 00 00 00 16
+T 00 00 83 AE 90 70 29 74 02 F0 75 D1 07 D0 A0 D0
+R 00 00 00 16
+T 00 00 90 98 D0 A8 C0 04 C0 05 C0 02 C0 03 88
+R 00 00 00 16
+T 00 00 9C 00 00 00 89 00 00 01 E4 F5
+R 00 00 00 16 F1 23 03 00 2A F1 23 07 00 2A
+T 00 00 A1 00 00 02 F5 00 00 03 90 28 F6 75 F0 5C
+R 00 00 00 16 F1 23 03 00 2A F1 23 07 00 2A
+T 00 00 AA 74 0F 12 00 00 E5 82 A8 83 90 70 30 F0
+R 00 00 00 16 02 06 01 6B
+T 00 00 B7 A3 E8 F0 D0 00 00 01 D0 00 00 00 E4 F5
+R 00 00 00 16 F1 23 07 00 2A F1 23 0B 00 2A
+T 00 00 C0 00 00 02 F5 00 00 03 90 F5 C3 75 F0 28
+R 00 00 00 16 F1 23 03 00 2A F1 23 07 00 2A
+T 00 00 C9 74 1C 12 00 00 E5 82 A8 83 90 70 32 F0
+R 00 00 00 16 02 06 01 6B
+T 00 00 D6 A3 E8 F0 D0 00 00 01 D0 00 00 00 E4 F5
+R 00 00 00 16 F1 23 07 00 2A F1 23 0B 00 2A
+T 00 00 DF 00 00 02 F5 00 00 03 90 99 9A 75 F0 99
+R 00 00 00 16 F1 23 03 00 2A F1 23 07 00 2A
+T 00 00 E8 74 19 12 00 00 E5 82 A8 83 90 70 34 F0
+R 00 00 00 16 02 06 01 6B
+T 00 00 F5 A3 E8 F0 22
+R 00 00 00 16
+
+
+M:adccalg
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+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adccalt
+
+;!FILE libmflarge/adccalt.asm
+XH3
+H 1A areas 35B global symbols
+M adccalt
+O -mmcs51 --model-large
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S __divslong_PARM_2 Ref000000
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S __mullong_PARM_2 Ref000000
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S __divslong Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$ADCCALTEMPGAIN0$0$0 Def007038
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$ADCCALTEMPGAIN1$0$0 Def007039
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S __mullong Ref000000
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _ADCCALTEMPGAIN0 Def007038
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _ADCCALTEMPGAIN1 Def007039
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$ADCCALTEMPOFFS0$0$0 Def00703A
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size E1 flags 20 addr 0
+S G$adc_calibrate_temp$0$0 Def000000
+S A$adccalt$1200 Def000003
+S A$adccalt$1300 Def0000A1
+S A$adccalt$1210 Def000014
+S A$adccalt$1201 Def000005
+S A$adccalt$1310 Def0000AF
+S A$adccalt$1301 Def0000A2
+S A$adccalt$1220 Def00002D
+S A$adccalt$1211 Def000017
+S A$adccalt$1202 Def000007
+S A$adccalt$1311 Def0000B2
+S A$adccalt$1302 Def0000A3
+S A$adccalt$1230 Def000040
+S A$adccalt$1212 Def00001A
+S A$adccalt$1203 Def00000A
+S A$adccalt$1330 Def0000D5
+S A$adccalt$1321 Def0000C1
+S A$adccalt$1312 Def0000B4
+S A$adccalt$1303 Def0000A5
+S A$adccalt$1240 Def00004C
+S A$adccalt$1222 Def000030
+S A$adccalt$1213 Def00001D
+S A$adccalt$1204 Def00000C
+S A$adccalt$1331 Def0000D7
+S A$adccalt$1322 Def0000C3
+S A$adccalt$1313 Def0000B6
+S A$adccalt$1304 Def0000A6
+S A$adccalt$1250 Def000057
+S A$adccalt$1241 Def00004D
+S A$adccalt$1232 Def000043
+S A$adccalt$1214 Def000020
+S A$adccalt$1205 Def00000E
+S A$adccalt$1332 Def0000D9
+S A$adccalt$1323 Def0000C5
+S A$adccalt$1314 Def0000B8
+S A$adccalt$1305 Def0000A7
+S A$adccalt$1260 Def000063
+S A$adccalt$1251 Def000058
+S A$adccalt$1242 Def00004F
+S A$adccalt$1233 Def000044
+S A$adccalt$1224 Def000033
+S A$adccalt$1215 Def000023
+S A$adccalt$1206 Def000010
+S A$adccalt$1333 Def0000DC
+S A$adccalt$1324 Def0000C6
+S A$adccalt$1315 Def0000BB
+S A$adccalt$1306 Def0000A9
+S A$adccalt$1270 Def000071
+S A$adccalt$1261 Def000064
+S A$adccalt$1252 Def000059
+S A$adccalt$1243 Def000050
+S A$adccalt$1234 Def000045
+S A$adccalt$1225 Def000035
+S A$adccalt$1216 Def000026
+S A$adccalt$1207 Def000011
+S A$adccalt$1334 Def0000DD
+S A$adccalt$1325 Def0000C8
+S A$adccalt$1316 Def0000BC
+S A$adccalt$1307 Def0000AA
+S A$adccalt$1271 Def000073
+S A$adccalt$1262 Def000065
+S A$adccalt$1253 Def00005A
+S A$adccalt$1244 Def000051
+S A$adccalt$1235 Def000046
+S A$adccalt$1226 Def000037
+S A$adccalt$1217 Def000028
+S A$adccalt$1208 Def000012
+S A$adccalt$1335 Def0000DE
+S A$adccalt$1326 Def0000CA
+S A$adccalt$1317 Def0000BD
+S A$adccalt$1308 Def0000AC
+S A$adccalt$1290 Def00008B
+S A$adccalt$1281 Def00007D
+S A$adccalt$1272 Def000074
+S A$adccalt$1263 Def000066
+S A$adccalt$1254 Def00005C
+S A$adccalt$1245 Def000052
+S A$adccalt$1236 Def000048
+S A$adccalt$1227 Def000039
+S A$adccalt$1218 Def000029
+S A$adccalt$1209 Def000013
+S A$adccalt$1336 Def0000DF
+S A$adccalt$1327 Def0000CD
+S A$adccalt$1318 Def0000BE
+S A$adccalt$1309 Def0000AE
+S A$adccalt$1291 Def00008D
+S A$adccalt$1282 Def00007F
+S A$adccalt$1273 Def000077
+S A$adccalt$1264 Def000067
+S A$adccalt$1255 Def00005D
+S A$adccalt$1246 Def000053
+S A$adccalt$1237 Def000049
+S A$adccalt$1228 Def00003B
+S A$adccalt$1219 Def00002C
+S C$adccalt.c$161$1$36 Def000000
+S _adc_calibrate_temp Def000000
+S A$adccalt$1328 Def0000D0
+S A$adccalt$1319 Def0000C0
+S A$adccalt$1292 Def000090
+S A$adccalt$1274 Def000079
+S A$adccalt$1265 Def000069
+S A$adccalt$1256 Def00005E
+S A$adccalt$1247 Def000055
+S A$adccalt$1238 Def00004A
+S A$adccalt$1229 Def00003D
+S C$adccalt.c$162$1$36 Def0000E0
+S A$adccalt$1329 Def0000D2
+S A$adccalt$1293 Def000093
+S A$adccalt$1284 Def000081
+S A$adccalt$1275 Def00007B
+S A$adccalt$1266 Def00006A
+S A$adccalt$1257 Def00005F
+S A$adccalt$1248 Def000056
+S A$adccalt$1239 Def00004B
+S A$adccalt$1339 Def0000E0
+S A$adccalt$1294 Def000095
+S A$adccalt$1285 Def000083
+S A$adccalt$1267 Def00006B
+S A$adccalt$1258 Def000060
+S A$adccalt$1295 Def000098
+S A$adccalt$1286 Def000085
+S A$adccalt$1259 Def000061
+S A$adccalt$1296 Def000099
+S A$adccalt$1287 Def000086
+S A$adccalt$1269 Def00006E
+S A$adccalt$1297 Def00009B
+S A$adccalt$1288 Def000087
+S A$adccalt$1198 Def000000
+S A$adccalt$1298 Def00009D
+S A$adccalt$1289 Def000089
+S A$adccalt$1199 Def000001
+S A$adccalt$1299 Def00009F
+S XG$adc_calibrate_temp$0$0 Def0000E0
+S C$adccalt.c$11$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E4 C0 A8 F5 A8 C0 98 75 98 40 C0 A0 F5
+R 00 00 00 16
+T 00 00 0D A0 F5 C9 F8 F9 FA FB 75 D1 28 75 CA F8
+R 00 00 00 16
+T 00 00 1A 75 CB F9 75 D2 FF 75 D3 FF 90 70 29 74
+R 00 00 00 16
+T 00 00 27 F2 F0 90 70 20 E0 75 F0 10
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 75 C9 01
+R 00 00 00 16
+T 00 00 33
+R 00 00 00 16
+T 00 00 33 E5 87 54 0C 44 01 F5 87 E5 D1 20 E7 F3
+R 00 00 00 16
+T 00 00 40 90 70 20 E0 A3 C4 54 0F FE E0 A3 C4 FF
+R 00 00 00 16
+T 00 00 4D 54 F0 4E 28 F8 EF 54 0F 39 F9 E0 A3 C4
+R 00 00 00 16
+T 00 00 5A 54 0F FE E0 A3 C4 FF 54 F0 4E 2A FA EF
+R 00 00 00 16
+T 00 00 67 54 0F 3B FB D5 F0 C2 90 70 29 74 02 F0
+R 00 00 00 16
+T 00 00 74 75 D1 07 D0 A0 D0 98 D0 A8 C0 00 C0 01
+R 00 00 00 16
+T 00 00 81 8A 00 00 00 8B 00 00 01 EB 33 95 E0 F5
+R 00 00 00 16 F1 23 04 01 2E F1 23 08 01 2E
+T 00 00 8A 00 00 02 F5 00 00 03 90 A5 32 75 F0 00
+R 00 00 00 16 F1 23 03 01 2E F1 23 07 01 2E
+T 00 00 93 74 00 12 00 00 F9 D0 E0 D0 00 C0 00 C0
+R 00 00 00 16 02 06 02 96
+T 00 00 A0 E0 C3 13 F5 00 00 01 E8 13 F5 00 00 00
+R 00 00 00 16 F1 23 07 00 2B F1 23 0D 00 2B
+T 00 00 A9 E4 F5 00 00 02 F5 00 00 03 E9 12
+R 00 00 00 16 F1 23 05 00 2B F1 23 09 00 2B
+T 00 00 B0 00 00 A8 83 E5 82 24 77 90 70 3A F0 A3
+R 00 00 00 16 02 03 01 69
+T 00 00 BD E8 34 3F F0 D0 00 00 01 D0 00 00 00 E4
+R 00 00 00 16 F1 23 08 00 2B F1 23 0C 00 2B
+T 00 00 C6 F5 00 00 02 F5 00 00 03 90 83 12 75 F0
+R 00 00 00 16 F1 23 04 00 2B F1 23 08 00 2B
+T 00 00 CF C0 74 13 12 00 00 E5 82 A8 83 90 70 38
+R 00 00 00 16 02 07 01 69
+T 00 00 DC F0 A3 E8 F0 22
+R 00 00 00 16
+
+
+M:adccalt
+F:G$adc_calibrate_temp$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
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+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
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+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
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+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
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+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
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+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
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+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
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+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPGAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPGAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALTEMPOFFS0$0$0({1}SC:U),F,0,0
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+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
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+S:G$PORTB$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
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+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
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+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
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+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
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+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
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+S:G$T0CNT$0$0({2}SI:U),I,0,0
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+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
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+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
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+S:G$U0SHREG$0$0({1}SC:U),I,0,0
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+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcuncal
+
+;!FILE libmflarge/adcuncal.asm
+XH3
+H 1A areas 30A global symbols
+M adcuncal
+O -mmcs51 --model-large
+S G$ADCCALTEMPOFFS1$0$0 Def00703B
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _ADCCALTEMPOFFS0 Def00703A
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _ADCCALTEMPOFFS1 Def00703B
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$ADCCALG00GAIN1$0$0 Def007031
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+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
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+S G$PORTB_1$0$0 Def000089
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+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
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+S _WTEVTA0 Def0000F4
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+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
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+S G$E2IE_4$0$0 Def0000A4
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+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
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+S G$ADCCH3VAL0$0$0 Def007026
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+S G$E2IE_7$0$0 Def0000A7
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+S G$T1CNT1$0$0 Def0000A5
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+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
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+S _ADCCALG01GAIN0 Def007032
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+S _B_6 Def0000F6
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+S _E2IE_5 Def0000A5
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+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
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+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
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+S _RADIOFDATAADDR1 Def007041
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+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
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+S _PORTA_6 Def000086
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+S _RADIOSTAT1 Def0000BF
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+S _FRCOSCFREQ1 Def007077
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+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs00
+
+;!FILE libmflarge/adcseoffs00.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs00
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$ADCCALG00GAIN0$0$0 Def007030
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG00GAIN1$0$0 Def007031
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
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+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
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+S G$PORTB_2$0$0 Def00008A
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+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG00GAIN$0$0({2}SI:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs01
+
+;!FILE libmflarge/adcseoffs01.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs01
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG01GAIN0$0$0 Def007032
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG01GAIN1$0$0 Def007033
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG01GAIN0 Def007032
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG01GAIN1 Def007033
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$ADCCALG01GAIN$0$0 Def007032
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _ADCCALG01GAIN Def007032
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+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
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+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+S A$adcseoffs01$1250 Def000038
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+S A$adcseoffs01$1216 Def000018
+S A$adcseoffs01$1207 Def000011
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+S A$adcseoffs01$1272 Def00004C
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+S A$adcseoffs01$1191 Def000000
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+
+
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+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
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+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN0$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG01GAIN$0$0({2}SI:U),F,0,0
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+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+adcseoffs10
+
+;!FILE libmflarge/adcseoffs10.asm
+XH3
+H 1B areas 327 global symbols
+M adcseoffs10
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$ADCCALG10GAIN0$0$0 Def007034
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$ADCCALG10GAIN1$0$0 Def007035
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _ADCCALG10GAIN0 Def007034
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _ADCCALG10GAIN1 Def007035
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$ADCCALG10GAIN$0$0 Def007034
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _ADCCALG10GAIN Def007034
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
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+A REG_BANK_0 size 8 flags 4 addr 0
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+A OSEG size 0 flags 4 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
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+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S _adc_singleended_offset_x10 Def000000
+S C$adcseoffs10.c$8$0$0 Def000000
+S XG$adc_singleended_offset_x10$0$0 Def000051
+S A$adcseoffs10$1200 Def00000A
+S A$adcseoffs10$1201 Def00000B
+S A$adcseoffs10$1220 Def00001D
+S A$adcseoffs10$1211 Def000013
+S A$adcseoffs10$1202 Def00000C
+S A$adcseoffs10$1230 Def000026
+S A$adcseoffs10$1221 Def00001F
+S A$adcseoffs10$1212 Def000014
+S A$adcseoffs10$1240 Def00002F
+S A$adcseoffs10$1231 Def000027
+S A$adcseoffs10$1222 Def000020
+S A$adcseoffs10$1213 Def000015
+S A$adcseoffs10$1250 Def000038
+S A$adcseoffs10$1241 Def000030
+S A$adcseoffs10$1232 Def000028
+S A$adcseoffs10$1223 Def000021
+S A$adcseoffs10$1214 Def000016
+S A$adcseoffs10$1205 Def00000D
+S A$adcseoffs10$1260 Def000040
+S A$adcseoffs10$1251 Def000039
+S A$adcseoffs10$1242 Def000031
+S A$adcseoffs10$1224 Def000022
+S A$adcseoffs10$1215 Def000017
+S A$adcseoffs10$1206 Def00000F
+S A$adcseoffs10$1261 Def000041
+S A$adcseoffs10$1252 Def00003A
+S A$adcseoffs10$1243 Def000033
+S A$adcseoffs10$1216 Def000018
+S A$adcseoffs10$1207 Def000011
+S A$adcseoffs10$1271 Def00004B
+S A$adcseoffs10$1262 Def000043
+S A$adcseoffs10$1253 Def00003B
+S A$adcseoffs10$1244 Def000034
+S A$adcseoffs10$1235 Def000029
+S A$adcseoffs10$1217 Def000019
+S A$adcseoffs10$1208 Def000012
+S A$adcseoffs10$1281 Def000051
+S A$adcseoffs10$1272 Def00004C
+S A$adcseoffs10$1263 Def000044
+S A$adcseoffs10$1254 Def00003C
+S A$adcseoffs10$1245 Def000035
+S A$adcseoffs10$1236 Def00002A
+S A$adcseoffs10$1227 Def000023
+S A$adcseoffs10$1218 Def00001B
+S A$adcseoffs10$1191 Def000000
+S A$adcseoffs10$1282 Def000053
+S A$adcseoffs10$1273 Def00004D
+S A$adcseoffs10$1264 Def000045
+S A$adcseoffs10$1246 Def000036
+S A$adcseoffs10$1237 Def00002B
+S A$adcseoffs10$1228 Def000024
+S A$adcseoffs10$1219 Def00001C
+S A$adcseoffs10$1192 Def000003
+S A$adcseoffs10$1283 Def000055
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+S A$adcseoffs10$1265 Def000047
+S A$adcseoffs10$1238 Def00002C
+S A$adcseoffs10$1229 Def000025
+S A$adcseoffs10$1193 Def000004
+S A$adcseoffs10$1275 Def00004F
+S A$adcseoffs10$1266 Def000048
+S A$adcseoffs10$1257 Def00003D
+S A$adcseoffs10$1239 Def00002D
+S A$adcseoffs10$1194 Def000005
+S A$adcseoffs10$1276 Def000050
+S A$adcseoffs10$1267 Def000049
+S A$adcseoffs10$1258 Def00003E
+S A$adcseoffs10$1249 Def000037
+S A$adcseoffs10$1195 Def000006
+S A$adcseoffs10$1268 Def00004A
+S A$adcseoffs10$1259 Def00003F
+S A$adcseoffs10$1198 Def000007
+S A$adcseoffs10$1199 Def000008
+S C$adcseoffs10.c$20$1$36 Def000029
+S C$adcseoffs10.c$21$1$36 Def000037
+S C$adcseoffs10.c$22$1$36 Def00003D
+S C$adcseoffs10.c$23$1$36 Def00004B
+S C$adcseoffs10.c$24$1$36 Def000051
+S C$adcseoffs10.c$25$1$36 Def000051
+S C$adcseoffs10.c$16$1$36 Def000007
+S C$adcseoffs10.c$17$1$36 Def00000D
+S C$adcseoffs10.c$18$1$36 Def000013
+S C$adcseoffs10.c$11$1$0 Def000000
+S C$adcseoffs10.c$19$1$36 Def000023
+S G$adc_singleended_offset_x10$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
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+T 00 00 00 90 70 34 E0 FE A3 E0 CE 25 E0 CE 33 FF
+R 00 00 00 17
+T 00 00 0D 8E 04 74 80 2F FD EF C4 03 CE C4 03 54
+R 00 00 00 17
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+R 00 00 00 17
+T 00 00 27 3D FD EF C4 CE C4 54 0F 6E CE 54 0F CE
+R 00 00 00 17
+T 00 00 34 6E CE FF EE 2C FC EF 3D FD EF C4 CE C4
+R 00 00 00 17
+T 00 00 41 54 0F 6E CE 54 0F CE 6E CE FF EC C3 9E
+R 00 00 00 17
+T 00 00 4E FC ED 9F 8C 82 F5 83 22
+R 00 00 00 17
+
+
+M:adcseoffs10
+F:G$adc_singleended_offset_x10$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$ADCCALG10GAIN1$0$0({1}SC:U),F,0,0
+S:G$ADCCALG10GAIN$0$0({2}SI:U),F,0,0
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+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
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+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
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+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
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+S:G$E2IE_5$0$0({1}SX:U),J,0,0
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+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
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+S:G$E2IP_3$0$0({1}SX:U),J,0,0
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+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
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+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
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+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$adc_measure_temperature$0$0({2}DF,SI:S),C,0,0
+S:G$adc_calibrate_gain$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate_temp$0$0({2}DF,SV:S),C,0,0
+S:G$adc_calibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_uncalibrate$0$0({2}DF,SV:S),C,0,0
+S:G$adc_singleended_offset_x01$0$0({2}DF,SI:U),C,0,0
+S:G$adc_singleended_offset_x1$0$0({2}DF,SI:U),C,0,0
+
+
+
+
+bch3121dec
+
+;!FILE libmflarge/bch3121dec.asm
+XH3
+H 1A areas 39A global symbols
+M bch3121dec
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S _bch3121_syndrometable Ref000000
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+S Lbch3121dec.bch3121_decode$sloc0$1$0 Def000000
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+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S Lbch3121dec.bch3121_decode$cw$1$32 Def000000
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+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
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+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 111 flags 20 addr 0
+S C$bch3121dec.c$14$1$33 Def0000A5
+S C$bch3121dec.c$15$1$33 Def0000B4
+S C$bch3121dec.c$16$1$33 Def0000BB
+S C$bch3121dec.c$17$1$33 Def0000F8
+S C$bch3121dec.c$18$1$33 Def000110
+S G$bch3121_decode$0$0 Def000000
+S C$bch3121dec.c$6$1$33 Def000015
+S C$bch3121dec.c$8$1$33 Def000037
+S _bch3121_decode Def000000
+S C$bch3121dec.c$4$0$0 Def000000
+S XG$bch3121_decode$0$0 Def000110
+S A$bch3121dec$1200 Def000011
+S A$bch3121dec$1300 Def000097
+S A$bch3121dec$1210 Def00001C
+S A$bch3121dec$1201 Def000012
+S A$bch3121dec$1400 Def00010D
+S A$bch3121dec$1310 Def0000A4
+S A$bch3121dec$1301 Def000099
+S A$bch3121dec$1220 Def00002D
+S A$bch3121dec$1211 Def00001D
+S A$bch3121dec$1202 Def000013
+S A$bch3121dec$1401 Def00010F
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+S A$bch3121dec$1226 Def000037
+S A$bch3121dec$1217 Def000025
+S A$bch3121dec$1208 Def000019
+S A$bch3121dec$1190 Def000004
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+S A$bch3121dec$1371 Def0000EC
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+S A$bch3121dec$1263 Def00006A
+S A$bch3121dec$1254 Def000059
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+S A$bch3121dec$1236 Def000045
+S A$bch3121dec$1227 Def000039
+S A$bch3121dec$1218 Def000027
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+S A$bch3121dec$1398 Def000109
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+S A$bch3121dec$1399 Def00010B
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+T 00 00 22 00 00 02 A3 E0 F5 00 00 03 85
+R 00 00 00 16 F1 21 03 00 05 F1 21 09 00 05
+T 00 00 28 00 00 00 82 85 00 00 01 83 85
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 2E 00 00 02 F0 12 00 00 AA 82 AB 83 8A 00
+R 00 00 00 16 F1 21 03 00 05 02 08 01 64
+T 00 00 39 EB C8 25 E0 C8 33 F9 E8 24 00 00 00 F5
+R 00 00 00 16 F1 03 0C 01 A1
+T 00 00 44 82 E9 34 00 00 00 F5 83 E4 93 FA A3 E4
+R 00 00 00 16 F1 83 06 01 A1
+T 00 00 4F 93 FB 8A 00 8B 01 E9 30 E7 15 74 01 45
+R 00 00 00 16
+T 00 00 5C 00 00 00 F8 A9 00 00 01 AE
+R 00 00 00 16 F1 21 03 00 05 F1 21 08 00 05
+T 00 00 61 00 00 02 AF 00 00 03 88 82 89 83 8E F0
+R 00 00 00 16 F1 21 03 00 05 F1 21 07 00 05
+T 00 00 6A EF 02 01 10
+R 00 00 00 16 00 05 00 16
+T 00 00 6E
+R 00 00 00 16
+T 00 00 6E 74 1F 5A FE 8E F0 05 F0 79 01 7C 00 7D
+R 00 00 00 16
+T 00 00 7B 00 7F 00 80 0C
+R 00 00 00 16
+T 00 00 80
+R 00 00 00 16
+T 00 00 80 E9 29 F9 EC 33 FC ED 33 FD EF 33 FF
+R 00 00 00 16
+T 00 00 8C
+R 00 00 00 16
+T 00 00 8C D5 F0 F1 90 00 00 E9 65 00 00 00 F0 EC
+R 00 00 00 16 00 07 00 0A F1 21 0B 00 05
+T 00 00 97 65 00 00 01 A3 F0 ED 65 00 00 02 A3 F0
+R 00 00 00 16 F1 21 04 00 05 F1 21 0B 00 05
+T 00 00 A0 EF 65 00 00 03 A3 F0 EB C4 03 CA C4 03
+R 00 00 00 16 F1 21 05 00 05
+T 00 00 AB 54 07 6A CA 54 07 CA 6A CA 53 02 1F 7B
+R 00 00 00 16
+T 00 00 B8 00 8A 06 8E F0 05 F0 7E 01 7F 00 7D 00
+R 00 00 00 16
+T 00 00 C5 7C 00 80 0C
+R 00 00 00 16
+T 00 00 C9
+R 00 00 00 16
+T 00 00 C9 EE 2E FE EF 33 FF ED 33 FD EC 33 FC
+R 00 00 00 16
+T 00 00 D5
+R 00 00 00 16
+T 00 00 D5 D5 F0 F1 90 00 00 E0 F8 A3 E0 F9 A3 E0
+R 00 00 00 16 00 07 00 0A
+T 00 00 E2 FA A3 E0 FB 90 00 00 EE 68 F0 EF 69 A3
+R 00 00 00 16 00 08 00 0A
+T 00 00 EF F0 ED 6A A3 F0 EC 6B A3 F0 90 00 00 E0
+R 00 00 00 16 00 0D 00 0A
+T 00 00 FC FC A3 E0 FD A3 E0 FE A3 E0 FF 53 04 FE
+R 00 00 00 16
+T 00 01 09 8C 82 8D 83 8E F0 EF
+R 00 00 00 16
+T 00 01 10
+R 00 00 00 16
+T 00 01 10 22
+R 00 00 00 16
+
+
+M:bch3121dec
+F:G$bch3121_decode$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lbch3121dec.bch3121_decode$x$1$33({2}SI:U),R,0,0,[r2,r3]
+S:Lbch3121dec.bch3121_decode$p$1$33({1}SC:U),R,0,0,[r6]
+S:Lbch3121dec.bch3121_decode$sloc0$1$0({4}SL:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Lbch3121dec.bch3121_decode$cw$1$32({4}SL:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121decp
+
+;!FILE libmflarge/bch3121decp.asm
+XH3
+H 1A areas 339 global symbols
+M bch3121decp
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S _bch3121_decode Ref000000
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _hweight32 Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S Lbch3121decp.bch3121_decode_parity$cw$1$32 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 8D flags 20 addr 0
+S C$bch3121decp.c$6$1$33 Def000015
+S C$bch3121decp.c$7$1$33 Def000027
+S G$bch3121_decode_parity$0$0 Def000000
+S C$bch3121decp.c$8$1$33 Def00004A
+S C$bch3121decp.c$9$1$33 Def00004E
+S C$bch3121decp.c$4$0$0 Def000000
+S _bch3121_decode_parity Def000000
+S XG$bch3121_decode_parity$0$0 Def00008C
+S A$bch3121decp$1210 Def00001F
+S A$bch3121decp$1220 Def000029
+S A$bch3121decp$1211 Def000020
+S A$bch3121decp$1202 Def000015
+S A$bch3121decp$1230 Def00003C
+S A$bch3121decp$1221 Def00002B
+S A$bch3121decp$1212 Def000021
+S A$bch3121decp$1203 Def000018
+S A$bch3121decp$1240 Def000048
+S A$bch3121decp$1231 Def00003F
+S A$bch3121decp$1222 Def00002D
+S A$bch3121decp$1213 Def000022
+S A$bch3121decp$1204 Def000019
+S A$bch3121decp$1250 Def000052
+S A$bch3121decp$1241 Def000049
+S A$bch3121decp$1232 Def000040
+S A$bch3121decp$1223 Def00002E
+S A$bch3121decp$1214 Def000023
+S A$bch3121decp$1205 Def00001A
+S A$bch3121decp$1260 Def00005E
+S A$bch3121decp$1251 Def000054
+S A$bch3121decp$1233 Def000041
+S A$bch3121decp$1224 Def000030
+S A$bch3121decp$1215 Def000025
+S A$bch3121decp$1206 Def00001B
+S A$bch3121decp$1270 Def00006E
+S A$bch3121decp$1261 Def000061
+S A$bch3121decp$1252 Def000055
+S A$bch3121decp$1234 Def000042
+S A$bch3121decp$1225 Def000033
+S A$bch3121decp$1216 Def000026
+S A$bch3121decp$1207 Def00001C
+S A$bch3121decp$1280 Def00007D
+S A$bch3121decp$1271 Def00006F
+S A$bch3121decp$1262 Def000063
+S A$bch3121decp$1244 Def00004A
+S A$bch3121decp$1235 Def000043
+S A$bch3121decp$1226 Def000035
+S A$bch3121decp$1208 Def00001D
+S A$bch3121decp$1190 Def00000B
+S A$bch3121decp$1290 Def000085
+S A$bch3121decp$1281 Def00007E
+S A$bch3121decp$1272 Def000071
+S A$bch3121decp$1263 Def000065
+S A$bch3121decp$1245 Def00004B
+S A$bch3121decp$1236 Def000044
+S A$bch3121decp$1227 Def000037
+S A$bch3121decp$1209 Def00001E
+S A$bch3121decp$1191 Def00000C
+S A$bch3121decp$1291 Def000087
+S A$bch3121decp$1282 Def00007F
+S A$bch3121decp$1273 Def000072
+S A$bch3121decp$1264 Def000067
+S A$bch3121decp$1237 Def000045
+S A$bch3121decp$1228 Def000039
+S A$bch3121decp$1219 Def000027
+S A$bch3121decp$1192 Def00000D
+S A$bch3121decp$1292 Def000089
+S A$bch3121decp$1283 Def000080
+S A$bch3121decp$1274 Def000074
+S A$bch3121decp$1265 Def000068
+S A$bch3121decp$1256 Def000057
+S A$bch3121decp$1238 Def000046
+S A$bch3121decp$1229 Def00003A
+S A$bch3121decp$1193 Def00000E
+S A$bch3121decp$1184 Def000000
+S A$bch3121decp$1293 Def00008B
+S A$bch3121decp$1284 Def000081
+S A$bch3121decp$1275 Def000075
+S A$bch3121decp$1266 Def000069
+S A$bch3121decp$1257 Def000059
+S A$bch3121decp$1248 Def00004E
+S A$bch3121decp$1239 Def000047
+S A$bch3121decp$1194 Def00000F
+S A$bch3121decp$1185 Def000002
+S A$bch3121decp$1285 Def000082
+S A$bch3121decp$1276 Def000077
+S A$bch3121decp$1267 Def00006A
+S A$bch3121decp$1258 Def00005B
+S A$bch3121decp$1249 Def000050
+S A$bch3121decp$1195 Def000010
+S A$bch3121decp$1186 Def000004
+S A$bch3121decp$1286 Def000083
+S A$bch3121decp$1277 Def00007A
+S A$bch3121decp$1268 Def00006B
+S A$bch3121decp$1259 Def00005D
+S A$bch3121decp$1196 Def000011
+S A$bch3121decp$1187 Def000006
+S A$bch3121decp$1287 Def000084
+S A$bch3121decp$1278 Def00007B
+S A$bch3121decp$1269 Def00006C
+S A$bch3121decp$1197 Def000012
+S A$bch3121decp$1188 Def000007
+S A$bch3121decp$1297 Def00008C
+S A$bch3121decp$1279 Def00007C
+S A$bch3121decp$1198 Def000013
+S A$bch3121decp$1189 Def00000A
+S C$bch3121decp.c$10$1$33 Def000057
+S A$bch3121decp$1199 Def000014
+S C$bch3121decp.c$11$1$33 Def000085
+S C$bch3121decp.c$12$1$33 Def00008C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
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+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 00 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 FC
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A A3 E0 FD A3 E0 FE A3 E0 FF 74 01 5C F8
+R 00 00 00 16
+T 00 00 27 8C 82 8D 83 8E F0 EF C0 00 12 00 00 AC
+R 00 00 00 16 02 0D 00 EC
+T 00 00 34 82 AD 83 AE F0 FF D0 00 90 00 00 EC F0
+R 00 00 00 16 00 0C 00 0A
+T 00 00 41 ED A3 F0 EE A3 F0 EF A3 F0 EC 30 E0 09
+R 00 00 00 16
+T 00 00 4E 8C 82 8D 83 8E F0 EF 80 35
+R 00 00 00 16
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+R 00 00 00 16 02 0B 02 20
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+R 00 00 00 16
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+T 00 00 8C 22
+R 00 00 00 16
+
+
+M:bch3121decp
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+S:G$ACC$0$0({1}SC:U),I,0,0
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+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121enc
+
+;!FILE libmflarge/bch3121enc.asm
+XH3
+H 1A areas 33E global symbols
+M bch3121enc
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S Lbch3121enc.bch3121_encode$cw$1$32 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 92 flags 20 addr 0
+S A$bch3121enc$1291 Def00008B
+S A$bch3121enc$1282 Def000082
+S A$bch3121enc$1273 Def000079
+S A$bch3121enc$1264 Def000070
+S A$bch3121enc$1255 Def000061
+S A$bch3121enc$1246 Def000051
+S A$bch3121enc$1237 Def00003F
+S A$bch3121enc$1228 Def000036
+S A$bch3121enc$1219 Def00002D
+S A$bch3121enc$1192 Def00000F
+S A$bch3121enc$1183 Def000002
+S A$bch3121enc$1292 Def00008D
+S A$bch3121enc$1283 Def000083
+S A$bch3121enc$1274 Def00007A
+S A$bch3121enc$1265 Def000071
+S A$bch3121enc$1256 Def000062
+S A$bch3121enc$1247 Def000053
+S A$bch3121enc$1238 Def000040
+S A$bch3121enc$1229 Def000037
+S A$bch3121enc$1193 Def000010
+S A$bch3121enc$1184 Def000004
+S A$bch3121enc$1293 Def00008F
+S A$bch3121enc$1284 Def000084
+S A$bch3121enc$1275 Def00007B
+S A$bch3121enc$1266 Def000072
+S A$bch3121enc$1257 Def000063
+S A$bch3121enc$1248 Def000055
+S A$bch3121enc$1239 Def000042
+S A$bch3121enc$1194 Def000011
+S A$bch3121enc$1185 Def000006
+S A$bch3121enc$1285 Def000085
+S A$bch3121enc$1276 Def00007C
+S A$bch3121enc$1267 Def000073
+S A$bch3121enc$1258 Def000064
+S A$bch3121enc$1249 Def000057
+S A$bch3121enc$1195 Def000012
+S A$bch3121enc$1186 Def000007
+S A$bch3121enc$1286 Def000086
+S A$bch3121enc$1277 Def00007D
+S A$bch3121enc$1268 Def000074
+S A$bch3121enc$1259 Def000066
+S A$bch3121enc$1196 Def000013
+S A$bch3121enc$1187 Def00000A
+S A$bch3121enc$1296 Def000091
+S A$bch3121enc$1287 Def000087
+S A$bch3121enc$1269 Def000075
+S A$bch3121enc$1197 Def000014
+S A$bch3121enc$1188 Def00000B
+S A$bch3121enc$1288 Def000088
+S A$bch3121enc$1189 Def00000C
+S A$bch3121enc$1289 Def000089
+S G$bch3121_encode$0$0 Def000000
+S C$bch3121enc.c$6$1$33 Def000015
+S C$bch3121enc.c$7$1$33 Def000032
+S C$bch3121enc.c$8$1$33 Def00007E
+S C$bch3121enc.c$9$1$33 Def000091
+S _bch3121_encode Def000000
+S C$bch3121enc.c$4$0$0 Def000000
+S XG$bch3121_encode$0$0 Def000091
+S A$bch3121enc$1200 Def000015
+S A$bch3121enc$1210 Def000021
+S A$bch3121enc$1201 Def000018
+S A$bch3121enc$1220 Def00002E
+S A$bch3121enc$1211 Def000022
+S A$bch3121enc$1202 Def000019
+S A$bch3121enc$1230 Def000038
+S A$bch3121enc$1221 Def00002F
+S A$bch3121enc$1212 Def000025
+S A$bch3121enc$1203 Def00001A
+S A$bch3121enc$1240 Def000044
+S A$bch3121enc$1231 Def000039
+S A$bch3121enc$1222 Def000030
+S A$bch3121enc$1213 Def000026
+S A$bch3121enc$1204 Def00001B
+S A$bch3121enc$1250 Def000059
+S A$bch3121enc$1241 Def000046
+S A$bch3121enc$1232 Def00003A
+S A$bch3121enc$1223 Def000031
+S A$bch3121enc$1214 Def000027
+S A$bch3121enc$1205 Def00001C
+S A$bch3121enc$1260 Def000068
+S A$bch3121enc$1251 Def00005B
+S A$bch3121enc$1242 Def000048
+S A$bch3121enc$1233 Def00003B
+S A$bch3121enc$1215 Def000029
+S A$bch3121enc$1206 Def00001D
+S A$bch3121enc$1270 Def000076
+S A$bch3121enc$1261 Def00006A
+S A$bch3121enc$1252 Def00005D
+S A$bch3121enc$1243 Def00004A
+S A$bch3121enc$1234 Def00003C
+S A$bch3121enc$1216 Def00002A
+S A$bch3121enc$1207 Def00001E
+S A$bch3121enc$1280 Def00007E
+S A$bch3121enc$1271 Def000077
+S A$bch3121enc$1262 Def00006C
+S A$bch3121enc$1253 Def00005E
+S A$bch3121enc$1244 Def00004C
+S A$bch3121enc$1235 Def00003D
+S A$bch3121enc$1226 Def000032
+S A$bch3121enc$1217 Def00002B
+S A$bch3121enc$1208 Def00001F
+S A$bch3121enc$1190 Def00000D
+S A$bch3121enc$1290 Def00008A
+S A$bch3121enc$1281 Def000081
+S A$bch3121enc$1272 Def000078
+S A$bch3121enc$1263 Def00006F
+S A$bch3121enc$1254 Def00005F
+S A$bch3121enc$1245 Def00004E
+S A$bch3121enc$1236 Def00003E
+S A$bch3121enc$1227 Def000035
+S A$bch3121enc$1218 Def00002C
+S A$bch3121enc$1209 Def000020
+S A$bch3121enc$1191 Def00000E
+S A$bch3121enc$1182 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 0A
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 AE 83 AD F0 FC 90 00 00 EF F0 EE
+R 00 00 00 16 00 0B 00 0A
+T 00 00 0D A3 F0 ED A3 F0 EC A3 F0 90 00 00 E0 A3
+R 00 00 00 16 00 0C 00 0A
+T 00 00 1A E0 FD A3 E0 FE A3 E0 FF 90 00 00 E4 F0
+R 00 00 00 16 00 0C 00 0A
+T 00 00 27 74 F8 5D A3 F0 EE A3 F0 EF A3 F0 90
+R 00 00 00 16
+T 00 00 33 00 00 E0 FC A3 E0 FD A3 E0 FE A3 E0 FF
+R 00 00 00 16 00 03 00 0A
+T 00 00 40 8C 82 8D 83 8E F0 C0 07 C0 06 C0 05 C0
+R 00 00 00 16
+T 00 00 4D 04 12 00 00 AA 82 AB 83 D0 04 D0 05 D0
+R 00 00 00 16 02 05 01 64
+T 00 00 5A 06 D0 07 EB CA 25 E0 CA 33 FB 8A 00 8B
+R 00 00 00 16
+T 00 00 67 01 7A 00 7B 00 90 00 00 E8 4C F0 E9 4D
+R 00 00 00 16 00 09 00 0A
+T 00 00 74 A3 F0 EA 4E A3 F0 EB 4F A3 F0 90 00 00
+R 00 00 00 16 00 0E 00 0A
+T 00 00 81 E0 FC A3 E0 FD A3 E0 FE A3 E0 8C 82 8D
+R 00 00 00 16
+T 00 00 8E 83 8E F0 22
+R 00 00 00 16
+
+
+M:bch3121enc
+F:G$bch3121_encode$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:Lbch3121enc.bch3121_encode$cw$1$32({4}SL:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121encp
+
+;!FILE libmflarge/bch3121encp.asm
+XH3
+H 1A areas 366 global symbols
+M bch3121encp
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S _bch3121_syndrome Ref000000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S _hweight32 Ref000000
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 4 flags 40 addr 0
+S Lbch3121encp.bch3121_encode_parity$cw$1$32 Def000000
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size C6 flags 20 addr 0
+S C$bch3121encp.c$6$1$33 Def000015
+S C$bch3121encp.c$7$1$33 Def000032
+S G$bch3121_encode_parity$0$0 Def000000
+S C$bch3121encp.c$8$1$33 Def00007E
+S C$bch3121encp.c$9$1$33 Def0000B2
+S C$bch3121encp.c$4$0$0 Def000000
+S _bch3121_encode_parity Def000000
+S XG$bch3121_encode_parity$0$0 Def0000C5
+S A$bch3121encp$1300 Def00009A
+S A$bch3121encp$1210 Def000020
+S A$bch3121encp$1201 Def000015
+S A$bch3121encp$1310 Def0000A9
+S A$bch3121encp$1301 Def00009C
+S A$bch3121encp$1220 Def00002D
+S A$bch3121encp$1211 Def000021
+S A$bch3121encp$1202 Def000018
+S A$bch3121encp$1311 Def0000AA
+S A$bch3121encp$1302 Def00009E
+S A$bch3121encp$1230 Def000037
+S A$bch3121encp$1221 Def00002E
+S A$bch3121encp$1212 Def000022
+S A$bch3121encp$1203 Def000019
+S A$bch3121encp$1330 Def0000BD
+S A$bch3121encp$1321 Def0000B2
+S A$bch3121encp$1312 Def0000AB
+S A$bch3121encp$1303 Def0000A0
+S A$bch3121encp$1240 Def000042
+S A$bch3121encp$1231 Def000038
+S A$bch3121encp$1222 Def00002F
+S A$bch3121encp$1213 Def000025
+S A$bch3121encp$1204 Def00001A
+S A$bch3121encp$1331 Def0000BE
+S A$bch3121encp$1322 Def0000B5
+S A$bch3121encp$1313 Def0000AC
+S A$bch3121encp$1304 Def0000A3
+S A$bch3121encp$1250 Def000057
+S A$bch3121encp$1241 Def000044
+S A$bch3121encp$1232 Def000039
+S A$bch3121encp$1223 Def000030
+S A$bch3121encp$1214 Def000026
+S A$bch3121encp$1205 Def00001B
+S A$bch3121encp$1332 Def0000BF
+S A$bch3121encp$1323 Def0000B6
+S A$bch3121encp$1314 Def0000AD
+S A$bch3121encp$1305 Def0000A4
+S A$bch3121encp$1260 Def000066
+S A$bch3121encp$1251 Def000059
+S A$bch3121encp$1242 Def000046
+S A$bch3121encp$1233 Def00003A
+S A$bch3121encp$1224 Def000031
+S A$bch3121encp$1215 Def000027
+S A$bch3121encp$1206 Def00001C
+S A$bch3121encp$1333 Def0000C1
+S A$bch3121encp$1324 Def0000B7
+S A$bch3121encp$1315 Def0000AE
+S A$bch3121encp$1306 Def0000A5
+S A$bch3121encp$1270 Def000075
+S A$bch3121encp$1261 Def000068
+S A$bch3121encp$1252 Def00005B
+S A$bch3121encp$1243 Def000048
+S A$bch3121encp$1234 Def00003B
+S A$bch3121encp$1216 Def000029
+S A$bch3121encp$1207 Def00001D
+S A$bch3121encp$1334 Def0000C3
+S A$bch3121encp$1325 Def0000B8
+S A$bch3121encp$1316 Def0000AF
+S A$bch3121encp$1307 Def0000A6
+S A$bch3121encp$1271 Def000076
+S A$bch3121encp$1262 Def00006A
+S A$bch3121encp$1253 Def00005D
+S A$bch3121encp$1244 Def00004A
+S A$bch3121encp$1235 Def00003C
+S A$bch3121encp$1217 Def00002A
+S A$bch3121encp$1208 Def00001E
+S A$bch3121encp$1190 Def00000C
+S A$bch3121encp$1326 Def0000B9
+S A$bch3121encp$1317 Def0000B0
+S A$bch3121encp$1308 Def0000A7
+S A$bch3121encp$1290 Def000089
+S A$bch3121encp$1281 Def00007E
+S A$bch3121encp$1272 Def000077
+S A$bch3121encp$1263 Def00006C
+S A$bch3121encp$1254 Def00005E
+S A$bch3121encp$1245 Def00004C
+S A$bch3121encp$1236 Def00003D
+S A$bch3121encp$1227 Def000032
+S A$bch3121encp$1218 Def00002B
+S A$bch3121encp$1209 Def00001F
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+S A$bch3121encp$1298 Def000097
+S A$bch3121encp$1289 Def000088
+S A$bch3121encp$1299 Def000099
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
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+
+
+M:bch3121encp
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+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
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+S:G$XTALOSC$0$0({1}SC:U),F,0,0
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+S:Lbch3121encp.bch3121_encode_parity$cw$1$32({4}SL:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
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+S:G$EIE$0$0({1}SC:U),I,0,0
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+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
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+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
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+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
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+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
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+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121stab
+
+XH3
+H 1A areas 3 global symbols
+M bch3121stab
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 800 flags 20 addr 0
+S G$bch3121_syndrometable$0$0 Def000000
+S _bch3121_syndrometable Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
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+T 00 04 AC 00 80 63 02 00 80 EE 02 F6 03 64 02 00
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+T 00 05 3B 00 DA 03 42 02 00 80 F0 02 00 80 00 80
+R 00 00 00 17
+T 00 05 48 B3 02 7A 03 00 80 00 80 2F 03 00 80 56
+R 00 00 00 17
+T 00 05 55 03 00 80 CD 03 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 62 EC 01 90 02 CB 03 E9 03 00 80 00 80 00
+R 00 00 00 17
+T 00 05 6F 80 00 80 00 80 27 02 00 80 00 80 46 02
+R 00 00 00 17
+T 00 05 7C B3 03 90 03 00 80 4E 03 89 03 00 80 00
+R 00 00 00 17
+T 00 05 89 80 00 80 00 80 00 80 00 80 F0 03 00 80
+R 00 00 00 17
+T 00 05 96 2B 03 00 80 AC 01 00 80 89 02 CF 03 0A
+R 00 00 00 17
+T 00 05 A3 03 8B 01 68 02 2D 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 B0 00 80 00 80 26 02 00 80 E9 02 47 02 00
+R 00 00 00 17
+T 00 05 BD 80 00 80 00 80 00 80 00 80 00 80 CF 02
+R 00 00 00 17
+T 00 05 CA 00 80 59 03 00 80 00 80 00 80 25 02 6F
+R 00 00 00 17
+T 00 05 D7 03 CB 01 AA 03 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 05 E4 24 02 CD 01 00 80 00 80 00 80 AA 02 22
+R 00 00 00 17
+T 00 05 F1 02 00 80 11 00 21 02 00 80 00 80 23 02
+R 00 00 00 17
+T 00 05 FE 4C 03 49 01 00 80 E4 01 00 80 47 03 00
+R 00 00 00 17
+T 00 06 0B 80 00 80 00 80 E2 01 00 80 0F 00 E1 01
+R 00 00 00 17
+T 00 06 18 00 80 17 03 E3 01 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 06 25 80 98 03 D1 02 00 80 00 80 00 80 4E 02
+R 00 00 00 17
+T 00 06 32 00 80 E5 01 71 03 00 80 00 80 14 03 00
+R 00 00 00 17
+T 00 06 3F 80 D1 03 00 80 B4 03 00 80 00 80 00 80
+R 00 00 00 17
+T 00 06 4C 4C 02 00 80 00 80 67 01 E6 01 F5 02 00
+R 00 00 00 17
+T 00 06 59 80 00 80 70 02 BC 03 00 80 B7 03 00 80
+R 00 00 00 17
+T 00 06 66 00 80 E8 03 95 03 A7 01 00 80 B4 02 00
+R 00 00 00 17
+T 00 06 73 80 00 80 00 80 00 80 00 80 00 80 32 03
+R 00 00 00 17
+T 00 06 80 43 03 2C 02 88 03 F5 03 1A 00 41 03 42
+R 00 00 00 17
+T 00 06 8D 03 D2 03 00 80 66 01 E7 01 00 80 44 03
+R 00 00 00 17
+T 00 06 9A 00 80 00 80 88 02 00 80 00 80 00 80 69
+R 00 00 00 17
+T 00 06 A7 02 45 03 00 80 A6 01 00 80 31 03 FD 03
+R 00 00 00 17
+T 00 06 B4 00 80 00 80 E8 02 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 06 C1 80 64 01 00 80 00 80 46 03 F8 03 A5 01
+R 00 00 00 17
+T 00 06 CE 00 80 61 01 0B 00 00 80 62 01 00 80 63
+R 00 00 00 17
+T 00 06 DB 01 00 80 00 80 00 80 00 80 A3 01 D2 02
+R 00 00 00 17
+T 00 06 E8 A2 01 00 80 0D 00 A1 01 00 80 65 01 00
+R 00 00 00 17
+T 00 06 F5 80 00 80 72 03 0A 02 A4 01 2E 02 00 80
+R 00 00 00 17
+T 00 07 02 AD 02 87 03 00 80 AB 03 CA 01 00 80 30
+R 00 00 00 17
+T 00 07 0F 02 00 80 D3 03 E8 01 00 80 00 80 00 80
+R 00 00 00 17
+T 00 07 1C 00 80 87 02 00 80 00 80 00 80 00 80 E6
+R 00 00 00 17
+T 00 07 29 03 58 03 00 80 00 80 00 80 00 80 00 80
+R 00 00 00 17
+T 00 07 36 AD 03 E7 02 49 02 AB 02 00 80 00 80 00
+R 00 00 00 17
+T 00 07 43 80 2A 03 00 80 E5 03 00 80 00 80 0D 03
+R 00 00 00 17
+T 00 07 50 00 80 BA 03 00 80 00 80 00 80 00 80 00
+R 00 00 00 17
+T 00 07 5D 80 00 80 E3 03 00 80 73 03 55 03 1F 00
+R 00 00 00 17
+T 00 07 6A E1 03 E2 03 00 80 0B 03 00 80 00 80 8A
+R 00 00 00 17
+T 00 07 77 01 E4 03 D3 02 00 80 00 80 82 03 00 80
+R 00 00 00 17
+T 00 07 84 1C 00 81 03 48 03 00 80 83 03 84 02 00
+R 00 00 00 17
+T 00 07 91 80 00 80 84 03 83 02 E5 02 82 02 81 02
+R 00 00 00 17
+T 00 07 9E 14 00 00 80 00 80 85 03 00 80 E4 02 00
+R 00 00 00 17
+T 00 07 AB 80 6E 02 00 80 E3 02 00 80 CA 03 0F 03
+R 00 00 00 17
+T 00 07 B8 17 00 E1 02 E2 02 85 02 50 02 6A 03 86
+R 00 00 00 17
+T 00 07 C5 03 00 80 00 80 00 80 00 80 AF 03 6C 02
+R 00 00 00 17
+T 00 07 D2 68 01 00 80 00 80 00 80 00 80 CA 02 86
+R 00 00 00 17
+T 00 07 DF 02 00 80 33 03 00 80 00 80 E7 03 00 80
+R 00 00 00 17
+T 00 07 EC A8 01 00 80 00 80 00 80 29 02 00 80 E6
+R 00 00 00 17
+T 00 07 F9 02 AF 02 00 80 00 80
+R 00 00 00 17
+
+
+M:bch3121stab
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_syndrome$0$0({2}DF,SI:U),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+bch3121syn
+
+;!FILE libmflarge/bch3121syn.asm
+XH3
+H 1B areas 345 global symbols
+M bch3121syn
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+S Lbch3121syn.bch3121_syndrome$cw$1$32 Def000000
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+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 8A flags 20 addr 0
+S C$bch3121syn.c$7$1$33 Def000017
+S C$bch3121syn.c$8$2$34 Def000017
+S C$bch3121syn.c$9$2$34 Def000028
+S C$bch3121syn.c$4$0$0 Def000000
+S C$bch3121syn.c$6$1$0 Def000015
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+S A$bch3121syn$1300 Def00007D
+S A$bch3121syn$1210 Def00001C
+S A$bch3121syn$1201 Def000015
+S A$bch3121syn$1301 Def00007E
+S A$bch3121syn$1211 Def00001D
+S A$bch3121syn$1311 Def000089
+S A$bch3121syn$1302 Def00007F
+S A$bch3121syn$1230 Def000033
+S A$bch3121syn$1212 Def00001E
+S A$bch3121syn$1303 Def000080
+S A$bch3121syn$1240 Def00003D
+S A$bch3121syn$1231 Def000034
+S A$bch3121syn$1222 Def000028
+S A$bch3121syn$1213 Def00001F
+S A$bch3121syn$1304 Def000081
+S A$bch3121syn$1250 Def000047
+S A$bch3121syn$1241 Def00003E
+S A$bch3121syn$1232 Def000035
+S A$bch3121syn$1223 Def00002B
+S A$bch3121syn$1214 Def000020
+S A$bch3121syn$1305 Def000082
+S A$bch3121syn$1260 Def000051
+S A$bch3121syn$1251 Def000048
+S A$bch3121syn$1242 Def00003F
+S A$bch3121syn$1233 Def000037
+S A$bch3121syn$1224 Def00002C
+S A$bch3121syn$1215 Def000021
+S A$bch3121syn$1306 Def000084
+S A$bch3121syn$1270 Def00005D
+S A$bch3121syn$1261 Def000052
+S A$bch3121syn$1252 Def000049
+S A$bch3121syn$1243 Def000040
+S A$bch3121syn$1234 Def000038
+S A$bch3121syn$1225 Def00002D
+S A$bch3121syn$1216 Def000022
+S A$bch3121syn$1207 Def000017
+S A$bch3121syn$1307 Def000085
+S A$bch3121syn$1280 Def000065
+S A$bch3121syn$1271 Def00005E
+S A$bch3121syn$1262 Def000053
+S A$bch3121syn$1253 Def00004A
+S A$bch3121syn$1244 Def000041
+S A$bch3121syn$1235 Def000039
+S A$bch3121syn$1226 Def00002E
+S A$bch3121syn$1217 Def000023
+S A$bch3121syn$1208 Def00001A
+S A$bch3121syn$1190 Def00000C
+S A$bch3121syn$1308 Def000087
+S A$bch3121syn$1290 Def000070
+S A$bch3121syn$1281 Def000066
+S A$bch3121syn$1272 Def00005F
+S A$bch3121syn$1263 Def000054
+S A$bch3121syn$1254 Def00004B
+S A$bch3121syn$1245 Def000042
+S A$bch3121syn$1227 Def00002F
+S A$bch3121syn$1218 Def000024
+S A$bch3121syn$1209 Def00001B
+S A$bch3121syn$1191 Def00000D
+S _bch3121_syndrome Def000000
+S A$bch3121syn$1291 Def000071
+S A$bch3121syn$1273 Def000060
+S A$bch3121syn$1264 Def000057
+S A$bch3121syn$1255 Def00004C
+S A$bch3121syn$1246 Def000043
+S A$bch3121syn$1228 Def000030
+S A$bch3121syn$1219 Def000025
+S A$bch3121syn$1192 Def00000E
+S A$bch3121syn$1183 Def000000
+S A$bch3121syn$1292 Def000072
+S A$bch3121syn$1274 Def000061
+S A$bch3121syn$1265 Def000058
+S A$bch3121syn$1256 Def00004D
+S A$bch3121syn$1247 Def000044
+S A$bch3121syn$1229 Def000032
+S A$bch3121syn$1193 Def00000F
+S A$bch3121syn$1184 Def000002
+S A$bch3121syn$1293 Def000073
+S A$bch3121syn$1284 Def000068
+S A$bch3121syn$1266 Def000059
+S A$bch3121syn$1257 Def00004E
+S A$bch3121syn$1248 Def000045
+S A$bch3121syn$1239 Def00003A
+S A$bch3121syn$1194 Def000010
+S A$bch3121syn$1185 Def000004
+S A$bch3121syn$1294 Def000075
+S A$bch3121syn$1285 Def00006B
+S A$bch3121syn$1267 Def00005A
+S A$bch3121syn$1258 Def00004F
+S A$bch3121syn$1249 Def000046
+S A$bch3121syn$1195 Def000011
+S A$bch3121syn$1186 Def000006
+S A$bch3121syn$1295 Def000077
+S A$bch3121syn$1286 Def00006C
+S A$bch3121syn$1277 Def000062
+S A$bch3121syn$1268 Def00005B
+S A$bch3121syn$1259 Def000050
+S A$bch3121syn$1196 Def000012
+S A$bch3121syn$1187 Def000007
+S A$bch3121syn$1296 Def000078
+S A$bch3121syn$1287 Def00006D
+S A$bch3121syn$1278 Def000063
+S A$bch3121syn$1269 Def00005C
+S A$bch3121syn$1197 Def000013
+S A$bch3121syn$1188 Def00000A
+S A$bch3121syn$1297 Def000079
+S A$bch3121syn$1288 Def00006E
+S A$bch3121syn$1279 Def000064
+S A$bch3121syn$1198 Def000014
+S A$bch3121syn$1189 Def00000B
+S A$bch3121syn$1298 Def00007A
+S A$bch3121syn$1289 Def00006F
+S C$bch3121syn.c$11$1$33 Def000062
+S A$bch3121syn$1299 Def00007B
+S C$bch3121syn.c$12$1$33 Def000068
+S C$bch3121syn.c$10$2$34 Def00003A
+S C$bch3121syn.c$13$1$33 Def000089
+S XG$bch3121_syndrome$0$0 Def000089
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+T 00 00 7B A2 E7 CC 33 CC 33 CC 54 03 FD 8C 82 8D
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+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$bch3121_encode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_encode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_decode_parity$0$0({2}DF,SL:U),C,0,0
+S:G$bch3121_syndrometable$0$0({2048}DA1024d,SI:U),D,0,0
+
+
+
+
+wrnum16
+
+;!FILE libmflarge/wrnum16.asm
+XH3
+H 1A areas 48 global symbols
+M wrnum16
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 62 flags 20 addr 0
+S A$wrnum16$160 Def000043
+S A$wrnum16$151 Def00003A
+S A$wrnum16$142 Def00002A
+S A$wrnum16$133 Def00001C
+S A$wrnum16$124 Def000010
+S A$wrnum16$115 Def000000
+S A$wrnum16$161 Def000044
+S A$wrnum16$143 Def00002C
+S A$wrnum16$134 Def00001E
+S A$wrnum16$125 Def000011
+S A$wrnum16$116 Def000002
+S A$wrnum16$180 Def00005B
+S A$wrnum16$171 Def00004E
+S A$wrnum16$162 Def000045
+S A$wrnum16$153 Def00003C
+S A$wrnum16$144 Def00002F
+S A$wrnum16$135 Def000020
+S A$wrnum16$126 Def000012
+S A$wrnum16$117 Def000004
+S A$wrnum16$181 Def00005D
+S A$wrnum16$172 Def00004F
+S A$wrnum16$163 Def000046
+S A$wrnum16$154 Def00003D
+S A$wrnum16$145 Def000031
+S A$wrnum16$136 Def000021
+S A$wrnum16$127 Def000014
+S A$wrnum16$118 Def000006
+S A$wrnum16$182 Def00005F
+S A$wrnum16$173 Def000050
+S A$wrnum16$164 Def000048
+S A$wrnum16$155 Def00003E
+S A$wrnum16$146 Def000033
+S A$wrnum16$137 Def000024
+S A$wrnum16$128 Def000016
+S A$wrnum16$119 Def000008
+S A$wrnum16$183 Def000061
+S A$wrnum16$174 Def000051
+S A$wrnum16$165 Def000049
+S A$wrnum16$156 Def00003F
+S A$wrnum16$147 Def000034
+S A$wrnum16$129 Def000017
+S A$wrnum16$175 Def000053
+S A$wrnum16$166 Def00004A
+S A$wrnum16$157 Def000040
+S A$wrnum16$148 Def000036
+S A$wrnum16$139 Def000026
+S A$wrnum16$176 Def000055
+S A$wrnum16$167 Def00004B
+S A$wrnum16$158 Def000041
+S A$wrnum16$149 Def000038
+S C$wrnum16.c$87$1$30 Def000000
+S C$wrnum16.c$12$0$0 Def000000
+S A$wrnum16$168 Def00004C
+S A$wrnum16$159 Def000042
+S C$wrnum16.c$88$1$30 Def000062
+S A$wrnum16$178 Def000057
+S A$wrnum16$169 Def00004D
+S A$wrnum16$179 Def000059
+S G$libmf_num16_digit$0$0 Def000000
+S _libmf_num16_digit Def000000
+S XG$libmf_num16_digit$0$0 Def000062
+S A$wrnum16$120 Def00000A
+S A$wrnum16$130 Def000018
+S A$wrnum16$121 Def00000C
+S A$wrnum16$140 Def000027
+S A$wrnum16$122 Def00000E
+S A$wrnum16$150 Def000039
+S A$wrnum16$141 Def000028
+S A$wrnum16$132 Def00001A
+S A$wrnum16$123 Def00000F
+A CONST size 20 flags 20 addr 0
+S Fwrnum16$subtbl$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 03 C0 06 C0 07 C0 00 C0 01 E5 81 24
+R 00 00 00 16
+T 00 00 0D F9 F8 E6 F8 E6 24 FA 50 04 E4 F6 80 3D
+R 00 00 00 16
+T 00 00 1A
+R 00 00 00 16
+T 00 00 1A 24 04 40 08 E5 82 F6 90 00 00 80 31
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 C4 03 AF 82 AE 83 90 00 00 25 82 F5 82
+R 00 00 00 16 00 0A 00 17
+T 00 00 33 E4 35 83 F5 83 E4 F6 74 08
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C F9 E4 93 A3 2F FB E4 93 A3 3E 50 06 FE
+R 00 00 00 16
+T 00 00 49 EB FF E6 49 F6
+R 00 00 00 16
+T 00 00 4E
+R 00 00 00 16
+T 00 00 4E E9 C3 13 70 E9 8F 82 8E 83
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 D0 01 D0 00 D0 07 D0 06 D0 03 22
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 B0 FF D8 FF EC FF F6 FF E0 FC 70 FE 38
+R 00 00 00 17
+T 00 00 0D FF 9C FF C0 E0 60 F0 30 F8 18 FC 00 00
+R 00 00 00 17
+T 00 00 1A C0 63 E0 B1 F0 D8
+R 00 00 00 17
+
+
+M:wrnum16
+F:G$libmf_num16_digit$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lwrnum16.libmf_num16_digit$dp$1$29({1}DD,SC:U),B,1,-3
+S:Lwrnum16.libmf_num16_digit$val$1$29({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num32_digit$0$0({2}DF,SL:U),C,0,0
+S:Fwrnum16$subtbl$0$0({32}DA16d,SI:U),D,0,0
+
+
+
+
+wrnum32
+
+;!FILE libmflarge/wrnum32.asm
+XH3
+H 1A areas 62 global symbols
+M wrnum32
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 87 flags 20 addr 0
+S A$wrnum32$207 Def000082
+S A$wrnum32$180 Def00005D
+S A$wrnum32$171 Def000053
+S A$wrnum32$162 Def00004A
+S A$wrnum32$153 Def00003F
+S A$wrnum32$144 Def00002F
+S A$wrnum32$135 Def000020
+S A$wrnum32$126 Def000015
+S A$wrnum32$117 Def000004
+S A$wrnum32$208 Def000084
+S A$wrnum32$190 Def000069
+S A$wrnum32$181 Def00005F
+S A$wrnum32$172 Def000054
+S A$wrnum32$163 Def00004B
+S A$wrnum32$154 Def000040
+S A$wrnum32$127 Def000016
+S A$wrnum32$118 Def000006
+S A$wrnum32$209 Def000086
+S A$wrnum32$182 Def000060
+S A$wrnum32$173 Def000055
+S A$wrnum32$164 Def00004C
+S A$wrnum32$155 Def000042
+S A$wrnum32$146 Def000031
+S A$wrnum32$137 Def000022
+S A$wrnum32$128 Def000017
+S A$wrnum32$119 Def000008
+S A$wrnum32$192 Def00006A
+S A$wrnum32$183 Def000062
+S A$wrnum32$174 Def000056
+S A$wrnum32$165 Def00004D
+S A$wrnum32$156 Def000044
+S A$wrnum32$147 Def000032
+S A$wrnum32$138 Def000024
+S A$wrnum32$129 Def000018
+S A$wrnum32$193 Def00006B
+S A$wrnum32$184 Def000063
+S A$wrnum32$175 Def000057
+S A$wrnum32$166 Def00004E
+S A$wrnum32$157 Def000045
+S A$wrnum32$148 Def000034
+S A$wrnum32$139 Def000026
+S A$wrnum32$194 Def00006C
+S A$wrnum32$185 Def000064
+S A$wrnum32$176 Def000059
+S A$wrnum32$167 Def00004F
+S A$wrnum32$158 Def000046
+S A$wrnum32$149 Def000036
+S A$wrnum32$195 Def00006D
+S A$wrnum32$186 Def000065
+S A$wrnum32$177 Def00005A
+S A$wrnum32$168 Def000050
+S A$wrnum32$196 Def00006F
+S A$wrnum32$187 Def000066
+S A$wrnum32$178 Def00005B
+S A$wrnum32$169 Def000051
+S A$wrnum32$197 Def000071
+S A$wrnum32$188 Def000067
+S A$wrnum32$179 Def00005C
+S A$wrnum32$198 Def000073
+S A$wrnum32$189 Def000068
+S A$wrnum32$199 Def000075
+S C$wrnum32.c$17$0$0 Def000000
+S G$libmf_num32_digit$0$0 Def000000
+S _libmf_num32_digit Def000000
+S C$wrnum32.c$118$1$30 Def000000
+S C$wrnum32.c$119$1$30 Def000087
+S XG$libmf_num32_digit$0$0 Def000087
+S A$wrnum32$201 Def000076
+S A$wrnum32$120 Def00000A
+S A$wrnum32$202 Def000078
+S A$wrnum32$130 Def000019
+S A$wrnum32$121 Def00000C
+S A$wrnum32$203 Def00007A
+S A$wrnum32$140 Def000028
+S A$wrnum32$131 Def00001B
+S A$wrnum32$122 Def00000E
+S A$wrnum32$204 Def00007C
+S A$wrnum32$150 Def000038
+S A$wrnum32$141 Def000029
+S A$wrnum32$132 Def00001D
+S A$wrnum32$123 Def000010
+S A$wrnum32$205 Def00007E
+S A$wrnum32$160 Def000048
+S A$wrnum32$151 Def00003B
+S A$wrnum32$142 Def00002A
+S A$wrnum32$133 Def00001E
+S A$wrnum32$124 Def000011
+S A$wrnum32$115 Def000000
+S A$wrnum32$206 Def000080
+S A$wrnum32$170 Def000052
+S A$wrnum32$161 Def000049
+S A$wrnum32$152 Def00003D
+S A$wrnum32$143 Def00002C
+S A$wrnum32$134 Def00001F
+S A$wrnum32$125 Def000013
+S A$wrnum32$116 Def000002
+A CONST size 90 flags 20 addr 0
+S Fwrnum32$subtbl$0$0 Def000000
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 02 C0 03 C0 04 C0 05 C0 06 C0 07 C0
+R 00 00 00 16
+T 00 00 0D 00 C0 01 FC E5 81 24 F6 F8 E6 F8 E6 24
+R 00 00 00 16
+T 00 00 1A F5 50 05 E4 F6 EC 80 54
+R 00 00 00 16
+T 00 00 22
+R 00 00 00 16
+T 00 00 22 24 09 40 0B E5 82 F6 E4 F5 F0 90 00 00
+R 00 00 00 16
+T 00 00 2F 80 45
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 C4 AF 82 AE 83 AD F0 90 00 00 25 82 F5
+R 00 00 00 16 00 0B 00 17
+T 00 00 3E 82 E4 35 83 F5 83 E4 F6 74 08
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 F9 E4 93 A3 2F FB E4 93 A3 3E FA E4 93
+R 00 00 00 16
+T 00 00 55 A3 3D F5 F0 E4 93 A3 3C 50 0B FC E5 F0
+R 00 00 00 16
+T 00 00 62 FD EA FE EB FF E6 49 F6
+R 00 00 00 16
+T 00 00 6A
+R 00 00 00 16
+T 00 00 6A E9 C3 13 70 D9 8F 82 8E 83 8D F0 EC
+R 00 00 00 16
+T 00 00 76
+R 00 00 00 16
+T 00 00 76 D0 01 D0 00 D0 07 D0 06 D0 05 D0 04 D0
+R 00 00 00 16
+T 00 00 83 03 D0 02 22
+R 00 00 00 16
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 B0 FF FF FF D8 FF FF FF EC FF FF FF F6
+R 00 00 00 17
+T 00 00 0D FF FF FF E0 FC FF FF 70 FE FF FF 38 FF
+R 00 00 00 17
+T 00 00 1A FF FF 9C FF FF FF C0 E0 FF FF 60 F0 FF
+R 00 00 00 17
+T 00 00 27 FF 30 F8 FF FF 18 FC FF FF 80 C7 FE FF
+R 00 00 00 17
+T 00 00 34 C0 63 FF FF E0 B1 FF FF F0 D8 FF FF 00
+R 00 00 00 17
+T 00 00 41 CB F3 FF 80 E5 F9 FF C0 F2 FC FF 60 79
+R 00 00 00 17
+T 00 00 4E FE FF 00 EE 85 FF 00 F7 C2 FF 80 7B E1
+R 00 00 00 17
+T 00 00 5B FF C0 BD F0 FF 00 4C 3B FB 00 A6 9D FD
+R 00 00 00 17
+T 00 00 68 00 D3 CE FE 80 69 67 FF 00 F8 50 D0 00
+R 00 00 00 17
+T 00 00 75 7C 28 E8 00 3E 14 F4 00 1F 0A FA 00 00
+R 00 00 00 17
+T 00 00 82 00 00 00 00 00 80 00 6C CA 88 00 36 65
+R 00 00 00 17
+T 00 00 8F C4
+R 00 00 00 17
+
+
+M:wrnum32
+F:G$libmf_num32_digit$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lwrnum32.libmf_num32_digit$dp$1$29({1}DD,SC:U),B,1,-3
+S:Lwrnum32.libmf_num32_digit$val$1$29({4}SL:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$libmf_num16_digit$0$0({2}DF,SI:U),C,0,0
+S:Fwrnum32$subtbl$0$0({144}DA36d,SL:U),D,0,0
+
+
+
+
+offxosc
+
+;!FILE libmflarge/offxosc.asm
+XH3
+H 1A areas 316 global symbols
+M offxosc
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 57 flags 20 addr 0
+S A$offxosc$1200 Def000014
+S A$offxosc$1210 Def000021
+S A$offxosc$1201 Def000017
+S A$offxosc$1202 Def000018
+S A$offxosc$1203 Def000019
+S A$offxosc$1240 Def000036
+S A$offxosc$1231 Def00002F
+S A$offxosc$1222 Def000028
+S A$offxosc$1213 Def000022
+S A$offxosc$1204 Def00001B
+S A$offxosc$1241 Def000039
+S A$offxosc$1223 Def00002B
+S A$offxosc$1205 Def00001C
+S A$offxosc$1260 Def000047
+S A$offxosc$1242 Def00003A
+S A$offxosc$1224 Def00002C
+S A$offxosc$1270 Def00004E
+S A$offxosc$1261 Def000048
+S A$offxosc$1243 Def00003B
+S A$offxosc$1234 Def000031
+S A$offxosc$1216 Def000024
+S A$offxosc$1280 Def000056
+S A$offxosc$1271 Def000051
+S A$offxosc$1244 Def00003D
+S A$offxosc$1208 Def00001D
+S A$offxosc$1190 Def00000A
+S A$offxosc$1272 Def000052
+S A$offxosc$1254 Def000041
+S A$offxosc$1245 Def00003E
+S A$offxosc$1227 Def00002D
+S A$offxosc$1209 Def00001F
+S A$offxosc$1191 Def00000D
+S A$offxosc$1264 Def00004A
+S A$offxosc$1237 Def000033
+S A$offxosc$1228 Def00002E
+S A$offxosc$1219 Def000026
+S A$offxosc$1192 Def00000E
+S A$offxosc$1193 Def00000F
+S A$offxosc$1184 Def000000
+S A$offxosc$1275 Def000053
+S A$offxosc$1257 Def000044
+S A$offxosc$1248 Def00003F
+S A$offxosc$1185 Def000003
+S A$offxosc$1276 Def000054
+S A$offxosc$1267 Def00004C
+S A$offxosc$1258 Def000045
+S A$offxosc$1186 Def000004
+S A$offxosc$1259 Def000046
+S A$offxosc$1196 Def000012
+S A$offxosc$1187 Def000005
+S G$turn_off_xosc$0$0 Def000000
+S A$offxosc$1188 Def000008
+S C$offxosc.c$20$1$33 Def00002D
+S C$offxosc.c$30$1$33 Def00004C
+S C$offxosc.c$21$1$33 Def00002F
+S C$offxosc.c$12$1$33 Def000000
+S C$offxosc.c$31$1$33 Def00004E
+S C$offxosc.c$22$1$33 Def000031
+S C$offxosc.c$13$1$33 Def000012
+S C$offxosc.c$32$1$33 Def000053
+S C$offxosc.c$23$1$33 Def000033
+S C$offxosc.c$14$1$33 Def000014
+S C$offxosc.c$33$1$33 Def000056
+S C$offxosc.c$24$1$33 Def000036
+S C$offxosc.c$15$1$33 Def00001D
+S C$offxosc.c$25$1$33 Def00003F
+S C$offxosc.c$16$1$33 Def000022
+S C$offxosc.c$26$1$33 Def000041
+S C$offxosc.c$17$1$33 Def000024
+S C$offxosc.c$18$1$33 Def000026
+S C$offxosc.c$28$1$33 Def000044
+S C$offxosc.c$19$1$33 Def000028
+S C$offxosc.c$29$1$33 Def00004A
+S C$offxosc.c$27$2$34 Def000041
+S _turn_off_xosc Def000000
+S XG$turn_off_xosc$0$0 Def000056
+S C$offxosc.c$8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 7F 00 E0 FF BF 8E 02 80 0A
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 90 7F 01 E0 FF 30 E1 02 80 42
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 90 7F 01 E0 FF 74 02 4F F0 74 80 55 A8
+R 00 00 00 16
+T 00 00 21 FF C2 AF AE 80 AD 89 90 7F 1A E0 FC E4
+R 00 00 00 16
+T 00 00 2E F0 D2 80 C2 81 43 89 03 90 70 50 E0 FB
+R 00 00 00 16
+T 00 00 3B 74 FB 5B F0 7B 06
+R 00 00 00 16
+T 00 00 41
+R 00 00 00 16
+T 00 00 41 63 80 03 EB 14 FA FB 70 F7 8D 89 8E 80
+R 00 00 00 16
+T 00 00 4E 90 7F 1A EC F0 EF 42 A8
+R 00 00 00 16
+T 00 00 56
+R 00 00 00 16
+T 00 00 56 22
+R 00 00 00 16
+
+
+M:offxosc
+F:G$turn_off_xosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Loffxosc.turn_off_xosc$iesave$1$33({1}SC:U),R,0,0,[r7]
+S:Loffxosc.turn_off_xosc$portasave$1$33({1}SC:U),R,0,0,[r6]
+S:Loffxosc.turn_off_xosc$dirasave$1$33({1}SC:U),R,0,0,[r5]
+S:Loffxosc.turn_off_xosc$xtalreadysave$1$33({1}SC:U),R,0,0,[r4]
+S:Loffxosc.turn_off_xosc$i$1$33({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
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+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+offlpxosc
+
+;!FILE libmflarge/offlpxosc.asm
+XH3
+H 1A areas 315 global symbols
+M offlpxosc
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S XG$turn_off_lpxosc$0$0 Def000053
+S C$offlpxosc.c$8$0$0 Def000000
+S A$offlpxosc$1200 Def000014
+S A$offlpxosc$1210 Def000021
+S A$offlpxosc$1201 Def000017
+S A$offlpxosc$1202 Def000018
+S A$offlpxosc$1203 Def000019
+S A$offlpxosc$1231 Def00002F
+S A$offlpxosc$1222 Def000028
+S A$offlpxosc$1213 Def000022
+S A$offlpxosc$1204 Def00001B
+S A$offlpxosc$1232 Def000032
+S A$offlpxosc$1205 Def00001C
+S A$offlpxosc$1233 Def000033
+S A$offlpxosc$1252 Def00003D
+S A$offlpxosc$1234 Def000034
+S A$offlpxosc$1225 Def00002A
+S A$offlpxosc$1216 Def000024
+S A$offlpxosc$1280 Def000053
+S A$offlpxosc$1262 Def000046
+S A$offlpxosc$1253 Def00003E
+S A$offlpxosc$1235 Def000036
+S A$offlpxosc$1208 Def00001D
+S A$offlpxosc$1190 Def00000A
+S A$offlpxosc$1272 Def00004E
+S A$offlpxosc$1263 Def000047
+S A$offlpxosc$1254 Def00003F
+S A$offlpxosc$1245 Def00003A
+S A$offlpxosc$1236 Def000037
+S A$offlpxosc$1209 Def00001F
+S A$offlpxosc$1191 Def00000D
+S A$offlpxosc$1264 Def000048
+S A$offlpxosc$1255 Def000040
+S A$offlpxosc$1228 Def00002C
+S A$offlpxosc$1219 Def000026
+S A$offlpxosc$1192 Def00000E
+S A$offlpxosc$1265 Def000049
+S A$offlpxosc$1256 Def000041
+S A$offlpxosc$1193 Def00000F
+S A$offlpxosc$1184 Def000000
+S A$offlpxosc$1275 Def000050
+S A$offlpxosc$1266 Def00004A
+S A$offlpxosc$1239 Def000038
+S A$offlpxosc$1185 Def000003
+S A$offlpxosc$1276 Def000051
+S A$offlpxosc$1249 Def00003C
+S A$offlpxosc$1186 Def000004
+S A$offlpxosc$1259 Def000043
+S A$offlpxosc$1196 Def000012
+S A$offlpxosc$1187 Def000005
+S G$turn_off_lpxosc$0$0 Def000000
+S A$offlpxosc$1269 Def00004C
+S A$offlpxosc$1188 Def000008
+S C$offlpxosc.c$20$1$33 Def00002A
+S C$offlpxosc.c$30$1$33 Def000046
+S C$offlpxosc.c$21$1$33 Def00002C
+S C$offlpxosc.c$12$1$33 Def000000
+S C$offlpxosc.c$31$1$33 Def00004C
+S C$offlpxosc.c$22$1$33 Def00002F
+S C$offlpxosc.c$13$1$33 Def000012
+S C$offlpxosc.c$32$1$33 Def00004E
+S C$offlpxosc.c$23$1$33 Def000038
+S C$offlpxosc.c$14$1$33 Def000014
+S C$offlpxosc.c$33$1$33 Def000050
+S C$offlpxosc.c$24$1$33 Def00003A
+S C$offlpxosc.c$15$1$33 Def00001D
+S C$offlpxosc.c$34$1$33 Def000053
+S C$offlpxosc.c$16$1$33 Def000022
+S C$offlpxosc.c$25$2$33 Def00003A
+S C$offlpxosc.c$17$1$33 Def000024
+S C$offlpxosc.c$18$1$33 Def000026
+S C$offlpxosc.c$19$1$33 Def000028
+S _turn_off_lpxosc Def000000
+S C$offlpxosc.c$28$2$34 Def00003D
+S C$offlpxosc.c$29$2$34 Def000043
+S C$offlpxosc.c$27$3$35 Def00003C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 90 7F 00 E0 FF BF 8E 02 80 0A
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 90 7F 01 E0 FF 30 E0 02 80 3F
+R 00 00 00 16
+T 00 00 14
+R 00 00 00 16
+T 00 00 14 90 7F 01 E0 FF 74 01 4F F0 74 80 55 A8
+R 00 00 00 16
+T 00 00 21 FF C2 AF AE 80 AD 89 D2 84 C2 85 43 89
+R 00 00 00 16
+T 00 00 2E 18 90 70 50 E0 FC 74 F7 5C F0 7C 06
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A 7B 80
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 00 EB 14 FA FB 70 F9 63 80 18 EC 14 FB
+R 00 00 00 16
+T 00 00 49 FC 70 EE 8D 89 8E 80 EF 42 A8
+R 00 00 00 16
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 22
+R 00 00 00 16
+
+
+M:offlpxosc
+F:G$turn_off_lpxosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lofflpxosc.turn_off_lpxosc$iesave$1$33({1}SC:U),R,0,0,[r7]
+S:Lofflpxosc.turn_off_lpxosc$portasave$1$33({1}SC:U),R,0,0,[r6]
+S:Lofflpxosc.turn_off_lpxosc$dirasave$1$33({1}SC:U),R,0,0,[r5]
+S:Lofflpxosc.turn_off_lpxosc$i$1$33({1}SC:U),R,0,0,[r4]
+S:Lofflpxosc.turn_off_lpxosc$j$2$34({1}SC:U),R,0,0,[r3]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setuplpxosc
+
+;!FILE libmflarge/setuplpxosc.asm
+XH3
+H 1A areas 2E3 global symbols
+M setuplpxosc
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1D flags 20 addr 0
+S C$setuplpxosc.c$8$0$0 Def000000
+S _setup_lpxosc Def000000
+S XG$setup_lpxosc$0$0 Def00001C
+S A$setuplpxosc$1202 Def00001C
+S A$setuplpxosc$1180 Def000005
+S A$setuplpxosc$1190 Def00000E
+S A$setuplpxosc$1181 Def000006
+S A$setuplpxosc$1182 Def000007
+S A$setuplpxosc$1183 Def000009
+S A$setuplpxosc$1193 Def000011
+S A$setuplpxosc$1184 Def00000A
+S A$setuplpxosc$1194 Def000014
+S A$setuplpxosc$1176 Def000000
+S A$setuplpxosc$1195 Def000015
+S A$setuplpxosc$1196 Def000016
+S A$setuplpxosc$1187 Def00000B
+S A$setuplpxosc$1197 Def000018
+S A$setuplpxosc$1179 Def000002
+S A$setuplpxosc$1198 Def000019
+S C$setuplpxosc.c$10$1$33 Def000002
+S A$setuplpxosc$1199 Def00001A
+S C$setuplpxosc.c$11$1$33 Def00000B
+S C$setuplpxosc.c$12$1$33 Def00000E
+S C$setuplpxosc.c$13$1$33 Def000011
+S C$setuplpxosc.c$14$1$33 Def00001C
+S G$setup_lpxosc$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 90 70 07 E0 FF 74 18 4F F0 53 89
+R 00 00 00 16
+T 00 00 0D E7 53 80 E7 90 7F 01 E0 FF 74 FE 5F F0
+R 00 00 00 16
+T 00 00 1A D0 07 22
+R 00 00 00 16
+
+
+M:setuplpxosc
+F:G$setup_lpxosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setupxosc
+
+;!FILE libmflarge/setupxosc.asm
+XH3
+H 1A areas 2E3 global symbols
+M setupxosc
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1D flags 20 addr 0
+S A$setupxosc$1180 Def000005
+S A$setupxosc$1190 Def00000E
+S A$setupxosc$1181 Def000006
+S A$setupxosc$1182 Def000007
+S A$setupxosc$1183 Def000009
+S A$setupxosc$1193 Def000011
+S A$setupxosc$1184 Def00000A
+S A$setupxosc$1194 Def000014
+S A$setupxosc$1176 Def000000
+S A$setupxosc$1195 Def000015
+S A$setupxosc$1196 Def000016
+S A$setupxosc$1187 Def00000B
+S A$setupxosc$1197 Def000018
+S A$setupxosc$1179 Def000002
+S A$setupxosc$1198 Def000019
+S C$setupxosc.c$10$1$33 Def000002
+S A$setupxosc$1199 Def00001A
+S C$setupxosc.c$11$1$33 Def00000B
+S C$setupxosc.c$12$1$33 Def00000E
+S C$setupxosc.c$13$1$33 Def000011
+S C$setupxosc.c$14$1$33 Def00001C
+S G$setup_xosc$0$0 Def000000
+S C$setupxosc.c$8$0$0 Def000000
+S _setup_xosc Def000000
+S XG$setup_xosc$0$0 Def00001C
+S A$setupxosc$1202 Def00001C
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 C0 07 90 70 07 E0 FF 74 03 4F F0 53 89
+R 00 00 00 16
+T 00 00 0D FC 53 80 FC 90 7F 01 E0 FF 74 FD 5F F0
+R 00 00 00 16
+T 00 00 1A D0 07 22
+R 00 00 00 16
+
+
+M:setupxosc
+F:G$setup_xosc$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_osc_calibration$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+setupcal
+
+;!FILE libmflarge/setupcal.asm
+XH3
+H 1A areas 492 global symbols
+M setupcal
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S __divulong_PARM_2 Ref000000
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _setup_lpxosc Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S __divulong Ref000000
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
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+S G$ADCCH3VAL0$0$0 Def007026
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+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
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+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S _setup_xosc Ref000000
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+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S _bp Ref000000
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+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
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+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
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+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
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+A GSINIT size 0 flags 20 addr 0
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+S A$setupcal$1696 Def000233
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+S C$setupcal.c$50$2$40 Def000131
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+S C$setupcal.c$13$2$34 Def00001A
+S C$setupcal.c$53$2$40 Def00013E
+S C$setupcal.c$14$2$34 Def00001E
+S C$setupcal.c$30$2$37 Def00006F
+S C$setupcal.c$15$2$34 Def000022
+S C$setupcal.c$72$1$42 Def00017C
+S C$setupcal.c$31$2$37 Def000078
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+S C$setupcal.c$73$1$42 Def00019C
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+S C$setupcal.c$32$2$37 Def00009C
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+S C$setupcal.c$84$2$43 Def0001EE
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+S C$setupcal.c$64$1$39 Def000168
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+S Fsetupcal$compute_frcoscref$0$0 Def00004D
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+S C$setupcal.c$66$1$39 Def000169
+S C$setupcal.c$48$1$39 Def0000FF
+S G$setup_osc_calibration$0$0 Def000169
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+S C$setupcal.c$113$1$42 Def000242
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+S A$setupcal$1700 Def000235
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+S A$setupcal$1214 Def000024
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+S C$setupcal.c$114$1$42 Def00024B
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+S A$setupcal$1620 Def0001EA
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+S A$setupcal$1720 Def000245
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+M:setupcal
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+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$setup_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:Fsetupcal$compute_frcosccfg$0$0({2}DF,SC:U),C,0,0
+S:Fsetupcal$compute_frcoscref$0$0({2}DF,SV:S),C,0,4
+S:Fsetupcal$compute_lposccfg$0$0({2}DF,SC:U),C,0,0
+S:Lsetupcal.compute_frcoscref$refs$1$36({36}DA9d,SL:U),D,0,0
+
+
+
+
+wtimer
+
+;!FILE libmflarge/wtimer.asm
+XH3
+H 21 areas 691 global symbols
+M wtimer
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _enter_sleep_cont Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S _enter_standby Ref000000
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S _enter_sleep Ref000000
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A BIT_BANK size 1 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 12 flags 40 addr 0
+S G$wtimer_state$0$0 Def000000
+S G$wtimer_pending$0$0 Def000010
+S _wtimer_state Def000000
+S _wtimer_pending Def000010
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 1BB flags 20 addr 0
+S C$wtimer.c$28$2$62 Def000038
+S C$wtimer.c$23$1$59 Def000021
+S C$wtimer.c$18$1$59 Def000000
+S Fwtimer$dummy1$0$0 Def00006B
+S Fwtimer$dummy3$0$0 Def000113
+S _wtimer0_update Def0000E7
+S XG$wtimer0_schedq$0$0 Def0000E6
+S _wtimer1_update Def00018F
+S Fwtimer$dummy5$0$0 Def0001BB
+S XG$wtimer1_schedq$0$0 Def00018E
+S XG$wtimer0_update$0$0 Def000113
+S XG$wtimer1_update$0$0 Def0001BB
+S G$wtimer_irq$0$0 Def000000
+S XFwtimer$dummy0$0$0 Def000000
+S XFwtimer$dummy2$0$0 Def00006B
+S XFwtimer$dummy4$0$0 Def000113
+S _wtimer_irq Def000000
+S A$wtimer$2000 Def00017B
+S A$wtimer$2010 Def000189
+S A$wtimer$2001 Def00017C
+S A$wtimer$2011 Def00018A
+S A$wtimer$2002 Def00017D
+S A$wtimer$1300 Def000056
+S A$wtimer$2030 Def00018F
+S A$wtimer$2012 Def00018B
+S A$wtimer$1301 Def000058
+S A$wtimer$2040 Def00019D
+S A$wtimer$2031 Def000191
+S A$wtimer$2013 Def00018D
+S A$wtimer$2004 Def000180
+S A$wtimer$1302 Def00005A
+S A$wtimer$2050 Def0001AB
+S A$wtimer$2041 Def00019E
+S A$wtimer$2032 Def000193
+S A$wtimer$2005 Def000183
+S A$wtimer$1312 Def00006A
+S A$wtimer$1303 Def00005C
+S A$wtimer$1240 Def00000C
+S A$wtimer$2060 Def0001B6
+S A$wtimer$2051 Def0001AC
+S A$wtimer$2042 Def00019F
+S A$wtimer$2033 Def000196
+S A$wtimer$2006 Def000184
+S A$wtimer$1700 Def0000D8
+S A$wtimer$1304 Def00005E
+S A$wtimer$1241 Def00000E
+S A$wtimer$2061 Def0001B7
+S A$wtimer$2052 Def0001AD
+S A$wtimer$2043 Def0001A0
+S A$wtimer$2034 Def000197
+S A$wtimer$2016 Def00018E
+S A$wtimer$2007 Def000185
+S A$wtimer$1701 Def0000DB
+S A$wtimer$1611 Def00006B
+S A$wtimer$1305 Def000060
+S A$wtimer$1260 Def000026
+S A$wtimer$1251 Def00001F
+S A$wtimer$1242 Def000010
+S A$wtimer$2062 Def0001B9
+S A$wtimer$2053 Def0001AE
+S A$wtimer$2044 Def0001A1
+S A$wtimer$2035 Def000198
+S A$wtimer$2008 Def000186
+S A$wtimer$1702 Def0000DC
+S A$wtimer$1621 Def000079
+S A$wtimer$1612 Def00006E
+S A$wtimer$1306 Def000062
+S A$wtimer$1270 Def000034
+S A$wtimer$1261 Def000027
+S A$wtimer$1243 Def000012
+S A$wtimer$1234 Def000000
+S A$wtimer$2054 Def0001AF
+S A$wtimer$2045 Def0001A2
+S A$wtimer$2036 Def000199
+S A$wtimer$2009 Def000187
+S A$wtimer$1730 Def0000EF
+S A$wtimer$1712 Def0000E6
+S A$wtimer$1703 Def0000DD
+S A$wtimer$1640 Def000092
+S A$wtimer$1622 Def00007C
+S A$wtimer$1613 Def00006F
+S A$wtimer$1307 Def000064
+S A$wtimer$1280 Def00003D
+S A$wtimer$1271 Def000036
+S A$wtimer$1244 Def000014
+S A$wtimer$1235 Def000002
+S C$wtimer.c$510$1$90 Def00018F
+S A$wtimer$2064 Def0001BA
+S A$wtimer$2055 Def0001B0
+S A$wtimer$2046 Def0001A4
+S A$wtimer$2037 Def00019A
+S A$wtimer$1920 Def00011A
+S A$wtimer$1740 Def0000F9
+S A$wtimer$1731 Def0000F0
+S A$wtimer$1704 Def0000DE
+S A$wtimer$1650 Def00009E
+S A$wtimer$1641 Def000093
+S A$wtimer$1632 Def000088
+S A$wtimer$1623 Def00007D
+S A$wtimer$1614 Def000070
+S A$wtimer$1308 Def000066
+S A$wtimer$1254 Def000021
+S A$wtimer$1245 Def000016
+S A$wtimer$1236 Def000004
+S C$wtimer.c$301$1$84 Def000113
+S A$wtimer$2056 Def0001B1
+S A$wtimer$2047 Def0001A6
+S A$wtimer$2038 Def00019B
+S A$wtimer$1930 Def00012A
+S A$wtimer$1921 Def00011B
+S A$wtimer$1750 Def000107
+S A$wtimer$1741 Def0000FA
+S A$wtimer$1732 Def0000F1
+S A$wtimer$1705 Def0000DF
+S A$wtimer$1660 Def0000A8
+S A$wtimer$1651 Def00009F
+S A$wtimer$1642 Def000094
+S A$wtimer$1633 Def00008A
+S A$wtimer$1624 Def00007F
+S A$wtimer$1615 Def000071
+S A$wtimer$1309 Def000068
+S A$wtimer$1291 Def00004A
+S A$wtimer$1264 Def00002A
+S A$wtimer$1246 Def000018
+S A$wtimer$1237 Def000006
+S XG$wtimer_irq$0$0 Def00006A
+S A$wtimer$2057 Def0001B2
+S A$wtimer$2048 Def0001A9
+S A$wtimer$2039 Def00019C
+S A$wtimer$1940 Def000136
+S A$wtimer$1931 Def00012B
+S A$wtimer$1922 Def00011E
+S A$wtimer$1760 Def000112
+S A$wtimer$1751 Def000108
+S A$wtimer$1742 Def0000FC
+S A$wtimer$1733 Def0000F2
+S A$wtimer$1706 Def0000E1
+S A$wtimer$1670 Def0000B3
+S A$wtimer$1661 Def0000A9
+S A$wtimer$1652 Def0000A0
+S A$wtimer$1643 Def000095
+S A$wtimer$1634 Def00008C
+S A$wtimer$1625 Def000081
+S A$wtimer$1616 Def000072
+S A$wtimer$1283 Def000040
+S A$wtimer$1274 Def000038
+S A$wtimer$1265 Def00002C
+S A$wtimer$1247 Def00001A
+S A$wtimer$1238 Def000008
+S C$wtimer.c$253$1$80 Def00006B
+S A$wtimer$2058 Def0001B4
+S A$wtimer$2049 Def0001AA
+S A$wtimer$1950 Def000140
+S A$wtimer$1941 Def000137
+S A$wtimer$1932 Def00012D
+S A$wtimer$1752 Def000109
+S A$wtimer$1743 Def0000FE
+S A$wtimer$1734 Def0000F3
+S A$wtimer$1707 Def0000E2
+S A$wtimer$1680 Def0000C0
+S A$wtimer$1671 Def0000B5
+S A$wtimer$1662 Def0000AA
+S A$wtimer$1653 Def0000A1
+S A$wtimer$1644 Def000096
+S A$wtimer$1635 Def00008D
+S A$wtimer$1626 Def000082
+S A$wtimer$1617 Def000073
+S A$wtimer$1284 Def000042
+S A$wtimer$1275 Def00003A
+S A$wtimer$1266 Def00002E
+S A$wtimer$1257 Def000023
+S A$wtimer$1248 Def00001C
+S A$wtimer$1239 Def00000A
+S C$wtimer.c$254$1$80 Def0000E6
+S A$wtimer$2059 Def0001B5
+S A$wtimer$1960 Def00014C
+S A$wtimer$1951 Def000141
+S A$wtimer$1942 Def000138
+S A$wtimer$1933 Def00012F
+S A$wtimer$1915 Def000113
+S A$wtimer$1753 Def00010A
+S A$wtimer$1744 Def000101
+S A$wtimer$1735 Def0000F4
+S A$wtimer$1726 Def0000E7
+S A$wtimer$1708 Def0000E3
+S A$wtimer$1690 Def0000CB
+S A$wtimer$1681 Def0000C1
+S A$wtimer$1672 Def0000B6
+S A$wtimer$1663 Def0000AB
+S A$wtimer$1654 Def0000A2
+S A$wtimer$1645 Def000097
+S A$wtimer$1636 Def00008E
+S A$wtimer$1627 Def000083
+S A$wtimer$1618 Def000076
+S C$wtimer.c$506$1$90 Def000113
+S C$wtimer.c$400$1$88 Def000113
+S A$wtimer$1970 Def000156
+S A$wtimer$1961 Def00014D
+S A$wtimer$1952 Def000142
+S A$wtimer$1943 Def000139
+S A$wtimer$1925 Def000121
+S A$wtimer$1916 Def000116
+S A$wtimer$1754 Def00010C
+S A$wtimer$1745 Def000102
+S A$wtimer$1736 Def0000F5
+S A$wtimer$1727 Def0000E9
+S A$wtimer$1709 Def0000E5
+S A$wtimer$1691 Def0000CC
+S A$wtimer$1673 Def0000B7
+S A$wtimer$1664 Def0000AC
+S A$wtimer$1655 Def0000A3
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+S G$wtimer1_schedq$0$0 Def000113
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+T 00 01 F8
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+T 00 01 F8 8B 82 8C 83 E0 F9 A3 E0 FA 90 00 10 E9
+R 00 00 00 17 00 0D 00 0B
+T 00 02 05 F0 EA A3 F0 EE 42 A8 0D 8B 82 8C 83 A3
+R 00 00 00 17
+T 00 02 12 A3 E0 F9 A3 E0 FA C0 06 C0 05 C0 02 C0
+R 00 00 00 17
+T 00 02 1F 01 12 02 25 80 09
+R 00 00 00 17 00 05 00 17
+T 00 02 25
+R 00 00 00 17
+T 00 02 25 C0 01 C0 02 8B 82 8C 83 22
+R 00 00 00 17
+T 00 02 2E
+R 00 00 00 17
+T 00 02 2E D0 01 D0 02 D0 05 D0 06 C2 AF 80 AE
+R 00 00 00 17
+T 00 02 3A
+R 00 00 00 17
+T 00 02 3A 8D 07 12 01 9C AC 82 EE 42 A8 EC 70 84
+R 00 00 00 17 00 06 00 17
+T 00 02 47 8D 82 22
+R 00 00 00 17
+T 00 02 4A
+R 00 00 00 17
+T 00 02 4A AF 82 74 80 55 A8 FE C2 AF 90 00 10 E0
+R 00 00 00 17 00 0D 00 0B
+T 00 02 57 FC A3 E0 FD BC FF 0A BD FF 07 12 01 9C
+R 00 00 00 17 00 0E 00 17
+T 00 02 64 E5 82 60 08
+R 00 00 00 17
+T 00 02 68
+R 00 00 00 17
+T 00 02 68 EE 42 A8 75 82 01 80 5D
+R 00 00 00 17
+T 00 02 70
+R 00 00 00 17
+T 00 02 70 EF 54 05 60 4B C0 07 C0 06 12 00 04 E5
+R 00 00 00 17 00 0D 00 18
+T 00 02 7D 82 D0 06 D0 07 60 3C 12 01 43 74 F0 24
+R 00 00 00 17 00 0B 00 17
+T 00 02 8A 00 00 00 40 08 74 0C 55 87 44 04 F5 87
+R 00 00 00 17 F1 81 03 00 0B
+T 00 02 95
+R 00 00 00 17
+T 00 02 95 C3 74 00 00 00 94 F8 74 00 00 00 94 0F
+R 00 00 00 17 F1 01 05 00 0B F1 81 0B 00 0B
+T 00 02 9E 40 08 74 0C 55 87 44 08 F5 87
+R 00 00 00 17
+T 00 02 A8
+R 00 00 00 17
+T 00 02 A8 EF 30 E2 0F C0 06 12 00 00 D0 06 EE 42
+R 00 00 00 17 02 0A 00 5B
+T 00 02 B5 A8 75 82 02 80 12
+R 00 00 00 17
+T 00 02 BB
+R 00 00 00 17
+T 00 02 BB 12 00 00 80 07
+R 00 00 00 17 02 04 02 32
+T 00 02 C0
+R 00 00 00 17
+T 00 02 C0 EF 30 E1 03 12 00 00
+R 00 00 00 17 02 08 00 CE
+T 00 02 C7
+R 00 00 00 17
+T 00 02 C7 EE 42 A8 75 82 00
+R 00 00 00 17
+T 00 02 CD
+R 00 00 00 17
+T 00 02 CD 22
+R 00 00 00 17
+
+
+M:wtimer
+F:Fwtimer$dummy0$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer_irq$0$0({2}DF,SV:S),Z,0,0,1,1,0
+F:Fwtimer$dummy1$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:Fwtimer$wtimer_doinit$0$0({2}DF,SV:S),C,0,0,0,0,0
+S:Lwtimer.wtimer_doinit$wakeup$1$66({1}SC:U),R,0,0,[r7]
+F:G$wtimer_init$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer_addcb_core$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer_addcb_core$desc$1$74({2}DX,STwtimer_callback:S),R,0,0,[r6,r7]
+S:Lwtimer.wtimer_addcb_core$d$1$75({2}DX,STwtimer_callback:S),R,0,0,[r4,r5]
+S:Lwtimer.wtimer_addcb_core$dn$2$76({2}DX,STwtimer_callback:S),R,0,0,[r2,r3]
+F:Fwtimer$dummy2$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer0_schedq$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer0_update$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fwtimer$dummy3$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer0_addcore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer0_addcore$desc$1$85({2}DX,STwtimer_desc:S),R,0,0,[]
+F:Fwtimer$dummy4$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer1_schedq$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$wtimer1_update$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:Fwtimer$dummy5$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer1_addcore$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtimer.wtimer1_addcore$desc$1$95({2}DX,STwtimer_desc:S),R,0,0,[]
+F:Fwtimer$wtimer_preparesleep$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:Fwtimer$wtimer_checkexpired$0$0({2}DF,SC:U),C,0,0,0,0,0
+F:Fwtimer$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0,0,0,0
+F:G$wtimer_runcallbacks$0$0({2}DF,SC:U),Z,0,0,0,0,0
+F:G$wtimer_idle$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtimer.wtimer_idle$flags$1$112({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_idle$iesave$1$113({1}SC:U),R,0,0,[r6]
+T:Fwtimer$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtimer$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtimer$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtimer$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:Lwtimer.wtimer_irq$dpssave$1$61({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_irq$s$1$61({1}SC:U),R,0,0,[r6]
+S:Lwtimer.wtimer_runcallbacks$ret$1$106({1}SC:U),R,0,0,[r7]
+S:Lwtimer.wtimer_runcallbacks$iesave$2$107({1}SC:U),R,0,0,[r6]
+S:Lwtimer.wtimer_runcallbacks$d$4$109({2}DX,STwtimer_callback:S),R,0,0,[r3,r4]
+S:Lwtimer.wtimer_runcallbacks$exp$4$111({1}SC:U),R,0,0,[r4]
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:Fwtimer$dummy0$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy1$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_doinit$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy2$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy3$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy4$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$dummy5$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_preparesleep$0$0({2}DF,SV:S),C,0,0
+S:Fwtimer$wtimer_checkexpired$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:Fwtimer$wtimer_cansleep_dummy$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wtrem
+
+;!FILE libmflarge/wtrem.asm
+XH3
+H 1A areas 30C global symbols
+M wtrem
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S _wtimer_pending Ref000000
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 51 flags 20 addr 0
+S A$wtrem$1232 Def000037
+S A$wtrem$1223 Def00002F
+S A$wtrem$1214 Def000024
+S A$wtrem$1205 Def000019
+S A$wtrem$1260 Def000047
+S A$wtrem$1233 Def00003A
+S A$wtrem$1224 Def000031
+S A$wtrem$1215 Def000026
+S A$wtrem$1206 Def00001B
+S A$wtrem$1261 Def000049
+S A$wtrem$1234 Def00003D
+S A$wtrem$1225 Def000032
+S A$wtrem$1216 Def000028
+S A$wtrem$1226 Def000033
+S A$wtrem$1217 Def000029
+S A$wtrem$1190 Def000006
+S A$wtrem$1281 Def00004B
+S A$wtrem$1227 Def000034
+S A$wtrem$1218 Def00002A
+S A$wtrem$1209 Def00001C
+S A$wtrem$1191 Def000008
+S A$wtrem$1282 Def00004D
+S A$wtrem$1237 Def00003F
+S A$wtrem$1228 Def000035
+S A$wtrem$1219 Def00002B
+S A$wtrem$1283 Def00004F
+S A$wtrem$1238 Def000041
+S A$wtrem$1184 Def000000
+S A$wtrem$1239 Def000043
+S A$wtrem$1194 Def00000A
+S A$wtrem$1185 Def000002
+S A$wtrem$1195 Def00000C
+S A$wtrem$1259 Def000045
+S A$wtrem$1196 Def00000E
+S A$wtrem$1197 Def00000F
+S A$wtrem$1188 Def000004
+S A$wtrem$1198 Def000010
+S A$wtrem$1199 Def000011
+S G$wtimer0_removecb_core$0$0 Def000045
+S G$wtimer1_removecb_core$0$0 Def00004B
+S C$wtrem.c$85$1$61 Def000045
+S C$wtrem.c$86$1$61 Def00004B
+S C$wtrem.c$95$1$63 Def00004B
+S C$wtrem.c$88$1$61 Def00004B
+S C$wtrem.c$96$1$63 Def000051
+S C$wtrem.c$75$1$59 Def000000
+S C$wtrem.c$76$1$59 Def000045
+S C$wtrem.c$78$1$59 Def000045
+S _wtimer0_removecb_core Def000045
+S _wtimer1_removecb_core Def00004B
+S G$wtimer_removecb_core$0$0 Def000000
+S C$wtrem.c$6$0$0 Def000000
+S XG$wtimer0_removecb_core$0$0 Def00004B
+S XG$wtimer1_removecb_core$0$0 Def000051
+S _wtimer_removecb_core Def000000
+S A$wtrem$1200 Def000012
+S A$wtrem$1210 Def00001D
+S A$wtrem$1220 Def00002C
+S A$wtrem$1211 Def000020
+S A$wtrem$1202 Def000013
+S XG$wtimer_removecb_core$0$0 Def000045
+S A$wtrem$1230 Def000036
+S A$wtrem$1212 Def000021
+S A$wtrem$1203 Def000016
+S A$wtrem$1222 Def00002D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 7C 00 00 00 7D 00 00 00
+R 00 00 00 16 F1 03 04 02 7E F1 83 08 02 7E
+T 00 00 04
+R 00 00 00 16
+T 00 00 04 78 00 AA 82 AB 83
+R 00 00 00 16
+T 00 00 0A
+R 00 00 00 16
+T 00 00 0A 8C 82 8D 83 E0 FE A3 E0 FF BE FF 06 BF
+R 00 00 00 16
+T 00 00 17 FF 03
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 88 82 22
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C EA B5 06 1F EB B5 07 1B 8E 82 8F 83 E0
+R 00 00 00 16
+T 00 00 29 FE A3 E0 FF 8C 82 8D 83 EE F0 A3 EF F0
+R 00 00 00 16
+T 00 00 36 08 BE FF 05 BF FF 02 80 DA
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F AC 06 AD 07 80 C5
+R 00 00 00 16
+T 00 00 45
+R 00 00 00 16
+T 00 00 45 7C 00 00 06 7D 00 00 06 80 B9
+R 00 00 00 16 F1 03 04 02 40 F1 83 08 02 40
+T 00 00 4B
+R 00 00 00 16
+T 00 00 4B 7C 00 00 0E 7D 00 00 0E 80 B3
+R 00 00 00 16 F1 03 04 02 40 F1 83 08 02 40
+
+
+M:wtrem
+F:G$wtimer_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer_removecb_core$desc$1$58({2}DX,STwtimer_callback:S),R,0,0,[]
+F:G$wtimer0_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer0_removecb_core$desc$1$60({2}DX,STwtimer_desc:S),R,0,0,[]
+F:G$wtimer1_removecb_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lwtrem.wtimer1_removecb_core$desc$1$62({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwtrem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtrem$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtrem$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtrem$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wtcbadd
+
+;!FILE libmflarge/wtcbadd.asm
+XH3
+H 1A areas 2E1 global symbols
+M wtcbadd
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S _wtimer_addcb_core Ref000000
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1A flags 20 addr 0
+S _wtimer_add_callback Def000000
+S C$wtcbadd.c$4$0$0 Def000000
+S C$wtcbadd.c$6$1$59 Def000004
+S C$wtcbadd.c$7$1$59 Def000009
+S C$wtcbadd.c$8$1$59 Def00000B
+S C$wtcbadd.c$9$1$59 Def000016
+S XG$wtimer_add_callback$0$0 Def000019
+S A$wtcbadd$1200 Def000017
+S A$wtcbadd$1203 Def000019
+S A$wtcbadd$1180 Def000000
+S A$wtcbadd$1181 Def000002
+S A$wtcbadd$1192 Def00000B
+S A$wtcbadd$1193 Def00000D
+S A$wtcbadd$1184 Def000004
+S A$wtcbadd$1194 Def00000F
+S A$wtcbadd$1185 Def000006
+S A$wtcbadd$1195 Def000011
+S A$wtcbadd$1186 Def000008
+S A$wtcbadd$1196 Def000014
+S A$wtcbadd$1189 Def000009
+S A$wtcbadd$1199 Def000016
+S C$wtcbadd.c$10$1$59 Def000019
+S G$wtimer_add_callback$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF 8E 82
+R 00 00 00 16
+T 00 00 0D 8F 83 C0 05 12 00 00 D0 05 ED 42 A8 22
+R 00 00 00 16 02 08 00 8C
+
+
+M:wtcbadd
+F:G$wtimer_add_callback$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwtcbadd.wtimer_add_callback$desc$1$58({2}DX,STwtimer_callback:S),R,0,0,[r6,r7]
+S:Lwtcbadd.wtimer_add_callback$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwtcbadd$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwtcbadd$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwtcbadd$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwtcbadd$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wtcbrem
+
+;!FILE libmflarge/wtcbrem.asm
+XH3
+H 1A areas 2E4 global symbols
+M wtcbrem
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S A$wtcbrem$1202 Def000018
+S A$wtcbrem$1203 Def000019
+S A$wtcbrem$1206 Def00001B
+S A$wtcbrem$1209 Def00001D
+S A$wtcbrem$1191 Def000009
+S A$wtcbrem$1182 Def000000
+S A$wtcbrem$1183 Def000002
+S A$wtcbrem$1194 Def00000B
+S A$wtcbrem$1195 Def00000D
+S A$wtcbrem$1186 Def000004
+S A$wtcbrem$1196 Def00000F
+S A$wtcbrem$1187 Def000006
+S A$wtcbrem$1197 Def000011
+S A$wtcbrem$1188 Def000008
+S A$wtcbrem$1198 Def000014
+S A$wtcbrem$1199 Def000016
+S C$wtcbrem.c$10$1$59 Def00000B
+S C$wtcbrem.c$11$1$59 Def000018
+S C$wtcbrem.c$12$1$59 Def00001B
+S C$wtcbrem.c$13$1$59 Def00001D
+S G$wtimer_remove_callback$0$0 Def000000
+S C$wtcbrem.c$4$0$0 Def000000
+S C$wtcbrem.c$8$1$59 Def000004
+S C$wtcbrem.c$9$1$59 Def000009
+S _wtimer_remove_callback Def000000
+S XG$wtimer_remove_callback$0$0 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
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+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF 8E 82
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+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0setcfg
+
+;!FILE libmflarge/wt0setcfg.asm
+XH3
+H 1A areas 2E4 global symbols
+M wt0setcfg
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S _wtimer0_setconfig Def000000
+S C$wt0setcfg.c$4$0$0 Def000000
+S C$wt0setcfg.c$6$1$59 Def000000
+S C$wt0setcfg.c$7$1$59 Def00000B
+S C$wt0setcfg.c$8$1$59 Def00000D
+S C$wt0setcfg.c$9$1$59 Def000010
+S XG$wtimer0_setconfig$0$0 Def00001D
+S A$wt0setcfg$1211 Def00001D
+S A$wt0setcfg$1202 Def000016
+S A$wt0setcfg$1203 Def000018
+S A$wt0setcfg$1204 Def000019
+S A$wt0setcfg$1207 Def00001B
+S A$wt0setcfg$1180 Def000000
+S A$wt0setcfg$1181 Def000002
+S A$wt0setcfg$1182 Def000003
+S A$wt0setcfg$1183 Def000005
+S A$wt0setcfg$1193 Def00000D
+S A$wt0setcfg$1184 Def000007
+S A$wt0setcfg$1185 Def000009
+S A$wt0setcfg$1196 Def000010
+S A$wt0setcfg$1189 Def00000B
+S A$wt0setcfg$1199 Def000013
+S C$wt0setcfg.c$10$1$59 Def000013
+S C$wt0setcfg.c$11$1$59 Def000016
+S G$wtimer0_setconfig$0$0 Def000000
+S C$wt0setcfg.c$12$1$59 Def00001B
+S C$wt0setcfg.c$13$1$59 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF 65 F1 54 3F 60 02 80 02
+R 00 00 00 16
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B 80 10
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D 53 07 3F 43 F1 04 75 F1 0F 74 FC 4F 52
+R 00 00 00 16
+T 00 00 1A F1 8F F1
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 22
+R 00 00 00 16
+
+
+M:wt0setcfg
+F:G$wtimer0_setconfig$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0setcfg.wtimer0_setconfig$cfg$1$58({1}SC:U),R,0,0,[r7]
+T:Fwt0setcfg$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0setcfg$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0setcfg$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0setcfg$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1setcfg
+
+;!FILE libmflarge/wt1setcfg.asm
+XH3
+H 1A areas 2E4 global symbols
+M wt1setcfg
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 1E flags 20 addr 0
+S _wtimer1_setconfig Def000000
+S C$wt1setcfg.c$4$0$0 Def000000
+S C$wt1setcfg.c$6$1$59 Def000000
+S C$wt1setcfg.c$7$1$59 Def00000B
+S C$wt1setcfg.c$8$1$59 Def00000D
+S C$wt1setcfg.c$9$1$59 Def000010
+S XG$wtimer1_setconfig$0$0 Def00001D
+S A$wt1setcfg$1211 Def00001D
+S A$wt1setcfg$1202 Def000016
+S A$wt1setcfg$1203 Def000018
+S A$wt1setcfg$1204 Def000019
+S A$wt1setcfg$1207 Def00001B
+S A$wt1setcfg$1180 Def000000
+S A$wt1setcfg$1181 Def000002
+S A$wt1setcfg$1182 Def000003
+S A$wt1setcfg$1183 Def000005
+S A$wt1setcfg$1193 Def00000D
+S A$wt1setcfg$1184 Def000007
+S A$wt1setcfg$1185 Def000009
+S A$wt1setcfg$1196 Def000010
+S A$wt1setcfg$1189 Def00000B
+S A$wt1setcfg$1199 Def000013
+S C$wt1setcfg.c$10$1$59 Def000013
+S C$wt1setcfg.c$11$1$59 Def000016
+S G$wtimer1_setconfig$0$0 Def000000
+S C$wt1setcfg.c$12$1$59 Def00001B
+S C$wt1setcfg.c$13$1$59 Def00001D
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 82 FF 65 F9 54 3F 60 02 80 02
+R 00 00 00 16
+T 00 00 0B
+R 00 00 00 16
+T 00 00 0B 80 10
+R 00 00 00 16
+T 00 00 0D
+R 00 00 00 16
+T 00 00 0D 53 07 3F 43 F9 04 75 F9 0F 74 FC 4F 52
+R 00 00 00 16
+T 00 00 1A F9 8F F9
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D 22
+R 00 00 00 16
+
+
+M:wt1setcfg
+F:G$wtimer1_setconfig$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1setcfg.wtimer1_setconfig$cfg$1$58({1}SC:U),R,0,0,[r7]
+T:Fwt1setcfg$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1setcfg$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1setcfg$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1setcfg$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wtstdby
+
+;!FILE libmflarge/wtstdby.asm
+XH3
+H 1D areas 2D5 global symbols
+M wtstdby
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A WTSTDBY0 size 0 flags 20 addr 0
+S _wtimer_standby Def000000
+S C$wtstdby.c$24$1$28 Def000000
+S C$wtstdby.c$10$0$0 Def000000
+S G$wtimer_standby$0$0 Def000000
+A WTSTDBY1 size 0 flags 20 addr 0
+A WTSTDBY2 size A flags 20 addr 0
+S XG$wtimer_standby$0$0 Def000009
+S A$wtstdby$1190 Def000009
+S A$wtstdby$1183 Def000000
+S A$wtstdby$1184 Def000002
+S A$wtstdby$1185 Def000004
+S A$wtstdby$1186 Def000006
+S A$wtstdby$1187 Def000008
+S C$wtstdby.c$25$1$28 Def000009
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 17
+T 00 00 00 74 0C 55 87 44 01 F5 87 22 22
+R 00 00 00 19
+
+
+M:wtstdby
+F:G$wtimer_standby$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+wt0adda
+
+;!FILE libmflarge/wt0adda.asm
+XH3
+H 1A areas 2ED global symbols
+M wt0adda
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer0_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S _wtimer0_addcore Ref000000
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _wtimer0_schedq Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S A$wt0adda$1197 Def000011
+S A$wt0adda$1188 Def000008
+S A$wt0adda$1198 Def000014
+S A$wt0adda$1199 Def000016
+S G$wtimer0_addabsolute$0$0 Def000000
+S C$wt0adda.c$10$1$59 Def000023
+S C$wt0adda.c$11$1$59 Def000028
+S C$wt0adda.c$12$1$59 Def00002B
+S _wtimer0_addabsolute Def000000
+S XG$wtimer0_addabsolute$0$0 Def00002B
+S C$wt0adda.c$4$0$0 Def000000
+S C$wt0adda.c$6$1$59 Def000004
+S C$wt0adda.c$7$1$59 Def000009
+S C$wt0adda.c$8$1$59 Def00000B
+S C$wt0adda.c$9$1$59 Def00001A
+S A$wt0adda$1200 Def000018
+S A$wt0adda$1210 Def000026
+S A$wt0adda$1203 Def00001A
+S A$wt0adda$1213 Def000028
+S A$wt0adda$1204 Def00001C
+S A$wt0adda$1214 Def000029
+S A$wt0adda$1205 Def00001E
+S A$wt0adda$1206 Def000020
+S A$wt0adda$1217 Def00002B
+S A$wt0adda$1209 Def000023
+S A$wt0adda$1191 Def000009
+S A$wt0adda$1182 Def000000
+S A$wt0adda$1183 Def000002
+S A$wt0adda$1194 Def00000B
+S A$wt0adda$1195 Def00000D
+S A$wt0adda$1186 Def000004
+S A$wt0adda$1196 Def00000F
+S A$wt0adda$1187 Def000006
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF C0 07
+R 00 00 00 16
+T 00 00 0D C0 06 C0 05 12 00 00 D0 05 D0 06 D0 07
+R 00 00 00 16 02 08 00 6B
+T 00 00 1A 8E 82 8F 83 C0 05 12 00 00 12 00 00 D0
+R 00 00 00 16 02 0A 00 FF 02 0D 02 C2
+T 00 00 27 05 ED 42 A8 22
+R 00 00 00 16
+
+
+M:wt0adda
+F:G$wtimer0_addabsolute$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0adda.wtimer0_addabsolute$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt0adda.wtimer0_addabsolute$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt0adda$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0adda$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0adda$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0adda$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1adda
+
+;!FILE libmflarge/wt1adda.asm
+XH3
+H 1A areas 2ED global symbols
+M wt1adda
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S _wtimer1_update Ref000000
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S _wtimer1_addcore Ref000000
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+S _wtimer1_schedq Ref000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S A$wt1adda$1196 Def00000F
+S A$wt1adda$1187 Def000006
+S A$wt1adda$1197 Def000011
+S A$wt1adda$1188 Def000008
+S A$wt1adda$1198 Def000014
+S A$wt1adda$1199 Def000016
+S G$wtimer1_addabsolute$0$0 Def000000
+S C$wt1adda.c$10$1$59 Def000023
+S C$wt1adda.c$11$1$59 Def000028
+S C$wt1adda.c$12$1$59 Def00002B
+S _wtimer1_addabsolute Def000000
+S XG$wtimer1_addabsolute$0$0 Def00002B
+S C$wt1adda.c$4$0$0 Def000000
+S C$wt1adda.c$6$1$59 Def000004
+S C$wt1adda.c$7$1$59 Def000009
+S C$wt1adda.c$8$1$59 Def00000B
+S C$wt1adda.c$9$1$59 Def00001A
+S A$wt1adda$1200 Def000018
+S A$wt1adda$1210 Def000026
+S A$wt1adda$1203 Def00001A
+S A$wt1adda$1213 Def000028
+S A$wt1adda$1204 Def00001C
+S A$wt1adda$1214 Def000029
+S A$wt1adda$1205 Def00001E
+S A$wt1adda$1206 Def000020
+S A$wt1adda$1217 Def00002B
+S A$wt1adda$1209 Def000023
+S A$wt1adda$1191 Def000009
+S A$wt1adda$1182 Def000000
+S A$wt1adda$1183 Def000002
+S A$wt1adda$1194 Def00000B
+S A$wt1adda$1195 Def00000D
+S A$wt1adda$1186 Def000004
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AE 82 AF 83 74 80 55 A8 FD C2 AF C0 07
+R 00 00 00 16
+T 00 00 0D C0 06 C0 05 12 00 00 D0 05 D0 06 D0 07
+R 00 00 00 16 02 08 00 77
+T 00 00 1A 8E 82 8F 83 C0 05 12 00 00 12 00 00 D0
+R 00 00 00 16 02 0A 01 0F 02 0D 02 CB
+T 00 00 27 05 ED 42 A8 22
+R 00 00 00 16
+
+
+M:wt1adda
+F:G$wtimer1_addabsolute$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1adda.wtimer1_addabsolute$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt1adda.wtimer1_addabsolute$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt1adda$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1adda$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1adda$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1adda$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0addr
+
+;!FILE libmflarge/wt0addr.asm
+XH3
+H 1A areas 304 global symbols
+M wt0addr
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S _wtimer0_update Ref000000
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S _wtimer0_addcore Ref000000
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S _wtimer0_schedq Ref000000
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 47 flags 20 addr 0
+S A$wt0addr$1200 Def000028
+S A$wt0addr$1210 Def000032
+S A$wt0addr$1201 Def000029
+S A$wt0addr$1220 Def000042
+S A$wt0addr$1211 Def000033
+S A$wt0addr$1202 Def00002A
+S A$wt0addr$1221 Def000044
+S A$wt0addr$1212 Def000034
+S A$wt0addr$1203 Def00002B
+S A$wt0addr$1222 Def000046
+S A$wt0addr$1213 Def000035
+S A$wt0addr$1204 Def00002C
+S A$wt0addr$1214 Def000036
+S A$wt0addr$1205 Def00002D
+S A$wt0addr$1215 Def000037
+S A$wt0addr$1206 Def00002E
+S A$wt0addr$1216 Def000038
+S A$wt0addr$1207 Def00002F
+S A$wt0addr$1217 Def00003A
+S A$wt0addr$1208 Def000030
+S A$wt0addr$1190 Def00001A
+S A$wt0addr$1181 Def00000F
+S A$wt0addr$1218 Def00003C
+S A$wt0addr$1209 Def000031
+S A$wt0addr$1191 Def00001B
+S A$wt0addr$1182 Def000012
+S A$wt0addr$1173 Def000000
+S _wtimer0_addrelative Def000000
+S A$wt0addr$1219 Def00003F
+S A$wt0addr$1192 Def00001C
+S A$wt0addr$1183 Def000013
+S A$wt0addr$1174 Def000002
+S A$wt0addr$1193 Def00001D
+S A$wt0addr$1184 Def000014
+S A$wt0addr$1175 Def000004
+S A$wt0addr$1194 Def00001F
+S A$wt0addr$1185 Def000015
+S A$wt0addr$1176 Def000006
+S A$wt0addr$1195 Def000021
+S A$wt0addr$1186 Def000016
+S A$wt0addr$1177 Def000008
+S A$wt0addr$1196 Def000023
+S A$wt0addr$1187 Def000017
+S A$wt0addr$1178 Def00000A
+S A$wt0addr$1197 Def000025
+S A$wt0addr$1188 Def000018
+S A$wt0addr$1179 Def00000C
+S A$wt0addr$1198 Def000026
+S A$wt0addr$1189 Def000019
+S A$wt0addr$1199 Def000027
+S XG$wtimer0_addrelative$0$0 Def000047
+S C$wt0addr.c$60$1$59 Def000047
+S C$wt0addr.c$59$1$59 Def000000
+S C$wt0addr.c$6$0$0 Def000000
+S G$wtimer0_addrelative$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 A8 54 80 C0 E0 C2 AF C0 82 C0 83 12
+R 00 00 00 16
+T 00 00 0D 00 00 90 00 00 E0 FA A3 E0 FB A3 E0 FC
+R 00 00 00 16 02 03 00 5B 02 06 02 42
+T 00 00 1A A3 E0 FD D0 83 D0 82 AE 82 AF 83 A3 A3
+R 00 00 00 16
+T 00 00 27 A3 A3 E0 2A F0 A3 E0 3B F0 A3 E0 3C F0
+R 00 00 00 16
+T 00 00 34 A3 E0 3D F0 8E 82 8F 83 12 00 00 12
+R 00 00 00 16 02 0C 00 F4
+T 00 00 40 00 00 D0 E0 42 A8 22
+R 00 00 00 16 02 03 02 B7
+
+
+M:wt0addr
+F:G$wtimer0_addrelative$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt0addr.wtimer0_addrelative$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwt0addr$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0addr$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0addr$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0addr$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1addr
+
+;!FILE libmflarge/wt1addr.asm
+XH3
+H 1A areas 304 global symbols
+M wt1addr
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer1_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S _wtimer1_addcore Ref000000
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S _wtimer1_schedq Ref000000
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 47 flags 20 addr 0
+S G$wtimer1_addrelative$0$0 Def000000
+S A$wt1addr$1200 Def000028
+S A$wt1addr$1210 Def000032
+S A$wt1addr$1201 Def000029
+S A$wt1addr$1220 Def000042
+S A$wt1addr$1211 Def000033
+S A$wt1addr$1202 Def00002A
+S A$wt1addr$1221 Def000044
+S A$wt1addr$1212 Def000034
+S A$wt1addr$1203 Def00002B
+S A$wt1addr$1222 Def000046
+S A$wt1addr$1213 Def000035
+S A$wt1addr$1204 Def00002C
+S A$wt1addr$1214 Def000036
+S A$wt1addr$1205 Def00002D
+S A$wt1addr$1215 Def000037
+S A$wt1addr$1206 Def00002E
+S A$wt1addr$1216 Def000038
+S A$wt1addr$1207 Def00002F
+S A$wt1addr$1217 Def00003A
+S A$wt1addr$1208 Def000030
+S A$wt1addr$1190 Def00001A
+S A$wt1addr$1181 Def00000F
+S A$wt1addr$1218 Def00003C
+S A$wt1addr$1209 Def000031
+S A$wt1addr$1191 Def00001B
+S A$wt1addr$1182 Def000012
+S A$wt1addr$1173 Def000000
+S _wtimer1_addrelative Def000000
+S A$wt1addr$1219 Def00003F
+S A$wt1addr$1192 Def00001C
+S A$wt1addr$1183 Def000013
+S A$wt1addr$1174 Def000002
+S A$wt1addr$1193 Def00001D
+S A$wt1addr$1184 Def000014
+S A$wt1addr$1175 Def000004
+S A$wt1addr$1194 Def00001F
+S A$wt1addr$1185 Def000015
+S A$wt1addr$1176 Def000006
+S A$wt1addr$1195 Def000021
+S A$wt1addr$1186 Def000016
+S A$wt1addr$1177 Def000008
+S A$wt1addr$1196 Def000023
+S A$wt1addr$1187 Def000017
+S A$wt1addr$1178 Def00000A
+S A$wt1addr$1197 Def000025
+S A$wt1addr$1188 Def000018
+S A$wt1addr$1179 Def00000C
+S A$wt1addr$1198 Def000026
+S A$wt1addr$1189 Def000019
+S A$wt1addr$1199 Def000027
+S XG$wtimer1_addrelative$0$0 Def000047
+S C$wt1addr.c$60$1$59 Def000047
+S C$wt1addr.c$59$1$59 Def000000
+S C$wt1addr.c$6$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 A8 54 80 C0 E0 C2 AF C0 82 C0 83 12
+R 00 00 00 16
+T 00 00 0D 00 00 90 00 08 E0 FA A3 E0 FB A3 E0 FC
+R 00 00 00 16 02 03 00 6B 02 06 02 42
+T 00 00 1A A3 E0 FD D0 83 D0 82 AE 82 AF 83 A3 A3
+R 00 00 00 16
+T 00 00 27 A3 A3 E0 2A F0 A3 E0 3B F0 A3 E0 3C F0
+R 00 00 00 16
+T 00 00 34 A3 E0 3D F0 8E 82 8F 83 12 00 00 12
+R 00 00 00 16 02 0C 00 FF
+T 00 00 40 00 00 D0 E0 42 A8 22
+R 00 00 00 16 02 03 02 C3
+
+
+M:wt1addr
+F:G$wtimer1_addrelative$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lwt1addr.wtimer1_addrelative$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[]
+T:Fwt1addr$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1addr$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1addr$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1addr$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0curt
+
+;!FILE libmflarge/wt0curt.asm
+XH3
+H 1A areas 2F0 global symbols
+M wt0curt
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S _wtimer0_update Ref000000
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$wt0curt.c$13$1$59 Def000026
+S XG$wtimer0_curtime$0$0 Def000026
+S C$wt0curt.c$4$0$0 Def000000
+S C$wt0curt.c$7$1$59 Def000000
+S C$wt0curt.c$8$1$59 Def000005
+S C$wt0curt.c$9$1$59 Def000007
+S A$wt0curt$1200 Def000015
+S A$wt0curt$1210 Def00001D
+S A$wt0curt$1201 Def000016
+S A$wt0curt$1202 Def000017
+S A$wt0curt$1203 Def000018
+S A$wt0curt$1213 Def00001F
+S A$wt0curt$1204 Def000019
+S A$wt0curt$1214 Def000021
+S A$wt0curt$1205 Def00001A
+S A$wt0curt$1215 Def000023
+S A$wt0curt$1206 Def00001B
+S A$wt0curt$1216 Def000025
+S A$wt0curt$1190 Def000007
+S A$wt0curt$1209 Def00001C
+S A$wt0curt$1191 Def000009
+S A$wt0curt$1182 Def000000
+S A$wt0curt$1219 Def000026
+S A$wt0curt$1192 Def00000C
+S A$wt0curt$1183 Def000002
+S A$wt0curt$1184 Def000004
+S A$wt0curt$1195 Def00000E
+S A$wt0curt$1196 Def000011
+S A$wt0curt$1187 Def000005
+S G$wtimer0_curtime$0$0 Def000000
+S A$wt0curt$1197 Def000012
+S A$wt0curt$1198 Def000013
+S A$wt0curt$1199 Def000014
+S C$wt0curt.c$10$1$59 Def00000E
+S C$wt0curt.c$11$1$59 Def00001C
+S C$wt0curt.c$12$1$59 Def00001F
+S _wtimer0_curtime Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF C0 07 12 00 00 D0
+R 00 00 00 16 02 0D 00 6B
+T 00 00 0D 07 90 00 00 E0 FB A3 E0 FC A3 E0 FD A3
+R 00 00 00 16 02 05 02 41
+T 00 00 1A E0 FE EF 42 A8 8B 82 8C 83 8D F0 EE 22
+R 00 00 00 16
+
+
+M:wt0curt
+F:G$wtimer0_curtime$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lwt0curt.wtimer0_curtime$r$1$59({4}SL:U),R,0,0,[r3,r4,r5,r6]
+S:Lwt0curt.wtimer0_curtime$iesave$1$59({1}SC:U),R,0,0,[r7]
+T:Fwt0curt$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt0curt$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt0curt$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt0curt$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1curt
+
+;!FILE libmflarge/wt1curt.asm
+XH3
+H 1A areas 2F0 global symbols
+M wt1curt
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S _wtimer1_update Ref000000
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
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+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S _wtimer_state Ref000000
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
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+S C$wt1curt.c$12$1$59 Def00001F
+S _wtimer1_curtime Def000000
+S C$wt1curt.c$13$1$59 Def000026
+S XG$wtimer1_curtime$0$0 Def000026
+S C$wt1curt.c$4$0$0 Def000000
+S C$wt1curt.c$7$1$59 Def000000
+S C$wt1curt.c$8$1$59 Def000005
+S C$wt1curt.c$9$1$59 Def000007
+S A$wt1curt$1200 Def000015
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+S A$wt1curt$1203 Def000018
+S A$wt1curt$1213 Def00001F
+S A$wt1curt$1204 Def000019
+S A$wt1curt$1214 Def000021
+S A$wt1curt$1205 Def00001A
+S A$wt1curt$1215 Def000023
+S A$wt1curt$1206 Def00001B
+S A$wt1curt$1216 Def000025
+S A$wt1curt$1190 Def000007
+S A$wt1curt$1209 Def00001C
+S A$wt1curt$1191 Def000009
+S A$wt1curt$1182 Def000000
+S A$wt1curt$1219 Def000026
+S A$wt1curt$1192 Def00000C
+S A$wt1curt$1183 Def000002
+S A$wt1curt$1184 Def000004
+S A$wt1curt$1195 Def00000E
+S A$wt1curt$1196 Def000011
+S A$wt1curt$1187 Def000005
+S G$wtimer1_curtime$0$0 Def000000
+S A$wt1curt$1197 Def000012
+S A$wt1curt$1198 Def000013
+S A$wt1curt$1199 Def000014
+S C$wt1curt.c$10$1$59 Def00000E
+S C$wt1curt.c$11$1$59 Def00001C
+A CONST size 0 flags 20 addr 0
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+T 00 00 0D 07 90 00 08 E0 FB A3 E0 FC A3 E0 FD A3
+R 00 00 00 16 02 05 02 41
+T 00 00 1A E0 FE EF 42 A8 8B 82 8C 83 8D F0 EE 22
+R 00 00 00 16
+
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
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+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt0rem
+
+;!FILE libmflarge/wt0rem.asm
+XH3
+H 1A areas 2F7 global symbols
+M wt0rem
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _wtimer0_removecb_core Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
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+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
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+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
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+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
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+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
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+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+A RSEG size 0 flags 8 addr 0
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+A GSINIT2 size 0 flags 20 addr 0
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
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+S C$wt0rem.c$12$1$59 Def000038
+S C$wt0rem.c$13$1$59 Def00003B
+S C$wt0rem.c$14$1$59 Def00003D
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+S C$wt0rem.c$8$1$59 Def000004
+S C$wt0rem.c$9$1$59 Def000009
+S XG$wtimer0_remove$0$0 Def00003D
+S A$wt0rem$1200 Def000015
+S A$wt0rem$1210 Def000026
+S A$wt0rem$1201 Def000017
+S A$wt0rem$1211 Def000028
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+S A$wt0rem$1222 Def000038
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+S A$wt0rem$1205 Def000020
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+S A$wt0rem$1216 Def000033
+S A$wt0rem$1226 Def00003B
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+S A$wt0rem$1218 Def000036
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+S A$wt0rem$1198 Def000011
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+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt1rem
+
+;!FILE libmflarge/wt1rem.asm
+XH3
+H 1A areas 2F7 global symbols
+M wt1rem
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _wtimer1_removecb_core Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
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+S G$ADCCH3VAL$0$0 Def007026
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+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+A XSEG size 0 flags 40 addr 0
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+A XISEG size 0 flags 40 addr 0
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+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3E flags 20 addr 0
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+S C$wt1rem.c$11$1$59 Def000024
+S C$wt1rem.c$12$1$59 Def000038
+S C$wt1rem.c$13$1$59 Def00003B
+S C$wt1rem.c$14$1$59 Def00003D
+S G$wtimer1_remove$0$0 Def000000
+S _wtimer1_remove Def000000
+S C$wt1rem.c$4$0$0 Def000000
+S C$wt1rem.c$8$1$59 Def000004
+S C$wt1rem.c$9$1$59 Def000009
+S XG$wtimer1_remove$0$0 Def00003D
+S A$wt1rem$1200 Def000015
+S A$wt1rem$1210 Def000026
+S A$wt1rem$1201 Def000017
+S A$wt1rem$1211 Def000028
+S A$wt1rem$1202 Def000019
+S A$wt1rem$1212 Def00002A
+S A$wt1rem$1203 Def00001C
+S A$wt1rem$1222 Def000038
+S A$wt1rem$1213 Def00002C
+S A$wt1rem$1204 Def00001E
+S A$wt1rem$1223 Def000039
+S A$wt1rem$1214 Def00002F
+S A$wt1rem$1205 Def000020
+S A$wt1rem$1215 Def000031
+S A$wt1rem$1206 Def000022
+S A$wt1rem$1216 Def000033
+S A$wt1rem$1226 Def00003B
+S A$wt1rem$1217 Def000035
+S A$wt1rem$1218 Def000036
+S A$wt1rem$1209 Def000024
+S A$wt1rem$1219 Def000037
+S A$wt1rem$1192 Def000009
+S A$wt1rem$1183 Def000000
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+S A$wt1rem$1184 Def000002
+S A$wt1rem$1195 Def00000B
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+S A$wt1rem$1188 Def000006
+S A$wt1rem$1198 Def000011
+S A$wt1rem$1189 Def000008
+S A$wt1rem$1199 Def000013
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+A XINIT size 0 flags 20 addr 0
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+R 00 00 00 16 02 09 01 61
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+R 00 00 00 16
+
+
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+S:Lwt1rem.wtimer1_remove$desc$1$58({2}DX,STwtimer_desc:S),R,0,0,[r6,r7]
+S:Lwt1rem.wtimer1_remove$d$1$59({2}DX,STwtimer_desc:S),B,1,3
+S:Lwt1rem.wtimer1_remove$ret$1$59({1}SC:U),R,0,0,[r4]
+S:Lwt1rem.wtimer1_remove$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt1rem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt1rem$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt1rem$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt1rem$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
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+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
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+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
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+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
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+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+wt01rem
+
+;!FILE libmflarge/wt01rem.asm
+XH3
+H 1A areas 308 global symbols
+M wt01rem
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S _wtimer0_removecb_core Ref000000
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S _wtimer1_removecb_core Ref000000
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S _wtimer_removecb_core Ref000000
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
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+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+A XSEG size 0 flags 40 addr 0
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+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
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+S C$wt01rem.c$8$1$59 Def000004
+S C$wt01rem.c$9$1$59 Def000009
+S G$wtimer_remove$0$0 Def000000
+S A$wt01rem$1200 Def000013
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+S A$wt01rem$1211 Def000026
+S A$wt01rem$1202 Def000017
+S A$wt01rem$1230 Def000046
+S A$wt01rem$1221 Def00003B
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+S A$wt01rem$1203 Def000019
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+S A$wt01rem$1231 Def000048
+S A$wt01rem$1222 Def00003D
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+S A$wt01rem$1204 Def00001C
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+S A$wt01rem$1232 Def00004B
+S A$wt01rem$1223 Def00003E
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+S A$wt01rem$1233 Def00004D
+S A$wt01rem$1224 Def00003F
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+S A$wt01rem$1206 Def000020
+S A$wt01rem$1234 Def00004F
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+S A$wt01rem$1207 Def000022
+S A$wt01rem$1244 Def000057
+S A$wt01rem$1235 Def000051
+S A$wt01rem$1217 Def000033
+S A$wt01rem$1190 Def000008
+S _wtimer_remove Def000000
+S A$wt01rem$1236 Def000052
+S A$wt01rem$1227 Def000040
+S A$wt01rem$1218 Def000035
+S A$wt01rem$1237 Def000053
+S A$wt01rem$1228 Def000042
+S A$wt01rem$1219 Def000037
+S A$wt01rem$1247 Def000059
+S A$wt01rem$1229 Def000044
+S A$wt01rem$1193 Def000009
+S A$wt01rem$1184 Def000000
+S A$wt01rem$1185 Def000002
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+S A$wt01rem$1197 Def00000D
+S A$wt01rem$1188 Def000004
+S A$wt01rem$1198 Def00000F
+S A$wt01rem$1189 Def000006
+S A$wt01rem$1199 Def000011
+S XG$wtimer_remove$0$0 Def000059
+S C$wt01rem.c$10$1$59 Def00000B
+S C$wt01rem.c$11$1$59 Def000024
+S C$wt01rem.c$12$1$59 Def000040
+S C$wt01rem.c$13$1$59 Def000054
+S C$wt01rem.c$14$1$59 Def000057
+S C$wt01rem.c$15$1$59 Def000059
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+R 00 00 00 16 02 0B 01 62
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+R 00 00 00 16
+
+
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+S:Lwt01rem.wtimer_remove$d$1$59({2}DX,STwtimer_desc:S),B,1,3
+S:Lwt01rem.wtimer_remove$ret$1$59({1}SC:U),R,0,0,[r4]
+S:Lwt01rem.wtimer_remove$iesave$1$59({1}SC:U),R,0,0,[r5]
+T:Fwt01rem$wtimer_state[({0}S:S$time$0$0({6}STwtimer_state_time:S),Z,0,0)({6}S:S$queue$0$0({2}DX,STwtimer_desc:S),Z,0,0)]
+T:Fwt01rem$wtimer_callback[({0}S:S$next$0$0({2}DX,STwtimer_callback:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)]
+T:Fwt01rem$wtimer_state_time[({0}S:S$cur$0$0({4}SL:U),Z,0,0)({4}S:S$ref$0$0({2}SI:U),Z,0,0)]
+T:Fwt01rem$wtimer_desc[({0}S:S$next$0$0({2}DX,STwtimer_desc:S),Z,0,0)({2}S:S$handler$0$0({2}DC,DF,SV:S),Z,0,0)({4}S:S$time$0$0({4}SL:U),Z,0,0)]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
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+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
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+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
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+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
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+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$wtimer_state$0$0({16}DA2d,STwtimer_state:S),F,0,0
+S:G$wtimer_pending$0$0({2}DX,STwtimer_callback:S),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_setconfig$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_init_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_idle$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_runcallbacks$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer1_curtime$0$0({2}DF,SL:U),C,0,0
+S:G$wtimer0_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addabsolute$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addrelative$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_remove$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_add_callback$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_remove_callback$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_cansleep$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer_irq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_addcb_core$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer0_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer0_removecb_core$0$0({2}DF,SC:U),C,0,0
+S:G$wtimer1_schedq$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_update$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_addcore$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer1_removecb_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+radiord16
+
+;!FILE libmflarge/radiord16.asm
+XH3
+H 1A areas 2E1 global symbols
+M radiord16
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 23 flags 20 addr 0
+S G$radio_read16$0$0 Def000000
+S C$radiord16.c$7$0$0 Def000000
+S _radio_read16 Def000000
+S XG$radio_read16$0$0 Def000023
+S A$radiord16$1180 Def00000B
+S A$radiord16$1190 Def000020
+S A$radiord16$1181 Def00000D
+S A$radiord16$1191 Def000022
+S A$radiord16$1182 Def00000F
+S A$radiord16$1183 Def000011
+S A$radiord16$1174 Def000000
+S A$radiord16$1184 Def000013
+S A$radiord16$1175 Def000002
+S A$radiord16$1185 Def000015
+S A$radiord16$1176 Def000004
+S A$radiord16$1186 Def000017
+S A$radiord16$1177 Def000006
+S A$radiord16$1187 Def000018
+S A$radiord16$1178 Def000008
+S A$radiord16$1188 Def00001B
+S A$radiord16$1179 Def00000A
+S A$radiord16$1189 Def00001D
+S C$radiord16.c$30$1$64 Def000023
+S C$radiord16.c$29$1$64 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 01 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 F5 83 85 B5 82 92 AF 22
+R 00 00 00 16
+
+
+M:radiord16
+F:G$radio_read16$0$0({2}DF,SI:U),Z,0,0,0,0,0
+S:Lradiord16.radio_read16$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
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+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiord24
+
+;!FILE libmflarge/radiord24.asm
+XH3
+H 1A areas 2E3 global symbols
+M radiord24
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S G$radio_read24$0$0 Def000000
+S C$radiord24.c$7$0$0 Def000000
+S _radio_read24 Def000000
+S XG$radio_read24$0$0 Def000027
+S A$radiord24$1180 Def00000B
+S A$radiord24$1190 Def000020
+S A$radiord24$1181 Def00000D
+S A$radiord24$1191 Def000023
+S A$radiord24$1182 Def00000F
+S A$radiord24$1192 Def000025
+S A$radiord24$1183 Def000011
+S A$radiord24$1174 Def000000
+S A$radiord24$1193 Def000026
+S A$radiord24$1184 Def000013
+S A$radiord24$1175 Def000002
+S A$radiord24$1185 Def000015
+S A$radiord24$1176 Def000004
+S A$radiord24$1186 Def000017
+S A$radiord24$1177 Def000006
+S A$radiord24$1187 Def000018
+S A$radiord24$1178 Def000008
+S A$radiord24$1188 Def00001B
+S A$radiord24$1179 Def00000A
+S A$radiord24$1189 Def00001D
+S C$radiord24.c$31$1$64 Def000000
+S C$radiord24.c$32$1$64 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 02 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 F5 F0 85 B5 83 85 B6 82 92 AF E4 22
+R 00 00 00 16
+
+
+M:radiord24
+F:G$radio_read24$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lradiord24.radio_read24$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
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+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiord32
+
+;!FILE libmflarge/radiord32.asm
+XH3
+H 1A areas 2E2 global symbols
+M radiord32
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S G$radio_read32$0$0 Def000000
+S C$radiord32.c$7$0$0 Def000000
+S _radio_read32 Def000000
+S XG$radio_read32$0$0 Def000027
+S A$radiord32$1180 Def00000B
+S A$radiord32$1190 Def000021
+S A$radiord32$1181 Def00000D
+S A$radiord32$1191 Def000024
+S A$radiord32$1182 Def00000F
+S A$radiord32$1192 Def000026
+S A$radiord32$1183 Def000011
+S A$radiord32$1174 Def000000
+S A$radiord32$1184 Def000013
+S A$radiord32$1175 Def000002
+S A$radiord32$1185 Def000015
+S A$radiord32$1176 Def000004
+S A$radiord32$1186 Def000017
+S A$radiord32$1177 Def000006
+S A$radiord32$1187 Def000018
+S A$radiord32$1178 Def000008
+S A$radiord32$1188 Def00001B
+S A$radiord32$1179 Def00000A
+S A$radiord32$1189 Def00001E
+S C$radiord32.c$30$1$64 Def000000
+S C$radiord32.c$31$1$64 Def000027
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 A8 33 C2 AF
+R 00 00 00 16
+T 00 00 0D E5 B1 F5 F0 54 FC 44 03 F5 B1 E0 85 F0
+R 00 00 00 16
+T 00 00 1A B1 85 B5 F0 85 B6 83 85 B7 82 92 AF 22
+R 00 00 00 16
+
+
+M:radiord32
+F:G$radio_read32$0$0({2}DF,SL:U),Z,0,0,0,0,0
+S:Lradiord32.radio_read32$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr16
+
+;!FILE libmflarge/radiowr16.asm
+XH3
+H 1A areas 2E7 global symbols
+M radiowr16
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2B flags 20 addr 0
+S C$radiowr16.c$45$1$64 Def000000
+S C$radiowr16.c$46$1$64 Def00002B
+S G$radio_write16$0$0 Def000000
+S C$radiowr16.c$7$0$0 Def000000
+S _radio_write16 Def000000
+S A$radiowr16$1200 Def000020
+S XG$radio_write16$0$0 Def00002B
+S A$radiowr16$1201 Def000021
+S A$radiowr16$1202 Def000022
+S A$radiowr16$1203 Def000023
+S A$radiowr16$1204 Def000026
+S A$radiowr16$1205 Def000028
+S A$radiowr16$1206 Def00002A
+S A$radiowr16$1190 Def00000E
+S A$radiowr16$1191 Def00000F
+S A$radiowr16$1192 Def000011
+S A$radiowr16$1183 Def000000
+S A$radiowr16$1193 Def000012
+S A$radiowr16$1184 Def000002
+S A$radiowr16$1194 Def000014
+S A$radiowr16$1185 Def000004
+S A$radiowr16$1195 Def000016
+S A$radiowr16$1186 Def000006
+S A$radiowr16$1196 Def000018
+S A$radiowr16$1187 Def000008
+S A$radiowr16$1197 Def00001A
+S A$radiowr16$1188 Def00000A
+S A$radiowr16$1198 Def00001C
+S A$radiowr16$1189 Def00000C
+S A$radiowr16$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FD C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B5 08 E6 F0 85 F0 B1 92
+R 00 00 00 16
+T 00 00 27 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr16
+F:G$radio_write16$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lradiowr16.radio_write16$d$1$63({2}SI:U),B,1,-4
+S:Lradiowr16.radio_write16$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr24
+
+;!FILE libmflarge/radiowr24.asm
+XH3
+H 1A areas 2E9 global symbols
+M radiowr24
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2E flags 20 addr 0
+S C$radiowr24.c$47$1$64 Def000000
+S C$radiowr24.c$48$1$64 Def00002E
+S G$radio_write24$0$0 Def000000
+S C$radiowr24.c$7$0$0 Def000000
+S _radio_write24 Def000000
+S A$radiowr24$1200 Def000020
+S XG$radio_write24$0$0 Def00002E
+S A$radiowr24$1201 Def000021
+S A$radiowr24$1202 Def000023
+S A$radiowr24$1203 Def000024
+S A$radiowr24$1204 Def000025
+S A$radiowr24$1205 Def000026
+S A$radiowr24$1206 Def000029
+S A$radiowr24$1207 Def00002B
+S A$radiowr24$1208 Def00002D
+S A$radiowr24$1190 Def00000E
+S A$radiowr24$1191 Def00000F
+S A$radiowr24$1192 Def000011
+S A$radiowr24$1183 Def000000
+S A$radiowr24$1193 Def000012
+S A$radiowr24$1184 Def000002
+S A$radiowr24$1194 Def000014
+S A$radiowr24$1185 Def000004
+S A$radiowr24$1195 Def000016
+S A$radiowr24$1186 Def000006
+S A$radiowr24$1196 Def000018
+S A$radiowr24$1187 Def000008
+S A$radiowr24$1197 Def00001A
+S A$radiowr24$1188 Def00000A
+S A$radiowr24$1198 Def00001C
+S A$radiowr24$1189 Def00000C
+S A$radiowr24$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FB C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B6 08 86 B5 08 E6 F0 85
+R 00 00 00 16
+T 00 00 27 F0 B1 92 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr24
+F:G$radio_write24$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lradiowr24.radio_write24$d$1$63({4}SL:U),B,1,-6
+S:Lradiowr24.radio_write24$addr$1$63({2}SI:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiowr32
+
+;!FILE libmflarge/radiowr32.asm
+XH3
+H 1A areas 2EB global symbols
+M radiowr32
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _EIP_6 Def0000B6
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _EIP_7 Def0000B7
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _PINC_7 Def0000FF
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _WTCNTA0 Def0000F2
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _WTCNTB1 Def0000FB
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AC Def0000D6
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _E2IE Def0000A0
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 31 flags 20 addr 0
+S C$radiowr32.c$50$1$64 Def000031
+S C$radiowr32.c$49$1$64 Def000000
+S G$radio_write32$0$0 Def000000
+S C$radiowr32.c$7$0$0 Def000000
+S _radio_write32 Def000000
+S A$radiowr32$1200 Def000020
+S XG$radio_write32$0$0 Def000031
+S A$radiowr32$1210 Def000030
+S A$radiowr32$1201 Def000021
+S A$radiowr32$1202 Def000023
+S A$radiowr32$1203 Def000024
+S A$radiowr32$1204 Def000026
+S A$radiowr32$1205 Def000027
+S A$radiowr32$1206 Def000028
+S A$radiowr32$1207 Def000029
+S A$radiowr32$1208 Def00002C
+S A$radiowr32$1190 Def00000E
+S A$radiowr32$1209 Def00002E
+S A$radiowr32$1191 Def00000F
+S A$radiowr32$1192 Def000011
+S A$radiowr32$1183 Def000000
+S A$radiowr32$1193 Def000012
+S A$radiowr32$1184 Def000002
+S A$radiowr32$1194 Def000014
+S A$radiowr32$1185 Def000004
+S A$radiowr32$1195 Def000016
+S A$radiowr32$1186 Def000006
+S A$radiowr32$1196 Def000018
+S A$radiowr32$1187 Def000008
+S A$radiowr32$1197 Def00001A
+S A$radiowr32$1188 Def00000A
+S A$radiowr32$1198 Def00001C
+S A$radiowr32$1189 Def00000C
+S A$radiowr32$1199 Def00001E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 83 54 0F 44 40 F5 83 E5 81 24 FB C0
+R 00 00 00 16
+T 00 00 0D 00 F8 E5 A8 33 C2 AF E5 B1 F5 F0 54 FC
+R 00 00 00 16
+T 00 00 1A 44 01 F5 B1 86 B7 08 86 B6 08 86 B5 08
+R 00 00 00 16
+T 00 00 27 E6 F0 85 F0 B1 92 AF D0 00 22
+R 00 00 00 16
+
+
+M:radiowr32
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+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
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+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
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+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
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+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
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+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
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+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
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+S:G$B_2$0$0({1}SX:U),J,0,0
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+S:G$E2IE_1$0$0({1}SX:U),J,0,0
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+S:G$E2IE_7$0$0({1}SX:U),J,0,0
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+S:G$E2IP_4$0$0({1}SX:U),J,0,0
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+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+radiodswakecore
+
+;!FILE libmflarge/radiodswakecore.asm
+XH3
+H 1A areas 86D global symbols
+M radiodswakecore
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 32 flags 20 addr 0
+S XG$radio_wakeup_deepsleep_core$0$0 Def000031
+S A$radiodswakecore$3301 Def000015
+S A$radiodswakecore$3311 Def00001C
+S A$radiodswakecore$3330 Def000029
+S A$radiodswakecore$3321 Def000024
+S A$radiodswakecore$3312 Def00001D
+S A$radiodswakecore$3331 Def00002C
+S A$radiodswakecore$3313 Def00001E
+S A$radiodswakecore$3304 Def000017
+S A$radiodswakecore$3332 Def00002E
+S A$radiodswakecore$3314 Def00001F
+S A$radiodswakecore$3315 Def000020
+S A$radiodswakecore$3335 Def00002F
+S A$radiodswakecore$3308 Def000019
+S A$radiodswakecore$3281 Def000002
+S A$radiodswakecore$3327 Def000026
+S A$radiodswakecore$3318 Def000022
+S A$radiodswakecore$3291 Def00000A
+S C$radiodswakecore.c$10$1$30 Def000005
+S A$radiodswakecore$3338 Def000031
+S A$radiodswakecore$3284 Def000005
+S A$radiodswakecore$3294 Def00000D
+S C$radiodswakecore.c$21$1$30 Def000022
+S C$radiodswakecore.c$22$1$30 Def000024
+S C$radiodswakecore.c$20$2$31 Def00001C
+S A$radiodswakecore$3278 Def000000
+S C$radiodswakecore.c$23$1$30 Def000026
+S A$radiodswakecore$3297 Def000010
+S A$radiodswakecore$3288 Def000007
+S C$radiodswakecore.c$24$1$30 Def000026
+S A$radiodswakecore$3298 Def000012
+S C$radiodswakecore.c$25$1$30 Def000029
+S C$radiodswakecore.c$12$3$32 Def000007
+S C$radiodswakecore.c$26$1$30 Def00002F
+S C$radiodswakecore.c$13$3$32 Def00000A
+S C$radiodswakecore.c$27$1$30 Def000031
+S C$radiodswakecore.c$14$3$32 Def00000D
+S C$radiodswakecore.c$15$3$32 Def000010
+S C$radiodswakecore.c$16$4$33 Def000015
+S C$radiodswakecore.c$19$3$32 Def000019
+S C$radiodswakecore.c$17$4$33 Def000017
+S C$radiodswakecore.c$8$1$30 Def000002
+S G$radio_wakeup_deepsleep_core$0$0 Def000000
+S C$radiodswakecore.c$5$0$0 Def000000
+S C$radiodswakecore.c$7$1$0 Def000000
+S _radio_wakeup_deepsleep_core Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 7F 00 53 8C F7 7E 03
+R 00 00 00 16
+T 00 00 07
+R 00 00 00 16
+T 00 00 07 43 8E 08 53 8E F7 53 8C FE E5 8D 30 E3
+R 00 00 00 16
+T 00 00 14 04 7D 00 80 0D
+R 00 00 00 16
+T 00 00 19
+R 00 00 00 16
+T 00 00 19 43 8C 01 EF 14 FC FF 70 E5 DE E3 7D 04
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 43 8C 09 90 70 44 74 47 F0 8D 82 22
+R 00 00 00 16
+
+
+M:radiodswakecore
+F:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lradiodswakecore.radio_wakeup_deepsleep_core$i$1$30({1}SC:U),R,0,0,[r5]
+S:Lradiodswakecore.radio_wakeup_deepsleep_core$j$1$30({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
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+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
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+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
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+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
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+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_REF$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RXDATARATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLE$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKDATARATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKRFFREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TXPWRCOEFFD0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TXPWRCOEFFE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPTIMER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLY$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
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+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031comminit
+
+;!FILE libmflarge/ax5031comminit.asm
+XH3
+H 1A areas 3A7 global symbols
+M ax5031comminit
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S _ax5031_comminit Def000000
+S XG$ax5031_comminit$0$0 Def000026
+S A$ax5031comminit$1460 Def000000
+S A$ax5031comminit$1471 Def00000C
+S A$ax5031comminit$1490 Def000021
+S A$ax5031comminit$1463 Def000003
+S A$ax5031comminit$1491 Def000024
+S A$ax5031comminit$1482 Def000018
+S A$ax5031comminit$1492 Def000025
+S A$ax5031comminit$1483 Def00001B
+S A$ax5031comminit$1474 Def00000F
+S A$ax5031comminit$1484 Def00001D
+S A$ax5031comminit$1475 Def000012
+S A$ax5031comminit$1466 Def000006
+S A$ax5031comminit$1485 Def00001E
+S A$ax5031comminit$1476 Def000014
+S A$ax5031comminit$1467 Def000009
+S A$ax5031comminit$1495 Def000026
+S A$ax5031comminit$1486 Def00001F
+S A$ax5031comminit$1477 Def000015
+S A$ax5031comminit$1468 Def00000B
+S A$ax5031comminit$1487 Def000020
+S A$ax5031comminit$1478 Def000016
+S A$ax5031comminit$1479 Def000017
+S C$ax5031comminit.c$10$1$66 Def000000
+S C$ax5031comminit.c$11$1$66 Def000003
+S C$ax5031comminit.c$12$1$66 Def000006
+S C$ax5031comminit.c$13$1$66 Def00000C
+S C$ax5031comminit.c$23$1$66 Def000021
+S C$ax5031comminit.c$24$1$66 Def000026
+S C$ax5031comminit.c$15$1$66 Def00000F
+S C$ax5031comminit.c$16$1$66 Def000018
+S G$ax5031_comminit$0$0 Def000000
+S C$ax5031comminit.c$8$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 40 74 05 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 26 22
+R 00 00 00 16
+
+
+M:ax5031comminit
+F:G$ax5031_comminit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031commslpexit
+
+;!FILE libmflarge/ax5031commslpexit.asm
+XH3
+H 1A areas 3A9 global symbols
+M ax5031commslpexit
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S _ax5031_probeirq Ref000000
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
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+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
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+S C$ax5031commslpexit.c$8$0$0 Def000000
+S G$ax5031_commsleepexit$0$0 Def000000
+S _ax5031_commsleepexit Def000000
+S XG$ax5031_commsleepexit$0$0 Def000027
+S A$ax5031commslpexit$1470 Def00000B
+S A$ax5031commslpexit$1461 Def000000
+S A$ax5031commslpexit$1480 Def000017
+S A$ax5031commslpexit$1471 Def00000D
+S A$ax5031commslpexit$1490 Def000022
+S A$ax5031commslpexit$1481 Def000018
+S A$ax5031commslpexit$1472 Def00000E
+S A$ax5031commslpexit$1491 Def000023
+S A$ax5031commslpexit$1482 Def000019
+S A$ax5031commslpexit$1464 Def000003
+S A$ax5031commslpexit$1483 Def00001A
+S A$ax5031commslpexit$1475 Def00000F
+S A$ax5031commslpexit$1494 Def000024
+S A$ax5031commslpexit$1467 Def000006
+S A$ax5031commslpexit$1486 Def00001B
+S A$ax5031commslpexit$1468 Def000009
+S A$ax5031commslpexit$1487 Def00001E
+S A$ax5031commslpexit$1478 Def000012
+S A$ax5031commslpexit$1469 Def00000A
+S A$ax5031commslpexit$1497 Def000027
+S A$ax5031commslpexit$1488 Def000020
+S A$ax5031commslpexit$1479 Def000015
+S A$ax5031commslpexit$1489 Def000021
+S C$ax5031commslpexit.c$10$1$66 Def000000
+S C$ax5031commslpexit.c$11$1$66 Def000003
+S C$ax5031commslpexit.c$12$1$66 Def000006
+S C$ax5031commslpexit.c$13$1$66 Def00000F
+S C$ax5031commslpexit.c$24$1$66 Def000024
+S C$ax5031commslpexit.c$15$1$66 Def000012
+S C$ax5031commslpexit.c$25$1$66 Def000027
+S C$ax5031commslpexit.c$16$1$66 Def00001B
+A CONST size 0 flags 20 addr 0
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+
+
+M:ax5031commslpexit
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+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031reset
+
+;!FILE libmflarge/ax5031reset.asm
+XH3
+H 1A areas 436 global symbols
+M ax5031reset
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S _delay Ref000000
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size DF flags 20 addr 0
+S C$ax5031reset.c$8$0$0 Def000000
+S _ax5031_reset Def000000
+S _ax5031_probeirq Def000079
+S XG$ax5031_reset$0$0 Def000078
+S XG$ax5031_probeirq$0$0 Def0000DE
+S A$ax5031reset$1500 Def00002A
+S A$ax5031reset$1501 Def00002C
+S A$ax5031reset$1700 Def0000D9
+S A$ax5031reset$1610 Def000088
+S A$ax5031reset$1601 Def000081
+S A$ax5031reset$1520 Def00003B
+S A$ax5031reset$1620 Def000093
+S A$ax5031reset$1611 Def00008B
+S A$ax5031reset$1530 Def000045
+S A$ax5031reset$1521 Def00003E
+S A$ax5031reset$1512 Def000035
+S A$ax5031reset$1630 Def00009D
+S A$ax5031reset$1621 Def000095
+S A$ax5031reset$1612 Def00008C
+S A$ax5031reset$1531 Def000048
+S A$ax5031reset$1513 Def000038
+S A$ax5031reset$1504 Def00002D
+S A$ax5031reset$1703 Def0000DB
+S A$ax5031reset$1640 Def0000A6
+S A$ax5031reset$1631 Def00009E
+S A$ax5031reset$1622 Def000097
+S A$ax5031reset$1604 Def000083
+S A$ax5031reset$1532 Def00004A
+S A$ax5031reset$1505 Def00002E
+S A$ax5031reset$1650 Def0000B0
+S A$ax5031reset$1641 Def0000A9
+S A$ax5031reset$1632 Def00009F
+S A$ax5031reset$1560 Def000067
+S A$ax5031reset$1542 Def000052
+S A$ax5031reset$1470 Def000006
+S A$ax5031reset$1660 Def0000B9
+S A$ax5031reset$1651 Def0000B3
+S A$ax5031reset$1615 Def00008D
+S A$ax5031reset$1570 Def000073
+S A$ax5031reset$1552 Def00005D
+S A$ax5031reset$1543 Def000055
+S A$ax5031reset$1525 Def000040
+S A$ax5031reset$1516 Def000039
+S A$ax5031reset$1480 Def000014
+S A$ax5031reset$1471 Def000009
+S A$ax5031reset$1652 Def0000B4
+S A$ax5031reset$1625 Def000098
+S A$ax5031reset$1616 Def000090
+S A$ax5031reset$1607 Def000085
+S A$ax5031reset$1553 Def00005E
+S A$ax5031reset$1535 Def00004B
+S A$ax5031reset$1526 Def000043
+S A$ax5031reset$1517 Def00003A
+S A$ax5031reset$1508 Def00002F
+S A$ax5031reset$1472 Def00000B
+S A$ax5031reset$1707 Def0000DE
+S A$ax5031reset$1680 Def0000CB
+S A$ax5031reset$1653 Def0000B5
+S A$ax5031reset$1635 Def0000A1
+S A$ax5031reset$1626 Def00009A
+S A$ax5031reset$1617 Def000092
+S A$ax5031reset$1554 Def00005F
+S A$ax5031reset$1536 Def00004C
+S A$ax5031reset$1509 Def000032
+S A$ax5031reset$1491 Def00001E
+S A$ax5031reset$1464 Def000000
+S A$ax5031reset$1690 Def0000D2
+S A$ax5031reset$1681 Def0000CC
+S A$ax5031reset$1654 Def0000B7
+S A$ax5031reset$1645 Def0000AB
+S A$ax5031reset$1636 Def0000A4
+S A$ax5031reset$1564 Def000069
+S A$ax5031reset$1555 Def000062
+S A$ax5031reset$1537 Def00004D
+S A$ax5031reset$1492 Def000021
+S A$ax5031reset$1483 Def000015
+S A$ax5031reset$1664 Def0000BB
+S A$ax5031reset$1655 Def0000B8
+S A$ax5031reset$1646 Def0000AE
+S A$ax5031reset$1637 Def0000A5
+S A$ax5031reset$1574 Def000075
+S A$ax5031reset$1565 Def00006C
+S A$ax5031reset$1547 Def000057
+S A$ax5031reset$1538 Def000050
+S A$ax5031reset$1493 Def000023
+S A$ax5031reset$1484 Def000018
+S A$ax5031reset$1475 Def00000C
+S A$ax5031reset$1674 Def0000C4
+S A$ax5031reset$1665 Def0000BE
+S A$ax5031reset$1629 Def00009B
+S A$ax5031reset$1566 Def00006E
+S A$ax5031reset$1548 Def00005A
+S A$ax5031reset$1494 Def000024
+S A$ax5031reset$1485 Def00001A
+S A$ax5031reset$1467 Def000003
+S A$ax5031reset$1684 Def0000CD
+S A$ax5031reset$1666 Def0000BF
+S A$ax5031reset$1549 Def00005C
+S A$ax5031reset$1495 Def000025
+S A$ax5031reset$1486 Def00001B
+S A$ax5031reset$1694 Def0000D4
+S A$ax5031reset$1667 Def0000C0
+S A$ax5031reset$1595 Def000079
+S A$ax5031reset$1559 Def000064
+S A$ax5031reset$1496 Def000026
+S A$ax5031reset$1487 Def00001C
+S A$ax5031reset$1478 Def00000F
+S A$ax5031reset$1695 Def0000D5
+S A$ax5031reset$1668 Def0000C2
+S A$ax5031reset$1596 Def00007C
+S A$ax5031reset$1578 Def000078
+S A$ax5031reset$1569 Def000070
+S A$ax5031reset$1488 Def00001D
+S A$ax5031reset$1479 Def000012
+S A$ax5031reset$1696 Def0000D6
+S A$ax5031reset$1687 Def0000CF
+S A$ax5031reset$1678 Def0000C6
+S A$ax5031reset$1669 Def0000C3
+S A$ax5031reset$1597 Def00007D
+S A$ax5031reset$1697 Def0000D7
+S A$ax5031reset$1679 Def0000C9
+S A$ax5031reset$1598 Def00007E
+S A$ax5031reset$1499 Def000027
+S C$ax5031reset.c$20$1$66 Def00000F
+S C$ax5031reset.c$12$1$66 Def000000
+S C$ax5031reset.c$22$1$66 Def000015
+S C$ax5031reset.c$13$1$66 Def000003
+S C$ax5031reset.c$23$1$66 Def00001E
+S C$ax5031reset.c$60$1$66 Def000075
+S C$ax5031reset.c$51$1$66 Def000045
+S C$ax5031reset.c$42$1$66 Def000035
+S C$ax5031reset.c$61$1$66 Def000078
+S C$ax5031reset.c$52$1$66 Def00004B
+S C$ax5031reset.c$43$1$66 Def000039
+S C$ax5031reset.c$53$1$66 Def000052
+S C$ax5031reset.c$35$1$66 Def000027
+S C$ax5031reset.c$17$1$66 Def000006
+S C$ax5031reset.c$70$1$68 Def000085
+S C$ax5031reset.c$54$1$66 Def000057
+S C$ax5031reset.c$36$1$66 Def00002D
+S C$ax5031reset.c$71$1$68 Def000088
+S C$ax5031reset.c$64$1$66 Def000079
+S C$ax5031reset.c$55$1$66 Def00005D
+S C$ax5031reset.c$19$1$66 Def00000C
+S C$ax5031reset.c$72$1$68 Def00008D
+S C$ax5031reset.c$56$1$66 Def000064
+S C$ax5031reset.c$91$1$68 Def0000D2
+S C$ax5031reset.c$80$2$69 Def0000B9
+S C$ax5031reset.c$73$1$68 Def000093
+S C$ax5031reset.c$48$1$66 Def00003B
+S C$ax5031reset.c$39$1$66 Def00002F
+S C$ax5031reset.c$92$1$68 Def0000D4
+S C$ax5031reset.c$90$2$69 Def0000CF
+S C$ax5031reset.c$74$1$68 Def000098
+S C$ax5031reset.c$58$1$66 Def000069
+S C$ax5031reset.c$49$1$66 Def000040
+S C$ax5031reset.c$93$1$68 Def0000D9
+S C$ax5031reset.c$82$2$69 Def0000B9
+S C$ax5031reset.c$75$1$68 Def00009B
+S C$ax5031reset.c$59$1$66 Def000070
+S C$ax5031reset.c$94$1$68 Def0000DB
+S C$ax5031reset.c$83$2$69 Def0000BB
+S C$ax5031reset.c$76$1$68 Def0000A1
+S C$ax5031reset.c$67$1$68 Def000079
+S C$ax5031reset.c$95$1$68 Def0000DE
+S C$ax5031reset.c$84$2$69 Def0000C4
+S C$ax5031reset.c$77$1$68 Def0000A6
+S C$ax5031reset.c$68$1$68 Def000081
+S C$ax5031reset.c$69$1$68 Def000083
+S G$ax5031_reset$0$0 Def000000
+S C$ax5031reset.c$86$2$69 Def0000C4
+S G$ax5031_probeirq$0$0 Def000079
+S C$ax5031reset.c$78$2$69 Def0000AB
+S C$ax5031reset.c$88$2$69 Def0000C6
+S C$ax5031reset.c$79$2$69 Def0000B0
+S C$ax5031reset.c$89$2$69 Def0000CD
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 00 0A 12
+R 00 00 00 16
+T 00 00 33 00 00 90 40 00 E0 E0 FF BF 21 02 80 05
+R 00 00 00 16 02 03 02 70
+T 00 00 40
+R 00 00 00 16
+T 00 00 40 75 82 01 80 33
+R 00 00 00 16
+T 00 00 45
+R 00 00 00 16
+T 00 00 45 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 52
+R 00 00 00 16
+T 00 00 52 75 82 02 80 21
+R 00 00 00 16
+T 00 00 57
+R 00 00 00 16
+T 00 00 57 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 64
+R 00 00 00 16
+T 00 00 64 75 82 02 80 0F
+R 00 00 00 16
+T 00 00 69
+R 00 00 00 16
+T 00 00 69 12 00 79 E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 04 00 16
+T 00 00 75
+R 00 00 00 16
+T 00 00 75 75 82 00
+R 00 00 00 16
+T 00 00 78
+R 00 00 00 16
+T 00 00 78 22
+R 00 00 00 16
+T 00 00 79
+R 00 00 00 16
+T 00 00 79 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 86 8C EB 90 40 0C EF F0 90 40 0D 74 22 F0
+R 00 00 00 16
+T 00 00 93 74 60 55 8D FD 74 20 F0 E5 8D F4 FC 52
+R 00 00 00 16
+T 00 00 A0 05 90 40 0D E4 F0 BD 20 02 80 05
+R 00 00 00 16
+T 00 00 AB
+R 00 00 00 16
+T 00 00 AB BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 B0
+R 00 00 00 16
+T 00 00 B0 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 BB
+R 00 00 00 16
+T 00 00 BB 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 C6
+R 00 00 00 16
+T 00 00 C6 90 40 0C 74 20 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 D3 0A
+R 00 00 00 16
+T 00 00 D4
+R 00 00 00 16
+T 00 00 D4 ED F4 FD 52 8C 8E A8 75 82 00
+R 00 00 00 16
+T 00 00 DE
+R 00 00 00 16
+T 00 00 DE 22
+R 00 00 00 16
+
+
+M:ax5031reset
+F:G$ax5031_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5031reset.ax5031_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5031_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5031reset.ax5031_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5031reset.ax5031_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5031reset.ax5031_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031deepsleep
+
+XH3
+H 1A areas 385 global symbols
+M ax5031deepsleep
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5031deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
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+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
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+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031rclkena
+
+;!FILE libmflarge/ax5031rclkena.asm
+XH3
+H 1A areas 3B7 global symbols
+M ax5031rclkena
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3D flags 20 addr 0
+S G$ax5031_rclk_enable$0$0 Def000000
+S A$ax5031rclkena$1500 Def000025
+S A$ax5031rclkena$1501 Def000028
+S _ax5031_rclk_enable Def000000
+S A$ax5031rclkena$1520 Def00003A
+S A$ax5031rclkena$1511 Def000030
+S A$ax5031rclkena$1512 Def000032
+S A$ax5031rclkena$1513 Def000033
+S A$ax5031rclkena$1504 Def000029
+S A$ax5031rclkena$1523 Def00003C
+S A$ax5031rclkena$1514 Def000036
+S A$ax5031rclkena$1505 Def00002A
+S A$ax5031rclkena$1515 Def000038
+S A$ax5031rclkena$1506 Def00002C
+S A$ax5031rclkena$1470 Def000007
+S A$ax5031rclkena$1507 Def00002E
+S A$ax5031rclkena$1480 Def00000F
+S A$ax5031rclkena$1462 Def000000
+S A$ax5031rclkena$1490 Def000019
+S A$ax5031rclkena$1481 Def000011
+S A$ax5031rclkena$1491 Def00001C
+S A$ax5031rclkena$1519 Def000039
+S A$ax5031rclkena$1492 Def00001F
+S A$ax5031rclkena$1474 Def000009
+S A$ax5031rclkena$1465 Def000002
+S A$ax5031rclkena$1493 Def000020
+S A$ax5031rclkena$1484 Def000012
+S A$ax5031rclkena$1475 Def00000A
+S A$ax5031rclkena$1494 Def000021
+S A$ax5031rclkena$1476 Def00000C
+S A$ax5031rclkena$1467 Def000005
+S XG$ax5031_rclk_enable$0$0 Def00003C
+S A$ax5031rclkena$1487 Def000014
+S A$ax5031rclkena$1497 Def000022
+S A$ax5031rclkena$1488 Def000017
+S A$ax5031rclkena$1479 Def00000D
+S A$ax5031rclkena$1489 Def000018
+S C$ax5031rclkena.c$10$1$64 Def000009
+S C$ax5031rclkena.c$11$1$64 Def00000D
+S C$ax5031rclkena.c$12$1$64 Def000012
+S C$ax5031rclkena.c$13$1$64 Def000014
+S C$ax5031rclkena.c$14$1$64 Def000022
+S C$ax5031rclkena.c$15$1$64 Def000025
+S C$ax5031rclkena.c$16$1$64 Def000029
+S C$ax5031rclkena.c$17$1$64 Def000030
+S C$ax5031rclkena.c$18$1$64 Def000039
+S C$ax5031rclkena.c$19$1$64 Def00003C
+S C$ax5031rclkena.c$8$1$64 Def000002
+S C$ax5031rclkena.c$9$1$64 Def000007
+S C$ax5031rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 09
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031rclkena
+F:G$ax5031_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031rclkena.ax5031_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5031rclkena.ax5031_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5031rclkena.ax5031_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5031rclkdis
+
+;!FILE libmflarge/ax5031rclkdis.asm
+XH3
+H 1A areas 3AC global symbols
+M ax5031rclkdis
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S C$ax5031rclkdis.c$8$1$64 Def000000
+S C$ax5031rclkdis.c$9$1$64 Def000005
+S C$ax5031rclkdis.c$5$0$0 Def000000
+S XG$ax5031_rclk_disable$0$0 Def00002B
+S A$ax5031rclkdis$1501 Def000028
+S A$ax5031rclkdis$1502 Def000029
+S A$ax5031rclkdis$1505 Def00002B
+S A$ax5031rclkdis$1480 Def000014
+S A$ax5031rclkdis$1471 Def000007
+S A$ax5031rclkdis$1490 Def00001D
+S A$ax5031rclkdis$1463 Def000000
+S A$ax5031rclkdis$1491 Def00001E
+S A$ax5031rclkdis$1464 Def000002
+S A$ax5031rclkdis$1483 Def000015
+S A$ax5031rclkdis$1474 Def00000A
+S A$ax5031rclkdis$1465 Def000004
+S A$ax5031rclkdis$1484 Def000018
+S A$ax5031rclkdis$1475 Def00000D
+S A$ax5031rclkdis$1494 Def000021
+S A$ax5031rclkdis$1485 Def000019
+S A$ax5031rclkdis$1476 Def00000E
+S A$ax5031rclkdis$1495 Def000024
+S A$ax5031rclkdis$1477 Def00000F
+S A$ax5031rclkdis$1468 Def000005
+S A$ax5031rclkdis$1496 Def000026
+S A$ax5031rclkdis$1478 Def000011
+S A$ax5031rclkdis$1497 Def000027
+S A$ax5031rclkdis$1488 Def00001A
+S A$ax5031rclkdis$1479 Def000012
+S A$ax5031rclkdis$1489 Def00001C
+S C$ax5031rclkdis.c$10$1$64 Def000007
+S C$ax5031rclkdis.c$11$1$64 Def00000A
+S C$ax5031rclkdis.c$12$1$64 Def000015
+S C$ax5031rclkdis.c$13$1$64 Def00001A
+S C$ax5031rclkdis.c$14$1$64 Def000021
+S C$ax5031rclkdis.c$15$1$64 Def000028
+S G$ax5031_rclk_disable$0$0 Def000000
+S C$ax5031rclkdis.c$16$1$64 Def00002B
+S _ax5031_rclk_disable Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 74 0F 5E FD BD 05 07 90 40 02 74 F0 5E
+R 00 00 00 16
+T 00 00 27 F0
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031rclkdis
+F:G$ax5031_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031rclkdis.ax5031_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5031rclkdis.ax5031_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5031rdfifo
+
+;!FILE libmflarge/ax5031rdfifo.asm
+XH3
+H 1A areas 3BD global symbols
+M ax5031rdfifo
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
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+S G$EIE_2$0$0 Def00009A
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+S _ADCCH2VAL0 Def007024
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+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
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+S G$E2IP_6$0$0 Def0000C6
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+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
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+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
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+S G$AX5031_TXPWR$0$0 Def004030
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+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
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+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
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+S G$ADCCH1VAL$0$0 Def007022
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+S G$OC1STATUS$0$0 Def0000C3
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+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
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+S G$OC1MODE$0$0 Def0000C1
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+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
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+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
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+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
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+S _AX5031_XTALOSC Def004003
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+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031wrfifo
+
+;!FILE libmflarge/ax5031wrfifo.asm
+XH3
+H 1A areas 3BF global symbols
+M ax5031wrfifo
+O -mmcs51 --model-large
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5031_FOURFSK Def004050
+S _AX5031_FREQA1 Def004022
+S _AX5031_FREQB0 Def00401F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5031_FIFOCOUNT$0$0 Def004035
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5031_FREQA2 Def004021
+S _AX5031_FREQB1 Def00401E
+S _AX5031_TXBITRATEMIDNB Def005032
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5031_XTALOSCNB$0$0 Def005003
+S G$AX5031_PWRMODENB$0$0 Def005002
+S G$AX5031_XTALOSCCFG$0$0 Def004051
+S G$AX5031_PLLRANGING$0$0 Def00402D
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5031_FREQA3 Def004020
+S _AX5031_FREQB2 Def00401D
+S _AX5031_PLLLOOP Def00402C
+S _AX5031_TXBITRATELONB Def005033
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5031_FREQA0NB$0$0 Def005023
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5031_FREQB3 Def00401C
+S _AX5031_MODULATORMISC Def004034
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5031_FREQB0NB$0$0 Def00501F
+S G$AX5031_FREQA1NB$0$0 Def005022
+S G$AX5031_FOURFSKNB$0$0 Def005050
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5031_FREQB1NB$0$0 Def00501E
+S G$AX5031_FREQA2NB$0$0 Def005021
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5031_TXPWR Def004030
+S _AX5031_IRQREQUESTNB Def005007
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5031_PLLLOOPNB$0$0 Def00502C
+S G$AX5031_FREQB2NB$0$0 Def00501D
+S G$AX5031_FREQA3NB$0$0 Def005020
+S G$AX5031_FIFOTHRESH$0$0 Def004036
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5031_MODULATORMISCNB$0$0 Def005034
+S G$AX5031_FREQB3NB$0$0 Def00501C
+S G$AX5031_FSKDEV0$0$0 Def004027
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5031_VREG$0$0 Def00401B
+S G$AX5031_IFMODE$0$0 Def004008
+S G$AX5031_FSKDEV1$0$0 Def004026
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5031_PINCFG1 Def00400C
+S _AX5031_IRQMASKNB Def005006
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5031_TXPWRNB$0$0 Def005030
+S G$AX5031_FSKDEV2$0$0 Def004025
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5031_IRQINVERSION Def00400F
+S _AX5031_PINCFG2 Def00400D
+S _AX5031_PLLRNGCLK Def00402E
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5031_PINCFG3 Def00400E
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5031_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _IP_4 Def0000BC
+S G$AX5031_PINCFG1NB$0$0 Def00500C
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5031_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5031_PINCFG2NB$0$0 Def00500D
+S G$AX5031_IRQINVERSIONNB$0$0 Def00500F
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5031_FIFOCOUNT Def004035
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5031_PINCFG3NB$0$0 Def00500E
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5031_PLLRANGING Def00402D
+S _AX5031_XTALOSCCFG Def004051
+S _AX5031_PWRMODENB Def005002
+S _AX5031_XTALOSCNB Def005003
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5031_FREQA0NB Def005023
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5031_MODULATION$0$0 Def004010
+S G$AX5031_CRCINIT0$0$0 Def004017
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5031_FOURFSKNB Def005050
+S _AX5031_FREQA1NB Def005022
+S _AX5031_FREQB0NB Def00501F
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5031_FIFOCOUNTNB$0$0 Def005035
+S G$AX5031_CRCINIT1$0$0 Def004016
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5031_FREQA2NB Def005021
+S _AX5031_FREQB1NB Def00501E
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5031_XTALOSCCFGNB$0$0 Def005051
+S G$AX5031_PLLRANGINGNB$0$0 Def00502D
+S G$AX5031_FIFODATA$0$0 Def004005
+S G$AX5031_CRCINIT2$0$0 Def004015
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5031_FIFOTHRESH Def004036
+S _AX5031_FREQA3NB Def005020
+S _AX5031_FREQB2NB Def00501D
+S _AX5031_PLLLOOPNB Def00502C
+S _EIP_6 Def0000B6
+S G$AX5031_CRCINIT3$0$0 Def004014
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5031_FSKDEV0 Def004027
+S _AX5031_FREQB3NB Def00501C
+S _AX5031_MODULATORMISCNB Def005034
+S _EIP_7 Def0000B7
+S G$AX5031_SILICONREVISION$0$0 Def004000
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5031_FSKDEV1 Def004026
+S _AX5031_IFMODE Def004008
+S _AX5031_VREG Def00401B
+S _XPAGE Def0000D9
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5031_FSKDEV2 Def004025
+S _AX5031_TXPWRNB Def005030
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5031_FIFOTHRESHNB$0$0 Def005036
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5031_FSKDEV0NB$0$0 Def005027
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5031_FIFOCONTROL2 Def004037
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5031_VREGNB$0$0 Def00501B
+S G$AX5031_IFMODENB$0$0 Def005008
+S G$AX5031_FSKDEV1NB$0$0 Def005026
+S G$AX5031_FRAMING$0$0 Def004012
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5031_PINCFG1NB Def00500C
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5031_FSKDEV2NB$0$0 Def005025
+S G$AX5031_FIFOCONTROL$0$0 Def004004
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5031_IRQINVERSIONNB Def00500F
+S _AX5031_PINCFG2NB Def00500D
+S _AX5031_PLLRNGCLKNB Def00502E
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5031_PINCFG3NB Def00500E
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5031_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5031_ENCODING$0$0 Def004011
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5031_TXBITRATEHI$0$0 Def004031
+S G$AX5031_SCRATCH$0$0 Def004001
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5031_CRCINIT0 Def004017
+S _AX5031_MODULATION Def004010
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5031_CRCINIT1 Def004016
+S _AX5031_FIFOCOUNTNB Def005035
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5031_CRCINIT2 Def004015
+S _AX5031_FIFODATA Def004005
+S _AX5031_PLLRANGINGNB Def00502D
+S _AX5031_XTALOSCCFGNB Def005051
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5031_CRCINIT3 Def004014
+S _PINC_7 Def0000FF
+S G$AX5031_MODULATIONNB$0$0 Def005010
+S G$AX5031_CRCINIT0NB$0$0 Def005017
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5031_SILICONREVISION Def004000
+S _WTCNTA0 Def0000F2
+S G$AX5031_CRCINIT1NB$0$0 Def005016
+S G$AX5031_XTALCAP$0$0 Def00404F
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5031_FIFODATANB$0$0 Def005005
+S G$AX5031_CRCINIT2NB$0$0 Def005015
+S G$AX5031_FEC$0$0 Def004018
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5031_FIFOTHRESHNB Def005036
+S _WTCNTB1 Def0000FB
+S G$AX5031_CRCINIT3NB$0$0 Def005014
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5031_FSKDEV0NB Def005027
+S _AC Def0000D6
+S G$AX5031_SILICONREVISIONNB$0$0 Def005000
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5031_FRAMING Def004012
+S _AX5031_FSKDEV1NB Def005026
+S _AX5031_IFMODENB Def005008
+S _AX5031_VREGNB Def00501B
+S _E2IE Def0000A0
+S G$AX5031_TXBITRATEMID$0$0 Def004032
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5031_FIFOCONTROL Def004004
+S _AX5031_FSKDEV2NB Def005025
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5031_TXBITRATELO$0$0 Def004033
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5031_ENCODING Def004011
+S _AX5031_FIFOCONTROL2NB Def005037
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5031_FRAMINGNB$0$0 Def005012
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5031_SCRATCH Def004001
+S _AX5031_TXBITRATEHI Def004031
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5031_FIFOCONTROLNB$0$0 Def005004
+S G$AX5031_IRQREQUEST$0$0 Def004007
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _WTEVTA0 Def0000F4
+S G$AX5031_ENCODINGNB$0$0 Def005011
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5031_TXBITRATEHINB$0$0 Def005031
+S G$AX5031_SCRATCHNB$0$0 Def005001
+S G$AX5031_IRQMASK$0$0 Def004006
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5031_CRCINIT0NB Def005017
+S _AX5031_MODULATIONNB Def005010
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5031_XTALCAP Def00404F
+S _AX5031_CRCINIT1NB Def005016
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5031_FEC Def004018
+S _AX5031_CRCINIT2NB Def005015
+S _AX5031_FIFODATANB Def005005
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5031_CRCINIT3NB Def005014
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5031_SILICONREVISIONNB Def005000
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5031_XTALCAPNB$0$0 Def00504F
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5031_TXBITRATEMID Def004032
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5031_FECNB$0$0 Def005018
+S G$AX5031_XTALOSC$0$0 Def004003
+S G$AX5031_PWRMODE$0$0 Def004002
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5031_TXBITRATELO Def004033
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5031_FREQA0$0$0 Def004023
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5031_FREQB0$0$0 Def00401F
+S G$AX5031_FREQA1$0$0 Def004022
+S G$AX5031_FOURFSK$0$0 Def004050
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5031_FRAMINGNB Def005012
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5031_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5031_FREQB1$0$0 Def00401E
+S G$AX5031_FREQA2$0$0 Def004021
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5031_IRQREQUEST Def004007
+S _AX5031_FIFOCONTROLNB Def005004
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5031_TXBITRATELONB$0$0 Def005033
+S G$AX5031_PLLLOOP$0$0 Def00402C
+S G$AX5031_FREQB2$0$0 Def00401D
+S G$AX5031_FREQA3$0$0 Def004020
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5031_MODULATORMISC$0$0 Def004034
+S G$AX5031_FREQB3$0$0 Def00401C
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5031_ENCODINGNB Def005011
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5031_IRQMASK Def004006
+S _AX5031_SCRATCHNB Def005001
+S _AX5031_TXBITRATEHINB Def005031
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5031_IRQREQUESTNB$0$0 Def005007
+S G$AX5031_TXPWR$0$0 Def004030
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5031_IRQMASKNB$0$0 Def005006
+S G$AX5031_PINCFG1$0$0 Def00400C
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5031_PLLRNGCLK$0$0 Def00402E
+S G$AX5031_PINCFG2$0$0 Def00400D
+S G$AX5031_IRQINVERSION$0$0 Def00400F
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5031_XTALCAPNB Def00504F
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5031_PINCFG3$0$0 Def00400E
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5031_PWRMODE Def004002
+S _AX5031_XTALOSC Def004003
+S _AX5031_FECNB Def005018
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5031_FREQA0 Def004023
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S A$ax5031wrfifo$1511 Def00004D
+S A$ax5031wrfifo$1502 Def000040
+S A$ax5031wrfifo$1512 Def00004E
+S A$ax5031wrfifo$1503 Def000041
+S A$ax5031wrfifo$1513 Def000050
+S A$ax5031wrfifo$1504 Def000043
+S A$ax5031wrfifo$1514 Def000052
+S A$ax5031wrfifo$1505 Def000045
+S A$ax5031wrfifo$1460 Def000005
+S A$ax5031wrfifo$1515 Def000053
+S A$ax5031wrfifo$1506 Def000048
+S A$ax5031wrfifo$1470 Def000018
+S A$ax5031wrfifo$1461 Def000006
+S A$ax5031wrfifo$1516 Def000055
+S A$ax5031wrfifo$1480 Def000020
+S A$ax5031wrfifo$1471 Def000019
+S A$ax5031wrfifo$1462 Def000008
+S A$ax5031wrfifo$1508 Def00004A
+S A$ax5031wrfifo$1481 Def000022
+S A$ax5031wrfifo$1472 Def00001A
+S A$ax5031wrfifo$1463 Def000009
+S A$ax5031wrfifo$1509 Def00004B
+S A$ax5031wrfifo$1491 Def000031
+S A$ax5031wrfifo$1464 Def00000C
+S A$ax5031wrfifo$1492 Def000032
+S A$ax5031wrfifo$1483 Def000023
+S A$ax5031wrfifo$1474 Def00001C
+S A$ax5031wrfifo$1465 Def00000F
+S A$ax5031wrfifo$1493 Def000033
+S A$ax5031wrfifo$1484 Def000025
+S A$ax5031wrfifo$1466 Def000011
+S A$ax5031wrfifo$1457 Def000000
+S A$ax5031wrfifo$1494 Def000034
+S A$ax5031wrfifo$1485 Def000027
+S A$ax5031wrfifo$1467 Def000014
+S A$ax5031wrfifo$1458 Def000002
+S A$ax5031wrfifo$1495 Def000036
+S A$ax5031wrfifo$1486 Def000028
+S A$ax5031wrfifo$1477 Def00001D
+S A$ax5031wrfifo$1459 Def000004
+S A$ax5031wrfifo$1496 Def000038
+S A$ax5031wrfifo$1487 Def00002A
+S A$ax5031wrfifo$1478 Def00001E
+S A$ax5031wrfifo$1469 Def000017
+S A$ax5031wrfifo$1497 Def000039
+S A$ax5031wrfifo$1488 Def00002C
+S A$ax5031wrfifo$1479 Def00001F
+S A$ax5031wrfifo$1498 Def00003B
+S A$ax5031wrfifo$1489 Def00002F
+S C$ax5031wrfifo.c$10$0$0 Def000000
+S C$ax5031wrfifo.c$75$1$66 Def000000
+S C$ax5031wrfifo.c$76$1$66 Def000056
+S G$ax5031_writefifo$0$0 Def000000
+S _ax5031_writefifo Def000000
+S XG$ax5031_writefifo$0$0 Def000056
+S A$ax5031wrfifo$1500 Def00003C
+S A$ax5031wrfifo$1510 Def00004C
+S A$ax5031wrfifo$1501 Def00003E
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
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+R 00 00 00 16
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+T 00 00 17 E6 F0 08 DF FB
+R 00 00 00 16
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+R 00 00 00 16
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+R 00 00 00 16
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+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 05
+R 00 00 00 16
+T 00 00 31
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+T 00 00 31 E0 F2 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
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+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 05
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E4 93 F2 A3 DF FA 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5031wrfifo
+F:G$ax5031_writefifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5031wrfifo.ax5031_writefifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5031wrfifo.ax5031_writefifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSK$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFG$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FOURFSKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5031_XTALOSCCFGNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5031regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5031regs
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5031regs
+
+
+
+
+ax5042comminit
+
+;!FILE libmflarge/ax5042comminit.asm
+XH3
+H 1A areas 3FF global symbols
+M ax5042comminit
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
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+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$ax5042comminit.c$8$0$0 Def000000
+S _ax5042_comminit Def000000
+S XG$ax5042_comminit$0$0 Def000026
+S A$ax5042comminit$1600 Def00000B
+S A$ax5042comminit$1610 Def000016
+S A$ax5042comminit$1611 Def000017
+S A$ax5042comminit$1603 Def00000C
+S A$ax5042comminit$1622 Def000021
+S A$ax5042comminit$1623 Def000024
+S A$ax5042comminit$1614 Def000018
+S A$ax5042comminit$1624 Def000025
+S A$ax5042comminit$1615 Def00001B
+S A$ax5042comminit$1606 Def00000F
+S A$ax5042comminit$1616 Def00001D
+S A$ax5042comminit$1607 Def000012
+S A$ax5042comminit$1617 Def00001E
+S A$ax5042comminit$1608 Def000014
+S A$ax5042comminit$1627 Def000026
+S A$ax5042comminit$1618 Def00001F
+S A$ax5042comminit$1609 Def000015
+S A$ax5042comminit$1619 Def000020
+S A$ax5042comminit$1592 Def000000
+S A$ax5042comminit$1595 Def000003
+S A$ax5042comminit$1598 Def000006
+S A$ax5042comminit$1599 Def000009
+S C$ax5042comminit.c$10$1$66 Def000000
+S C$ax5042comminit.c$11$1$66 Def000003
+S C$ax5042comminit.c$12$1$66 Def000006
+S C$ax5042comminit.c$13$1$66 Def00000C
+S C$ax5042comminit.c$23$1$66 Def000021
+S C$ax5042comminit.c$24$1$66 Def000026
+S C$ax5042comminit.c$15$1$66 Def00000F
+S C$ax5042comminit.c$16$1$66 Def000018
+S G$ax5042_comminit$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
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+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
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+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
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+R 00 00 00 16
+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 26 22
+R 00 00 00 16
+
+
+M:ax5042comminit
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+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
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+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
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+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
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+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
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+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
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+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042commslpexit
+
+;!FILE libmflarge/ax5042commslpexit.asm
+XH3
+H 1A areas 401 global symbols
+M ax5042commslpexit
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _ax5042_probeirq Ref000000
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5042commslpexit.c$24$1$66 Def000024
+S C$ax5042commslpexit.c$15$1$66 Def000012
+S C$ax5042commslpexit.c$25$1$66 Def000027
+S C$ax5042commslpexit.c$16$1$66 Def00001B
+S C$ax5042commslpexit.c$8$0$0 Def000000
+S G$ax5042_commsleepexit$0$0 Def000000
+S _ax5042_commsleepexit Def000000
+S A$ax5042commslpexit$1600 Def000009
+S A$ax5042commslpexit$1610 Def000012
+S A$ax5042commslpexit$1601 Def00000A
+S A$ax5042commslpexit$1620 Def000020
+S A$ax5042commslpexit$1611 Def000015
+S A$ax5042commslpexit$1602 Def00000B
+S A$ax5042commslpexit$1621 Def000021
+S A$ax5042commslpexit$1612 Def000017
+S A$ax5042commslpexit$1603 Def00000D
+S A$ax5042commslpexit$1622 Def000022
+S A$ax5042commslpexit$1613 Def000018
+S A$ax5042commslpexit$1604 Def00000E
+S XG$ax5042_commsleepexit$0$0 Def000027
+S A$ax5042commslpexit$1623 Def000023
+S A$ax5042commslpexit$1614 Def000019
+S A$ax5042commslpexit$1615 Def00001A
+S A$ax5042commslpexit$1607 Def00000F
+S A$ax5042commslpexit$1626 Def000024
+S A$ax5042commslpexit$1618 Def00001B
+S A$ax5042commslpexit$1619 Def00001E
+S A$ax5042commslpexit$1629 Def000027
+S A$ax5042commslpexit$1593 Def000000
+S A$ax5042commslpexit$1596 Def000003
+S A$ax5042commslpexit$1599 Def000006
+S C$ax5042commslpexit.c$10$1$66 Def000000
+S C$ax5042commslpexit.c$11$1$66 Def000003
+S C$ax5042commslpexit.c$12$1$66 Def000006
+S C$ax5042commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
+R 00 00 00 16
+T 00 00 0D 4F F0 75 B1 00 90 70 40 74 05 F0 E4 A3
+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 04 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 5F
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5042commslpexit
+F:G$ax5042_commsleepexit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042reset
+
+;!FILE libmflarge/ax5042reset.asm
+XH3
+H 1A areas 49B global symbols
+M ax5042reset
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size F3 flags 20 addr 0
+S C$ax5042reset.c$8$0$0 Def000000
+S _ax5042_reset Def000000
+S _ax5042_probeirq Def00008A
+S XG$ax5042_reset$0$0 Def000089
+S XG$ax5042_probeirq$0$0 Def0000F2
+S A$ax5042reset$1610 Def000012
+S A$ax5042reset$1601 Def000006
+S A$ax5042reset$1800 Def0000C8
+S A$ax5042reset$1701 Def00006E
+S A$ax5042reset$1611 Def000014
+S A$ax5042reset$1602 Def000009
+S A$ax5042reset$1801 Def0000C9
+S A$ax5042reset$1711 Def00007A
+S A$ax5042reset$1702 Def000071
+S A$ax5042reset$1630 Def000027
+S A$ax5042reset$1603 Def00000B
+S A$ax5042reset$1802 Def0000CB
+S A$ax5042reset$1721 Def000086
+S A$ax5042reset$1712 Def00007D
+S A$ax5042reset$1703 Def000073
+S A$ax5042reset$1640 Def000032
+S A$ax5042reset$1631 Def00002A
+S A$ax5042reset$1622 Def00001E
+S A$ax5042reset$1812 Def0000CF
+S A$ax5042reset$1803 Def0000CC
+S A$ax5042reset$1713 Def00007F
+S A$ax5042reset$1632 Def00002C
+S A$ax5042reset$1623 Def000021
+S A$ax5042reset$1614 Def000015
+S A$ax5042reset$1822 Def0000D8
+S A$ax5042reset$1813 Def0000D2
+S A$ax5042reset$1624 Def000023
+S A$ax5042reset$1615 Def000018
+S A$ax5042reset$1606 Def00000C
+S A$ax5042reset$1832 Def0000E1
+S A$ax5042reset$1814 Def0000D3
+S A$ax5042reset$1760 Def00009F
+S A$ax5042reset$1751 Def000094
+S A$ax5042reset$1742 Def00008A
+S A$ax5042reset$1706 Def000074
+S A$ax5042reset$1670 Def00004F
+S A$ax5042reset$1652 Def00003A
+S A$ax5042reset$1643 Def000033
+S A$ax5042reset$1625 Def000024
+S A$ax5042reset$1616 Def00001A
+S A$ax5042reset$1851 Def0000EF
+S A$ax5042reset$1842 Def0000E8
+S A$ax5042reset$1815 Def0000D4
+S A$ax5042reset$1770 Def0000AA
+S A$ax5042reset$1743 Def00008D
+S A$ax5042reset$1725 Def000089
+S A$ax5042reset$1716 Def000081
+S A$ax5042reset$1707 Def000077
+S A$ax5042reset$1680 Def000058
+S A$ax5042reset$1662 Def000045
+S A$ax5042reset$1653 Def00003D
+S A$ax5042reset$1644 Def000034
+S A$ax5042reset$1635 Def00002D
+S A$ax5042reset$1626 Def000025
+S A$ax5042reset$1617 Def00001B
+S A$ax5042reset$1843 Def0000E9
+S A$ax5042reset$1816 Def0000D6
+S A$ax5042reset$1780 Def0000B2
+S A$ax5042reset$1744 Def00008E
+S A$ax5042reset$1717 Def000084
+S A$ax5042reset$1708 Def000079
+S A$ax5042reset$1681 Def000059
+S A$ax5042reset$1663 Def000046
+S A$ax5042reset$1636 Def00002E
+S A$ax5042reset$1627 Def000026
+S A$ax5042reset$1618 Def00001C
+S A$ax5042reset$1609 Def00000F
+S A$ax5042reset$1844 Def0000EA
+S A$ax5042reset$1835 Def0000E3
+S A$ax5042reset$1826 Def0000DA
+S A$ax5042reset$1817 Def0000D7
+S A$ax5042reset$1808 Def0000CD
+S A$ax5042reset$1763 Def0000A0
+S A$ax5042reset$1754 Def000096
+S A$ax5042reset$1745 Def00008F
+S A$ax5042reset$1691 Def000063
+S A$ax5042reset$1682 Def00005C
+S A$ax5042reset$1664 Def000047
+S A$ax5042reset$1619 Def00001D
+S A$ax5042reset$1845 Def0000EB
+S A$ax5042reset$1827 Def0000DD
+S A$ax5042reset$1773 Def0000AB
+S A$ax5042reset$1764 Def0000A3
+S A$ax5042reset$1692 Def000066
+S A$ax5042reset$1674 Def000051
+S A$ax5042reset$1665 Def00004A
+S A$ax5042reset$1647 Def000035
+S A$ax5042reset$1855 Def0000F2
+S A$ax5042reset$1828 Def0000DF
+S A$ax5042reset$1783 Def0000B4
+S A$ax5042reset$1774 Def0000AD
+S A$ax5042reset$1765 Def0000A5
+S A$ax5042reset$1693 Def000067
+S A$ax5042reset$1675 Def000054
+S A$ax5042reset$1657 Def00003F
+S A$ax5042reset$1648 Def000038
+S A$ax5042reset$1639 Def00002F
+S A$ax5042reset$1838 Def0000E6
+S A$ax5042reset$1829 Def0000E0
+S A$ax5042reset$1793 Def0000BF
+S A$ax5042reset$1784 Def0000B7
+S A$ax5042reset$1757 Def000099
+S A$ax5042reset$1748 Def000092
+S A$ax5042reset$1676 Def000056
+S A$ax5042reset$1658 Def000042
+S A$ax5042reset$1595 Def000000
+S A$ax5042reset$1848 Def0000ED
+S A$ax5042reset$1794 Def0000C2
+S A$ax5042reset$1785 Def0000B9
+S A$ax5042reset$1758 Def00009C
+S A$ax5042reset$1686 Def00005E
+S A$ax5042reset$1659 Def000044
+S A$ax5042reset$1777 Def0000AE
+S A$ax5042reset$1768 Def0000A6
+S A$ax5042reset$1759 Def00009E
+S A$ax5042reset$1696 Def000068
+S A$ax5042reset$1687 Def000061
+S A$ax5042reset$1669 Def00004C
+S A$ax5042reset$1778 Def0000B0
+S A$ax5042reset$1769 Def0000A8
+S A$ax5042reset$1697 Def00006B
+S A$ax5042reset$1679 Def000057
+S A$ax5042reset$1598 Def000003
+S A$ax5042reset$1788 Def0000BA
+S A$ax5042reset$1779 Def0000B1
+S A$ax5042reset$1698 Def00006D
+S A$ax5042reset$1798 Def0000C4
+S A$ax5042reset$1789 Def0000BD
+S A$ax5042reset$1799 Def0000C7
+S C$ax5042reset.c$20$1$66 Def00000F
+S C$ax5042reset.c$12$1$66 Def000000
+S C$ax5042reset.c$22$1$66 Def000015
+S C$ax5042reset.c$13$1$66 Def000003
+S C$ax5042reset.c$23$1$66 Def00001E
+S C$ax5042reset.c$60$1$66 Def00006E
+S C$ax5042reset.c$51$1$66 Def00003F
+S C$ax5042reset.c$42$1$66 Def00002F
+S C$ax5042reset.c$61$1$66 Def000074
+S C$ax5042reset.c$52$1$66 Def000045
+S C$ax5042reset.c$43$1$66 Def000033
+S C$ax5042reset.c$62$1$66 Def00007A
+S C$ax5042reset.c$53$1$66 Def00004C
+S C$ax5042reset.c$35$1$66 Def000027
+S C$ax5042reset.c$17$1$66 Def000006
+S C$ax5042reset.c$63$1$66 Def000081
+S C$ax5042reset.c$54$1$66 Def000051
+S C$ax5042reset.c$36$1$66 Def00002D
+S C$ax5042reset.c$80$1$68 Def0000B4
+S C$ax5042reset.c$71$1$68 Def00008A
+S C$ax5042reset.c$64$1$66 Def000086
+S C$ax5042reset.c$55$1$66 Def000057
+S C$ax5042reset.c$19$1$66 Def00000C
+S C$ax5042reset.c$81$1$68 Def0000BA
+S C$ax5042reset.c$72$1$68 Def000092
+S C$ax5042reset.c$65$1$66 Def000089
+S C$ax5042reset.c$56$1$66 Def00005E
+S C$ax5042reset.c$73$1$68 Def000094
+S C$ax5042reset.c$48$1$66 Def000035
+S C$ax5042reset.c$90$2$69 Def0000D8
+S C$ax5042reset.c$74$1$68 Def000096
+S C$ax5042reset.c$58$1$66 Def000063
+S C$ax5042reset.c$49$1$66 Def00003A
+S C$ax5042reset.c$82$2$69 Def0000BF
+S C$ax5042reset.c$75$1$68 Def000099
+S C$ax5042reset.c$68$1$66 Def00008A
+S C$ax5042reset.c$59$1$66 Def000068
+S C$ax5042reset.c$92$2$69 Def0000DA
+S C$ax5042reset.c$83$2$69 Def0000C4
+S C$ax5042reset.c$76$1$68 Def0000A0
+S C$ax5042reset.c$95$1$68 Def0000E6
+S C$ax5042reset.c$93$2$69 Def0000E1
+S C$ax5042reset.c$84$2$69 Def0000CD
+S C$ax5042reset.c$77$1$68 Def0000A6
+S C$ax5042reset.c$96$1$68 Def0000E8
+S C$ax5042reset.c$94$2$69 Def0000E3
+S C$ax5042reset.c$78$1$68 Def0000AB
+S G$ax5042_reset$0$0 Def000000
+S C$ax5042reset.c$97$1$68 Def0000ED
+S C$ax5042reset.c$86$2$69 Def0000CD
+S C$ax5042reset.c$79$1$68 Def0000AE
+S G$ax5042_probeirq$0$0 Def00008A
+S C$ax5042reset.c$98$1$68 Def0000EF
+S C$ax5042reset.c$87$2$69 Def0000CF
+S C$ax5042reset.c$99$1$68 Def0000F2
+S C$ax5042reset.c$88$2$69 Def0000D8
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 40 00 E0 E0
+R 00 00 00 16
+T 00 00 34 FF BF 02 02 80 05
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A 75 82 01 80 4A
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 4C
+R 00 00 00 16
+T 00 00 4C 75 82 02 80 38
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 5E
+R 00 00 00 16
+T 00 00 5E 75 82 02 80 26
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 90 40 08 E4 F0 90 40 39 74 0E F0 90
+R 00 00 00 16
+T 00 00 6F 40 74 74 01 F0 90 40 7D 74 35 F0 12
+R 00 00 00 16
+T 00 00 7B 00 8A E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 03 00 16
+T 00 00 86
+R 00 00 00 16
+T 00 00 86 75 82 00
+R 00 00 00 16
+T 00 00 89
+R 00 00 00 16
+T 00 00 89 22
+R 00 00 00 16
+T 00 00 8A
+R 00 00 00 16
+T 00 00 8A 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 97 8C EB 90 40 0C 74 D0 4F F0 90 40 0D 74
+R 00 00 00 16
+T 00 00 A4 E2 F0 74 60 55 8D FD 74 E0 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 B1 FC 52 05 90 40 0D 74 C0 F0 BD 20 02 80
+R 00 00 00 16
+T 00 00 BE 05
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 C4
+R 00 00 00 16
+T 00 00 C4 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 CF
+R 00 00 00 16
+T 00 00 CF 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 DA
+R 00 00 00 16
+T 00 00 DA 90 40 0C 74 F0 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 E7 0A
+R 00 00 00 16
+T 00 00 E8
+R 00 00 00 16
+T 00 00 E8 ED F4 FD 52 8C 8E A8 75 82 00
+R 00 00 00 16
+T 00 00 F2
+R 00 00 00 16
+T 00 00 F2 22
+R 00 00 00 16
+
+
+M:ax5042reset
+F:G$ax5042_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5042reset.ax5042_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5042_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5042reset.ax5042_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5042reset.ax5042_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5042reset.ax5042_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$NVDATA$0$0({2}SI:U),I,0,0
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+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
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+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
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+S:G$SPSHREG$0$0({1}SC:U),I,0,0
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+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
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+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
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+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
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+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
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+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
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+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
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+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
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+S:G$F1$0$0({1}SX:U),J,0,0
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+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
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+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042deepsleep
+
+XH3
+H 1A areas 3DD global symbols
+M ax5042deepsleep
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5042deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
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+S:G$RADIODATA$0$0({4}SL:U),I,0,0
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+S:G$PINA_7$0$0({1}SX:U),J,0,0
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+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042rclkena
+
+;!FILE libmflarge/ax5042rclkena.asm
+XH3
+H 1A areas 40D global symbols
+M ax5042rclkena
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 39 flags 20 addr 0
+S G$ax5042_rclk_enable$0$0 Def000000
+S _ax5042_rclk_enable Def000000
+S A$ax5042rclkena$1620 Def000017
+S A$ax5042rclkena$1611 Def00000D
+S A$ax5042rclkena$1602 Def000007
+S A$ax5042rclkena$1621 Def000018
+S A$ax5042rclkena$1612 Def00000F
+S A$ax5042rclkena$1622 Def000019
+S A$ax5042rclkena$1613 Def000011
+S A$ax5042rclkena$1650 Def000036
+S A$ax5042rclkena$1632 Def000025
+S A$ax5042rclkena$1623 Def00001C
+S A$ax5042rclkena$1633 Def000028
+S A$ax5042rclkena$1624 Def00001F
+S A$ax5042rclkena$1606 Def000009
+S A$ax5042rclkena$1643 Def000030
+S A$ax5042rclkena$1625 Def000020
+S A$ax5042rclkena$1616 Def000012
+S A$ax5042rclkena$1607 Def00000A
+S A$ax5042rclkena$1653 Def000038
+S A$ax5042rclkena$1644 Def000033
+S A$ax5042rclkena$1626 Def000021
+S A$ax5042rclkena$1608 Def00000C
+S A$ax5042rclkena$1645 Def000034
+S A$ax5042rclkena$1636 Def000029
+S A$ax5042rclkena$1637 Def00002A
+S A$ax5042rclkena$1619 Def000014
+S A$ax5042rclkena$1638 Def00002C
+S A$ax5042rclkena$1629 Def000022
+S A$ax5042rclkena$1639 Def00002E
+S A$ax5042rclkena$1594 Def000000
+S XG$ax5042_rclk_enable$0$0 Def000038
+S A$ax5042rclkena$1649 Def000035
+S A$ax5042rclkena$1597 Def000002
+S C$ax5042rclkena.c$10$1$64 Def000009
+S A$ax5042rclkena$1599 Def000005
+S C$ax5042rclkena.c$11$1$64 Def00000D
+S C$ax5042rclkena.c$12$1$64 Def000012
+S C$ax5042rclkena.c$13$1$64 Def000014
+S C$ax5042rclkena.c$14$1$64 Def000022
+S C$ax5042rclkena.c$15$1$64 Def000025
+S C$ax5042rclkena.c$16$1$64 Def000029
+S C$ax5042rclkena.c$17$1$64 Def000030
+S C$ax5042rclkena.c$18$1$64 Def000035
+S C$ax5042rclkena.c$19$1$64 Def000038
+S C$ax5042rclkena.c$8$1$64 Def000002
+S C$ax5042rclkena.c$9$1$64 Def000007
+S C$ax5042rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 05
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 90 40 70 E4 F0
+R 00 00 00 16
+T 00 00 35
+R 00 00 00 16
+T 00 00 35 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5042rclkena
+F:G$ax5042_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5042rclkena.ax5042_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5042rclkena.ax5042_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5042rclkena.ax5042_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
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+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
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+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
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+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
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+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
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+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
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+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
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+S:G$ADCCONV$0$0({1}SC:U),I,0,0
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+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
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+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
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+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
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+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
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+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
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+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5042rclkdis
+
+;!FILE libmflarge/ax5042rclkdis.asm
+XH3
+H 1A areas 402 global symbols
+M ax5042rclkdis
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2A flags 20 addr 0
+S _ax5042_rclk_disable Def000000
+S C$ax5042rclkdis.c$8$1$64 Def000000
+S C$ax5042rclkdis.c$9$1$64 Def000005
+S C$ax5042rclkdis.c$5$0$0 Def000000
+S XG$ax5042_rclk_disable$0$0 Def000029
+S A$ax5042rclkdis$1600 Def000005
+S A$ax5042rclkdis$1610 Def000011
+S A$ax5042rclkdis$1620 Def00001A
+S A$ax5042rclkdis$1611 Def000012
+S A$ax5042rclkdis$1621 Def00001C
+S A$ax5042rclkdis$1612 Def000014
+S A$ax5042rclkdis$1603 Def000007
+S A$ax5042rclkdis$1622 Def00001E
+S A$ax5042rclkdis$1632 Def000026
+S A$ax5042rclkdis$1633 Def000027
+S A$ax5042rclkdis$1615 Def000015
+S A$ax5042rclkdis$1606 Def00000A
+S A$ax5042rclkdis$1616 Def000018
+S A$ax5042rclkdis$1607 Def00000D
+S A$ax5042rclkdis$1626 Def000020
+S A$ax5042rclkdis$1608 Def00000E
+S A$ax5042rclkdis$1636 Def000029
+S A$ax5042rclkdis$1627 Def000023
+S A$ax5042rclkdis$1609 Def00000F
+S A$ax5042rclkdis$1628 Def000025
+S A$ax5042rclkdis$1619 Def000019
+S A$ax5042rclkdis$1595 Def000000
+S A$ax5042rclkdis$1596 Def000002
+S A$ax5042rclkdis$1597 Def000004
+S C$ax5042rclkdis.c$10$1$64 Def000007
+S C$ax5042rclkdis.c$11$1$64 Def00000A
+S C$ax5042rclkdis.c$12$1$64 Def000015
+S C$ax5042rclkdis.c$13$1$64 Def000019
+S C$ax5042rclkdis.c$14$1$64 Def000020
+S C$ax5042rclkdis.c$15$1$64 Def000026
+S G$ax5042_rclk_disable$0$0 Def000000
+S C$ax5042rclkdis.c$16$1$64 Def000029
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 54 2F 60 02 80 06
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 90 40 70 74 80 F0
+R 00 00 00 16
+T 00 00 26
+R 00 00 00 16
+T 00 00 26 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5042rclkdis
+F:G$ax5042_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5042rclkdis.ax5042_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5042rclkdis.ax5042_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5042rdfifo
+
+;!FILE libmflarge/ax5042rdfifo.asm
+XH3
+H 1A areas 415 global symbols
+M ax5042rdfifo
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5042_PLLVCOINB$0$0 Def005072
+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S C$ax5042rdfifo.c$10$0$0 Def000000
+S C$ax5042rdfifo.c$74$1$66 Def000000
+S C$ax5042rdfifo.c$75$1$66 Def000054
+S G$ax5042_readfifo$0$0 Def000000
+S _ax5042_readfifo Def000000
+S XG$ax5042_readfifo$0$0 Def000054
+S A$ax5042rdfifo$1610 Def00001E
+S A$ax5042rdfifo$1601 Def000017
+S A$ax5042rdfifo$1620 Def00002C
+S A$ax5042rdfifo$1611 Def00001F
+S A$ax5042rdfifo$1602 Def000018
+S A$ax5042rdfifo$1630 Def00003B
+S A$ax5042rdfifo$1621 Def00002F
+S A$ax5042rdfifo$1612 Def000020
+S A$ax5042rdfifo$1603 Def000019
+S A$ax5042rdfifo$1640 Def00004A
+S A$ax5042rdfifo$1613 Def000022
+S A$ax5042rdfifo$1604 Def00001A
+S A$ax5042rdfifo$1632 Def00003C
+S A$ax5042rdfifo$1623 Def000031
+S A$ax5042rdfifo$1642 Def00004B
+S A$ax5042rdfifo$1633 Def00003E
+S A$ax5042rdfifo$1624 Def000032
+S A$ax5042rdfifo$1615 Def000023
+S A$ax5042rdfifo$1606 Def00001C
+S A$ax5042rdfifo$1643 Def00004C
+S A$ax5042rdfifo$1634 Def000040
+S A$ax5042rdfifo$1625 Def000033
+S A$ax5042rdfifo$1616 Def000025
+S A$ax5042rdfifo$1644 Def00004E
+S A$ax5042rdfifo$1635 Def000041
+S A$ax5042rdfifo$1626 Def000034
+S A$ax5042rdfifo$1617 Def000027
+S A$ax5042rdfifo$1590 Def000002
+S A$ax5042rdfifo$1645 Def000050
+S A$ax5042rdfifo$1636 Def000043
+S A$ax5042rdfifo$1627 Def000036
+S A$ax5042rdfifo$1618 Def000028
+S A$ax5042rdfifo$1609 Def00001D
+S A$ax5042rdfifo$1591 Def000004
+S A$ax5042rdfifo$1646 Def000051
+S A$ax5042rdfifo$1637 Def000045
+S A$ax5042rdfifo$1628 Def000038
+S A$ax5042rdfifo$1619 Def00002A
+S A$ax5042rdfifo$1592 Def000005
+S A$ax5042rdfifo$1647 Def000053
+S A$ax5042rdfifo$1638 Def000048
+S A$ax5042rdfifo$1629 Def000039
+S A$ax5042rdfifo$1593 Def000006
+S A$ax5042rdfifo$1594 Def000008
+S A$ax5042rdfifo$1595 Def000009
+S A$ax5042rdfifo$1596 Def00000C
+S A$ax5042rdfifo$1597 Def00000F
+S A$ax5042rdfifo$1598 Def000011
+S A$ax5042rdfifo$1589 Def000000
+S A$ax5042rdfifo$1599 Def000014
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
+T 00 00 0D F6 14 A8 82 90 40 05 20 F5 06
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 E0 F6 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D E0 F2 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 05
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E2 F0 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 05
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E2 A3 DF FC 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5042rdfifo
+F:G$ax5042_readfifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5042rdfifo.ax5042_readfifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5042rdfifo.ax5042_readfifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042wrfifo
+
+;!FILE libmflarge/ax5042wrfifo.asm
+XH3
+H 1A areas 417 global symbols
+M ax5042wrfifo
+O -mmcs51 --model-large
+S G$AX5042_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5042_FREQ0 Def004023
+S _AX5042_PWRMODE Def004002
+S _AX5042_XTALOSC Def004003
+S _AX5042_FECNB Def005018
+S _AX5042_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5042_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5042_FREQ1 Def004022
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5042_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5042_FREQ2 Def004021
+S _AX5042_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5042_REFNB$0$0 Def00507C
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5042_DATARATELO Def004041
+S _AX5042_FREQ3 Def004020
+S _AX5042_FREQUENCYGAINNB Def005045
+S _AX5042_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5042_XTALOSCNB$0$0 Def005003
+S G$AX5042_PWRMODENB$0$0 Def005002
+S G$AX5042_FREQ0NB$0$0 Def005023
+S G$AX5042_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5042_PLLLOOP Def00402C
+S _AX5042_AGCTARGETNB Def005039
+S _AX5042_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5042_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5042_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5042_FREQ2NB$0$0 Def005021
+S G$AX5042_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5042_FREQ3NB$0$0 Def005020
+S G$AX5042_DATARATELONB$0$0 Def005041
+S G$AX5042_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5042_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5042_TXPWR Def004030
+S _AX5042_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5042_PLLLOOPNB$0$0 Def00502C
+S G$AX5042_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5042_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5042_MODULATORMISCNB$0$0 Def005034
+S G$AX5042_TRKPHASEHI$0$0 Def00404A
+S G$AX5042_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5042_TRKAMPLITUDEHI Def004048
+S _AX5042_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5042_IFMODE$0$0 Def004008
+S G$AX5042_FSKDEV1$0$0 Def004026
+S G$AX5042_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5042_PINCFG1 Def00400C
+S _AX5042_IFFREQLONB Def005029
+S _AX5042_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5042_TXPWRNB$0$0 Def005030
+S G$AX5042_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5042_IRQINVERSION Def00400F
+S _AX5042_PINCFG2 Def00400D
+S _AX5042_PLLRNGCLK Def00402E
+S _AX5042_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5042_CICDECLO$0$0 Def00403F
+S G$AX5042_APEOVERRIDE$0$0 Def004070
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5042_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5042_TRKAMPLITUDEHINB$0$0 Def005048
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5042_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5042_PINCFG1NB$0$0 Def00500C
+S G$AX5042_TXDSPMODE$0$0 Def00400A
+S G$AX5042_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5042_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5042_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5042_PINCFG2NB$0$0 Def00500D
+S G$AX5042_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5042_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5042_PINCFG3NB$0$0 Def00500E
+S G$AX5042_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5042_PLLRANGING Def00402D
+S _AX5042_FREQ0NB Def005023
+S _AX5042_PWRMODENB Def005002
+S _AX5042_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5042_AGCCOUNTERNB$0$0 Def00503C
+S G$AX5042_PLLRNGMISC$0$0 Def004074
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5042_FREQ1NB Def005022
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5042_CICDECHINB$0$0 Def00503E
+S G$AX5042_MODULATION$0$0 Def004010
+S G$AX5042_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5042_TRKFREQHI Def00404C
+S _AX5042_FREQ2NB Def005021
+S _EIP_6 Def0000B6
+S G$AX5042_TRKPHASELO$0$0 Def00404B
+S G$AX5042_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5042_AGCDECAY Def00403B
+S _AX5042_TRKAMPLITUDELO Def004049
+S _AX5042_DATARATELONB Def005041
+S _AX5042_FREQ3NB Def005020
+S _EIP_7 Def0000B7
+S G$AX5042_PLLRANGINGNB$0$0 Def00502D
+S G$AX5042_FIFODATA$0$0 Def004005
+S G$AX5042_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5042_FECSTATUS Def00401A
+S _AX5042_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5042_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5042_FSKDEV0 Def004027
+S _AX5042_TRKPHASEHI Def00404A
+S _AX5042_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5042_TRKFREQHINB$0$0 Def00504C
+S G$AX5042_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5042_ADCMISC Def004038
+S _AX5042_FSKDEV1 Def004026
+S _AX5042_IFMODE Def004008
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5042_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5042_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5042_FSKDEV2 Def004025
+S _AX5042_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5042_FECSTATUSNB$0$0 Def00501A
+S G$AX5042_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5042_APEOVERRIDE Def004070
+S _AX5042_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5042_TRKPHASEHINB$0$0 Def00504A
+S G$AX5042_FSKDEV0NB$0$0 Def005027
+S G$AX5042_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5042_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5042_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5042_IFMODENB$0$0 Def005008
+S G$AX5042_FSKDEV1NB$0$0 Def005026
+S G$AX5042_ADCMISCNB$0$0 Def005038
+S G$AX5042_FRAMING$0$0 Def004012
+S G$AX5042_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5042_TIMINGGAINHI Def004042
+S _AX5042_TXDSPMODE Def00400A
+S _AX5042_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5042_FSKDEV2NB$0$0 Def005025
+S G$AX5042_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5042_IRQINVERSIONNB Def00500F
+S _AX5042_PINCFG2NB Def00500D
+S _AX5042_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5042_CICDECLONB$0$0 Def00503F
+S G$AX5042_APEOVERRIDENB$0$0 Def005070
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5042_TRKFREQLO Def00404D
+S _AX5042_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5042_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5042_PLLRNGMISC Def004074
+S _AX5042_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5042_TXDSPMODENB$0$0 Def00500A
+S G$AX5042_TIMINGGAINHINB$0$0 Def005042
+S G$AX5042_TXBITRATEHI$0$0 Def004031
+S G$AX5042_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5042_CRCINIT0 Def004017
+S _AX5042_MODULATION Def004010
+S _AX5042_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5042_CRCINIT1 Def004016
+S _AX5042_TRKPHASELO Def00404B
+S _PINC_7 Def0000FF
+S G$AX5042_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5042_CRCINIT2 Def004015
+S _AX5042_FIFODATA Def004005
+S _AX5042_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5042_PLLRNGMISCNB$0$0 Def005074
+S G$AX5042_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5042_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5042_MODULATIONNB$0$0 Def005010
+S G$AX5042_CRCINIT0NB$0$0 Def005017
+S G$AX5042_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5042_SILICONREVISION Def004000
+S _AX5042_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5042_TRKPHASELONB$0$0 Def00504B
+S G$AX5042_CRCINIT1NB$0$0 Def005016
+S G$AX5042_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5042_AGCDECAYNB Def00503B
+S _AX5042_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5042_FIFODATANB$0$0 Def005005
+S G$AX5042_CRCINIT2NB$0$0 Def005015
+S G$AX5042_IFFREQHI$0$0 Def004028
+S G$AX5042_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5042_TIMINGGAINLO Def004043
+S _AX5042_FECSTATUSNB Def00501A
+S _E2IE Def0000A0
+S G$AX5042_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5042_AGCATTACK Def00403A
+S _AX5042_FREQUENCYGAIN2 Def004046
+S _AX5042_FSKDEV0NB Def005027
+S _AX5042_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5042_SILICONREVISIONNB$0$0 Def005000
+S G$AX5042_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5042_AMPLITUDEGAIN Def004047
+S _AX5042_FRAMING Def004012
+S _AX5042_ADCMISCNB Def005038
+S _AX5042_FSKDEV1NB Def005026
+S _AX5042_IFMODENB Def005008
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5042_TXBITRATEMID$0$0 Def004032
+S G$AX5042_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5042_FIFOCONTROL Def004004
+S _AX5042_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5042_TIMINGGAINLONB$0$0 Def005043
+S G$AX5042_TXBITRATELO$0$0 Def004033
+S G$AX5042_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5042_APEOVERRIDENB Def005070
+S _AX5042_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5042_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5042_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5042_ENCODING Def004011
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5042_FRAMINGNB$0$0 Def005012
+S G$AX5042_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5042_SCRATCH Def004001
+S _AX5042_TXBITRATEHI Def004031
+S _AX5042_TIMINGGAINHINB Def005042
+S _AX5042_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5042_FIFOCONTROLNB$0$0 Def005004
+S G$AX5042_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5042_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5042_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5042_ENCODINGNB$0$0 Def005011
+S G$AX5042_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5042_FECSYNC Def004019
+S _AX5042_PLLRNGMISCNB Def005074
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5042_TXBITRATEHINB$0$0 Def005031
+S G$AX5042_SCRATCHNB$0$0 Def005001
+S G$AX5042_IRQMASK$0$0 Def004006
+S G$AX5042_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5042_DSPMODE Def004009
+S _AX5042_CRCINIT0NB Def005017
+S _AX5042_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5042_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5042_CICSHIFT Def00403D
+S _AX5042_CRCINIT1NB Def005016
+S _AX5042_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5042_FEC Def004018
+S _AX5042_IFFREQHI Def004028
+S _AX5042_CRCINIT2NB Def005015
+S _AX5042_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5042_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5042_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5042_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5042_PHASEGAIN Def004044
+S _AX5042_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5042_CICSHIFTNB$0$0 Def00503D
+S G$AX5042_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5042_FREQUENCYGAIN Def004045
+S _AX5042_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5042_IFFREQHINB$0$0 Def005028
+S G$AX5042_FECNB$0$0 Def005018
+S G$AX5042_XTALOSC$0$0 Def004003
+S G$AX5042_PWRMODE$0$0 Def004002
+S G$AX5042_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5042_AGCTARGET Def004039
+S _AX5042_TXBITRATELO Def004033
+S _AX5042_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5042_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5042_AGCATTACKNB Def00503A
+S _AX5042_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5042_PHASEGAINNB$0$0 Def005044
+S G$AX5042_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5042_AMPLITUDEGAINNB Def005047
+S _AX5042_FRAMINGNB Def005012
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5042_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5042_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5042_FREQ3$0$0 Def004020
+S G$AX5042_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5042_IRQREQUEST Def004007
+S _AX5042_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5042_TXBITRATELONB$0$0 Def005033
+S G$AX5042_AGCTARGETNB$0$0 Def005039
+S G$AX5042_PLLLOOP$0$0 Def00402C
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5042_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5042_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5042_DATARATEHI Def004040
+S _AX5042_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5042_IFFREQLO Def004029
+S _AX5042_IRQMASK Def004006
+S _AX5042_SCRATCHNB Def005001
+S _AX5042_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5042_IRQREQUESTNB$0$0 Def005007
+S G$AX5042_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5042_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5042_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
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+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
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+S G$AX5042_DATARATEHINB$0$0 Def005040
+S G$AX5042_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
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+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5042_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5042_IRQMASKNB$0$0 Def005006
+S G$AX5042_IFFREQLONB$0$0 Def005029
+S G$AX5042_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
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+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5042_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
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+S G$AX5042_PLLRNGCLK$0$0 Def00402E
+S G$AX5042_PINCFG2$0$0 Def00400D
+S G$AX5042_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
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+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5042_REF Def00407C
+S _AX5042_CICSHIFTNB Def00503D
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
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+A GSINIT5 size 0 flags 20 addr 0
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+S A$ax5042wrfifo$1620 Def00002C
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+S A$ax5042wrfifo$1602 Def000018
+S A$ax5042wrfifo$1630 Def00003B
+S A$ax5042wrfifo$1621 Def00002F
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+S A$ax5042wrfifo$1603 Def000019
+S A$ax5042wrfifo$1640 Def00004A
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+S A$ax5042wrfifo$1628 Def000038
+S A$ax5042wrfifo$1619 Def00002A
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+S A$ax5042wrfifo$1593 Def000006
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+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDE$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_REF$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5042_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_APEOVERRIDENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLRNGMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5042_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5042_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5042regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5042regs
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5042regs
+
+
+
+
+ax5043comminit
+
+;!FILE libmflarge/ax5043comminit.asm
+XH3
+H 1A areas 861 global symbols
+M ax5043comminit
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
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+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
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+S C$ax5043comminit.c$8$0$0 Def000000
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+S A$ax5043comminit$3300 Def00001E
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+S A$ax5043comminit$3294 Def000017
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+S A$ax5043comminit$3298 Def00001B
+S A$ax5043comminit$3289 Def00000F
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+S C$ax5043comminit.c$10$1$66 Def000000
+S C$ax5043comminit.c$11$1$66 Def000003
+S C$ax5043comminit.c$12$1$66 Def000006
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+S C$ax5043comminit.c$15$1$66 Def00000F
+S C$ax5043comminit.c$16$1$66 Def000018
+S G$ax5043_comminit$0$0 Def000000
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+
+
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+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSEL$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXAGC$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXCOARSEAGC$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSI$0$0({1}SC:U),F,0,0
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+S:G$AX5043_WAKEUPXOEARLY$0$0({1}SC:U),F,0,0
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+S:G$AX5043_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043commslpexit
+
+;!FILE libmflarge/ax5043commslpexit.asm
+XH3
+H 1A areas 863 global symbols
+M ax5043commslpexit
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S _ax5043_probeirq Ref000000
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5043commslpexit.c$24$1$66 Def000024
+S C$ax5043commslpexit.c$15$1$66 Def000012
+S C$ax5043commslpexit.c$25$1$66 Def000027
+S C$ax5043commslpexit.c$16$1$66 Def00001B
+S C$ax5043commslpexit.c$8$0$0 Def000000
+S G$ax5043_commsleepexit$0$0 Def000000
+S _ax5043_commsleepexit Def000000
+S A$ax5043commslpexit$3301 Def00001B
+S A$ax5043commslpexit$3302 Def00001E
+S A$ax5043commslpexit$3312 Def000027
+S A$ax5043commslpexit$3303 Def000020
+S A$ax5043commslpexit$3304 Def000021
+S A$ax5043commslpexit$3305 Def000022
+S XG$ax5043_commsleepexit$0$0 Def000027
+S A$ax5043commslpexit$3306 Def000023
+S A$ax5043commslpexit$3290 Def00000F
+S A$ax5043commslpexit$3309 Def000024
+S A$ax5043commslpexit$3282 Def000006
+S A$ax5043commslpexit$3283 Def000009
+S A$ax5043commslpexit$3293 Def000012
+S A$ax5043commslpexit$3284 Def00000A
+S A$ax5043commslpexit$3294 Def000015
+S A$ax5043commslpexit$3285 Def00000B
+S A$ax5043commslpexit$3276 Def000000
+S A$ax5043commslpexit$3295 Def000017
+S A$ax5043commslpexit$3286 Def00000D
+S A$ax5043commslpexit$3296 Def000018
+S A$ax5043commslpexit$3287 Def00000E
+S A$ax5043commslpexit$3297 Def000019
+S A$ax5043commslpexit$3279 Def000003
+S A$ax5043commslpexit$3298 Def00001A
+S C$ax5043commslpexit.c$10$1$66 Def000000
+S C$ax5043commslpexit.c$11$1$66 Def000003
+S C$ax5043commslpexit.c$12$1$66 Def000006
+S C$ax5043commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
+R 00 00 00 16
+T 00 00 0D 4F F0 75 B1 0C 90 70 40 74 29 F0 E4 A3
+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 28 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 EF
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5043commslpexit
+F:G$ax5043_commsleepexit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIOD$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAX$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGF$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGP$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSEL$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQ$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOST$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGA$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMP$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATE$0$0({1}SC:U),F,0,0
+S:G$AX5043_REF$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHR$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043reset
+
+;!FILE libmflarge/ax5043reset.asm
+XH3
+H 1A areas 8ED global symbols
+M ax5043reset
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$RADIODRV$0$0 Def007045
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S _delay Ref000000
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _radio_wakeup_deepsleep_core Ref000000
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIODRV Def007045
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size D7 flags 20 addr 0
+S C$ax5043reset.c$8$0$0 Def000000
+S _ax5043_reset Def000000
+S _ax5043_probeirq Def00007C
+S XG$ax5043_reset$0$0 Def00007B
+S XG$ax5043_probeirq$0$0 Def0000D6
+S A$ax5043reset$3400 Def00007B
+S A$ax5043reset$3310 Def00001E
+S A$ax5043reset$3311 Def000021
+S A$ax5043reset$3302 Def000015
+S A$ax5043reset$3330 Def000032
+S A$ax5043reset$3321 Def00002A
+S A$ax5043reset$3312 Def000023
+S A$ax5043reset$3303 Def000018
+S A$ax5043reset$3502 Def0000CA
+S A$ax5043reset$3430 Def00008B
+S A$ax5043reset$3331 Def000035
+S A$ax5043reset$3322 Def00002D
+S A$ax5043reset$3313 Def000024
+S A$ax5043reset$3304 Def00001A
+S A$ax5043reset$3512 Def0000D1
+S A$ax5043reset$3422 Def000080
+S A$ax5043reset$3323 Def00002F
+S A$ax5043reset$3314 Def000025
+S A$ax5043reset$3305 Def00001B
+S A$ax5043reset$3450 Def00009E
+S A$ax5043reset$3360 Def000053
+S A$ax5043reset$3342 Def00003E
+S A$ax5043reset$3315 Def000026
+S A$ax5043reset$3306 Def00001C
+S A$ax5043reset$3442 Def000093
+S A$ax5043reset$3433 Def00008C
+S A$ax5043reset$3370 Def00005D
+S A$ax5043reset$3352 Def000048
+S A$ax5043reset$3343 Def000041
+S A$ax5043reset$3334 Def000038
+S A$ax5043reset$3307 Def00001D
+S A$ax5043reset$3515 Def0000D3
+S A$ax5043reset$3506 Def0000CC
+S A$ax5043reset$3443 Def000095
+S A$ax5043reset$3434 Def00008E
+S A$ax5043reset$3425 Def000083
+S A$ax5043reset$3416 Def00007C
+S A$ax5043reset$3371 Def00005F
+S A$ax5043reset$3353 Def00004B
+S A$ax5043reset$3335 Def00003B
+S A$ax5043reset$3326 Def000030
+S A$ax5043reset$3290 Def000009
+S A$ax5043reset$3507 Def0000CD
+S A$ax5043reset$3480 Def0000B9
+S A$ax5043reset$3453 Def00009F
+S A$ax5043reset$3444 Def000096
+S A$ax5043reset$3435 Def000090
+S A$ax5043reset$3381 Def000067
+S A$ax5043reset$3354 Def00004D
+S A$ax5043reset$3327 Def000031
+S A$ax5043reset$3318 Def000027
+S A$ax5043reset$3291 Def00000B
+S A$ax5043reset$3508 Def0000CE
+S A$ax5043reset$3481 Def0000BB
+S A$ax5043reset$3463 Def0000A9
+S A$ax5043reset$3454 Def0000A2
+S A$ax5043reset$3445 Def000097
+S A$ax5043reset$3391 Def000073
+S A$ax5043reset$3382 Def00006A
+S A$ax5043reset$3364 Def000055
+S A$ax5043reset$3283 Def000000
+S A$ax5043reset$3509 Def0000CF
+S A$ax5043reset$3491 Def0000BF
+S A$ax5043reset$3482 Def0000BC
+S A$ax5043reset$3473 Def0000B2
+S A$ax5043reset$3464 Def0000AC
+S A$ax5043reset$3428 Def000086
+S A$ax5043reset$3419 Def00007E
+S A$ax5043reset$3392 Def000076
+S A$ax5043reset$3374 Def000060
+S A$ax5043reset$3365 Def000058
+S A$ax5043reset$3347 Def000043
+S A$ax5043reset$3338 Def00003C
+S A$ax5043reset$3519 Def0000D6
+S A$ax5043reset$3492 Def0000C2
+S A$ax5043reset$3465 Def0000AD
+S A$ax5043reset$3438 Def000091
+S A$ax5043reset$3429 Def000089
+S A$ax5043reset$3375 Def000061
+S A$ax5043reset$3357 Def00004E
+S A$ax5043reset$3348 Def000046
+S A$ax5043reset$3339 Def00003D
+S A$ax5043reset$3294 Def00000C
+S A$ax5043reset$3493 Def0000C4
+S A$ax5043reset$3466 Def0000AE
+S A$ax5043reset$3448 Def000099
+S A$ax5043reset$3439 Def000092
+S A$ax5043reset$3376 Def000062
+S A$ax5043reset$3358 Def00004F
+S A$ax5043reset$3286 Def000003
+S A$ax5043reset$3467 Def0000B0
+S A$ax5043reset$3458 Def0000A4
+S A$ax5043reset$3449 Def00009C
+S A$ax5043reset$3386 Def00006C
+S A$ax5043reset$3377 Def000065
+S A$ax5043reset$3359 Def000050
+S A$ax5043reset$3477 Def0000B4
+S A$ax5043reset$3468 Def0000B1
+S A$ax5043reset$3459 Def0000A7
+S A$ax5043reset$3396 Def000078
+S A$ax5043reset$3387 Def00006F
+S A$ax5043reset$3369 Def00005A
+S A$ax5043reset$3297 Def00000F
+S A$ax5043reset$3496 Def0000C5
+S A$ax5043reset$3487 Def0000BD
+S A$ax5043reset$3478 Def0000B7
+S A$ax5043reset$3388 Def000071
+S A$ax5043reset$3298 Def000012
+S A$ax5043reset$3289 Def000006
+S A$ax5043reset$3479 Def0000B8
+S A$ax5043reset$3299 Def000014
+S A$ax5043reset$3499 Def0000C7
+S C$ax5043reset.c$20$1$66 Def00000F
+S C$ax5043reset.c$12$1$66 Def000000
+S C$ax5043reset.c$22$1$66 Def000015
+S C$ax5043reset.c$13$1$66 Def000003
+S C$ax5043reset.c$32$1$66 Def000027
+S C$ax5043reset.c$23$1$66 Def00001E
+S C$ax5043reset.c$60$1$66 Def000078
+S C$ax5043reset.c$51$1$66 Def000048
+S C$ax5043reset.c$42$1$66 Def000038
+S C$ax5043reset.c$15$1$66 Def000006
+S C$ax5043reset.c$61$1$66 Def00007B
+S C$ax5043reset.c$52$1$66 Def00004E
+S C$ax5043reset.c$43$1$66 Def00003C
+S C$ax5043reset.c$53$1$66 Def000055
+S C$ax5043reset.c$35$1$66 Def00002A
+S C$ax5043reset.c$70$1$68 Def00007E
+S C$ax5043reset.c$54$1$66 Def00005A
+S C$ax5043reset.c$36$1$66 Def000030
+S C$ax5043reset.c$71$1$68 Def000080
+S C$ax5043reset.c$55$1$66 Def000060
+S C$ax5043reset.c$19$1$66 Def00000C
+S C$ax5043reset.c$72$1$68 Def000083
+S C$ax5043reset.c$56$1$66 Def000067
+S C$ax5043reset.c$80$2$69 Def0000A9
+S C$ax5043reset.c$73$1$68 Def000086
+S C$ax5043reset.c$66$1$66 Def00007C
+S C$ax5043reset.c$48$1$66 Def00003E
+S C$ax5043reset.c$39$1$66 Def000032
+S C$ax5043reset.c$92$1$68 Def0000CA
+S C$ax5043reset.c$90$2$69 Def0000C5
+S C$ax5043reset.c$81$2$69 Def0000B2
+S C$ax5043reset.c$74$1$68 Def00008C
+S C$ax5043reset.c$58$1$66 Def00006C
+S C$ax5043reset.c$49$1$66 Def000043
+S C$ax5043reset.c$93$1$68 Def0000CC
+S C$ax5043reset.c$91$2$69 Def0000C7
+S C$ax5043reset.c$75$1$68 Def000091
+S C$ax5043reset.c$59$1$66 Def000073
+S C$ax5043reset.c$94$1$68 Def0000D1
+S C$ax5043reset.c$83$2$69 Def0000B2
+S C$ax5043reset.c$76$1$68 Def000093
+S C$ax5043reset.c$69$1$66 Def00007C
+S C$ax5043reset.c$95$1$68 Def0000D3
+S C$ax5043reset.c$84$2$69 Def0000B4
+S C$ax5043reset.c$77$1$68 Def000099
+S C$ax5043reset.c$96$1$68 Def0000D6
+S C$ax5043reset.c$85$2$69 Def0000BD
+S C$ax5043reset.c$78$1$68 Def00009F
+S G$ax5043_reset$0$0 Def000000
+S G$ax5043_probeirq$0$0 Def00007C
+S C$ax5043reset.c$87$2$69 Def0000BD
+S C$ax5043reset.c$79$2$69 Def0000A4
+S C$ax5043reset.c$89$2$69 Def0000BF
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
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+R 00 00 00 16 02 04 07 58
+T 00 00 33 00 0A 12 00 00 90 40 00 E0 E0 FF BF 51
+R 00 00 00 16 02 06 05 F3
+T 00 00 40 02 80 05
+R 00 00 00 16
+T 00 00 43
+R 00 00 00 16
+T 00 00 43 75 82 01 80 33
+R 00 00 00 16
+T 00 00 48
+R 00 00 00 16
+T 00 00 48 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 55
+R 00 00 00 16
+T 00 00 55 75 82 02 80 21
+R 00 00 00 16
+T 00 00 5A
+R 00 00 00 16
+T 00 00 5A 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 67
+R 00 00 00 16
+T 00 00 67 75 82 02 80 0F
+R 00 00 00 16
+T 00 00 6C
+R 00 00 00 16
+T 00 00 6C 12 00 7C E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 00 04 00 16
+T 00 00 78
+R 00 00 00 16
+T 00 00 78 75 82 00
+R 00 00 00 16
+T 00 00 7B
+R 00 00 00 16
+T 00 00 7B 22
+R 00 00 00 16
+T 00 00 7C
+R 00 00 00 16
+T 00 00 7C AF A8 C2 AC 53 8C EB 43 8C 2B 90 40 24
+R 00 00 00 16
+T 00 00 89 74 01 F0 74 60 55 8D FE E4 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 96 FD 52 06 90 40 24 74 03 F0 BE 20 02 80
+R 00 00 00 16
+T 00 00 A3 05
+R 00 00 00 16
+T 00 00 A4
+R 00 00 00 16
+T 00 00 A4 BE 40 18 80 0B
+R 00 00 00 16
+T 00 00 A9
+R 00 00 00 16
+T 00 00 A9 90 70 44 E0 FD 74 F7 5D F0 80 18
+R 00 00 00 16
+T 00 00 B4
+R 00 00 00 16
+T 00 00 B4 90 70 44 E0 FD 74 08 4D F0 80 0D
+R 00 00 00 16
+T 00 00 BF
+R 00 00 00 16
+T 00 00 BF 90 40 24 74 02 F0 8F A8 75 82 01 80 0A
+R 00 00 00 16
+T 00 00 CC
+R 00 00 00 16
+T 00 00 CC EE F4 FE 52 8C 8F A8 75 82 00
+R 00 00 00 16
+T 00 00 D6
+R 00 00 00 16
+T 00 00 D6 22
+R 00 00 00 16
+
+
+M:ax5043reset
+F:G$ax5043_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043reset.ax5043_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5043_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043reset.ax5043_probeirq$p$1$68({1}SC:U),R,0,0,[r6]
+S:Lax5043reset.ax5043_probeirq$iesave$1$68({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
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+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043deepsleep
+
+;!FILE libmflarge/ax5043deepsleep.asm
+XH3
+H 1A areas 894 global symbols
+M ax5043deepsleep
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S _ax5043_probeirq Ref000000
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S _radio_wakeup_deepsleep_core Ref000000
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 63 flags 20 addr 0
+S C$ax5043deepsleep.c$21$1$66 Def000019
+S C$ax5043deepsleep.c$12$1$66 Def000000
+S C$ax5043deepsleep.c$22$1$66 Def00001F
+S C$ax5043deepsleep.c$13$1$66 Def000003
+S C$ax5043deepsleep.c$10$0$0 Def000000
+S C$ax5043deepsleep.c$31$1$68 Def00002F
+S C$ax5043deepsleep.c$24$1$66 Def000020
+S C$ax5043deepsleep.c$32$1$68 Def000038
+S C$ax5043deepsleep.c$17$1$66 Def000009
+S C$ax5043deepsleep.c$41$2$69 Def000046
+S C$ax5043deepsleep.c$18$1$66 Def00000E
+S _ax5043_wakeup_deepsleep Def000020
+S C$ax5043deepsleep.c$42$2$69 Def000049
+S C$ax5043deepsleep.c$26$1$68 Def000020
+S C$ax5043deepsleep.c$19$1$66 Def000010
+S C$ax5043deepsleep.c$45$1$68 Def000053
+S C$ax5043deepsleep.c$43$2$69 Def00004F
+S C$ax5043deepsleep.c$27$1$68 Def000023
+S C$ax5043deepsleep.c$46$1$68 Def00005A
+S C$ax5043deepsleep.c$28$1$68 Def000026
+S C$ax5043deepsleep.c$47$1$68 Def00005F
+S C$ax5043deepsleep.c$29$1$68 Def00002C
+S C$ax5043deepsleep.c$48$1$68 Def000062
+S C$ax5043deepsleep.c$39$1$68 Def000041
+S G$ax5043_enter_deepsleep$0$0 Def000000
+S XG$ax5043_wakeup_deepsleep$0$0 Def000062
+S _ax5043_enter_deepsleep Def000000
+S XG$ax5043_enter_deepsleep$0$0 Def00001F
+S A$ax5043deepsleep$3300 Def000018
+S A$ax5043deepsleep$3330 Def000029
+S A$ax5043deepsleep$3303 Def000019
+S A$ax5043deepsleep$3340 Def000035
+S A$ax5043deepsleep$3331 Def00002B
+S A$ax5043deepsleep$3304 Def00001B
+S A$ax5043deepsleep$3350 Def000040
+S A$ax5043deepsleep$3341 Def000036
+S A$ax5043deepsleep$3323 Def000020
+S A$ax5043deepsleep$3305 Def00001D
+S A$ax5043deepsleep$3342 Def000037
+S A$ax5043deepsleep$3361 Def000049
+S A$ax5043deepsleep$3334 Def00002C
+S A$ax5043deepsleep$3362 Def00004B
+S A$ax5043deepsleep$3353 Def000041
+S A$ax5043deepsleep$3326 Def000023
+S A$ax5043deepsleep$3308 Def00001F
+S A$ax5043deepsleep$3281 Def000003
+S A$ax5043deepsleep$3372 Def000053
+S A$ax5043deepsleep$3363 Def00004C
+S A$ax5043deepsleep$3354 Def000044
+S A$ax5043deepsleep$3345 Def000038
+S A$ax5043deepsleep$3291 Def00000E
+S A$ax5043deepsleep$3282 Def000006
+S A$ax5043deepsleep$3382 Def00005F
+S A$ax5043deepsleep$3373 Def000056
+S A$ax5043deepsleep$3364 Def00004D
+S A$ax5043deepsleep$3355 Def000045
+S A$ax5043deepsleep$3346 Def00003B
+S A$ax5043deepsleep$3337 Def00002F
+S A$ax5043deepsleep$3292 Def00000F
+S A$ax5043deepsleep$3283 Def000008
+S A$ax5043deepsleep$3374 Def000058
+S A$ax5043deepsleep$3347 Def00003D
+S A$ax5043deepsleep$3338 Def000032
+S A$ax5043deepsleep$3329 Def000026
+S A$ax5043deepsleep$3348 Def00003E
+S A$ax5043deepsleep$3339 Def000034
+S A$ax5043deepsleep$3367 Def00004F
+S A$ax5043deepsleep$3358 Def000046
+S A$ax5043deepsleep$3349 Def00003F
+S A$ax5043deepsleep$3295 Def000010
+S A$ax5043deepsleep$3286 Def000009
+S A$ax5043deepsleep$3386 Def000062
+S A$ax5043deepsleep$3377 Def00005A
+S A$ax5043deepsleep$3368 Def000051
+S A$ax5043deepsleep$3296 Def000013
+S A$ax5043deepsleep$3287 Def00000C
+S A$ax5043deepsleep$3278 Def000000
+S A$ax5043deepsleep$3378 Def00005D
+S A$ax5043deepsleep$3297 Def000014
+S A$ax5043deepsleep$3288 Def00000D
+S G$ax5043_wakeup_deepsleep$0$0 Def000020
+S A$ax5043deepsleep$3298 Def000015
+S A$ax5043deepsleep$3299 Def000017
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 43 8C 0B 90 40 21 74 01 F0 90 40 02 E4
+R 00 00 00 16
+T 00 00 0D F0 04 F0 90 70 44 E0 FF 74 BF 5F F0 74
+R 00 00 00 16
+T 00 00 1A F7 45 8D 52 8C 22
+R 00 00 00 16
+T 00 00 20
+R 00 00 00 16
+T 00 00 20 75 8E 15 75 8C EB 90 70 44 74 07 F0 75
+R 00 00 00 16
+T 00 00 2D B1 0C 90 70 40 74 29 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 39 70 42 74 28 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 46 12 00 00 E5 82 FF FE 60 04 8E 82 80 0F
+R 00 00 00 16 02 04 07 57
+T 00 00 53
+R 00 00 00 16
+T 00 00 53 12 00 00 E5 82 60 05 75 82 03 80 03
+R 00 00 00 16 02 04 00 EF
+T 00 00 5F
+R 00 00 00 16
+T 00 00 5F 75 82 00
+R 00 00 00 16
+T 00 00 62
+R 00 00 00 16
+T 00 00 62 22
+R 00 00 00 16
+
+
+M:ax5043deepsleep
+F:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),Z,0,0,0,0,0
+F:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5043deepsleep.ax5043_wakeup_deepsleep$i$2$69({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
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+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043rclkena
+
+;!FILE libmflarge/ax5043rclkena.asm
+XH3
+H 1A areas 86C global symbols
+M ax5043rclkena
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 34 flags 20 addr 0
+S G$ax5043_rclk_enable$0$0 Def000000
+S A$ax5043rclkena$3310 Def00001C
+S _ax5043_rclk_enable Def000000
+S A$ax5043rclkena$3311 Def00001F
+S A$ax5043rclkena$3302 Def000014
+S A$ax5043rclkena$3330 Def000031
+S A$ax5043rclkena$3321 Def000027
+S A$ax5043rclkena$3303 Def000017
+S A$ax5043rclkena$3322 Def000029
+S A$ax5043rclkena$3304 Def000018
+S A$ax5043rclkena$3323 Def00002A
+S A$ax5043rclkena$3314 Def000020
+S A$ax5043rclkena$3333 Def000033
+S A$ax5043rclkena$3324 Def00002D
+S A$ax5043rclkena$3315 Def000021
+S A$ax5043rclkena$3325 Def00002F
+S A$ax5043rclkena$3316 Def000023
+S A$ax5043rclkena$3307 Def000019
+S A$ax5043rclkena$3280 Def000002
+S A$ax5043rclkena$3317 Def000025
+S A$ax5043rclkena$3290 Def00000A
+S A$ax5043rclkena$3291 Def00000C
+S A$ax5043rclkena$3282 Def000005
+S A$ax5043rclkena$3329 Def000030
+S A$ax5043rclkena$3294 Def00000D
+S A$ax5043rclkena$3285 Def000007
+S A$ax5043rclkena$3295 Def00000F
+S A$ax5043rclkena$3277 Def000000
+S XG$ax5043_rclk_enable$0$0 Def000033
+S A$ax5043rclkena$3296 Def000011
+S A$ax5043rclkena$3289 Def000009
+S A$ax5043rclkena$3299 Def000012
+S C$ax5043rclkena.c$10$1$64 Def000009
+S C$ax5043rclkena.c$11$1$64 Def00000D
+S C$ax5043rclkena.c$12$1$64 Def000012
+S C$ax5043rclkena.c$13$1$64 Def000014
+S C$ax5043rclkena.c$14$1$64 Def000019
+S C$ax5043rclkena.c$15$1$64 Def00001C
+S C$ax5043rclkena.c$16$1$64 Def000020
+S C$ax5043rclkena.c$17$1$64 Def000027
+S C$ax5043rclkena.c$18$1$64 Def000030
+S C$ax5043rclkena.c$19$1$64 Def000033
+S C$ax5043rclkena.c$8$1$64 Def000002
+S C$ax5043rclkena.c$9$1$64 Def000007
+S C$ax5043rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0A 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0A
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 21 EF F0 53 8C FD 90 40 02 E0 FF 54
+R 00 00 00 16
+T 00 00 22 0F 60 02 80 09
+R 00 00 00 16
+T 00 00 27
+R 00 00 00 16
+T 00 00 27 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rclkena
+F:G$ax5043_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5043rclkena.ax5043_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5043rclkena.ax5043_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5043rclkena.ax5043_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
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+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5043rclkdis
+
+;!FILE libmflarge/ax5043rclkdis.asm
+XH3
+H 1A areas 862 global symbols
+M ax5043rclkdis
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S _ax5043_rclk_disable Def000000
+S C$ax5043rclkdis.c$8$1$64 Def000000
+S C$ax5043rclkdis.c$9$1$64 Def000005
+S C$ax5043rclkdis.c$5$0$0 Def000000
+S XG$ax5043_rclk_disable$0$0 Def000026
+S A$ax5043rclkdis$3300 Def000017
+S A$ax5043rclkdis$3301 Def000018
+S A$ax5043rclkdis$3302 Def000019
+S A$ax5043rclkdis$3312 Def000023
+S A$ax5043rclkdis$3313 Def000024
+S A$ax5043rclkdis$3305 Def00001C
+S A$ax5043rclkdis$3306 Def00001F
+S A$ax5043rclkdis$3316 Def000026
+S A$ax5043rclkdis$3307 Def000021
+S A$ax5043rclkdis$3280 Def000004
+S A$ax5043rclkdis$3308 Def000022
+S A$ax5043rclkdis$3290 Def00000D
+S A$ax5043rclkdis$3291 Def00000F
+S A$ax5043rclkdis$3283 Def000005
+S A$ax5043rclkdis$3294 Def000010
+S A$ax5043rclkdis$3295 Def000013
+S A$ax5043rclkdis$3286 Def000007
+S A$ax5043rclkdis$3296 Def000014
+S A$ax5043rclkdis$3278 Def000000
+S A$ax5043rclkdis$3279 Def000002
+S A$ax5043rclkdis$3289 Def00000A
+S A$ax5043rclkdis$3299 Def000015
+S C$ax5043rclkdis.c$10$1$64 Def000007
+S C$ax5043rclkdis.c$11$1$64 Def00000A
+S C$ax5043rclkdis.c$12$1$64 Def000010
+S C$ax5043rclkdis.c$13$1$64 Def000015
+S C$ax5043rclkdis.c$14$1$64 Def00001C
+S C$ax5043rclkdis.c$15$1$64 Def000023
+S G$ax5043_rclk_disable$0$0 Def000000
+S C$ax5043rclkdis.c$16$1$64 Def000026
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 21
+R 00 00 00 16
+T 00 00 0D 74 01 F0 90 40 02 E0 FE 74 0F 5E FD BD
+R 00 00 00 16
+T 00 00 1A 05 07 90 40 02 74 F0 5E F0
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rclkdis
+F:G$ax5043_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5043rclkdis.ax5043_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5043rclkdis.ax5043_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$XDPTR0$0$0({2}SI:U),F,0,0
+S:G$XDPTR1$0$0({2}SI:U),F,0,0
+S:G$XIE$0$0({1}SC:U),F,0,0
+S:G$XIP$0$0({1}SC:U),F,0,0
+S:G$XPCON$0$0({1}SC:U),F,0,0
+S:G$XADCCH0CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH1CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH2CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
+S:G$XCLKCON$0$0({1}SC:U),F,0,0
+S:G$XCLKSTAT$0$0({1}SC:U),F,0,0
+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKBUF$0$0({1}SC:U),F,0,0
+S:G$XDBGLNKSTAT$0$0({1}SC:U),F,0,0
+S:G$XDIRA$0$0({1}SC:U),F,0,0
+S:G$XDIRB$0$0({1}SC:U),F,0,0
+S:G$XDIRC$0$0({1}SC:U),F,0,0
+S:G$XDIRR$0$0({1}SC:U),F,0,0
+S:G$XPINA$0$0({1}SC:U),F,0,0
+S:G$XPINB$0$0({1}SC:U),F,0,0
+S:G$XPINC$0$0({1}SC:U),F,0,0
+S:G$XPINR$0$0({1}SC:U),F,0,0
+S:G$XPORTA$0$0({1}SC:U),F,0,0
+S:G$XPORTB$0$0({1}SC:U),F,0,0
+S:G$XPORTC$0$0({1}SC:U),F,0,0
+S:G$XPORTR$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC0CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC0MODE$0$0({1}SC:U),F,0,0
+S:G$XIC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT0$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT1$0$0({1}SC:U),F,0,0
+S:G$XIC1CAPT$0$0({2}SI:U),F,0,0
+S:G$XIC1MODE$0$0({1}SC:U),F,0,0
+S:G$XIC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XNVADDR0$0$0({1}SC:U),F,0,0
+S:G$XNVADDR1$0$0({1}SC:U),F,0,0
+S:G$XNVADDR$0$0({2}SI:U),F,0,0
+S:G$XNVDATA0$0$0({1}SC:U),F,0,0
+S:G$XNVDATA1$0$0({1}SC:U),F,0,0
+S:G$XNVDATA$0$0({2}SI:U),F,0,0
+S:G$XNVKEY$0$0({1}SC:U),F,0,0
+S:G$XNVSTATUS$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC0COMP$0$0({2}SI:U),F,0,0
+S:G$XOC0MODE$0$0({1}SC:U),F,0,0
+S:G$XOC0PIN$0$0({1}SC:U),F,0,0
+S:G$XOC0STATUS$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP0$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP1$0$0({1}SC:U),F,0,0
+S:G$XOC1COMP$0$0({2}SI:U),F,0,0
+S:G$XOC1MODE$0$0({1}SC:U),F,0,0
+S:G$XOC1PIN$0$0({1}SC:U),F,0,0
+S:G$XOC1STATUS$0$0({1}SC:U),F,0,0
+S:G$XRADIOACC$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR0$0$0({1}SC:U),F,0,0
+S:G$XRADIOADDR1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA0$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA1$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
+S:G$XRADIODATA3$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT0$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT1$0$0({1}SC:U),F,0,0
+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
+S:G$XSPCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XSPMODE$0$0({1}SC:U),F,0,0
+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
+S:G$XSPSTATUS$0$0({1}SC:U),F,0,0
+S:G$XT0CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT0CNT0$0$0({1}SC:U),F,0,0
+S:G$XT0CNT1$0$0({1}SC:U),F,0,0
+S:G$XT0CNT$0$0({2}SI:U),F,0,0
+S:G$XT0MODE$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT0PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT0STATUS$0$0({1}SC:U),F,0,0
+S:G$XT1CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT1CNT0$0$0({1}SC:U),F,0,0
+S:G$XT1CNT1$0$0({1}SC:U),F,0,0
+S:G$XT1CNT$0$0({2}SI:U),F,0,0
+S:G$XT1MODE$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT1PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT1STATUS$0$0({1}SC:U),F,0,0
+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
+S:G$XT2CNT0$0$0({1}SC:U),F,0,0
+S:G$XT2CNT1$0$0({1}SC:U),F,0,0
+S:G$XT2CNT$0$0({2}SI:U),F,0,0
+S:G$XT2MODE$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD0$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD1$0$0({1}SC:U),F,0,0
+S:G$XT2PERIOD$0$0({2}SI:U),F,0,0
+S:G$XT2STATUS$0$0({1}SC:U),F,0,0
+S:G$XU0CTRL$0$0({1}SC:U),F,0,0
+S:G$XU0MODE$0$0({1}SC:U),F,0,0
+S:G$XU0SHREG$0$0({1}SC:U),F,0,0
+S:G$XU0STATUS$0$0({1}SC:U),F,0,0
+S:G$XU1CTRL$0$0({1}SC:U),F,0,0
+S:G$XU1MODE$0$0({1}SC:U),F,0,0
+S:G$XU1SHREG$0$0({1}SC:U),F,0,0
+S:G$XU1STATUS$0$0({1}SC:U),F,0,0
+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
+S:G$XWTCFGA$0$0({1}SC:U),F,0,0
+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTA$0$0({2}SI:U),F,0,0
+S:G$XWTCNTB0$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB1$0$0({1}SC:U),F,0,0
+S:G$XWTCNTB$0$0({2}SI:U),F,0,0
+S:G$XWTCNTR1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTA$0$0({2}SI:U),F,0,0
+S:G$XWTEVTB0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTB$0$0({2}SI:U),F,0,0
+S:G$XWTEVTC0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTC$0$0({2}SI:U),F,0,0
+S:G$XWTEVTD0$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD1$0$0({1}SC:U),F,0,0
+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
+S:G$XWTSTAT$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTER$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITY$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
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+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5043rdfifo
+
+;!FILE libmflarge/ax5043rdfifo.asm
+XH3
+H 1A areas 877 global symbols
+M ax5043rdfifo
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S C$ax5043rdfifo.c$10$0$0 Def000000
+S C$ax5043rdfifo.c$74$1$66 Def000000
+S C$ax5043rdfifo.c$75$1$66 Def000054
+S G$ax5043_readfifo$0$0 Def000000
+S _ax5043_readfifo Def000000
+S A$ax5043rdfifo$3300 Def000027
+S A$ax5043rdfifo$3310 Def000036
+S A$ax5043rdfifo$3301 Def000028
+S XG$ax5043_readfifo$0$0 Def000054
+S A$ax5043rdfifo$3320 Def000045
+S A$ax5043rdfifo$3311 Def000038
+S A$ax5043rdfifo$3302 Def00002A
+S A$ax5043rdfifo$3330 Def000053
+S A$ax5043rdfifo$3321 Def000048
+S A$ax5043rdfifo$3312 Def000039
+S A$ax5043rdfifo$3303 Def00002C
+S A$ax5043rdfifo$3313 Def00003B
+S A$ax5043rdfifo$3304 Def00002F
+S A$ax5043rdfifo$3323 Def00004A
+S A$ax5043rdfifo$3315 Def00003C
+S A$ax5043rdfifo$3306 Def000031
+S A$ax5043rdfifo$3325 Def00004B
+S A$ax5043rdfifo$3316 Def00003E
+S A$ax5043rdfifo$3307 Def000032
+S A$ax5043rdfifo$3280 Def00000F
+S A$ax5043rdfifo$3326 Def00004C
+S A$ax5043rdfifo$3317 Def000040
+S A$ax5043rdfifo$3308 Def000033
+S A$ax5043rdfifo$3281 Def000011
+S A$ax5043rdfifo$3272 Def000000
+S A$ax5043rdfifo$3327 Def00004E
+S A$ax5043rdfifo$3318 Def000041
+S A$ax5043rdfifo$3309 Def000034
+S A$ax5043rdfifo$3282 Def000014
+S A$ax5043rdfifo$3273 Def000002
+S A$ax5043rdfifo$3328 Def000050
+S A$ax5043rdfifo$3319 Def000043
+S A$ax5043rdfifo$3292 Def00001D
+S A$ax5043rdfifo$3274 Def000004
+S A$ax5043rdfifo$3329 Def000051
+S A$ax5043rdfifo$3293 Def00001E
+S A$ax5043rdfifo$3284 Def000017
+S A$ax5043rdfifo$3275 Def000005
+S A$ax5043rdfifo$3294 Def00001F
+S A$ax5043rdfifo$3285 Def000018
+S A$ax5043rdfifo$3276 Def000006
+S A$ax5043rdfifo$3295 Def000020
+S A$ax5043rdfifo$3286 Def000019
+S A$ax5043rdfifo$3277 Def000008
+S A$ax5043rdfifo$3296 Def000022
+S A$ax5043rdfifo$3287 Def00001A
+S A$ax5043rdfifo$3278 Def000009
+S A$ax5043rdfifo$3279 Def00000C
+S A$ax5043rdfifo$3298 Def000023
+S A$ax5043rdfifo$3289 Def00001C
+S A$ax5043rdfifo$3299 Def000025
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
+T 00 00 0D F6 14 A8 82 90 40 29 20 F5 06
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 E0 F6 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D E0 F2 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 29
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E2 F0 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 29
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E2 A3 DF FC 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5043rdfifo
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+S:Lax5043rdfifo.ax5043_readfifo$len$1$65({1}SC:U),B,1,-3
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+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
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+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$XADCCH3CONFIG$0$0({1}SC:U),F,0,0
+S:G$XADCCLKSRC$0$0({1}SC:U),F,0,0
+S:G$XADCCONV$0$0({1}SC:U),F,0,0
+S:G$XANALOGCOMP$0$0({1}SC:U),F,0,0
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+S:G$XCODECONFIG$0$0({1}SC:U),F,0,0
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+S:G$XRADIODATA2$0$0({1}SC:U),F,0,0
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+S:G$XRADIOSTAT$0$0({2}SI:U),F,0,0
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+S:G$XSPSHREG$0$0({1}SC:U),F,0,0
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+S:G$XWTEVTD$0$0({2}SI:U),F,0,0
+S:G$XWTIRQEN$0$0({1}SC:U),F,0,0
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+S:G$AX5043_AFSKCTRL$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTER$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BBOFFSCAP$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNE$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSI$0$0({1}SC:U),F,0,0
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+S:G$AX5043_BGNDRSSITHR$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIG$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_DECIMATION$0$0({1}SC:U),F,0,0
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+S:G$AX5043_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5043_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTACCEPTFLAGS$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZE$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLLOCKDET$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLVCODIV$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PLLVCOIR$0$0({1}SC:U),F,0,0
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+S:G$AX5043_TMGRXOFFSACQ$0$0({1}SC:U),F,0,0
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+S:G$AX5043_XTALSTATUS$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF0C$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1C$0$0({1}SC:U),F,0,0
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+S:G$AX5043_0xF22$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQDEV02$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV03$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV10$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV11$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV12$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV13$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINA1$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINA3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINB3$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAINC2$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAINC3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND0$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYGAIND1$0$0({1}SC:U),F,0,0
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+S:G$AX5043_FREQUENCYGAIND3$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQUENCYLEAK$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN0$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PHASEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PHASEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FOURFSK3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV01NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQDEV02NB$0$0({1}SC:U),F,0,0
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+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043wrfifo
+
+;!FILE libmflarge/ax5043wrfifo.asm
+XH3
+H 1A areas 879 global symbols
+M ax5043wrfifo
+O -mmcs51 --model-large
+S G$AX5043_TMGRXBOOSTNB$0$0 Def005223
+S G$AX5043_PLLVCOINB$0$0 Def005180
+S G$AX5043_LPOSCPER1NB$0$0 Def005318
+S G$AX5043_IRQINVERSION0NB$0$0 Def00500B
+S G$AX5043_PKTADDRMASK3$0$0 Def004208
+S G$AX5043_TRKRFFREQ2$0$0 Def00404D
+S G$AX5043_TRKDATARATE2$0$0 Def004045
+S G$AX5043_PLLRNGCLK$0$0 Def004183
+S G$AX5043_PLLLOOPBOOST$0$0 Def004038
+S G$AX5043_PKTSTOREFLAGS$0$0 Def004232
+S G$XIC1CAPT0$0$0 Def003FD6
+S G$XIC0CAPT1$0$0 Def003FCF
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _XT2PERIOD Def003FAE
+S _AX5043_DECIMATION Def004102
+S _AX5043_FIFOCOUNT0 Def00402B
+S _AX5043_REF Def004F0D
+S _AX5043_TMGRXAGC Def004227
+S _AX5043_XTALSTATUS Def00401D
+S _AX5043_AGCGAIN3 Def004150
+S _AX5043_RADIOEVENTMASK0NB Def005009
+S _AX5043_TMGRXPREAMBLE3NB Def00522B
+S _AX5043_XTALCAPNB Def005184
+S _AX5043_BBOFFSRES1NB Def00513F
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5043_RXPARAMSETSNB$0$0 Def005117
+S G$AX5043_PKTADDRCFGNB$0$0 Def005200
+S G$AX5043_AGCGAIN0NB$0$0 Def005120
+S G$AX5043_TMGRXCOARSEAGCNB$0$0 Def005226
+S G$AX5043_PINFUNCANTSELNB$0$0 Def005025
+S G$AX5043_IRQINVERSION1NB$0$0 Def00500A
+S G$AX5043_AFSKCTRLNB$0$0 Def005114
+S G$AX5043_PINFUNCPWRAMP$0$0 Def004026
+S G$XIC1CAPT1$0$0 Def003FD7
+S G$XCLKSTAT$0$0 Def003FC7
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _XADCCLKSRC Def003FD1
+S _AX5043_FIFOCOUNT1 Def00402A
+S _AX5043_PWRMODE Def004002
+S _AX5043_XTALOSC Def004F10
+S _AX5043_PKTLENCFG Def004201
+S _AX5043_FECNB Def005018
+S _AX5043_LPOSCREF0NB Def005315
+S _AX5043_POWIRQMASKNB Def005005
+S _AX5043_RADIOEVENTMASK1NB Def005008
+S _AX5043_0xF00NB Def005F00
+S _AX5043_BBOFFSRES2NB Def00514F
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5043_AGCGAIN1NB$0$0 Def005130
+S G$AX5043_TMGTXBOOSTNB$0$0 Def005220
+S G$AX5043_WAKEUPFREQ0$0$0 Def00406D
+S G$AX5043_PLLVCOIR$0$0 Def004181
+S G$AX5043_LPOSCKFILT0$0$0 Def004313
+S G$AX5043_AGCCOUNTER$0$0 Def004043
+S G$XPORTR$0$0 Def003F8C
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _XWTEVTA0 Def003FF4
+S _AX5043_FREQA0 Def004037
+S _AX5043_LPOSCFREQ0 Def004317
+S _AX5043_LPOSCREF1NB Def005314
+S _AX5043_TRKFREQ0NB Def005051
+S _AX5043_BBOFFSRES3NB Def00515F
+S _AX5043_FREQUENCYLEAKNB Def005116
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5043_AGCGAIN2NB$0$0 Def005140
+S G$AX5043_POWCTRL1NB$0$0 Def005F08
+S G$AX5043_BGNDRSSINB$0$0 Def005041
+S G$AX5043_WAKEUPFREQ1$0$0 Def00406C
+S G$AX5043_PINFUNCSYSCLK$0$0 Def004021
+S G$AX5043_LPOSCKFILT1$0$0 Def004312
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _XWTEVTA1 Def003FF5
+S _XWTEVTB0 Def003FF6
+S _AX5043_FIFOSTAT Def004028
+S _AX5043_FREQA1 Def004036
+S _AX5043_FREQB0 Def00403F
+S _AX5043_LPOSCFREQ1 Def004316
+S _AX5043_RXDATARATE0 Def004105
+S _AX5043_RSSIREFERENCENB Def00522C
+S _AX5043_TRKFREQ1NB Def005050
+S _AX5043_FOURFSK0NB Def00512E
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5043_AGCGAIN3NB$0$0 Def005150
+S G$AX5043_XTALSTATUSNB$0$0 Def00501D
+S G$AX5043_TMGRXAGCNB$0$0 Def005227
+S G$AX5043_REFNB$0$0 Def005F0D
+S G$AX5043_FIFOCOUNT0NB$0$0 Def00502B
+S G$AX5043_DECIMATIONNB$0$0 Def005102
+S G$AX5043_FREQDEV00$0$0 Def00412D
+S G$AX5043_PINFUNCDATA$0$0 Def004023
+S G$AX5043_IFFREQ0$0$0 Def004101
+S G$XT0CNT0$0$0 Def003F9C
+S G$XIP$0$0 Def003FB8
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _XNVKEY Def003F96
+S _XWTEVTB1 Def003FF7
+S _XWTEVTC0 Def003FFC
+S _AX5043_FREQA2 Def004035
+S _AX5043_FREQB1 Def00403E
+S _AX5043_RXDATARATE1 Def004104
+S _AX5043_0xF0C Def004F0C
+S _AX5043_0xF21NB Def005F21
+S _AX5043_0xF30NB Def005F30
+S _AX5043_FOURFSK1NB Def00513E
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5043_PKTLENCFGNB$0$0 Def005201
+S G$AX5043_XTALOSCNB$0$0 Def005F10
+S G$AX5043_PWRMODENB$0$0 Def005002
+S G$AX5043_FIFOCOUNT1NB$0$0 Def00502A
+S G$AX5043_FREQDEV10$0$0 Def00412C
+S G$AX5043_FREQDEV01$0$0 Def00413D
+S G$AX5043_TRKFSKDEMOD0$0$0 Def004053
+S G$AX5043_PLLLOCKDET$0$0 Def004182
+S G$AX5043_IFFREQ1$0$0 Def004100
+S G$XT1CNT0$0$0 Def003FA4
+S G$XT0CNT1$0$0 Def003F9D
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _XIE Def003FA8
+S _XWTEVTC1 Def003FFD
+S _XWTEVTD0 Def003FFE
+S _AX5043_FIFOTHRESH0 Def00402F
+S _AX5043_FREQA3 Def004034
+S _AX5043_FREQB2 Def00403D
+S _AX5043_GPADCPERIOD Def004301
+S _AX5043_PLLLOOP Def004030
+S _AX5043_RXDATARATE2 Def004103
+S _AX5043_0xF1C Def004F1C
+S _AX5043_TRKPHASE0NB Def00504B
+S _AX5043_0xF22NB Def005F22
+S _AX5043_0xF31NB Def005F31
+S _AX5043_FOURFSK2NB Def00514E
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5043_LPOSCFREQ0NB$0$0 Def005317
+S G$AX5043_FREQA0NB$0$0 Def005037
+S G$AX5043_FREQDEV11$0$0 Def00413C
+S G$AX5043_FREQDEV02$0$0 Def00414D
+S G$AX5043_TRKFSKDEMOD1$0$0 Def004052
+S G$AX5043_TRKAFSKDEMOD0$0$0 Def004055
+S G$AX5043_PLLRANGINGA$0$0 Def004033
+S G$XWTEVTA$0$0 Def003FF4
+S G$XT2CNT0$0$0 Def003FAC
+S G$XT1CNT1$0$0 Def003FA5
+S G$XRADIOSTAT0$0$0 Def003FBE
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _XDBGLNKBUF Def003FE3
+S _XWTEVTD1 Def003FFF
+S _AX5043_FIFOTHRESH1 Def00402E
+S _AX5043_FREQB3 Def00403C
+S _AX5043_PKTCHUNKSIZE Def004230
+S _AX5043_TMGRXSETTLE Def004224
+S _AX5043_XTALAMPL Def004F11
+S _AX5043_TMGRXRSSINB Def005228
+S _AX5043_TRKPHASE1NB Def00504A
+S _AX5043_0xF23NB Def005F23
+S _AX5043_0xF32NB Def005F32
+S _AX5043_FOURFSK3NB Def00515E
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5043_RXDATARATE0NB$0$0 Def005105
+S G$AX5043_LPOSCFREQ1NB$0$0 Def005316
+S G$AX5043_FREQB0NB$0$0 Def00503F
+S G$AX5043_FREQA1NB$0$0 Def005036
+S G$AX5043_FIFOSTATNB$0$0 Def005028
+S G$AX5043_FREQDEV12$0$0 Def00414C
+S G$AX5043_FREQDEV03$0$0 Def00415D
+S G$AX5043_TRKAFSKDEMOD1$0$0 Def004054
+S G$AX5043_RADIOSTATE$0$0 Def00401C
+S G$AX5043_PLLRANGINGB$0$0 Def00403B
+S G$AX5043_GPADC13VALUE0$0$0 Def004309
+S G$AX5043_AMPLFILTER$0$0 Def004115
+S G$XWTEVTB$0$0 Def003FF6
+S G$XT2CNT1$0$0 Def003FAD
+S G$XSPSHREG$0$0 Def003FDE
+S G$XRADIOSTAT1$0$0 Def003FBF
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5043_GPADCCTRLNB Def005300
+S _AX5043_0xF33NB Def005F33
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5043_0xF0CNB$0$0 Def005F0C
+S G$AX5043_RXDATARATE1NB$0$0 Def005104
+S G$AX5043_FREQB1NB$0$0 Def00503E
+S G$AX5043_FREQA2NB$0$0 Def005035
+S G$AX5043_RXPARAMCURSET$0$0 Def004118
+S G$AX5043_FREQDEV13$0$0 Def00415C
+S G$AX5043_WAKEUPXOEARLY$0$0 Def00406E
+S G$AX5043_TIMER0$0$0 Def00405B
+S G$AX5043_PINFUNCDCLK$0$0 Def004022
+S G$AX5043_MODCFGA$0$0 Def004164
+S G$AX5043_GPADC13VALUE1$0$0 Def004308
+S G$XWTEVTC$0$0 Def003FFC
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _XCODECONFIG Def003F97
+S _XWTCNTA Def003FF2
+S _AX5043_LPOSCSTATUS Def004311
+S _AX5043_TMGTXSETTLE Def004221
+S _AX5043_DRGAIN0 Def004125
+S _AX5043_TMGRXOFFSACQNB Def005225
+S _AX5043_0xF34NB Def005F34
+S _AX5043_PKTLENOFFSETNB Def005202
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5043_0xF1CNB$0$0 Def005F1C
+S G$AX5043_RXDATARATE2NB$0$0 Def005103
+S G$AX5043_PLLLOOPNB$0$0 Def005030
+S G$AX5043_GPADCPERIODNB$0$0 Def005301
+S G$AX5043_FREQB2NB$0$0 Def00503D
+S G$AX5043_FREQA3NB$0$0 Def005034
+S G$AX5043_FIFOTHRESH0NB$0$0 Def00502F
+S G$AX5043_TIMER1$0$0 Def00405A
+S G$AX5043_POWSTAT$0$0 Def004003
+S G$AX5043_MATCH0PAT0$0$0 Def004213
+S G$AX5043_FECSTATUS$0$0 Def00401A
+S G$XWTEVTD$0$0 Def003FFE
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _XWTCNTB Def003FFA
+S _AX5043_DRGAIN1 Def004135
+S _AX5043_PKTADDRMASK0 Def00420B
+S _AX5043_0xF26NB Def005F26
+S _AX5043_0xF35NB Def005F35
+S _AX5043_0xF44NB Def005F44
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5043_XTALAMPLNB$0$0 Def005F11
+S G$AX5043_TMGRXSETTLENB$0$0 Def005224
+S G$AX5043_PKTCHUNKSIZENB$0$0 Def005230
+S G$AX5043_FREQB3NB$0$0 Def00503C
+S G$AX5043_FIFOTHRESH1NB$0$0 Def00502E
+S G$AX5043_TIMER2$0$0 Def004059
+S G$AX5043_PLLVCODIV$0$0 Def004032
+S G$AX5043_MAXDROFFSET0$0$0 Def004108
+S G$AX5043_MATCH1PAT0$0$0 Def004219
+S G$AX5043_MATCH0PAT1$0$0 Def004212
+S G$AX5043_FSKDEV0$0$0 Def004163
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _XWTCNTR1 Def003FEB
+S _AX5043_TRKDATARATE0 Def004047
+S _AX5043_TRKRFFREQ0 Def00404F
+S _AX5043_DRGAIN2 Def004145
+S _AX5043_PKTADDRMASK1 Def00420A
+S _AX5043_PWRAMPNB Def005027
+S _AX5043_0xF18NB Def005F18
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5043_PKTMAXLEN$0$0 Def004203
+S G$AX5043_AMPLITUDEGAIN0$0$0 Def00412B
+S G$AX5043_MAXDROFFSET1$0$0 Def004107
+S G$AX5043_MATCH1PAT1$0$0 Def004218
+S G$AX5043_MATCH0PAT2$0$0 Def004211
+S G$AX5043_FSKDEV1$0$0 Def004162
+S G$XIC0STATUS$0$0 Def003FCD
+S G$XDIRA$0$0 Def003F89
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _XIC0CAPT0 Def003FCE
+S _AX5043_PINSTATE Def004020
+S _AX5043_TRKDATARATE1 Def004046
+S _AX5043_TRKRFFREQ1 Def00404E
+S _AX5043_DRGAIN3 Def004155
+S _AX5043_PKTADDRMASK2 Def004209
+S _AX5043_LPOSCPER0NB Def005319
+S _IP_4 Def0000BC
+S G$AX5043_DRGAIN0NB$0$0 Def005125
+S G$AX5043_TMGTXSETTLENB$0$0 Def005221
+S G$AX5043_LPOSCSTATUSNB$0$0 Def005311
+S G$AX5043_AMPLITUDEGAIN1$0$0 Def00413B
+S G$AX5043_MAXRFOFFSET0$0$0 Def00410B
+S G$AX5043_MAXDROFFSET2$0$0 Def004106
+S G$AX5043_MATCH0PAT3$0$0 Def004210
+S G$AX5043_FSKDEV2$0$0 Def004161
+S G$AX5043_DACVALUE0$0$0 Def004331
+S G$XOC0COMP0$0$0 Def003FBC
+S G$XIC1STATUS$0$0 Def003FD5
+S G$XIC0MODE$0$0 Def003FCC
+S G$XDIRB$0$0 Def003F8A
+S G$XANALOGCOMP$0$0 Def003FE1
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _XIC0CAPT1 Def003FCF
+S _XIC1CAPT0 Def003FD6
+S _AX5043_PKTSTOREFLAGS Def004232
+S _AX5043_PLLLOOPBOOST Def004038
+S _AX5043_PLLRNGCLK Def004183
+S _AX5043_TRKDATARATE2 Def004045
+S _AX5043_TRKRFFREQ2 Def00404D
+S _AX5043_PKTADDRMASK3 Def004208
+S _AX5043_IRQINVERSION0NB Def00500B
+S _AX5043_LPOSCPER1NB Def005318
+S _AX5043_PLLVCOINB Def005180
+S _AX5043_TMGRXBOOSTNB Def005223
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5043_PKTADDRMASK0NB$0$0 Def00520B
+S G$AX5043_DRGAIN1NB$0$0 Def005135
+S G$AX5043_AMPLITUDEGAIN2$0$0 Def00414B
+S G$AX5043_MODCFGF$0$0 Def004160
+S G$AX5043_MAXRFOFFSET1$0$0 Def00410A
+S G$AX5043_FIFOFREE0$0$0 Def00402D
+S G$AX5043_DACVALUE1$0$0 Def004330
+S G$XOC1COMP0$0$0 Def003FC4
+S G$XOC0COMP1$0$0 Def003FBD
+S G$XIC1MODE$0$0 Def003FD4
+S G$XDIRC$0$0 Def003F8B
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _XCLKSTAT Def003FC7
+S _XIC1CAPT1 Def003FD7
+S _AX5043_PINFUNCPWRAMP Def004026
+S _AX5043_AFSKCTRLNB Def005114
+S _AX5043_IRQINVERSION1NB Def00500A
+S _AX5043_PINFUNCANTSELNB Def005025
+S _AX5043_TMGRXCOARSEAGCNB Def005226
+S _AX5043_AGCGAIN0NB Def005120
+S _AX5043_PKTADDRCFGNB Def005200
+S _AX5043_RXPARAMSETSNB Def005117
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5043_PKTADDRMASK1NB$0$0 Def00520A
+S G$AX5043_DRGAIN2NB$0$0 Def005145
+S G$AX5043_TRKRFFREQ0NB$0$0 Def00504F
+S G$AX5043_TRKDATARATE0NB$0$0 Def005047
+S G$AX5043_AMPLITUDEGAIN3$0$0 Def00415B
+S G$AX5043_MAXRFOFFSET2$0$0 Def004109
+S G$AX5043_LPOSCCONFIG$0$0 Def004310
+S G$AX5043_FIFOFREE1$0$0 Def00402C
+S G$XOC1COMP1$0$0 Def003FC5
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _XPORTR Def003F8C
+S _AX5043_AGCCOUNTER Def004043
+S _AX5043_LPOSCKFILT0 Def004313
+S _AX5043_PLLVCOIR Def004181
+S _AX5043_WAKEUPFREQ0 Def00406D
+S _AX5043_TMGTXBOOSTNB Def005220
+S _AX5043_AGCGAIN1NB Def005130
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5043_PKTADDRMASK2NB$0$0 Def005209
+S G$AX5043_DRGAIN3NB$0$0 Def005155
+S G$AX5043_TRKRFFREQ1NB$0$0 Def00504E
+S G$AX5043_TRKDATARATE1NB$0$0 Def005046
+S G$AX5043_PINSTATENB$0$0 Def005020
+S G$XIC0CAPT$0$0 Def003FCE
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5043_LPOSCKFILT1 Def004312
+S _AX5043_PINFUNCSYSCLK Def004021
+S _AX5043_WAKEUPFREQ1 Def00406C
+S _AX5043_BGNDRSSINB Def005041
+S _AX5043_POWCTRL1NB Def005F08
+S _AX5043_AGCGAIN2NB Def005140
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5043_PKTADDRMASK3NB$0$0 Def005208
+S G$AX5043_TRKRFFREQ2NB$0$0 Def00504D
+S G$AX5043_TRKDATARATE2NB$0$0 Def005045
+S G$AX5043_PLLRNGCLKNB$0$0 Def005183
+S G$AX5043_PLLLOOPBOOSTNB$0$0 Def005038
+S G$AX5043_PKTSTOREFLAGSNB$0$0 Def005232
+S G$AX5043_TXPWRCOEFFA0$0$0 Def004169
+S G$XSPCLKSRC$0$0 Def003FDF
+S G$XIC1CAPT$0$0 Def003FD6
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _XIP Def003FB8
+S _XT0CNT0 Def003F9C
+S _AX5043_IFFREQ0 Def004101
+S _AX5043_PINFUNCDATA Def004023
+S _AX5043_FREQDEV00 Def00412D
+S _AX5043_DECIMATIONNB Def005102
+S _AX5043_FIFOCOUNT0NB Def00502B
+S _AX5043_REFNB Def005F0D
+S _AX5043_TMGRXAGCNB Def005227
+S _AX5043_XTALSTATUSNB Def00501D
+S _AX5043_AGCGAIN3NB Def005150
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5043_PINFUNCPWRAMPNB$0$0 Def005026
+S G$AX5043_PKTADDR0$0$0 Def004207
+S G$AX5043_TXPWRCOEFFB0$0$0 Def00416B
+S G$AX5043_TXPWRCOEFFA1$0$0 Def004168
+S G$XOC0STATUS$0$0 Def003FBB
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _XT0CNT1 Def003F9D
+S _XT1CNT0 Def003FA4
+S _AX5043_IFFREQ1 Def004100
+S _AX5043_PLLLOCKDET Def004182
+S _AX5043_TRKFSKDEMOD0 Def004053
+S _AX5043_FREQDEV01 Def00413D
+S _AX5043_FREQDEV10 Def00412C
+S _AX5043_FIFOCOUNT1NB Def00502A
+S _AX5043_PWRMODENB Def005002
+S _AX5043_XTALOSCNB Def005F10
+S _AX5043_PKTLENCFGNB Def005201
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5043_WAKEUPFREQ0NB$0$0 Def00506D
+S G$AX5043_PLLVCOIRNB$0$0 Def005181
+S G$AX5043_LPOSCKFILT0NB$0$0 Def005313
+S G$AX5043_AGCCOUNTERNB$0$0 Def005043
+S G$AX5043_PKTADDR1$0$0 Def004206
+S G$AX5043_TXPWRCOEFFC0$0$0 Def00416D
+S G$AX5043_TXPWRCOEFFB1$0$0 Def00416A
+S G$AX5043_BGNDRSSIGAIN$0$0 Def00422E
+S G$XWTSTAT$0$0 Def003FEA
+S G$XOC1STATUS$0$0 Def003FC3
+S G$XOC0MODE$0$0 Def003FB9
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _XRADIOSTAT0 Def003FBE
+S _XT1CNT1 Def003FA5
+S _XT2CNT0 Def003FAC
+S _XWTEVTA Def003FF4
+S _AX5043_PLLRANGINGA Def004033
+S _AX5043_TRKAFSKDEMOD0 Def004055
+S _AX5043_TRKFSKDEMOD1 Def004052
+S _AX5043_FREQDEV02 Def00414D
+S _AX5043_FREQDEV11 Def00413C
+S _AX5043_FREQA0NB Def005037
+S _AX5043_LPOSCFREQ0NB Def005317
+S _EIP_6 Def0000B6
+S G$AX5043_WAKEUPFREQ1NB$0$0 Def00506C
+S G$AX5043_PINFUNCSYSCLKNB$0$0 Def005021
+S G$AX5043_LPOSCKFILT1NB$0$0 Def005312
+S G$AX5043_PKTADDR2$0$0 Def004205
+S G$AX5043_TXPWRCOEFFD0$0$0 Def00416F
+S G$AX5043_TXPWRCOEFFC1$0$0 Def00416C
+S G$AX5043_MODULATION$0$0 Def004010
+S G$AX5043_MATCH0LEN$0$0 Def004214
+S G$AX5043_FSKDMIN0$0$0 Def00410F
+S G$AX5043_CRCINIT0$0$0 Def004017
+S G$XT0STATUS$0$0 Def003F9B
+S G$XOC1MODE$0$0 Def003FC1
+S G$XPINA$0$0 Def003FC8
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _XRADIOSTAT1 Def003FBF
+S _XSPSHREG Def003FDE
+S _XT2CNT1 Def003FAD
+S _XWTEVTB Def003FF6
+S _AX5043_AMPLFILTER Def004115
+S _AX5043_GPADC13VALUE0 Def004309
+S _AX5043_PLLRANGINGB Def00403B
+S _AX5043_RADIOSTATE Def00401C
+S _AX5043_TRKAFSKDEMOD1 Def004054
+S _AX5043_FREQDEV03 Def00415D
+S _AX5043_FREQDEV12 Def00414C
+S _AX5043_FIFOSTATNB Def005028
+S _AX5043_FREQA1NB Def005036
+S _AX5043_FREQB0NB Def00503F
+S _AX5043_LPOSCFREQ1NB Def005316
+S _AX5043_RXDATARATE0NB Def005105
+S _EIP_7 Def0000B7
+S G$AX5043_FREQDEV00NB$0$0 Def00512D
+S G$AX5043_PINFUNCDATANB$0$0 Def005023
+S G$AX5043_IFFREQ0NB$0$0 Def005101
+S G$AX5043_PKTADDR3$0$0 Def004204
+S G$AX5043_WAKEUP0$0$0 Def00406B
+S G$AX5043_TXPWRCOEFFE0$0$0 Def004171
+S G$AX5043_TXPWRCOEFFD1$0$0 Def00416E
+S G$AX5043_MATCH1LEN$0$0 Def00421C
+S G$AX5043_FSKDMIN1$0$0 Def00410E
+S G$AX5043_CRCINIT1$0$0 Def004016
+S G$XU0STATUS$0$0 Def003FE5
+S G$XT1STATUS$0$0 Def003FA3
+S G$XT0MODE$0$0 Def003F99
+S G$XT0CNT$0$0 Def003F9C
+S G$XOC0PIN$0$0 Def003FBA
+S G$XPINB$0$0 Def003FE8
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _XWTEVTC Def003FFC
+S _AX5043_GPADC13VALUE1 Def004308
+S _AX5043_MODCFGA Def004164
+S _AX5043_PINFUNCDCLK Def004022
+S _AX5043_TIMER0 Def00405B
+S _AX5043_WAKEUPXOEARLY Def00406E
+S _AX5043_FREQDEV13 Def00415C
+S _AX5043_RXPARAMCURSET Def004118
+S _AX5043_FREQA2NB Def005035
+S _AX5043_FREQB1NB Def00503E
+S _AX5043_RXDATARATE1NB Def005104
+S _AX5043_0xF0CNB Def005F0C
+S _XPAGE Def0000D9
+S G$AX5043_FREQDEV10NB$0$0 Def00512C
+S G$AX5043_FREQDEV01NB$0$0 Def00513D
+S G$AX5043_TRKFSKDEMOD0NB$0$0 Def005053
+S G$AX5043_PLLLOCKDETNB$0$0 Def005182
+S G$AX5043_IFFREQ1NB$0$0 Def005100
+S G$AX5043_TIMEGAIN0$0$0 Def004124
+S G$AX5043_WAKEUPTIMER0$0$0 Def004069
+S G$AX5043_WAKEUP1$0$0 Def00406A
+S G$AX5043_TXPWRCOEFFE1$0$0 Def004170
+S G$AX5043_FSKDMAX0$0$0 Def00410D
+S G$AX5043_FIFODATA$0$0 Def004029
+S G$AX5043_DACCONFIG$0$0 Def004332
+S G$AX5043_CRCINIT2$0$0 Def004015
+S G$XWTIRQEN$0$0 Def003FE9
+S G$XU1STATUS$0$0 Def003FED
+S G$XU0MODE$0$0 Def003FE7
+S G$XT2STATUS$0$0 Def003FAB
+S G$XT1MODE$0$0 Def003FA1
+S G$XT1CNT$0$0 Def003FA4
+S G$XOC1PIN$0$0 Def003FC2
+S G$XPINC$0$0 Def003FF8
+S G$XDPTR0$0$0 Def003F82
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _XWTEVTD Def003FFE
+S _AX5043_FECSTATUS Def00401A
+S _AX5043_MATCH0PAT0 Def004213
+S _AX5043_POWSTAT Def004003
+S _AX5043_TIMER1 Def00405A
+S _AX5043_FIFOTHRESH0NB Def00502F
+S _AX5043_FREQA3NB Def005034
+S _AX5043_FREQB2NB Def00503D
+S _AX5043_GPADCPERIODNB Def005301
+S _AX5043_PLLLOOPNB Def005030
+S _AX5043_RXDATARATE2NB Def005103
+S _AX5043_0xF1CNB Def005F1C
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5043_FREQDEV11NB$0$0 Def00513C
+S G$AX5043_FREQDEV02NB$0$0 Def00514D
+S G$AX5043_TRKFSKDEMOD1NB$0$0 Def005052
+S G$AX5043_TRKAFSKDEMOD0NB$0$0 Def005055
+S G$AX5043_PLLRANGINGANB$0$0 Def005033
+S G$AX5043_TIMEGAIN1$0$0 Def004134
+S G$AX5043_WAKEUPTIMER1$0$0 Def004068
+S G$AX5043_PINFUNCIRQ$0$0 Def004024
+S G$AX5043_FSKDMAX1$0$0 Def00410C
+S G$AX5043_CRCINIT3$0$0 Def004014
+S G$XU1MODE$0$0 Def003FEF
+S G$XT2MODE$0$0 Def003FA9
+S G$XT2CNT$0$0 Def003FAC
+S G$XRADIOSTAT$0$0 Def003FBE
+S G$XDPTR1$0$0 Def003F84
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5043_FSKDEV0 Def004163
+S _AX5043_MATCH0PAT1 Def004212
+S _AX5043_MATCH1PAT0 Def004219
+S _AX5043_MAXDROFFSET0 Def004108
+S _AX5043_PLLVCODIV Def004032
+S _AX5043_TIMER2 Def004059
+S _AX5043_FIFOTHRESH1NB Def00502E
+S _AX5043_FREQB3NB Def00503C
+S _AX5043_PKTCHUNKSIZENB Def005230
+S _AX5043_TMGRXSETTLENB Def005224
+S _AX5043_XTALAMPLNB Def005F11
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5043_FREQDEV12NB$0$0 Def00514C
+S G$AX5043_FREQDEV03NB$0$0 Def00515D
+S G$AX5043_TRKAFSKDEMOD1NB$0$0 Def005054
+S G$AX5043_RADIOSTATENB$0$0 Def00501C
+S G$AX5043_PLLRANGINGBNB$0$0 Def00503B
+S G$AX5043_GPADC13VALUE0NB$0$0 Def005309
+S G$AX5043_AMPLFILTERNB$0$0 Def005115
+S G$AX5043_TIMEGAIN2$0$0 Def004144
+S G$AX5043_PHASEGAIN0$0$0 Def004126
+S G$AX5043_SILICONREVISION$0$0 Def004000
+S G$AX5043_MODCFGP$0$0 Def004F5F
+S G$AX5043_BBTUNE$0$0 Def004188
+S G$AX5043_AFSKMARK0$0$0 Def004113
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _XDIRA Def003F89
+S _XIC0STATUS Def003FCD
+S _AX5043_FSKDEV1 Def004162
+S _AX5043_MATCH0PAT2 Def004211
+S _AX5043_MATCH1PAT1 Def004218
+S _AX5043_MAXDROFFSET1 Def004107
+S _AX5043_AMPLITUDEGAIN0 Def00412B
+S _AX5043_PKTMAXLEN Def004203
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5043_RXPARAMCURSETNB$0$0 Def005118
+S G$AX5043_FREQDEV13NB$0$0 Def00515C
+S G$AX5043_WAKEUPXOEARLYNB$0$0 Def00506E
+S G$AX5043_TIMER0NB$0$0 Def00505B
+S G$AX5043_PINFUNCDCLKNB$0$0 Def005022
+S G$AX5043_MODCFGANB$0$0 Def005164
+S G$AX5043_GPADC13VALUE1NB$0$0 Def005308
+S G$AX5043_TIMEGAIN3$0$0 Def004154
+S G$AX5043_PHASEGAIN1$0$0 Def004136
+S G$AX5043_RSSI$0$0 Def004040
+S G$AX5043_MATCH0MIN$0$0 Def004215
+S G$AX5043_AFSKSPACE0$0$0 Def004111
+S G$AX5043_AFSKMARK1$0$0 Def004112
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _XANALOGCOMP Def003FE1
+S _XDIRB Def003F8A
+S _XIC0MODE Def003FCC
+S _XIC1STATUS Def003FD5
+S _XOC0COMP0 Def003FBC
+S _AX5043_DACVALUE0 Def004331
+S _AX5043_FSKDEV2 Def004161
+S _AX5043_MATCH0PAT3 Def004210
+S _AX5043_MAXDROFFSET2 Def004106
+S _AX5043_MAXRFOFFSET0 Def00410B
+S _AX5043_AMPLITUDEGAIN1 Def00413B
+S _AX5043_LPOSCSTATUSNB Def005311
+S _AX5043_TMGTXSETTLENB Def005221
+S _AX5043_DRGAIN0NB Def005125
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5043_TIMER1NB$0$0 Def00505A
+S G$AX5043_POWSTATNB$0$0 Def005003
+S G$AX5043_MATCH0PAT0NB$0$0 Def005213
+S G$AX5043_FECSTATUSNB$0$0 Def00501A
+S G$AX5043_PHASEGAIN2$0$0 Def004146
+S G$AX5043_FREQUENCYGAINA0$0$0 Def004127
+S G$AX5043_AGCTARGET0$0$0 Def004121
+S G$AX5043_MATCH1MIN$0$0 Def00421D
+S G$AX5043_AFSKSPACE1$0$0 Def004110
+S G$XNVDATA0$0$0 Def003F94
+S G$XDBGLNKSTAT$0$0 Def003FE2
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _XDIRC Def003F8B
+S _XIC1MODE Def003FD4
+S _XOC0COMP1 Def003FBD
+S _XOC1COMP0 Def003FC4
+S _AX5043_DACVALUE1 Def004330
+S _AX5043_FIFOFREE0 Def00402D
+S _AX5043_MAXRFOFFSET1 Def00410A
+S _AX5043_MODCFGF Def004160
+S _AX5043_AMPLITUDEGAIN2 Def00414B
+S _AX5043_DRGAIN1NB Def005135
+S _AX5043_PKTADDRMASK0NB Def00520B
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5043_TIMER2NB$0$0 Def005059
+S G$AX5043_PLLVCODIVNB$0$0 Def005032
+S G$AX5043_MAXDROFFSET0NB$0$0 Def005108
+S G$AX5043_MATCH1PAT0NB$0$0 Def005219
+S G$AX5043_MATCH0PAT1NB$0$0 Def005212
+S G$AX5043_FSKDEV0NB$0$0 Def005163
+S G$AX5043_PHASEGAIN3$0$0 Def004156
+S G$AX5043_FREQUENCYGAINB0$0$0 Def004128
+S G$AX5043_FREQUENCYGAINA1$0$0 Def004137
+S G$AX5043_AGCTARGET1$0$0 Def004131
+S G$AX5043_MATCH0MAX$0$0 Def004216
+S G$AX5043_DIVERSITY$0$0 Def004042
+S G$XNVDATA1$0$0 Def003F95
+S G$XNVADDR0$0$0 Def003F92
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _XOC1COMP1 Def003FC5
+S _AX5043_FIFOFREE1 Def00402C
+S _AX5043_LPOSCCONFIG Def004310
+S _AX5043_MAXRFOFFSET2 Def004109
+S _AX5043_AMPLITUDEGAIN3 Def00415B
+S _AX5043_TRKDATARATE0NB Def005047
+S _AX5043_TRKRFFREQ0NB Def00504F
+S _AX5043_DRGAIN2NB Def005145
+S _AX5043_PKTADDRMASK1NB Def00520A
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5043_PKTMAXLENNB$0$0 Def005203
+S G$AX5043_AMPLITUDEGAIN0NB$0$0 Def00512B
+S G$AX5043_MAXDROFFSET1NB$0$0 Def005107
+S G$AX5043_MATCH1PAT1NB$0$0 Def005218
+S G$AX5043_MATCH0PAT2NB$0$0 Def005211
+S G$AX5043_FSKDEV1NB$0$0 Def005162
+S G$AX5043_FREQUENCYGAINC0$0$0 Def004129
+S G$AX5043_FREQUENCYGAINB1$0$0 Def004138
+S G$AX5043_FREQUENCYGAINA2$0$0 Def004147
+S G$AX5043_AGCTARGET2$0$0 Def004141
+S G$AX5043_AGCAHYST0$0$0 Def004122
+S G$AX5043_PLLCPI$0$0 Def004031
+S G$AX5043_MATCH1MAX$0$0 Def00421E
+S G$AX5043_FRAMING$0$0 Def004012
+S G$XNVADDR1$0$0 Def003F93
+S G$XPCON$0$0 Def003F87
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _XIC0CAPT Def003FCE
+S _AX5043_PINSTATENB Def005020
+S _AX5043_TRKDATARATE1NB Def005046
+S _AX5043_TRKRFFREQ1NB Def00504E
+S _AX5043_DRGAIN3NB Def005155
+S _AX5043_PKTADDRMASK2NB Def005209
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5043_AMPLITUDEGAIN1NB$0$0 Def00513B
+S G$AX5043_MAXRFOFFSET0NB$0$0 Def00510B
+S G$AX5043_MAXDROFFSET2NB$0$0 Def005106
+S G$AX5043_MATCH0PAT3NB$0$0 Def005210
+S G$AX5043_FSKDEV2NB$0$0 Def005161
+S G$AX5043_DACVALUE0NB$0$0 Def005331
+S G$AX5043_FREQUENCYGAIND0$0$0 Def00412A
+S G$AX5043_FREQUENCYGAINC1$0$0 Def004139
+S G$AX5043_FREQUENCYGAINB2$0$0 Def004148
+S G$AX5043_FREQUENCYGAINA3$0$0 Def004157
+S G$AX5043_AGCTARGET3$0$0 Def004151
+S G$AX5043_AGCMINMAX0$0$0 Def004123
+S G$AX5043_AGCAHYST1$0$0 Def004132
+S G$AX5043_RSSIABSTHR$0$0 Def00422D
+S G$AX5043_IRQREQUEST0$0$0 Def00400D
+S G$XOC0COMP$0$0 Def003FBC
+S G$XDIRR$0$0 Def003F8E
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _XIC1CAPT Def003FD6
+S _XSPCLKSRC Def003FDF
+S _AX5043_TXPWRCOEFFA0 Def004169
+S _AX5043_PKTSTOREFLAGSNB Def005232
+S _AX5043_PLLLOOPBOOSTNB Def005038
+S _AX5043_PLLRNGCLKNB Def005183
+S _AX5043_TRKDATARATE2NB Def005045
+S _AX5043_TRKRFFREQ2NB Def00504D
+S _AX5043_PKTADDRMASK3NB Def005208
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5043_AMPLITUDEGAIN2NB$0$0 Def00514B
+S G$AX5043_MODCFGFNB$0$0 Def005160
+S G$AX5043_MAXRFOFFSET1NB$0$0 Def00510A
+S G$AX5043_FIFOFREE0NB$0$0 Def00502D
+S G$AX5043_DACVALUE1NB$0$0 Def005330
+S G$AX5043_FREQUENCYGAIND1$0$0 Def00413A
+S G$AX5043_FREQUENCYGAINC2$0$0 Def004149
+S G$AX5043_FREQUENCYGAINB3$0$0 Def004158
+S G$AX5043_AGCMINMAX1$0$0 Def004133
+S G$AX5043_AGCAHYST2$0$0 Def004142
+S G$AX5043_TRKAMPLITUDE0$0$0 Def004049
+S G$AX5043_IRQREQUEST1$0$0 Def00400C
+S G$AX5043_BBOFFSCAP$0$0 Def004189
+S G$XWDTRESET$0$0 Def003FDB
+S G$XOC1COMP$0$0 Def003FC4
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _XOC0STATUS Def003FBB
+S _AX5043_TXPWRCOEFFA1 Def004168
+S _AX5043_TXPWRCOEFFB0 Def00416B
+S _AX5043_PKTADDR0 Def004207
+S _AX5043_PINFUNCPWRAMPNB Def005026
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5043_AMPLITUDEGAIN3NB$0$0 Def00515B
+S G$AX5043_MAXRFOFFSET2NB$0$0 Def005109
+S G$AX5043_LPOSCCONFIGNB$0$0 Def005310
+S G$AX5043_FIFOFREE1NB$0$0 Def00502C
+S G$AX5043_FREQUENCYGAIND2$0$0 Def00414A
+S G$AX5043_FREQUENCYGAINC3$0$0 Def004159
+S G$AX5043_AGCMINMAX2$0$0 Def004143
+S G$AX5043_AGCAHYST3$0$0 Def004152
+S G$AX5043_TRKAMPLITUDE1$0$0 Def004048
+S G$AX5043_ENCODING$0$0 Def004011
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _XOC0MODE Def003FB9
+S _XOC1STATUS Def003FC3
+S _XWTSTAT Def003FEA
+S _AX5043_BGNDRSSIGAIN Def00422E
+S _AX5043_TXPWRCOEFFB1 Def00416A
+S _AX5043_TXPWRCOEFFC0 Def00416D
+S _AX5043_PKTADDR1 Def004206
+S _AX5043_AGCCOUNTERNB Def005043
+S _AX5043_LPOSCKFILT0NB Def005313
+S _AX5043_PLLVCOIRNB Def005181
+S _AX5043_WAKEUPFREQ0NB Def00506D
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$AX5043_FREQUENCYGAIND3$0$0 Def00415A
+S G$AX5043_AGCMINMAX3$0$0 Def004153
+S G$AX5043_TXRATE0$0$0 Def004167
+S G$AX5043_SCRATCH$0$0 Def004001
+S G$AX5043_PKTMISCFLAGS$0$0 Def004231
+S G$AX5043_IRQMASK0$0$0 Def004007
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _XPINA Def003FC8
+S _XOC1MODE Def003FC1
+S _XT0STATUS Def003F9B
+S _AX5043_CRCINIT0 Def004017
+S _AX5043_FSKDMIN0 Def00410F
+S _AX5043_MATCH0LEN Def004214
+S _AX5043_MODULATION Def004010
+S _AX5043_TXPWRCOEFFC1 Def00416C
+S _AX5043_TXPWRCOEFFD0 Def00416F
+S _AX5043_PKTADDR2 Def004205
+S _AX5043_LPOSCKFILT1NB Def005312
+S _AX5043_PINFUNCSYSCLKNB Def005021
+S _AX5043_WAKEUPFREQ1NB Def00506C
+S _PINC_7 Def0000FF
+S G$AX5043_TXPWRCOEFFA0NB$0$0 Def005169
+S G$AX5043_TXRATE1$0$0 Def004166
+S G$AX5043_RADIOEVENTREQ0$0$0 Def00400F
+S G$AX5043_POWSTICKYSTAT$0$0 Def004004
+S G$AX5043_IRQMASK1$0$0 Def004006
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _XPINB Def003FE8
+S _XOC0PIN Def003FBA
+S _XT0CNT Def003F9C
+S _XT0MODE Def003F99
+S _XT1STATUS Def003FA3
+S _XU0STATUS Def003FE5
+S _AX5043_CRCINIT1 Def004016
+S _AX5043_FSKDMIN1 Def00410E
+S _AX5043_MATCH1LEN Def00421C
+S _AX5043_TXPWRCOEFFD1 Def00416E
+S _AX5043_TXPWRCOEFFE0 Def004171
+S _AX5043_WAKEUP0 Def00406B
+S _AX5043_PKTADDR3 Def004204
+S _AX5043_IFFREQ0NB Def005101
+S _AX5043_PINFUNCDATANB Def005023
+S _AX5043_FREQDEV00NB Def00512D
+S _WTCNTA0 Def0000F2
+S G$AX5043_PKTADDR0NB$0$0 Def005207
+S G$AX5043_TXPWRCOEFFB0NB$0$0 Def00516B
+S G$AX5043_TXPWRCOEFFA1NB$0$0 Def005168
+S G$AX5043_TXRATE2$0$0 Def004165
+S G$AX5043_RADIOEVENTREQ1$0$0 Def00400E
+S G$AX5043_BGNDRSSITHR$0$0 Def00422F
+S G$XRADIOACC$0$0 Def003FB1
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _XDPTR0 Def003F82
+S _XPINC Def003FF8
+S _XOC1PIN Def003FC2
+S _XT1CNT Def003FA4
+S _XT1MODE Def003FA1
+S _XT2STATUS Def003FAB
+S _XU0MODE Def003FE7
+S _XU1STATUS Def003FED
+S _XWTIRQEN Def003FE9
+S _AX5043_CRCINIT2 Def004015
+S _AX5043_DACCONFIG Def004332
+S _AX5043_FIFODATA Def004029
+S _AX5043_FSKDMAX0 Def00410D
+S _AX5043_TXPWRCOEFFE1 Def004170
+S _AX5043_WAKEUP1 Def00406A
+S _AX5043_WAKEUPTIMER0 Def004069
+S _AX5043_TIMEGAIN0 Def004124
+S _AX5043_IFFREQ1NB Def005100
+S _AX5043_PLLLOCKDETNB Def005182
+S _AX5043_TRKFSKDEMOD0NB Def005053
+S _AX5043_FREQDEV01NB Def00513D
+S _AX5043_FREQDEV10NB Def00512C
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5043_PKTADDR1NB$0$0 Def005206
+S G$AX5043_TXPWRCOEFFC0NB$0$0 Def00516D
+S G$AX5043_TXPWRCOEFFB1NB$0$0 Def00516A
+S G$AX5043_BGNDRSSIGAINNB$0$0 Def00522E
+S G$AX5043_TMGRXPREAMBLE1$0$0 Def004229
+S G$AX5043_PLLCPIBOOST$0$0 Def004039
+S G$AX5043_FECSYNC$0$0 Def004019
+S G$XT0PERIOD0$0$0 Def003F9E
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _XDPTR1 Def003F84
+S _XRADIOSTAT Def003FBE
+S _XT2CNT Def003FAC
+S _XT2MODE Def003FA9
+S _XU1MODE Def003FEF
+S _AX5043_CRCINIT3 Def004014
+S _AX5043_FSKDMAX1 Def00410C
+S _AX5043_PINFUNCIRQ Def004024
+S _AX5043_WAKEUPTIMER1 Def004068
+S _AX5043_TIMEGAIN1 Def004134
+S _AX5043_PLLRANGINGANB Def005033
+S _AX5043_TRKAFSKDEMOD0NB Def005055
+S _AX5043_TRKFSKDEMOD1NB Def005052
+S _AX5043_FREQDEV02NB Def00514D
+S _AX5043_FREQDEV11NB Def00513C
+S _WTCNTB1 Def0000FB
+S G$AX5043_PKTADDR2NB$0$0 Def005205
+S G$AX5043_TXPWRCOEFFD0NB$0$0 Def00516F
+S G$AX5043_TXPWRCOEFFC1NB$0$0 Def00516C
+S G$AX5043_MODULATIONNB$0$0 Def005010
+S G$AX5043_MATCH0LENNB$0$0 Def005214
+S G$AX5043_FSKDMIN0NB$0$0 Def00510F
+S G$AX5043_CRCINIT0NB$0$0 Def005017
+S G$AX5043_BBOFFSRES0$0$0 Def00412F
+S G$AX5043_TMGRXPREAMBLE2$0$0 Def00422A
+S G$AX5043_PKTACCEPTFLAGS$0$0 Def004233
+S G$XT1PERIOD0$0$0 Def003FA6
+S G$XT0PERIOD1$0$0 Def003F9F
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5043_AFSKMARK0 Def004113
+S _AX5043_BBTUNE Def004188
+S _AX5043_MODCFGP Def004F5F
+S _AX5043_SILICONREVISION Def004000
+S _AX5043_PHASEGAIN0 Def004126
+S _AX5043_TIMEGAIN2 Def004144
+S _AX5043_AMPLFILTERNB Def005115
+S _AX5043_GPADC13VALUE0NB Def005309
+S _AX5043_PLLRANGINGBNB Def00503B
+S _AX5043_RADIOSTATENB Def00501C
+S _AX5043_TRKAFSKDEMOD1NB Def005054
+S _AX5043_FREQDEV03NB Def00515D
+S _AX5043_FREQDEV12NB Def00514C
+S _AC Def0000D6
+S G$AX5043_PKTADDR3NB$0$0 Def005204
+S G$AX5043_WAKEUP0NB$0$0 Def00506B
+S G$AX5043_TXPWRCOEFFE0NB$0$0 Def005171
+S G$AX5043_TXPWRCOEFFD1NB$0$0 Def00516E
+S G$AX5043_MATCH1LENNB$0$0 Def00521C
+S G$AX5043_FSKDMIN1NB$0$0 Def00510E
+S G$AX5043_CRCINIT1NB$0$0 Def005016
+S G$AX5043_BBOFFSRES1$0$0 Def00413F
+S G$AX5043_XTALCAP$0$0 Def004184
+S G$AX5043_TMGRXPREAMBLE3$0$0 Def00422B
+S G$AX5043_RADIOEVENTMASK0$0$0 Def004009
+S G$XT2PERIOD0$0$0 Def003FAE
+S G$XT1PERIOD1$0$0 Def003FA7
+S G$XRADIODATA0$0$0 Def003FB7
+S G$XPINR$0$0 Def003F8D
+S G$XADCCH0CONFIG$0$0 Def003FCA
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5043_AFSKMARK1 Def004112
+S _AX5043_AFSKSPACE0 Def004111
+S _AX5043_MATCH0MIN Def004215
+S _AX5043_RSSI Def004040
+S _AX5043_PHASEGAIN1 Def004136
+S _AX5043_TIMEGAIN3 Def004154
+S _AX5043_GPADC13VALUE1NB Def005308
+S _AX5043_MODCFGANB Def005164
+S _AX5043_PINFUNCDCLKNB Def005022
+S _AX5043_TIMER0NB Def00505B
+S _AX5043_WAKEUPXOEARLYNB Def00506E
+S _AX5043_FREQDEV13NB Def00515C
+S _AX5043_RXPARAMCURSETNB Def005118
+S _E2IE Def0000A0
+S G$AX5043_TIMEGAIN0NB$0$0 Def005124
+S G$AX5043_WAKEUPTIMER0NB$0$0 Def005069
+S G$AX5043_WAKEUP1NB$0$0 Def00506A
+S G$AX5043_TXPWRCOEFFE1NB$0$0 Def005170
+S G$AX5043_FSKDMAX0NB$0$0 Def00510D
+S G$AX5043_FIFODATANB$0$0 Def005029
+S G$AX5043_DACCONFIGNB$0$0 Def005332
+S G$AX5043_CRCINIT2NB$0$0 Def005015
+S G$AX5043_BBOFFSRES2$0$0 Def00414F
+S G$AX5043_0xF00$0$0 Def004F00
+S G$AX5043_RADIOEVENTMASK1$0$0 Def004008
+S G$AX5043_POWIRQMASK$0$0 Def004005
+S G$AX5043_LPOSCREF0$0$0 Def004315
+S G$AX5043_FEC$0$0 Def004018
+S G$XU0CTRL$0$0 Def003FE4
+S G$XT2PERIOD1$0$0 Def003FAF
+S G$XRADIODATA1$0$0 Def003FB6
+S G$XRADIOADDR0$0$0 Def003FB3
+S G$XCLKCON$0$0 Def003FC6
+S G$XADCCH1CONFIG$0$0 Def003FCB
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _XDBGLNKSTAT Def003FE2
+S _XNVDATA0 Def003F94
+S _AX5043_AFSKSPACE1 Def004110
+S _AX5043_MATCH1MIN Def00421D
+S _AX5043_AGCTARGET0 Def004121
+S _AX5043_FREQUENCYGAINA0 Def004127
+S _AX5043_PHASEGAIN2 Def004146
+S _AX5043_FECSTATUSNB Def00501A
+S _AX5043_MATCH0PAT0NB Def005213
+S _AX5043_POWSTATNB Def005003
+S _AX5043_TIMER1NB Def00505A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5043_TIMEGAIN1NB$0$0 Def005134
+S G$AX5043_WAKEUPTIMER1NB$0$0 Def005068
+S G$AX5043_PINFUNCIRQNB$0$0 Def005024
+S G$AX5043_FSKDMAX1NB$0$0 Def00510C
+S G$AX5043_CRCINIT3NB$0$0 Def005014
+S G$AX5043_FREQUENCYLEAK$0$0 Def004116
+S G$AX5043_BBOFFSRES3$0$0 Def00415F
+S G$AX5043_TRKFREQ0$0$0 Def004051
+S G$AX5043_LPOSCREF1$0$0 Def004314
+S G$XU1CTRL$0$0 Def003FEC
+S G$XRADIODATA2$0$0 Def003FB5
+S G$XRADIOADDR1$0$0 Def003FB2
+S G$XADCCH2CONFIG$0$0 Def003FD2
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _XNVADDR0 Def003F92
+S _XNVDATA1 Def003F95
+S _AX5043_DIVERSITY Def004042
+S _AX5043_MATCH0MAX Def004216
+S _AX5043_AGCTARGET1 Def004131
+S _AX5043_FREQUENCYGAINA1 Def004137
+S _AX5043_FREQUENCYGAINB0 Def004128
+S _AX5043_PHASEGAIN3 Def004156
+S _AX5043_FSKDEV0NB Def005163
+S _AX5043_MATCH0PAT1NB Def005212
+S _AX5043_MATCH1PAT0NB Def005219
+S _AX5043_MAXDROFFSET0NB Def005108
+S _AX5043_PLLVCODIVNB Def005032
+S _AX5043_TIMER2NB Def005059
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5043_TIMEGAIN2NB$0$0 Def005144
+S G$AX5043_PHASEGAIN0NB$0$0 Def005126
+S G$AX5043_SILICONREVISIONNB$0$0 Def005000
+S G$AX5043_MODCFGPNB$0$0 Def005F5F
+S G$AX5043_BBTUNENB$0$0 Def005188
+S G$AX5043_AFSKMARK0NB$0$0 Def005113
+S G$AX5043_FOURFSK0$0$0 Def00412E
+S G$AX5043_TRKFREQ1$0$0 Def004050
+S G$AX5043_RSSIREFERENCE$0$0 Def00422C
+S G$XWTCFGA$0$0 Def003FF1
+S G$XRADIODATA3$0$0 Def003FB4
+S G$XADCCH3CONFIG$0$0 Def003FD3
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _XPCON Def003F87
+S _XNVADDR1 Def003F93
+S _AX5043_FRAMING Def004012
+S _AX5043_MATCH1MAX Def00421E
+S _AX5043_PLLCPI Def004031
+S _AX5043_AGCAHYST0 Def004122
+S _AX5043_AGCTARGET2 Def004141
+S _AX5043_FREQUENCYGAINA2 Def004147
+S _AX5043_FREQUENCYGAINB1 Def004138
+S _AX5043_FREQUENCYGAINC0 Def004129
+S _AX5043_FSKDEV1NB Def005162
+S _AX5043_MATCH0PAT2NB Def005211
+S _AX5043_MATCH1PAT1NB Def005218
+S _AX5043_MAXDROFFSET1NB Def005107
+S _AX5043_AMPLITUDEGAIN0NB Def00512B
+S _AX5043_PKTMAXLENNB Def005203
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5043_TIMEGAIN3NB$0$0 Def005154
+S G$AX5043_PHASEGAIN1NB$0$0 Def005136
+S G$AX5043_RSSINB$0$0 Def005040
+S G$AX5043_MATCH0MINNB$0$0 Def005215
+S G$AX5043_AFSKSPACE0NB$0$0 Def005111
+S G$AX5043_AFSKMARK1NB$0$0 Def005112
+S G$AX5043_FOURFSK1$0$0 Def00413E
+S G$AX5043_0xF30$0$0 Def004F30
+S G$AX5043_0xF21$0$0 Def004F21
+S G$XWTCFGB$0$0 Def003FF9
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _XDIRR Def003F8E
+S _XOC0COMP Def003FBC
+S _AX5043_IRQREQUEST0 Def00400D
+S _AX5043_RSSIABSTHR Def00422D
+S _AX5043_AGCAHYST1 Def004132
+S _AX5043_AGCMINMAX0 Def004123
+S _AX5043_AGCTARGET3 Def004151
+S _AX5043_FREQUENCYGAINA3 Def004157
+S _AX5043_FREQUENCYGAINB2 Def004148
+S _AX5043_FREQUENCYGAINC1 Def004139
+S _AX5043_FREQUENCYGAIND0 Def00412A
+S _AX5043_DACVALUE0NB Def005331
+S _AX5043_FSKDEV2NB Def005161
+S _AX5043_MATCH0PAT3NB Def005210
+S _AX5043_MAXDROFFSET2NB Def005106
+S _AX5043_MAXRFOFFSET0NB Def00510B
+S _AX5043_AMPLITUDEGAIN1NB Def00513B
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5043_PHASEGAIN2NB$0$0 Def005146
+S G$AX5043_FREQUENCYGAINA0NB$0$0 Def005127
+S G$AX5043_AGCTARGET0NB$0$0 Def005121
+S G$AX5043_MATCH1MINNB$0$0 Def00521D
+S G$AX5043_AFSKSPACE1NB$0$0 Def005110
+S G$AX5043_FOURFSK2$0$0 Def00414E
+S G$AX5043_0xF31$0$0 Def004F31
+S G$AX5043_0xF22$0$0 Def004F22
+S G$AX5043_TRKPHASE0$0$0 Def00404B
+S G$XU0SHREG$0$0 Def003FE6
+S G$XNVDATA$0$0 Def003F94
+S G$XADCCONV$0$0 Def003FC9
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _XOC1COMP Def003FC4
+S _XWDTRESET Def003FDB
+S _AX5043_BBOFFSCAP Def004189
+S _AX5043_IRQREQUEST1 Def00400C
+S _AX5043_TRKAMPLITUDE0 Def004049
+S _AX5043_AGCAHYST2 Def004142
+S _AX5043_AGCMINMAX1 Def004133
+S _AX5043_FREQUENCYGAINB3 Def004158
+S _AX5043_FREQUENCYGAINC2 Def004149
+S _AX5043_FREQUENCYGAIND1 Def00413A
+S _AX5043_DACVALUE1NB Def005330
+S _AX5043_FIFOFREE0NB Def00502D
+S _AX5043_MAXRFOFFSET1NB Def00510A
+S _AX5043_MODCFGFNB Def005160
+S _AX5043_AMPLITUDEGAIN2NB Def00514B
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5043_PHASEGAIN3NB$0$0 Def005156
+S G$AX5043_FREQUENCYGAINB0NB$0$0 Def005128
+S G$AX5043_FREQUENCYGAINA1NB$0$0 Def005137
+S G$AX5043_AGCTARGET1NB$0$0 Def005131
+S G$AX5043_MATCH0MAXNB$0$0 Def005216
+S G$AX5043_DIVERSITYNB$0$0 Def005042
+S G$AX5043_FOURFSK3$0$0 Def00415E
+S G$AX5043_0xF32$0$0 Def004F32
+S G$AX5043_0xF23$0$0 Def004F23
+S G$AX5043_TRKPHASE1$0$0 Def00404A
+S G$AX5043_TMGRXRSSI$0$0 Def004228
+S G$XWDTCFG$0$0 Def003FDA
+S G$XU1SHREG$0$0 Def003FEE
+S G$XNVADDR$0$0 Def003F92
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5043_ENCODING Def004011
+S _AX5043_TRKAMPLITUDE1 Def004048
+S _AX5043_AGCAHYST3 Def004152
+S _AX5043_AGCMINMAX2 Def004143
+S _AX5043_FREQUENCYGAINC3 Def004159
+S _AX5043_FREQUENCYGAIND2 Def00414A
+S _AX5043_FIFOFREE1NB Def00502C
+S _AX5043_LPOSCCONFIGNB Def005310
+S _AX5043_MAXRFOFFSET2NB Def005109
+S _AX5043_AMPLITUDEGAIN3NB Def00515B
+S _WTEVTA0 Def0000F4
+S G$AX5043_FREQUENCYGAINC0NB$0$0 Def005129
+S G$AX5043_FREQUENCYGAINB1NB$0$0 Def005138
+S G$AX5043_FREQUENCYGAINA2NB$0$0 Def005147
+S G$AX5043_AGCTARGET2NB$0$0 Def005141
+S G$AX5043_AGCAHYST0NB$0$0 Def005122
+S G$AX5043_PLLCPINB$0$0 Def005031
+S G$AX5043_MATCH1MAXNB$0$0 Def00521E
+S G$AX5043_FRAMINGNB$0$0 Def005012
+S G$AX5043_0xF33$0$0 Def004F33
+S G$AX5043_GPADCCTRL$0$0 Def004300
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _AX5043_IRQMASK0 Def004007
+S _AX5043_PKTMISCFLAGS Def004231
+S _AX5043_SCRATCH Def004001
+S _AX5043_TXRATE0 Def004167
+S _AX5043_AGCMINMAX3 Def004153
+S _AX5043_FREQUENCYGAIND3 Def00415A
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5043_FREQUENCYGAIND0NB$0$0 Def00512A
+S G$AX5043_FREQUENCYGAINC1NB$0$0 Def005139
+S G$AX5043_FREQUENCYGAINB2NB$0$0 Def005148
+S G$AX5043_FREQUENCYGAINA3NB$0$0 Def005157
+S G$AX5043_AGCTARGET3NB$0$0 Def005151
+S G$AX5043_AGCMINMAX0NB$0$0 Def005123
+S G$AX5043_AGCAHYST1NB$0$0 Def005132
+S G$AX5043_RSSIABSTHRNB$0$0 Def00522D
+S G$AX5043_IRQREQUEST0NB$0$0 Def00500D
+S G$AX5043_PKTLENOFFSET$0$0 Def004202
+S G$AX5043_0xF34$0$0 Def004F34
+S G$AX5043_TMGRXOFFSACQ$0$0 Def004225
+S G$XWTCNTA0$0$0 Def003FF2
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5043_IRQMASK1 Def004006
+S _AX5043_POWSTICKYSTAT Def004004
+S _AX5043_RADIOEVENTREQ0 Def00400F
+S _AX5043_TXRATE1 Def004166
+S _AX5043_TXPWRCOEFFA0NB Def005169
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5043_FREQUENCYGAIND1NB$0$0 Def00513A
+S G$AX5043_FREQUENCYGAINC2NB$0$0 Def005149
+S G$AX5043_FREQUENCYGAINB3NB$0$0 Def005158
+S G$AX5043_AGCMINMAX1NB$0$0 Def005133
+S G$AX5043_AGCAHYST2NB$0$0 Def005142
+S G$AX5043_TRKAMPLITUDE0NB$0$0 Def005049
+S G$AX5043_IRQREQUEST1NB$0$0 Def00500C
+S G$AX5043_BBOFFSCAPNB$0$0 Def005189
+S G$AX5043_0xF44$0$0 Def004F44
+S G$AX5043_0xF35$0$0 Def004F35
+S G$AX5043_0xF26$0$0 Def004F26
+S G$XWTCNTB0$0$0 Def003FFA
+S G$XWTCNTA1$0$0 Def003FF3
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _XRADIOACC Def003FB1
+S _AX5043_BGNDRSSITHR Def00422F
+S _AX5043_RADIOEVENTREQ1 Def00400E
+S _AX5043_TXRATE2 Def004165
+S _AX5043_TXPWRCOEFFA1NB Def005168
+S _AX5043_TXPWRCOEFFB0NB Def00516B
+S _AX5043_PKTADDR0NB Def005207
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5043_FREQUENCYGAIND2NB$0$0 Def00514A
+S G$AX5043_FREQUENCYGAINC3NB$0$0 Def005159
+S G$AX5043_AGCMINMAX2NB$0$0 Def005143
+S G$AX5043_AGCAHYST3NB$0$0 Def005152
+S G$AX5043_TRKAMPLITUDE1NB$0$0 Def005048
+S G$AX5043_ENCODINGNB$0$0 Def005011
+S G$AX5043_0xF18$0$0 Def004F18
+S G$AX5043_PWRAMP$0$0 Def004027
+S G$XWTCNTB1$0$0 Def003FFB
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _XT0PERIOD0 Def003F9E
+S _AX5043_FECSYNC Def004019
+S _AX5043_PLLCPIBOOST Def004039
+S _AX5043_TMGRXPREAMBLE1 Def004229
+S _AX5043_BGNDRSSIGAINNB Def00522E
+S _AX5043_TXPWRCOEFFB1NB Def00516A
+S _AX5043_TXPWRCOEFFC0NB Def00516D
+S _AX5043_PKTADDR1NB Def005206
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5043_FREQUENCYGAIND3NB$0$0 Def00515A
+S G$AX5043_AGCMINMAX3NB$0$0 Def005153
+S G$AX5043_TXRATE0NB$0$0 Def005167
+S G$AX5043_SCRATCHNB$0$0 Def005001
+S G$AX5043_PKTMISCFLAGSNB$0$0 Def005231
+S G$AX5043_IRQMASK0NB$0$0 Def005007
+S G$AX5043_LPOSCPER0$0$0 Def004319
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _XT0PERIOD1 Def003F9F
+S _XT1PERIOD0 Def003FA6
+S _AX5043_PKTACCEPTFLAGS Def004233
+S _AX5043_TMGRXPREAMBLE2 Def00422A
+S _AX5043_BBOFFSRES0 Def00412F
+S _AX5043_CRCINIT0NB Def005017
+S _AX5043_FSKDMIN0NB Def00510F
+S _AX5043_MATCH0LENNB Def005214
+S _AX5043_MODULATIONNB Def005010
+S _AX5043_TXPWRCOEFFC1NB Def00516C
+S _AX5043_TXPWRCOEFFD0NB Def00516F
+S _AX5043_PKTADDR2NB Def005205
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$AX5043_TXRATE1NB$0$0 Def005166
+S G$AX5043_RADIOEVENTREQ0NB$0$0 Def00500F
+S G$AX5043_POWSTICKYSTATNB$0$0 Def005004
+S G$AX5043_IRQMASK1NB$0$0 Def005006
+S G$AX5043_TMGRXBOOST$0$0 Def004223
+S G$AX5043_PLLVCOI$0$0 Def004180
+S G$AX5043_LPOSCPER1$0$0 Def004318
+S G$AX5043_IRQINVERSION0$0$0 Def00400B
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _XADCCH0CONFIG Def003FCA
+S _XPINR Def003F8D
+S _XRADIODATA0 Def003FB7
+S _XT1PERIOD1 Def003FA7
+S _XT2PERIOD0 Def003FAE
+S _AX5043_RADIOEVENTMASK0 Def004009
+S _AX5043_TMGRXPREAMBLE3 Def00422B
+S _AX5043_XTALCAP Def004184
+S _AX5043_BBOFFSRES1 Def00413F
+S _AX5043_CRCINIT1NB Def005016
+S _AX5043_FSKDMIN1NB Def00510E
+S _AX5043_MATCH1LENNB Def00521C
+S _AX5043_TXPWRCOEFFD1NB Def00516E
+S _AX5043_TXPWRCOEFFE0NB Def005171
+S _AX5043_WAKEUP0NB Def00506B
+S _AX5043_PKTADDR3NB Def005204
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5043_TXRATE2NB$0$0 Def005165
+S G$AX5043_RADIOEVENTREQ1NB$0$0 Def00500E
+S G$AX5043_BGNDRSSITHRNB$0$0 Def00522F
+S G$AX5043_RXPARAMSETS$0$0 Def004117
+S G$AX5043_PKTADDRCFG$0$0 Def004200
+S G$AX5043_AGCGAIN0$0$0 Def004120
+S G$AX5043_TMGRXCOARSEAGC$0$0 Def004226
+S G$AX5043_PINFUNCANTSEL$0$0 Def004025
+S G$AX5043_IRQINVERSION1$0$0 Def00400A
+S G$AX5043_AFSKCTRL$0$0 Def004114
+S G$XT0CLKSRC$0$0 Def003F9A
+S G$XPORTA$0$0 Def003F80
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _XADCCH1CONFIG Def003FCB
+S _XCLKCON Def003FC6
+S _XRADIOADDR0 Def003FB3
+S _XRADIODATA1 Def003FB6
+S _XT2PERIOD1 Def003FAF
+S _XU0CTRL Def003FE4
+S _AX5043_FEC Def004018
+S _AX5043_LPOSCREF0 Def004315
+S _AX5043_POWIRQMASK Def004005
+S _AX5043_RADIOEVENTMASK1 Def004008
+S _AX5043_0xF00 Def004F00
+S _AX5043_BBOFFSRES2 Def00414F
+S _AX5043_CRCINIT2NB Def005015
+S _AX5043_DACCONFIGNB Def005332
+S _AX5043_FIFODATANB Def005029
+S _AX5043_FSKDMAX0NB Def00510D
+S _AX5043_TXPWRCOEFFE1NB Def005170
+S _AX5043_WAKEUP1NB Def00506A
+S _AX5043_WAKEUPTIMER0NB Def005069
+S _AX5043_TIMEGAIN0NB Def005124
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5043_TMGRXPREAMBLE1NB$0$0 Def005229
+S G$AX5043_PLLCPIBOOSTNB$0$0 Def005039
+S G$AX5043_FECSYNCNB$0$0 Def005019
+S G$AX5043_AGCGAIN1$0$0 Def004130
+S G$AX5043_TMGTXBOOST$0$0 Def004220
+S G$XT1CLKSRC$0$0 Def003FA2
+S G$XT0PERIOD$0$0 Def003F9E
+S G$XSPSTATUS$0$0 Def003FDD
+S G$XPORTB$0$0 Def003F88
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _XADCCH2CONFIG Def003FD2
+S _XRADIOADDR1 Def003FB2
+S _XRADIODATA2 Def003FB5
+S _XU1CTRL Def003FEC
+S _AX5043_LPOSCREF1 Def004314
+S _AX5043_TRKFREQ0 Def004051
+S _AX5043_BBOFFSRES3 Def00415F
+S _AX5043_FREQUENCYLEAK Def004116
+S _AX5043_CRCINIT3NB Def005014
+S _AX5043_FSKDMAX1NB Def00510C
+S _AX5043_PINFUNCIRQNB Def005024
+S _AX5043_WAKEUPTIMER1NB Def005068
+S _AX5043_TIMEGAIN1NB Def005134
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5043_BBOFFSRES0NB$0$0 Def00512F
+S G$AX5043_TMGRXPREAMBLE2NB$0$0 Def00522A
+S G$AX5043_PKTACCEPTFLAGSNB$0$0 Def005233
+S G$AX5043_AGCGAIN2$0$0 Def004140
+S G$AX5043_POWCTRL1$0$0 Def004F08
+S G$AX5043_BGNDRSSI$0$0 Def004041
+S G$XT2CLKSRC$0$0 Def003FAA
+S G$XT1PERIOD$0$0 Def003FA6
+S G$XSPMODE$0$0 Def003FDC
+S G$XNVSTATUS$0$0 Def003F91
+S G$XPORTC$0$0 Def003F90
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _XADCCH3CONFIG Def003FD3
+S _XRADIODATA3 Def003FB4
+S _XWTCFGA Def003FF1
+S _AX5043_RSSIREFERENCE Def00422C
+S _AX5043_TRKFREQ1 Def004050
+S _AX5043_FOURFSK0 Def00412E
+S _AX5043_AFSKMARK0NB Def005113
+S _AX5043_BBTUNENB Def005188
+S _AX5043_MODCFGPNB Def005F5F
+S _AX5043_SILICONREVISIONNB Def005000
+S _AX5043_PHASEGAIN0NB Def005126
+S _AX5043_TIMEGAIN2NB Def005144
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5043_BBOFFSRES1NB$0$0 Def00513F
+S G$AX5043_XTALCAPNB$0$0 Def005184
+S G$AX5043_TMGRXPREAMBLE3NB$0$0 Def00522B
+S G$AX5043_RADIOEVENTMASK0NB$0$0 Def005009
+S G$AX5043_AGCGAIN3$0$0 Def004150
+S G$AX5043_XTALSTATUS$0$0 Def00401D
+S G$AX5043_TMGRXAGC$0$0 Def004227
+S G$AX5043_REF$0$0 Def004F0D
+S G$AX5043_FIFOCOUNT0$0$0 Def00402B
+S G$AX5043_DECIMATION$0$0 Def004102
+S G$XT2PERIOD$0$0 Def003FAE
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _XWTCFGB Def003FF9
+S _AX5043_0xF21 Def004F21
+S _AX5043_0xF30 Def004F30
+S _AX5043_FOURFSK1 Def00413E
+S _AX5043_AFSKMARK1NB Def005112
+S _AX5043_AFSKSPACE0NB Def005111
+S _AX5043_MATCH0MINNB Def005215
+S _AX5043_RSSINB Def005040
+S _AX5043_PHASEGAIN1NB Def005136
+S _AX5043_TIMEGAIN3NB Def005154
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5043_BBOFFSRES2NB$0$0 Def00514F
+S G$AX5043_0xF00NB$0$0 Def005F00
+S G$AX5043_RADIOEVENTMASK1NB$0$0 Def005008
+S G$AX5043_POWIRQMASKNB$0$0 Def005005
+S G$AX5043_LPOSCREF0NB$0$0 Def005315
+S G$AX5043_FECNB$0$0 Def005018
+S G$AX5043_PKTLENCFG$0$0 Def004201
+S G$AX5043_XTALOSC$0$0 Def004F10
+S G$AX5043_PWRMODE$0$0 Def004002
+S G$AX5043_FIFOCOUNT1$0$0 Def00402A
+S G$XADCCLKSRC$0$0 Def003FD1
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _XADCCONV Def003FC9
+S _XNVDATA Def003F94
+S _XU0SHREG Def003FE6
+S _AX5043_TRKPHASE0 Def00404B
+S _AX5043_0xF22 Def004F22
+S _AX5043_0xF31 Def004F31
+S _AX5043_FOURFSK2 Def00414E
+S _AX5043_AFSKSPACE1NB Def005110
+S _AX5043_MATCH1MINNB Def00521D
+S _AX5043_AGCTARGET0NB Def005121
+S _AX5043_FREQUENCYGAINA0NB Def005127
+S _AX5043_PHASEGAIN2NB Def005146
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5043_FREQUENCYLEAKNB$0$0 Def005116
+S G$AX5043_BBOFFSRES3NB$0$0 Def00515F
+S G$AX5043_TRKFREQ0NB$0$0 Def005051
+S G$AX5043_LPOSCREF1NB$0$0 Def005314
+S G$AX5043_LPOSCFREQ0$0$0 Def004317
+S G$AX5043_FREQA0$0$0 Def004037
+S G$XWTEVTA0$0$0 Def003FF4
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _XNVADDR Def003F92
+S _XU1SHREG Def003FEE
+S _XWDTCFG Def003FDA
+S _AX5043_TMGRXRSSI Def004228
+S _AX5043_TRKPHASE1 Def00404A
+S _AX5043_0xF23 Def004F23
+S _AX5043_0xF32 Def004F32
+S _AX5043_FOURFSK3 Def00415E
+S _AX5043_DIVERSITYNB Def005042
+S _AX5043_MATCH0MAXNB Def005216
+S _AX5043_AGCTARGET1NB Def005131
+S _AX5043_FREQUENCYGAINA1NB Def005137
+S _AX5043_FREQUENCYGAINB0NB Def005128
+S _AX5043_PHASEGAIN3NB Def005156
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5043_FOURFSK0NB$0$0 Def00512E
+S G$AX5043_TRKFREQ1NB$0$0 Def005050
+S G$AX5043_RSSIREFERENCENB$0$0 Def00522C
+S G$AX5043_RXDATARATE0$0$0 Def004105
+S G$AX5043_LPOSCFREQ1$0$0 Def004316
+S G$AX5043_FREQB0$0$0 Def00403F
+S G$AX5043_FREQA1$0$0 Def004036
+S G$AX5043_FIFOSTAT$0$0 Def004028
+S G$XWTEVTB0$0$0 Def003FF6
+S G$XWTEVTA1$0$0 Def003FF5
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5043_GPADCCTRL Def004300
+S _AX5043_0xF33 Def004F33
+S _AX5043_FRAMINGNB Def005012
+S _AX5043_MATCH1MAXNB Def00521E
+S _AX5043_PLLCPINB Def005031
+S _AX5043_AGCAHYST0NB Def005122
+S _AX5043_AGCTARGET2NB Def005141
+S _AX5043_FREQUENCYGAINA2NB Def005147
+S _AX5043_FREQUENCYGAINB1NB Def005138
+S _AX5043_FREQUENCYGAINC0NB Def005129
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5043_FOURFSK1NB$0$0 Def00513E
+S G$AX5043_0xF30NB$0$0 Def005F30
+S G$AX5043_0xF21NB$0$0 Def005F21
+S G$AX5043_0xF0C$0$0 Def004F0C
+S G$AX5043_RXDATARATE1$0$0 Def004104
+S G$AX5043_FREQB1$0$0 Def00403E
+S G$AX5043_FREQA2$0$0 Def004035
+S G$XWTEVTC0$0$0 Def003FFC
+S G$XWTEVTB1$0$0 Def003FF7
+S G$XNVKEY$0$0 Def003F96
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _XWTCNTA0 Def003FF2
+S _AX5043_TMGRXOFFSACQ Def004225
+S _AX5043_0xF34 Def004F34
+S _AX5043_PKTLENOFFSET Def004202
+S _AX5043_IRQREQUEST0NB Def00500D
+S _AX5043_RSSIABSTHRNB Def00522D
+S _AX5043_AGCAHYST1NB Def005132
+S _AX5043_AGCMINMAX0NB Def005123
+S _AX5043_AGCTARGET3NB Def005151
+S _AX5043_FREQUENCYGAINA3NB Def005157
+S _AX5043_FREQUENCYGAINB2NB Def005148
+S _AX5043_FREQUENCYGAINC1NB Def005139
+S _AX5043_FREQUENCYGAIND0NB Def00512A
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5043_FOURFSK2NB$0$0 Def00514E
+S G$AX5043_0xF31NB$0$0 Def005F31
+S G$AX5043_0xF22NB$0$0 Def005F22
+S G$AX5043_TRKPHASE0NB$0$0 Def00504B
+S G$AX5043_0xF1C$0$0 Def004F1C
+S G$AX5043_RXDATARATE2$0$0 Def004103
+S G$AX5043_PLLLOOP$0$0 Def004030
+S G$AX5043_GPADCPERIOD$0$0 Def004301
+S G$AX5043_FREQB2$0$0 Def00403D
+S G$AX5043_FREQA3$0$0 Def004034
+S G$AX5043_FIFOTHRESH0$0$0 Def00402F
+S G$XWTEVTD0$0$0 Def003FFE
+S G$XWTEVTC1$0$0 Def003FFD
+S G$XIE$0$0 Def003FA8
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _XWTCNTA1 Def003FF3
+S _XWTCNTB0 Def003FFA
+S _AX5043_0xF26 Def004F26
+S _AX5043_0xF35 Def004F35
+S _AX5043_0xF44 Def004F44
+S _AX5043_BBOFFSCAPNB Def005189
+S _AX5043_IRQREQUEST1NB Def00500C
+S _AX5043_TRKAMPLITUDE0NB Def005049
+S _AX5043_AGCAHYST2NB Def005142
+S _AX5043_AGCMINMAX1NB Def005133
+S _AX5043_FREQUENCYGAINB3NB Def005158
+S _AX5043_FREQUENCYGAINC2NB Def005149
+S _AX5043_FREQUENCYGAIND1NB Def00513A
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$AX5043_FOURFSK3NB$0$0 Def00515E
+S G$AX5043_0xF32NB$0$0 Def005F32
+S G$AX5043_0xF23NB$0$0 Def005F23
+S G$AX5043_TRKPHASE1NB$0$0 Def00504A
+S G$AX5043_TMGRXRSSINB$0$0 Def005228
+S G$AX5043_XTALAMPL$0$0 Def004F11
+S G$AX5043_TMGRXSETTLE$0$0 Def004224
+S G$AX5043_PKTCHUNKSIZE$0$0 Def004230
+S G$AX5043_FREQB3$0$0 Def00403C
+S G$AX5043_FIFOTHRESH1$0$0 Def00402E
+S G$XWTEVTD1$0$0 Def003FFF
+S G$XDBGLNKBUF$0$0 Def003FE3
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _XWTCNTB1 Def003FFB
+S _AX5043_PWRAMP Def004027
+S _AX5043_0xF18 Def004F18
+S _AX5043_ENCODINGNB Def005011
+S _AX5043_TRKAMPLITUDE1NB Def005048
+S _AX5043_AGCAHYST3NB Def005152
+S _AX5043_AGCMINMAX2NB Def005143
+S _AX5043_FREQUENCYGAINC3NB Def005159
+S _AX5043_FREQUENCYGAIND2NB Def00514A
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5043_0xF33NB$0$0 Def005F33
+S G$AX5043_GPADCCTRLNB$0$0 Def005300
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5043_LPOSCPER0 Def004319
+S _AX5043_IRQMASK0NB Def005007
+S _AX5043_PKTMISCFLAGSNB Def005231
+S _AX5043_SCRATCHNB Def005001
+S _AX5043_TXRATE0NB Def005167
+S _AX5043_AGCMINMAX3NB Def005153
+S _AX5043_FREQUENCYGAIND3NB Def00515A
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5043_PKTLENOFFSETNB$0$0 Def005202
+S G$AX5043_0xF34NB$0$0 Def005F34
+S G$AX5043_TMGRXOFFSACQNB$0$0 Def005225
+S G$AX5043_DRGAIN0$0$0 Def004125
+S G$AX5043_TMGTXSETTLE$0$0 Def004221
+S G$AX5043_LPOSCSTATUS$0$0 Def004311
+S G$XWTCNTA$0$0 Def003FF2
+S G$XCODECONFIG$0$0 Def003F97
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _AX5043_IRQINVERSION0 Def00400B
+S _AX5043_LPOSCPER1 Def004318
+S _AX5043_PLLVCOI Def004180
+S _AX5043_TMGRXBOOST Def004223
+S _AX5043_IRQMASK1NB Def005006
+S _AX5043_POWSTICKYSTATNB Def005004
+S _AX5043_RADIOEVENTREQ0NB Def00500F
+S _AX5043_TXRATE1NB Def005166
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5043_0xF44NB$0$0 Def005F44
+S G$AX5043_0xF35NB$0$0 Def005F35
+S G$AX5043_0xF26NB$0$0 Def005F26
+S G$AX5043_PKTADDRMASK0$0$0 Def00420B
+S G$AX5043_DRGAIN1$0$0 Def004135
+S G$XWTCNTB$0$0 Def003FFA
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _XPORTA Def003F80
+S _XT0CLKSRC Def003F9A
+S _AX5043_AFSKCTRL Def004114
+S _AX5043_IRQINVERSION1 Def00400A
+S _AX5043_PINFUNCANTSEL Def004025
+S _AX5043_TMGRXCOARSEAGC Def004226
+S _AX5043_AGCGAIN0 Def004120
+S _AX5043_PKTADDRCFG Def004200
+S _AX5043_RXPARAMSETS Def004117
+S _AX5043_BGNDRSSITHRNB Def00522F
+S _AX5043_RADIOEVENTREQ1NB Def00500E
+S _AX5043_TXRATE2NB Def005165
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5043_0xF18NB$0$0 Def005F18
+S G$AX5043_PWRAMPNB$0$0 Def005027
+S G$AX5043_PKTADDRMASK1$0$0 Def00420A
+S G$AX5043_DRGAIN2$0$0 Def004145
+S G$AX5043_TRKRFFREQ0$0$0 Def00404F
+S G$AX5043_TRKDATARATE0$0$0 Def004047
+S G$XWTCNTR1$0$0 Def003FEB
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _XPORTB Def003F88
+S _XSPSTATUS Def003FDD
+S _XT0PERIOD Def003F9E
+S _XT1CLKSRC Def003FA2
+S _AX5043_TMGTXBOOST Def004220
+S _AX5043_AGCGAIN1 Def004130
+S _AX5043_FECSYNCNB Def005019
+S _AX5043_PLLCPIBOOSTNB Def005039
+S _AX5043_TMGRXPREAMBLE1NB Def005229
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5043_LPOSCPER0NB$0$0 Def005319
+S G$AX5043_PKTADDRMASK2$0$0 Def004209
+S G$AX5043_DRGAIN3$0$0 Def004155
+S G$AX5043_TRKRFFREQ1$0$0 Def00404E
+S G$AX5043_TRKDATARATE1$0$0 Def004046
+S G$AX5043_PINSTATE$0$0 Def004020
+S G$XIC0CAPT0$0$0 Def003FCE
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _XPORTC Def003F90
+S _XNVSTATUS Def003F91
+S _XSPMODE Def003FDC
+S _XT1PERIOD Def003FA6
+S _XT2CLKSRC Def003FAA
+S _AX5043_BGNDRSSI Def004041
+S _AX5043_POWCTRL1 Def004F08
+S _AX5043_AGCGAIN2 Def004140
+S _AX5043_PKTACCEPTFLAGSNB Def005233
+S _AX5043_TMGRXPREAMBLE2NB Def00522A
+S _AX5043_BBOFFSRES0NB Def00512F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
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+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
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+S A$ax5043wrfifo$3277 Def000008
+S A$ax5043wrfifo$3296 Def000022
+S A$ax5043wrfifo$3287 Def00001A
+S A$ax5043wrfifo$3278 Def000009
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+S A$ax5043wrfifo$3298 Def000023
+S A$ax5043wrfifo$3289 Def00001C
+S A$ax5043wrfifo$3299 Def000025
+S C$ax5043wrfifo.c$10$0$0 Def000000
+S C$ax5043wrfifo.c$75$1$66 Def000000
+S C$ax5043wrfifo.c$76$1$66 Def000056
+S G$ax5043_writefifo$0$0 Def000000
+S _ax5043_writefifo Def000000
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+A CONST size 0 flags 20 addr 0
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+A CABS size 0 flags 28 addr 0
+T 00 00 00
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+
+
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+S:G$XT2CLKSRC$0$0({1}SC:U),F,0,0
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+S:G$XWDTCFG$0$0({1}SC:U),F,0,0
+S:G$XWDTRESET$0$0({1}SC:U),F,0,0
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+S:G$XWTCFGB$0$0({1}SC:U),F,0,0
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+S:G$AX5043_PKTADDR0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDR3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK0$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK1$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK2$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTADDRMASK3$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENCFG$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTLENOFFSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMAXLEN$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMCURSET$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXPARAMSETS$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN0$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN1$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMEGAIN3$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKMARK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AFSKSPACE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLFILTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBTUNENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSIGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BGNDRSSITHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DACVALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DECIMATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DIVERSITYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOCOUNT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOFREE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FIFOTHRESH1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FREQB3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_FSKDMIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADC13VALUE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCCTRLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_GPADCPERIODNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQINVERSION1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_IRQREQUEST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCCONFIGNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCKFILT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCPER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCREF1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_LPOSCSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH0PAT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1LENNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MAXNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1MINNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MATCH1PAT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXDROFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MAXRFOFFSET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODCFGPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCANTSELNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDATANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCDCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCIRQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCPWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINFUNCSYSCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PINSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTACCEPTFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTCHUNKSIZENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTMISCFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PKTSTOREFLAGSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLCPIBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOCKDETNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLLOOPBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGANB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRANGINGBNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCODIVNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PLLVCOIRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWCTRL1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWIRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_POWSTICKYSTATNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRAMPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTMASK1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOEVENTREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RADIOSTATENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIABSTHRNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RSSIREFERENCENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_RXDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TIMER2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXCOARSEAGCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXOFFSACQNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXPREAMBLE3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXRSSINB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGRXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXBOOSTNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TMGTXSETTLENB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKAMPLITUDE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKDATARATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKFSKDEMOD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKPHASE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TRKRFFREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFB1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFC1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFD1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXPWRCOEFFE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_TXRATE2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUP1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPFREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPTIMER1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_WAKEUPXOEARLYNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALAMPLNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_XTALSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF00NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF0CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF18NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF1CNB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF21NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF22NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF23NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF26NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF30NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF31NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF32NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF33NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF34NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF35NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_0xF44NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCAHYST3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCMINMAX3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AGCTARGET3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_AMPLITUDEGAIN3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES0NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES1NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES2NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_BBOFFSRES3NB$0$0({1}SC:U),F,0,0
+S:G$AX5043_DRGAIN0NB$0$0({1}SC:U),F,0,0
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+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5043regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5043regs
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5043regs
+
+
+
+
+ax5051comminit
+
+;!FILE libmflarge/ax5051comminit.asm
+XH3
+H 1A areas 423 global symbols
+M ax5051comminit
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 27 flags 20 addr 0
+S C$ax5051comminit.c$8$0$0 Def000000
+S _ax5051_comminit Def000000
+S XG$ax5051_comminit$0$0 Def000026
+S A$ax5051comminit$1660 Def00000F
+S A$ax5051comminit$1670 Def00001D
+S A$ax5051comminit$1661 Def000012
+S A$ax5051comminit$1652 Def000006
+S A$ax5051comminit$1671 Def00001E
+S A$ax5051comminit$1662 Def000014
+S A$ax5051comminit$1653 Def000009
+S A$ax5051comminit$1681 Def000026
+S A$ax5051comminit$1672 Def00001F
+S A$ax5051comminit$1663 Def000015
+S A$ax5051comminit$1654 Def00000B
+S A$ax5051comminit$1673 Def000020
+S A$ax5051comminit$1664 Def000016
+S A$ax5051comminit$1646 Def000000
+S A$ax5051comminit$1665 Def000017
+S A$ax5051comminit$1657 Def00000C
+S A$ax5051comminit$1676 Def000021
+S A$ax5051comminit$1649 Def000003
+S A$ax5051comminit$1677 Def000024
+S A$ax5051comminit$1668 Def000018
+S A$ax5051comminit$1678 Def000025
+S A$ax5051comminit$1669 Def00001B
+S C$ax5051comminit.c$10$1$66 Def000000
+S C$ax5051comminit.c$11$1$66 Def000003
+S C$ax5051comminit.c$12$1$66 Def000006
+S C$ax5051comminit.c$13$1$66 Def00000C
+S C$ax5051comminit.c$23$1$66 Def000021
+S C$ax5051comminit.c$24$1$66 Def000026
+S C$ax5051comminit.c$15$1$66 Def00000F
+S C$ax5051comminit.c$16$1$66 Def000018
+S G$ax5051_comminit$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 40 74 05 F0 E4 A3 F0 90
+R 00 00 00 16
+T 00 00 19 70 42 74 04 F0 E4 A3 F0 90 70 0C 04 F0
+R 00 00 00 16
+T 00 00 26 22
+R 00 00 00 16
+
+
+M:ax5051comminit
+F:G$ax5051_comminit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
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+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
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+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
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+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
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+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
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+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
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+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051commslpexit
+
+;!FILE libmflarge/ax5051commslpexit.asm
+XH3
+H 1A areas 425 global symbols
+M ax5051commslpexit
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S _ax5051_probeirq Ref000000
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
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+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 28 flags 20 addr 0
+S C$ax5051commslpexit.c$24$1$66 Def000024
+S C$ax5051commslpexit.c$15$1$66 Def000012
+S C$ax5051commslpexit.c$25$1$66 Def000027
+S C$ax5051commslpexit.c$16$1$66 Def00001B
+S C$ax5051commslpexit.c$8$0$0 Def000000
+S G$ax5051_commsleepexit$0$0 Def000000
+S _ax5051_commsleepexit Def000000
+S XG$ax5051_commsleepexit$0$0 Def000027
+S A$ax5051commslpexit$1650 Def000003
+S A$ax5051commslpexit$1661 Def00000F
+S A$ax5051commslpexit$1680 Def000024
+S A$ax5051commslpexit$1653 Def000006
+S A$ax5051commslpexit$1672 Def00001B
+S A$ax5051commslpexit$1654 Def000009
+S A$ax5051commslpexit$1673 Def00001E
+S A$ax5051commslpexit$1664 Def000012
+S A$ax5051commslpexit$1655 Def00000A
+S A$ax5051commslpexit$1683 Def000027
+S A$ax5051commslpexit$1674 Def000020
+S A$ax5051commslpexit$1665 Def000015
+S A$ax5051commslpexit$1656 Def00000B
+S A$ax5051commslpexit$1647 Def000000
+S A$ax5051commslpexit$1675 Def000021
+S A$ax5051commslpexit$1666 Def000017
+S A$ax5051commslpexit$1657 Def00000D
+S A$ax5051commslpexit$1676 Def000022
+S A$ax5051commslpexit$1667 Def000018
+S A$ax5051commslpexit$1658 Def00000E
+S A$ax5051commslpexit$1677 Def000023
+S A$ax5051commslpexit$1668 Def000019
+S A$ax5051commslpexit$1669 Def00001A
+S C$ax5051commslpexit.c$10$1$66 Def000000
+S C$ax5051commslpexit.c$11$1$66 Def000003
+S C$ax5051commslpexit.c$12$1$66 Def000006
+S C$ax5051commslpexit.c$13$1$66 Def00000F
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
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+T 00 00 00
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+T 00 00 00
+R 00 00 00 04
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+T 00 00 00 75 8E 15 75 8C EB 90 70 44 E0 FF 74 40
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+R 00 00 00 16
+T 00 00 1A F0 90 70 42 74 04 F0 E4 A3 F0 12 00 00
+R 00 00 00 16 02 0E 00 67
+T 00 00 27 22
+R 00 00 00 16
+
+
+M:ax5051commslpexit
+F:G$ax5051_commsleepexit$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051reset
+
+;!FILE libmflarge/ax5051reset.asm
+XH3
+H 1A areas 4F0 global symbols
+M ax5051reset
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 13A flags 20 addr 0
+S C$ax5051reset.c$8$0$0 Def000000
+S _ax5051_reset Def000000
+S _ax5051_probeirq Def000088
+S XG$ax5051_reset$0$0 Def000087
+S XG$ax5051_probeirq$0$0 Def000139
+S A$ax5051reset$1800 Def000090
+S A$ax5051reset$1710 Def000042
+S A$ax5051reset$1701 Def000035
+S A$ax5051reset$1810 Def00009A
+S A$ax5051reset$1720 Def00004B
+S A$ax5051reset$1702 Def000038
+S A$ax5051reset$1910 Def0000F7
+S A$ax5051reset$1820 Def0000A4
+S A$ax5051reset$1811 Def00009C
+S A$ax5051reset$1721 Def00004C
+S A$ax5051reset$1920 Def000106
+S A$ax5051reset$1911 Def0000F8
+S A$ax5051reset$1902 Def0000EC
+S A$ax5051reset$1830 Def0000AE
+S A$ax5051reset$1821 Def0000A6
+S A$ax5051reset$1812 Def00009D
+S A$ax5051reset$1803 Def000092
+S A$ax5051reset$1731 Def000056
+S A$ax5051reset$1722 Def00004F
+S A$ax5051reset$1704 Def00003A
+S A$ax5051reset$1930 Def000114
+S A$ax5051reset$1921 Def000107
+S A$ax5051reset$1912 Def0000FB
+S A$ax5051reset$1903 Def0000EF
+S A$ax5051reset$1840 Def0000B8
+S A$ax5051reset$1831 Def0000AF
+S A$ax5051reset$1822 Def0000A8
+S A$ax5051reset$1750 Def00006C
+S A$ax5051reset$1732 Def000059
+S A$ax5051reset$1714 Def000044
+S A$ax5051reset$1705 Def00003D
+S A$ax5051reset$1660 Def00000C
+S C$ax5051reset.c$111$1$68 Def000117
+S A$ax5051reset$1940 Def00011C
+S A$ax5051reset$1931 Def000115
+S A$ax5051reset$1913 Def0000FE
+S A$ax5051reset$1904 Def0000F1
+S A$ax5051reset$1850 Def0000C2
+S A$ax5051reset$1841 Def0000BB
+S A$ax5051reset$1832 Def0000B0
+S A$ax5051reset$1760 Def000077
+S A$ax5051reset$1733 Def00005B
+S A$ax5051reset$1715 Def000047
+S A$ax5051reset$1670 Def00001A
+S A$ax5051reset$1652 Def000003
+S C$ax5051reset.c$112$1$68 Def00011C
+S C$ax5051reset.c$103$1$68 Def0000EA
+S A$ax5051reset$1941 Def00011F
+S A$ax5051reset$1932 Def000116
+S A$ax5051reset$1914 Def0000FF
+S A$ax5051reset$1905 Def0000F2
+S A$ax5051reset$1860 Def0000CB
+S A$ax5051reset$1851 Def0000C5
+S A$ax5051reset$1815 Def00009E
+S A$ax5051reset$1806 Def000094
+S A$ax5051reset$1743 Def000063
+S A$ax5051reset$1716 Def000049
+S A$ax5051reset$1680 Def000025
+S A$ax5051reset$1671 Def00001B
+S C$ax5051reset.c$113$1$68 Def00012B
+S A$ax5051reset$1960 Def000134
+S A$ax5051reset$1951 Def00012B
+S A$ax5051reset$1942 Def000120
+S A$ax5051reset$1924 Def000108
+S A$ax5051reset$1915 Def000100
+S A$ax5051reset$1852 Def0000C6
+S A$ax5051reset$1825 Def0000A9
+S A$ax5051reset$1816 Def0000A1
+S A$ax5051reset$1753 Def00006D
+S A$ax5051reset$1744 Def000066
+S A$ax5051reset$1726 Def000051
+S A$ax5051reset$1690 Def00002E
+S A$ax5051reset$1681 Def000026
+S A$ax5051reset$1672 Def00001C
+S A$ax5051reset$1663 Def00000F
+S C$ax5051reset.c$105$1$68 Def0000EC
+S A$ax5051reset$1952 Def00012C
+S A$ax5051reset$1943 Def000121
+S A$ax5051reset$1925 Def00010B
+S A$ax5051reset$1880 Def0000DD
+S A$ax5051reset$1853 Def0000C7
+S A$ax5051reset$1835 Def0000B2
+S A$ax5051reset$1826 Def0000AB
+S A$ax5051reset$1817 Def0000A3
+S A$ax5051reset$1763 Def000078
+S A$ax5051reset$1754 Def000070
+S A$ax5051reset$1736 Def00005C
+S A$ax5051reset$1727 Def000054
+S A$ax5051reset$1709 Def00003F
+S A$ax5051reset$1673 Def00001D
+S A$ax5051reset$1664 Def000012
+S A$ax5051reset$1655 Def000006
+S C$ax5051reset.c$115$1$68 Def00012E
+S C$ax5051reset.c$106$1$68 Def0000F3
+S A$ax5051reset$1944 Def000124
+S A$ax5051reset$1935 Def000117
+S A$ax5051reset$1926 Def00010C
+S A$ax5051reset$1908 Def0000F3
+S A$ax5051reset$1890 Def0000E4
+S A$ax5051reset$1881 Def0000DE
+S A$ax5051reset$1854 Def0000C9
+S A$ax5051reset$1845 Def0000BD
+S A$ax5051reset$1836 Def0000B5
+S A$ax5051reset$1809 Def000097
+S A$ax5051reset$1773 Def000084
+S A$ax5051reset$1764 Def00007B
+S A$ax5051reset$1755 Def000071
+S A$ax5051reset$1737 Def00005D
+S A$ax5051reset$1719 Def00004A
+S A$ax5051reset$1665 Def000014
+S A$ax5051reset$1656 Def000009
+S C$ax5051reset.c$116$1$68 Def000134
+S A$ax5051reset$1963 Def000136
+S A$ax5051reset$1945 Def000127
+S A$ax5051reset$1936 Def00011A
+S A$ax5051reset$1927 Def00010D
+S A$ax5051reset$1918 Def000101
+S A$ax5051reset$1909 Def0000F6
+S A$ax5051reset$1864 Def0000CD
+S A$ax5051reset$1855 Def0000CA
+S A$ax5051reset$1846 Def0000C0
+S A$ax5051reset$1837 Def0000B7
+S A$ax5051reset$1765 Def00007D
+S A$ax5051reset$1738 Def00005E
+S A$ax5051reset$1693 Def00002F
+S A$ax5051reset$1684 Def000027
+S A$ax5051reset$1657 Def00000B
+S C$ax5051reset.c$117$1$68 Def000136
+S C$ax5051reset.c$108$1$68 Def000101
+S A$ax5051reset$1955 Def00012E
+S A$ax5051reset$1946 Def000128
+S A$ax5051reset$1937 Def00011B
+S A$ax5051reset$1928 Def000110
+S A$ax5051reset$1919 Def000104
+S A$ax5051reset$1874 Def0000D6
+S A$ax5051reset$1865 Def0000D0
+S A$ax5051reset$1829 Def0000AC
+S A$ax5051reset$1748 Def000068
+S A$ax5051reset$1739 Def000061
+S A$ax5051reset$1694 Def000032
+S A$ax5051reset$1685 Def00002A
+S A$ax5051reset$1676 Def00001E
+S A$ax5051reset$1649 Def000000
+S C$ax5051reset.c$118$1$68 Def000139
+S C$ax5051reset.c$109$1$68 Def000108
+S A$ax5051reset$1956 Def000130
+S A$ax5051reset$1947 Def000129
+S A$ax5051reset$1929 Def000113
+S A$ax5051reset$1884 Def0000DF
+S A$ax5051reset$1866 Def0000D1
+S A$ax5051reset$1794 Def000088
+S A$ax5051reset$1758 Def000072
+S A$ax5051reset$1749 Def00006B
+S A$ax5051reset$1686 Def00002C
+S A$ax5051reset$1677 Def000021
+S A$ax5051reset$1668 Def000015
+S A$ax5051reset$1957 Def000132
+S A$ax5051reset$1948 Def00012A
+S A$ax5051reset$1894 Def0000E6
+S A$ax5051reset$1867 Def0000D2
+S A$ax5051reset$1795 Def00008B
+S A$ax5051reset$1777 Def000087
+S A$ax5051reset$1768 Def00007F
+S A$ax5051reset$1759 Def000075
+S A$ax5051reset$1678 Def000023
+S A$ax5051reset$1669 Def000018
+S A$ax5051reset$1967 Def000139
+S A$ax5051reset$1895 Def0000E7
+S A$ax5051reset$1868 Def0000D4
+S A$ax5051reset$1796 Def00008C
+S A$ax5051reset$1769 Def000082
+S A$ax5051reset$1697 Def000033
+S A$ax5051reset$1679 Def000024
+S A$ax5051reset$1896 Def0000E8
+S A$ax5051reset$1887 Def0000E1
+S A$ax5051reset$1878 Def0000D8
+S A$ax5051reset$1869 Def0000D5
+S A$ax5051reset$1797 Def00008D
+S A$ax5051reset$1698 Def000034
+S A$ax5051reset$1689 Def00002D
+S A$ax5051reset$1879 Def0000DB
+S C$ax5051reset.c$20$1$66 Def00000F
+S A$ax5051reset$1899 Def0000EA
+S C$ax5051reset.c$12$1$66 Def000000
+S C$ax5051reset.c$22$1$66 Def000015
+S C$ax5051reset.c$13$1$66 Def000003
+S C$ax5051reset.c$23$1$66 Def00001E
+S C$ax5051reset.c$60$1$66 Def000072
+S C$ax5051reset.c$51$1$66 Def000044
+S C$ax5051reset.c$42$1$66 Def00002F
+S C$ax5051reset.c$61$1$66 Def000078
+S C$ax5051reset.c$52$1$66 Def00004A
+S C$ax5051reset.c$43$1$66 Def000033
+S C$ax5051reset.c$62$1$66 Def00007F
+S C$ax5051reset.c$53$1$66 Def000051
+S C$ax5051reset.c$35$1$66 Def000027
+S C$ax5051reset.c$17$1$66 Def000006
+S C$ax5051reset.c$70$1$68 Def000088
+S C$ax5051reset.c$63$1$66 Def000084
+S C$ax5051reset.c$54$1$66 Def000056
+S C$ax5051reset.c$45$1$66 Def000035
+S C$ax5051reset.c$36$1$66 Def00002D
+S C$ax5051reset.c$80$1$68 Def0000B8
+S C$ax5051reset.c$71$1$68 Def000090
+S C$ax5051reset.c$64$1$66 Def000087
+S C$ax5051reset.c$55$1$66 Def00005C
+S C$ax5051reset.c$46$1$66 Def00003F
+S C$ax5051reset.c$19$1$66 Def00000C
+S C$ax5051reset.c$72$1$68 Def000092
+S C$ax5051reset.c$56$1$66 Def000063
+S C$ax5051reset.c$73$1$68 Def000094
+S C$ax5051reset.c$81$2$69 Def0000BD
+S C$ax5051reset.c$74$1$68 Def000097
+S C$ax5051reset.c$67$1$66 Def000088
+S C$ax5051reset.c$58$1$66 Def000068
+S C$ax5051reset.c$91$2$69 Def0000D8
+S C$ax5051reset.c$82$2$69 Def0000C2
+S C$ax5051reset.c$75$1$68 Def00009E
+S C$ax5051reset.c$59$1$66 Def00006D
+S C$ax5051reset.c$94$1$68 Def0000E4
+S C$ax5051reset.c$92$2$69 Def0000DF
+S C$ax5051reset.c$83$2$69 Def0000CB
+S C$ax5051reset.c$76$1$68 Def0000A4
+S C$ax5051reset.c$95$1$68 Def0000E6
+S C$ax5051reset.c$93$2$69 Def0000E1
+S C$ax5051reset.c$77$1$68 Def0000A9
+S C$ax5051reset.c$85$2$69 Def0000CB
+S C$ax5051reset.c$78$1$68 Def0000AC
+S G$ax5051_reset$0$0 Def000000
+S C$ax5051reset.c$86$2$69 Def0000CD
+S C$ax5051reset.c$79$1$68 Def0000B2
+S G$ax5051_probeirq$0$0 Def000088
+S C$ax5051reset.c$87$2$69 Def0000D6
+S C$ax5051reset.c$89$2$69 Def0000D6
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 75 8E 15 75 8C EB 90 70 44 74 47 F0 75
+R 00 00 00 16
+T 00 00 0D B1 00 90 70 0C 74 01 F0 90 70 40 74 05
+R 00 00 00 16
+T 00 00 1A F0 E4 A3 F0 90 70 42 74 04 F0 E4 A3 F0
+R 00 00 00 16
+T 00 00 27 90 40 02 74 80 F0 E4 F0 90 40 00 E0 E0
+R 00 00 00 16
+T 00 00 34 FF BF 16 02 80 0A
+R 00 00 00 16
+T 00 00 3A
+R 00 00 00 16
+T 00 00 3A BF 14 02 80 05
+R 00 00 00 16
+T 00 00 3F
+R 00 00 00 16
+T 00 00 3F 75 82 01 80 43
+R 00 00 00 16
+T 00 00 44
+R 00 00 00 16
+T 00 00 44 90 40 01 74 55 F0 E0 FF BF 55 02 80 05
+R 00 00 00 16
+T 00 00 51
+R 00 00 00 16
+T 00 00 51 75 82 02 80 31
+R 00 00 00 16
+T 00 00 56
+R 00 00 00 16
+T 00 00 56 90 40 01 74 AA F0 E0 FF BF AA 02 80 05
+R 00 00 00 16
+T 00 00 63
+R 00 00 00 16
+T 00 00 63 75 82 02 80 1F
+R 00 00 00 16
+T 00 00 68
+R 00 00 00 16
+T 00 00 68 90 40 08 E4 F0 90 40 72 04 F0 90 40 7D
+R 00 00 00 16
+T 00 00 75 74 35 F0 12 00 88 E5 82 60 05 75 82 03
+R 00 00 00 16 00 07 00 16
+T 00 00 82 80 03
+R 00 00 00 16
+T 00 00 84
+R 00 00 00 16
+T 00 00 84 75 82 00
+R 00 00 00 16
+T 00 00 87
+R 00 00 00 16
+T 00 00 87 22
+R 00 00 00 16
+T 00 00 88
+R 00 00 00 16
+T 00 00 88 90 40 0C E0 FF 53 07 0F AE A8 C2 AC 75
+R 00 00 00 16
+T 00 00 95 8C EB 90 40 0C 74 D0 4F F0 90 40 0D 74
+R 00 00 00 16
+T 00 00 A2 F2 F0 74 60 55 8D FD 74 F0 F0 E5 8D F4
+R 00 00 00 16
+T 00 00 AF FC 52 05 90 40 0D 74 D0 F0 BD 20 02 80
+R 00 00 00 16
+T 00 00 BC 05
+R 00 00 00 16
+T 00 00 BD
+R 00 00 00 16
+T 00 00 BD BD 40 18 80 0B
+R 00 00 00 16
+T 00 00 C2
+R 00 00 00 16
+T 00 00 C2 90 70 44 E0 FC 74 F7 5C F0 80 19
+R 00 00 00 16
+T 00 00 CD
+R 00 00 00 16
+T 00 00 CD 90 70 44 E0 FC 74 08 4C F0 80 0E
+R 00 00 00 16
+T 00 00 D8
+R 00 00 00 16
+T 00 00 D8 90 40 0C 74 A0 4F F0 8E A8 75 82 01 80
+R 00 00 00 16
+T 00 00 E5 53
+R 00 00 00 16
+T 00 00 E6
+R 00 00 00 16
+T 00 00 E6 ED F4 52 8C C2 AF 90 40 0C 74 C0 4F F0
+R 00 00 00 16
+T 00 00 F3 90 40 0E E0 FC 53 04 01 90 40 0D E0 4C
+R 00 00 00 16
+T 00 01 00 F0 90 40 0C 74 80 4F F0 90 40 0E E0 FC
+R 00 00 00 16
+T 00 01 0D 53 04 04 90 40 0D E0 FB 4C F0 90 40 0C
+R 00 00 00 16
+T 00 01 1A EF F0 90 40 0E E0 FF 53 07 08 90 40 0D
+R 00 00 00 16
+T 00 01 27 E0 FC 4F F0 ED 42 A8 74 DF 45 8D 52 8C
+R 00 00 00 16
+T 00 01 34 8E A8 75 82 00
+R 00 00 00 16
+T 00 01 39
+R 00 00 00 16
+T 00 01 39 22
+R 00 00 00 16
+
+
+M:ax5051reset
+F:G$ax5051_reset$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5051reset.ax5051_reset$i$1$66({1}SC:U),R,0,0,[r7]
+F:G$ax5051_probeirq$0$0({2}DF,SC:U),Z,0,0,0,0,0
+S:Lax5051reset.ax5051_probeirq$p$1$68({1}SC:U),R,0,0,[r5]
+S:Lax5051reset.ax5051_probeirq$pc1$1$68({1}SC:U),R,0,0,[r7]
+S:Lax5051reset.ax5051_probeirq$iesave$1$68({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051deepsleep
+
+XH3
+H 1A areas 401 global symbols
+M ax5051deepsleep
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5051deepsleep
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051rclkena
+
+;!FILE libmflarge/ax5051rclkena.asm
+XH3
+H 1A areas 433 global symbols
+M ax5051rclkena
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 3D flags 20 addr 0
+S G$ax5051_rclk_enable$0$0 Def000000
+S _ax5051_rclk_enable Def000000
+S A$ax5051rclkena$1700 Def000036
+S A$ax5051rclkena$1701 Def000038
+S A$ax5051rclkena$1705 Def000039
+S A$ax5051rclkena$1660 Def000009
+S A$ax5051rclkena$1651 Def000002
+S A$ax5051rclkena$1706 Def00003A
+S A$ax5051rclkena$1670 Def000012
+S A$ax5051rclkena$1661 Def00000A
+S A$ax5051rclkena$1680 Def000021
+S A$ax5051rclkena$1662 Def00000C
+S A$ax5051rclkena$1653 Def000005
+S A$ax5051rclkena$1690 Def000029
+S A$ax5051rclkena$1709 Def00003C
+S A$ax5051rclkena$1691 Def00002A
+S A$ax5051rclkena$1673 Def000014
+S A$ax5051rclkena$1692 Def00002C
+S A$ax5051rclkena$1683 Def000022
+S A$ax5051rclkena$1674 Def000017
+S A$ax5051rclkena$1665 Def00000D
+S A$ax5051rclkena$1656 Def000007
+S A$ax5051rclkena$1693 Def00002E
+S A$ax5051rclkena$1675 Def000018
+S A$ax5051rclkena$1666 Def00000F
+S A$ax5051rclkena$1648 Def000000
+S XG$ax5051_rclk_enable$0$0 Def00003C
+S A$ax5051rclkena$1676 Def000019
+S A$ax5051rclkena$1667 Def000011
+S A$ax5051rclkena$1686 Def000025
+S A$ax5051rclkena$1677 Def00001C
+S A$ax5051rclkena$1687 Def000028
+S A$ax5051rclkena$1678 Def00001F
+S A$ax5051rclkena$1697 Def000030
+S A$ax5051rclkena$1679 Def000020
+S C$ax5051rclkena.c$10$1$64 Def000009
+S A$ax5051rclkena$1698 Def000032
+S C$ax5051rclkena.c$11$1$64 Def00000D
+S A$ax5051rclkena$1699 Def000033
+S C$ax5051rclkena.c$12$1$64 Def000012
+S C$ax5051rclkena.c$13$1$64 Def000014
+S C$ax5051rclkena.c$14$1$64 Def000022
+S C$ax5051rclkena.c$15$1$64 Def000025
+S C$ax5051rclkena.c$16$1$64 Def000029
+S C$ax5051rclkena.c$17$1$64 Def000030
+S C$ax5051rclkena.c$18$1$64 Def000039
+S C$ax5051rclkena.c$19$1$64 Def00003C
+S C$ax5051rclkena.c$8$1$64 Def000002
+S C$ax5051rclkena.c$9$1$64 Def000007
+S C$ax5051rclkena.c$5$0$0 Def000000
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 AF 82 BF 0B 00
+R 00 00 00 16
+T 00 00 05
+R 00 00 00 16
+T 00 00 05 40 02 7F 0B
+R 00 00 00 16
+T 00 00 09
+R 00 00 00 16
+T 00 00 09 EF 24 04 FF 74 80 55 A8 FE C2 AF 90
+R 00 00 00 16
+T 00 00 15 40 0C E0 FD 53 05 F0 90 40 0C EF 4D F0
+R 00 00 00 16
+T 00 00 22 53 8C FD 90 40 02 E0 FF 54 0F 60 02 80
+R 00 00 00 16
+T 00 00 2F 09
+R 00 00 00 16
+T 00 00 30
+R 00 00 00 16
+T 00 00 30 74 F0 5F 90 40 02 44 05 F0
+R 00 00 00 16
+T 00 00 39
+R 00 00 00 16
+T 00 00 39 EE 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rclkena
+F:G$ax5051_rclk_enable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rclkena.ax5051_rclk_enable$div$1$63({1}SC:U),R,0,0,[r7]
+S:Lax5051rclkena.ax5051_rclk_enable$p$1$64({1}SC:U),R,0,0,[r7]
+S:Lax5051rclkena.ax5051_rclk_enable$irqe$1$64({1}SC:U),R,0,0,[r6]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
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+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
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+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
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+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
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+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
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+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
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+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
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+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5051rclkdis
+
+;!FILE libmflarge/ax5051rclkdis.asm
+XH3
+H 1A areas 428 global symbols
+M ax5051rclkdis
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 2C flags 20 addr 0
+S _ax5051_rclk_disable Def000000
+S C$ax5051rclkdis.c$8$1$64 Def000000
+S C$ax5051rclkdis.c$9$1$64 Def000005
+S C$ax5051rclkdis.c$5$0$0 Def000000
+S XG$ax5051_rclk_disable$0$0 Def00002B
+S A$ax5051rclkdis$1650 Def000002
+S A$ax5051rclkdis$1660 Def00000A
+S A$ax5051rclkdis$1651 Def000004
+S A$ax5051rclkdis$1670 Def000018
+S A$ax5051rclkdis$1661 Def00000D
+S A$ax5051rclkdis$1680 Def000021
+S A$ax5051rclkdis$1671 Def000019
+S A$ax5051rclkdis$1662 Def00000E
+S A$ax5051rclkdis$1681 Def000024
+S A$ax5051rclkdis$1663 Def00000F
+S A$ax5051rclkdis$1654 Def000005
+S A$ax5051rclkdis$1691 Def00002B
+S A$ax5051rclkdis$1682 Def000026
+S A$ax5051rclkdis$1664 Def000011
+S A$ax5051rclkdis$1683 Def000027
+S A$ax5051rclkdis$1674 Def00001A
+S A$ax5051rclkdis$1665 Def000012
+S A$ax5051rclkdis$1675 Def00001C
+S A$ax5051rclkdis$1666 Def000014
+S A$ax5051rclkdis$1657 Def000007
+S A$ax5051rclkdis$1676 Def00001D
+S A$ax5051rclkdis$1649 Def000000
+S A$ax5051rclkdis$1677 Def00001E
+S A$ax5051rclkdis$1687 Def000028
+S A$ax5051rclkdis$1669 Def000015
+S A$ax5051rclkdis$1688 Def000029
+S C$ax5051rclkdis.c$10$1$64 Def000007
+S C$ax5051rclkdis.c$11$1$64 Def00000A
+S C$ax5051rclkdis.c$12$1$64 Def000015
+S C$ax5051rclkdis.c$13$1$64 Def00001A
+S C$ax5051rclkdis.c$14$1$64 Def000021
+S C$ax5051rclkdis.c$15$1$64 Def000028
+S G$ax5051_rclk_disable$0$0 Def000000
+S C$ax5051rclkdis.c$16$1$64 Def00002B
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 74 80 55 A8 FF C2 AF 43 8C 02 90 40 0C
+R 00 00 00 16
+T 00 00 0D E0 FE 74 F0 5E 44 01 F0 90 40 02 E0 FE
+R 00 00 00 16
+T 00 00 1A 74 0F 5E FD BD 05 07 90 40 02 74 F0 5E
+R 00 00 00 16
+T 00 00 27 F0
+R 00 00 00 16
+T 00 00 28
+R 00 00 00 16
+T 00 00 28 EF 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rclkdis
+F:G$ax5051_rclk_disable$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rclkdis.ax5051_rclk_disable$p$1$64({1}SC:U),R,0,0,[r6]
+S:Lax5051rclkdis.ax5051_rclk_disable$irqe$1$64({1}SC:U),R,0,0,[r7]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
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+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
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+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
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+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
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+S:G$OC0PIN$0$0({1}SC:U),I,0,0
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+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
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+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
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+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
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+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
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+S:G$T1CNT1$0$0({1}SC:U),I,0,0
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+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
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+S:G$T2STATUS$0$0({1}SC:U),I,0,0
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+S:G$U0SHREG$0$0({1}SC:U),I,0,0
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+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
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+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
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+S:G$ACC_7$0$0({1}SX:U),J,0,0
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+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+
+
+
+
+ax5051rdfifo
+
+;!FILE libmflarge/ax5051rdfifo.asm
+XH3
+H 1A areas 439 global symbols
+M ax5051rdfifo
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 54 flags 20 addr 0
+S A$ax5051rdfifo$1699 Def000050
+S C$ax5051rdfifo.c$10$0$0 Def000000
+S C$ax5051rdfifo.c$74$1$66 Def000000
+S C$ax5051rdfifo.c$75$1$66 Def000054
+S G$ax5051_readfifo$0$0 Def000000
+S _ax5051_readfifo Def000000
+S XG$ax5051_readfifo$0$0 Def000054
+S A$ax5051rdfifo$1700 Def000051
+S A$ax5051rdfifo$1701 Def000053
+S A$ax5051rdfifo$1650 Def00000C
+S A$ax5051rdfifo$1660 Def00001C
+S A$ax5051rdfifo$1651 Def00000F
+S A$ax5051rdfifo$1670 Def000025
+S A$ax5051rdfifo$1652 Def000011
+S A$ax5051rdfifo$1643 Def000000
+S A$ax5051rdfifo$1680 Def000034
+S A$ax5051rdfifo$1671 Def000027
+S A$ax5051rdfifo$1653 Def000014
+S A$ax5051rdfifo$1644 Def000002
+S A$ax5051rdfifo$1690 Def000043
+S A$ax5051rdfifo$1681 Def000036
+S A$ax5051rdfifo$1672 Def000028
+S A$ax5051rdfifo$1663 Def00001D
+S A$ax5051rdfifo$1645 Def000004
+S A$ax5051rdfifo$1691 Def000045
+S A$ax5051rdfifo$1682 Def000038
+S A$ax5051rdfifo$1673 Def00002A
+S A$ax5051rdfifo$1664 Def00001E
+S A$ax5051rdfifo$1655 Def000017
+S A$ax5051rdfifo$1646 Def000005
+S A$ax5051rdfifo$1692 Def000048
+S A$ax5051rdfifo$1683 Def000039
+S A$ax5051rdfifo$1674 Def00002C
+S A$ax5051rdfifo$1665 Def00001F
+S A$ax5051rdfifo$1656 Def000018
+S A$ax5051rdfifo$1647 Def000006
+S A$ax5051rdfifo$1684 Def00003B
+S A$ax5051rdfifo$1675 Def00002F
+S A$ax5051rdfifo$1666 Def000020
+S A$ax5051rdfifo$1657 Def000019
+S A$ax5051rdfifo$1648 Def000008
+S A$ax5051rdfifo$1694 Def00004A
+S A$ax5051rdfifo$1667 Def000022
+S A$ax5051rdfifo$1658 Def00001A
+S A$ax5051rdfifo$1649 Def000009
+S A$ax5051rdfifo$1686 Def00003C
+S A$ax5051rdfifo$1677 Def000031
+S A$ax5051rdfifo$1696 Def00004B
+S A$ax5051rdfifo$1687 Def00003E
+S A$ax5051rdfifo$1678 Def000032
+S A$ax5051rdfifo$1669 Def000023
+S A$ax5051rdfifo$1697 Def00004C
+S A$ax5051rdfifo$1688 Def000040
+S A$ax5051rdfifo$1679 Def000033
+S A$ax5051rdfifo$1698 Def00004E
+S A$ax5051rdfifo$1689 Def000041
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+T 00 00 00
+R 00 00 00 16
+T 00 00 00 E5 81 24 FE F8 E6 60 14 FF 20 F7 30 30
+R 00 00 00 16
+T 00 00 0D F6 14 A8 82 90 40 05 20 F5 06
+R 00 00 00 16
+T 00 00 17
+R 00 00 00 16
+T 00 00 17 E0 F6 08 DF FB
+R 00 00 00 16
+T 00 00 1C
+R 00 00 00 16
+T 00 00 1C 22
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D
+R 00 00 00 16
+T 00 00 1D E0 F2 08 DF FB 22
+R 00 00 00 16
+T 00 00 23
+R 00 00 00 16
+T 00 00 23 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 30 05
+R 00 00 00 16
+T 00 00 31
+R 00 00 00 16
+T 00 00 31 E2 F0 A3 DF FB 8E D9 ED 42 A8 22
+R 00 00 00 16
+T 00 00 3C
+R 00 00 00 16
+T 00 00 3C 74 80 55 A8 FD C2 AF AE D9 75 D9 40 78
+R 00 00 00 16
+T 00 00 49 05
+R 00 00 00 16
+T 00 00 4A
+R 00 00 00 16
+T 00 00 4A E2 A3 DF FC 8E D9 ED 42 A8 22
+R 00 00 00 16
+
+
+M:ax5051rdfifo
+F:G$ax5051_readfifo$0$0({2}DF,SV:S),Z,0,0,0,0,0
+S:Lax5051rdfifo.ax5051_readfifo$len$1$65({1}SC:U),B,1,-3
+S:Lax5051rdfifo.ax5051_readfifo$ptr$1$65({3}DG,SC:U),R,0,0,[]
+S:G$random_seed$0$0({2}SI:U),E,0,0
+S:G$ADCCH0VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH0VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH1VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH1VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH2VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH2VAL$0$0({2}SI:U),F,0,0
+S:G$ADCCH3VAL0$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL1$0$0({1}SC:U),F,0,0
+S:G$ADCCH3VAL$0$0({2}SI:U),F,0,0
+S:G$ADCTUNE0$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE1$0$0({1}SC:U),F,0,0
+S:G$ADCTUNE2$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA0ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA0CONFIG$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR0$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR1$0$0({1}SC:U),F,0,0
+S:G$DMA1ADDR$0$0({2}SI:U),F,0,0
+S:G$DMA1CONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$FRCOSCCTRL$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$FRCOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$FRCOSCPER0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCPER$0$0({2}SI:U),F,0,0
+S:G$FRCOSCREF0$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF1$0$0({1}SC:U),F,0,0
+S:G$FRCOSCREF$0$0({2}SI:U),F,0,0
+S:G$ANALOGA$0$0({1}SC:U),F,0,0
+S:G$GPIOENABLE$0$0({1}SC:U),F,0,0
+S:G$EXTIRQ$0$0({1}SC:U),F,0,0
+S:G$INTCHGA$0$0({1}SC:U),F,0,0
+S:G$INTCHGB$0$0({1}SC:U),F,0,0
+S:G$INTCHGC$0$0({1}SC:U),F,0,0
+S:G$PALTA$0$0({1}SC:U),F,0,0
+S:G$PALTB$0$0({1}SC:U),F,0,0
+S:G$PALTC$0$0({1}SC:U),F,0,0
+S:G$PALTRADIO$0$0({1}SC:U),F,0,0
+S:G$PINCHGA$0$0({1}SC:U),F,0,0
+S:G$PINCHGB$0$0({1}SC:U),F,0,0
+S:G$PINCHGC$0$0({1}SC:U),F,0,0
+S:G$PINSEL$0$0({1}SC:U),F,0,0
+S:G$LPOSCCONFIG$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ0$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ1$0$0({1}SC:U),F,0,0
+S:G$LPOSCFREQ$0$0({2}SI:U),F,0,0
+S:G$LPOSCKFILT0$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT1$0$0({1}SC:U),F,0,0
+S:G$LPOSCKFILT$0$0({2}SI:U),F,0,0
+S:G$LPOSCPER0$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER1$0$0({1}SC:U),F,0,0
+S:G$LPOSCPER$0$0({2}SI:U),F,0,0
+S:G$LPOSCREF0$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF1$0$0({1}SC:U),F,0,0
+S:G$LPOSCREF$0$0({2}SI:U),F,0,0
+S:G$LPXOSCGM$0$0({1}SC:U),F,0,0
+S:G$MISCCTRL$0$0({1}SC:U),F,0,0
+S:G$OSCCALIB$0$0({1}SC:U),F,0,0
+S:G$OSCFORCERUN$0$0({1}SC:U),F,0,0
+S:G$OSCREADY$0$0({1}SC:U),F,0,0
+S:G$OSCRUN$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFDATAADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOFSTATADDR0$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR1$0$0({1}SC:U),F,0,0
+S:G$RADIOFSTATADDR$0$0({2}SI:U),F,0,0
+S:G$RADIOMUX$0$0({1}SC:U),F,0,0
+S:G$SCRATCH0$0$0({1}SC:U),F,0,0
+S:G$SCRATCH1$0$0({1}SC:U),F,0,0
+S:G$SCRATCH2$0$0({1}SC:U),F,0,0
+S:G$SCRATCH3$0$0({1}SC:U),F,0,0
+S:G$SILICONREV$0$0({1}SC:U),F,0,0
+S:G$XTALAMPL$0$0({1}SC:U),F,0,0
+S:G$XTALOSC$0$0({1}SC:U),F,0,0
+S:G$XTALREADY$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACK$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTER$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAY$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGET$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFT$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FEC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEM$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUS$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNC$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNT$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATA$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESH$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMING$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSION$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASK$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUEST$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATION$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAIN$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOP$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGING$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLK$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOI$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_REF$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISC$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCH$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISION$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHI$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELO$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMID$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODE$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWR$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREG$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAP$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSC$0$0({1}SC:U),F,0,0
+S:G$AX5051_ADCMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCATTACKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCCOUNTERNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCDECAYNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AGCTARGETNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_AMPLITUDEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICDECLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CICSHIFTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_CRCINIT3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DATARATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_DSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_ENCODINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECMEMNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSTATUSNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FECSYNCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROLNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCONTROL2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOCOUNTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFODATANB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FIFOTHRESHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FRAMINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQ3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQA3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FREQUENCYGAIN2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV0NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_FSKDEV2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IFMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQINVERSIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQMASKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_IRQREQUESTNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_MODULATORMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG1NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG2NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PINCFG3NB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLLOOPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRANGINGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PWRMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_REFNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RFMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_RXMISCNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SCRATCHNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_SILICONREVISIONNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TIMINGGAINLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKAMPLITUDELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKFREQLONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TRKPHASELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATEMIDNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXPWRNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
+S:G$ACC$0$0({1}SC:U),I,0,0
+S:G$B$0$0({1}SC:U),I,0,0
+S:G$DPH$0$0({1}SC:U),I,0,0
+S:G$DPH1$0$0({1}SC:U),I,0,0
+S:G$DPL$0$0({1}SC:U),I,0,0
+S:G$DPL1$0$0({1}SC:U),I,0,0
+S:G$DPTR0$0$0({2}SI:U),I,0,0
+S:G$DPTR1$0$0({2}SI:U),I,0,0
+S:G$DPS$0$0({1}SC:U),I,0,0
+S:G$E2IE$0$0({1}SC:U),I,0,0
+S:G$E2IP$0$0({1}SC:U),I,0,0
+S:G$EIE$0$0({1}SC:U),I,0,0
+S:G$EIP$0$0({1}SC:U),I,0,0
+S:G$IE$0$0({1}SC:U),I,0,0
+S:G$IP$0$0({1}SC:U),I,0,0
+S:G$PCON$0$0({1}SC:U),I,0,0
+S:G$PSW$0$0({1}SC:U),I,0,0
+S:G$SP$0$0({1}SC:U),I,0,0
+S:G$XPAGE$0$0({1}SC:U),I,0,0
+S:G$_XPAGE$0$0({1}SC:U),I,0,0
+S:G$ADCCH0CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH1CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH2CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCH3CONFIG$0$0({1}SC:U),I,0,0
+S:G$ADCCLKSRC$0$0({1}SC:U),I,0,0
+S:G$ADCCONV$0$0({1}SC:U),I,0,0
+S:G$ANALOGCOMP$0$0({1}SC:U),I,0,0
+S:G$CLKCON$0$0({1}SC:U),I,0,0
+S:G$CLKSTAT$0$0({1}SC:U),I,0,0
+S:G$CODECONFIG$0$0({1}SC:U),I,0,0
+S:G$DBGLNKBUF$0$0({1}SC:U),I,0,0
+S:G$DBGLNKSTAT$0$0({1}SC:U),I,0,0
+S:G$DIRA$0$0({1}SC:U),I,0,0
+S:G$DIRB$0$0({1}SC:U),I,0,0
+S:G$DIRC$0$0({1}SC:U),I,0,0
+S:G$DIRR$0$0({1}SC:U),I,0,0
+S:G$PINA$0$0({1}SC:U),I,0,0
+S:G$PINB$0$0({1}SC:U),I,0,0
+S:G$PINC$0$0({1}SC:U),I,0,0
+S:G$PINR$0$0({1}SC:U),I,0,0
+S:G$PORTA$0$0({1}SC:U),I,0,0
+S:G$PORTB$0$0({1}SC:U),I,0,0
+S:G$PORTC$0$0({1}SC:U),I,0,0
+S:G$PORTR$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC0CAPT$0$0({2}SI:U),I,0,0
+S:G$IC0MODE$0$0({1}SC:U),I,0,0
+S:G$IC0STATUS$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT0$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT1$0$0({1}SC:U),I,0,0
+S:G$IC1CAPT$0$0({2}SI:U),I,0,0
+S:G$IC1MODE$0$0({1}SC:U),I,0,0
+S:G$IC1STATUS$0$0({1}SC:U),I,0,0
+S:G$NVADDR0$0$0({1}SC:U),I,0,0
+S:G$NVADDR1$0$0({1}SC:U),I,0,0
+S:G$NVADDR$0$0({2}SI:U),I,0,0
+S:G$NVDATA0$0$0({1}SC:U),I,0,0
+S:G$NVDATA1$0$0({1}SC:U),I,0,0
+S:G$NVDATA$0$0({2}SI:U),I,0,0
+S:G$NVKEY$0$0({1}SC:U),I,0,0
+S:G$NVSTATUS$0$0({1}SC:U),I,0,0
+S:G$OC0COMP0$0$0({1}SC:U),I,0,0
+S:G$OC0COMP1$0$0({1}SC:U),I,0,0
+S:G$OC0COMP$0$0({2}SI:U),I,0,0
+S:G$OC0MODE$0$0({1}SC:U),I,0,0
+S:G$OC0PIN$0$0({1}SC:U),I,0,0
+S:G$OC0STATUS$0$0({1}SC:U),I,0,0
+S:G$OC1COMP0$0$0({1}SC:U),I,0,0
+S:G$OC1COMP1$0$0({1}SC:U),I,0,0
+S:G$OC1COMP$0$0({2}SI:U),I,0,0
+S:G$OC1MODE$0$0({1}SC:U),I,0,0
+S:G$OC1PIN$0$0({1}SC:U),I,0,0
+S:G$OC1STATUS$0$0({1}SC:U),I,0,0
+S:G$RADIOACC$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR0$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR1$0$0({1}SC:U),I,0,0
+S:G$RADIOADDR$0$0({2}SI:U),I,0,0
+S:G$RADIODATA0$0$0({1}SC:U),I,0,0
+S:G$RADIODATA1$0$0({1}SC:U),I,0,0
+S:G$RADIODATA2$0$0({1}SC:U),I,0,0
+S:G$RADIODATA3$0$0({1}SC:U),I,0,0
+S:G$RADIODATA$0$0({4}SL:U),I,0,0
+S:G$RADIOSTAT0$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT1$0$0({1}SC:U),I,0,0
+S:G$RADIOSTAT$0$0({2}SI:U),I,0,0
+S:G$SPCLKSRC$0$0({1}SC:U),I,0,0
+S:G$SPMODE$0$0({1}SC:U),I,0,0
+S:G$SPSHREG$0$0({1}SC:U),I,0,0
+S:G$SPSTATUS$0$0({1}SC:U),I,0,0
+S:G$T0CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T0CNT0$0$0({1}SC:U),I,0,0
+S:G$T0CNT1$0$0({1}SC:U),I,0,0
+S:G$T0CNT$0$0({2}SI:U),I,0,0
+S:G$T0MODE$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T0PERIOD$0$0({2}SI:U),I,0,0
+S:G$T0STATUS$0$0({1}SC:U),I,0,0
+S:G$T1CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T1CNT0$0$0({1}SC:U),I,0,0
+S:G$T1CNT1$0$0({1}SC:U),I,0,0
+S:G$T1CNT$0$0({2}SI:U),I,0,0
+S:G$T1MODE$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T1PERIOD$0$0({2}SI:U),I,0,0
+S:G$T1STATUS$0$0({1}SC:U),I,0,0
+S:G$T2CLKSRC$0$0({1}SC:U),I,0,0
+S:G$T2CNT0$0$0({1}SC:U),I,0,0
+S:G$T2CNT1$0$0({1}SC:U),I,0,0
+S:G$T2CNT$0$0({2}SI:U),I,0,0
+S:G$T2MODE$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD0$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD1$0$0({1}SC:U),I,0,0
+S:G$T2PERIOD$0$0({2}SI:U),I,0,0
+S:G$T2STATUS$0$0({1}SC:U),I,0,0
+S:G$U0CTRL$0$0({1}SC:U),I,0,0
+S:G$U0MODE$0$0({1}SC:U),I,0,0
+S:G$U0SHREG$0$0({1}SC:U),I,0,0
+S:G$U0STATUS$0$0({1}SC:U),I,0,0
+S:G$U1CTRL$0$0({1}SC:U),I,0,0
+S:G$U1MODE$0$0({1}SC:U),I,0,0
+S:G$U1SHREG$0$0({1}SC:U),I,0,0
+S:G$U1STATUS$0$0({1}SC:U),I,0,0
+S:G$WDTCFG$0$0({1}SC:U),I,0,0
+S:G$WDTRESET$0$0({1}SC:U),I,0,0
+S:G$WTCFGA$0$0({1}SC:U),I,0,0
+S:G$WTCFGB$0$0({1}SC:U),I,0,0
+S:G$WTCNTA0$0$0({1}SC:U),I,0,0
+S:G$WTCNTA1$0$0({1}SC:U),I,0,0
+S:G$WTCNTA$0$0({2}SI:U),I,0,0
+S:G$WTCNTB0$0$0({1}SC:U),I,0,0
+S:G$WTCNTB1$0$0({1}SC:U),I,0,0
+S:G$WTCNTB$0$0({2}SI:U),I,0,0
+S:G$WTCNTR1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA0$0$0({1}SC:U),I,0,0
+S:G$WTEVTA1$0$0({1}SC:U),I,0,0
+S:G$WTEVTA$0$0({2}SI:U),I,0,0
+S:G$WTEVTB0$0$0({1}SC:U),I,0,0
+S:G$WTEVTB1$0$0({1}SC:U),I,0,0
+S:G$WTEVTB$0$0({2}SI:U),I,0,0
+S:G$WTEVTC0$0$0({1}SC:U),I,0,0
+S:G$WTEVTC1$0$0({1}SC:U),I,0,0
+S:G$WTEVTC$0$0({2}SI:U),I,0,0
+S:G$WTEVTD0$0$0({1}SC:U),I,0,0
+S:G$WTEVTD1$0$0({1}SC:U),I,0,0
+S:G$WTEVTD$0$0({2}SI:U),I,0,0
+S:G$WTIRQEN$0$0({1}SC:U),I,0,0
+S:G$WTSTAT$0$0({1}SC:U),I,0,0
+S:G$ACC_0$0$0({1}SX:U),J,0,0
+S:G$ACC_1$0$0({1}SX:U),J,0,0
+S:G$ACC_2$0$0({1}SX:U),J,0,0
+S:G$ACC_3$0$0({1}SX:U),J,0,0
+S:G$ACC_4$0$0({1}SX:U),J,0,0
+S:G$ACC_5$0$0({1}SX:U),J,0,0
+S:G$ACC_6$0$0({1}SX:U),J,0,0
+S:G$ACC_7$0$0({1}SX:U),J,0,0
+S:G$B_0$0$0({1}SX:U),J,0,0
+S:G$B_1$0$0({1}SX:U),J,0,0
+S:G$B_2$0$0({1}SX:U),J,0,0
+S:G$B_3$0$0({1}SX:U),J,0,0
+S:G$B_4$0$0({1}SX:U),J,0,0
+S:G$B_5$0$0({1}SX:U),J,0,0
+S:G$B_6$0$0({1}SX:U),J,0,0
+S:G$B_7$0$0({1}SX:U),J,0,0
+S:G$E2IE_0$0$0({1}SX:U),J,0,0
+S:G$E2IE_1$0$0({1}SX:U),J,0,0
+S:G$E2IE_2$0$0({1}SX:U),J,0,0
+S:G$E2IE_3$0$0({1}SX:U),J,0,0
+S:G$E2IE_4$0$0({1}SX:U),J,0,0
+S:G$E2IE_5$0$0({1}SX:U),J,0,0
+S:G$E2IE_6$0$0({1}SX:U),J,0,0
+S:G$E2IE_7$0$0({1}SX:U),J,0,0
+S:G$E2IP_0$0$0({1}SX:U),J,0,0
+S:G$E2IP_1$0$0({1}SX:U),J,0,0
+S:G$E2IP_2$0$0({1}SX:U),J,0,0
+S:G$E2IP_3$0$0({1}SX:U),J,0,0
+S:G$E2IP_4$0$0({1}SX:U),J,0,0
+S:G$E2IP_5$0$0({1}SX:U),J,0,0
+S:G$E2IP_6$0$0({1}SX:U),J,0,0
+S:G$E2IP_7$0$0({1}SX:U),J,0,0
+S:G$EIE_0$0$0({1}SX:U),J,0,0
+S:G$EIE_1$0$0({1}SX:U),J,0,0
+S:G$EIE_2$0$0({1}SX:U),J,0,0
+S:G$EIE_3$0$0({1}SX:U),J,0,0
+S:G$EIE_4$0$0({1}SX:U),J,0,0
+S:G$EIE_5$0$0({1}SX:U),J,0,0
+S:G$EIE_6$0$0({1}SX:U),J,0,0
+S:G$EIE_7$0$0({1}SX:U),J,0,0
+S:G$EIP_0$0$0({1}SX:U),J,0,0
+S:G$EIP_1$0$0({1}SX:U),J,0,0
+S:G$EIP_2$0$0({1}SX:U),J,0,0
+S:G$EIP_3$0$0({1}SX:U),J,0,0
+S:G$EIP_4$0$0({1}SX:U),J,0,0
+S:G$EIP_5$0$0({1}SX:U),J,0,0
+S:G$EIP_6$0$0({1}SX:U),J,0,0
+S:G$EIP_7$0$0({1}SX:U),J,0,0
+S:G$IE_0$0$0({1}SX:U),J,0,0
+S:G$IE_1$0$0({1}SX:U),J,0,0
+S:G$IE_2$0$0({1}SX:U),J,0,0
+S:G$IE_3$0$0({1}SX:U),J,0,0
+S:G$IE_4$0$0({1}SX:U),J,0,0
+S:G$IE_5$0$0({1}SX:U),J,0,0
+S:G$IE_6$0$0({1}SX:U),J,0,0
+S:G$IE_7$0$0({1}SX:U),J,0,0
+S:G$EA$0$0({1}SX:U),J,0,0
+S:G$IP_0$0$0({1}SX:U),J,0,0
+S:G$IP_1$0$0({1}SX:U),J,0,0
+S:G$IP_2$0$0({1}SX:U),J,0,0
+S:G$IP_3$0$0({1}SX:U),J,0,0
+S:G$IP_4$0$0({1}SX:U),J,0,0
+S:G$IP_5$0$0({1}SX:U),J,0,0
+S:G$IP_6$0$0({1}SX:U),J,0,0
+S:G$IP_7$0$0({1}SX:U),J,0,0
+S:G$P$0$0({1}SX:U),J,0,0
+S:G$F1$0$0({1}SX:U),J,0,0
+S:G$OV$0$0({1}SX:U),J,0,0
+S:G$RS0$0$0({1}SX:U),J,0,0
+S:G$RS1$0$0({1}SX:U),J,0,0
+S:G$F0$0$0({1}SX:U),J,0,0
+S:G$AC$0$0({1}SX:U),J,0,0
+S:G$CY$0$0({1}SX:U),J,0,0
+S:G$PINA_0$0$0({1}SX:U),J,0,0
+S:G$PINA_1$0$0({1}SX:U),J,0,0
+S:G$PINA_2$0$0({1}SX:U),J,0,0
+S:G$PINA_3$0$0({1}SX:U),J,0,0
+S:G$PINA_4$0$0({1}SX:U),J,0,0
+S:G$PINA_5$0$0({1}SX:U),J,0,0
+S:G$PINA_6$0$0({1}SX:U),J,0,0
+S:G$PINA_7$0$0({1}SX:U),J,0,0
+S:G$PINB_0$0$0({1}SX:U),J,0,0
+S:G$PINB_1$0$0({1}SX:U),J,0,0
+S:G$PINB_2$0$0({1}SX:U),J,0,0
+S:G$PINB_3$0$0({1}SX:U),J,0,0
+S:G$PINB_4$0$0({1}SX:U),J,0,0
+S:G$PINB_5$0$0({1}SX:U),J,0,0
+S:G$PINB_6$0$0({1}SX:U),J,0,0
+S:G$PINB_7$0$0({1}SX:U),J,0,0
+S:G$PINC_0$0$0({1}SX:U),J,0,0
+S:G$PINC_1$0$0({1}SX:U),J,0,0
+S:G$PINC_2$0$0({1}SX:U),J,0,0
+S:G$PINC_3$0$0({1}SX:U),J,0,0
+S:G$PINC_4$0$0({1}SX:U),J,0,0
+S:G$PINC_5$0$0({1}SX:U),J,0,0
+S:G$PINC_6$0$0({1}SX:U),J,0,0
+S:G$PINC_7$0$0({1}SX:U),J,0,0
+S:G$PORTA_0$0$0({1}SX:U),J,0,0
+S:G$PORTA_1$0$0({1}SX:U),J,0,0
+S:G$PORTA_2$0$0({1}SX:U),J,0,0
+S:G$PORTA_3$0$0({1}SX:U),J,0,0
+S:G$PORTA_4$0$0({1}SX:U),J,0,0
+S:G$PORTA_5$0$0({1}SX:U),J,0,0
+S:G$PORTA_6$0$0({1}SX:U),J,0,0
+S:G$PORTA_7$0$0({1}SX:U),J,0,0
+S:G$PORTB_0$0$0({1}SX:U),J,0,0
+S:G$PORTB_1$0$0({1}SX:U),J,0,0
+S:G$PORTB_2$0$0({1}SX:U),J,0,0
+S:G$PORTB_3$0$0({1}SX:U),J,0,0
+S:G$PORTB_4$0$0({1}SX:U),J,0,0
+S:G$PORTB_5$0$0({1}SX:U),J,0,0
+S:G$PORTB_6$0$0({1}SX:U),J,0,0
+S:G$PORTB_7$0$0({1}SX:U),J,0,0
+S:G$PORTC_0$0$0({1}SX:U),J,0,0
+S:G$PORTC_1$0$0({1}SX:U),J,0,0
+S:G$PORTC_2$0$0({1}SX:U),J,0,0
+S:G$PORTC_3$0$0({1}SX:U),J,0,0
+S:G$PORTC_4$0$0({1}SX:U),J,0,0
+S:G$PORTC_5$0$0({1}SX:U),J,0,0
+S:G$PORTC_6$0$0({1}SX:U),J,0,0
+S:G$PORTC_7$0$0({1}SX:U),J,0,0
+S:G$delay$0$0({2}DF,SV:S),C,0,0
+S:G$random$0$0({2}DF,SI:U),C,0,0
+S:G$signextend12$0$0({2}DF,SL:S),C,0,0
+S:G$signextend16$0$0({2}DF,SL:S),C,0,0
+S:G$signextend20$0$0({2}DF,SL:S),C,0,0
+S:G$signextend24$0$0({2}DF,SL:S),C,0,0
+S:G$hweight8$0$0({2}DF,SC:U),C,0,0
+S:G$hweight16$0$0({2}DF,SC:U),C,0,0
+S:G$hweight32$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit16$0$0({2}DF,SI:S),C,0,0
+S:G$checksignedlimit16$0$0({2}DF,SC:U),C,0,0
+S:G$signedlimit32$0$0({2}DF,SL:S),C,0,0
+S:G$checksignedlimit32$0$0({2}DF,SC:U),C,0,0
+S:G$gray_encode8$0$0({2}DF,SC:U),C,0,0
+S:G$gray_decode8$0$0({2}DF,SC:U),C,0,0
+S:G$rev8$0$0({2}DF,SC:U),C,0,0
+S:G$fmemset$0$0({2}DF,SV:S),C,0,0
+S:G$fmemcpy$0$0({2}DF,SV:S),C,0,0
+S:G$wtimer_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_standby$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep$0$0({2}DF,SV:S),C,0,0
+S:G$enter_sleep_cont$0$0({2}DF,SV:S),C,0,0
+S:G$enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$reset_cpu$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_xosc$0$0({2}DF,SV:S),C,0,0
+S:G$turn_off_lpxosc$0$0({2}DF,SV:S),C,0,0
+S:G$radio_read16$0$0({2}DF,SI:U),C,0,0
+S:G$radio_read24$0$0({2}DF,SL:U),C,0,0
+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051wrfifo
+
+;!FILE libmflarge/ax5051wrfifo.asm
+XH3
+H 1A areas 43B global symbols
+M ax5051wrfifo
+O -mmcs51 --model-large
+S G$AX5051_PINCFG3$0$0 Def00400E
+S G$LPXOSCGM$0$0 Def007054
+S G$IP_5$0$0 Def0000BD
+S G$EIP_0$0$0 Def0000B0
+S _MISCCTRL Def007F01
+S _AX5051_FREQ0 Def004023
+S _AX5051_PWRMODE Def004002
+S _AX5051_XTALOSC Def004003
+S _AX5051_FECNB Def005018
+S _AX5051_IFFREQHINB Def005028
+S _ANALOGCOMP Def0000E1
+S _DIRB Def00008A
+S _IC0MODE Def0000CC
+S _IC1STATUS Def0000D5
+S _OC0COMP0 Def0000BC
+S _E2IP_2 Def0000C2
+S _IE_4 Def0000AC
+S G$AX5051_AGCCOUNTER$0$0 Def00403C
+S G$XTALREADY$0$0 Def007F1A
+S G$FRCOSCFREQ$0$0 Def007076
+S G$IP_6$0$0 Def0000BE
+S G$EIP_1$0$0 Def0000B1
+S G$NVDATA0$0$0 Def000094
+S G$DBGLNKSTAT$0$0 Def0000E2
+S _AX5051_FREQ1 Def004022
+S _AX5051_FREQA0 Def004023
+S _DIRC Def00008B
+S _IC1MODE Def0000D4
+S _OC0COMP1 Def0000BD
+S _OC1COMP0 Def0000C4
+S _E2IP_3 Def0000C3
+S _EIE_0 Def000098
+S _IE_5 Def0000AD
+S G$AX5051_CICDECHI$0$0 Def00403E
+S G$LPOSCFREQ$0$0 Def007066
+S G$IP_7$0$0 Def0000BF
+S G$EIP_2$0$0 Def0000B2
+S G$NVDATA1$0$0 Def000095
+S G$NVADDR0$0$0 Def000092
+S _XTALAMPL Def007F19
+S _AX5051_FREQ2 Def004021
+S _AX5051_FREQA1 Def004022
+S _AX5051_PHASEGAINNB Def005044
+S _SP Def000081
+S _OC1COMP1 Def0000C5
+S _E2IP_4 Def0000C4
+S _EIE_1 Def000099
+S _IE_6 Def0000AE
+S G$AX5051_REFNB$0$0 Def00507C
+S G$AX5051_FIFOCOUNT$0$0 Def004035
+S G$AX5051_FECMEM$0$0 Def00406F
+S G$EIP_3$0$0 Def0000B3
+S G$NVADDR1$0$0 Def000093
+S G$PCON$0$0 Def000087
+S _AX5051_DATARATELO Def004041
+S _AX5051_FREQ3 Def004020
+S _AX5051_FREQA2 Def004021
+S _AX5051_FREQUENCYGAINNB Def005045
+S _AX5051_TXBITRATEMIDNB Def005032
+S _IC0CAPT Def00CFCE
+S _E2IP_5 Def0000C5
+S _EIE_2 Def00009A
+S _IE_7 Def0000AF
+S G$AX5051_XTALOSCNB$0$0 Def005003
+S G$AX5051_PWRMODENB$0$0 Def005002
+S G$AX5051_FREQ0NB$0$0 Def005023
+S G$AX5051_PLLRANGING$0$0 Def00402D
+S G$EIP_4$0$0 Def0000B4
+S G$OC0COMP$0$0 Def00BDBC
+S G$DIRR$0$0 Def00008E
+S _AX5051_FREQA3 Def004020
+S _AX5051_PLLLOOP Def00402C
+S _AX5051_AGCTARGETNB Def005039
+S _AX5051_TXBITRATELONB Def005033
+S _IC1CAPT Def00D7D6
+S _SPCLKSRC Def0000DF
+S _E2IP_6 Def0000C6
+S _EIE_3 Def00009B
+S _OV Def0000D2
+S G$AX5051_FREQA0NB$0$0 Def005023
+S G$AX5051_FREQ1NB$0$0 Def005022
+S G$PALTA$0$0 Def007008
+S G$EIP_5$0$0 Def0000B5
+S G$WDTRESET$0$0 Def0000DB
+S G$OC1COMP$0$0 Def00C5C4
+S _ADCCH0VAL Def007020
+S _AX5051_MODULATORMISC Def004034
+S _OC0STATUS Def0000BB
+S _E2IP_7 Def0000C7
+S _EIE_4 Def00009C
+S G$AX5051_FREQA1NB$0$0 Def005022
+S G$AX5051_FREQ2NB$0$0 Def005021
+S G$AX5051_TRKFREQHI$0$0 Def00404C
+S G$PALTB$0$0 Def007009
+S G$ANALOGA$0$0 Def007007
+S G$EIP_6$0$0 Def0000B6
+S _ADCCH1VAL Def007022
+S _FRCOSCPER Def007078
+S _DPS Def000086
+S _OC0MODE Def0000B9
+S _OC1STATUS Def0000C3
+S _WTSTAT Def0000EA
+S _EIE_5 Def00009D
+S G$AX5051_FREQA2NB$0$0 Def005021
+S G$AX5051_FREQ3NB$0$0 Def005020
+S G$AX5051_DATARATELONB$0$0 Def005041
+S G$AX5051_TRKAMPLITUDELO$0$0 Def004049
+S G$AX5051_AGCDECAY$0$0 Def00403B
+S G$PALTC$0$0 Def00700A
+S G$ADCTUNE0$0$0 Def007028
+S G$EIP_7$0$0 Def0000B7
+S _ADCCH2VAL Def007024
+S _LPOSCPER Def007068
+S _AX5051_TXPWR Def004030
+S _AX5051_IRQREQUESTNB Def005007
+S _PINA Def0000C8
+S _OC1MODE Def0000C1
+S _T0STATUS Def00009B
+S _EIE_6 Def00009E
+S _IP_0 Def0000B8
+S G$AX5051_PLLLOOPNB$0$0 Def00502C
+S G$AX5051_FREQA3NB$0$0 Def005020
+S G$AX5051_FIFOTHRESH$0$0 Def004036
+S G$AX5051_FECSTATUS$0$0 Def00401A
+S G$FRCOSCCTRL$0$0 Def007071
+S G$ADCTUNE1$0$0 Def007029
+S G$XPAGE$0$0 Def0000D9
+S _ADCCH3VAL Def007026
+S _RADIOMUX Def007044
+S _AX5051_RXMISCNB Def00507D
+S _PINB Def0000E8
+S _OC0PIN Def0000BA
+S _T0CNT Def009D9C
+S _T0MODE Def000099
+S _T1STATUS Def0000A3
+S _U0STATUS Def0000E5
+S _EIE_7 Def00009F
+S _IP_1 Def0000B9
+S G$AX5051_MODULATORMISCNB$0$0 Def005034
+S G$AX5051_TRKPHASEHI$0$0 Def00404A
+S G$AX5051_FSKDEV0$0$0 Def004027
+S G$FRCOSCCONFIG$0$0 Def007070
+S G$ADCTUNE2$0$0 Def00702A
+S G$F0$0$0 Def0000D5
+S G$RADIOACC$0$0 Def0000B1
+S _FRCOSCKFILT0 Def007072
+S _RADIOFDATAADDR Def007040
+S _AX5051_TRKAMPLITUDEHI Def004048
+S _AX5051_DATARATEHINB Def005040
+S _DPTR0 Def008382
+S _PINC Def0000F8
+S _OC1PIN Def0000C2
+S _T1CNT Def00A5A4
+S _T1MODE Def0000A1
+S _T2STATUS Def0000AB
+S _U0MODE Def0000E7
+S _U1STATUS Def0000ED
+S _WTIRQEN Def0000E9
+S _IP_2 Def0000BA
+S G$AX5051_VREG$0$0 Def00401B
+S G$AX5051_IFMODE$0$0 Def004008
+S G$AX5051_FSKDEV1$0$0 Def004026
+S G$AX5051_ADCMISC$0$0 Def004038
+S G$LPOSCCONFIG$0$0 Def007060
+S G$PINA_0$0$0 Def0000C8
+S G$F1$0$0 Def0000D1
+S G$T0PERIOD0$0$0 Def00009E
+S _FRCOSCKFILT1 Def007073
+S _LPOSCKFILT0 Def007062
+S _AX5051_PINCFG1 Def00400C
+S _AX5051_IFFREQLONB Def005029
+S _AX5051_IRQMASKNB Def005006
+S _DPTR1 Def008584
+S _RADIOSTAT Def00BFBE
+S _T2CNT Def00ADAC
+S _T2MODE Def0000A9
+S _U1MODE Def0000EF
+S _IP_3 Def0000BB
+S G$AX5051_TXPWRNB$0$0 Def005030
+S G$AX5051_FSKDEV2$0$0 Def004025
+S G$SCRATCH0$0$0 Def007084
+S G$DMA0CONFIG$0$0 Def007014
+S G$PINB_0$0$0 Def0000E8
+S G$PINA_1$0$0 Def0000C9
+S G$T1PERIOD0$0$0 Def0000A6
+S G$T0PERIOD1$0$0 Def00009F
+S _LPOSCKFILT1 Def007063
+S _AX5051_IRQINVERSION Def00400F
+S _AX5051_PINCFG2 Def00400D
+S _AX5051_PLLRNGCLK Def00402E
+S _AX5051_PLLVCOINB Def005072
+S _IP_4 Def0000BC
+S G$AX5051_CICDECLO$0$0 Def00403F
+S G$SCRATCH1$0$0 Def007085
+S G$DMA1CONFIG$0$0 Def007015
+S G$PINC_0$0$0 Def0000F8
+S G$PINB_1$0$0 Def0000E9
+S G$PINA_2$0$0 Def0000CA
+S G$T2PERIOD0$0$0 Def0000AE
+S G$T1PERIOD1$0$0 Def0000A7
+S G$RADIODATA0$0$0 Def0000B7
+S G$PINR$0$0 Def00008D
+S G$ADCCH0CONFIG$0$0 Def0000CA
+S _LPXOSCGM Def007054
+S _AX5051_PINCFG3 Def00400E
+S _EIP_0 Def0000B0
+S _IP_5 Def0000BD
+S G$AX5051_TRKAMPLITUDEHINB$0$0 Def005048
+S G$AX5051_FIFOCONTROL2$0$0 Def004037
+S G$SCRATCH2$0$0 Def007086
+S G$PINCHGA$0$0 Def007004
+S G$FRCOSCKFILT$0$0 Def007072
+S G$PINC_1$0$0 Def0000F9
+S G$PINB_2$0$0 Def0000EA
+S G$PINA_3$0$0 Def0000CB
+S G$U0CTRL$0$0 Def0000E4
+S G$T2PERIOD1$0$0 Def0000AF
+S G$RADIODATA1$0$0 Def0000B6
+S G$RADIOADDR0$0$0 Def0000B3
+S G$CLKCON$0$0 Def0000C6
+S G$ADCCH1CONFIG$0$0 Def0000CB
+S G$PSW$0$0 Def0000D0
+S _FRCOSCFREQ Def007076
+S _XTALREADY Def007F1A
+S _AX5051_AGCCOUNTER Def00403C
+S _DBGLNKSTAT Def0000E2
+S _NVDATA0 Def000094
+S _EIP_1 Def0000B1
+S _IP_6 Def0000BE
+S G$AX5051_PINCFG1NB$0$0 Def00500C
+S G$AX5051_TXDSPMODE$0$0 Def00400A
+S G$AX5051_TIMINGGAINHI$0$0 Def004042
+S G$SCRATCH3$0$0 Def007087
+S G$LPOSCKFILT$0$0 Def007062
+S G$PINCHGB$0$0 Def007005
+S G$PINC_2$0$0 Def0000FA
+S G$PINB_3$0$0 Def0000EB
+S G$PINA_4$0$0 Def0000CC
+S G$U1CTRL$0$0 Def0000EC
+S G$RADIODATA2$0$0 Def0000B5
+S G$RADIOADDR1$0$0 Def0000B2
+S G$ADCCH2CONFIG$0$0 Def0000D2
+S _LPOSCFREQ Def007066
+S _AX5051_CICDECHI Def00403E
+S _NVADDR0 Def000092
+S _NVDATA1 Def000095
+S _EIP_2 Def0000B2
+S _IP_7 Def0000BF
+S G$AX5051_PLLRNGCLKNB$0$0 Def00502E
+S G$AX5051_PINCFG2NB$0$0 Def00500D
+S G$AX5051_IRQINVERSIONNB$0$0 Def00500F
+S G$RADIOFSTATADDR0$0$0 Def007042
+S G$PINCHGC$0$0 Def007006
+S G$PINC_3$0$0 Def0000FB
+S G$PINB_4$0$0 Def0000EC
+S G$PINA_5$0$0 Def0000CD
+S G$WTCFGA$0$0 Def0000F1
+S G$RADIODATA3$0$0 Def0000B4
+S G$ADCCH3CONFIG$0$0 Def0000D3
+S _AX5051_FECMEM Def00406F
+S _AX5051_FIFOCOUNT Def004035
+S _AX5051_REFNB Def00507C
+S _PCON Def000087
+S _NVADDR1 Def000093
+S _EIP_3 Def0000B3
+S G$AX5051_PINCFG3NB$0$0 Def00500E
+S G$AX5051_TRKFREQLO$0$0 Def00404D
+S G$RADIOFSTATADDR1$0$0 Def007043
+S G$PINC_4$0$0 Def0000FC
+S G$PINB_5$0$0 Def0000ED
+S G$PINA_6$0$0 Def0000CE
+S G$WTCFGB$0$0 Def0000F9
+S _AX5051_PLLRANGING Def00402D
+S _AX5051_FREQ0NB Def005023
+S _AX5051_PWRMODENB Def005002
+S _AX5051_XTALOSCNB Def005003
+S _DIRR Def00008E
+S _OC0COMP Def00BDBC
+S _EIP_4 Def0000B4
+S G$AX5051_AGCCOUNTERNB$0$0 Def00503C
+S G$SILICONREV$0$0 Def007F00
+S G$INTCHGA$0$0 Def007000
+S G$PINC_5$0$0 Def0000FD
+S G$PINB_6$0$0 Def0000EE
+S G$PINA_7$0$0 Def0000CF
+S G$U0SHREG$0$0 Def0000E6
+S G$NVDATA$0$0 Def009594
+S G$ADCCONV$0$0 Def0000C9
+S _PALTA Def007008
+S _AX5051_FREQ1NB Def005022
+S _AX5051_FREQA0NB Def005023
+S _OC1COMP Def00C5C4
+S _WDTRESET Def0000DB
+S _EIP_5 Def0000B5
+S G$AX5051_CICDECHINB$0$0 Def00503E
+S G$AX5051_MODULATION$0$0 Def004010
+S G$AX5051_CRCINIT0$0$0 Def004017
+S G$INTCHGB$0$0 Def007001
+S G$PINC_6$0$0 Def0000FE
+S G$PINB_7$0$0 Def0000EF
+S G$WDTCFG$0$0 Def0000DA
+S G$U1SHREG$0$0 Def0000EE
+S G$NVADDR$0$0 Def009392
+S _ANALOGA Def007007
+S _PALTB Def007009
+S _AX5051_TRKFREQHI Def00404C
+S _AX5051_FREQ2NB Def005021
+S _AX5051_FREQA1NB Def005022
+S _EIP_6 Def0000B6
+S G$AX5051_FIFOCOUNTNB$0$0 Def005035
+S G$AX5051_FECMEMNB$0$0 Def00506F
+S G$AX5051_TRKPHASELO$0$0 Def00404B
+S G$AX5051_CRCINIT1$0$0 Def004016
+S G$OSCCALIB$0$0 Def007053
+S G$INTCHGC$0$0 Def007002
+S G$PINC_7$0$0 Def0000FF
+S _ADCTUNE0 Def007028
+S _PALTC Def00700A
+S _AX5051_AGCDECAY Def00403B
+S _AX5051_TRKAMPLITUDELO Def004049
+S _AX5051_DATARATELONB Def005041
+S _AX5051_FREQ3NB Def005020
+S _AX5051_FREQA2NB Def005021
+S _EIP_7 Def0000B7
+S G$AX5051_PLLRANGINGNB$0$0 Def00502D
+S G$AX5051_FIFODATA$0$0 Def004005
+S G$AX5051_CRCINIT2$0$0 Def004015
+S G$WTCNTA0$0$0 Def0000F2
+S _ADCTUNE1 Def007029
+S _FRCOSCCTRL Def007071
+S _AX5051_FECSTATUS Def00401A
+S _AX5051_FIFOTHRESH Def004036
+S _AX5051_FREQA3NB Def005020
+S _AX5051_PLLLOOPNB Def00502C
+S _XPAGE Def0000D9
+S G$AX5051_CRCINIT3$0$0 Def004014
+S G$WTCNTB0$0$0 Def0000FA
+S G$WTCNTA1$0$0 Def0000F3
+S G$B$0$0 Def0000F0
+S _ADCTUNE2 Def00702A
+S _FRCOSCCONFIG Def007070
+S _AX5051_FSKDEV0 Def004027
+S _AX5051_TRKPHASEHI Def00404A
+S _AX5051_MODULATORMISCNB Def005034
+S _RADIOACC Def0000B1
+S _F0 Def0000D5
+S G$AX5051_TRKFREQHINB$0$0 Def00504C
+S G$AX5051_SILICONREVISION$0$0 Def004000
+S G$WTCNTB1$0$0 Def0000FB
+S _LPOSCCONFIG Def007060
+S _AX5051_ADCMISC Def004038
+S _AX5051_FSKDEV1 Def004026
+S _AX5051_IFMODE Def004008
+S _AX5051_VREG Def00401B
+S _T0PERIOD0 Def00009E
+S _F1 Def0000D1
+S _PINA_0 Def0000C8
+S G$AX5051_TRKAMPLITUDELONB$0$0 Def005049
+S G$AX5051_AGCDECAYNB$0$0 Def00503B
+S G$AC$0$0 Def0000D6
+S _DMA0CONFIG Def007014
+S _SCRATCH0 Def007084
+S _AX5051_FSKDEV2 Def004025
+S _AX5051_TXPWRNB Def005030
+S _T0PERIOD1 Def00009F
+S _T1PERIOD0 Def0000A6
+S _PINA_1 Def0000C9
+S _PINB_0 Def0000E8
+S G$AX5051_FIFOTHRESHNB$0$0 Def005036
+S G$AX5051_FECSTATUSNB$0$0 Def00501A
+S G$AX5051_TIMINGGAINLO$0$0 Def004043
+S G$E2IE$0$0 Def0000A0
+S _DMA1CONFIG Def007015
+S _SCRATCH1 Def007085
+S _AX5051_CICDECLO Def00403F
+S _ADCCH0CONFIG Def0000CA
+S _PINR Def00008D
+S _RADIODATA0 Def0000B7
+S _T1PERIOD1 Def0000A7
+S _T2PERIOD0 Def0000AE
+S _PINA_2 Def0000CA
+S _PINB_1 Def0000E9
+S _PINC_0 Def0000F8
+S G$AX5051_TRKPHASEHINB$0$0 Def00504A
+S G$AX5051_FSKDEV0NB$0$0 Def005027
+S G$AX5051_FREQUENCYGAIN2$0$0 Def004046
+S G$AX5051_AGCATTACK$0$0 Def00403A
+S G$EA$0$0 Def0000AF
+S G$T0CLKSRC$0$0 Def00009A
+S G$PORTA$0$0 Def000080
+S _FRCOSCKFILT Def007072
+S _PINCHGA Def007004
+S _SCRATCH2 Def007086
+S _AX5051_FIFOCONTROL2 Def004037
+S _AX5051_TRKAMPLITUDEHINB Def005048
+S _PSW Def0000D0
+S _ADCCH1CONFIG Def0000CB
+S _CLKCON Def0000C6
+S _RADIOADDR0 Def0000B3
+S _RADIODATA1 Def0000B6
+S _T2PERIOD1 Def0000AF
+S _U0CTRL Def0000E4
+S _PINA_3 Def0000CB
+S _PINB_2 Def0000EA
+S _PINC_1 Def0000F9
+S G$AX5051_VREGNB$0$0 Def00501B
+S G$AX5051_IFMODENB$0$0 Def005008
+S G$AX5051_FSKDEV1NB$0$0 Def005026
+S G$AX5051_ADCMISCNB$0$0 Def005038
+S G$AX5051_RFMISC$0$0 Def00407A
+S G$AX5051_FRAMING$0$0 Def004012
+S G$AX5051_AMPLITUDEGAIN$0$0 Def004047
+S G$T1CLKSRC$0$0 Def0000A2
+S G$T0PERIOD$0$0 Def009F9E
+S G$SPSTATUS$0$0 Def0000DD
+S G$PORTB$0$0 Def000088
+S G$ACC$0$0 Def0000E0
+S _PINCHGB Def007005
+S _LPOSCKFILT Def007062
+S _SCRATCH3 Def007087
+S _AX5051_TIMINGGAINHI Def004042
+S _AX5051_TXDSPMODE Def00400A
+S _AX5051_PINCFG1NB Def00500C
+S _ADCCH2CONFIG Def0000D2
+S _RADIOADDR1 Def0000B2
+S _RADIODATA2 Def0000B5
+S _U1CTRL Def0000EC
+S _PINA_4 Def0000CC
+S _PINB_3 Def0000EB
+S _PINC_2 Def0000FA
+S G$AX5051_FSKDEV2NB$0$0 Def005025
+S G$AX5051_FIFOCONTROL$0$0 Def004004
+S G$T2CLKSRC$0$0 Def0000AA
+S G$T1PERIOD$0$0 Def00A7A6
+S G$SPMODE$0$0 Def0000DC
+S G$NVSTATUS$0$0 Def000091
+S G$PORTC$0$0 Def000090
+S _PINCHGC Def007006
+S _RADIOFSTATADDR0 Def007042
+S _AX5051_IRQINVERSIONNB Def00500F
+S _AX5051_PINCFG2NB Def00500D
+S _AX5051_PLLRNGCLKNB Def00502E
+S _ADCCH3CONFIG Def0000D3
+S _RADIODATA3 Def0000B4
+S _WTCFGA Def0000F1
+S _PINA_5 Def0000CD
+S _PINB_4 Def0000EC
+S _PINC_3 Def0000FB
+S G$AX5051_CICDECLONB$0$0 Def00503F
+S G$OSCFORCERUN$0$0 Def007050
+S G$T2PERIOD$0$0 Def00AFAE
+S G$RADIODATA$0$0 DefB4B5B6B7
+S _RADIOFSTATADDR1 Def007043
+S _AX5051_TRKFREQLO Def00404D
+S _AX5051_PINCFG3NB Def00500E
+S _WTCFGB Def0000F9
+S _PINA_6 Def0000CE
+S _PINB_5 Def0000ED
+S _PINC_4 Def0000FC
+S G$AX5051_FIFOCONTROL2NB$0$0 Def005037
+S G$AX5051_ENCODING$0$0 Def004011
+S G$RADIOADDR$0$0 Def00B2B3
+S G$ADCCLKSRC$0$0 Def0000D1
+S _INTCHGA Def007000
+S _SILICONREV Def007F00
+S _AX5051_AGCCOUNTERNB Def00503C
+S _ADCCONV Def0000C9
+S _NVDATA Def009594
+S _U0SHREG Def0000E6
+S _PINA_7 Def0000CF
+S _PINB_6 Def0000EE
+S _PINC_5 Def0000FD
+S G$AX5051_TXDSPMODENB$0$0 Def00500A
+S G$AX5051_TIMINGGAINHINB$0$0 Def005042
+S G$AX5051_TXBITRATEHI$0$0 Def004031
+S G$AX5051_SCRATCH$0$0 Def004001
+S G$PINSEL$0$0 Def00700B
+S G$WTEVTA0$0$0 Def0000F4
+S _INTCHGB Def007001
+S _AX5051_CRCINIT0 Def004017
+S _AX5051_MODULATION Def004010
+S _AX5051_CICDECHINB Def00503E
+S _NVADDR Def009392
+S _U1SHREG Def0000EE
+S _WDTCFG Def0000DA
+S _PINB_7 Def0000EF
+S _PINC_6 Def0000FE
+S .__.ABS. Def000000
+S G$RADIOFSTATADDR$0$0 Def007042
+S G$WTEVTB0$0$0 Def0000F6
+S G$WTEVTA1$0$0 Def0000F5
+S _INTCHGC Def007002
+S _OSCCALIB Def007053
+S _AX5051_CRCINIT1 Def004016
+S _AX5051_TRKPHASELO Def00404B
+S _AX5051_FECMEMNB Def00506F
+S _AX5051_FIFOCOUNTNB Def005035
+S _PINC_7 Def0000FF
+S G$AX5051_TRKFREQLONB$0$0 Def00504D
+S G$FRCOSCREF0$0$0 Def007074
+S G$DMA0ADDR0$0$0 Def007010
+S G$WTEVTC0$0$0 Def0000FC
+S G$WTEVTB1$0$0 Def0000F7
+S G$NVKEY$0$0 Def000096
+S G$DPH1$0$0 Def000085
+S _AX5051_CRCINIT2 Def004015
+S _AX5051_FIFODATA Def004005
+S _AX5051_PLLRANGINGNB Def00502D
+S _WTCNTA0 Def0000F2
+S G$AX5051_FECSYNC$0$0 Def004019
+S G$LPOSCREF0$0$0 Def007064
+S G$FRCOSCREF1$0$0 Def007075
+S G$DMA1ADDR0$0$0 Def007012
+S G$DMA0ADDR1$0$0 Def007011
+S G$WTEVTD0$0$0 Def0000FE
+S G$WTEVTC1$0$0 Def0000FD
+S G$IE$0$0 Def0000A8
+S _AX5051_CRCINIT3 Def004014
+S _B Def0000F0
+S _WTCNTA1 Def0000F3
+S _WTCNTB0 Def0000FA
+S G$AX5051_MODULATIONNB$0$0 Def005010
+S G$AX5051_CRCINIT0NB$0$0 Def005017
+S G$AX5051_DSPMODE$0$0 Def004009
+S G$LPOSCREF1$0$0 Def007065
+S G$DMA1ADDR1$0$0 Def007013
+S G$WTEVTD1$0$0 Def0000FF
+S G$DBGLNKBUF$0$0 Def0000E3
+S _AX5051_SILICONREVISION Def004000
+S _AX5051_TRKFREQHINB Def00504C
+S _WTCNTB1 Def0000FB
+S G$AX5051_TRKPHASELONB$0$0 Def00504B
+S G$AX5051_CRCINIT1NB$0$0 Def005016
+S G$AX5051_XTALCAP$0$0 Def00404F
+S G$AX5051_CICSHIFT$0$0 Def00403D
+S G$P$0$0 Def0000D0
+S G$E2IP$0$0 Def0000C0
+S _AX5051_AGCDECAYNB Def00503B
+S _AX5051_TRKAMPLITUDELONB Def005049
+S _AC Def0000D6
+S G$AX5051_FIFODATANB$0$0 Def005005
+S G$AX5051_CRCINIT2NB$0$0 Def005015
+S G$AX5051_IFFREQHI$0$0 Def004028
+S G$AX5051_FEC$0$0 Def004018
+S G$B_0$0$0 Def0000F0
+S G$WTCNTA$0$0 Def00F3F2
+S G$CODECONFIG$0$0 Def000097
+S G$DPL1$0$0 Def000084
+S _AX5051_TIMINGGAINLO Def004043
+S _AX5051_FECSTATUSNB Def00501A
+S _AX5051_FIFOTHRESHNB Def005036
+S _E2IE Def0000A0
+S G$AX5051_CRCINIT3NB$0$0 Def005014
+S G$B_1$0$0 Def0000F1
+S G$WTCNTB$0$0 Def00FBFA
+S _AX5051_AGCATTACK Def00403A
+S _AX5051_FREQUENCYGAIN2 Def004046
+S _AX5051_FSKDEV0NB Def005027
+S _AX5051_TRKPHASEHINB Def00504A
+S _PORTA Def000080
+S _T0CLKSRC Def00009A
+S _EA Def0000AF
+S G$AX5051_SILICONREVISIONNB$0$0 Def005000
+S G$AX5051_PHASEGAIN$0$0 Def004044
+S G$B_2$0$0 Def0000F2
+S G$WTCNTR1$0$0 Def0000EB
+S G$EIE$0$0 Def000098
+S _AX5051_AMPLITUDEGAIN Def004047
+S _AX5051_FRAMING Def004012
+S _AX5051_RFMISC Def00407A
+S _AX5051_ADCMISCNB Def005038
+S _AX5051_FSKDEV1NB Def005026
+S _AX5051_IFMODENB Def005008
+S _AX5051_VREGNB Def00501B
+S _ACC Def0000E0
+S _PORTB Def000088
+S _SPSTATUS Def0000DD
+S _T0PERIOD Def009F9E
+S _T1CLKSRC Def0000A2
+S G$AX5051_TXBITRATEMID$0$0 Def004032
+S G$AX5051_FREQUENCYGAIN$0$0 Def004045
+S G$E2IE_0$0$0 Def0000A0
+S G$B_3$0$0 Def0000F3
+S G$IC0CAPT0$0$0 Def0000CE
+S G$_XPAGE$0$0 Def0000D9
+S _AX5051_FIFOCONTROL Def004004
+S _AX5051_FSKDEV2NB Def005025
+S _PORTC Def000090
+S _NVSTATUS Def000091
+S _SPMODE Def0000DC
+S _T1PERIOD Def00A7A6
+S _T2CLKSRC Def0000AA
+S G$AX5051_TIMINGGAINLONB$0$0 Def005043
+S G$AX5051_TXBITRATELO$0$0 Def004033
+S G$AX5051_AGCTARGET$0$0 Def004039
+S G$PORTA_0$0$0 Def000080
+S G$RS0$0$0 Def0000D3
+S G$E2IE_1$0$0 Def0000A1
+S G$B_4$0$0 Def0000F4
+S G$IC1CAPT0$0$0 Def0000D6
+S G$IC0CAPT1$0$0 Def0000CF
+S _OSCFORCERUN Def007050
+S _AX5051_CICDECLONB Def00503F
+S _RADIODATA DefB4B5B6B7
+S _T2PERIOD Def00AFAE
+S G$AX5051_FREQUENCYGAIN2NB$0$0 Def005046
+S G$AX5051_AGCATTACKNB$0$0 Def00503A
+S G$GPIOENABLE$0$0 Def00700C
+S G$ADCCH0VAL0$0$0 Def007020
+S G$PORTB_0$0$0 Def000088
+S G$PORTA_1$0$0 Def000081
+S G$RS1$0$0 Def0000D4
+S G$E2IE_2$0$0 Def0000A2
+S G$B_5$0$0 Def0000F5
+S G$ACC_0$0$0 Def0000E0
+S G$IC1CAPT1$0$0 Def0000D7
+S G$CLKSTAT$0$0 Def0000C7
+S _AX5051_ENCODING Def004011
+S _AX5051_FIFOCONTROL2NB Def005037
+S _ADCCLKSRC Def0000D1
+S _RADIOADDR Def00B2B3
+S G$AX5051_RFMISCNB$0$0 Def00507A
+S G$AX5051_FRAMINGNB$0$0 Def005012
+S G$AX5051_AMPLITUDEGAINNB$0$0 Def005047
+S G$FRCOSCPER0$0$0 Def007078
+S G$ADCCH1VAL0$0$0 Def007022
+S G$ADCCH0VAL1$0$0 Def007021
+S G$PORTC_0$0$0 Def000090
+S G$PORTB_1$0$0 Def000089
+S G$PORTA_2$0$0 Def000082
+S G$E2IE_3$0$0 Def0000A3
+S G$B_6$0$0 Def0000F6
+S G$ACC_1$0$0 Def0000E1
+S G$PORTR$0$0 Def00008C
+S _PINSEL Def00700B
+S _AX5051_SCRATCH Def004001
+S _AX5051_TXBITRATEHI Def004031
+S _AX5051_TIMINGGAINHINB Def005042
+S _AX5051_TXDSPMODENB Def00500A
+S _WTEVTA0 Def0000F4
+S G$AX5051_FIFOCONTROLNB$0$0 Def005004
+S G$AX5051_IRQREQUEST$0$0 Def004007
+S G$LPOSCPER0$0$0 Def007068
+S G$FRCOSCPER1$0$0 Def007079
+S G$ADCCH2VAL0$0$0 Def007024
+S G$ADCCH1VAL1$0$0 Def007023
+S G$PORTC_1$0$0 Def000091
+S G$PORTB_2$0$0 Def00008A
+S G$PORTA_3$0$0 Def000083
+S G$E2IE_4$0$0 Def0000A4
+S G$B_7$0$0 Def0000F7
+S G$ACC_2$0$0 Def0000E2
+S _RADIOFSTATADDR Def007042
+S _WTEVTA1 Def0000F5
+S _WTEVTB0 Def0000F6
+S G$AX5051_RXMISC$0$0 Def00407D
+S G$LPOSCPER1$0$0 Def007069
+S G$ADCCH3VAL0$0$0 Def007026
+S G$ADCCH2VAL1$0$0 Def007025
+S G$PORTC_2$0$0 Def000092
+S G$PORTB_3$0$0 Def00008B
+S G$PORTA_4$0$0 Def000084
+S G$E2IE_5$0$0 Def0000A5
+S G$ACC_3$0$0 Def0000E3
+S G$T0CNT0$0$0 Def00009C
+S G$IP$0$0 Def0000B8
+S _DMA0ADDR0 Def007010
+S _FRCOSCREF0 Def007074
+S _AX5051_TRKFREQLONB Def00504D
+S _DPH1 Def000085
+S _NVKEY Def000096
+S _WTEVTB1 Def0000F7
+S _WTEVTC0 Def0000FC
+S G$AX5051_ENCODINGNB$0$0 Def005011
+S G$AX5051_DATARATEHI$0$0 Def004040
+S G$RADIOFDATAADDR0$0$0 Def007040
+S G$OSCRUN$0$0 Def007051
+S G$OSCREADY$0$0 Def007052
+S G$ADCCH3VAL1$0$0 Def007027
+S G$PORTC_3$0$0 Def000093
+S G$PORTB_4$0$0 Def00008C
+S G$PORTA_5$0$0 Def000085
+S G$E2IE_6$0$0 Def0000A6
+S G$ACC_4$0$0 Def0000E4
+S G$T1CNT0$0$0 Def0000A4
+S G$T0CNT1$0$0 Def00009D
+S _DMA0ADDR1 Def007011
+S _DMA1ADDR0 Def007012
+S _FRCOSCREF1 Def007075
+S _LPOSCREF0 Def007064
+S _AX5051_FECSYNC Def004019
+S _IE Def0000A8
+S _WTEVTC1 Def0000FD
+S _WTEVTD0 Def0000FE
+S G$AX5051_TXBITRATEHINB$0$0 Def005031
+S G$AX5051_SCRATCHNB$0$0 Def005001
+S G$AX5051_IRQMASK$0$0 Def004006
+S G$AX5051_IFFREQLO$0$0 Def004029
+S G$RADIOFDATAADDR1$0$0 Def007041
+S G$PORTC_4$0$0 Def000094
+S G$PORTB_5$0$0 Def00008D
+S G$PORTA_6$0$0 Def000086
+S G$E2IE_7$0$0 Def0000A7
+S G$ACC_5$0$0 Def0000E5
+S G$WTEVTA$0$0 Def00F5F4
+S G$T2CNT0$0$0 Def0000AC
+S G$T1CNT1$0$0 Def0000A5
+S G$RADIOSTAT0$0$0 Def0000BE
+S _DMA1ADDR1 Def007013
+S _LPOSCREF1 Def007065
+S _AX5051_DSPMODE Def004009
+S _AX5051_CRCINIT0NB Def005017
+S _AX5051_MODULATIONNB Def005010
+S _DBGLNKBUF Def0000E3
+S _WTEVTD1 Def0000FF
+S G$AX5051_PLLVCOI$0$0 Def004072
+S G$PORTC_5$0$0 Def000095
+S G$PORTB_6$0$0 Def00008E
+S G$PORTA_7$0$0 Def000087
+S G$CY$0$0 Def0000D7
+S G$ACC_6$0$0 Def0000E6
+S G$WTEVTB$0$0 Def00F7F6
+S G$T2CNT1$0$0 Def0000AD
+S G$SPSHREG$0$0 Def0000DE
+S G$RADIOSTAT1$0$0 Def0000BF
+S G$DPH$0$0 Def000083
+S _AX5051_CICSHIFT Def00403D
+S _AX5051_XTALCAP Def00404F
+S _AX5051_CRCINIT1NB Def005016
+S _AX5051_TRKPHASELONB Def00504B
+S _E2IP Def0000C0
+S _P Def0000D0
+S G$EXTIRQ$0$0 Def007003
+S G$FRCOSCREF$0$0 Def007074
+S G$DMA0ADDR$0$0 Def007010
+S G$PORTC_6$0$0 Def000096
+S G$PORTB_7$0$0 Def00008F
+S G$IE_0$0$0 Def0000A8
+S G$ACC_7$0$0 Def0000E7
+S G$WTEVTC$0$0 Def00FDFC
+S _AX5051_FEC Def004018
+S _AX5051_IFFREQHI Def004028
+S _AX5051_CRCINIT2NB Def005015
+S _AX5051_FIFODATANB Def005005
+S _DPL1 Def000084
+S _CODECONFIG Def000097
+S _WTCNTA Def00F3F2
+S _B_0 Def0000F0
+S G$AX5051_FECSYNCNB$0$0 Def005019
+S G$XTALOSC$0$0 Def007F18
+S G$LPOSCREF$0$0 Def007064
+S G$FRCOSCFREQ0$0$0 Def007076
+S G$DMA1ADDR$0$0 Def007012
+S G$PORTC_7$0$0 Def000097
+S G$IE_1$0$0 Def0000A9
+S G$WTEVTD$0$0 Def00FFFE
+S G$EIP$0$0 Def0000B0
+S _AX5051_CRCINIT3NB Def005014
+S _WTCNTB Def00FBFA
+S _B_1 Def0000F1
+S G$AX5051_DSPMODENB$0$0 Def005009
+S G$LPOSCFREQ0$0$0 Def007066
+S G$FRCOSCFREQ1$0$0 Def007077
+S G$IE_2$0$0 Def0000AA
+S G$E2IP_0$0$0 Def0000C0
+S _AX5051_PHASEGAIN Def004044
+S _AX5051_SILICONREVISIONNB Def005000
+S _EIE Def000098
+S _WTCNTR1 Def0000EB
+S _B_2 Def0000F2
+S G$AX5051_XTALCAPNB$0$0 Def00504F
+S G$AX5051_CICSHIFTNB$0$0 Def00503D
+S G$AX5051_REF$0$0 Def00407C
+S G$LPOSCFREQ1$0$0 Def007067
+S G$PALTRADIO$0$0 Def007046
+S G$IE_3$0$0 Def0000AB
+S G$E2IP_1$0$0 Def0000C1
+S G$IC0STATUS$0$0 Def0000CD
+S G$DIRA$0$0 Def000089
+S G$DPL$0$0 Def000082
+S _AX5051_FREQUENCYGAIN Def004045
+S _AX5051_TXBITRATEMID Def004032
+S __XPAGE Def0000D9
+S _IC0CAPT0 Def0000CE
+S _B_3 Def0000F3
+S _E2IE_0 Def0000A0
+S G$AX5051_IFFREQHINB$0$0 Def005028
+S G$AX5051_FECNB$0$0 Def005018
+S G$AX5051_XTALOSC$0$0 Def004003
+S G$AX5051_PWRMODE$0$0 Def004002
+S G$AX5051_FREQ0$0$0 Def004023
+S G$MISCCTRL$0$0 Def007F01
+S G$IE_4$0$0 Def0000AC
+S G$E2IP_2$0$0 Def0000C2
+S G$OC0COMP0$0$0 Def0000BC
+S G$IC1STATUS$0$0 Def0000D5
+S G$IC0MODE$0$0 Def0000CC
+S G$DIRB$0$0 Def00008A
+S G$ANALOGCOMP$0$0 Def0000E1
+S _AX5051_AGCTARGET Def004039
+S _AX5051_TXBITRATELO Def004033
+S _AX5051_TIMINGGAINLONB Def005043
+S _IC0CAPT1 Def0000CF
+S _IC1CAPT0 Def0000D6
+S _B_4 Def0000F4
+S _E2IE_1 Def0000A1
+S _RS0 Def0000D3
+S _PORTA_0 Def000080
+S G$AX5051_FREQA0$0$0 Def004023
+S G$AX5051_FREQ1$0$0 Def004022
+S G$IE_5$0$0 Def0000AD
+S G$EIE_0$0$0 Def000098
+S G$E2IP_3$0$0 Def0000C3
+S G$OC1COMP0$0$0 Def0000C4
+S G$OC0COMP1$0$0 Def0000BD
+S G$IC1MODE$0$0 Def0000D4
+S G$DIRC$0$0 Def00008B
+S _ADCCH0VAL0 Def007020
+S _GPIOENABLE Def00700C
+S _AX5051_AGCATTACKNB Def00503A
+S _AX5051_FREQUENCYGAIN2NB Def005046
+S _CLKSTAT Def0000C7
+S _IC1CAPT1 Def0000D7
+S _ACC_0 Def0000E0
+S _B_5 Def0000F5
+S _E2IE_2 Def0000A2
+S _RS1 Def0000D4
+S _PORTA_1 Def000081
+S _PORTB_0 Def000088
+S G$AX5051_PHASEGAINNB$0$0 Def005044
+S G$AX5051_FREQA1$0$0 Def004022
+S G$AX5051_FREQ2$0$0 Def004021
+S G$XTALAMPL$0$0 Def007F19
+S G$IE_6$0$0 Def0000AE
+S G$EIE_1$0$0 Def000099
+S G$E2IP_4$0$0 Def0000C4
+S G$OC1COMP1$0$0 Def0000C5
+S G$SP$0$0 Def000081
+S _ADCCH0VAL1 Def007021
+S _ADCCH1VAL0 Def007022
+S _FRCOSCPER0 Def007078
+S _AX5051_AMPLITUDEGAINNB Def005047
+S _AX5051_FRAMINGNB Def005012
+S _AX5051_RFMISCNB Def00507A
+S _PORTR Def00008C
+S _ACC_1 Def0000E1
+S _B_6 Def0000F6
+S _E2IE_3 Def0000A3
+S _PORTA_2 Def000082
+S _PORTB_1 Def000089
+S _PORTC_0 Def000090
+S G$AX5051_TXBITRATEMIDNB$0$0 Def005032
+S G$AX5051_FREQUENCYGAINNB$0$0 Def005045
+S G$AX5051_FREQA2$0$0 Def004021
+S G$AX5051_FREQ3$0$0 Def004020
+S G$AX5051_DATARATELO$0$0 Def004041
+S G$IE_7$0$0 Def0000AF
+S G$EIE_2$0$0 Def00009A
+S G$E2IP_5$0$0 Def0000C5
+S G$IC0CAPT$0$0 Def00CFCE
+S _ADCCH1VAL1 Def007023
+S _ADCCH2VAL0 Def007024
+S _FRCOSCPER1 Def007079
+S _LPOSCPER0 Def007068
+S _AX5051_IRQREQUEST Def004007
+S _AX5051_FIFOCONTROLNB Def005004
+S _ACC_2 Def0000E2
+S _B_7 Def0000F7
+S _E2IE_4 Def0000A4
+S _PORTA_3 Def000083
+S _PORTB_2 Def00008A
+S _PORTC_1 Def000091
+S G$AX5051_TXBITRATELONB$0$0 Def005033
+S G$AX5051_AGCTARGETNB$0$0 Def005039
+S G$AX5051_PLLLOOP$0$0 Def00402C
+S G$AX5051_FREQA3$0$0 Def004020
+S G$OV$0$0 Def0000D2
+S G$EIE_3$0$0 Def00009B
+S G$E2IP_6$0$0 Def0000C6
+S G$SPCLKSRC$0$0 Def0000DF
+S G$IC1CAPT$0$0 Def00D7D6
+S _ADCCH2VAL1 Def007025
+S _ADCCH3VAL0 Def007026
+S _LPOSCPER1 Def007069
+S _AX5051_RXMISC Def00407D
+S _IP Def0000B8
+S _T0CNT0 Def00009C
+S _ACC_3 Def0000E3
+S _E2IE_5 Def0000A5
+S _PORTA_4 Def000084
+S _PORTB_3 Def00008B
+S _PORTC_2 Def000092
+S G$AX5051_MODULATORMISC$0$0 Def004034
+S G$ADCCH0VAL$0$0 Def007020
+S G$EIE_4$0$0 Def00009C
+S G$E2IP_7$0$0 Def0000C7
+S G$OC0STATUS$0$0 Def0000BB
+S _ADCCH3VAL1 Def007027
+S _OSCREADY Def007052
+S _OSCRUN Def007051
+S _RADIOFDATAADDR0 Def007040
+S _AX5051_DATARATEHI Def004040
+S _AX5051_ENCODINGNB Def005011
+S _T0CNT1 Def00009D
+S _T1CNT0 Def0000A4
+S _ACC_4 Def0000E4
+S _E2IE_6 Def0000A6
+S _PORTA_5 Def000085
+S _PORTB_4 Def00008C
+S _PORTC_3 Def000093
+S G$FRCOSCPER$0$0 Def007078
+S G$ADCCH1VAL$0$0 Def007022
+S G$EIE_5$0$0 Def00009D
+S G$WTSTAT$0$0 Def0000EA
+S G$OC1STATUS$0$0 Def0000C3
+S G$OC0MODE$0$0 Def0000B9
+S G$DPS$0$0 Def000086
+S _RADIOFDATAADDR1 Def007041
+S _AX5051_IFFREQLO Def004029
+S _AX5051_IRQMASK Def004006
+S _AX5051_SCRATCHNB Def005001
+S _AX5051_TXBITRATEHINB Def005031
+S _RADIOSTAT0 Def0000BE
+S _T1CNT1 Def0000A5
+S _T2CNT0 Def0000AC
+S _WTEVTA Def00F5F4
+S _ACC_5 Def0000E5
+S _E2IE_7 Def0000A7
+S _PORTA_6 Def000086
+S _PORTB_5 Def00008D
+S _PORTC_4 Def000094
+S G$AX5051_IRQREQUESTNB$0$0 Def005007
+S G$AX5051_TXPWR$0$0 Def004030
+S G$LPOSCPER$0$0 Def007068
+S G$ADCCH2VAL$0$0 Def007024
+S G$IP_0$0$0 Def0000B8
+S G$EIE_6$0$0 Def00009E
+S G$T0STATUS$0$0 Def00009B
+S G$OC1MODE$0$0 Def0000C1
+S G$PINA$0$0 Def0000C8
+S _AX5051_PLLVCOI Def004072
+S _DPH Def000083
+S _RADIOSTAT1 Def0000BF
+S _SPSHREG Def0000DE
+S _T2CNT1 Def0000AD
+S _WTEVTB Def00F7F6
+S _ACC_6 Def0000E6
+S _CY Def0000D7
+S _PORTA_7 Def000087
+S _PORTB_6 Def00008E
+S _PORTC_5 Def000095
+S G$AX5051_RXMISCNB$0$0 Def00507D
+S G$RADIOMUX$0$0 Def007044
+S G$ADCCH3VAL$0$0 Def007026
+S G$IP_1$0$0 Def0000B9
+S G$EIE_7$0$0 Def00009F
+S G$U0STATUS$0$0 Def0000E5
+S G$T1STATUS$0$0 Def0000A3
+S G$T0MODE$0$0 Def000099
+S G$T0CNT$0$0 Def009D9C
+S G$OC0PIN$0$0 Def0000BA
+S G$PINB$0$0 Def0000E8
+S _DMA0ADDR Def007010
+S _FRCOSCREF Def007074
+S _EXTIRQ Def007003
+S _WTEVTC Def00FDFC
+S _ACC_7 Def0000E7
+S _IE_0 Def0000A8
+S _PORTB_7 Def00008F
+S _PORTC_6 Def000096
+S G$AX5051_DATARATEHINB$0$0 Def005040
+S G$AX5051_TRKAMPLITUDEHI$0$0 Def004048
+S G$RADIOFDATAADDR$0$0 Def007040
+S G$FRCOSCKFILT0$0$0 Def007072
+S G$IP_2$0$0 Def0000BA
+S G$WTIRQEN$0$0 Def0000E9
+S G$U1STATUS$0$0 Def0000ED
+S G$U0MODE$0$0 Def0000E7
+S G$T2STATUS$0$0 Def0000AB
+S G$T1MODE$0$0 Def0000A1
+S G$T1CNT$0$0 Def00A5A4
+S G$OC1PIN$0$0 Def0000C2
+S G$PINC$0$0 Def0000F8
+S G$DPTR0$0$0 Def008382
+S _DMA1ADDR Def007012
+S _FRCOSCFREQ0 Def007076
+S _LPOSCREF Def007064
+S _XTALOSC Def007F18
+S _AX5051_FECSYNCNB Def005019
+S _EIP Def0000B0
+S _WTEVTD Def00FFFE
+S _IE_1 Def0000A9
+S _PORTC_7 Def000097
+S G$AX5051_IRQMASKNB$0$0 Def005006
+S G$AX5051_IFFREQLONB$0$0 Def005029
+S G$AX5051_PINCFG1$0$0 Def00400C
+S G$LPOSCKFILT0$0$0 Def007062
+S G$FRCOSCKFILT1$0$0 Def007073
+S G$IP_3$0$0 Def0000BB
+S G$U1MODE$0$0 Def0000EF
+S G$T2MODE$0$0 Def0000A9
+S G$T2CNT$0$0 Def00ADAC
+S G$RADIOSTAT$0$0 Def00BFBE
+S G$DPTR1$0$0 Def008584
+S _FRCOSCFREQ1 Def007077
+S _LPOSCFREQ0 Def007066
+S _AX5051_DSPMODENB Def005009
+S _E2IP_0 Def0000C0
+S _IE_2 Def0000AA
+S G$AX5051_PLLVCOINB$0$0 Def005072
+S G$AX5051_PLLRNGCLK$0$0 Def00402E
+S G$AX5051_PINCFG2$0$0 Def00400D
+S G$AX5051_IRQINVERSION$0$0 Def00400F
+S G$LPOSCKFILT1$0$0 Def007063
+S G$IP_4$0$0 Def0000BC
+S _PALTRADIO Def007046
+S _LPOSCFREQ1 Def007067
+S _AX5051_REF Def00407C
+S _AX5051_CICSHIFTNB Def00503D
+S _AX5051_XTALCAPNB Def00504F
+S _DPL Def000082
+S _DIRA Def000089
+S _IC0STATUS Def0000CD
+S _E2IP_1 Def0000C1
+S _IE_3 Def0000AB
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 56 flags 20 addr 0
+S A$ax5051wrfifo$1700 Def000052
+S A$ax5051wrfifo$1701 Def000053
+S A$ax5051wrfifo$1702 Def000055
+S A$ax5051wrfifo$1650 Def00000C
+S A$ax5051wrfifo$1660 Def00001C
+S A$ax5051wrfifo$1651 Def00000F
+S A$ax5051wrfifo$1670 Def000025
+S A$ax5051wrfifo$1652 Def000011
+S A$ax5051wrfifo$1643 Def000000
+S A$ax5051wrfifo$1680 Def000034
+S A$ax5051wrfifo$1671 Def000027
+S A$ax5051wrfifo$1653 Def000014
+S A$ax5051wrfifo$1644 Def000002
+S A$ax5051wrfifo$1690 Def000043
+S A$ax5051wrfifo$1681 Def000036
+S A$ax5051wrfifo$1672 Def000028
+S A$ax5051wrfifo$1663 Def00001D
+S A$ax5051wrfifo$1645 Def000004
+S A$ax5051wrfifo$1691 Def000045
+S A$ax5051wrfifo$1682 Def000038
+S A$ax5051wrfifo$1673 Def00002A
+S A$ax5051wrfifo$1664 Def00001E
+S A$ax5051wrfifo$1655 Def000017
+S A$ax5051wrfifo$1646 Def000005
+S A$ax5051wrfifo$1692 Def000048
+S A$ax5051wrfifo$1683 Def000039
+S A$ax5051wrfifo$1674 Def00002C
+S A$ax5051wrfifo$1665 Def00001F
+S A$ax5051wrfifo$1656 Def000018
+S A$ax5051wrfifo$1647 Def000006
+S A$ax5051wrfifo$1684 Def00003B
+S A$ax5051wrfifo$1675 Def00002F
+S A$ax5051wrfifo$1666 Def000020
+S A$ax5051wrfifo$1657 Def000019
+S A$ax5051wrfifo$1648 Def000008
+S A$ax5051wrfifo$1694 Def00004A
+S A$ax5051wrfifo$1667 Def000022
+S A$ax5051wrfifo$1658 Def00001A
+S A$ax5051wrfifo$1649 Def000009
+S A$ax5051wrfifo$1695 Def00004B
+S A$ax5051wrfifo$1686 Def00003C
+S A$ax5051wrfifo$1677 Def000031
+S A$ax5051wrfifo$1696 Def00004C
+S A$ax5051wrfifo$1687 Def00003E
+S A$ax5051wrfifo$1678 Def000032
+S A$ax5051wrfifo$1669 Def000023
+S A$ax5051wrfifo$1697 Def00004D
+S A$ax5051wrfifo$1688 Def000040
+S A$ax5051wrfifo$1679 Def000033
+S A$ax5051wrfifo$1698 Def00004E
+S A$ax5051wrfifo$1689 Def000041
+S A$ax5051wrfifo$1699 Def000050
+S C$ax5051wrfifo.c$10$0$0 Def000000
+S C$ax5051wrfifo.c$75$1$66 Def000000
+S C$ax5051wrfifo.c$76$1$66 Def000056
+S G$ax5051_writefifo$0$0 Def000000
+S _ax5051_writefifo Def000000
+S XG$ax5051_writefifo$0$0 Def000056
+A CONST size 0 flags 20 addr 0
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+A CABS size 0 flags 28 addr 0
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+S:G$AX5051_PHASEGAINNB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_PLLRNGCLKNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_PLLVCOINB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_TXBITRATEHINB$0$0({1}SC:U),F,0,0
+S:G$AX5051_TXBITRATELONB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_TXDSPMODENB$0$0({1}SC:U),F,0,0
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+S:G$AX5051_VREGNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALCAPNB$0$0({1}SC:U),F,0,0
+S:G$AX5051_XTALOSCNB$0$0({1}SC:U),F,0,0
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+S:G$radio_read32$0$0({2}DF,SL:U),C,0,0
+S:G$radio_write16$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write24$0$0({2}DF,SV:S),C,0,0
+S:G$radio_write32$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5031_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5031_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5042_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5042_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_enter_deepsleep$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_wakeup_deepsleep$0$0({2}DF,SC:U),C,0,0
+S:G$ax5043_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5043_writefifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_comminit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_commsleepexit$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_reset$0$0({2}DF,SC:U),C,0,0
+S:G$ax5051_rclk_enable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_rclk_disable$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_readfifo$0$0({2}DF,SV:S),C,0,0
+S:G$ax5051_probeirq$0$0({2}DF,SC:U),C,0,0
+S:G$radio_wakeup_deepsleep_core$0$0({2}DF,SC:U),C,0,0
+
+
+
+
+ax5051regs
+
+XH3
+H 1A areas 1 global symbols
+M ax5051regs
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax5051regs
+
+
+
+
+ax8052regs
+
+XH3
+H 1A areas 1 global symbols
+M ax8052regs
+O -mmcs51 --model-large
+S .__.ABS. Def000000
+A _CODE size 0 flags 0 addr 0
+A RSEG size 0 flags 8 addr 0
+A RSEG0 size 0 flags 8 addr 0
+A RSEG1 size 0 flags 8 addr 0
+A REG_BANK_0 size 8 flags 4 addr 0
+A DSEG size 0 flags 0 addr 0
+A ISEG size 0 flags 0 addr 0
+A IABS size 0 flags 8 addr 0
+A BSEG size 0 flags 80 addr 0
+A PSEG size 0 flags 50 addr 0
+A XSEG size 0 flags 40 addr 0
+A XABS size 0 flags 48 addr 0
+A XISEG size 0 flags 40 addr 0
+A HOME size 0 flags 20 addr 0
+A GSINIT0 size 0 flags 20 addr 0
+A GSINIT1 size 0 flags 20 addr 0
+A GSINIT2 size 0 flags 20 addr 0
+A GSINIT3 size 0 flags 20 addr 0
+A GSINIT4 size 0 flags 20 addr 0
+A GSINIT5 size 0 flags 20 addr 0
+A GSINIT size 0 flags 20 addr 0
+A GSFINAL size 0 flags 20 addr 0
+A CSEG size 0 flags 20 addr 0
+A CONST size 0 flags 20 addr 0
+A XINIT size 0 flags 20 addr 0
+A CABS size 0 flags 28 addr 0
+T 00 00 00
+R 00 00 00 02
+T 00 00 00
+R 00 00 00 03
+T 00 00 00
+R 00 00 00 04
+
+
+M:ax8052regs
+
+
+
+
+
+
diff --git a/libs/libmf/source/adccal.c b/libs/libmf/source/adccal.c
new file mode 100644
index 00000000..6fba9c48
--- /dev/null
+++ b/libs/libmf/source/adccal.c
@@ -0,0 +1,8 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+void adc_calibrate(void)
+{
+ adc_calibrate_gain();
+ adc_calibrate_temp();
+}
diff --git a/libs/libmf/source/adccalg.c b/libs/libmf/source/adccalg.c
new file mode 100644
index 00000000..d0df2dfb
--- /dev/null
+++ b/libs/libmf/source/adccalg.c
@@ -0,0 +1,424 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALG00GAIN0, 0x7030) /* ADC Calibration Range 00 Gain Low Byte */
+SFRX(ADCCALG00GAIN1, 0x7031) /* ADC Calibration Range 00 Gain High Byte */
+SFRX(ADCCALG01GAIN0, 0x7032) /* ADC Calibration Range 01 Gain Low Byte */
+SFRX(ADCCALG01GAIN1, 0x7033) /* ADC Calibration Range 01 Gain High Byte */
+SFRX(ADCCALG10GAIN0, 0x7034) /* ADC Calibration Range 10 Gain Low Byte */
+SFRX(ADCCALG10GAIN1, 0x7035) /* ADC Calibration Range 10 Gain High Byte */
+
+#if defined(SDCC)
+
+void adc_calibrate_gain(void)
+{
+ __asm
+ar2 = 0x02
+ar3 = 0x03
+ar4 = 0x04
+ar5 = 0x05
+ar6 = 0x06
+ar7 = 0x07
+ar0 = 0x00
+ar1 = 0x01
+ clr a
+ push _IE
+ mov _IE,a
+ push _EIE
+ mov _EIE,#0x40
+ push _E2IE
+ mov _E2IE,a
+ mov _ADCCONV,a
+ mov r0,a
+ mov r1,a
+ mov r2,a
+ mov r3,a
+ mov r4,a
+ mov r5,a
+ mov _ADCCLKSRC,#0x28 ; 0.625MHz/16
+ mov _ADCCH0CONFIG,#0xe0
+ mov _ADCCH1CONFIG,#0xe8
+ mov _ADCCH2CONFIG,#0xf0
+ mov _ADCCH3CONFIG,#0xff
+ mov dptr,#_ADCTUNE1
+ mov a,#0xf2
+ movx @dptr,a
+ mov dptr,#_ADCCH0VAL0
+ movx a,@dptr
+ mov b,#0x10
+adccalloop:
+ mov _ADCCONV,#0x01
+adcwait0:
+ mov a,_PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov _PCON,a
+ mov a,_ADCCLKSRC
+ jb acc.7,adcwait0
+ mov dptr,#_ADCCH0VAL0
+ ;; channel 0
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r0
+ mov r0,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r1
+ mov r1,a
+ ;; channel 1
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r2
+ mov r2,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r3
+ mov r3,a
+ ;; channel 2
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r4
+ mov r4,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r5
+ mov r5,a
+ djnz b,adccalloop
+ ;; switch off ADC
+ mov dptr,#_ADCTUNE1
+ mov a,#0x02
+ movx @dptr,a
+ mov _ADCCLKSRC,#0x07 ; off
+ pop _E2IE
+ pop _EIE
+ pop _IE
+ ;; convert calibration constant to calibration value
+calconst0 = 0x0F5C28F6 ; 0.48*2^29
+calconst1 = 0x1C28F5C3 ; 0.88*2^29
+calconst2 = 0x1999999A ; 0.8*2^29
+ push ar4
+ push ar5
+ push ar2
+ push ar3
+ mov __divslong_PARM_2,r0
+ mov (__divslong_PARM_2 + 1),r1
+ clr a
+ mov (__divslong_PARM_2 + 2),a
+ mov (__divslong_PARM_2 + 3),a
+ mov dptr,#calconst0&0xffff
+ mov b,#calconst0>>16
+ mov a,#calconst0>>24
+ lcall __divslong
+ mov a,dpl
+ mov r0,dph
+ mov dptr,#_ADCCALG00GAIN0
+ movx @dptr,a
+ inc dptr
+ mov a,r0
+ movx @dptr,a
+ pop (__divslong_PARM_2 + 1)
+ pop __divslong_PARM_2
+ clr a
+ mov (__divslong_PARM_2 + 2),a
+ mov (__divslong_PARM_2 + 3),a
+ mov dptr,#calconst1&0xffff
+ mov b,#calconst1>>16
+ mov a,#calconst1>>24
+ lcall __divslong
+ mov a,dpl
+ mov r0,dph
+ mov dptr,#_ADCCALG01GAIN0
+ movx @dptr,a
+ inc dptr
+ mov a,r0
+ movx @dptr,a
+ pop (__divslong_PARM_2 + 1)
+ pop __divslong_PARM_2
+ clr a
+ mov (__divslong_PARM_2 + 2),a
+ mov (__divslong_PARM_2 + 3),a
+ mov dptr,#calconst2&0xffff
+ mov b,#calconst2>>16
+ mov a,#calconst2>>24
+ lcall __divslong
+ mov a,dpl
+ mov r0,dph
+ mov dptr,#_ADCCALG10GAIN0
+ movx @dptr,a
+ inc dptr
+ mov a,r0
+ movx @dptr,a
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+void adc_calibrate_gain(void)
+{
+#pragma asm
+ using 0
+ extrn CODE (?C?SLDIV)
+ clr a
+ push IE
+ mov IE,a
+ push EIE
+ mov EIE,#0x40
+ push E2IE
+ mov E2IE,a
+ mov ADCCONV,a
+ mov r0,a
+ mov r1,a
+ mov r2,a
+ mov r3,a
+ mov r4,a
+ mov r5,a
+ mov ADCCLKSRC,#0x28 ; 0.625MHz/16
+ mov ADCCH0CONFIG,#0xe0
+ mov ADCCH1CONFIG,#0xe8
+ mov ADCCH2CONFIG,#0xf0
+ mov ADCCH3CONFIG,#0xff
+ mov dptr,#ADCTUNE1
+ mov a,#0xf2
+ movx @dptr,a
+ mov dptr,#ADCCH0VAL0
+ movx a,@dptr
+ mov b,#0x10
+adccalloop:
+ mov ADCCONV,#0x01
+adcwait0:
+ mov a,PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov PCON,a
+ mov a,ADCCLKSRC
+ jb acc.7,adcwait0
+ mov dptr,#ADCCH0VAL0
+ ;; channel 0
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r0
+ mov r0,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r1
+ mov r1,a
+ ;; channel 1
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r2
+ mov r2,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r3
+ mov r3,a
+ ;; channel 2
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r4
+ mov r4,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r5
+ mov r5,a
+ djnz b,adccalloop
+ ;; switch off ADC
+ mov dptr,#ADCTUNE1
+ mov a,#0x02
+ movx @dptr,a
+ mov ADCCLKSRC,#0x07 ; off
+ pop E2IE
+ pop EIE
+ pop IE
+ ;; convert calibration constant to calibration value
+calconst0l equ 0x28F6 ; 0.48*2^29
+calconst0h equ 0x0F5C
+calconst1l equ 0xF5C3 ; 0.88*2^29
+calconst1h equ 0x1C28
+calconst2l equ 0x999A ; 0.8*2^29
+calconst2h equ 0x1999
+ push ar4
+ push ar5
+ push ar2
+ push ar3
+ mov r3,ar0
+ mov r2,ar1
+ clr a
+ mov r1,a
+ mov r0,a
+ mov r7,#calconst0l&0xff
+ mov r6,#calconst0l>>8
+ mov r5,#calconst0h&0xff
+ mov r4,#calconst0h>>8
+ lcall ?C?SLDIV
+ mov dptr,#ADCCALG00GAIN0
+ mov a,r7
+ movx @dptr,a
+ inc dptr
+ mov a,r6
+ movx @dptr,a
+ pop ar2
+ pop ar3
+ clr a
+ mov r1,a
+ mov r0,a
+ mov r7,#calconst1l&0xff
+ mov r6,#calconst1l>>8
+ mov r5,#calconst1h&0xff
+ mov r4,#calconst1h>>8
+ lcall ?C?SLDIV
+ mov dptr,#ADCCALG01GAIN0
+ mov a,r7
+ movx @dptr,a
+ inc dptr
+ mov a,r6
+ movx @dptr,a
+ pop ar2
+ pop ar3
+ clr a
+ mov r1,a
+ mov r0,a
+ mov r7,#calconst2l&0xff
+ mov r6,#calconst2l>>8
+ mov r5,#calconst2h&0xff
+ mov r4,#calconst2h>>8
+ lcall ?C?SLDIV
+ mov dptr,#ADCCALG10GAIN0
+ mov a,r7
+ movx @dptr,a
+ inc dptr
+ mov a,r6
+ movx @dptr,a
+#pragma endasm
+}
+
+#else
+
+#if defined __ICC8051__
+// 6.4: Internal error: [EbkCodeNode::SetNextSpan]: Jump size optimization will not terminate!
+#pragma optimize=low
+#endif
+
+void adc_calibrate_gain(void)
+{
+ static const int32_t calconst0 = 0x0F5C28F6; /* 0.48*2^29 */
+ static const int32_t calconst1 = 0x1C28F5C3; /* 0.88*2^29 */
+ static const int32_t calconst2 = 0x1999999A; /* 0.8*2^29 */
+ uint8_t __autodata iesave = IE, eiesave = EIE, e2iesave = E2IE, cnt = 0x10;
+ uint16_t __autodata adcv0 = 0, adcv1 = 0, adcv2 = 0, v;
+ IE = 0;
+ EIE = 0x40;
+ E2IE = 0;
+ ADCCONV = 0;
+ ADCCLKSRC = 0x28; /* 0.625MHz/16 */
+ ADCCH0CONFIG = 0xe0;
+ ADCCH1CONFIG = 0xe8;
+ ADCCH2CONFIG = 0xf0;
+ ADCCH3CONFIG = 0xff;
+ ADCTUNE1 = 0xf2;
+ ADCCH0VAL0;
+ do {
+ ADCCONV = 0x01;
+ do {
+ enter_standby();
+ } while (ADCCLKSRC & 0x80);
+ v = ADCCH0VAL1;
+ v <<= 4;
+ v |= ADCCH0VAL0 >> 4;
+ adcv0 += v;
+ v = ADCCH1VAL1;
+ v <<= 4;
+ v |= ADCCH1VAL0 >> 4;
+ adcv1 += v;
+ v = ADCCH2VAL1;
+ v <<= 4;
+ v |= ADCCH2VAL0 >> 4;
+ adcv2 += v;
+ } while (--cnt);
+ /* switch off ADC */
+ ADCTUNE1 = 0x02;
+ ADCCLKSRC = 0x07;
+ E2IE = e2iesave;
+ EIE = eiesave;
+ IE = iesave;
+ /* convert calibration constant to calibration value */
+ v = calconst0 / adcv0;
+ ADCCALG00GAIN0 = v;
+ ADCCALG00GAIN1 = v >> 8;
+ v = calconst1 / adcv1;
+ ADCCALG01GAIN0 = v;
+ ADCCALG01GAIN1 = v >> 8;
+ v = calconst2 / adcv2;
+ ADCCALG10GAIN0 = v;
+ ADCCALG10GAIN1 = v >> 8;
+}
+
+#endif
+
+#if 0
+
+uint32_t mulx(uint8_t a, uint8_t b, int32_t c, int32_t d)
+{
+ return c * d;
+}
+
+
+uint16_t divx(uint8_t a, uint8_t b, int32_t c, int16_t d)
+{
+ return c / d;
+}
+
+#endif
diff --git a/libs/libmf/source/adccalt.c b/libs/libmf/source/adccalt.c
new file mode 100644
index 00000000..b4eb975c
--- /dev/null
+++ b/libs/libmf/source/adccalt.c
@@ -0,0 +1,370 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALTEMPGAIN0, 0x7038) /* ADC Calibration Temperature Gain Low Byte */
+SFRX(ADCCALTEMPGAIN1, 0x7039) /* ADC Calibration Temperature Gain High Byte */
+SFRX(ADCCALTEMPOFFS0, 0x703A) /* ADC Calibration Temperature Offset Low Byte */
+SFRX(ADCCALTEMPOFFS1, 0x703B) /* ADC Calibration Temperature Offset High Byte */
+
+#if defined(SDCC)
+
+void adc_calibrate_temp(void)
+{
+ __asm
+ar2 = 0x02
+ar3 = 0x03
+ar4 = 0x04
+ar5 = 0x05
+ar6 = 0x06
+ar7 = 0x07
+ar0 = 0x00
+ar1 = 0x01
+ clr a
+ push _IE
+ mov _IE,a
+ push _EIE
+ mov _EIE,#0x40
+ push _E2IE
+ mov _E2IE,a
+ mov _ADCCONV,a
+ mov r0,a
+ mov r1,a
+ mov r2,a
+ mov r3,a
+ mov _ADCCLKSRC,#0x28 ; 0.625MHz/16
+ mov _ADCCH0CONFIG,#0xf8
+ mov _ADCCH1CONFIG,#0xf9
+ mov _ADCCH2CONFIG,#0xff
+ mov _ADCCH3CONFIG,#0xff
+ mov dptr,#_ADCTUNE1
+ mov a,#0xf2
+ movx @dptr,a
+ mov dptr,#_ADCCH0VAL0
+ movx a,@dptr
+ mov b,#0x10
+adccaltloop:
+ mov _ADCCONV,#0x01
+adcwait1:
+ mov a,_PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov _PCON,a
+ mov a,_ADCCLKSRC
+ jb acc.7,adcwait1
+ mov dptr,#_ADCCH0VAL0
+ ;; channel 0
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r0
+ mov r0,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r1
+ mov r1,a
+ ;; channel 1
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r2
+ mov r2,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r3
+ mov r3,a
+ djnz b,adccaltloop
+ ;; switch off ADC
+ mov dptr,#_ADCTUNE1
+ mov a,#0x02
+ movx @dptr,a
+ mov _ADCCLKSRC,#0x07 ; off
+ pop _E2IE
+ pop _EIE
+ pop _IE
+ ;; convert calibration constant to calibration value
+caltconst0 = 0x13C08312 ; 0.96*82.3*2^-6*2^8*2^14*2^6
+caltconst1 = 0x0000A532 ; 82.3*4.0145*2^8/2
+;caltconst2 = 0x00014877 ; (82.3*3.68+25.6)*2^8
+caltconst2 = 0x00013F77 ; (82.3*3.68+25.6-9)*2^8
+ push ar0
+ push ar1
+ ;; first compute offset
+ mov __mullong_PARM_2,r2
+ mov (__mullong_PARM_2+1),r3
+ mov a,r3
+ rlc a
+ subb a,acc
+ mov (__mullong_PARM_2+2),a
+ mov (__mullong_PARM_2+3),a
+ mov dptr,#caltconst1&0xffff
+ mov b,#caltconst1>>16
+ mov a,#caltconst1>>24
+ lcall __mullong
+ mov r1,a
+ pop acc
+ pop ar0
+ push ar0
+ push acc
+ clr c
+ rrc a
+ mov (__divslong_PARM_2 + 1),a
+ mov a,r0
+ rrc a
+ mov __divslong_PARM_2,a
+ clr a
+ mov (__divslong_PARM_2 + 2),a
+ mov (__divslong_PARM_2 + 3),a
+ mov a,r1
+ lcall __divslong
+ mov r0,dph
+ mov a,dpl
+ add a,#caltconst2&0xff
+ mov dptr,#_ADCCALTEMPOFFS0
+ movx @dptr,a
+ inc dptr
+ mov a,r0
+ addc a,#caltconst2>>8
+ movx @dptr,a
+ ;; second compute gain
+ pop (__divslong_PARM_2 + 1)
+ pop __divslong_PARM_2
+ clr a
+ mov (__divslong_PARM_2 + 2),a
+ mov (__divslong_PARM_2 + 3),a
+ mov dptr,#caltconst0&0xffff
+ mov b,#caltconst0>>16
+ mov a,#caltconst0>>24
+ lcall __divslong
+ mov a,dpl
+ mov r0,dph
+ mov dptr,#_ADCCALTEMPGAIN0
+ movx @dptr,a
+ inc dptr
+ mov a,r0
+ movx @dptr,a
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+void adc_calibrate_temp(void)
+{
+#pragma asm
+ using 0
+ extrn CODE (?C?LMUL)
+ extrn CODE (?C?SLDIV)
+ clr a
+ push IE
+ mov IE,a
+ push EIE
+ mov EIE,#0x40
+ push E2IE
+ mov E2IE,a
+ mov ADCCONV,a
+ mov r0,a
+ mov r1,a
+ mov r2,a
+ mov r3,a
+ mov ADCCLKSRC,#0x28 ; 0.625MHz/16
+ mov ADCCH0CONFIG,#0xf8
+ mov ADCCH1CONFIG,#0xf9
+ mov ADCCH2CONFIG,#0xff
+ mov ADCCH3CONFIG,#0xff
+ mov dptr,#ADCTUNE1
+ mov a,#0xf2
+ movx @dptr,a
+ mov dptr,#ADCCH0VAL0
+ movx a,@dptr
+ mov b,#0x10
+adccaltloop:
+ mov ADCCONV,#0x01
+adcwait1:
+ mov a,PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov PCON,a
+ mov a,ADCCLKSRC
+ jb acc.7,adcwait1
+ mov dptr,#ADCCH0VAL0
+ ;; channel 0
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r0
+ mov r0,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r1
+ mov r1,a
+ ;; channel 1
+ movx a,@dptr
+ inc dptr
+ swap a
+ anl a,#0x0f
+ mov r6,a
+ movx a,@dptr
+ inc dptr
+ swap a
+ mov r7,a
+ anl a,#0xf0
+ orl a,r6
+ add a,r2
+ mov r2,a
+ mov a,r7
+ anl a,#0x0f
+ addc a,r3
+ mov r3,a
+ djnz b,adccaltloop
+ ;; switch off ADC
+ mov dptr,#ADCTUNE1
+ mov a,#0x02
+ movx @dptr,a
+ mov ADCCLKSRC,#0x07 ; off
+ pop E2IE
+ pop EIE
+ pop IE
+ ;; convert calibration constant to calibration value
+caltconst0l equ 0x8312 ; 0.96*82.3*2^-6*2^8*2^14*2^6
+caltconst0h equ 0x13C0
+caltconst1l equ 0xA532 ; 82.3*4.0145*2^8/2
+caltconst1h equ 0x0000
+;caltconst2l equ 0x4877 ; (82.3*3.68+25.6)*2^8
+;caltconst2h equ 0x0001
+caltconst2l equ 0x3F77 ; (82.3*3.68+25.6-9)*2^8
+caltconst2h equ 0x0001
+ push ar0
+ push ar1
+ ;; first compute offset
+ mov r7,ar2
+ mov a,r3
+ mov r6,a
+ rlc a
+ subb a,acc
+ mov r5,a
+ mov r4,a
+ mov r3,#caltconst1l&0xff
+ mov r2,#caltconst1l>>8
+ mov r1,#caltconst1h&0xff
+ mov r0,#caltconst1h>>8
+ lcall ?C?LMUL
+ pop acc
+ pop ar3
+ push ar3
+ push acc
+ clr c
+ rrc a
+ mov r2,a
+ mov a,r3
+ rrc a
+ mov r3,a
+ clr a
+ mov r1,a
+ mov r0,a
+ lcall ?C?SLDIV
+ mov a,r7
+ add a,#caltconst2l&0xff
+ mov dptr,#ADCCALTEMPOFFS0
+ movx @dptr,a
+ inc dptr
+ mov a,r6
+ addc a,#caltconst2l>>8
+ movx @dptr,a
+ ;; second compute gain
+ pop ar2
+ pop ar3
+ clr a
+ mov r1,a
+ mov r0,a
+ mov r7,#caltconst0l&0xff
+ mov r6,#caltconst0l>>8
+ mov r5,#caltconst0h&0xff
+ mov r4,#caltconst0h>>8
+ lcall ?C?SLDIV
+ mov a,r7
+ mov dptr,#ADCCALTEMPGAIN0
+ movx @dptr,a
+ inc dptr
+ mov a,r6
+ movx @dptr,a
+#pragma endasm
+}
+
+#else
+
+void adc_calibrate_temp(void)
+{
+ static const int32_t caltconst0 = 0x13C08312; /* 0.96*82.3*2^-6*2^8*2^14*2^6 */
+ static const int32_t caltconst1 = 0x0000A532; /* 82.3*4.0145*2^8/2 */
+ /*static const uint16_t caltconst2 = 0x00014877; */ /* (82.3*3.68+25.6)*2^8 */
+ static const uint16_t caltconst2 = 0x00013F77; /* (82.3*3.68+25.6-9)*2^8 */
+ uint8_t __autodata iesave = IE, eiesave = EIE, e2iesave = E2IE, cnt = 0x10;
+ uint16_t __autodata adcv0 = 0, adcv1 = 0, v;
+ int32_t __autodata x;
+ IE = 0;
+ EIE = 0x40;
+ E2IE = 0;
+ ADCCONV = 0;
+ ADCCLKSRC = 0x28; /* 0.625MHz/16 */
+ ADCCH0CONFIG = 0xf8;
+ ADCCH1CONFIG = 0xf9;
+ ADCCH2CONFIG = 0xff;
+ ADCCH3CONFIG = 0xff;
+ ADCTUNE1 = 0xf2;
+ ADCCH0VAL0;
+ do {
+ ADCCONV = 0x01;
+ do {
+ enter_standby();
+ } while (ADCCLKSRC & 0x80);
+ v = ADCCH0VAL1;
+ v <<= 4;
+ v |= ADCCH0VAL0 >> 4;
+ adcv0 += v;
+ v = ADCCH1VAL1;
+ v <<= 4;
+ v |= ADCCH1VAL0 >> 4;
+ adcv1 += v;
+ } while (--cnt);
+ /* switch off ADC */
+ ADCTUNE1 = 0x02;
+ ADCCLKSRC = 0x07;
+ E2IE = e2iesave;
+ EIE = eiesave;
+ IE = iesave;
+ /* convert calibration constant to calibration value */
+ /* first compute offset */
+ v = (caltconst1 * (int16_t)adcv1) / (adcv0 >> 1);
+ v += caltconst2;
+ ADCCALTEMPOFFS0 = v;
+ ADCCALTEMPOFFS1 = v >> 8;
+ /* second compute gain */
+ v = caltconst0 / adcv0;
+ ADCCALTEMPGAIN0 = v;
+ ADCCALTEMPGAIN1 = v >> 8;
+}
+
+#endif
diff --git a/libs/libmf/source/adcseoffs00.c b/libs/libmf/source/adcseoffs00.c
new file mode 100644
index 00000000..7b784210
--- /dev/null
+++ b/libs/libmf/source/adcseoffs00.c
@@ -0,0 +1,25 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALG00GAIN0, 0x7030) /* ADC Calibration Range 00 Gain Low Byte */
+SFRX(ADCCALG00GAIN1, 0x7031) /* ADC Calibration Range 00 Gain High Byte */
+SFR16LEX(ADCCALG00GAIN, 0x7030) /* ADC Calibration Range 00 Gain */
+
+uint16_t adc_singleended_offset_x01(void)
+{
+#if defined(SDCC)
+ uint16_t __autodata cal = ADCCALG00GAIN;
+#else
+ uint16_t __autodata cal = (((uint16_t)ADCCALG00GAIN1) << 8) | ADCCALG00GAIN0;
+#endif
+ uint16_t __autodata sum = 0x8000;
+ cal <<= 1;
+ sum += cal;
+ cal >>= 5;
+ sum += cal;
+ cal >>= 4;
+ sum += cal;
+ cal >>= 4;
+ sum -= cal;
+ return sum;
+}
diff --git a/libs/libmf/source/adcseoffs01.c b/libs/libmf/source/adcseoffs01.c
new file mode 100644
index 00000000..0820ac2b
--- /dev/null
+++ b/libs/libmf/source/adcseoffs01.c
@@ -0,0 +1,25 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALG01GAIN0, 0x7032) /* ADC Calibration Range 01 Gain Low Byte */
+SFRX(ADCCALG01GAIN1, 0x7033) /* ADC Calibration Range 01 Gain High Byte */
+SFR16LEX(ADCCALG01GAIN, 0x7032) /* ADC Calibration Range 01 Gain */
+
+uint16_t adc_singleended_offset_x1(void)
+{
+#if defined(SDCC)
+ uint16_t __autodata cal = ADCCALG01GAIN;
+#else
+ uint16_t __autodata cal = (((uint16_t)ADCCALG01GAIN1) << 8) | ADCCALG01GAIN0;
+#endif
+ uint16_t __autodata sum = 0x8000;
+ cal <<= 1;
+ sum += cal;
+ cal >>= 5;
+ sum += cal;
+ cal >>= 4;
+ sum += cal;
+ cal >>= 4;
+ sum -= cal;
+ return sum;
+}
diff --git a/libs/libmf/source/adcseoffs10.c b/libs/libmf/source/adcseoffs10.c
new file mode 100644
index 00000000..3c48fc98
--- /dev/null
+++ b/libs/libmf/source/adcseoffs10.c
@@ -0,0 +1,25 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALG10GAIN0, 0x7034) /* ADC Calibration Range 10 Gain Low Byte */
+SFRX(ADCCALG10GAIN1, 0x7035) /* ADC Calibration Range 10 Gain High Byte */
+SFR16LEX(ADCCALG10GAIN, 0x7034) /* ADC Calibration Range 10 Gain */
+
+uint16_t adc_singleended_offset_x10(void)
+{
+#if defined(SDCC)
+ uint16_t __autodata cal = ADCCALG10GAIN;
+#else
+ uint16_t __autodata cal = (((uint16_t)ADCCALG10GAIN1) << 8) | ADCCALG10GAIN0;
+#endif
+ uint16_t __autodata sum = 0x8000;
+ cal <<= 1;
+ sum += cal;
+ cal >>= 5;
+ sum += cal;
+ cal >>= 4;
+ sum += cal;
+ cal >>= 4;
+ sum -= cal;
+ return sum;
+}
diff --git a/libs/libmf/source/adctemp.c b/libs/libmf/source/adctemp.c
new file mode 100644
index 00000000..a3a3d4e0
--- /dev/null
+++ b/libs/libmf/source/adctemp.c
@@ -0,0 +1,234 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+#if defined(SDCC)
+
+__reentrantb int16_t adc_measure_temperature(void) __reentrant
+{
+ __asm
+ clr a
+ mov b,_IE
+ mov _IE,a
+ mov r0,_EIE
+ mov _EIE,a
+ mov r1,_E2IE
+ mov _E2IE,a
+
+ mov dptr,#_ADCTUNE0
+ mov a,#0x01
+ movx @dptr,a
+ inc dptr
+ mov a,#0x06
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ clr a
+ movx @dptr,a
+
+ mov r3,_ADCCLKSRC
+ mov _ADCCLKSRC,#0x30
+
+ mov r4,_ADCCH0CONFIG
+ mov _ADCCH0CONFIG,#0xd8
+ mov r5,_ADCCH1CONFIG
+ mov _ADCCH1CONFIG,#0xd8
+ mov r6,_ADCCH2CONFIG
+ mov _ADCCH2CONFIG,#0xd8
+ mov r7,_ADCCH3CONFIG
+ mov _ADCCH3CONFIG,#0xd8
+
+ mov _ADCCONV,#0x01
+ setb _EIE_6
+00000$: mov a,_ADCCONV
+ jb acc.7,00001$
+ mov a,_PCON
+ anl a,#0x0c
+ orl a,#0x01
+ mov _PCON,a
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ sjmp 00000$
+00001$: ;; restore registers
+ mov _ADCCH0CONFIG,r4
+ mov _ADCCH1CONFIG,r5
+ mov _ADCCH2CONFIG,r6
+ mov _ADCCH3CONFIG,r7
+
+ mov _ADCCLKSRC,r3
+
+ mov dptr,#_ADCTUNE2
+ mov a,r2
+ movx @dptr,a
+
+ mov _EIE,r0
+ mov _E2IE,r1
+
+ mov dptr,#_ADCCH1VAL0
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ inc dptr
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+
+ mov _IE,b
+
+ ;; compute median
+
+ ;; A=R5:R4 - R3:R2
+ mov a,r4
+ clr c
+ subb a,r2
+ mov a,r5
+ subb a,r3
+ jnb acc.7,00010$
+ ;; if R3:R2 > R5:R4, swap
+ mov a,r2
+ xch a,r4
+ mov r2,a
+ mov a,r3
+ xch a,r5
+ mov r3,a
+00010$:
+ ;; A=R7:R6 - R5:R4
+ mov a,r6
+ clr c
+ subb a,r4
+ mov a,r7
+ subb a,r5
+ jnb acc.7,00011$
+ ;; if R5:R4 > R7:R6, swap
+ mov a,r4
+ xch a,r6
+ mov r4,a
+ mov a,r5
+ xch a,r7
+ mov r5,a
+00011$:
+ ;; A=R5:R4 - R3:R2
+ mov a,r4
+ clr c
+ subb a,r2
+ mov a,r5
+ subb a,r3
+ jnb acc.7,00012$
+ ;; if R3:R2 > R5:R4, swap
+ mov a,r2
+ xch a,r4
+ mov r2,a
+ mov a,r3
+ xch a,r5
+ mov r3,a
+00012$:
+
+ ;; return is in R5:R4
+ mov dpl,r4
+ mov dph,r5
+ __endasm;
+}
+
+#else
+
+// returns 256*temperature [deg]
+// median of ADC channels 1,2 and 3 is used.
+// Note: MCU is put in standby mode with all interrupts disabled during conversion!
+
+__reentrantb int16_t adc_measure_temperature(void) __reentrant
+{
+ int16_t t1, t2, t3;
+ {
+ uint8_t ie_save = IE;
+ uint8_t eie_save = EIE;
+ uint8_t e2ie_save = E2IE;
+ uint8_t tune2save, clksrcsave, ch0cfgsave, ch1cfgsave, ch2cfgsave, ch3cfgsave;
+ IE = 0;
+ EIE = 0;
+ E2IE = 0;
+
+ ADCTUNE0 = 0x01;
+ ADCTUNE1 = 0x06;
+ tune2save = ADCTUNE2;
+ ADCTUNE2 = 0x00;
+
+ clksrcsave = ADCCLKSRC;
+ ADCCLKSRC = 0x30;
+
+ // configure all channels for TEMP
+ ch0cfgsave = ADCCH0CONFIG;
+ ADCCH0CONFIG = 0xD8;
+ ch1cfgsave = ADCCH1CONFIG;
+ ADCCH1CONFIG = 0xD8;
+ ch2cfgsave = ADCCH2CONFIG;
+ ADCCH2CONFIG = 0xD8;
+ ch3cfgsave = ADCCH3CONFIG;
+ ADCCH3CONFIG = 0xD8;
+
+ ADCCONV = 0x01;
+ EIE_6 = 1;
+ for (;;) {
+ if (ADCCONV & 0x80)
+ break;
+ enter_standby();
+ }
+
+ t1 = ADCCH1VAL1;
+ t1 <<= 8;
+ t1 |= ADCCH1VAL0;
+
+ t2 = ADCCH2VAL1;
+ t2 <<= 8;
+ t2 |= ADCCH2VAL0;
+
+ t3 = ADCCH3VAL1;
+ t3 <<= 8;
+ t3 |= ADCCH3VAL0;
+
+ ADCCH0CONFIG = ch0cfgsave;
+ ADCCH1CONFIG = ch1cfgsave;
+ ADCCH2CONFIG = ch2cfgsave;
+ ADCCH3CONFIG = ch3cfgsave;
+ ADCCLKSRC = clksrcsave;
+ ADCTUNE2 = tune2save;
+
+ E2IE = e2ie_save;
+ EIE = eie_save;
+ IE = ie_save;
+
+ }
+ // compute median
+ if (t1 > t2) {
+ int16_t x = t1;
+ t1 = t2;
+ t2 = x;
+ }
+ if (t2 > t3) {
+ int16_t x = t2;
+ t2 = t3;
+ t3 = x;
+ }
+ if (t1 > t2) {
+ int16_t x = t1;
+ t1 = t2;
+ t2 = x;
+ }
+ return t2;
+}
+
+#endif
diff --git a/libs/libmf/source/adcuncal.c b/libs/libmf/source/adcuncal.c
new file mode 100644
index 00000000..e0a89131
--- /dev/null
+++ b/libs/libmf/source/adcuncal.c
@@ -0,0 +1,27 @@
+#include "ax8052.h"
+#include "libmfadc.h"
+
+SFRX(ADCCALG00GAIN0, 0x7030) /* ADC Calibration Range 00 Gain Low Byte */
+SFRX(ADCCALG00GAIN1, 0x7031) /* ADC Calibration Range 00 Gain High Byte */
+SFRX(ADCCALG01GAIN0, 0x7032) /* ADC Calibration Range 01 Gain Low Byte */
+SFRX(ADCCALG01GAIN1, 0x7033) /* ADC Calibration Range 01 Gain High Byte */
+SFRX(ADCCALG10GAIN0, 0x7034) /* ADC Calibration Range 10 Gain Low Byte */
+SFRX(ADCCALG10GAIN1, 0x7035) /* ADC Calibration Range 10 Gain High Byte */
+SFRX(ADCCALTEMPGAIN0, 0x7038) /* ADC Calibration Temperature Gain Low Byte */
+SFRX(ADCCALTEMPGAIN1, 0x7039) /* ADC Calibration Temperature Gain High Byte */
+SFRX(ADCCALTEMPOFFS0, 0x703A) /* ADC Calibration Temperature Offset Low Byte */
+SFRX(ADCCALTEMPOFFS1, 0x703B) /* ADC Calibration Temperature Offset High Byte */
+
+void adc_uncalibrate(void)
+{
+ ADCCALG00GAIN0 = 0x00;
+ ADCCALG00GAIN1 = 0x40;
+ ADCCALG01GAIN0 = 0x00;
+ ADCCALG01GAIN1 = 0x40;
+ ADCCALG10GAIN0 = 0x00;
+ ADCCALG10GAIN1 = 0x40;
+ ADCCALTEMPGAIN0 = 0x00;
+ ADCCALTEMPGAIN1 = 0x40;
+ ADCCALTEMPOFFS0 = 0x00;
+ ADCCALTEMPOFFS1 = 0x00;
+}
diff --git a/libs/libmf/source/ax5031rclkdis.c b/libs/libmf/source/ax5031rclkdis.c
new file mode 100644
index 00000000..71c4925e
--- /dev/null
+++ b/libs/libmf/source/ax5031rclkdis.c
@@ -0,0 +1,16 @@
+#include "ax8052f131.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5031_rclk_disable(void) __reentrant
+{
+ uint8_t p, irqe;
+ irqe = IE & 0x80;
+ EA = 0;
+ PORTR |= 0x02;
+ AX5031_PINCFG1 = (AX5031_PINCFG1 & 0xF0) | 0x01;
+ p = AX5031_PWRMODE;
+ if ((p & 0x0F) == 0x05)
+ AX5031_PWRMODE = (p & 0xF0);
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5031rclkena.c b/libs/libmf/source/ax5031rclkena.c
new file mode 100644
index 00000000..cdfe80e6
--- /dev/null
+++ b/libs/libmf/source/ax5031rclkena.c
@@ -0,0 +1,19 @@
+#include "ax8052f131.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5031_rclk_enable(uint8_t div) __reentrant
+{
+ uint8_t p, irqe;
+ if (div >= 11)
+ div = 11;
+ div += 4;
+ irqe = IE & 0x80;
+ EA = 0;
+ AX5031_PINCFG1 = (AX5031_PINCFG1 & 0xF0) | div;
+ PORTR &= (uint8_t)~0x02;
+ p = AX5031_PWRMODE;
+ if (!(p & 0x0F))
+ AX5031_PWRMODE = (p & 0xF0) | 0x05;
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5031regs.c b/libs/libmf/source/ax5031regs.c
new file mode 100644
index 00000000..ccae399f
--- /dev/null
+++ b/libs/libmf/source/ax5031regs.c
@@ -0,0 +1,17 @@
+#if defined __ICC8051__
+
+#define AXCOMPILER_H
+# define SBIT(name, addr, bit)
+# define SFR(name, addr)
+# define SFRX(name, addr) __no_init __root volatile unsigned char __xdata name @ addr ;
+# define SFR16(name, addr)
+# define SFR16E(name, fulladdr)
+# define SFR16LEX(name, addr)
+# define SFR32(name, fulladdr)
+# define SFR32E(name, fulladdr)
+
+#define AX8052_H
+
+#include "ax8052f131.h"
+
+#endif
diff --git a/libs/libmf/source/ax5042rclkdis.c b/libs/libmf/source/ax5042rclkdis.c
new file mode 100644
index 00000000..71c0fae7
--- /dev/null
+++ b/libs/libmf/source/ax5042rclkdis.c
@@ -0,0 +1,16 @@
+#include "ax8052f142.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5042_rclk_disable(void) __reentrant
+{
+ uint8_t p, irqe;
+ irqe = IE & 0x80;
+ EA = 0;
+ PORTR |= 0x02;
+ AX5042_PINCFG1 = (AX5042_PINCFG1 & 0xF0) | 0x01;
+ p = AX5042_PWRMODE;
+ if ((p & 0x2F) == 0x00)
+ AX5042_APEOVERRIDE = 0x80;
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5042rclkena.c b/libs/libmf/source/ax5042rclkena.c
new file mode 100644
index 00000000..9de4e47c
--- /dev/null
+++ b/libs/libmf/source/ax5042rclkena.c
@@ -0,0 +1,19 @@
+#include "ax8052f142.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5042_rclk_enable(uint8_t div) __reentrant
+{
+ uint8_t p, irqe;
+ if (div >= 11)
+ div = 11;
+ div += 4;
+ irqe = IE & 0x80;
+ EA = 0;
+ AX5042_PINCFG1 = (AX5042_PINCFG1 & 0xF0) | div;
+ PORTR &= (uint8_t)~0x02;
+ p = AX5042_PWRMODE;
+ if (!(p & 0x0F))
+ AX5042_APEOVERRIDE = 0x00;
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5042regs.c b/libs/libmf/source/ax5042regs.c
new file mode 100644
index 00000000..0e3fdf16
--- /dev/null
+++ b/libs/libmf/source/ax5042regs.c
@@ -0,0 +1,17 @@
+#if defined __ICC8051__
+
+#define AXCOMPILER_H
+# define SBIT(name, addr, bit)
+# define SFR(name, addr)
+# define SFRX(name, addr) __no_init __root volatile unsigned char __xdata name @ addr ;
+# define SFR16(name, addr)
+# define SFR16E(name, fulladdr)
+# define SFR16LEX(name, addr)
+# define SFR32(name, fulladdr)
+# define SFR32E(name, fulladdr)
+
+#define AX8052_H
+
+#include "ax8052f142.h"
+
+#endif
diff --git a/libs/libmf/source/ax5043rclkdis.c b/libs/libmf/source/ax5043rclkdis.c
new file mode 100644
index 00000000..85f403c2
--- /dev/null
+++ b/libs/libmf/source/ax5043rclkdis.c
@@ -0,0 +1,16 @@
+#include "ax8052f143.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5043_rclk_disable(void) __reentrant
+{
+ uint8_t p, irqe;
+ irqe = IE & 0x80;
+ EA = 0;
+ PORTR |= 0x02;
+ AX5043_PINFUNCSYSCLK = 0x01;
+ p = AX5043_PWRMODE;
+ if ((p & 0x0F) == 0x05)
+ AX5043_PWRMODE = (p & 0xF0);
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5043rclkena.c b/libs/libmf/source/ax5043rclkena.c
new file mode 100644
index 00000000..b5e9108e
--- /dev/null
+++ b/libs/libmf/source/ax5043rclkena.c
@@ -0,0 +1,19 @@
+#include "ax8052f143.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5043_rclk_enable(uint8_t div) __reentrant
+{
+ uint8_t p, irqe;
+ if (div >= 10)
+ div = 10;
+ div += 4;
+ irqe = IE & 0x80;
+ EA = 0;
+ AX5043_PINFUNCSYSCLK = div;
+ PORTR &= (uint8_t)~0x02;
+ p = AX5043_PWRMODE;
+ if (!(p & 0x0F))
+ AX5043_PWRMODE = (p & 0xF0) | 0x05;
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5043regs.c b/libs/libmf/source/ax5043regs.c
new file mode 100644
index 00000000..620b65f6
--- /dev/null
+++ b/libs/libmf/source/ax5043regs.c
@@ -0,0 +1,17 @@
+#if defined __ICC8051__
+
+#define AXCOMPILER_H
+# define SBIT(name, addr, bit)
+# define SFR(name, addr)
+# define SFRX(name, addr) __no_init __root volatile unsigned char __xdata name @ addr ;
+# define SFR16(name, addr)
+# define SFR16E(name, fulladdr)
+# define SFR16LEX(name, addr)
+# define SFR32(name, fulladdr)
+# define SFR32E(name, fulladdr)
+
+#define AX8052_H
+
+#include "ax8052f143.h"
+
+#endif
diff --git a/libs/libmf/source/ax5051rclkdis.c b/libs/libmf/source/ax5051rclkdis.c
new file mode 100644
index 00000000..487f9525
--- /dev/null
+++ b/libs/libmf/source/ax5051rclkdis.c
@@ -0,0 +1,16 @@
+#include "ax8052f151.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5051_rclk_disable(void) __reentrant
+{
+ uint8_t p, irqe;
+ irqe = IE & 0x80;
+ EA = 0;
+ PORTR |= 0x02;
+ AX5051_PINCFG1 = (AX5051_PINCFG1 & 0xF0) | 0x01;
+ p = AX5051_PWRMODE;
+ if ((p & 0x0F) == 0x05)
+ AX5051_PWRMODE = (p & 0xF0);
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5051rclkena.c b/libs/libmf/source/ax5051rclkena.c
new file mode 100644
index 00000000..1e8144c8
--- /dev/null
+++ b/libs/libmf/source/ax5051rclkena.c
@@ -0,0 +1,19 @@
+#include "ax8052f151.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+__reentrantb void ax5051_rclk_enable(uint8_t div) __reentrant
+{
+ uint8_t p, irqe;
+ if (div >= 11)
+ div = 11;
+ div += 4;
+ irqe = IE & 0x80;
+ EA = 0;
+ AX5051_PINCFG1 = (AX5051_PINCFG1 & 0xF0) | div;
+ PORTR &= (uint8_t)~0x02;
+ p = AX5051_PWRMODE;
+ if (!(p & 0x0F))
+ AX5051_PWRMODE = (p & 0xF0) | 0x05;
+ IE |= irqe;
+}
diff --git a/libs/libmf/source/ax5051regs.c b/libs/libmf/source/ax5051regs.c
new file mode 100644
index 00000000..49979b3e
--- /dev/null
+++ b/libs/libmf/source/ax5051regs.c
@@ -0,0 +1,17 @@
+#if defined __ICC8051__
+
+#define AXCOMPILER_H
+# define SBIT(name, addr, bit)
+# define SFR(name, addr)
+# define SFRX(name, addr) __no_init __root volatile unsigned char __xdata name @ addr ;
+# define SFR16(name, addr)
+# define SFR16E(name, fulladdr)
+# define SFR16LEX(name, addr)
+# define SFR32(name, fulladdr)
+# define SFR32E(name, fulladdr)
+
+#define AX8052_H
+
+#include "ax8052f151.h"
+
+#endif
diff --git a/libs/libmf/source/ax8052.h b/libs/libmf/source/ax8052.h
new file mode 100644
index 00000000..0d85a9f2
--- /dev/null
+++ b/libs/libmf/source/ax8052.h
@@ -0,0 +1,588 @@
+/*-------------------------------------------------------------------------
+ AX8052.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052_H
+#define AX8052_H
+
+#include
+
+/* SFR Address Space */
+
+SFR(ACC, 0xE0) /* Accumulator */
+SBIT(ACC_0, 0xE0, 0) /* Accumulator bit 0 */
+SBIT(ACC_1, 0xE0, 1) /* Accumulator bit 1 */
+SBIT(ACC_2, 0xE0, 2) /* Accumulator bit 2 */
+SBIT(ACC_3, 0xE0, 3) /* Accumulator bit 3 */
+SBIT(ACC_4, 0xE0, 4) /* Accumulator bit 4 */
+SBIT(ACC_5, 0xE0, 5) /* Accumulator bit 5 */
+SBIT(ACC_6, 0xE0, 6) /* Accumulator bit 6 */
+SBIT(ACC_7, 0xE0, 7) /* Accumulator bit 7 */
+SFR(B, 0xF0) /* B Register */
+SBIT(B_0, 0xF0, 0) /* Register B bit 0 */
+SBIT(B_1, 0xF0, 1) /* Register B bit 1 */
+SBIT(B_2, 0xF0, 2) /* Register B bit 2 */
+SBIT(B_3, 0xF0, 3) /* Register B bit 3 */
+SBIT(B_4, 0xF0, 4) /* Register B bit 4 */
+SBIT(B_5, 0xF0, 5) /* Register B bit 5 */
+SBIT(B_6, 0xF0, 6) /* Register B bit 6 */
+SBIT(B_7, 0xF0, 7) /* Register B bit 7 */
+SFR(DPH, 0x83) /* Data Pointer 0 High Byte */
+SFR(DPH1, 0x85) /* Data Pointer 1 High Byte */
+SFR(DPL, 0x82) /* Data Pointer 0 Low Byte */
+SFR(DPL1, 0x84) /* Data Pointer 1 Low Byte */
+SFR16(DPTR0, 0x82) /* Data Pointer 0 */
+SFR16(DPTR1, 0x84) /* Data Pointer 1 */
+SFR(DPS, 0x86) /* Data Pointer Select */
+SFR(E2IE, 0xA0) /* 2nd Extended Interrupt Enable */
+SBIT(E2IE_0, 0xA0, 0) /* Output Compare 0 Interrupt Enable */
+SBIT(E2IE_1, 0xA0, 1) /* Output Compare 1 Interrupt Enable */
+SBIT(E2IE_2, 0xA0, 2) /* Input Capture 0 Interrupt Enable */
+SBIT(E2IE_3, 0xA0, 3) /* Input Capture 1 Interrupt Enable */
+SBIT(E2IE_4, 0xA0, 4) /* */
+SBIT(E2IE_5, 0xA0, 5) /* */
+SBIT(E2IE_6, 0xA0, 6) /* DebugLink Interrupt Enable */
+SBIT(E2IE_7, 0xA0, 7) /* */
+SFR(E2IP, 0xC0) /* 2nd Extended Interrupt Priority */
+SBIT(E2IP_0, 0xC0, 0) /* Output Compare 0 Interrupt Priority */
+SBIT(E2IP_1, 0xC0, 1) /* Output Compare 1 Interrupt Priority */
+SBIT(E2IP_2, 0xC0, 2) /* Input Capture 0 Interrupt Priority */
+SBIT(E2IP_3, 0xC0, 3) /* Input Capture 1 Interrupt Priority */
+SBIT(E2IP_4, 0xC0, 4) /* */
+SBIT(E2IP_5, 0xC0, 5) /* */
+SBIT(E2IP_6, 0xC0, 6) /* DebugLink Interrupt Priority */
+SBIT(E2IP_7, 0xC0, 7) /* */
+SFR(EIE, 0x98) /* Extended Interrupt Enable */
+SBIT(EIE_0, 0x98, 0) /* Timer 0 Interrupt Enable */
+SBIT(EIE_1, 0x98, 1) /* Timer 1 Interrupt Enable */
+SBIT(EIE_2, 0x98, 2) /* Timer 2 Interrupt Enable */
+SBIT(EIE_3, 0x98, 3) /* SPI 0 Interrupt Enable */
+SBIT(EIE_4, 0x98, 4) /* UART 0 Interrupt Enable */
+SBIT(EIE_5, 0x98, 5) /* UART 1 Interrupt Enable */
+SBIT(EIE_6, 0x98, 6) /* GPADC Interrupt Enable */
+SBIT(EIE_7, 0x98, 7) /* DMA Interrupt Enable */
+SFR(EIP, 0xB0) /* Extended Interrupt Priority */
+SBIT(EIP_0, 0xB0, 0) /* Timer 0 Interrupt Priority */
+SBIT(EIP_1, 0xB0, 1) /* Timer 1 Interrupt Priority */
+SBIT(EIP_2, 0xB0, 2) /* Timer 2 Interrupt Priority */
+SBIT(EIP_3, 0xB0, 3) /* SPI 0 Interrupt Priority */
+SBIT(EIP_4, 0xB0, 4) /* UART 0 Interrupt Priority */
+SBIT(EIP_5, 0xB0, 5) /* UART 1 Interrupt Priority */
+SBIT(EIP_6, 0xB0, 6) /* GPADC Interrupt Priority */
+SBIT(EIP_7, 0xB0, 7) /* DMA Interrupt Priority */
+SFR(IE, 0xA8) /* Interrupt Enable */
+SBIT(IE_0, 0xA8, 0) /* External 0 Interrupt Enable */
+SBIT(IE_1, 0xA8, 1) /* Wakeup Timer Interrupt Enable */
+SBIT(IE_2, 0xA8, 2) /* External 1 Interrupt Enable */
+SBIT(IE_3, 0xA8, 3) /* GPIO Interrupt Enable */
+SBIT(IE_4, 0xA8, 4) /* Radio Interrupt Enable */
+SBIT(IE_5, 0xA8, 5) /* Clock Management Interrupt Enable */
+SBIT(IE_6, 0xA8, 6) /* Power Management Interrupt Enable */
+SBIT(IE_7, 0xA8, 7) /* Global Interrupt Enable */
+SBIT(EA, 0xA8, 7) /* Global Interrupt Enable */
+SFR(IP, 0xB8) /* Interrupt Priority */
+SBIT(IP_0, 0xB8, 0) /* External 0 Interrupt Priority */
+SBIT(IP_1, 0xB8, 1) /* Wakeup Timer Interrupt Priority */
+SBIT(IP_2, 0xB8, 2) /* External 1 Interrupt Priority */
+SBIT(IP_3, 0xB8, 3) /* GPIO Interrupt Priority */
+SBIT(IP_4, 0xB8, 4) /* Radio Interrupt Priority */
+SBIT(IP_5, 0xB8, 5) /* Clock Management Interrupt Priority */
+SBIT(IP_6, 0xB8, 6) /* Power Management Interrupt Priority */
+SBIT(IP_7, 0xB8, 7) /* */
+SFR(PCON, 0x87) /* Power Mode Control */
+SFR(PSW, 0xD0) /* Program Status Word */
+SBIT(P, 0xD0, 0) /* Parity Flag */
+SBIT(F1, 0xD0, 1) /* User-Defined Flag */
+SBIT(OV, 0xD0, 2) /* Overflow Flag */
+SBIT(RS0, 0xD0, 3) /* Register Bank Select 0 */
+SBIT(RS1, 0xD0, 4) /* Register Bank Select 1 */
+SBIT(F0, 0xD0, 5) /* User-Defined Flag */
+SBIT(AC, 0xD0, 6) /* Auxiliary Carry Flag */
+SBIT(CY, 0xD0, 7) /* Carry Flag */
+SFR(SP, 0x81) /* Stack Pointer */
+SFR(XPAGE, 0xD9) /* Memory Page Select */
+SFR(_XPAGE, 0xD9) /* Memory Page Select, SDCC name */
+SFR(ADCCH0CONFIG, 0xCA) /* ADC Channel 0 Configuration */
+SFR(ADCCH1CONFIG, 0xCB) /* ADC Channel 1 Configuration */
+SFR(ADCCH2CONFIG, 0xD2) /* ADC Channel 2 Configuration */
+SFR(ADCCH3CONFIG, 0xD3) /* ADC Channel 3 Configuration */
+SFR(ADCCLKSRC, 0xD1) /* ADC Clock Source */
+SFR(ADCCONV, 0xC9) /* ADC Conversion Source */
+SFR(ANALOGCOMP, 0xE1) /* Analog Comparators */
+SFR(CLKCON, 0xC6) /* Clock Control */
+SFR(CLKSTAT, 0xC7) /* Clock Status */
+SFR(CODECONFIG, 0x97) /* Code Space Configuration */
+SFR(DBGLNKBUF, 0xE3) /* Debug Link Buffer */
+SFR(DBGLNKSTAT, 0xE2) /* Debug Link Status */
+SFR(DIRA, 0x89) /* Port A Direction */
+SFR(DIRB, 0x8A) /* Port B Direction */
+SFR(DIRC, 0x8B) /* Port C Direction */
+SFR(DIRR, 0x8E) /* Port R Direction */
+SFR(PINA, 0xC8) /* Port A Input */
+SBIT(PINA_0, 0xC8, 0) /* */
+SBIT(PINA_1, 0xC8, 1) /* */
+SBIT(PINA_2, 0xC8, 2) /* */
+SBIT(PINA_3, 0xC8, 3) /* */
+SBIT(PINA_4, 0xC8, 4) /* */
+SBIT(PINA_5, 0xC8, 5) /* */
+SBIT(PINA_6, 0xC8, 6) /* */
+SBIT(PINA_7, 0xC8, 7) /* */
+SFR(PINB, 0xE8) /* Port B Input */
+SBIT(PINB_0, 0xE8, 0) /* */
+SBIT(PINB_1, 0xE8, 1) /* */
+SBIT(PINB_2, 0xE8, 2) /* */
+SBIT(PINB_3, 0xE8, 3) /* */
+SBIT(PINB_4, 0xE8, 4) /* */
+SBIT(PINB_5, 0xE8, 5) /* */
+SBIT(PINB_6, 0xE8, 6) /* */
+SBIT(PINB_7, 0xE8, 7) /* */
+SFR(PINC, 0xF8) /* Port C Input */
+SBIT(PINC_0, 0xF8, 0) /* */
+SBIT(PINC_1, 0xF8, 1) /* */
+SBIT(PINC_2, 0xF8, 2) /* */
+SBIT(PINC_3, 0xF8, 3) /* */
+SBIT(PINC_4, 0xF8, 4) /* */
+SBIT(PINC_5, 0xF8, 5) /* */
+SBIT(PINC_6, 0xF8, 6) /* */
+SBIT(PINC_7, 0xF8, 7) /* */
+SFR(PINR, 0x8D) /* Port R Input */
+SFR(PORTA, 0x80) /* Port A Output */
+SBIT(PORTA_0, 0x80, 0) /* */
+SBIT(PORTA_1, 0x80, 1) /* */
+SBIT(PORTA_2, 0x80, 2) /* */
+SBIT(PORTA_3, 0x80, 3) /* */
+SBIT(PORTA_4, 0x80, 4) /* */
+SBIT(PORTA_5, 0x80, 5) /* */
+SBIT(PORTA_6, 0x80, 6) /* */
+SBIT(PORTA_7, 0x80, 7) /* */
+SFR(PORTB, 0x88) /* Port B Output */
+SBIT(PORTB_0, 0x88, 0) /* */
+SBIT(PORTB_1, 0x88, 1) /* */
+SBIT(PORTB_2, 0x88, 2) /* */
+SBIT(PORTB_3, 0x88, 3) /* */
+SBIT(PORTB_4, 0x88, 4) /* */
+SBIT(PORTB_5, 0x88, 5) /* */
+SBIT(PORTB_6, 0x88, 6) /* */
+SBIT(PORTB_7, 0x88, 7) /* */
+SFR(PORTC, 0x90) /* Port C Output */
+SBIT(PORTC_0, 0x90, 0) /* */
+SBIT(PORTC_1, 0x90, 1) /* */
+SBIT(PORTC_2, 0x90, 2) /* */
+SBIT(PORTC_3, 0x90, 3) /* */
+SBIT(PORTC_4, 0x90, 4) /* */
+SBIT(PORTC_5, 0x90, 5) /* */
+SBIT(PORTC_6, 0x90, 6) /* */
+SBIT(PORTC_7, 0x90, 7) /* */
+SFR(PORTR, 0x8C) /* Port R Output */
+SFR(IC0CAPT0, 0xCE) /* Input Capture 0 Low Byte */
+SFR(IC0CAPT1, 0xCF) /* Input Capture 0 High Byte */
+SFR16(IC0CAPT, 0xCE) /* Input Capture 0 */
+SFR(IC0MODE, 0xCC) /* Input Capture 0 Mode */
+SFR(IC0STATUS, 0xCD) /* Input Capture 0 Status */
+SFR(IC1CAPT0, 0xD6) /* Input Capture 1 Low Byte */
+SFR(IC1CAPT1, 0xD7) /* Input Capture 1 High Byte */
+SFR16(IC1CAPT, 0xD6) /* Input Capture 1 */
+SFR(IC1MODE, 0xD4) /* Input Capture 1 Mode */
+SFR(IC1STATUS, 0xD5) /* Input Capture 1 Status */
+SFR(NVADDR0, 0x92) /* Non-Volatile Memory Address Low Byte */
+SFR(NVADDR1, 0x93) /* Non-Volatile Memory Address High Byte */
+SFR16(NVADDR, 0x92) /* Non-Volatile Memory Address */
+SFR(NVDATA0, 0x94) /* Non-Volatile Memory Data Low Byte */
+SFR(NVDATA1, 0x95) /* Non-Volatile Memory Data High Byte */
+SFR16(NVDATA, 0x94) /* Non-Volatile Memory Data */
+SFR(NVKEY, 0x96) /* Non-Volatile Memory Write/Erase Key */
+SFR(NVSTATUS, 0x91) /* Non-Volatile Memory Command / Status */
+SFR(OC0COMP0, 0xBC) /* Output Compare 0 Low Byte */
+SFR(OC0COMP1, 0xBD) /* Output Compare 0 High Byte */
+SFR16(OC0COMP, 0xBC) /* Output Compare 0 */
+SFR(OC0MODE, 0xB9) /* Output Compare 0 Mode */
+SFR(OC0PIN, 0xBA) /* Output Compare 0 Pin Configuration */
+SFR(OC0STATUS, 0xBB) /* Output Compare 0 Status */
+SFR(OC1COMP0, 0xC4) /* Output Compare 1 Low Byte */
+SFR(OC1COMP1, 0xC5) /* Output Compare 1 High Byte */
+SFR16(OC1COMP, 0xC4) /* Output Compare 1 */
+SFR(OC1MODE, 0xC1) /* Output Compare 1 Mode */
+SFR(OC1PIN, 0xC2) /* Output Compare 1 Pin Configuration */
+SFR(OC1STATUS, 0xC3) /* Output Compare 1 Status */
+SFR(RADIOACC, 0xB1) /* Radio Controller Access Mode */
+SFR(RADIOADDR0, 0xB3) /* Radio Register Address Low Byte */
+SFR(RADIOADDR1, 0xB2) /* Radio Register Address High Byte */
+SFR16E(RADIOADDR, 0xB2B3) /* Radio Register Address */
+SFR(RADIODATA0, 0xB7) /* Radio Register Data 0 */
+SFR(RADIODATA1, 0xB6) /* Radio Register Data 1 */
+SFR(RADIODATA2, 0xB5) /* Radio Register Data 2 */
+SFR(RADIODATA3, 0xB4) /* Radio Register Data 3 */
+SFR32E(RADIODATA, 0xB4B5B6B7) /* Radio Register Data */
+SFR(RADIOSTAT0, 0xBE) /* Radio Access Status Low Byte */
+SFR(RADIOSTAT1, 0xBF) /* Radio Access Status High Byte */
+SFR16(RADIOSTAT, 0xBE) /* Radio Access Status */
+SFR(SPCLKSRC, 0xDF) /* SPI Clock Source */
+SFR(SPMODE, 0xDC) /* SPI Mode */
+SFR(SPSHREG, 0xDE) /* SPI Shift Register */
+SFR(SPSTATUS, 0xDD) /* SPI Status */
+SFR(T0CLKSRC, 0x9A) /* Timer 0 Clock Source */
+SFR(T0CNT0, 0x9C) /* Timer 0 Count Low Byte */
+SFR(T0CNT1, 0x9D) /* Timer 0 Count High Byte */
+SFR16(T0CNT, 0x9C) /* Timer 0 Count */
+SFR(T0MODE, 0x99) /* Timer 0 Mode */
+SFR(T0PERIOD0, 0x9E) /* Timer 0 Period Low Byte */
+SFR(T0PERIOD1, 0x9F) /* Timer 0 Period High Byte */
+SFR16(T0PERIOD, 0x9E) /* Timer 0 Period */
+SFR(T0STATUS, 0x9B) /* Timer 0 Status */
+SFR(T1CLKSRC, 0xA2) /* Timer 1 Clock Source */
+SFR(T1CNT0, 0xA4) /* Timer 1 Count Low Byte */
+SFR(T1CNT1, 0xA5) /* Timer 1 Count High Byte */
+SFR16(T1CNT, 0xA4) /* Timer 1 Count */
+SFR(T1MODE, 0xA1) /* Timer 1 Mode */
+SFR(T1PERIOD0, 0xA6) /* Timer 1 Period Low Byte */
+SFR(T1PERIOD1, 0xA7) /* Timer 1 Period High Byte */
+SFR16(T1PERIOD, 0xA6) /* Timer 1 Period */
+SFR(T1STATUS, 0xA3) /* Timer 1 Status */
+SFR(T2CLKSRC, 0xAA) /* Timer 2 Clock Source */
+SFR(T2CNT0, 0xAC) /* Timer 2 Count Low Byte */
+SFR(T2CNT1, 0xAD) /* Timer 2 Count High Byte */
+SFR16(T2CNT, 0xAC) /* Timer 2 Count */
+SFR(T2MODE, 0xA9) /* Timer 2 Mode */
+SFR(T2PERIOD0, 0xAE) /* Timer 2 Period Low Byte */
+SFR(T2PERIOD1, 0xAF) /* Timer 2 Period High Byte */
+SFR16(T2PERIOD, 0xAE) /* Timer 2 Period */
+SFR(T2STATUS, 0xAB) /* Timer 2 Status */
+SFR(U0CTRL, 0xE4) /* UART 0 Control */
+SFR(U0MODE, 0xE7) /* UART 0 Mode */
+SFR(U0SHREG, 0xE6) /* UART 0 Shift Register */
+SFR(U0STATUS, 0xE5) /* UART 0 Status */
+SFR(U1CTRL, 0xEC) /* UART 1 Control */
+SFR(U1MODE, 0xEF) /* UART 1 Mode */
+SFR(U1SHREG, 0xEE) /* UART 1 Shift Register */
+SFR(U1STATUS, 0xED) /* UART 1 Status */
+SFR(WDTCFG, 0xDA) /* Watchdog Configuration */
+SFR(WDTRESET, 0xDB) /* Watchdog Reset */
+SFR(WTCFGA, 0xF1) /* Wakeup Timer A Configuration */
+SFR(WTCFGB, 0xF9) /* Wakeup Timer B Configuration */
+SFR(WTCNTA0, 0xF2) /* Wakeup Counter A Low Byte */
+SFR(WTCNTA1, 0xF3) /* Wakeup Counter A High Byte */
+SFR16(WTCNTA, 0xF2) /* Wakeup Counter A */
+SFR(WTCNTB0, 0xFA) /* Wakeup Counter B Low Byte */
+SFR(WTCNTB1, 0xFB) /* Wakeup Counter B High Byte */
+SFR16(WTCNTB, 0xFA) /* Wakeup Counter B */
+SFR(WTCNTR1, 0xEB) /* Wakeup Counter High Byte Latch */
+SFR(WTEVTA0, 0xF4) /* Wakeup Event A Low Byte */
+SFR(WTEVTA1, 0xF5) /* Wakeup Event A High Byte */
+SFR16(WTEVTA, 0xF4) /* Wakeup Event A */
+SFR(WTEVTB0, 0xF6) /* Wakeup Event B Low Byte */
+SFR(WTEVTB1, 0xF7) /* Wakeup Event B High Byte */
+SFR16(WTEVTB, 0xF6) /* Wakeup Event B */
+SFR(WTEVTC0, 0xFC) /* Wakeup Event C Low Byte */
+SFR(WTEVTC1, 0xFD) /* Wakeup Event C High Byte */
+SFR16(WTEVTC, 0xFC) /* Wakeup Event C */
+SFR(WTEVTD0, 0xFE) /* Wakeup Event D Low Byte */
+SFR(WTEVTD1, 0xFF) /* Wakeup Event D High Byte */
+SFR16(WTEVTD, 0xFE) /* Wakeup Event D */
+SFR(WTIRQEN, 0xE9) /* Wakeup Timer Interrupt Enable */
+SFR(WTSTAT, 0xEA) /* Wakeup Timer Status */
+
+/* X Address Space */
+
+#define AX8052_RADIOBASE 0x4000
+#define AX8052_RADIOBASENB 0x5000
+
+SFRX(ADCCH0VAL0, 0x7020) /* ADC Channel 0 Low Byte */
+SFRX(ADCCH0VAL1, 0x7021) /* ADC Channel 0 High Byte */
+SFR16LEX(ADCCH0VAL, 0x7020) /* ADC Channel 0 */
+SFRX(ADCCH1VAL0, 0x7022) /* ADC Channel 1 Low Byte */
+SFRX(ADCCH1VAL1, 0x7023) /* ADC Channel 1 High Byte */
+SFR16LEX(ADCCH1VAL, 0x7022) /* ADC Channel 1 */
+SFRX(ADCCH2VAL0, 0x7024) /* ADC Channel 2 Low Byte */
+SFRX(ADCCH2VAL1, 0x7025) /* ADC Channel 2 High Byte */
+SFR16LEX(ADCCH2VAL, 0x7024) /* ADC Channel 2 */
+SFRX(ADCCH3VAL0, 0x7026) /* ADC Channel 3 Low Byte */
+SFRX(ADCCH3VAL1, 0x7027) /* ADC Channel 3 High Byte */
+SFR16LEX(ADCCH3VAL, 0x7026) /* ADC Channel 3 */
+SFRX(ADCTUNE0, 0x7028) /* ADC Tuning 0 */
+SFRX(ADCTUNE1, 0x7029) /* ADC Tuning 1 */
+SFRX(ADCTUNE2, 0x702A) /* ADC Tuning 2 */
+SFRX(DMA0ADDR0, 0x7010) /* DMA Channel 0 Address Low Byte */
+SFRX(DMA0ADDR1, 0x7011) /* DMA Channel 0 Address High Byte */
+SFR16LEX(DMA0ADDR, 0x7010) /* DMA Channel 0 Address */
+SFRX(DMA0CONFIG, 0x7014) /* DMA Channel 0 Configuration */
+SFRX(DMA1ADDR0, 0x7012) /* DMA Channel 1 Address Low Byte */
+SFRX(DMA1ADDR1, 0x7013) /* DMA Channel 1 Address High Byte */
+SFR16LEX(DMA1ADDR, 0x7012) /* DMA Channel 1 Address */
+SFRX(DMA1CONFIG, 0x7015) /* DMA Channel 1 Configuration */
+SFRX(FRCOSCCONFIG, 0x7070) /* Fast RC Oscillator Calibration Configuration */
+SFRX(FRCOSCCTRL, 0x7071) /* Fast RC Oscillator Control */
+SFRX(FRCOSCFREQ0, 0x7076) /* Fast RC Oscillator Frequency Tuning Low Byte */
+SFRX(FRCOSCFREQ1, 0x7077) /* Fast RC Oscillator Frequency Tuning High Byte */
+SFR16LEX(FRCOSCFREQ, 0x7076) /* Fast RC Oscillator Frequency Tuning */
+SFRX(FRCOSCKFILT0, 0x7072) /* Fast RC Oscillator Calibration Filter Constant Low Byte */
+SFRX(FRCOSCKFILT1, 0x7073) /* Fast RC Oscillator Calibration Filter Constant High Byte */
+SFR16LEX(FRCOSCKFILT, 0x7072) /* Fast RC Oscillator Calibration Filter Constant */
+SFRX(FRCOSCPER0, 0x7078) /* Fast RC Oscillator Period Low Byte */
+SFRX(FRCOSCPER1, 0x7079) /* Fast RC Oscillator Period High Byte */
+SFR16LEX(FRCOSCPER, 0x7078) /* Fast RC Oscillator Period */
+SFRX(FRCOSCREF0, 0x7074) /* Fast RC Oscillator Reference Frequency Low Byte */
+SFRX(FRCOSCREF1, 0x7075) /* Fast RC Oscillator Reference Frequency High Byte */
+SFR16LEX(FRCOSCREF, 0x7074) /* Fast RC Oscillator Reference Frequency */
+SFRX(ANALOGA, 0x7007) /* Port A Analog Mode */
+SFRX(GPIOENABLE, 0x700C) /* GPIO Port Enable */
+SFRX(EXTIRQ, 0x7003) /* External IRQ Configuration */
+SFRX(INTCHGA, 0x7000) /* Port A Interrupt on Change */
+SFRX(INTCHGB, 0x7001) /* Port B Interrupt on Change */
+SFRX(INTCHGC, 0x7002) /* Port C Interrupt on Change */
+SFRX(PALTA, 0x7008) /* Port A Alternate Function */
+SFRX(PALTB, 0x7009) /* Port B Alternate Function */
+SFRX(PALTC, 0x700A) /* Port C Alternate Function */
+SFRX(PALTRADIO, 0x7046) /* Port Radio Alternate Function */
+SFRX(PINCHGA, 0x7004) /* Port A Level Change */
+SFRX(PINCHGB, 0x7005) /* Port B Level Change */
+SFRX(PINCHGC, 0x7006) /* Port C Level Change */
+SFRX(PINSEL, 0x700B) /* Port Input Selection */
+SFRX(LPOSCCONFIG, 0x7060) /* Low Power Oscillator Calibration Configuration */
+SFRX(LPOSCFREQ0, 0x7066) /* Low Power Oscillator Frequency Tuning Low Byte */
+SFRX(LPOSCFREQ1, 0x7067) /* Low Power Oscillator Frequency Tuning High Byte */
+SFR16LEX(LPOSCFREQ, 0x7066) /* Low Power Oscillator Frequency Tuning */
+SFRX(LPOSCKFILT0, 0x7062) /* Low Power Oscillator Calibration Filter Constant Low Byte */
+SFRX(LPOSCKFILT1, 0x7063) /* Low Power Oscillator Calibration Filter Constant High Byte */
+SFR16LEX(LPOSCKFILT, 0x7062) /* Low Power Oscillator Calibration Filter Constant */
+SFRX(LPOSCPER0, 0x7068) /* Low Power Oscillator Period Low Byte */
+SFRX(LPOSCPER1, 0x7069) /* Low Power Oscillator Period High Byte */
+SFR16LEX(LPOSCPER, 0x7068) /* Low Power Oscillator Period */
+SFRX(LPOSCREF0, 0x7064) /* Low Power Oscillator Reference Frequency Low Byte */
+SFRX(LPOSCREF1, 0x7065) /* Low Power Oscillator Reference Frequency High Byte */
+SFR16LEX(LPOSCREF, 0x7064) /* Low Power Oscillator Reference Frequency */
+SFRX(LPXOSCGM, 0x7054) /* Low Power Crystal Oscillator Transconductance */
+SFRX(MISCCTRL, 0x7F01) /* Miscellaneous Control */
+SFRX(OSCCALIB, 0x7053) /* Oscillator Calibration Interrupt / Status */
+SFRX(OSCFORCERUN, 0x7050) /* Oscillator Run Force */
+SFRX(OSCREADY, 0x7052) /* Oscillator Ready Status */
+SFRX(OSCRUN, 0x7051) /* Oscillator Run Status */
+SFRX(RADIOFDATAADDR0, 0x7040) /* Radio FIFO Data Register Address Low Byte */
+SFRX(RADIOFDATAADDR1, 0x7041) /* Radio FIFO Data Register Address High Byte */
+SFR16LEX(RADIOFDATAADDR, 0x7040) /* Radio FIFO Data Register Address */
+SFRX(RADIOFSTATADDR0, 0x7042) /* Radio FIFO Status Register Address Low Byte */
+SFRX(RADIOFSTATADDR1, 0x7043) /* Radio FIFO Status Register Address High Byte */
+SFR16LEX(RADIOFSTATADDR, 0x7042) /* Radio FIFO Status Register Address */
+SFRX(RADIOMUX, 0x7044) /* Radio Multiplexer Control */
+SFRX(SCRATCH0, 0x7084) /* Scratch Register 0 */
+SFRX(SCRATCH1, 0x7085) /* Scratch Register 1 */
+SFRX(SCRATCH2, 0x7086) /* Scratch Register 2 */
+SFRX(SCRATCH3, 0x7087) /* Scratch Register 3 */
+SFRX(SILICONREV, 0x7F00) /* Silicon Revision */
+SFRX(XTALAMPL, 0x7F19) /* Crystal Oscillator Amplitude Control */
+SFRX(XTALOSC, 0x7F18) /* Crystal Oscillator Configuration */
+SFRX(XTALREADY, 0x7F1A) /* Crystal Oscillator Ready Mode */
+
+/* X Address Space aliases of SFR Address Space Registers */
+
+#if defined AX8052F143_H && !defined AX5043_DISABLE_XSFR
+SFR16LEX(XDPTR0, 0x3F82) /* Data Pointer 0 */
+SFR16LEX(XDPTR1, 0x3F84) /* Data Pointer 1 */
+SFRX(XIE, 0x3FA8) /* Interrupt Enable */
+SFRX(XIP, 0x3FB8) /* Interrupt Priority */
+SFRX(XPCON, 0x3F87) /* Power Mode Control */
+SFRX(XADCCH0CONFIG, 0x3FCA) /* ADC Channel 0 Configuration */
+SFRX(XADCCH1CONFIG, 0x3FCB) /* ADC Channel 1 Configuration */
+SFRX(XADCCH2CONFIG, 0x3FD2) /* ADC Channel 2 Configuration */
+SFRX(XADCCH3CONFIG, 0x3FD3) /* ADC Channel 3 Configuration */
+SFRX(XADCCLKSRC, 0x3FD1) /* ADC Clock Source */
+SFRX(XADCCONV, 0x3FC9) /* ADC Conversion Source */
+SFRX(XANALOGCOMP, 0x3FE1) /* Analog Comparators */
+SFRX(XCLKCON, 0x3FC6) /* Clock Control */
+SFRX(XCLKSTAT, 0x3FC7) /* Clock Status */
+SFRX(XCODECONFIG, 0x3F97) /* Code Space Configuration */
+SFRX(XDBGLNKBUF, 0x3FE3) /* Debug Link Buffer */
+SFRX(XDBGLNKSTAT, 0x3FE2) /* Debug Link Status */
+SFRX(XDIRA, 0x3F89) /* Port A Direction */
+SFRX(XDIRB, 0x3F8A) /* Port B Direction */
+SFRX(XDIRC, 0x3F8B) /* Port C Direction */
+SFRX(XDIRR, 0x3F8E) /* Port R Direction */
+SFRX(XPINA, 0x3FC8) /* Port A Input */
+SFRX(XPINB, 0x3FE8) /* Port B Input */
+SFRX(XPINC, 0x3FF8) /* Port C Input */
+SFRX(XPINR, 0x3F8D) /* Port R Input */
+SFRX(XPORTA, 0x3F80) /* Port A Output */
+SFRX(XPORTB, 0x3F88) /* Port B Output */
+SFRX(XPORTC, 0x3F90) /* Port C Output */
+SFRX(XPORTR, 0x3F8C) /* Port R Output */
+SFRX(XIC0CAPT0, 0x3FCE) /* Input Capture 0 Low Byte */
+SFRX(XIC0CAPT1, 0x3FCF) /* Input Capture 0 High Byte */
+SFR16LEX(XIC0CAPT, 0x3FCE) /* Input Capture 0 */
+SFRX(XIC0MODE, 0x3FCC) /* Input Capture 0 Mode */
+SFRX(XIC0STATUS, 0x3FCD) /* Input Capture 0 Status */
+SFRX(XIC1CAPT0, 0x3FD6) /* Input Capture 1 Low Byte */
+SFRX(XIC1CAPT1, 0x3FD7) /* Input Capture 1 High Byte */
+SFR16LEX(XIC1CAPT, 0x3FD6) /* Input Capture 1 */
+SFRX(XIC1MODE, 0x3FD4) /* Input Capture 1 Mode */
+SFRX(XIC1STATUS, 0x3FD5) /* Input Capture 1 Status */
+SFRX(XNVADDR0, 0x3F92) /* Non-Volatile Memory Address Low Byte */
+SFRX(XNVADDR1, 0x3F93) /* Non-Volatile Memory Address High Byte */
+SFR16LEX(XNVADDR, 0x3F92) /* Non-Volatile Memory Address */
+SFRX(XNVDATA0, 0x3F94) /* Non-Volatile Memory Data Low Byte */
+SFRX(XNVDATA1, 0x3F95) /* Non-Volatile Memory Data High Byte */
+SFR16LEX(XNVDATA, 0x3F94) /* Non-Volatile Memory Data */
+SFRX(XNVKEY, 0x3F96) /* Non-Volatile Memory Write/Erase Key */
+SFRX(XNVSTATUS, 0x3F91) /* Non-Volatile Memory Command / Status */
+SFRX(XOC0COMP0, 0x3FBC) /* Output Compare 0 Low Byte */
+SFRX(XOC0COMP1, 0x3FBD) /* Output Compare 0 High Byte */
+SFR16LEX(XOC0COMP, 0x3FBC) /* Output Compare 0 */
+SFRX(XOC0MODE, 0x3FB9) /* Output Compare 0 Mode */
+SFRX(XOC0PIN, 0x3FBA) /* Output Compare 0 Pin Configuration */
+SFRX(XOC0STATUS, 0x3FBB) /* Output Compare 0 Status */
+SFRX(XOC1COMP0, 0x3FC4) /* Output Compare 1 Low Byte */
+SFRX(XOC1COMP1, 0x3FC5) /* Output Compare 1 High Byte */
+SFR16LEX(XOC1COMP, 0x3FC4) /* Output Compare 1 */
+SFRX(XOC1MODE, 0x3FC1) /* Output Compare 1 Mode */
+SFRX(XOC1PIN, 0x3FC2) /* Output Compare 1 Pin Configuration */
+SFRX(XOC1STATUS, 0x3FC3) /* Output Compare 1 Status */
+SFRX(XRADIOACC, 0x3FB1) /* Radio Controller Access Mode */
+SFRX(XRADIOADDR0, 0x3FB3) /* Radio Register Address Low Byte */
+SFRX(XRADIOADDR1, 0x3FB2) /* Radio Register Address High Byte */
+SFRX(XRADIODATA0, 0x3FB7) /* Radio Register Data 0 */
+SFRX(XRADIODATA1, 0x3FB6) /* Radio Register Data 1 */
+SFRX(XRADIODATA2, 0x3FB5) /* Radio Register Data 2 */
+SFRX(XRADIODATA3, 0x3FB4) /* Radio Register Data 3 */
+SFRX(XRADIOSTAT0, 0x3FBE) /* Radio Access Status Low Byte */
+SFRX(XRADIOSTAT1, 0x3FBF) /* Radio Access Status High Byte */
+SFR16LEX(XRADIOSTAT, 0x3FBE) /* Radio Access Status */
+SFRX(XSPCLKSRC, 0x3FDF) /* SPI Clock Source */
+SFRX(XSPMODE, 0x3FDC) /* SPI Mode */
+SFRX(XSPSHREG, 0x3FDE) /* SPI Shift Register */
+SFRX(XSPSTATUS, 0x3FDD) /* SPI Status */
+SFRX(XT0CLKSRC, 0x3F9A) /* Timer 0 Clock Source */
+SFRX(XT0CNT0, 0x3F9C) /* Timer 0 Count Low Byte */
+SFRX(XT0CNT1, 0x3F9D) /* Timer 0 Count High Byte */
+SFR16LEX(XT0CNT, 0x3F9C) /* Timer 0 Count */
+SFRX(XT0MODE, 0x3F99) /* Timer 0 Mode */
+SFRX(XT0PERIOD0, 0x3F9E) /* Timer 0 Period Low Byte */
+SFRX(XT0PERIOD1, 0x3F9F) /* Timer 0 Period High Byte */
+SFR16LEX(XT0PERIOD, 0x3F9E) /* Timer 0 Period */
+SFRX(XT0STATUS, 0x3F9B) /* Timer 0 Status */
+SFRX(XT1CLKSRC, 0x3FA2) /* Timer 1 Clock Source */
+SFRX(XT1CNT0, 0x3FA4) /* Timer 1 Count Low Byte */
+SFRX(XT1CNT1, 0x3FA5) /* Timer 1 Count High Byte */
+SFR16LEX(XT1CNT, 0x3FA4) /* Timer 1 Count */
+SFRX(XT1MODE, 0x3FA1) /* Timer 1 Mode */
+SFRX(XT1PERIOD0, 0x3FA6) /* Timer 1 Period Low Byte */
+SFRX(XT1PERIOD1, 0x3FA7) /* Timer 1 Period High Byte */
+SFR16LEX(XT1PERIOD, 0x3FA6) /* Timer 1 Period */
+SFRX(XT1STATUS, 0x3FA3) /* Timer 1 Status */
+SFRX(XT2CLKSRC, 0x3FAA) /* Timer 2 Clock Source */
+SFRX(XT2CNT0, 0x3FAC) /* Timer 2 Count Low Byte */
+SFRX(XT2CNT1, 0x3FAD) /* Timer 2 Count High Byte */
+SFR16LEX(XT2CNT, 0x3FAC) /* Timer 2 Count */
+SFRX(XT2MODE, 0x3FA9) /* Timer 2 Mode */
+SFRX(XT2PERIOD0, 0x3FAE) /* Timer 2 Period Low Byte */
+SFRX(XT2PERIOD1, 0x3FAF) /* Timer 2 Period High Byte */
+SFR16LEX(XT2PERIOD, 0x3FAE) /* Timer 2 Period */
+SFRX(XT2STATUS, 0x3FAB) /* Timer 2 Status */
+SFRX(XU0CTRL, 0x3FE4) /* UART 0 Control */
+SFRX(XU0MODE, 0x3FE7) /* UART 0 Mode */
+SFRX(XU0SHREG, 0x3FE6) /* UART 0 Shift Register */
+SFRX(XU0STATUS, 0x3FE5) /* UART 0 Status */
+SFRX(XU1CTRL, 0x3FEC) /* UART 1 Control */
+SFRX(XU1MODE, 0x3FEF) /* UART 1 Mode */
+SFRX(XU1SHREG, 0x3FEE) /* UART 1 Shift Register */
+SFRX(XU1STATUS, 0x3FED) /* UART 1 Status */
+SFRX(XWDTCFG, 0x3FDA) /* Watchdog Configuration */
+SFRX(XWDTRESET, 0x3FDB) /* Watchdog Reset */
+SFRX(XWTCFGA, 0x3FF1) /* Wakeup Timer A Configuration */
+SFRX(XWTCFGB, 0x3FF9) /* Wakeup Timer B Configuration */
+SFRX(XWTCNTA0, 0x3FF2) /* Wakeup Counter A Low Byte */
+SFRX(XWTCNTA1, 0x3FF3) /* Wakeup Counter A High Byte */
+SFR16LEX(XWTCNTA, 0x3FF2) /* Wakeup Counter A */
+SFRX(XWTCNTB0, 0x3FFA) /* Wakeup Counter B Low Byte */
+SFRX(XWTCNTB1, 0x3FFB) /* Wakeup Counter B High Byte */
+SFR16LEX(XWTCNTB, 0x3FFA) /* Wakeup Counter B */
+SFRX(XWTCNTR1, 0x3FEB) /* Wakeup Counter High Byte Latch */
+SFRX(XWTEVTA0, 0x3FF4) /* Wakeup Event A Low Byte */
+SFRX(XWTEVTA1, 0x3FF5) /* Wakeup Event A High Byte */
+SFR16LEX(XWTEVTA, 0x3FF4) /* Wakeup Event A */
+SFRX(XWTEVTB0, 0x3FF6) /* Wakeup Event B Low Byte */
+SFRX(XWTEVTB1, 0x3FF7) /* Wakeup Event B High Byte */
+SFR16LEX(XWTEVTB, 0x3FF6) /* Wakeup Event B */
+SFRX(XWTEVTC0, 0x3FFC) /* Wakeup Event C Low Byte */
+SFRX(XWTEVTC1, 0x3FFD) /* Wakeup Event C High Byte */
+SFR16LEX(XWTEVTC, 0x3FFC) /* Wakeup Event C */
+SFRX(XWTEVTD0, 0x3FFE) /* Wakeup Event D Low Byte */
+SFRX(XWTEVTD1, 0x3FFF) /* Wakeup Event D High Byte */
+SFR16LEX(XWTEVTD, 0x3FFE) /* Wakeup Event D */
+SFRX(XWTIRQEN, 0x3FE9) /* Wakeup Timer Interrupt Enable */
+SFRX(XWTSTAT, 0x3FEA) /* Wakeup Timer Status */
+#endif
+
+/* Interrupt Numbers */
+
+#define INT_EXTERNAL0 0
+#define INT_WAKEUPTIMER 1
+#define INT_EXTERNAL1 2
+#define INT_GPIO 3
+#define INT_RADIO 4
+#define INT_CLOCKMGMT 5
+#define INT_POWERMGMT 6
+#define INT_TIMER0 7
+#define INT_TIMER1 8
+#define INT_TIMER2 9
+#define INT_SPI0 10
+#define INT_UART0 11
+#define INT_UART1 12
+#define INT_GPADC 13
+#define INT_DMA 14
+#define INT_OUTPUTCOMP0 15
+#define INT_OUTPUTCOMP1 16
+#define INT_INPUTCAPT0 17
+#define INT_INPUTCAPT1 18
+#define INT_DEBUGLINK 21
+
+/* DMA Sources */
+
+#define DMASOURCE_XRAMTOOTHER 0x00
+#define DMASOURCE_SPITX 0x01
+#define DMASOURCE_UART0TX 0x02
+#define DMASOURCE_UART1TX 0x03
+#define DMASOURCE_TIMER0 0x04
+#define DMASOURCE_TIMER1 0x05
+#define DMASOURCE_TIMER2 0x06
+#define DMASOURCE_RADIOTX 0x07
+#define DMASOURCE_OC0 0x08
+#define DMASOURCE_OC1 0x09
+#define DMASOURCE_OTHERTOXRAM 0x10
+#define DMASOURCE_SPIRX 0x11
+#define DMASOURCE_UART0RX 0x12
+#define DMASOURCE_UART1RX 0x13
+#define DMASOURCE_ADC 0x14
+#define DMASOURCE_RADIORX 0x17
+#define DMASOURCE_IC0 0x18
+#define DMASOURCE_IC1 0x19
+
+/* Silicon Revision Numbers */
+
+#define SILICONREVISION_V1 0x8E
+#define SILICONREVISION_V1C 0x8F
+
+#endif /* AX8052_H */
diff --git a/libs/libmf/source/ax8052f131.h b/libs/libmf/source/ax8052f131.h
new file mode 100644
index 00000000..402af3d7
--- /dev/null
+++ b/libs/libmf/source/ax8052f131.h
@@ -0,0 +1,148 @@
+/*-------------------------------------------------------------------------
+ AX8052F131.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F131_H
+#define AX8052F131_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5031_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5031_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5031_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5031_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5031_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5031_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5031_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5031_FIFOCONTROL2, 0x4037) /* FIFO Control 2 */
+SFRX(AX5031_FIFOCOUNT, 0x4035) /* FIFO Count */
+SFRX(AX5031_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5031_FIFOTHRESH, 0x4036) /* FIFO Threshold */
+SFRX(AX5031_FOURFSK, 0x4050) /* 4-FSK Control */
+SFRX(AX5031_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5031_FREQA0, 0x4023) /* Frequency A 0 */
+SFRX(AX5031_FREQA1, 0x4022) /* Frequency A 1 */
+SFRX(AX5031_FREQA2, 0x4021) /* Frequency A 2 */
+SFRX(AX5031_FREQA3, 0x4020) /* Frequency A 3 */
+SFRX(AX5031_FREQB0, 0x401F) /* Frequency B 0 */
+SFRX(AX5031_FREQB1, 0x401E) /* Frequency B 1 */
+SFRX(AX5031_FREQB2, 0x401D) /* Frequency B 2 */
+SFRX(AX5031_FREQB3, 0x401C) /* Frequency B 3 */
+SFRX(AX5031_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5031_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5031_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5031_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5031_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5031_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5031_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5031_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5031_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5031_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5031_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5031_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5031_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5031_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5031_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5031_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5031_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5031_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5031_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5031_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5031_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5031_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5031_VREG, 0x401B) /* Voltage Regulator */
+SFRX(AX5031_XTALCAP, 0x404F) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5031_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+SFRX(AX5031_XTALOSCCFG, 0x4051) /* Crystal Oscillator Mode Configuration */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5031_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5031_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5031_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5031_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5031_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5031_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5031_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5031_FIFOCONTROL2NB, 0x5037) /* FIFO Control 2, Non-Blocking */
+SFRX(AX5031_FIFOCOUNTNB, 0x5035) /* FIFO Count, Non-Blocking */
+SFRX(AX5031_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5031_FIFOTHRESHNB, 0x5036) /* FIFO Threshold, Non-Blocking */
+SFRX(AX5031_FOURFSKNB, 0x5050) /* 4-FSK Control, Non-Blocking */
+SFRX(AX5031_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5031_FREQA0NB, 0x5023) /* Frequency A 0, Non-Blocking */
+SFRX(AX5031_FREQA1NB, 0x5022) /* Frequency A 1, Non-Blocking */
+SFRX(AX5031_FREQA2NB, 0x5021) /* Frequency A 2, Non-Blocking */
+SFRX(AX5031_FREQA3NB, 0x5020) /* Frequency A 3, Non-Blocking */
+SFRX(AX5031_FREQB0NB, 0x501F) /* Frequency B 0, Non-Blocking */
+SFRX(AX5031_FREQB1NB, 0x501E) /* Frequency B 1, Non-Blocking */
+SFRX(AX5031_FREQB2NB, 0x501D) /* Frequency B 2, Non-Blocking */
+SFRX(AX5031_FREQB3NB, 0x501C) /* Frequency B 3, Non-Blocking */
+SFRX(AX5031_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5031_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5031_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5031_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5031_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5031_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5031_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5031_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5031_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5031_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5031_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5031_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5031_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5031_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5031_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5031_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5031_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5031_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5031_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5031_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5031_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5031_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5031_VREGNB, 0x501B) /* Voltage Regulator, Non-Blocking */
+SFRX(AX5031_XTALCAPNB, 0x504F) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5031_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+SFRX(AX5031_XTALOSCCFGNB, 0x5051) /* Crystal Oscillator Mode Configuration, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5031_MODMISC AX5031_MODULATORMISC
+#define AX5031_TXRATEHI AX5031_TXBITRATEHI
+#define AX5031_TXRATELO AX5031_TXBITRATELO
+#define AX5031_TXRATEMID AX5031_TXBITRATEMID
+
+#define AX5031_MODMISCNB AX5031_MODULATORMISCNB
+#define AX5031_TXRATEHINB AX5031_TXBITRATEHINB
+#define AX5031_TXRATELONB AX5031_TXBITRATELONB
+#define AX5031_TXRATEMIDNB AX5031_TXBITRATEMIDNB
+
+#endif /* AX8052F131_H */
diff --git a/libs/libmf/source/ax8052f142.h b/libs/libmf/source/ax8052f142.h
new file mode 100644
index 00000000..6d0d8f8d
--- /dev/null
+++ b/libs/libmf/source/ax8052f142.h
@@ -0,0 +1,202 @@
+/*-------------------------------------------------------------------------
+ AX8052F142.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F142_H
+#define AX8052F142_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5042_ADCMISC, 0x4038) /* ADC Miscellaneous Control */
+SFRX(AX5042_AGCATTACK, 0x403A) /* AGC Attack Speed */
+SFRX(AX5042_AGCCOUNTER, 0x403C) /* AGC Counter */
+SFRX(AX5042_AGCDECAY, 0x403B) /* AGC Decay Speed */
+SFRX(AX5042_AGCTARGET, 0x4039) /* AGC Target Value */
+SFRX(AX5042_AMPLITUDEGAIN, 0x4047) /* Amplitude Estimator Bandwidth */
+SFRX(AX5042_APEOVERRIDE, 0x4070) /* APE Override */
+SFRX(AX5042_CICDECHI, 0x403E) /* Decimation Factor High */
+SFRX(AX5042_CICDECLO, 0x403F) /* Decimation Factor Low */
+SFRX(AX5042_CICSHIFT, 0x403D) /* Decimation Filter Attenuation */
+SFRX(AX5042_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5042_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5042_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5042_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5042_DATARATEHI, 0x4040) /* Datarate High */
+SFRX(AX5042_DATARATELO, 0x4041) /* Datarate Low */
+SFRX(AX5042_DSPMODE, 0x4009) /* DSP Mode Interface Control */
+SFRX(AX5042_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5042_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5042_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5042_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5042_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5042_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5042_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5042_FREQ0, 0x4023) /* Frequency 0 */
+SFRX(AX5042_FREQ1, 0x4022) /* Frequency 1 */
+SFRX(AX5042_FREQ2, 0x4021) /* Frequency 2 */
+SFRX(AX5042_FREQ3, 0x4020) /* Frequency 3 */
+SFRX(AX5042_FREQUENCYGAIN, 0x4045) /* Frequency Estimator Bandwidth */
+SFRX(AX5042_FREQUENCYGAIN2, 0x4046) /* Frequency Estimator Bandwidth 2 */
+SFRX(AX5042_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5042_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5042_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5042_IFFREQHI, 0x4028) /* IF Frequency Low */
+SFRX(AX5042_IFFREQLO, 0x4029) /* IF Frequency High */
+SFRX(AX5042_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5042_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5042_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5042_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5042_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5042_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5042_PHASEGAIN, 0x4044) /* Phase Estimator Bandwidth */
+SFRX(AX5042_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5042_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5042_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5042_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5042_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5042_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5042_PLLRNGMISC, 0x4074) /* PLL Autoranging Miscellaneous */
+SFRX(AX5042_PLLVCOI, 0x4072) /* PLL VCO Current */
+SFRX(AX5042_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5042_REF, 0x407C) /* Reference */
+SFRX(AX5042_RXMISC, 0x407D) /* Receiver Miscellaneous Control */
+SFRX(AX5042_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5042_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5042_TIMINGGAINHI, 0x4042) /* Timing Estimator Bandwidth High */
+SFRX(AX5042_TIMINGGAINLO, 0x4043) /* Timing Estimator Bandwidth Low */
+SFRX(AX5042_TRKAMPLITUDEHI, 0x4048) /* Amplitude Tracking High */
+SFRX(AX5042_TRKAMPLITUDELO, 0x4049) /* Amplitude Tracking Low */
+SFRX(AX5042_TRKFREQHI, 0x404C) /* Frequency Tracking High */
+SFRX(AX5042_TRKFREQLO, 0x404D) /* Frequency Tracking Low */
+SFRX(AX5042_TRKPHASEHI, 0x404A) /* Phase Tracking High */
+SFRX(AX5042_TRKPHASELO, 0x404B) /* Phase Tracking Low */
+SFRX(AX5042_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5042_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5042_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5042_TXDSPMODE, 0x400A) /* Transmit DSP Mode */
+SFRX(AX5042_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5042_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5042_ADCMISCNB, 0x5038) /* ADC Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_AGCATTACKNB, 0x503A) /* AGC Attack Speed, Non-Blocking */
+SFRX(AX5042_AGCCOUNTERNB, 0x503C) /* AGC Counter, Non-Blocking */
+SFRX(AX5042_AGCDECAYNB, 0x503B) /* AGC Decay Speed, Non-Blocking */
+SFRX(AX5042_AGCTARGETNB, 0x5039) /* AGC Target Value, Non-Blocking */
+SFRX(AX5042_AMPLITUDEGAINNB, 0x5047) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_APEOVERRIDENB, 0x5070) /* APE Override, Non-Blocking */
+SFRX(AX5042_CICDECHINB, 0x503E) /* Decimation Factor High, Non-Blocking */
+SFRX(AX5042_CICDECLONB, 0x503F) /* Decimation Factor Low, Non-Blocking */
+SFRX(AX5042_CICSHIFTNB, 0x503D) /* Decimation Filter Attenuation, Non-Blocking */
+SFRX(AX5042_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5042_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5042_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5042_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5042_DATARATEHINB, 0x5040) /* Datarate High, Non-Blocking */
+SFRX(AX5042_DATARATELONB, 0x5041) /* Datarate Low, Non-Blocking */
+SFRX(AX5042_DSPMODENB, 0x5009) /* DSP Mode Interface Control, Non-Blocking */
+SFRX(AX5042_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5042_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5042_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5042_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5042_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5042_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5042_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5042_FREQ0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5042_FREQ1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5042_FREQ2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5042_FREQ3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5042_FREQUENCYGAINNB, 0x5045) /* Frequency Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_FREQUENCYGAIN2NB, 0x5046) /* Frequency Estimator Bandwidth 2, Non-Blocking */
+SFRX(AX5042_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5042_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5042_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5042_IFFREQHINB, 0x5028) /* IF Frequency Low, Non-Blocking */
+SFRX(AX5042_IFFREQLONB, 0x5029) /* IF Frequency High, Non-Blocking */
+SFRX(AX5042_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5042_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5042_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5042_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5042_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5042_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_PHASEGAINNB, 0x5044) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5042_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5042_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5042_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5042_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5042_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5042_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5042_PLLRNGMISCNB, 0x5074) /* PLL Autoranging Miscellaneous, Non-Blocking */
+SFRX(AX5042_PLLVCOINB, 0x5072) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5042_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5042_REFNB, 0x507C) /* Reference, Non-Blocking */
+SFRX(AX5042_RXMISCNB, 0x507D) /* Receiver Miscellaneous Control, Non-Blocking */
+SFRX(AX5042_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5042_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5042_TIMINGGAINHINB, 0x5042) /* Timing Estimator Bandwidth High, Non-Blocking */
+SFRX(AX5042_TIMINGGAINLONB, 0x5043) /* Timing Estimator Bandwidth Low, Non-Blocking */
+SFRX(AX5042_TRKAMPLITUDEHINB, 0x5048) /* Amplitude Tracking High, Non-Blocking */
+SFRX(AX5042_TRKAMPLITUDELONB, 0x5049) /* Amplitude Tracking Low, Non-Blocking */
+SFRX(AX5042_TRKFREQHINB, 0x504C) /* Frequency Tracking High, Non-Blocking */
+SFRX(AX5042_TRKFREQLONB, 0x504D) /* Frequency Tracking Low, Non-Blocking */
+SFRX(AX5042_TRKPHASEHINB, 0x504A) /* Phase Tracking High, Non-Blocking */
+SFRX(AX5042_TRKPHASELONB, 0x504B) /* Phase Tracking Low, Non-Blocking */
+SFRX(AX5042_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5042_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5042_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5042_TXDSPMODENB, 0x500A) /* Transmit DSP Mode, Non-Blocking */
+SFRX(AX5042_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5042_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5042_AMPLGAIN AX5042_AMPLITUDEGAIN
+#define AX5042_FREQGAIN AX5042_FREQUENCYGAIN
+#define AX5042_FREQGAIN2 AX5042_FREQUENCYGAIN2
+#define AX5042_MODMISC AX5042_MODULATORMISC
+#define AX5042_TMGGAINHI AX5042_TIMINGGAINHI
+#define AX5042_TMGGAINLO AX5042_TIMINGGAINLO
+#define AX5042_TXRATEHI AX5042_TXBITRATEHI
+#define AX5042_TXRATELO AX5042_TXBITRATELO
+#define AX5042_TXRATEMID AX5042_TXBITRATEMID
+
+#define AX5042_AMPLGAINNB AX5042_AMPLITUDEGAINNB
+#define AX5042_FREQGAINNB AX5042_FREQUENCYGAINNB
+#define AX5042_FREQGAIN2NB AX5042_FREQUENCYGAIN2NB
+#define AX5042_MODMISCNB AX5042_MODULATORMISCNB
+#define AX5042_TMGGAINHINB AX5042_TIMINGGAINHINB
+#define AX5042_TMGGAINLONB AX5042_TIMINGGAINLONB
+#define AX5042_TXRATEHINB AX5042_TXBITRATEHINB
+#define AX5042_TXRATELONB AX5042_TXBITRATELONB
+#define AX5042_TXRATEMIDNB AX5042_TXBITRATEMIDNB
+
+#endif /* AX8052F142_H */
diff --git a/libs/libmf/source/ax8052f143.h b/libs/libmf/source/ax8052f143.h
new file mode 100644
index 00000000..9f46cd2f
--- /dev/null
+++ b/libs/libmf/source/ax8052f143.h
@@ -0,0 +1,885 @@
+/*-------------------------------------------------------------------------
+ ax8052f143.h - Register Declarations for the Axsem Integrated Radio
+
+ Copyright (C) 2010, 2011, 2012, 2014, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+#ifndef AX8052F143_H
+#define AX8052F143_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5043_AFSKCTRL, 0x4114) /* AFSK Control */
+SFRX(AX5043_AFSKMARK0, 0x4113) /* AFSK Mark (1) Frequency 0 */
+SFRX(AX5043_AFSKMARK1, 0x4112) /* AFSK Mark (1) Frequency 1 */
+SFRX(AX5043_AFSKSPACE0, 0x4111) /* AFSK Space (0) Frequency 0 */
+SFRX(AX5043_AFSKSPACE1, 0x4110) /* AFSK Space (0) Frequency 1 */
+SFRX(AX5043_AGCCOUNTER, 0x4043) /* AGC Counter */
+SFRX(AX5043_AMPLFILTER, 0x4115) /* Amplitude Filter */
+SFRX(AX5043_BBOFFSCAP, 0x4189) /* Baseband Offset Compensation Capacitors */
+SFRX(AX5043_BBTUNE, 0x4188) /* Baseband Tuning */
+SFRX(AX5043_BGNDRSSI, 0x4041) /* Background RSSI */
+SFRX(AX5043_BGNDRSSIGAIN, 0x422E) /* Background RSSI Averaging Time Constant */
+SFRX(AX5043_BGNDRSSITHR, 0x422F) /* Background RSSI Relative Threshold */
+SFRX(AX5043_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5043_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5043_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5043_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5043_DACCONFIG, 0x4332) /* DAC Configuration */
+SFRX(AX5043_DACVALUE0, 0x4331) /* DAC Value 0 */
+SFRX(AX5043_DACVALUE1, 0x4330) /* DAC Value 1 */
+SFRX(AX5043_DECIMATION, 0x4102) /* Decimation Factor */
+SFRX(AX5043_DIVERSITY, 0x4042) /* Antenna Diversity Configuration */
+SFRX(AX5043_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5043_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5043_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5043_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5043_FIFOCOUNT0, 0x402B) /* Number of Words currently in FIFO 0 */
+SFRX(AX5043_FIFOCOUNT1, 0x402A) /* Number of Words currently in FIFO 1 */
+SFRX(AX5043_FIFODATA, 0x4029) /* FIFO Data */
+SFRX(AX5043_FIFOFREE0, 0x402D) /* Number of Words that can be written to FIFO 0 */
+SFRX(AX5043_FIFOFREE1, 0x402C) /* Number of Words that can be written to FIFO 1 */
+SFRX(AX5043_FIFOSTAT, 0x4028) /* FIFO Control */
+SFRX(AX5043_FIFOTHRESH0, 0x402F) /* FIFO Threshold 0 */
+SFRX(AX5043_FIFOTHRESH1, 0x402E) /* FIFO Threshold 1 */
+SFRX(AX5043_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5043_FREQA0, 0x4037) /* Frequency A 0 */
+SFRX(AX5043_FREQA1, 0x4036) /* Frequency A 1 */
+SFRX(AX5043_FREQA2, 0x4035) /* Frequency A 2 */
+SFRX(AX5043_FREQA3, 0x4034) /* Frequency A 3 */
+SFRX(AX5043_FREQB0, 0x403F) /* Frequency B 0 */
+SFRX(AX5043_FREQB1, 0x403E) /* Frequency B 1 */
+SFRX(AX5043_FREQB2, 0x403D) /* Frequency B 2 */
+SFRX(AX5043_FREQB3, 0x403C) /* Frequency B 3 */
+SFRX(AX5043_FSKDEV0, 0x4163) /* FSK Deviation 0 */
+SFRX(AX5043_FSKDEV1, 0x4162) /* FSK Deviation 1 */
+SFRX(AX5043_FSKDEV2, 0x4161) /* FSK Deviation 2 */
+SFRX(AX5043_FSKDMAX0, 0x410D) /* Four FSK Rx Maximum Deviation 0 */
+SFRX(AX5043_FSKDMAX1, 0x410C) /* Four FSK Rx Maximum Deviation 1 */
+SFRX(AX5043_FSKDMIN0, 0x410F) /* Four FSK Rx Minimum Deviation 0 */
+SFRX(AX5043_FSKDMIN1, 0x410E) /* Four FSK Rx Minimum Deviation 1 */
+SFRX(AX5043_GPADC13VALUE0, 0x4309) /* GPADC13 Value 0 */
+SFRX(AX5043_GPADC13VALUE1, 0x4308) /* GPADC13 Value 1 */
+SFRX(AX5043_GPADCCTRL, 0x4300) /* General Purpose ADC Control */
+SFRX(AX5043_GPADCPERIOD, 0x4301) /* GPADC Sampling Period */
+SFRX(AX5043_IFFREQ0, 0x4101) /* 2nd LO / IF Frequency 0 */
+SFRX(AX5043_IFFREQ1, 0x4100) /* 2nd LO / IF Frequency 1 */
+SFRX(AX5043_IRQINVERSION0, 0x400B) /* IRQ Inversion 0 */
+SFRX(AX5043_IRQINVERSION1, 0x400A) /* IRQ Inversion 1 */
+SFRX(AX5043_IRQMASK0, 0x4007) /* IRQ Mask 0 */
+SFRX(AX5043_IRQMASK1, 0x4006) /* IRQ Mask 1 */
+SFRX(AX5043_IRQREQUEST0, 0x400D) /* IRQ Request 0 */
+SFRX(AX5043_IRQREQUEST1, 0x400C) /* IRQ Request 1 */
+SFRX(AX5043_LPOSCCONFIG, 0x4310) /* Low Power Oscillator Calibration Configuration */
+SFRX(AX5043_LPOSCFREQ0, 0x4317) /* Low Power Oscillator Frequency Tuning Low Byte */
+SFRX(AX5043_LPOSCFREQ1, 0x4316) /* Low Power Oscillator Frequency Tuning High Byte */
+SFRX(AX5043_LPOSCKFILT0, 0x4313) /* Low Power Oscillator Calibration Filter Constant Low Byte */
+SFRX(AX5043_LPOSCKFILT1, 0x4312) /* Low Power Oscillator Calibration Filter Constant High Byte */
+SFRX(AX5043_LPOSCPER0, 0x4319) /* Low Power Oscillator Period Low Byte */
+SFRX(AX5043_LPOSCPER1, 0x4318) /* Low Power Oscillator Period High Byte */
+SFRX(AX5043_LPOSCREF0, 0x4315) /* Low Power Oscillator Reference Frequency Low Byte */
+SFRX(AX5043_LPOSCREF1, 0x4314) /* Low Power Oscillator Reference Frequency High Byte */
+SFRX(AX5043_LPOSCSTATUS, 0x4311) /* Low Power Oscillator Calibration Status */
+SFRX(AX5043_MATCH0LEN, 0x4214) /* Pattern Match Unit 0, Pattern Length */
+SFRX(AX5043_MATCH0MAX, 0x4216) /* Pattern Match Unit 0, Maximum Match */
+SFRX(AX5043_MATCH0MIN, 0x4215) /* Pattern Match Unit 0, Minimum Match */
+SFRX(AX5043_MATCH0PAT0, 0x4213) /* Pattern Match Unit 0, Pattern 0 */
+SFRX(AX5043_MATCH0PAT1, 0x4212) /* Pattern Match Unit 0, Pattern 1 */
+SFRX(AX5043_MATCH0PAT2, 0x4211) /* Pattern Match Unit 0, Pattern 2 */
+SFRX(AX5043_MATCH0PAT3, 0x4210) /* Pattern Match Unit 0, Pattern 3 */
+SFRX(AX5043_MATCH1LEN, 0x421C) /* Pattern Match Unit 1, Pattern Length */
+SFRX(AX5043_MATCH1MAX, 0x421E) /* Pattern Match Unit 1, Maximum Match */
+SFRX(AX5043_MATCH1MIN, 0x421D) /* Pattern Match Unit 1, Minimum Match */
+SFRX(AX5043_MATCH1PAT0, 0x4219) /* Pattern Match Unit 1, Pattern 0 */
+SFRX(AX5043_MATCH1PAT1, 0x4218) /* Pattern Match Unit 1, Pattern 1 */
+SFRX(AX5043_MAXDROFFSET0, 0x4108) /* Maximum Receiver Datarate Offset 0 */
+SFRX(AX5043_MAXDROFFSET1, 0x4107) /* Maximum Receiver Datarate Offset 1 */
+SFRX(AX5043_MAXDROFFSET2, 0x4106) /* Maximum Receiver Datarate Offset 2 */
+SFRX(AX5043_MAXRFOFFSET0, 0x410B) /* Maximum Receiver RF Offset 0 */
+SFRX(AX5043_MAXRFOFFSET1, 0x410A) /* Maximum Receiver RF Offset 1 */
+SFRX(AX5043_MAXRFOFFSET2, 0x4109) /* Maximum Receiver RF Offset 2 */
+SFRX(AX5043_MODCFGA, 0x4164) /* Modulator Configuration A */
+SFRX(AX5043_MODCFGF, 0x4160) /* Modulator Configuration F */
+SFRX(AX5043_MODCFGP, 0x4F5F) /* Modulator Configuration P */
+SFRX(AX5043_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5043_PINFUNCANTSEL, 0x4025) /* Pin Function ANTSEL */
+SFRX(AX5043_PINFUNCDATA, 0x4023) /* Pin Function DATA */
+SFRX(AX5043_PINFUNCDCLK, 0x4022) /* Pin Function DCLK */
+SFRX(AX5043_PINFUNCIRQ, 0x4024) /* Pin Function IRQ */
+SFRX(AX5043_PINFUNCPWRAMP, 0x4026) /* Pin Function PWRAMP */
+SFRX(AX5043_PINFUNCSYSCLK, 0x4021) /* Pin Function SYSCLK */
+SFRX(AX5043_PINSTATE, 0x4020) /* Pin State */
+SFRX(AX5043_PKTACCEPTFLAGS, 0x4233) /* Packet Controller Accept Flags */
+SFRX(AX5043_PKTCHUNKSIZE, 0x4230) /* Packet Chunk Size */
+SFRX(AX5043_PKTMISCFLAGS, 0x4231) /* Packet Controller Miscellaneous Flags */
+SFRX(AX5043_PKTSTOREFLAGS, 0x4232) /* Packet Controller Store Flags */
+SFRX(AX5043_PLLCPI, 0x4031) /* PLL Charge Pump Current */
+SFRX(AX5043_PLLCPIBOOST, 0x4039) /* PLL Charge Pump Current (Boosted) */
+SFRX(AX5043_PLLLOCKDET, 0x4182) /* PLL Lock Detect Delay */
+SFRX(AX5043_PLLLOOP, 0x4030) /* PLL Loop Filter Settings */
+SFRX(AX5043_PLLLOOPBOOST, 0x4038) /* PLL Loop Filter Settings (Boosted) */
+SFRX(AX5043_PLLRANGINGA, 0x4033) /* PLL Autoranging A */
+SFRX(AX5043_PLLRANGINGB, 0x403B) /* PLL Autoranging B */
+SFRX(AX5043_PLLRNGCLK, 0x4183) /* PLL Autoranging Clock */
+SFRX(AX5043_PLLVCODIV, 0x4032) /* PLL Divider Settings */
+SFRX(AX5043_PLLVCOI, 0x4180) /* PLL VCO Current */
+SFRX(AX5043_PLLVCOIR, 0x4181) /* PLL VCO Current Readback */
+SFRX(AX5043_POWCTRL1, 0x4F08) /* Power Control 1 */
+SFRX(AX5043_POWIRQMASK, 0x4005) /* Power Management Interrupt Mask */
+SFRX(AX5043_POWSTAT, 0x4003) /* Power Management Status */
+SFRX(AX5043_POWSTICKYSTAT, 0x4004) /* Power Management Sticky Status */
+SFRX(AX5043_PWRAMP, 0x4027) /* PWRAMP Control */
+SFRX(AX5043_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5043_RADIOEVENTMASK0, 0x4009) /* Radio Event Mask 0 */
+SFRX(AX5043_RADIOEVENTMASK1, 0x4008) /* Radio Event Mask 1 */
+SFRX(AX5043_RADIOEVENTREQ0, 0x400F) /* Radio Event Request 0 */
+SFRX(AX5043_RADIOEVENTREQ1, 0x400E) /* Radio Event Request 1 */
+SFRX(AX5043_RADIOSTATE, 0x401C) /* Radio Controller State */
+SFRX(AX5043_REF, 0x4F0D) /* Reference */
+SFRX(AX5043_RSSI, 0x4040) /* Received Signal Strength Indicator */
+SFRX(AX5043_RSSIABSTHR, 0x422D) /* RSSI Absolute Threshold */
+SFRX(AX5043_RSSIREFERENCE, 0x422C) /* RSSI Offset */
+SFRX(AX5043_RXDATARATE0, 0x4105) /* Receiver Datarate 0 */
+SFRX(AX5043_RXDATARATE1, 0x4104) /* Receiver Datarate 1 */
+SFRX(AX5043_RXDATARATE2, 0x4103) /* Receiver Datarate 2 */
+SFRX(AX5043_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5043_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5043_TIMER0, 0x405B) /* 1MHz Timer 0 */
+SFRX(AX5043_TIMER1, 0x405A) /* 1MHz Timer 1 */
+SFRX(AX5043_TIMER2, 0x4059) /* 1MHz Timer 2 */
+SFRX(AX5043_TMGRXAGC, 0x4227) /* Receiver AGC Settling Time */
+SFRX(AX5043_TMGRXBOOST, 0x4223) /* Receive PLL Boost Time */
+SFRX(AX5043_TMGRXCOARSEAGC, 0x4226) /* Receive Coarse AGC Time */
+SFRX(AX5043_TMGRXOFFSACQ, 0x4225) /* Receive Baseband DC Offset Acquisition Time */
+SFRX(AX5043_TMGRXPREAMBLE1, 0x4229) /* Receiver Preamble 1 Timeout */
+SFRX(AX5043_TMGRXPREAMBLE2, 0x422A) /* Receiver Preamble 2 Timeout */
+SFRX(AX5043_TMGRXPREAMBLE3, 0x422B) /* Receiver Preamble 3 Timeout */
+SFRX(AX5043_TMGRXRSSI, 0x4228) /* Receiver RSSI Settling Time */
+SFRX(AX5043_TMGRXSETTLE, 0x4224) /* Receive PLL (post Boost) Settling Time */
+SFRX(AX5043_TMGTXBOOST, 0x4220) /* Transmit PLL Boost Time */
+SFRX(AX5043_TMGTXSETTLE, 0x4221) /* Transmit PLL (post Boost) Settling Time */
+SFRX(AX5043_TRKAFSKDEMOD0, 0x4055) /* AFSK Demodulator Tracking 0 */
+SFRX(AX5043_TRKAFSKDEMOD1, 0x4054) /* AFSK Demodulator Tracking 1 */
+SFRX(AX5043_TRKAMPLITUDE0, 0x4049) /* Amplitude Tracking 0 */
+SFRX(AX5043_TRKAMPLITUDE1, 0x4048) /* Amplitude Tracking 1 */
+SFRX(AX5043_TRKDATARATE0, 0x4047) /* Datarate Tracking 0 */
+SFRX(AX5043_TRKDATARATE1, 0x4046) /* Datarate Tracking 1 */
+SFRX(AX5043_TRKDATARATE2, 0x4045) /* Datarate Tracking 2 */
+SFRX(AX5043_TRKFREQ0, 0x4051) /* Frequency Tracking 0 */
+SFRX(AX5043_TRKFREQ1, 0x4050) /* Frequency Tracking 1 */
+SFRX(AX5043_TRKFSKDEMOD0, 0x4053) /* FSK Demodulator Tracking 0 */
+SFRX(AX5043_TRKFSKDEMOD1, 0x4052) /* FSK Demodulator Tracking 1 */
+SFRX(AX5043_TRKPHASE0, 0x404B) /* Phase Tracking 0 */
+SFRX(AX5043_TRKPHASE1, 0x404A) /* Phase Tracking 1 */
+SFRX(AX5043_TRKRFFREQ0, 0x404F) /* RF Frequency Tracking 0 */
+SFRX(AX5043_TRKRFFREQ1, 0x404E) /* RF Frequency Tracking 1 */
+SFRX(AX5043_TRKRFFREQ2, 0x404D) /* RF Frequency Tracking 2 */
+SFRX(AX5043_TXPWRCOEFFA0, 0x4169) /* Transmitter Predistortion Coefficient A 0 */
+SFRX(AX5043_TXPWRCOEFFA1, 0x4168) /* Transmitter Predistortion Coefficient A 1 */
+SFRX(AX5043_TXPWRCOEFFB0, 0x416B) /* Transmitter Predistortion Coefficient B 0 */
+SFRX(AX5043_TXPWRCOEFFB1, 0x416A) /* Transmitter Predistortion Coefficient B 1 */
+SFRX(AX5043_TXPWRCOEFFC0, 0x416D) /* Transmitter Predistortion Coefficient C 0 */
+SFRX(AX5043_TXPWRCOEFFC1, 0x416C) /* Transmitter Predistortion Coefficient C 1 */
+SFRX(AX5043_TXPWRCOEFFD0, 0x416F) /* Transmitter Predistortion Coefficient D 0 */
+SFRX(AX5043_TXPWRCOEFFD1, 0x416E) /* Transmitter Predistortion Coefficient D 1 */
+SFRX(AX5043_TXPWRCOEFFE0, 0x4171) /* Transmitter Predistortion Coefficient E 0 */
+SFRX(AX5043_TXPWRCOEFFE1, 0x4170) /* Transmitter Predistortion Coefficient E 1 */
+SFRX(AX5043_TXRATE0, 0x4167) /* Transmitter Bitrate 0 */
+SFRX(AX5043_TXRATE1, 0x4166) /* Transmitter Bitrate 1 */
+SFRX(AX5043_TXRATE2, 0x4165) /* Transmitter Bitrate 2 */
+SFRX(AX5043_WAKEUP0, 0x406B) /* Wakeup Time 0 */
+SFRX(AX5043_WAKEUP1, 0x406A) /* Wakeup Time 1 */
+SFRX(AX5043_WAKEUPFREQ0, 0x406D) /* Wakeup Frequency 0 */
+SFRX(AX5043_WAKEUPFREQ1, 0x406C) /* Wakeup Frequency 1 */
+SFRX(AX5043_WAKEUPTIMER0, 0x4069) /* Wakeup Timer 0 */
+SFRX(AX5043_WAKEUPTIMER1, 0x4068) /* Wakeup Timer 1 */
+SFRX(AX5043_WAKEUPXOEARLY, 0x406E) /* Wakeup Crystal Oscillator Early */
+SFRX(AX5043_XTALAMPL, 0x4F11) /* Crystal Oscillator Amplitude Control */
+SFRX(AX5043_XTALCAP, 0x4184) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5043_XTALOSC, 0x4F10) /* Crystal Oscillator Control */
+SFRX(AX5043_XTALSTATUS, 0x401D) /* Crystal Oscillator Status */
+
+SFRX(AX5043_0xF00, 0x4F00)
+SFRX(AX5043_0xF0C, 0x4F0C)
+SFRX(AX5043_0xF18, 0x4F18)
+SFRX(AX5043_0xF1C, 0x4F1C)
+SFRX(AX5043_0xF21, 0x4F21)
+SFRX(AX5043_0xF22, 0x4F22)
+SFRX(AX5043_0xF23, 0x4F23)
+SFRX(AX5043_0xF26, 0x4F26)
+SFRX(AX5043_0xF30, 0x4F30)
+SFRX(AX5043_0xF31, 0x4F31)
+SFRX(AX5043_0xF32, 0x4F32)
+SFRX(AX5043_0xF33, 0x4F33)
+SFRX(AX5043_0xF34, 0x4F34)
+SFRX(AX5043_0xF35, 0x4F35)
+SFRX(AX5043_0xF44, 0x4F44)
+
+#if defined AX5043V1
+SFRX(AX5043_AGCGAIN0_V1, 0x4120) /* AGC Speed */
+SFRX(AX5043_AGCGAIN1_V1, 0x412E) /* AGC Speed */
+SFRX(AX5043_AGCGAIN2_V1, 0x413C) /* AGC Speed */
+SFRX(AX5043_AGCGAIN3_V1, 0x414A) /* AGC Speed */
+SFRX(AX5043_AGCTARGET0_V1, 0x4121) /* AGC Target */
+SFRX(AX5043_AGCTARGET1_V1, 0x412F) /* AGC Target */
+SFRX(AX5043_AGCTARGET2_V1, 0x413D) /* AGC Target */
+SFRX(AX5043_AGCTARGET3_V1, 0x414B) /* AGC Target */
+SFRX(AX5043_AMPLITUDEGAIN0_V1, 0x4129) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN1_V1, 0x4137) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN2_V1, 0x4145) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN3_V1, 0x4153) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_BBOFFSRES0_V1, 0x412D) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES1_V1, 0x413B) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES2_V1, 0x4149) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES3_V1, 0x4157) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_DRGAIN0_V1, 0x4123) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN1_V1, 0x4131) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN2_V1, 0x413F) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN3_V1, 0x414D) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_FOURFSK0_V1, 0x412C) /* Four FSK Control */
+SFRX(AX5043_FOURFSK1_V1, 0x413A) /* Four FSK Control */
+SFRX(AX5043_FOURFSK2_V1, 0x4148) /* Four FSK Control */
+SFRX(AX5043_FOURFSK3_V1, 0x4156) /* Four FSK Control */
+SFRX(AX5043_FREQDEV00_V1, 0x412B) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV01_V1, 0x4139) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV02_V1, 0x4147) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV03_V1, 0x4155) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV10_V1, 0x412A) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV11_V1, 0x4138) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV12_V1, 0x4146) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV13_V1, 0x4154) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQUENCYGAINA0_V1, 0x4125) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA1_V1, 0x4133) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA2_V1, 0x4141) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA3_V1, 0x414F) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINB0_V1, 0x4126) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB1_V1, 0x4134) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB2_V1, 0x4142) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB3_V1, 0x4150) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINC0_V1, 0x4127) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC1_V1, 0x4135) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC2_V1, 0x4143) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC3_V1, 0x4151) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAIND0_V1, 0x4128) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND1_V1, 0x4136) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND2_V1, 0x4144) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND3_V1, 0x4152) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_PHASEGAIN0_V1, 0x4124) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN1_V1, 0x4132) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN2_V1, 0x4140) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN3_V1, 0x414E) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PKTADDR0_V1, 0x4203) /* Packet Address 0 */
+SFRX(AX5043_PKTADDR1_V1, 0x4202) /* Packet Address 1 */
+SFRX(AX5043_PKTADDRCFG_V1, 0x4201) /* Packet Address Config */
+SFRX(AX5043_PKTADDRMASK0_V1, 0x4205) /* Packet Address Mask 0 */
+SFRX(AX5043_PKTADDRMASK1_V1, 0x4204) /* Packet Address Mask 1 */
+SFRX(AX5043_PKTLENCFG_V1, 0x4206) /* Packet Length Configuration */
+SFRX(AX5043_PKTLENOFFSET_V1, 0x4207) /* Packet Length Offset */
+SFRX(AX5043_PKTMAXLEN_V1, 0x4208) /* Packet Maximum Length */
+SFRX(AX5043_RXPARAMCURSET_V1, 0x4117) /* Receiver Parameter Current Set */
+SFRX(AX5043_RXPARAMSETS_V1, 0x4116) /* Receiver Parameter Set Indirection */
+SFRX(AX5043_TIMEGAIN0_V1, 0x4122) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN1_V1, 0x4130) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN2_V1, 0x413E) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN3_V1, 0x414C) /* Time Estimator Bandwidth */
+
+#define AX5043_AGCGAIN0 AX5043_AGCGAIN0_V1
+#define AX5043_AGCGAIN1 AX5043_AGCGAIN1_V1
+#define AX5043_AGCGAIN2 AX5043_AGCGAIN2_V1
+#define AX5043_AGCGAIN3 AX5043_AGCGAIN3_V1
+#define AX5043_AGCTARGET0 AX5043_AGCTARGET0_V1
+#define AX5043_AGCTARGET1 AX5043_AGCTARGET1_V1
+#define AX5043_AGCTARGET2 AX5043_AGCTARGET2_V1
+#define AX5043_AGCTARGET3 AX5043_AGCTARGET3_V1
+#define AX5043_AMPLITUDEGAIN0 AX5043_AMPLITUDEGAIN0_V1
+#define AX5043_AMPLITUDEGAIN1 AX5043_AMPLITUDEGAIN1_V1
+#define AX5043_AMPLITUDEGAIN2 AX5043_AMPLITUDEGAIN2_V1
+#define AX5043_AMPLITUDEGAIN3 AX5043_AMPLITUDEGAIN3_V1
+#define AX5043_BBOFFSRES0 AX5043_BBOFFSRES0_V1
+#define AX5043_BBOFFSRES1 AX5043_BBOFFSRES1_V1
+#define AX5043_BBOFFSRES2 AX5043_BBOFFSRES2_V1
+#define AX5043_BBOFFSRES3 AX5043_BBOFFSRES3_V1
+#define AX5043_DRGAIN0 AX5043_DRGAIN0_V1
+#define AX5043_DRGAIN1 AX5043_DRGAIN1_V1
+#define AX5043_DRGAIN2 AX5043_DRGAIN2_V1
+#define AX5043_DRGAIN3 AX5043_DRGAIN3_V1
+#define AX5043_FOURFSK0 AX5043_FOURFSK0_V1
+#define AX5043_FOURFSK1 AX5043_FOURFSK1_V1
+#define AX5043_FOURFSK2 AX5043_FOURFSK2_V1
+#define AX5043_FOURFSK3 AX5043_FOURFSK3_V1
+#define AX5043_FREQDEV00 AX5043_FREQDEV00_V1
+#define AX5043_FREQDEV01 AX5043_FREQDEV01_V1
+#define AX5043_FREQDEV02 AX5043_FREQDEV02_V1
+#define AX5043_FREQDEV03 AX5043_FREQDEV03_V1
+#define AX5043_FREQDEV10 AX5043_FREQDEV10_V1
+#define AX5043_FREQDEV11 AX5043_FREQDEV11_V1
+#define AX5043_FREQDEV12 AX5043_FREQDEV12_V1
+#define AX5043_FREQDEV13 AX5043_FREQDEV13_V1
+#define AX5043_FREQUENCYGAINA0 AX5043_FREQUENCYGAINA0_V1
+#define AX5043_FREQUENCYGAINA1 AX5043_FREQUENCYGAINA1_V1
+#define AX5043_FREQUENCYGAINA2 AX5043_FREQUENCYGAINA2_V1
+#define AX5043_FREQUENCYGAINA3 AX5043_FREQUENCYGAINA3_V1
+#define AX5043_FREQUENCYGAINB0 AX5043_FREQUENCYGAINB0_V1
+#define AX5043_FREQUENCYGAINB1 AX5043_FREQUENCYGAINB1_V1
+#define AX5043_FREQUENCYGAINB2 AX5043_FREQUENCYGAINB2_V1
+#define AX5043_FREQUENCYGAINB3 AX5043_FREQUENCYGAINB3_V1
+#define AX5043_FREQUENCYGAINC0 AX5043_FREQUENCYGAINC0_V1
+#define AX5043_FREQUENCYGAINC1 AX5043_FREQUENCYGAINC1_V1
+#define AX5043_FREQUENCYGAINC2 AX5043_FREQUENCYGAINC2_V1
+#define AX5043_FREQUENCYGAINC3 AX5043_FREQUENCYGAINC3_V1
+#define AX5043_FREQUENCYGAIND0 AX5043_FREQUENCYGAIND0_V1
+#define AX5043_FREQUENCYGAIND1 AX5043_FREQUENCYGAIND1_V1
+#define AX5043_FREQUENCYGAIND2 AX5043_FREQUENCYGAIND2_V1
+#define AX5043_FREQUENCYGAIND3 AX5043_FREQUENCYGAIND3_V1
+#define AX5043_PHASEGAIN0 AX5043_PHASEGAIN0_V1
+#define AX5043_PHASEGAIN1 AX5043_PHASEGAIN1_V1
+#define AX5043_PHASEGAIN2 AX5043_PHASEGAIN2_V1
+#define AX5043_PHASEGAIN3 AX5043_PHASEGAIN3_V1
+#define AX5043_PKTADDR0 AX5043_PKTADDR0_V1
+#define AX5043_PKTADDR1 AX5043_PKTADDR1_V1
+#define AX5043_PKTADDRCFG AX5043_PKTADDRCFG_V1
+#define AX5043_PKTADDRMASK0 AX5043_PKTADDRMASK0_V1
+#define AX5043_PKTADDRMASK1 AX5043_PKTADDRMASK1_V1
+#define AX5043_PKTLENCFG AX5043_PKTLENCFG_V1
+#define AX5043_PKTLENOFFSET AX5043_PKTLENOFFSET_V1
+#define AX5043_PKTMAXLEN AX5043_PKTMAXLEN_V1
+#define AX5043_RXPARAMCURSET AX5043_RXPARAMCURSET_V1
+#define AX5043_RXPARAMSETS AX5043_RXPARAMSETS_V1
+#define AX5043_TIMEGAIN0 AX5043_TIMEGAIN0_V1
+#define AX5043_TIMEGAIN1 AX5043_TIMEGAIN1_V1
+#define AX5043_TIMEGAIN2 AX5043_TIMEGAIN2_V1
+#define AX5043_TIMEGAIN3 AX5043_TIMEGAIN3_V1
+#else
+SFRX(AX5043_AGCAHYST0, 0x4122) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST1, 0x4132) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST2, 0x4142) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCAHYST3, 0x4152) /* AGC Analog Hysteresis */
+SFRX(AX5043_AGCGAIN0, 0x4120) /* AGC Speed */
+SFRX(AX5043_AGCGAIN1, 0x4130) /* AGC Speed */
+SFRX(AX5043_AGCGAIN2, 0x4140) /* AGC Speed */
+SFRX(AX5043_AGCGAIN3, 0x4150) /* AGC Speed */
+SFRX(AX5043_AGCMINMAX0, 0x4123) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX1, 0x4133) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX2, 0x4143) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCMINMAX3, 0x4153) /* AGC Analog Update Behaviour */
+SFRX(AX5043_AGCTARGET0, 0x4121) /* AGC Target */
+SFRX(AX5043_AGCTARGET1, 0x4131) /* AGC Target */
+SFRX(AX5043_AGCTARGET2, 0x4141) /* AGC Target */
+SFRX(AX5043_AGCTARGET3, 0x4151) /* AGC Target */
+SFRX(AX5043_AMPLITUDEGAIN0, 0x412B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN1, 0x413B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN2, 0x414B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_AMPLITUDEGAIN3, 0x415B) /* Amplitude Estimator Bandwidth */
+SFRX(AX5043_BBOFFSRES0, 0x412F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES1, 0x413F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES2, 0x414F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_BBOFFSRES3, 0x415F) /* Baseband Offset Compensation Resistors */
+SFRX(AX5043_DRGAIN0, 0x4125) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN1, 0x4135) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN2, 0x4145) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_DRGAIN3, 0x4155) /* Data Rate Estimator Bandwidth */
+SFRX(AX5043_FOURFSK0, 0x412E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK1, 0x413E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK2, 0x414E) /* Four FSK Control */
+SFRX(AX5043_FOURFSK3, 0x415E) /* Four FSK Control */
+SFRX(AX5043_FREQDEV00, 0x412D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV01, 0x413D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV02, 0x414D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV03, 0x415D) /* Receiver Frequency Deviation 0 */
+SFRX(AX5043_FREQDEV10, 0x412C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV11, 0x413C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV12, 0x414C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQDEV13, 0x415C) /* Receiver Frequency Deviation 1 */
+SFRX(AX5043_FREQUENCYGAINA0, 0x4127) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA1, 0x4137) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA2, 0x4147) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINA3, 0x4157) /* Frequency Estimator Bandwidth A */
+SFRX(AX5043_FREQUENCYGAINB0, 0x4128) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB1, 0x4138) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB2, 0x4148) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINB3, 0x4158) /* Frequency Estimator Bandwidth B */
+SFRX(AX5043_FREQUENCYGAINC0, 0x4129) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC1, 0x4139) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC2, 0x4149) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAINC3, 0x4159) /* Frequency Estimator Bandwidth C */
+SFRX(AX5043_FREQUENCYGAIND0, 0x412A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND1, 0x413A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND2, 0x414A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYGAIND3, 0x415A) /* Frequency Estimator Bandwidth D */
+SFRX(AX5043_FREQUENCYLEAK, 0x4116) /* Baseband Frequency Recovery Loop Leakiness */
+SFRX(AX5043_PHASEGAIN0, 0x4126) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN1, 0x4136) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN2, 0x4146) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PHASEGAIN3, 0x4156) /* Phase Estimator Bandwidth */
+SFRX(AX5043_PKTADDR0, 0x4207) /* Packet Address 0 */
+SFRX(AX5043_PKTADDR1, 0x4206) /* Packet Address 1 */
+SFRX(AX5043_PKTADDR2, 0x4205) /* Packet Address 2 */
+SFRX(AX5043_PKTADDR3, 0x4204) /* Packet Address 3 */
+SFRX(AX5043_PKTADDRCFG, 0x4200) /* Packet Address Config */
+SFRX(AX5043_PKTADDRMASK0, 0x420B) /* Packet Address Mask 0 */
+SFRX(AX5043_PKTADDRMASK1, 0x420A) /* Packet Address Mask 1 */
+SFRX(AX5043_PKTADDRMASK2, 0x4209) /* Packet Address Mask 2 */
+SFRX(AX5043_PKTADDRMASK3, 0x4208) /* Packet Address Mask 3 */
+SFRX(AX5043_PKTLENCFG, 0x4201) /* Packet Length Configuration */
+SFRX(AX5043_PKTLENOFFSET, 0x4202) /* Packet Length Offset */
+SFRX(AX5043_PKTMAXLEN, 0x4203) /* Packet Maximum Length */
+SFRX(AX5043_RXPARAMCURSET, 0x4118) /* Receiver Parameter Current Set */
+SFRX(AX5043_RXPARAMSETS, 0x4117) /* Receiver Parameter Set Indirection */
+SFRX(AX5043_TIMEGAIN0, 0x4124) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN1, 0x4134) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN2, 0x4144) /* Time Estimator Bandwidth */
+SFRX(AX5043_TIMEGAIN3, 0x4154) /* Time Estimator Bandwidth */
+#endif
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+#if !defined AX5043_DISABLE_NONBLOCKING
+SFRX(AX5043_AFSKCTRLNB, 0x5114) /* AFSK Control, Non-Blocking */
+SFRX(AX5043_AFSKMARK0NB, 0x5113) /* AFSK Mark (1) Frequency 0, Non-Blocking */
+SFRX(AX5043_AFSKMARK1NB, 0x5112) /* AFSK Mark (1) Frequency 1, Non-Blocking */
+SFRX(AX5043_AFSKSPACE0NB, 0x5111) /* AFSK Space (0) Frequency 0, Non-Blocking */
+SFRX(AX5043_AFSKSPACE1NB, 0x5110) /* AFSK Space (0) Frequency 1, Non-Blocking */
+SFRX(AX5043_AGCCOUNTERNB, 0x5043) /* AGC Counter, Non-Blocking */
+SFRX(AX5043_AMPLFILTERNB, 0x5115) /* Amplitude Filter, Non-Blocking */
+SFRX(AX5043_BBOFFSCAPNB, 0x5189) /* Baseband Offset Compensation Capacitors, Non-Blocking */
+SFRX(AX5043_BBTUNENB, 0x5188) /* Baseband Tuning, Non-Blocking */
+SFRX(AX5043_BGNDRSSINB, 0x5041) /* Background RSSI, Non-Blocking */
+SFRX(AX5043_BGNDRSSIGAINNB, 0x522E) /* Background RSSI Averaging Time Constant, Non-Blocking */
+SFRX(AX5043_BGNDRSSITHRNB, 0x522F) /* Background RSSI Relative Threshold, Non-Blocking */
+SFRX(AX5043_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5043_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5043_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5043_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5043_DACCONFIGNB, 0x5332) /* DAC Configuration, Non-Blocking */
+SFRX(AX5043_DACVALUE0NB, 0x5331) /* DAC Value 0, Non-Blocking */
+SFRX(AX5043_DACVALUE1NB, 0x5330) /* DAC Value 1, Non-Blocking */
+SFRX(AX5043_DECIMATIONNB, 0x5102) /* Decimation Factor , Non-Blocking */
+SFRX(AX5043_DIVERSITYNB, 0x5042) /* Antenna Diversity Configuration, Non-Blocking */
+SFRX(AX5043_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5043_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5043_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5043_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5043_FIFOCOUNT0NB, 0x502B) /* Number of Words currently in FIFO 0, Non-Blocking */
+SFRX(AX5043_FIFOCOUNT1NB, 0x502A) /* Number of Words currently in FIFO 1, Non-Blocking */
+SFRX(AX5043_FIFODATANB, 0x5029) /* FIFO Data, Non-Blocking */
+SFRX(AX5043_FIFOFREE0NB, 0x502D) /* Number of Words that can be written to FIFO 0, Non-Blocking */
+SFRX(AX5043_FIFOFREE1NB, 0x502C) /* Number of Words that can be written to FIFO 1, Non-Blocking */
+SFRX(AX5043_FIFOSTATNB, 0x5028) /* FIFO Control, Non-Blocking */
+SFRX(AX5043_FIFOTHRESH0NB, 0x502F) /* FIFO Threshold 0, Non-Blocking */
+SFRX(AX5043_FIFOTHRESH1NB, 0x502E) /* FIFO Threshold 1, Non-Blocking */
+SFRX(AX5043_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5043_FREQA0NB, 0x5037) /* Frequency A 0, Non-Blocking */
+SFRX(AX5043_FREQA1NB, 0x5036) /* Frequency A 1, Non-Blocking */
+SFRX(AX5043_FREQA2NB, 0x5035) /* Frequency A 2, Non-Blocking */
+SFRX(AX5043_FREQA3NB, 0x5034) /* Frequency A 3, Non-Blocking */
+SFRX(AX5043_FREQB0NB, 0x503F) /* Frequency B 0, Non-Blocking */
+SFRX(AX5043_FREQB1NB, 0x503E) /* Frequency B 1, Non-Blocking */
+SFRX(AX5043_FREQB2NB, 0x503D) /* Frequency B 2, Non-Blocking */
+SFRX(AX5043_FREQB3NB, 0x503C) /* Frequency B 3, Non-Blocking */
+SFRX(AX5043_FSKDEV0NB, 0x5163) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDEV1NB, 0x5162) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5043_FSKDEV2NB, 0x5161) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5043_FSKDMAX0NB, 0x510D) /* Four FSK Rx Maximum Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDMAX1NB, 0x510C) /* Four FSK Rx Maximum Deviation 1, Non-Blocking */
+SFRX(AX5043_FSKDMIN0NB, 0x510F) /* Four FSK Rx Minimum Deviation 0, Non-Blocking */
+SFRX(AX5043_FSKDMIN1NB, 0x510E) /* Four FSK Rx Minimum Deviation 1, Non-Blocking */
+SFRX(AX5043_GPADC13VALUE0NB, 0x5309) /* GPADC13 Value 0, Non-Blocking */
+SFRX(AX5043_GPADC13VALUE1NB, 0x5308) /* GPADC13 Value 1, Non-Blocking */
+SFRX(AX5043_GPADCCTRLNB, 0x5300) /* General Purpose ADC Control, Non-Blocking */
+SFRX(AX5043_GPADCPERIODNB, 0x5301) /* GPADC Sampling Period, Non-Blocking */
+SFRX(AX5043_IFFREQ0NB, 0x5101) /* 2nd LO / IF Frequency 0, Non-Blocking */
+SFRX(AX5043_IFFREQ1NB, 0x5100) /* 2nd LO / IF Frequency 1, Non-Blocking */
+SFRX(AX5043_IRQINVERSION0NB, 0x500B) /* IRQ Inversion 0, Non-Blocking */
+SFRX(AX5043_IRQINVERSION1NB, 0x500A) /* IRQ Inversion 1, Non-Blocking */
+SFRX(AX5043_IRQMASK0NB, 0x5007) /* IRQ Mask 0, Non-Blocking */
+SFRX(AX5043_IRQMASK1NB, 0x5006) /* IRQ Mask 1, Non-Blocking */
+SFRX(AX5043_IRQREQUEST0NB, 0x500D) /* IRQ Request 0, Non-Blocking */
+SFRX(AX5043_IRQREQUEST1NB, 0x500C) /* IRQ Request 1, Non-Blocking */
+SFRX(AX5043_LPOSCCONFIGNB, 0x5310) /* Low Power Oscillator Calibration Configuration, Non-Blocking */
+SFRX(AX5043_LPOSCFREQ0NB, 0x5317) /* Low Power Oscillator Frequency Tuning Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCFREQ1NB, 0x5316) /* Low Power Oscillator Frequency Tuning High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCKFILT0NB, 0x5313) /* Low Power Oscillator Calibration Filter Constant Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCKFILT1NB, 0x5312) /* Low Power Oscillator Calibration Filter Constant High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCPER0NB, 0x5319) /* Low Power Oscillator Period Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCPER1NB, 0x5318) /* Low Power Oscillator Period High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCREF0NB, 0x5315) /* Low Power Oscillator Reference Frequency Low Byte, Non-Blocking */
+SFRX(AX5043_LPOSCREF1NB, 0x5314) /* Low Power Oscillator Reference Frequency High Byte, Non-Blocking */
+SFRX(AX5043_LPOSCSTATUSNB, 0x5311) /* Low Power Oscillator Calibration Status, Non-Blocking */
+SFRX(AX5043_MATCH0LENNB, 0x5214) /* Pattern Match Unit 0, Pattern Length, Non-Blocking */
+SFRX(AX5043_MATCH0MAXNB, 0x5216) /* Pattern Match Unit 0, Maximum Match, Non-Blocking */
+SFRX(AX5043_MATCH0MINNB, 0x5215) /* Pattern Match Unit 0, Minimum Match, Non-Blocking */
+SFRX(AX5043_MATCH0PAT0NB, 0x5213) /* Pattern Match Unit 0, Pattern 0, Non-Blocking */
+SFRX(AX5043_MATCH0PAT1NB, 0x5212) /* Pattern Match Unit 0, Pattern 1, Non-Blocking */
+SFRX(AX5043_MATCH0PAT2NB, 0x5211) /* Pattern Match Unit 0, Pattern 2, Non-Blocking */
+SFRX(AX5043_MATCH0PAT3NB, 0x5210) /* Pattern Match Unit 0, Pattern 3, Non-Blocking */
+SFRX(AX5043_MATCH1LENNB, 0x521C) /* Pattern Match Unit 1, Pattern Length, Non-Blocking */
+SFRX(AX5043_MATCH1MAXNB, 0x521E) /* Pattern Match Unit 1, Maximum Match, Non-Blocking */
+SFRX(AX5043_MATCH1MINNB, 0x521D) /* Pattern Match Unit 1, Minimum Match, Non-Blocking */
+SFRX(AX5043_MATCH1PAT0NB, 0x5219) /* Pattern Match Unit 1, Pattern 0, Non-Blocking */
+SFRX(AX5043_MATCH1PAT1NB, 0x5218) /* Pattern Match Unit 1, Pattern 1, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET0NB, 0x5108) /* Maximum Receiver Datarate Offset 0, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET1NB, 0x5107) /* Maximum Receiver Datarate Offset 1, Non-Blocking */
+SFRX(AX5043_MAXDROFFSET2NB, 0x5106) /* Maximum Receiver Datarate Offset 2, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET0NB, 0x510B) /* Maximum Receiver RF Offset 0, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET1NB, 0x510A) /* Maximum Receiver RF Offset 1, Non-Blocking */
+SFRX(AX5043_MAXRFOFFSET2NB, 0x5109) /* Maximum Receiver RF Offset 2, Non-Blocking */
+SFRX(AX5043_MODCFGANB, 0x5164) /* Modulator Configuration A, Non-Blocking */
+SFRX(AX5043_MODCFGFNB, 0x5160) /* Modulator Configuration F, Non-Blocking */
+SFRX(AX5043_MODCFGPNB, 0x5F5F) /* Modulator Configuration P, Non-Blocking */
+SFRX(AX5043_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5043_PINFUNCANTSELNB, 0x5025) /* Pin Function ANTSEL, Non-Blocking */
+SFRX(AX5043_PINFUNCDATANB, 0x5023) /* Pin Function DATA, Non-Blocking */
+SFRX(AX5043_PINFUNCDCLKNB, 0x5022) /* Pin Function DCLK, Non-Blocking */
+SFRX(AX5043_PINFUNCIRQNB, 0x5024) /* Pin Function IRQ, Non-Blocking */
+SFRX(AX5043_PINFUNCPWRAMPNB, 0x5026) /* Pin Function PWRAMP, Non-Blocking */
+SFRX(AX5043_PINFUNCSYSCLKNB, 0x5021) /* Pin Function SYSCLK, Non-Blocking */
+SFRX(AX5043_PINSTATENB, 0x5020) /* Pin State, Non-Blocking */
+SFRX(AX5043_PKTACCEPTFLAGSNB, 0x5233) /* Packet Controller Accept Flags, Non-Blocking */
+SFRX(AX5043_PKTCHUNKSIZENB, 0x5230) /* Packet Chunk Size, Non-Blocking */
+SFRX(AX5043_PKTMISCFLAGSNB, 0x5231) /* Packet Controller Miscellaneous Flags, Non-Blocking */
+SFRX(AX5043_PKTSTOREFLAGSNB, 0x5232) /* Packet Controller Store Flags, Non-Blocking */
+SFRX(AX5043_PLLCPINB, 0x5031) /* PLL Charge Pump Current, Non-Blocking */
+SFRX(AX5043_PLLCPIBOOSTNB, 0x5039) /* PLL Charge Pump Current (Boosted), Non-Blocking */
+SFRX(AX5043_PLLLOCKDETNB, 0x5182) /* PLL Lock Detect Delay, Non-Blocking */
+SFRX(AX5043_PLLLOOPNB, 0x5030) /* PLL Loop Filter Settings, Non-Blocking */
+SFRX(AX5043_PLLLOOPBOOSTNB, 0x5038) /* PLL Loop Filter Settings (Boosted), Non-Blocking */
+SFRX(AX5043_PLLRANGINGANB, 0x5033) /* PLL Autoranging A, Non-Blocking */
+SFRX(AX5043_PLLRANGINGBNB, 0x503B) /* PLL Autoranging B, Non-Blocking */
+SFRX(AX5043_PLLRNGCLKNB, 0x5183) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5043_PLLVCODIVNB, 0x5032) /* PLL Divider Settings, Non-Blocking */
+SFRX(AX5043_PLLVCOINB, 0x5180) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5043_PLLVCOIRNB, 0x5181) /* PLL VCO Current Readback, Non-Blocking */
+SFRX(AX5043_POWCTRL1NB, 0x5F08) /* Power Control 1, Non-Blocking */
+SFRX(AX5043_POWIRQMASKNB, 0x5005) /* Power Management Interrupt Mask, Non-Blocking */
+SFRX(AX5043_POWSTATNB, 0x5003) /* Power Management Status, Non-Blocking */
+SFRX(AX5043_POWSTICKYSTATNB, 0x5004) /* Power Management Sticky Status, Non-Blocking */
+SFRX(AX5043_PWRAMPNB, 0x5027) /* PWRAMP Control, Non-Blocking */
+SFRX(AX5043_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5043_RADIOEVENTMASK0NB, 0x5009) /* Radio Event Mask 0, Non-Blocking */
+SFRX(AX5043_RADIOEVENTMASK1NB, 0x5008) /* Radio Event Mask 1, Non-Blocking */
+SFRX(AX5043_RADIOEVENTREQ0NB, 0x500F) /* Radio Event Request 0, Non-Blocking */
+SFRX(AX5043_RADIOEVENTREQ1NB, 0x500E) /* Radio Event Request 1, Non-Blocking */
+SFRX(AX5043_RADIOSTATENB, 0x501C) /* Radio Controller State, Non-Blocking */
+SFRX(AX5043_REFNB, 0x5F0D) /* Reference, Non-Blocking */
+SFRX(AX5043_RSSINB, 0x5040) /* Received Signal Strength Indicator, Non-Blocking */
+SFRX(AX5043_RSSIABSTHRNB, 0x522D) /* RSSI Absolute Threshold, Non-Blocking */
+SFRX(AX5043_RSSIREFERENCENB, 0x522C) /* RSSI Offset, Non-Blocking */
+SFRX(AX5043_RXDATARATE0NB, 0x5105) /* Receiver Datarate 0, Non-Blocking */
+SFRX(AX5043_RXDATARATE1NB, 0x5104) /* Receiver Datarate 1, Non-Blocking */
+SFRX(AX5043_RXDATARATE2NB, 0x5103) /* Receiver Datarate 2, Non-Blocking */
+SFRX(AX5043_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5043_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5043_TIMER0NB, 0x505B) /* 1MHz Timer 0, Non-Blocking */
+SFRX(AX5043_TIMER1NB, 0x505A) /* 1MHz Timer 1, Non-Blocking */
+SFRX(AX5043_TIMER2NB, 0x5059) /* 1MHz Timer 2, Non-Blocking */
+SFRX(AX5043_TMGRXAGCNB, 0x5227) /* Receiver AGC Settling Time, Non-Blocking */
+SFRX(AX5043_TMGRXBOOSTNB, 0x5223) /* Receive PLL Boost Time, Non-Blocking */
+SFRX(AX5043_TMGRXCOARSEAGCNB, 0x5226) /* Receive Coarse AGC Time, Non-Blocking */
+SFRX(AX5043_TMGRXOFFSACQNB, 0x5225) /* Receive Baseband DC Offset Acquisition Time, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE1NB, 0x5229) /* Receiver Preamble 1 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE2NB, 0x522A) /* Receiver Preamble 2 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXPREAMBLE3NB, 0x522B) /* Receiver Preamble 3 Timeout, Non-Blocking */
+SFRX(AX5043_TMGRXRSSINB, 0x5228) /* Receiver RSSI Settling Time, Non-Blocking */
+SFRX(AX5043_TMGRXSETTLENB, 0x5224) /* Receive PLL (post Boost) Settling Time, Non-Blocking */
+SFRX(AX5043_TMGTXBOOSTNB, 0x5220) /* Transmit PLL Boost Time, Non-Blocking */
+SFRX(AX5043_TMGTXSETTLENB, 0x5221) /* Transmit PLL (post Boost) Settling Time, Non-Blocking */
+SFRX(AX5043_TRKAFSKDEMOD0NB, 0x5055) /* AFSK Demodulator Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKAFSKDEMOD1NB, 0x5054) /* AFSK Demodulator Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKAMPLITUDE0NB, 0x5049) /* Amplitude Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKAMPLITUDE1NB, 0x5048) /* Amplitude Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKDATARATE0NB, 0x5047) /* Datarate Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKDATARATE1NB, 0x5046) /* Datarate Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKDATARATE2NB, 0x5045) /* Datarate Tracking 2, Non-Blocking */
+SFRX(AX5043_TRKFREQ0NB, 0x5051) /* Frequency Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKFREQ1NB, 0x5050) /* Frequency Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKFSKDEMOD0NB, 0x5053) /* FSK Demodulator Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKFSKDEMOD1NB, 0x5052) /* FSK Demodulator Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKPHASE0NB, 0x504B) /* Phase Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKPHASE1NB, 0x504A) /* Phase Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ0NB, 0x504F) /* RF Frequency Tracking 0, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ1NB, 0x504E) /* RF Frequency Tracking 1, Non-Blocking */
+SFRX(AX5043_TRKRFFREQ2NB, 0x504D) /* RF Frequency Tracking 2, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFA0NB, 0x5169) /* Transmitter Predistortion Coefficient A 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFA1NB, 0x5168) /* Transmitter Predistortion Coefficient A 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFB0NB, 0x516B) /* Transmitter Predistortion Coefficient B 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFB1NB, 0x516A) /* Transmitter Predistortion Coefficient B 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFC0NB, 0x516D) /* Transmitter Predistortion Coefficient C 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFC1NB, 0x516C) /* Transmitter Predistortion Coefficient C 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFD0NB, 0x516F) /* Transmitter Predistortion Coefficient D 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFD1NB, 0x516E) /* Transmitter Predistortion Coefficient D 1, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFE0NB, 0x5171) /* Transmitter Predistortion Coefficient E 0, Non-Blocking */
+SFRX(AX5043_TXPWRCOEFFE1NB, 0x5170) /* Transmitter Predistortion Coefficient E 1, Non-Blocking */
+SFRX(AX5043_TXRATE0NB, 0x5167) /* Transmitter Bitrate 0, Non-Blocking */
+SFRX(AX5043_TXRATE1NB, 0x5166) /* Transmitter Bitrate 1, Non-Blocking */
+SFRX(AX5043_TXRATE2NB, 0x5165) /* Transmitter Bitrate 2, Non-Blocking */
+SFRX(AX5043_WAKEUP0NB, 0x506B) /* Wakeup Time 0, Non-Blocking */
+SFRX(AX5043_WAKEUP1NB, 0x506A) /* Wakeup Time 1, Non-Blocking */
+SFRX(AX5043_WAKEUPFREQ0NB, 0x506D) /* Wakeup Frequency 0, Non-Blocking */
+SFRX(AX5043_WAKEUPFREQ1NB, 0x506C) /* Wakeup Frequency 1, Non-Blocking */
+SFRX(AX5043_WAKEUPTIMER0NB, 0x5069) /* Wakeup Timer 0, Non-Blocking */
+SFRX(AX5043_WAKEUPTIMER1NB, 0x5068) /* Wakeup Timer 1, Non-Blocking */
+SFRX(AX5043_WAKEUPXOEARLYNB, 0x506E) /* Wakeup Crystal Oscillator Early, Non-Blocking */
+SFRX(AX5043_XTALAMPLNB, 0x5F11) /* Crystal Oscillator Amplitude Control, Non-Blocking */
+SFRX(AX5043_XTALCAPNB, 0x5184) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5043_XTALOSCNB, 0x5F10) /* Crystal Oscillator Control, Non-Blocking */
+SFRX(AX5043_XTALSTATUSNB, 0x501D) /* Crystal Oscillator Status, Non-Blocking */
+
+SFRX(AX5043_0xF00NB, 0x5F00)
+SFRX(AX5043_0xF0CNB, 0x5F0C)
+SFRX(AX5043_0xF18NB, 0x5F18)
+SFRX(AX5043_0xF1CNB, 0x5F1C)
+SFRX(AX5043_0xF21NB, 0x5F21)
+SFRX(AX5043_0xF22NB, 0x5F22)
+SFRX(AX5043_0xF23NB, 0x5F23)
+SFRX(AX5043_0xF26NB, 0x5F26)
+SFRX(AX5043_0xF30NB, 0x5F30)
+SFRX(AX5043_0xF31NB, 0x5F31)
+SFRX(AX5043_0xF32NB, 0x5F32)
+SFRX(AX5043_0xF33NB, 0x5F33)
+SFRX(AX5043_0xF34NB, 0x5F34)
+SFRX(AX5043_0xF35NB, 0x5F35)
+SFRX(AX5043_0xF44NB, 0x5F44)
+
+#if defined AX5043V1
+SFRX(AX5043_AGCGAIN0NB_V1, 0x5120) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN1NB_V1, 0x512E) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN2NB_V1, 0x513C) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN3NB_V1, 0x514A) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCTARGET0NB_V1, 0x5121) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET1NB_V1, 0x512F) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET2NB_V1, 0x513D) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET3NB_V1, 0x514B) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN0NB_V1, 0x5129) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN1NB_V1, 0x5137) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN2NB_V1, 0x5145) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN3NB_V1, 0x5153) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_BBOFFSRES0NB_V1, 0x512D) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES1NB_V1, 0x513B) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES2NB_V1, 0x5149) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES3NB_V1, 0x5157) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_DRGAIN0NB_V1, 0x5123) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN1NB_V1, 0x5131) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN2NB_V1, 0x513F) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN3NB_V1, 0x514D) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_FOURFSK0NB_V1, 0x512C) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK1NB_V1, 0x513A) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK2NB_V1, 0x5148) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK3NB_V1, 0x5156) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FREQDEV00NB_V1, 0x512B) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV01NB_V1, 0x5139) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV02NB_V1, 0x5147) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV03NB_V1, 0x5155) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV10NB_V1, 0x512A) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV11NB_V1, 0x5138) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV12NB_V1, 0x5146) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV13NB_V1, 0x5154) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA0NB_V1, 0x5125) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA1NB_V1, 0x5133) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA2NB_V1, 0x5141) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA3NB_V1, 0x514F) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB0NB_V1, 0x5126) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB1NB_V1, 0x5134) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB2NB_V1, 0x5142) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB3NB_V1, 0x5150) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC0NB_V1, 0x5127) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC1NB_V1, 0x5135) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC2NB_V1, 0x5143) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC3NB_V1, 0x5151) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND0NB_V1, 0x5128) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND1NB_V1, 0x5136) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND2NB_V1, 0x5144) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND3NB_V1, 0x5152) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_PHASEGAIN0NB_V1, 0x5124) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN1NB_V1, 0x5132) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN2NB_V1, 0x5140) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN3NB_V1, 0x514E) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PKTADDR0NB_V1, 0x5203) /* Packet Address 0, Non-Blocking */
+SFRX(AX5043_PKTADDR1NB_V1, 0x5202) /* Packet Address 1, Non-Blocking */
+SFRX(AX5043_PKTADDRCFGNB_V1, 0x5201) /* Packet Address Config, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK0NB_V1, 0x5205) /* Packet Address Mask 0, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK1NB_V1, 0x5204) /* Packet Address Mask 1, Non-Blocking */
+SFRX(AX5043_PKTLENCFGNB_V1, 0x5206) /* Packet Length Configuration, Non-Blocking */
+SFRX(AX5043_PKTLENOFFSETNB_V1, 0x5207) /* Packet Length Offset, Non-Blocking */
+SFRX(AX5043_PKTMAXLENNB_V1, 0x5208) /* Packet Maximum Length, Non-Blocking */
+SFRX(AX5043_RXPARAMCURSETNB_V1, 0x5117) /* Receiver Parameter Current Set, Non-Blocking */
+SFRX(AX5043_RXPARAMSETSNB_V1, 0x5116) /* Receiver Parameter Set Indirection, Non-Blocking */
+SFRX(AX5043_TIMEGAIN0NB_V1, 0x5122) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN1NB_V1, 0x5130) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN2NB_V1, 0x513E) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN3NB_V1, 0x514C) /* Time Estimator Bandwidth, Non-Blocking */
+
+#define AX5043_AGCGAIN0NB AX5043_AGCGAIN0NB_V1
+#define AX5043_AGCGAIN1NB AX5043_AGCGAIN1NB_V1
+#define AX5043_AGCGAIN2NB AX5043_AGCGAIN2NB_V1
+#define AX5043_AGCGAIN3NB AX5043_AGCGAIN3NB_V1
+#define AX5043_AGCTARGET0NB AX5043_AGCTARGET0NB_V1
+#define AX5043_AGCTARGET1NB AX5043_AGCTARGET1NB_V1
+#define AX5043_AGCTARGET2NB AX5043_AGCTARGET2NB_V1
+#define AX5043_AGCTARGET3NB AX5043_AGCTARGET3NB_V1
+#define AX5043_AMPLITUDEGAIN0NB AX5043_AMPLITUDEGAIN0NB_V1
+#define AX5043_AMPLITUDEGAIN1NB AX5043_AMPLITUDEGAIN1NB_V1
+#define AX5043_AMPLITUDEGAIN2NB AX5043_AMPLITUDEGAIN2NB_V1
+#define AX5043_AMPLITUDEGAIN3NB AX5043_AMPLITUDEGAIN3NB_V1
+#define AX5043_BBOFFSRES0NB AX5043_BBOFFSRES0NB_V1
+#define AX5043_BBOFFSRES1NB AX5043_BBOFFSRES1NB_V1
+#define AX5043_BBOFFSRES2NB AX5043_BBOFFSRES2NB_V1
+#define AX5043_BBOFFSRES3NB AX5043_BBOFFSRES3NB_V1
+#define AX5043_DRGAIN0NB AX5043_DRGAIN0NB_V1
+#define AX5043_DRGAIN1NB AX5043_DRGAIN1NB_V1
+#define AX5043_DRGAIN2NB AX5043_DRGAIN2NB_V1
+#define AX5043_DRGAIN3NB AX5043_DRGAIN3NB_V1
+#define AX5043_FOURFSK0NB AX5043_FOURFSK0NB_V1
+#define AX5043_FOURFSK1NB AX5043_FOURFSK1NB_V1
+#define AX5043_FOURFSK2NB AX5043_FOURFSK2NB_V1
+#define AX5043_FOURFSK3NB AX5043_FOURFSK3NB_V1
+#define AX5043_FREQDEV00NB AX5043_FREQDEV00NB_V1
+#define AX5043_FREQDEV01NB AX5043_FREQDEV01NB_V1
+#define AX5043_FREQDEV02NB AX5043_FREQDEV02NB_V1
+#define AX5043_FREQDEV03NB AX5043_FREQDEV03NB_V1
+#define AX5043_FREQDEV10NB AX5043_FREQDEV10NB_V1
+#define AX5043_FREQDEV11NB AX5043_FREQDEV11NB_V1
+#define AX5043_FREQDEV12NB AX5043_FREQDEV12NB_V1
+#define AX5043_FREQDEV13NB AX5043_FREQDEV13NB_V1
+#define AX5043_FREQUENCYGAINA0NB AX5043_FREQUENCYGAINA0NB_V1
+#define AX5043_FREQUENCYGAINA1NB AX5043_FREQUENCYGAINA1NB_V1
+#define AX5043_FREQUENCYGAINA2NB AX5043_FREQUENCYGAINA2NB_V1
+#define AX5043_FREQUENCYGAINA3NB AX5043_FREQUENCYGAINA3NB_V1
+#define AX5043_FREQUENCYGAINB0NB AX5043_FREQUENCYGAINB0NB_V1
+#define AX5043_FREQUENCYGAINB1NB AX5043_FREQUENCYGAINB1NB_V1
+#define AX5043_FREQUENCYGAINB2NB AX5043_FREQUENCYGAINB2NB_V1
+#define AX5043_FREQUENCYGAINB3NB AX5043_FREQUENCYGAINB3NB_V1
+#define AX5043_FREQUENCYGAINC0NB AX5043_FREQUENCYGAINC0NB_V1
+#define AX5043_FREQUENCYGAINC1NB AX5043_FREQUENCYGAINC1NB_V1
+#define AX5043_FREQUENCYGAINC2NB AX5043_FREQUENCYGAINC2NB_V1
+#define AX5043_FREQUENCYGAINC3NB AX5043_FREQUENCYGAINC3NB_V1
+#define AX5043_FREQUENCYGAIND0NB AX5043_FREQUENCYGAIND0NB_V1
+#define AX5043_FREQUENCYGAIND1NB AX5043_FREQUENCYGAIND1NB_V1
+#define AX5043_FREQUENCYGAIND2NB AX5043_FREQUENCYGAIND2NB_V1
+#define AX5043_FREQUENCYGAIND3NB AX5043_FREQUENCYGAIND3NB_V1
+#define AX5043_PHASEGAIN0NB AX5043_PHASEGAIN0NB_V1
+#define AX5043_PHASEGAIN1NB AX5043_PHASEGAIN1NB_V1
+#define AX5043_PHASEGAIN2NB AX5043_PHASEGAIN2NB_V1
+#define AX5043_PHASEGAIN3NB AX5043_PHASEGAIN3NB_V1
+#define AX5043_PKTADDR0NB AX5043_PKTADDR0NB_V1
+#define AX5043_PKTADDR1NB AX5043_PKTADDR1NB_V1
+#define AX5043_PKTADDRCFGNB AX5043_PKTADDRCFGNB_V1
+#define AX5043_PKTADDRMASK0NB AX5043_PKTADDRMASK0NB_V1
+#define AX5043_PKTADDRMASK1NB AX5043_PKTADDRMASK1NB_V1
+#define AX5043_PKTLENCFGNB AX5043_PKTLENCFGNB_V1
+#define AX5043_PKTLENOFFSETNB AX5043_PKTLENOFFSETNB_V1
+#define AX5043_PKTMAXLENNB AX5043_PKTMAXLENNB_V1
+#define AX5043_RXPARAMCURSETNB AX5043_RXPARAMCURSETNB_V1
+#define AX5043_RXPARAMSETSNB AX5043_RXPARAMSETSNB_V1
+#define AX5043_TIMEGAIN0NB AX5043_TIMEGAIN0NB_V1
+#define AX5043_TIMEGAIN1NB AX5043_TIMEGAIN1NB_V1
+#define AX5043_TIMEGAIN2NB AX5043_TIMEGAIN2NB_V1
+#define AX5043_TIMEGAIN3NB AX5043_TIMEGAIN3NB_V1
+#else
+SFRX(AX5043_AGCAHYST0NB, 0x5122) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST1NB, 0x5132) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST2NB, 0x5142) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCAHYST3NB, 0x5152) /* AGC Analog Hysteresis, Non-Blocking */
+SFRX(AX5043_AGCGAIN0NB, 0x5120) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN1NB, 0x5130) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN2NB, 0x5140) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCGAIN3NB, 0x5150) /* AGC Speed, Non-Blocking */
+SFRX(AX5043_AGCMINMAX0NB, 0x5123) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX1NB, 0x5133) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX2NB, 0x5143) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCMINMAX3NB, 0x5153) /* AGC Analog Update Behaviour, Non-Blocking */
+SFRX(AX5043_AGCTARGET0NB, 0x5121) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET1NB, 0x5131) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET2NB, 0x5141) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AGCTARGET3NB, 0x5151) /* AGC Target, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN0NB, 0x512B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN1NB, 0x513B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN2NB, 0x514B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_AMPLITUDEGAIN3NB, 0x515B) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_BBOFFSRES0NB, 0x512F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES1NB, 0x513F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES2NB, 0x514F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_BBOFFSRES3NB, 0x515F) /* Baseband Offset Compensation Resistors, Non-Blocking */
+SFRX(AX5043_DRGAIN0NB, 0x5125) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN1NB, 0x5135) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN2NB, 0x5145) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_DRGAIN3NB, 0x5155) /* Data Rate Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_FOURFSK0NB, 0x512E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK1NB, 0x513E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK2NB, 0x514E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FOURFSK3NB, 0x515E) /* Four FSK Control, Non-Blocking */
+SFRX(AX5043_FREQDEV00NB, 0x512D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV01NB, 0x513D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV02NB, 0x514D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV03NB, 0x515D) /* Receiver Frequency Deviation 0, Non-Blocking */
+SFRX(AX5043_FREQDEV10NB, 0x512C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV11NB, 0x513C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV12NB, 0x514C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQDEV13NB, 0x515C) /* Receiver Frequency Deviation 1, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA0NB, 0x5127) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA1NB, 0x5137) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA2NB, 0x5147) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINA3NB, 0x5157) /* Frequency Estimator Bandwidth A, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB0NB, 0x5128) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB1NB, 0x5138) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB2NB, 0x5148) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINB3NB, 0x5158) /* Frequency Estimator Bandwidth B, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC0NB, 0x5129) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC1NB, 0x5139) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC2NB, 0x5149) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAINC3NB, 0x5159) /* Frequency Estimator Bandwidth C, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND0NB, 0x512A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND1NB, 0x513A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND2NB, 0x514A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYGAIND3NB, 0x515A) /* Frequency Estimator Bandwidth D, Non-Blocking */
+SFRX(AX5043_FREQUENCYLEAKNB, 0x5116) /* Baseband Frequency Recovery Loop Leakiness, Non-Blocking */
+SFRX(AX5043_PHASEGAIN0NB, 0x5126) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN1NB, 0x5136) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN2NB, 0x5146) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PHASEGAIN3NB, 0x5156) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_PKTADDR0NB, 0x5207) /* Packet Address 0, Non-Blocking */
+SFRX(AX5043_PKTADDR1NB, 0x5206) /* Packet Address 1, Non-Blocking */
+SFRX(AX5043_PKTADDR2NB, 0x5205) /* Packet Address 2, Non-Blocking */
+SFRX(AX5043_PKTADDR3NB, 0x5204) /* Packet Address 3, Non-Blocking */
+SFRX(AX5043_PKTADDRCFGNB, 0x5200) /* Packet Address Config, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK0NB, 0x520B) /* Packet Address Mask 0, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK1NB, 0x520A) /* Packet Address Mask 1, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK2NB, 0x5209) /* Packet Address Mask 2, Non-Blocking */
+SFRX(AX5043_PKTADDRMASK3NB, 0x5208) /* Packet Address Mask 3, Non-Blocking */
+SFRX(AX5043_PKTLENCFGNB, 0x5201) /* Packet Length Configuration, Non-Blocking */
+SFRX(AX5043_PKTLENOFFSETNB, 0x5202) /* Packet Length Offset, Non-Blocking */
+SFRX(AX5043_PKTMAXLENNB, 0x5203) /* Packet Maximum Length, Non-Blocking */
+SFRX(AX5043_RXPARAMCURSETNB, 0x5118) /* Receiver Parameter Current Set, Non-Blocking */
+SFRX(AX5043_RXPARAMSETSNB, 0x5117) /* Receiver Parameter Set Indirection, Non-Blocking */
+SFRX(AX5043_TIMEGAIN0NB, 0x5124) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN1NB, 0x5134) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN2NB, 0x5144) /* Time Estimator Bandwidth, Non-Blocking */
+SFRX(AX5043_TIMEGAIN3NB, 0x5154) /* Time Estimator Bandwidth, Non-Blocking */
+#endif
+#endif
+
+#endif /* AX8052F143_H */
diff --git a/libs/libmf/source/ax8052f151.h b/libs/libmf/source/ax8052f151.h
new file mode 100644
index 00000000..07ea03d7
--- /dev/null
+++ b/libs/libmf/source/ax8052f151.h
@@ -0,0 +1,220 @@
+/*-------------------------------------------------------------------------
+ AX8052F151.h - Register Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012, 2016 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052F151_H
+#define AX8052F151_H
+
+#include
+
+/* Radio Registers, X Address Space */
+
+SFRX(AX5051_ADCMISC, 0x4038) /* ADC Miscellaneous Control */
+SFRX(AX5051_AGCATTACK, 0x403A) /* AGC Attack Speed */
+SFRX(AX5051_AGCCOUNTER, 0x403C) /* AGC Counter */
+SFRX(AX5051_AGCDECAY, 0x403B) /* AGC Decay Speed */
+SFRX(AX5051_AGCTARGET, 0x4039) /* AGC Target Value */
+SFRX(AX5051_AMPLITUDEGAIN, 0x4047) /* Amplitude Estimator Bandwidth */
+SFRX(AX5051_CICDECHI, 0x403E) /* Decimation Factor High */
+SFRX(AX5051_CICDECLO, 0x403F) /* Decimation Factor Low */
+SFRX(AX5051_CICSHIFT, 0x403D) /* Decimation Filter Attenuation */
+SFRX(AX5051_CRCINIT0, 0x4017) /* CRC Initial Value 0 */
+SFRX(AX5051_CRCINIT1, 0x4016) /* CRC Initial Value 1 */
+SFRX(AX5051_CRCINIT2, 0x4015) /* CRC Initial Value 2 */
+SFRX(AX5051_CRCINIT3, 0x4014) /* CRC Initial Value 3 */
+SFRX(AX5051_DATARATEHI, 0x4040) /* Datarate High */
+SFRX(AX5051_DATARATELO, 0x4041) /* Datarate Low */
+SFRX(AX5051_DSPMODE, 0x4009) /* DSP Mode Interface Control */
+SFRX(AX5051_ENCODING, 0x4011) /* Encoding */
+SFRX(AX5051_FEC, 0x4018) /* Forward Error Correction */
+SFRX(AX5051_FECMEM, 0x406F) /* Forward Error Correction Memory */
+SFRX(AX5051_FECSTATUS, 0x401A) /* Forward Error Correction Status */
+SFRX(AX5051_FECSYNC, 0x4019) /* Forward Error Correction Sync Threshold */
+SFRX(AX5051_FIFOCONTROL, 0x4004) /* FIFO Control */
+SFRX(AX5051_FIFOCONTROL2, 0x4037) /* FIFO Control 2 */
+SFRX(AX5051_FIFOCOUNT, 0x4035) /* FIFO Count */
+SFRX(AX5051_FIFODATA, 0x4005) /* FIFO Data */
+SFRX(AX5051_FIFOTHRESH, 0x4036) /* FIFO Threshold */
+SFRX(AX5051_FRAMING, 0x4012) /* Framing Mode */
+SFRX(AX5051_FREQ0, 0x4023) /* Frequency 0 */
+SFRX(AX5051_FREQ1, 0x4022) /* Frequency 1 */
+SFRX(AX5051_FREQ2, 0x4021) /* Frequency 2 */
+SFRX(AX5051_FREQ3, 0x4020) /* Frequency 3 */
+SFRX(AX5051_FREQA0, 0x4023) /* Frequency 0 */
+SFRX(AX5051_FREQA1, 0x4022) /* Frequency 1 */
+SFRX(AX5051_FREQA2, 0x4021) /* Frequency 2 */
+SFRX(AX5051_FREQA3, 0x4020) /* Frequency 3 */
+SFRX(AX5051_FREQUENCYGAIN, 0x4045) /* Frequency Estimator Bandwidth */
+SFRX(AX5051_FREQUENCYGAIN2, 0x4046) /* Frequency Estimator Bandwidth 2 */
+SFRX(AX5051_FSKDEV0, 0x4027) /* FSK Deviation 0 */
+SFRX(AX5051_FSKDEV1, 0x4026) /* FSK Deviation 1 */
+SFRX(AX5051_FSKDEV2, 0x4025) /* FSK Deviation 2 */
+SFRX(AX5051_IFFREQHI, 0x4028) /* IF Frequency Low */
+SFRX(AX5051_IFFREQLO, 0x4029) /* IF Frequency High */
+SFRX(AX5051_IFMODE, 0x4008) /* Interface Mode */
+SFRX(AX5051_IRQINVERSION, 0x400F) /* IRQ Inversion */
+SFRX(AX5051_IRQMASK, 0x4006) /* IRQ Mask */
+SFRX(AX5051_IRQREQUEST, 0x4007) /* IRQ Request */
+SFRX(AX5051_MODULATION, 0x4010) /* Modulation */
+SFRX(AX5051_MODULATORMISC, 0x4034) /* Modulator Miscellaneous Control */
+SFRX(AX5051_PHASEGAIN, 0x4044) /* Phase Estimator Bandwidth */
+SFRX(AX5051_PINCFG1, 0x400C) /* Pin Configuration 1 */
+SFRX(AX5051_PINCFG2, 0x400D) /* Pin Configuration 2 */
+SFRX(AX5051_PINCFG3, 0x400E) /* Pin Configuration 3 */
+SFRX(AX5051_PLLLOOP, 0x402C) /* PLL Loop Filter */
+SFRX(AX5051_PLLRANGING, 0x402D) /* PLL Autoranging Control */
+SFRX(AX5051_PLLRNGCLK, 0x402E) /* PLL Autoranging Clock */
+SFRX(AX5051_PLLVCOI, 0x4072) /* PLL VCO Current */
+SFRX(AX5051_PWRMODE, 0x4002) /* Power Mode */
+SFRX(AX5051_REF, 0x407C) /* Reference */
+SFRX(AX5051_RFMISC, 0x407A) /* RF Miscellaneous Control */
+SFRX(AX5051_RXMISC, 0x407D) /* Receiver Miscellaneous Control */
+SFRX(AX5051_SCRATCH, 0x4001) /* Scratch */
+SFRX(AX5051_SILICONREVISION, 0x4000) /* Silicon Revision */
+SFRX(AX5051_TIMINGGAINHI, 0x4042) /* Timing Estimator Bandwidth High */
+SFRX(AX5051_TIMINGGAINLO, 0x4043) /* Timing Estimator Bandwidth Low */
+SFRX(AX5051_TRKAMPLITUDEHI, 0x4048) /* Amplitude Tracking High */
+SFRX(AX5051_TRKAMPLITUDELO, 0x4049) /* Amplitude Tracking Low */
+SFRX(AX5051_TRKFREQHI, 0x404C) /* Frequency Tracking High */
+SFRX(AX5051_TRKFREQLO, 0x404D) /* Frequency Tracking Low */
+SFRX(AX5051_TRKPHASEHI, 0x404A) /* Phase Tracking High */
+SFRX(AX5051_TRKPHASELO, 0x404B) /* Phase Tracking Low */
+SFRX(AX5051_TXBITRATEHI, 0x4031) /* Transmitter Bitrate High */
+SFRX(AX5051_TXBITRATELO, 0x4033) /* Transmitter Bitrate Low */
+SFRX(AX5051_TXBITRATEMID, 0x4032) /* Transmitter Bitrate Middle */
+SFRX(AX5051_TXDSPMODE, 0x400A) /* Transmit DSP Mode */
+SFRX(AX5051_TXPWR, 0x4030) /* Transmit Power */
+SFRX(AX5051_VREG, 0x401B) /* Voltage Regulator */
+SFRX(AX5051_XTALCAP, 0x404F) /* Crystal Oscillator Load Capacitance */
+SFRX(AX5051_XTALOSC, 0x4003) /* Crystal Oscillator Control */
+
+/* Radio Registers, X Address Space, Non-Blocking Version */
+
+SFRX(AX5051_ADCMISCNB, 0x5038) /* ADC Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_AGCATTACKNB, 0x503A) /* AGC Attack Speed, Non-Blocking */
+SFRX(AX5051_AGCCOUNTERNB, 0x503C) /* AGC Counter, Non-Blocking */
+SFRX(AX5051_AGCDECAYNB, 0x503B) /* AGC Decay Speed, Non-Blocking */
+SFRX(AX5051_AGCTARGETNB, 0x5039) /* AGC Target Value, Non-Blocking */
+SFRX(AX5051_AMPLITUDEGAINNB, 0x5047) /* Amplitude Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_CICDECHINB, 0x503E) /* Decimation Factor High, Non-Blocking */
+SFRX(AX5051_CICDECLONB, 0x503F) /* Decimation Factor Low, Non-Blocking */
+SFRX(AX5051_CICSHIFTNB, 0x503D) /* Decimation Filter Attenuation, Non-Blocking */
+SFRX(AX5051_CRCINIT0NB, 0x5017) /* CRC Initial Value 0, Non-Blocking */
+SFRX(AX5051_CRCINIT1NB, 0x5016) /* CRC Initial Value 1, Non-Blocking */
+SFRX(AX5051_CRCINIT2NB, 0x5015) /* CRC Initial Value 2, Non-Blocking */
+SFRX(AX5051_CRCINIT3NB, 0x5014) /* CRC Initial Value 3, Non-Blocking */
+SFRX(AX5051_DATARATEHINB, 0x5040) /* Datarate High, Non-Blocking */
+SFRX(AX5051_DATARATELONB, 0x5041) /* Datarate Low, Non-Blocking */
+SFRX(AX5051_DSPMODENB, 0x5009) /* DSP Mode Interface Control, Non-Blocking */
+SFRX(AX5051_ENCODINGNB, 0x5011) /* Encoding, Non-Blocking */
+SFRX(AX5051_FECNB, 0x5018) /* Forward Error Correction, Non-Blocking */
+SFRX(AX5051_FECMEMNB, 0x506F) /* Forward Error Correction Memory, Non-Blocking */
+SFRX(AX5051_FECSTATUSNB, 0x501A) /* Forward Error Correction Status, Non-Blocking */
+SFRX(AX5051_FECSYNCNB, 0x5019) /* Forward Error Correction Sync Threshold, Non-Blocking */
+SFRX(AX5051_FIFOCONTROLNB, 0x5004) /* FIFO Control, Non-Blocking */
+SFRX(AX5051_FIFOCONTROL2NB, 0x5037) /* FIFO Control 2, Non-Blocking */
+SFRX(AX5051_FIFOCOUNTNB, 0x5035) /* FIFO Count, Non-Blocking */
+SFRX(AX5051_FIFODATANB, 0x5005) /* FIFO Data, Non-Blocking */
+SFRX(AX5051_FIFOTHRESHNB, 0x5036) /* FIFO Threshold, Non-Blocking */
+SFRX(AX5051_FRAMINGNB, 0x5012) /* Framing Mode, Non-Blocking */
+SFRX(AX5051_FREQ0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5051_FREQ1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5051_FREQ2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5051_FREQ3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5051_FREQA0NB, 0x5023) /* Frequency 0, Non-Blocking */
+SFRX(AX5051_FREQA1NB, 0x5022) /* Frequency 1, Non-Blocking */
+SFRX(AX5051_FREQA2NB, 0x5021) /* Frequency 2, Non-Blocking */
+SFRX(AX5051_FREQA3NB, 0x5020) /* Frequency 3, Non-Blocking */
+SFRX(AX5051_FREQUENCYGAINNB, 0x5045) /* Frequency Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_FREQUENCYGAIN2NB, 0x5046) /* Frequency Estimator Bandwidth 2, Non-Blocking */
+SFRX(AX5051_FSKDEV0NB, 0x5027) /* FSK Deviation 0, Non-Blocking */
+SFRX(AX5051_FSKDEV1NB, 0x5026) /* FSK Deviation 1, Non-Blocking */
+SFRX(AX5051_FSKDEV2NB, 0x5025) /* FSK Deviation 2, Non-Blocking */
+SFRX(AX5051_IFFREQHINB, 0x5028) /* IF Frequency Low, Non-Blocking */
+SFRX(AX5051_IFFREQLONB, 0x5029) /* IF Frequency High, Non-Blocking */
+SFRX(AX5051_IFMODENB, 0x5008) /* Interface Mode, Non-Blocking */
+SFRX(AX5051_IRQINVERSIONNB, 0x500F) /* IRQ Inversion, Non-Blocking */
+SFRX(AX5051_IRQMASKNB, 0x5006) /* IRQ Mask, Non-Blocking */
+SFRX(AX5051_IRQREQUESTNB, 0x5007) /* IRQ Request, Non-Blocking */
+SFRX(AX5051_MODULATIONNB, 0x5010) /* Modulation, Non-Blocking */
+SFRX(AX5051_MODULATORMISCNB, 0x5034) /* Modulator Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_PHASEGAINNB, 0x5044) /* Phase Estimator Bandwidth, Non-Blocking */
+SFRX(AX5051_PINCFG1NB, 0x500C) /* Pin Configuration 1, Non-Blocking */
+SFRX(AX5051_PINCFG2NB, 0x500D) /* Pin Configuration 2, Non-Blocking */
+SFRX(AX5051_PINCFG3NB, 0x500E) /* Pin Configuration 3, Non-Blocking */
+SFRX(AX5051_PLLLOOPNB, 0x502C) /* PLL Loop Filter, Non-Blocking */
+SFRX(AX5051_PLLRANGINGNB, 0x502D) /* PLL Autoranging Control, Non-Blocking */
+SFRX(AX5051_PLLRNGCLKNB, 0x502E) /* PLL Autoranging Clock, Non-Blocking */
+SFRX(AX5051_PLLVCOINB, 0x5072) /* PLL VCO Current, Non-Blocking */
+SFRX(AX5051_PWRMODENB, 0x5002) /* Power Mode, Non-Blocking */
+SFRX(AX5051_REFNB, 0x507C) /* Reference, Non-Blocking */
+SFRX(AX5051_RFMISCNB, 0x507A) /* RF Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_RXMISCNB, 0x507D) /* Receiver Miscellaneous Control, Non-Blocking */
+SFRX(AX5051_SCRATCHNB, 0x5001) /* Scratch, Non-Blocking */
+SFRX(AX5051_SILICONREVISIONNB, 0x5000) /* Silicon Revision, Non-Blocking */
+SFRX(AX5051_TIMINGGAINHINB, 0x5042) /* Timing Estimator Bandwidth High, Non-Blocking */
+SFRX(AX5051_TIMINGGAINLONB, 0x5043) /* Timing Estimator Bandwidth Low, Non-Blocking */
+SFRX(AX5051_TRKAMPLITUDEHINB, 0x5048) /* Amplitude Tracking High, Non-Blocking */
+SFRX(AX5051_TRKAMPLITUDELONB, 0x5049) /* Amplitude Tracking Low, Non-Blocking */
+SFRX(AX5051_TRKFREQHINB, 0x504C) /* Frequency Tracking High, Non-Blocking */
+SFRX(AX5051_TRKFREQLONB, 0x504D) /* Frequency Tracking Low, Non-Blocking */
+SFRX(AX5051_TRKPHASEHINB, 0x504A) /* Phase Tracking High, Non-Blocking */
+SFRX(AX5051_TRKPHASELONB, 0x504B) /* Phase Tracking Low, Non-Blocking */
+SFRX(AX5051_TXBITRATEHINB, 0x5031) /* Transmitter Bitrate High, Non-Blocking */
+SFRX(AX5051_TXBITRATELONB, 0x5033) /* Transmitter Bitrate Low, Non-Blocking */
+SFRX(AX5051_TXBITRATEMIDNB, 0x5032) /* Transmitter Bitrate Middle, Non-Blocking */
+SFRX(AX5051_TXDSPMODENB, 0x500A) /* Transmit DSP Mode, Non-Blocking */
+SFRX(AX5051_TXPWRNB, 0x5030) /* Transmit Power, Non-Blocking */
+SFRX(AX5051_VREGNB, 0x501B) /* Voltage Regulator, Non-Blocking */
+SFRX(AX5051_XTALCAPNB, 0x504F) /* Crystal Oscillator Load Capacitance, Non-Blocking */
+SFRX(AX5051_XTALOSCNB, 0x5003) /* Crystal Oscillator Control, Non-Blocking */
+
+/* Alternate Names */
+
+#define AX5051_AMPLGAIN AX5051_AMPLITUDEGAIN
+#define AX5051_FREQGAIN AX5051_FREQUENCYGAIN
+#define AX5051_FREQGAIN2 AX5051_FREQUENCYGAIN2
+#define AX5051_MODMISC AX5051_MODULATORMISC
+#define AX5051_TMGGAINHI AX5051_TIMINGGAINHI
+#define AX5051_TMGGAINLO AX5051_TIMINGGAINLO
+#define AX5051_TXRATEHI AX5051_TXBITRATEHI
+#define AX5051_TXRATELO AX5051_TXBITRATELO
+#define AX5051_TXRATEMID AX5051_TXBITRATEMID
+
+#define AX5051_AMPLGAINNB AX5051_AMPLITUDEGAINNB
+#define AX5051_FREQGAINNB AX5051_FREQUENCYGAINNB
+#define AX5051_FREQGAIN2NB AX5051_FREQUENCYGAIN2NB
+#define AX5051_MODMISCNB AX5051_MODULATORMISCNB
+#define AX5051_TMGGAINHINB AX5051_TIMINGGAINHINB
+#define AX5051_TMGGAINLONB AX5051_TIMINGGAINLONB
+#define AX5051_TXRATEHINB AX5051_TXBITRATEHINB
+#define AX5051_TXRATELONB AX5051_TXBITRATELONB
+#define AX5051_TXRATEMIDNB AX5051_TXBITRATEMIDNB
+
+#endif /* AX8052F151_H */
diff --git a/libs/libmf/source/ax8052regaddr.h b/libs/libmf/source/ax8052regaddr.h
new file mode 100644
index 00000000..ff63906b
--- /dev/null
+++ b/libs/libmf/source/ax8052regaddr.h
@@ -0,0 +1,366 @@
+/*-------------------------------------------------------------------------
+ ax8052regaddr.h - Register Address Declarations for the Axsem Microfoot Processor Range
+
+ Copyright (C) 2010, 2011, 2012 Axsem AG
+ Author: Thomas Sailer, thomas.sailer@axsem.com
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+
+#ifndef AX8052REGADDR_H
+#define AX8052REGADDR_H
+
+/* SFR Address Space */
+
+#define SFRADDR_ACC 0xE0 /* Accumulator */
+#define SFRADDR_B 0xF0 /* B Register */
+#define SFRADDR_DPH 0x83 /* Data Pointer 0 High Byte */
+#define SFRADDR_DPH1 0x85 /* Data Pointer 1 High Byte */
+#define SFRADDR_DPL 0x82 /* Data Pointer 0 Low Byte */
+#define SFRADDR_DPL1 0x84 /* Data Pointer 1 Low Byte */
+#define SFRADDR_DPS 0x86 /* Data Pointer Select */
+#define SFRADDR_E2IE 0xA0 /* 2nd Extended Interrupt Enable */
+#define SFRADDR_E2IP 0xC0 /* 2nd Extended Interrupt Priority */
+#define SFRADDR_EIE 0x98 /* Extended Interrupt Enable */
+#define SFRADDR_EIP 0xB0 /* Extended Interrupt Priority */
+#define SFRADDR_IE 0xA8 /* Interrupt Enable */
+#define SFRADDR_IP 0xB8 /* Interrupt Priority */
+#define SFRADDR_PCON 0x87 /* Power Mode Control */
+#define SFRADDR_PSW 0xD0 /* Program Status Word */
+#define SFRADDR_SP 0x81 /* Stack Pointer */
+#define SFRADDR_WBTEST 0x8F /* Debug Breakpoint Register */
+#define SFRADDR_XPAGE 0xD9 /* Memory Page Select */
+#define SFRADDR_ADCCH0CONFIG 0xCA /* ADC Channel 0 Configuration */
+#define SFRADDR_ADCCH1CONFIG 0xCB /* ADC Channel 1 Configuration */
+#define SFRADDR_ADCCH2CONFIG 0xD2 /* ADC Channel 2 Configuration */
+#define SFRADDR_ADCCH3CONFIG 0xD3 /* ADC Channel 3 Configuration */
+#define SFRADDR_ADCCLKSRC 0xD1 /* ADC Clock Source */
+#define SFRADDR_ADCCONV 0xC9 /* ADC Conversion Source */
+#define SFRADDR_ANALOGCOMP 0xE1 /* Analog Comparators */
+#define SFRADDR_CLKCON 0xC6 /* Clock Control */
+#define SFRADDR_CLKSTAT 0xC7 /* Clock Status */
+#define SFRADDR_CODECONFIG 0x97 /* Code Space Configuration */
+#define SFRADDR_DBGLNKBUF 0xE3 /* Debug Link Buffer */
+#define SFRADDR_DBGLNKSTAT 0xE2 /* Debug Link Status */
+#define SFRADDR_DIRA 0x89 /* Port A Direction */
+#define SFRADDR_DIRB 0x8A /* Port B Direction */
+#define SFRADDR_DIRC 0x8B /* Port C Direction */
+#define SFRADDR_DIRR 0x8E /* Port R Direction */
+#define SFRADDR_PINA 0xC8 /* Port A Input */
+#define SFRADDR_PINB 0xE8 /* Port B Input */
+#define SFRADDR_PINC 0xF8 /* Port C Input */
+#define SFRADDR_PINR 0x8D /* Port R Input */
+#define SFRADDR_PORTA 0x80 /* Port A Output */
+#define SFRADDR_PORTB 0x88 /* Port B Output */
+#define SFRADDR_PORTC 0x90 /* Port C Output */
+#define SFRADDR_PORTR 0x8C /* Port R Output */
+#define SFRADDR_IC0CAPT0 0xCE /* Input Capture 0 Low Byte */
+#define SFRADDR_IC0CAPT1 0xCF /* Input Capture 0 High Byte */
+#define SFRADDR_IC0MODE 0xCC /* Input Capture 0 Mode */
+#define SFRADDR_IC0STATUS 0xCD /* Input Capture 0 Status */
+#define SFRADDR_IC1CAPT0 0xD6 /* Input Capture 1 Low Byte */
+#define SFRADDR_IC1CAPT1 0xD7 /* Input Capture 1 High Byte */
+#define SFRADDR_IC1MODE 0xD4 /* Input Capture 1 Mode */
+#define SFRADDR_IC1STATUS 0xD5 /* Input Capture 1 Status */
+#define SFRADDR_NVADDR0 0x92 /* Non-Volatile Memory Address Low Byte */
+#define SFRADDR_NVADDR1 0x93 /* Non-Volatile Memory Address High Byte */
+#define SFRADDR_NVDATA0 0x94 /* Non-Volatile Memory Data Low Byte */
+#define SFRADDR_NVDATA1 0x95 /* Non-Volatile Memory Data High Byte */
+#define SFRADDR_NVKEY 0x96 /* Non-Volatile Memory Write/Erase Key */
+#define SFRADDR_NVSTATUS 0x91 /* Non-Volatile Memory Command / Status */
+#define SFRADDR_OC0COMP0 0xBC /* Output Compare 0 Low Byte */
+#define SFRADDR_OC0COMP1 0xBD /* Output Compare 0 High Byte */
+#define SFRADDR_OC0MODE 0xB9 /* Output Compare 0 Mode */
+#define SFRADDR_OC0PIN 0xBA /* Output Compare 0 Pin Configuration */
+#define SFRADDR_OC0STATUS 0xBB /* Output Compare 0 Status */
+#define SFRADDR_OC1COMP0 0xC4 /* Output Compare 1 Low Byte */
+#define SFRADDR_OC1COMP1 0xC5 /* Output Compare 1 High Byte */
+#define SFRADDR_OC1MODE 0xC1 /* Output Compare 1 Mode */
+#define SFRADDR_OC1PIN 0xC2 /* Output Compare 1 Pin Configuration */
+#define SFRADDR_OC1STATUS 0xC3 /* Output Compare 1 Status */
+#define SFRADDR_RADIOACC 0xB1 /* Radio Controller Access Mode */
+#define SFRADDR_RADIOADDR0 0xB3 /* Radio Register Address Low Byte */
+#define SFRADDR_RADIOADDR1 0xB2 /* Radio Register Address High Byte */
+#define SFRADDR_RADIODATA0 0xB7 /* Radio Register Data 0 */
+#define SFRADDR_RADIODATA1 0xB6 /* Radio Register Data 1 */
+#define SFRADDR_RADIODATA2 0xB5 /* Radio Register Data 2 */
+#define SFRADDR_RADIODATA3 0xB4 /* Radio Register Data 3 */
+#define SFRADDR_RADIOSTAT0 0xBE /* Radio Access Status Low Byte */
+#define SFRADDR_RADIOSTAT1 0xBF /* Radio Access Status High Byte */
+#define SFRADDR_SPCLKSRC 0xDF /* SPI Clock Source */
+#define SFRADDR_SPMODE 0xDC /* SPI Mode */
+#define SFRADDR_SPSHREG 0xDE /* SPI Shift Register */
+#define SFRADDR_SPSTATUS 0xDD /* SPI Status */
+#define SFRADDR_T0CLKSRC 0x9A /* Timer 0 Clock Source */
+#define SFRADDR_T0CNT0 0x9C /* Timer 0 Count Low Byte */
+#define SFRADDR_T0CNT1 0x9D /* Timer 0 Count High Byte */
+#define SFRADDR_T0MODE 0x99 /* Timer 0 Mode */
+#define SFRADDR_T0PERIOD0 0x9E /* Timer 0 Period Low Byte */
+#define SFRADDR_T0PERIOD1 0x9F /* Timer 0 Period High Byte */
+#define SFRADDR_T0STATUS 0x9B /* Timer 0 Status */
+#define SFRADDR_T1CLKSRC 0xA2 /* Timer 1 Clock Source */
+#define SFRADDR_T1CNT0 0xA4 /* Timer 1 Count Low Byte */
+#define SFRADDR_T1CNT1 0xA5 /* Timer 1 Count High Byte */
+#define SFRADDR_T1MODE 0xA1 /* Timer 1 Mode */
+#define SFRADDR_T1PERIOD0 0xA6 /* Timer 1 Period Low Byte */
+#define SFRADDR_T1PERIOD1 0xA7 /* Timer 1 Period High Byte */
+#define SFRADDR_T1STATUS 0xA3 /* Timer 1 Status */
+#define SFRADDR_T2CLKSRC 0xAA /* Timer 2 Clock Source */
+#define SFRADDR_T2CNT0 0xAC /* Timer 2 Count Low Byte */
+#define SFRADDR_T2CNT1 0xAD /* Timer 2 Count High Byte */
+#define SFRADDR_T2MODE 0xA9 /* Timer 2 Mode */
+#define SFRADDR_T2PERIOD0 0xAE /* Timer 2 Period Low Byte */
+#define SFRADDR_T2PERIOD1 0xAF /* Timer 2 Period High Byte */
+#define SFRADDR_T2STATUS 0xAB /* Timer 2 Status */
+#define SFRADDR_U0CTRL 0xE4 /* UART 0 Control */
+#define SFRADDR_U0MODE 0xE7 /* UART 0 Mode */
+#define SFRADDR_U0SHREG 0xE6 /* UART 0 Shift Register */
+#define SFRADDR_U0STATUS 0xE5 /* UART 0 Status */
+#define SFRADDR_U1CTRL 0xEC /* UART 1 Control */
+#define SFRADDR_U1MODE 0xEF /* UART 1 Mode */
+#define SFRADDR_U1SHREG 0xEE /* UART 1 Shift Register */
+#define SFRADDR_U1STATUS 0xED /* UART 1 Status */
+#define SFRADDR_WDTCFG 0xDA /* Watchdog Configuration */
+#define SFRADDR_WDTRESET 0xDB /* Watchdog Reset */
+#define SFRADDR_WTCFGA 0xF1 /* Wakeup Timer A Configuration */
+#define SFRADDR_WTCFGB 0xF9 /* Wakeup Timer B Configuration */
+#define SFRADDR_WTCNTA0 0xF2 /* Wakeup Counter A Low Byte */
+#define SFRADDR_WTCNTA1 0xF3 /* Wakeup Counter A High Byte */
+#define SFRADDR_WTCNTB0 0xFA /* Wakeup Counter B Low Byte */
+#define SFRADDR_WTCNTB1 0xFB /* Wakeup Counter B High Byte */
+#define SFRADDR_WTCNTR1 0xEB /* Wakeup Counter High Byte Latch */
+#define SFRADDR_WTEVTA0 0xF4 /* Wakeup Event A Low Byte */
+#define SFRADDR_WTEVTA1 0xF5 /* Wakeup Event A High Byte */
+#define SFRADDR_WTEVTB0 0xF6 /* Wakeup Event B Low Byte */
+#define SFRADDR_WTEVTB1 0xF7 /* Wakeup Event B High Byte */
+#define SFRADDR_WTEVTC0 0xFC /* Wakeup Event C Low Byte */
+#define SFRADDR_WTEVTC1 0xFD /* Wakeup Event C High Byte */
+#define SFRADDR_WTEVTD0 0xFE /* Wakeup Event D Low Byte */
+#define SFRADDR_WTEVTD1 0xFF /* Wakeup Event D High Byte */
+#define SFRADDR_WTIRQEN 0xE9 /* Wakeup Timer Interrupt Enable */
+#define SFRADDR_WTSTAT 0xEA /* Wakeup Timer Status */
+
+/* X Address Space */
+
+
+#define SFRXADDR_ADCCALG00GAIN0 0x7030 /* ADC Calibration Range 00 Gain Low Byte */
+#define SFRXADDR_ADCCALG00GAIN1 0x7031 /* ADC Calibration Range 00 Gain High Byte */
+#define SFRXADDR_ADCCALG01GAIN0 0x7032 /* ADC Calibration Range 01 Gain Low Byte */
+#define SFRXADDR_ADCCALG01GAIN1 0x7033 /* ADC Calibration Range 01 Gain High Byte */
+#define SFRXADDR_ADCCALG10GAIN0 0x7034 /* ADC Calibration Range 10 Gain Low Byte */
+#define SFRXADDR_ADCCALG10GAIN1 0x7035 /* ADC Calibration Range 10 Gain High Byte */
+#define SFRXADDR_ADCCALTEMPGAIN0 0x7038 /* ADC Calibration Temperature Gain Low Byte */
+#define SFRXADDR_ADCCALTEMPGAIN1 0x7039 /* ADC Calibration Temperature Gain High Byte */
+#define SFRXADDR_ADCCALTEMPOFFS0 0x703A /* ADC Calibration Temperature Offset Low Byte */
+#define SFRXADDR_ADCCALTEMPOFFS1 0x703B /* ADC Calibration Temperature Offset High Byte */
+#define SFRXADDR_ADCCH0VAL0 0x7020 /* ADC Channel 0 Low Byte */
+#define SFRXADDR_ADCCH0VAL1 0x7021 /* ADC Channel 0 High Byte */
+#define SFRXADDR_ADCCH1VAL0 0x7022 /* ADC Channel 1 Low Byte */
+#define SFRXADDR_ADCCH1VAL1 0x7023 /* ADC Channel 1 High Byte */
+#define SFRXADDR_ADCCH2VAL0 0x7024 /* ADC Channel 2 Low Byte */
+#define SFRXADDR_ADCCH2VAL1 0x7025 /* ADC Channel 2 High Byte */
+#define SFRXADDR_ADCCH3VAL0 0x7026 /* ADC Channel 3 Low Byte */
+#define SFRXADDR_ADCCH3VAL1 0x7027 /* ADC Channel 3 High Byte */
+#define SFRXADDR_ADCTUNE0 0x7028 /* ADC Tuning 0 */
+#define SFRXADDR_ADCTUNE1 0x7029 /* ADC Tuning 1 */
+#define SFRXADDR_ADCTUNE2 0x702A /* ADC Tuning 2 */
+#define SFRXADDR_CLOCKGATE 0x7F1B /* Clock Gating */
+#define SFRXADDR_DMA0ADDR0 0x7010 /* DMA Channel 0 Address Low Byte */
+#define SFRXADDR_DMA0ADDR1 0x7011 /* DMA Channel 0 Address High Byte */
+#define SFRXADDR_DMA0CONFIG 0x7014 /* DMA Channel 0 Configuration */
+#define SFRXADDR_DMA1ADDR0 0x7012 /* DMA Channel 1 Address Low Byte */
+#define SFRXADDR_DMA1ADDR1 0x7013 /* DMA Channel 1 Address High Byte */
+#define SFRXADDR_DMA1CONFIG 0x7015 /* DMA Channel 1 Configuration */
+#define SFRXADDR_FRCOSCCONFIG 0x7070 /* Fast RC Oscillator Calibration Configuration */
+#define SFRXADDR_FRCOSCCTRL 0x7071 /* Fast RC Oscillator Control */
+#define SFRXADDR_FRCOSCFREQ0 0x7076 /* Fast RC Oscillator Frequency Tuning Low Byte */
+#define SFRXADDR_FRCOSCFREQ1 0x7077 /* Fast RC Oscillator Frequency Tuning High Byte */
+#define SFRXADDR_FRCOSCKFILT0 0x7072 /* Fast RC Oscillator Calibration Filter Constant Low Byte */
+#define SFRXADDR_FRCOSCKFILT1 0x7073 /* Fast RC Oscillator Calibration Filter Constant High Byte */
+#define SFRXADDR_FRCOSCPER0 0x7078 /* Fast RC Oscillator Period Low Byte */
+#define SFRXADDR_FRCOSCPER1 0x7079 /* Fast RC Oscillator Period High Byte */
+#define SFRXADDR_FRCOSCREF0 0x7074 /* Fast RC Oscillator Reference Frequency Low Byte */
+#define SFRXADDR_FRCOSCREF1 0x7075 /* Fast RC Oscillator Reference Frequency High Byte */
+#define SFRXADDR_ANALOGA 0x7007 /* Port A Analog Mode */
+#define SFRXADDR_GPIOENABLE 0x700C /* GPIO Port Enable */
+#define SFRXADDR_EXTIRQ 0x7003 /* External IRQ Configuration */
+#define SFRXADDR_INTCHGA 0x7000 /* Port A Interrupt on Change */
+#define SFRXADDR_INTCHGB 0x7001 /* Port B Interrupt on Change */
+#define SFRXADDR_INTCHGC 0x7002 /* Port C Interrupt on Change */
+#define SFRXADDR_PALTA 0x7008 /* Port A Alternate Function */
+#define SFRXADDR_PALTB 0x7009 /* Port B Alternate Function */
+#define SFRXADDR_PALTC 0x700A /* Port C Alternate Function */
+#define SFRXADDR_PALTRADIO 0x7046 /* Port Radio Alternate Function */
+#define SFRXADDR_PINCHGA 0x7004 /* Port A Level Change */
+#define SFRXADDR_PINCHGB 0x7005 /* Port B Level Change */
+#define SFRXADDR_PINCHGC 0x7006 /* Port C Level Change */
+#define SFRXADDR_PINSEL 0x700B /* Port Input Selection */
+#define SFRXADDR_LPOSCCONFIG 0x7060 /* Low Power Oscillator Calibration Configuration */
+#define SFRXADDR_LPOSCFREQ0 0x7066 /* Low Power Oscillator Frequency Tuning Low Byte */
+#define SFRXADDR_LPOSCFREQ1 0x7067 /* Low Power Oscillator Frequency Tuning High Byte */
+#define SFRXADDR_LPOSCKFILT0 0x7062 /* Low Power Oscillator Calibration Filter Constant Low Byte */
+#define SFRXADDR_LPOSCKFILT1 0x7063 /* Low Power Oscillator Calibration Filter Constant High Byte */
+#define SFRXADDR_LPOSCPER0 0x7068 /* Low Power Oscillator Period Low Byte */
+#define SFRXADDR_LPOSCPER1 0x7069 /* Low Power Oscillator Period High Byte */
+#define SFRXADDR_LPOSCREF0 0x7064 /* Low Power Oscillator Reference Frequency Low Byte */
+#define SFRXADDR_LPOSCREF1 0x7065 /* Low Power Oscillator Reference Frequency High Byte */
+#define SFRXADDR_LPXOSCGM 0x7054 /* Low Power Crystal Oscillator Transconductance */
+#define SFRXADDR_MISCCTRL 0x7F01 /* Miscellaneous Control */
+#define SFRXADDR_OSCCALIB 0x7053 /* Oscillator Calibration Interrupt / Status */
+#define SFRXADDR_OSCFORCERUN 0x7050 /* Oscillator Run Force */
+#define SFRXADDR_OSCREADY 0x7052 /* Oscillator Ready Status */
+#define SFRXADDR_OSCRUN 0x7051 /* Oscillator Run Status */
+#define SFRXADDR_POWCTRL0 0x7F10 /* Power Control 0 */
+#define SFRXADDR_POWCTRL1 0x7F11 /* Power Control 1 */
+#define SFRXADDR_POWCTRL2 0x7F12 /* Power Control 2 */
+#define SFRXADDR_RADIOFDATAADDR0 0x7040 /* Radio FIFO Data Register Address Low Byte */
+#define SFRXADDR_RADIOFDATAADDR1 0x7041 /* Radio FIFO Data Register Address High Byte */
+#define SFRXADDR_RADIOFSTATADDR0 0x7042 /* Radio FIFO Status Register Address Low Byte */
+#define SFRXADDR_RADIOFSTATADDR1 0x7043 /* Radio FIFO Status Register Address High Byte */
+#define SFRXADDR_RADIOMUX 0x7044 /* Radio Multiplexer Control */
+#define SFRXADDR_SCRATCH0 0x7084 /* Scratch Register 0 */
+#define SFRXADDR_SCRATCH1 0x7085 /* Scratch Register 1 */
+#define SFRXADDR_SCRATCH2 0x7086 /* Scratch Register 2 */
+#define SFRXADDR_SCRATCH3 0x7087 /* Scratch Register 3 */
+#define SFRXADDR_SILICONREV 0x7F00 /* Silicon Revision */
+#define SFRXADDR_XTALAMPL 0x7F19 /* Crystal Oscillator Amplitude Control */
+#define SFRXADDR_XTALOSC 0x7F18 /* Crystal Oscillator Configuration */
+#define SFRXADDR_XTALREADY 0x7F1A /* Crystal Oscillator Ready Mode */
+
+/* X Address Space aliases of SFR Address Space Registers */
+
+#define SFRXADDR_XIE 0x3FA8 /* Interrupt Enable */
+#define SFRXADDR_XIP 0x3FB8 /* Interrupt Priority */
+#define SFRXADDR_XPCON 0x3F87 /* Power Mode Control */
+#define SFRXADDR_XADCCH0CONFIG 0x3FCA /* ADC Channel 0 Configuration */
+#define SFRXADDR_XADCCH1CONFIG 0x3FCB /* ADC Channel 1 Configuration */
+#define SFRXADDR_XADCCH2CONFIG 0x3FD2 /* ADC Channel 2 Configuration */
+#define SFRXADDR_XADCCH3CONFIG 0x3FD3 /* ADC Channel 3 Configuration */
+#define SFRXADDR_XADCCLKSRC 0x3FD1 /* ADC Clock Source */
+#define SFRXADDR_XADCCONV 0x3FC9 /* ADC Conversion Source */
+#define SFRXADDR_XANALOGCOMP 0x3FE1 /* Analog Comparators */
+#define SFRXADDR_XCLKCON 0x3FC6 /* Clock Control */
+#define SFRXADDR_XCLKSTAT 0x3FC7 /* Clock Status */
+#define SFRXADDR_XCODECONFIG 0x3F97 /* Code Space Configuration */
+#define SFRXADDR_XDBGLNKBUF 0x3FE3 /* Debug Link Buffer */
+#define SFRXADDR_XDBGLNKSTAT 0x3FE2 /* Debug Link Status */
+#define SFRXADDR_XDIRA 0x3F89 /* Port A Direction */
+#define SFRXADDR_XDIRB 0x3F8A /* Port B Direction */
+#define SFRXADDR_XDIRC 0x3F8B /* Port C Direction */
+#define SFRXADDR_XDIRR 0x3F8E /* Port R Direction */
+#define SFRXADDR_XPINA 0x3FC8 /* Port A Input */
+#define SFRXADDR_XPINB 0x3FE8 /* Port B Input */
+#define SFRXADDR_XPINC 0x3FF8 /* Port C Input */
+#define SFRXADDR_XPINR 0x3F8D /* Port R Input */
+#define SFRXADDR_XPORTA 0x3F80 /* Port A Output */
+#define SFRXADDR_XPORTB 0x3F88 /* Port B Output */
+#define SFRXADDR_XPORTC 0x3F90 /* Port C Output */
+#define SFRXADDR_XPORTR 0x3F8C /* Port R Output */
+#define SFRXADDR_XIC0CAPT0 0x3FCE /* Input Capture 0 Low Byte */
+#define SFRXADDR_XIC0CAPT1 0x3FCF /* Input Capture 0 High Byte */
+#define SFRXADDR_XIC0MODE 0x3FCC /* Input Capture 0 Mode */
+#define SFRXADDR_XIC0STATUS 0x3FCD /* Input Capture 0 Status */
+#define SFRXADDR_XIC1CAPT0 0x3FD6 /* Input Capture 1 Low Byte */
+#define SFRXADDR_XIC1CAPT1 0x3FD7 /* Input Capture 1 High Byte */
+#define SFRXADDR_XIC1MODE 0x3FD4 /* Input Capture 1 Mode */
+#define SFRXADDR_XIC1STATUS 0x3FD5 /* Input Capture 1 Status */
+#define SFRXADDR_XNVADDR0 0x3F92 /* Non-Volatile Memory Address Low Byte */
+#define SFRXADDR_XNVADDR1 0x3F93 /* Non-Volatile Memory Address High Byte */
+#define SFRXADDR_XNVDATA0 0x3F94 /* Non-Volatile Memory Data Low Byte */
+#define SFRXADDR_XNVDATA1 0x3F95 /* Non-Volatile Memory Data High Byte */
+#define SFRXADDR_XNVKEY 0x3F96 /* Non-Volatile Memory Write/Erase Key */
+#define SFRXADDR_XNVSTATUS 0x3F91 /* Non-Volatile Memory Command / Status */
+#define SFRXADDR_XOC0COMP0 0x3FBC /* Output Compare 0 Low Byte */
+#define SFRXADDR_XOC0COMP1 0x3FBD /* Output Compare 0 High Byte */
+#define SFRXADDR_XOC0MODE 0x3FB9 /* Output Compare 0 Mode */
+#define SFRXADDR_XOC0PIN 0x3FBA /* Output Compare 0 Pin Configuration */
+#define SFRXADDR_XOC0STATUS 0x3FBB /* Output Compare 0 Status */
+#define SFRXADDR_XOC1COMP0 0x3FC4 /* Output Compare 1 Low Byte */
+#define SFRXADDR_XOC1COMP1 0x3FC5 /* Output Compare 1 High Byte */
+#define SFRXADDR_XOC1MODE 0x3FC1 /* Output Compare 1 Mode */
+#define SFRXADDR_XOC1PIN 0x3FC2 /* Output Compare 1 Pin Configuration */
+#define SFRXADDR_XOC1STATUS 0x3FC3 /* Output Compare 1 Status */
+#define SFRXADDR_XRADIOACC 0x3FB1 /* Radio Controller Access Mode */
+#define SFRXADDR_XRADIOADDR0 0x3FB3 /* Radio Register Address Low Byte */
+#define SFRXADDR_XRADIOADDR1 0x3FB2 /* Radio Register Address High Byte */
+#define SFRXADDR_XRADIODATA0 0x3FB7 /* Radio Register Data 0 */
+#define SFRXADDR_XRADIODATA1 0x3FB6 /* Radio Register Data 1 */
+#define SFRXADDR_XRADIODATA2 0x3FB5 /* Radio Register Data 2 */
+#define SFRXADDR_XRADIODATA3 0x3FB4 /* Radio Register Data 3 */
+#define SFRXADDR_XRADIOSTAT0 0x3FBE /* Radio Access Status Low Byte */
+#define SFRXADDR_XRADIOSTAT1 0x3FBF /* Radio Access Status High Byte */
+#define SFRXADDR_XSPCLKSRC 0x3FDF /* SPI Clock Source */
+#define SFRXADDR_XSPMODE 0x3FDC /* SPI Mode */
+#define SFRXADDR_XSPSHREG 0x3FDE /* SPI Shift Register */
+#define SFRXADDR_XSPSTATUS 0x3FDD /* SPI Status */
+#define SFRXADDR_XT0CLKSRC 0x3F9A /* Timer 0 Clock Source */
+#define SFRXADDR_XT0CNT0 0x3F9C /* Timer 0 Count Low Byte */
+#define SFRXADDR_XT0CNT1 0x3F9D /* Timer 0 Count High Byte */
+#define SFRXADDR_XT0MODE 0x3F99 /* Timer 0 Mode */
+#define SFRXADDR_XT0PERIOD0 0x3F9E /* Timer 0 Period Low Byte */
+#define SFRXADDR_XT0PERIOD1 0x3F9F /* Timer 0 Period High Byte */
+#define SFRXADDR_XT0STATUS 0x3F9B /* Timer 0 Status */
+#define SFRXADDR_XT1CLKSRC 0x3FA2 /* Timer 1 Clock Source */
+#define SFRXADDR_XT1CNT0 0x3FA4 /* Timer 1 Count Low Byte */
+#define SFRXADDR_XT1CNT1 0x3FA5 /* Timer 1 Count High Byte */
+#define SFRXADDR_XT1MODE 0x3FA1 /* Timer 1 Mode */
+#define SFRXADDR_XT1PERIOD0 0x3FA6 /* Timer 1 Period Low Byte */
+#define SFRXADDR_XT1PERIOD1 0x3FA7 /* Timer 1 Period High Byte */
+#define SFRXADDR_XT1STATUS 0x3FA3 /* Timer 1 Status */
+#define SFRXADDR_XT2CLKSRC 0x3FAA /* Timer 2 Clock Source */
+#define SFRXADDR_XT2CNT0 0x3FAC /* Timer 2 Count Low Byte */
+#define SFRXADDR_XT2CNT1 0x3FAD /* Timer 2 Count High Byte */
+#define SFRXADDR_XT2MODE 0x3FA9 /* Timer 2 Mode */
+#define SFRXADDR_XT2PERIOD0 0x3FAE /* Timer 2 Period Low Byte */
+#define SFRXADDR_XT2PERIOD1 0x3FAF /* Timer 2 Period High Byte */
+#define SFRXADDR_XT2STATUS 0x3FAB /* Timer 2 Status */
+#define SFRXADDR_XU0CTRL 0x3FE4 /* UART 0 Control */
+#define SFRXADDR_XU0MODE 0x3FE7 /* UART 0 Mode */
+#define SFRXADDR_XU0SHREG 0x3FE6 /* UART 0 Shift Register */
+#define SFRXADDR_XU0STATUS 0x3FE5 /* UART 0 Status */
+#define SFRXADDR_XU1CTRL 0x3FEC /* UART 1 Control */
+#define SFRXADDR_XU1MODE 0x3FEF /* UART 1 Mode */
+#define SFRXADDR_XU1SHREG 0x3FEE /* UART 1 Shift Register */
+#define SFRXADDR_XU1STATUS 0x3FED /* UART 1 Status */
+#define SFRXADDR_XWDTCFG 0x3FDA /* Watchdog Configuration */
+#define SFRXADDR_XWDTRESET 0x3FDB /* Watchdog Reset */
+#define SFRXADDR_XWTCFGA 0x3FF1 /* Wakeup Timer A Configuration */
+#define SFRXADDR_XWTCFGB 0x3FF9 /* Wakeup Timer B Configuration */
+#define SFRXADDR_XWTCNTA0 0x3FF2 /* Wakeup Counter A Low Byte */
+#define SFRXADDR_XWTCNTA1 0x3FF3 /* Wakeup Counter A High Byte */
+#define SFRXADDR_XWTCNTB0 0x3FFA /* Wakeup Counter B Low Byte */
+#define SFRXADDR_XWTCNTB1 0x3FFB /* Wakeup Counter B High Byte */
+#define SFRXADDR_XWTCNTR1 0x3FEB /* Wakeup Counter High Byte Latch */
+#define SFRXADDR_XWTEVTA0 0x3FF4 /* Wakeup Event A Low Byte */
+#define SFRXADDR_XWTEVTA1 0x3FF5 /* Wakeup Event A High Byte */
+#define SFRXADDR_XWTEVTB0 0x3FF6 /* Wakeup Event B Low Byte */
+#define SFRXADDR_XWTEVTB1 0x3FF7 /* Wakeup Event B High Byte */
+#define SFRXADDR_XWTEVTC0 0x3FFC /* Wakeup Event C Low Byte */
+#define SFRXADDR_XWTEVTC1 0x3FFD /* Wakeup Event C High Byte */
+#define SFRXADDR_XWTEVTD0 0x3FFE /* Wakeup Event D Low Byte */
+#define SFRXADDR_XWTEVTD1 0x3FFF /* Wakeup Event D High Byte */
+#define SFRXADDR_XWTIRQEN 0x3FE9 /* Wakeup Timer Interrupt Enable */
+#define SFRXADDR_XWTSTAT 0x3FEA /* Wakeup Timer Status */
+
+#endif /* AX8052REGADDR_H */
diff --git a/libs/libmf/source/ax8052regs.c b/libs/libmf/source/ax8052regs.c
new file mode 100644
index 00000000..b4698a23
--- /dev/null
+++ b/libs/libmf/source/ax8052regs.c
@@ -0,0 +1,29 @@
+#if defined __ICC8051__
+
+#define AXCOMPILER_H
+# define SBIT(name, addr, bit)
+# define SFR(name, addr)
+# define SFRX(name, addr) __no_init __root volatile unsigned char __xdata name @ addr ;
+# define SFR16(name, addr)
+# define SFR16E(name, fulladdr)
+# define SFR16LEX(name, addr)
+# define SFR32(name, fulladdr)
+# define SFR32E(name, fulladdr)
+
+#include "ax8052.h"
+
+SFRX(REF, 0x7F16) /* Reference Tuning */
+SFRX(POWCTRL0, 0x7F10) /* Power Control 0 */
+SFRX(POWCTRL1, 0x7F11) /* Power Control 1 */
+SFRX(ADCCALG00GAIN0, 0x7030) /* ADC Calibration Range 00 Gain Low Byte */
+SFRX(ADCCALG00GAIN1, 0x7031) /* ADC Calibration Range 00 Gain High Byte */
+SFRX(ADCCALG01GAIN0, 0x7032) /* ADC Calibration Range 01 Gain Low Byte */
+SFRX(ADCCALG01GAIN1, 0x7033) /* ADC Calibration Range 01 Gain High Byte */
+SFRX(ADCCALG10GAIN0, 0x7034) /* ADC Calibration Range 10 Gain Low Byte */
+SFRX(ADCCALG10GAIN1, 0x7035) /* ADC Calibration Range 10 Gain High Byte */
+SFRX(ADCCALTEMPGAIN0, 0x7038) /* ADC Calibration Temperature Gain Low Byte */
+SFRX(ADCCALTEMPGAIN1, 0x7039) /* ADC Calibration Temperature Gain High Byte */
+SFRX(ADCCALTEMPOFFS0, 0x703A) /* ADC Calibration Temperature Offset Low Byte */
+SFRX(ADCCALTEMPOFFS1, 0x703B) /* ADC Calibration Temperature Offset High Byte */
+
+#endif
diff --git a/libs/libmf/source/axcompiler.h b/libs/libmf/source/axcompiler.h
new file mode 100644
index 00000000..2494971d
--- /dev/null
+++ b/libs/libmf/source/axcompiler.h
@@ -0,0 +1,201 @@
+/*-------------------------------------------------------------------------
+ axcompiler.h
+
+ Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
+
+ This library is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 2.1, or (at your option) any
+ later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this library; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA.
+
+ As a special exception, if you link this library with other files,
+ some of which are compiled with SDCC, to produce an executable,
+ this library does not by itself cause the resulting executable to
+ be covered by the GNU General Public License. This exception does
+ not however invalidate any other reasons why the executable file
+ might be covered by the GNU General Public License.
+-------------------------------------------------------------------------*/
+
+ /*
+ * Header file to overcome 8051 compiler differences for specifying
+ * special function registers. The following compilers are supported:
+ * SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhaeuser.
+ * Unfortunately not for use with Dunfield. The compilers are identified by
+ * their unique predefined macros. See also:
+ * http://predef.sourceforge.net/precomp.html
+ *
+ * SBIT and SFR define special bit and special function registers at the given
+ * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in
+ * little-endian format. SFR16E and SFR32E define sfr combinations without
+ * prerequisite byte order or adjacency. None of these multi-byte sfr
+ * combinations will guarantee the order in which they are accessed when read
+ * or written.
+ * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined
+ * to avoid portability issues because of compiler endianness.
+ * SFR16LEX is provided for 16 bit little endian xdata registers. It is usable
+ * on little endian compilers only; on big endian compilers, these registers
+ * will not be defined.
+ * This file is to be included in every microcontroller specific header file.
+ * Example:
+ *
+ * // my_mcu.h: sfr definitions for my mcu
+ * #include
+ *
+ * SBIT (P0_1, 0x80, 1) // Port 0 pin 1
+ *
+ * SFR (P0, 0x80) // Port 0
+ *
+ * SFRX (CPUCS, 0xE600) // Cypress FX2 Control and Status register in xdata memory at 0xE600
+ *
+ * SFR16 (TMR2, 0xCC) // Timer 2, lsb at 0xCC, msb at 0xCD
+ *
+ * SFR16E(TMR0, 0x8C8A) // Timer 0, lsb at 0x8A, msb at 0x8C
+ *
+ * SFR32 (MAC0ACC, 0x93) // SiLabs C8051F120 32 bits MAC0 Accumulator, lsb at 0x93, msb at 0x96
+ *
+ * SFR32E(SUMR, 0xE5E4E3E2) // TI MSC1210 SUMR 32 bits Summation register, lsb at 0xE2, msb at 0xE5
+ *
+ */
+
+#ifndef AXCOMPILER_H
+#define AXCOMPILER_H
+
+/** SDCC - Small Device C Compiler
+ * http://sdcc.sf.net
+ */
+#if defined SDCC
+# define SBIT(name, addr, bit) __sbit __at(addr+bit) name ;
+# define SFR(name, addr) __sfr __at(addr) name ;
+# define SFRX(name, addr) __xdata volatile unsigned char __at(addr) name ;
+# define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name ;
+# define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name ;
+# define SFR16LEX(name, addr) __xdata volatile unsigned short __at(addr) name ;
+# define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name ;
+# define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name ;
+
+/** Keil C51
+ * http://www.keil.com
+ */
+#elif defined __CX51__ || defined __C51__
+# define SBIT(name, addr, bit) sbit name = addr^bit ;
+# define SFR(name, addr) sfr name = addr ;
+# define SFRX(name, addr) static volatile unsigned char xdata name _at_ addr ;
+# define SFR16(name, addr) sfr16 name = addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Raisonance
+ * http://www.raisonance.com
+ */
+#elif defined __RC51__
+# define SBIT(name, addr, bit) at (addr+bit) sbit name ;
+# define SFR(name, addr) sfr at addr name ;
+# define SFRX(name, addr) xdata at addr volatile unsigned char name ;
+# define SFR16(name, addr) sfr16 at addr name ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** IAR 8051
+ * http://www.iar.com
+ */
+#elif defined __ICC8051__
+
+#pragma language=extended
+#include
+
+# define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) ;
+# define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr ;
+# define SFRX(name, addr) extern __xdata __no_init volatile unsigned char name @ addr ;
+# define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr ;
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Tasking / Altium
+ * http://www.altium.com/tasking
+ */
+#elif defined _CC51
+# define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) ;
+# define SFR(name, addr) _sfrbyte name _at(addr) ;
+# define SFRX(name, addr) _xdat volatile unsigned char name _at(addr) ;
+#if _CC51 > 71
+# define SFR16(name, addr) _sfrword _little name _at(addr) ;
+#else
+# define SFR16(name, addr) /* not supported */
+#endif
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Hi-Tech 8051
+ * http://www.htsoft.com
+ */
+#elif defined HI_TECH_C
+# define SBIT(name, addr, bit) volatile bit name @ (addr+bit) ;
+# define SFR(name, addr) volatile unsigned char name @ addr ;
+# define SFRX(name, addr) volatile far unsigned char name @ addr ;
+# define SFR16(name, addr) /* not supported */
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Crossware
+ * http://www.crossware.com
+ */
+#elif defined _XC51_VER
+# define SBIT(name, addr, bit) _sfrbit name = (addr+bit) ;
+# define SFR(name, addr) _sfr name = addr ;
+# define SFRX(name, addr) volatile unsigned char _xdata name _at addr ;
+# define SFR16(name, addr) _sfrword name = addr ;
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** Wickenhaeuser
+ * http://www.wickenhaeuser.de
+ */
+#elif defined __UC__
+# define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) ;
+# define SFR(name, addr) near unsigned char name @ addr ;
+# define SFRX(name, addr) xdata volatile unsigned char name @ addr ;
+# define SFR16(name, addr) /* not supported */
+# define SFR16E(name, fulladdr) /* not supported */
+# define SFR16LEX(name, addr) /* not supported */
+# define SFR32(name, fulladdr) /* not supported */
+# define SFR32E(name, fulladdr) /* not supported */
+
+/** default
+ * unrecognized compiler
+ */
+#else
+# warning unrecognized compiler
+# define SBIT(name, addr, bit) volatile bool name ;
+# define SFR(name, addr) volatile unsigned char name ;
+# define SFRX(name, addr) volatile unsigned char name ;
+# define SFR16(name, addr) volatile unsigned short name ;
+# define SFR16E(name, fulladdr) volatile unsigned short name ;
+# define SFR16LEX(name, addr) volatile unsigned short name ;
+# define SFR32(name, fulladdr) volatile unsigned long name ;
+# define SFR32E(name, fulladdr) volatile unsigned long name ;
+
+#endif
+
+#endif //AXCOMPILER_H
diff --git a/libs/libmf/source/bch3121dec.c b/libs/libmf/source/bch3121dec.c
new file mode 100644
index 00000000..34efd910
--- /dev/null
+++ b/libs/libmf/source/bch3121dec.c
@@ -0,0 +1,18 @@
+#include "ax8052.h"
+#include "libmfbch.h"
+
+uint32_t bch3121_decode(uint32_t cw)
+{
+ uint16_t __autodata x = bch3121_syndrome(cw);
+ uint8_t __autodata p;
+ x = bch3121_syndrometable[x];
+ // check for decode failure
+ if (((int16_t)x) < 0)
+ return cw | 1UL;
+ p = x & 0x1F;
+ cw ^= (1UL << p);
+ x >>= 5;
+ p = x & 0x1F;
+ cw ^= (1UL << p);
+ return cw & ~1UL;
+}
diff --git a/libs/libmf/source/bch3121decp.c b/libs/libmf/source/bch3121decp.c
new file mode 100644
index 00000000..735d6153
--- /dev/null
+++ b/libs/libmf/source/bch3121decp.c
@@ -0,0 +1,12 @@
+#include "ax8052.h"
+#include "libmfbch.h"
+
+uint32_t bch3121_decode_parity(uint32_t cw)
+{
+ uint8_t __autodata p = cw & 1;
+ cw = bch3121_decode(cw);
+ if (cw & 1)
+ return cw;
+ cw |= p ^ parity32(cw);
+ return cw;
+}
diff --git a/libs/libmf/source/bch3121enc.c b/libs/libmf/source/bch3121enc.c
new file mode 100644
index 00000000..405d4c01
--- /dev/null
+++ b/libs/libmf/source/bch3121enc.c
@@ -0,0 +1,9 @@
+#include "ax8052.h"
+#include "libmfbch.h"
+
+uint32_t bch3121_encode(uint32_t cw)
+{
+ cw &= 0xFFFFF800;
+ cw |= bch3121_syndrome(cw) << 1;
+ return cw;
+}
diff --git a/libs/libmf/source/bch3121encp.c b/libs/libmf/source/bch3121encp.c
new file mode 100644
index 00000000..08b67155
--- /dev/null
+++ b/libs/libmf/source/bch3121encp.c
@@ -0,0 +1,10 @@
+#include "ax8052.h"
+#include "libmfbch.h"
+
+uint32_t bch3121_encode_parity(uint32_t cw)
+{
+ cw &= 0xFFFFF800;
+ cw |= bch3121_syndrome(cw) << 1;
+ cw |= parity32(cw);
+ return cw;
+}
diff --git a/libs/libmf/source/bch3121stab.c b/libs/libmf/source/bch3121stab.c
new file mode 100644
index 00000000..796e449d
--- /dev/null
+++ b/libs/libmf/source/bch3121stab.c
@@ -0,0 +1,137 @@
+/* automatically generated by genbch, do not edit! */
+
+#include "libmfbch.h"
+
+const uint16_t __code bch3121_syndrometable[1024] = {
+ 0x0000, 0x0001, 0x0002, 0x0041, 0x0003, 0x0061, 0x0062, 0x8000,
+ 0x0004, 0x0081, 0x0082, 0x8000, 0x0083, 0x0394, 0x8000, 0x0376,
+ 0x0005, 0x00a1, 0x00a2, 0x02f4, 0x00a3, 0x8000, 0x8000, 0x8000,
+ 0x00a4, 0x032c, 0x03b5, 0x8000, 0x8000, 0x8000, 0x0397, 0x01ab,
+ 0x0006, 0x00c1, 0x00c2, 0x8000, 0x00c3, 0x8000, 0x0315, 0x032e,
+ 0x00c4, 0x8000, 0x8000, 0x8000, 0x8000, 0x034b, 0x8000, 0x8000,
+ 0x00c5, 0x8000, 0x034d, 0x8000, 0x03d6, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x03db, 0x03b8, 0x8000, 0x01cc, 0x8000,
+ 0x0007, 0x00e1, 0x00e2, 0x0379, 0x00e3, 0x8000, 0x8000, 0x8000,
+ 0x00e4, 0x8000, 0x8000, 0x8000, 0x0336, 0x8000, 0x034f, 0x8000,
+ 0x00e5, 0x0308, 0x8000, 0x026a, 0x8000, 0x02cc, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x036c, 0x8000, 0x8000, 0x8000, 0x8000, 0x03ce,
+ 0x00e6, 0x03cc, 0x8000, 0x01eb, 0x036e, 0x8000, 0x8000, 0x0251,
+ 0x03f7, 0x8000, 0x8000, 0x02ce, 0x8000, 0x03a8, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x03fc, 0x02a8,
+ 0x03d9, 0x8000, 0x8000, 0x03f4, 0x01ed, 0x0209, 0x8000, 0x8000,
+ 0x0008, 0x0101, 0x0102, 0x8000, 0x0103, 0x01c9, 0x039a, 0x8000,
+ 0x0104, 0x8000, 0x8000, 0x0354, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x0105, 0x0307, 0x8000, 0x02d0, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x0357, 0x8000, 0x8000, 0x8000, 0x0370, 0x024a, 0x8000, 0x8000,
+ 0x0106, 0x8000, 0x0329, 0x8000, 0x8000, 0x8000, 0x028b, 0x03d0,
+ 0x8000, 0x0271, 0x02ed, 0x038b, 0x8000, 0x03a7, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x038d, 0x02eb, 0x8000, 0x02a7,
+ 0x8000, 0x028d, 0x8000, 0x0189, 0x8000, 0x8000, 0x03ef, 0x8000,
+ 0x0107, 0x0305, 0x03ed, 0x8000, 0x8000, 0x028f, 0x020c, 0x8000,
+ 0x038f, 0x8000, 0x8000, 0x8000, 0x8000, 0x03a6, 0x0272, 0x8000,
+ 0x0301, 0x0018, 0x8000, 0x0302, 0x8000, 0x0303, 0x02ef, 0x02a6,
+ 0x8000, 0x0304, 0x03c9, 0x8000, 0x8000, 0x03eb, 0x8000, 0x0330,
+ 0x8000, 0x0369, 0x8000, 0x8000, 0x8000, 0x03a4, 0x8000, 0x02a5,
+ 0x8000, 0x03a3, 0x8000, 0x8000, 0x03a1, 0x001d, 0x02c9, 0x03a2,
+ 0x03fa, 0x0306, 0x8000, 0x02a3, 0x8000, 0x02a2, 0x02a1, 0x0015,
+ 0x020e, 0x8000, 0x022a, 0x8000, 0x8000, 0x03a5, 0x8000, 0x02a4,
+ 0x0009, 0x0121, 0x0122, 0x03b6, 0x0123, 0x01c8, 0x8000, 0x8000,
+ 0x0124, 0x8000, 0x01ea, 0x03d8, 0x03bb, 0x8000, 0x8000, 0x8000,
+ 0x0125, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x0375, 0x0353,
+ 0x8000, 0x02d5, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x0126, 0x8000, 0x0328, 0x8000, 0x8000, 0x026d, 0x02f1, 0x8000,
+ 0x8000, 0x03f2, 0x8000, 0x8000, 0x8000, 0x03d5, 0x8000, 0x8000,
+ 0x0378, 0x8000, 0x8000, 0x8000, 0x8000, 0x0291, 0x8000, 0x03dd,
+ 0x0391, 0x8000, 0x026b, 0x0188, 0x8000, 0x0207, 0x8000, 0x0316,
+ 0x0127, 0x02f2, 0x8000, 0x8000, 0x034a, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x02ac, 0x8000, 0x03f1, 0x03b9,
+ 0x8000, 0x8000, 0x0292, 0x8000, 0x030e, 0x0335, 0x03ac, 0x8000,
+ 0x8000, 0x026f, 0x03c8, 0x8000, 0x8000, 0x0206, 0x8000, 0x0392,
+ 0x8000, 0x0368, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x03ae, 0x016a, 0x030c, 0x8000, 0x8000, 0x0205, 0x02c8, 0x8000,
+ 0x8000, 0x8000, 0x02ae, 0x0338, 0x8000, 0x0204, 0x01aa, 0x8000,
+ 0x8000, 0x0203, 0x8000, 0x8000, 0x0201, 0x0010, 0x8000, 0x0202,
+ 0x0128, 0x01c3, 0x0326, 0x8000, 0x01c1, 0x000e, 0x8000, 0x01c2,
+ 0x8000, 0x8000, 0x02b0, 0x8000, 0x022d, 0x01c4, 0x8000, 0x02f3,
+ 0x03b0, 0x0393, 0x8000, 0x022b, 0x8000, 0x01c5, 0x8000, 0x024f,
+ 0x8000, 0x8000, 0x03c7, 0x0186, 0x0293, 0x8000, 0x8000, 0x8000,
+ 0x0322, 0x0367, 0x0019, 0x0321, 0x8000, 0x01c6, 0x0323, 0x8000,
+ 0x8000, 0x8000, 0x0324, 0x0185, 0x0310, 0x8000, 0x02c7, 0x8000,
+ 0x8000, 0x8000, 0x0325, 0x0184, 0x03ea, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x0182, 0x0181, 0x000c, 0x8000, 0x8000, 0x0351, 0x0183,
+ 0x8000, 0x0366, 0x038a, 0x8000, 0x8000, 0x01c7, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x03c5, 0x8000, 0x8000, 0x8000, 0x02c6, 0x028a,
+ 0x8000, 0x0309, 0x03c4, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x03c2, 0x0352, 0x001e, 0x03c1, 0x02ea, 0x8000, 0x03c3, 0x8000,
+ 0x0361, 0x001b, 0x0327, 0x0362, 0x8000, 0x0363, 0x02c4, 0x03f3,
+ 0x8000, 0x0364, 0x02c3, 0x024d, 0x02c2, 0x03a9, 0x0016, 0x02c1,
+ 0x022f, 0x0365, 0x8000, 0x8000, 0x024b, 0x8000, 0x8000, 0x02a9,
+ 0x8000, 0x8000, 0x03c6, 0x0187, 0x8000, 0x0208, 0x02c5, 0x8000,
+ 0x000a, 0x0141, 0x0142, 0x8000, 0x0143, 0x8000, 0x03d7, 0x8000,
+ 0x0144, 0x8000, 0x01e9, 0x020d, 0x8000, 0x02b1, 0x8000, 0x03ec,
+ 0x0145, 0x8000, 0x8000, 0x0267, 0x020b, 0x03d4, 0x03f9, 0x03b1,
+ 0x03dc, 0x8000, 0x8000, 0x8000, 0x8000, 0x0248, 0x8000, 0x8000,
+ 0x0146, 0x02d4, 0x8000, 0x039b, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x0311, 0x0396, 0x8000, 0x0374, 0x8000,
+ 0x8000, 0x03ee, 0x02f6, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x0350, 0x8000, 0x8000, 0x8000, 0x0377, 0x8000, 0x8000,
+ 0x0147, 0x8000, 0x8000, 0x0265, 0x0349, 0x8000, 0x8000, 0x038e,
+ 0x8000, 0x8000, 0x028e, 0x8000, 0x0312, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x0262, 0x0261, 0x0013, 0x8000, 0x03fb, 0x8000, 0x0263,
+ 0x8000, 0x02ee, 0x03f6, 0x0264, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x0399, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x02ec,
+ 0x8000, 0x0169, 0x02b2, 0x8000, 0x8000, 0x0334, 0x03fe, 0x8000,
+ 0x03b2, 0x8000, 0x8000, 0x0266, 0x028c, 0x8000, 0x01a9, 0x020f,
+ 0x8000, 0x038c, 0x0228, 0x8000, 0x8000, 0x8000, 0x0337, 0x8000,
+ 0x0148, 0x8000, 0x0313, 0x8000, 0x8000, 0x8000, 0x8000, 0x02cb,
+ 0x036b, 0x8000, 0x8000, 0x8000, 0x8000, 0x0245, 0x8000, 0x01ee,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x0244, 0x8000, 0x036d,
+ 0x02cd, 0x0243, 0x8000, 0x8000, 0x0241, 0x0012, 0x03da, 0x0242,
+ 0x8000, 0x02f0, 0x8000, 0x8000, 0x02b3, 0x037a, 0x8000, 0x8000,
+ 0x032f, 0x8000, 0x0356, 0x8000, 0x03cd, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x01ec, 0x0290, 0x03cb, 0x03e9, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x0227, 0x8000, 0x8000, 0x0246, 0x03b3, 0x0390,
+ 0x8000, 0x034e, 0x0389, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x03f0, 0x8000, 0x032b, 0x8000, 0x01ac, 0x8000, 0x0289,
+ 0x03cf, 0x030a, 0x018b, 0x0268, 0x032d, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x0226, 0x8000, 0x02e9, 0x0247, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x02cf, 0x8000, 0x0359, 0x8000,
+ 0x8000, 0x8000, 0x0225, 0x036f, 0x01cb, 0x03aa, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x0224, 0x01cd, 0x8000, 0x8000, 0x8000, 0x02aa,
+ 0x0222, 0x8000, 0x0011, 0x0221, 0x8000, 0x8000, 0x0223, 0x034c,
+ 0x0149, 0x8000, 0x01e4, 0x8000, 0x0347, 0x8000, 0x8000, 0x8000,
+ 0x01e2, 0x8000, 0x000f, 0x01e1, 0x8000, 0x0317, 0x01e3, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x0398, 0x02d1, 0x8000, 0x8000, 0x8000,
+ 0x024e, 0x8000, 0x01e5, 0x0371, 0x8000, 0x8000, 0x0314, 0x8000,
+ 0x03d1, 0x8000, 0x03b4, 0x8000, 0x8000, 0x8000, 0x024c, 0x8000,
+ 0x8000, 0x0167, 0x01e6, 0x02f5, 0x8000, 0x8000, 0x0270, 0x03bc,
+ 0x8000, 0x03b7, 0x8000, 0x8000, 0x03e8, 0x0395, 0x01a7, 0x8000,
+ 0x02b4, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x0332,
+ 0x0343, 0x022c, 0x0388, 0x03f5, 0x001a, 0x0341, 0x0342, 0x03d2,
+ 0x8000, 0x0166, 0x01e7, 0x8000, 0x0344, 0x8000, 0x8000, 0x0288,
+ 0x8000, 0x8000, 0x8000, 0x0269, 0x0345, 0x8000, 0x01a6, 0x8000,
+ 0x0331, 0x03fd, 0x8000, 0x8000, 0x02e8, 0x8000, 0x8000, 0x8000,
+ 0x8000, 0x0164, 0x8000, 0x8000, 0x0346, 0x03f8, 0x01a5, 0x8000,
+ 0x0161, 0x000b, 0x8000, 0x0162, 0x8000, 0x0163, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x01a3, 0x02d2, 0x01a2, 0x8000, 0x000d, 0x01a1,
+ 0x8000, 0x0165, 0x8000, 0x8000, 0x0372, 0x020a, 0x01a4, 0x022e,
+ 0x8000, 0x02ad, 0x0387, 0x8000, 0x03ab, 0x01ca, 0x8000, 0x0230,
+ 0x8000, 0x03d3, 0x01e8, 0x8000, 0x8000, 0x8000, 0x8000, 0x0287,
+ 0x8000, 0x8000, 0x8000, 0x8000, 0x03e6, 0x0358, 0x8000, 0x8000,
+ 0x8000, 0x8000, 0x8000, 0x03ad, 0x02e7, 0x0249, 0x02ab, 0x8000,
+ 0x8000, 0x8000, 0x032a, 0x8000, 0x03e5, 0x8000, 0x8000, 0x030d,
+ 0x8000, 0x03ba, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x03e3, 0x8000, 0x0373, 0x0355, 0x001f, 0x03e1, 0x03e2, 0x8000,
+ 0x030b, 0x8000, 0x8000, 0x018a, 0x03e4, 0x02d3, 0x8000, 0x8000,
+ 0x0382, 0x8000, 0x001c, 0x0381, 0x0348, 0x8000, 0x0383, 0x0284,
+ 0x8000, 0x8000, 0x0384, 0x0283, 0x02e5, 0x0282, 0x0281, 0x0014,
+ 0x8000, 0x8000, 0x0385, 0x8000, 0x02e4, 0x8000, 0x026e, 0x8000,
+ 0x02e3, 0x8000, 0x03ca, 0x030f, 0x0017, 0x02e1, 0x02e2, 0x0285,
+ 0x0250, 0x036a, 0x0386, 0x8000, 0x8000, 0x8000, 0x8000, 0x03af,
+ 0x026c, 0x0168, 0x8000, 0x8000, 0x8000, 0x8000, 0x02ca, 0x0286,
+ 0x8000, 0x0333, 0x8000, 0x8000, 0x03e7, 0x8000, 0x01a8, 0x8000,
+ 0x8000, 0x8000, 0x0229, 0x8000, 0x02e6, 0x02af, 0x8000, 0x8000
+};
+
+/* Undecodable: 527 / 1024 */
+
diff --git a/libs/libmf/source/bch3121syn.c b/libs/libmf/source/bch3121syn.c
new file mode 100644
index 00000000..602b8d02
--- /dev/null
+++ b/libs/libmf/source/bch3121syn.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "libmfbch.h"
+
+uint16_t bch3121_syndrome(uint32_t cw)
+{
+ uint8_t __autodata cnt = 21;
+ do {
+ if (cw & 0x80000000)
+ cw ^= 0xED200000;
+ cw <<= 1;
+ } while (--cnt);
+ return cw >> 22;
+}
diff --git a/libs/libmf/source/chksgnlim16.c b/libs/libmf/source/chksgnlim16.c
new file mode 100644
index 00000000..7faa6756
--- /dev/null
+++ b/libs/libmf/source/chksgnlim16.c
@@ -0,0 +1,59 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant __naked
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ push ar0
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,dph
+ jnb acc.7,00010$
+ mov a,dpl
+ add a,@r0
+ inc r0
+ mov a,dph
+ addc a,@r0
+ xrl a,#0x80
+ sjmp 00011$
+00010$: setb c
+ mov a,dpl
+ subb a,@r0
+ inc r0
+ mov a,dph
+ subb a,@r0
+00011$: rlc a
+ clr a
+ rlc a
+ mov dpl,a
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+#include
+
+__reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant
+{
+ if (x < 0) {
+ x += lim;
+ return x >= 0;
+ }
+ x -= lim;
+ return x <= 0;
+}
+
+#endif
diff --git a/libs/libmf/source/chksgnlim32.c b/libs/libmf/source/chksgnlim32.c
new file mode 100644
index 00000000..ff7d6fa9
--- /dev/null
+++ b/libs/libmf/source/chksgnlim32.c
@@ -0,0 +1,74 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant __naked
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ push ar0
+ push ar1
+ mov r1,a
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,r1
+ jnb acc.7,00010$
+ mov a,dpl
+ add a,@r0
+ inc r0
+ mov a,dph
+ addc a,@r0
+ inc r0
+ mov a,b
+ addc a,@r0
+ inc r0
+ mov a,r1
+ addc a,@r0
+ xrl a,#0x80
+ sjmp 00011$
+00010$: setb c
+ mov a,dpl
+ subb a,@r0
+ inc r0
+ mov a,dph
+ subb a,@r0
+ inc r0
+ mov a,b
+ subb a,@r0
+ inc r0
+ mov a,r1
+ subb a,@r0
+00011$: rlc a
+ clr a
+ rlc a
+ mov dpl,a
+ pop ar1
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+#include
+
+__reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant
+{
+ if (x < 0) {
+ x += lim;
+ return x >= 0;
+ }
+ x -= lim;
+ return x <= 0;
+}
+
+#endif
diff --git a/libs/libmf/source/crc16.c b/libs/libmf/source/crc16.c
new file mode 100644
index 00000000..fd38cdcb
--- /dev/null
+++ b/libs/libmf/source/crc16.c
@@ -0,0 +1,63 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_byte crc_crc16_byte
+#define crc_table crc_crc16_table
+#define crc_table_asm _crc_crc16_table
+#elif CRCMODE == 1
+#define crc_byte crc_crc16dnp_byte
+#define crc_table crc_crc16dnp_table
+#define crc_table_asm _crc_crc16dnp_table
+#elif CRCMODE == 2
+#define crc_byte crc_ccitt_byte
+#define crc_table crc_ccitt_table
+#define crc_table_asm _crc_ccitt_table
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_table_asm
+ add a,r2
+ mov dpl,a
+ mov a,#(crc_table_asm >> 8)
+ addc a,r3
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#1
+ movc a,@a+dptr
+ mov dph,a
+ mov dpl,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/source/crc16b.c b/libs/libmf/source/crc16b.c
new file mode 100644
index 00000000..75fa48db
--- /dev/null
+++ b/libs/libmf/source/crc16b.c
@@ -0,0 +1,272 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_buf crc_crc16
+#define crc_byte crc_crc16_byte
+#define crc_table_asm _crc_crc16_table
+#define CRCMSB 0
+#elif CRCMODE == 1
+#define crc_buf crc_crc16_msb
+#define crc_byte crc_crc16_msb_byte
+#define crc_table_asm _crc_crc16_msbtable
+#define CRCMSB 1
+#elif CRCMODE == 2
+#define crc_buf crc_crc16dnp
+#define crc_byte crc_crc16dnp_byte
+#define crc_table_asm _crc_crc16dnp_table
+#define CRCMSB 0
+#elif CRCMODE == 3
+#define crc_buf crc_crc16dnp_msb
+#define crc_byte crc_crc16dnp_msb_byte
+#define crc_table_asm _crc_crc16dnp_msbtable
+#define CRCMSB 1
+#elif CRCMODE == 4
+#define crc_buf crc_ccitt
+#define crc_byte crc_ccitt_byte
+#define crc_table_asm _crc_ccitt_table
+#define CRCMSB 0
+#elif CRCMODE == 5
+#define crc_buf crc_ccitt_msb
+#define crc_byte crc_ccitt_msb_byte
+#define crc_table_asm _crc_ccitt_msbtable
+#define CRCMSB 1
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-5
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ mov r5,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff]
+ xrl a,r5
+ rl a
+ mov dpl,a
+ anl a,#0xfe
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x01
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/source/crc16dnpmsbtable.c b/libs/libmf/source/crc16dnpmsbtable.c
new file mode 100644
index 00000000..7776eeaa
--- /dev/null
+++ b/libs/libmf/source/crc16dnpmsbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^13 + x^12 + x^11 + x^10 + x^8 + x^6 + x^5 + x^2 + 1 = 0x13d65 MSB first */
+
+const uint16_t __code crc_crc16dnp_msbtable[256] = {
+ 0x0000, 0x3d65, 0x7aca, 0x47af, 0xf594, 0xc8f1, 0x8f5e, 0xb23b,
+ 0xd64d, 0xeb28, 0xac87, 0x91e2, 0x23d9, 0x1ebc, 0x5913, 0x6476,
+ 0x91ff, 0xac9a, 0xeb35, 0xd650, 0x646b, 0x590e, 0x1ea1, 0x23c4,
+ 0x47b2, 0x7ad7, 0x3d78, 0x001d, 0xb226, 0x8f43, 0xc8ec, 0xf589,
+ 0x1e9b, 0x23fe, 0x6451, 0x5934, 0xeb0f, 0xd66a, 0x91c5, 0xaca0,
+ 0xc8d6, 0xf5b3, 0xb21c, 0x8f79, 0x3d42, 0x0027, 0x4788, 0x7aed,
+ 0x8f64, 0xb201, 0xf5ae, 0xc8cb, 0x7af0, 0x4795, 0x003a, 0x3d5f,
+ 0x5929, 0x644c, 0x23e3, 0x1e86, 0xacbd, 0x91d8, 0xd677, 0xeb12,
+ 0x3d36, 0x0053, 0x47fc, 0x7a99, 0xc8a2, 0xf5c7, 0xb268, 0x8f0d,
+ 0xeb7b, 0xd61e, 0x91b1, 0xacd4, 0x1eef, 0x238a, 0x6425, 0x5940,
+ 0xacc9, 0x91ac, 0xd603, 0xeb66, 0x595d, 0x6438, 0x2397, 0x1ef2,
+ 0x7a84, 0x47e1, 0x004e, 0x3d2b, 0x8f10, 0xb275, 0xf5da, 0xc8bf,
+ 0x23ad, 0x1ec8, 0x5967, 0x6402, 0xd639, 0xeb5c, 0xacf3, 0x9196,
+ 0xf5e0, 0xc885, 0x8f2a, 0xb24f, 0x0074, 0x3d11, 0x7abe, 0x47db,
+ 0xb252, 0x8f37, 0xc898, 0xf5fd, 0x47c6, 0x7aa3, 0x3d0c, 0x0069,
+ 0x641f, 0x597a, 0x1ed5, 0x23b0, 0x918b, 0xacee, 0xeb41, 0xd624,
+ 0x7a6c, 0x4709, 0x00a6, 0x3dc3, 0x8ff8, 0xb29d, 0xf532, 0xc857,
+ 0xac21, 0x9144, 0xd6eb, 0xeb8e, 0x59b5, 0x64d0, 0x237f, 0x1e1a,
+ 0xeb93, 0xd6f6, 0x9159, 0xac3c, 0x1e07, 0x2362, 0x64cd, 0x59a8,
+ 0x3dde, 0x00bb, 0x4714, 0x7a71, 0xc84a, 0xf52f, 0xb280, 0x8fe5,
+ 0x64f7, 0x5992, 0x1e3d, 0x2358, 0x9163, 0xac06, 0xeba9, 0xd6cc,
+ 0xb2ba, 0x8fdf, 0xc870, 0xf515, 0x472e, 0x7a4b, 0x3de4, 0x0081,
+ 0xf508, 0xc86d, 0x8fc2, 0xb2a7, 0x009c, 0x3df9, 0x7a56, 0x4733,
+ 0x2345, 0x1e20, 0x598f, 0x64ea, 0xd6d1, 0xebb4, 0xac1b, 0x917e,
+ 0x475a, 0x7a3f, 0x3d90, 0x00f5, 0xb2ce, 0x8fab, 0xc804, 0xf561,
+ 0x9117, 0xac72, 0xebdd, 0xd6b8, 0x6483, 0x59e6, 0x1e49, 0x232c,
+ 0xd6a5, 0xebc0, 0xac6f, 0x910a, 0x2331, 0x1e54, 0x59fb, 0x649e,
+ 0x00e8, 0x3d8d, 0x7a22, 0x4747, 0xf57c, 0xc819, 0x8fb6, 0xb2d3,
+ 0x59c1, 0x64a4, 0x230b, 0x1e6e, 0xac55, 0x9130, 0xd69f, 0xebfa,
+ 0x8f8c, 0xb2e9, 0xf546, 0xc823, 0x7a18, 0x477d, 0x00d2, 0x3db7,
+ 0xc83e, 0xf55b, 0xb2f4, 0x8f91, 0x3daa, 0x00cf, 0x4760, 0x7a05,
+ 0x1e73, 0x2316, 0x64b9, 0x59dc, 0xebe7, 0xd682, 0x912d, 0xac48
+};
+
diff --git a/libs/libmf/source/crc16dnptable.c b/libs/libmf/source/crc16dnptable.c
new file mode 100644
index 00000000..b5d87ee3
--- /dev/null
+++ b/libs/libmf/source/crc16dnptable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^13 + x^12 + x^11 + x^10 + x^8 + x^6 + x^5 + x^2 + 1 = 0x13d65 LSB first */
+
+const uint16_t __code crc_crc16dnp_table[256] = {
+ 0x0000, 0x365e, 0x6cbc, 0x5ae2, 0xd978, 0xef26, 0xb5c4, 0x839a,
+ 0xff89, 0xc9d7, 0x9335, 0xa56b, 0x26f1, 0x10af, 0x4a4d, 0x7c13,
+ 0xb26b, 0x8435, 0xded7, 0xe889, 0x6b13, 0x5d4d, 0x07af, 0x31f1,
+ 0x4de2, 0x7bbc, 0x215e, 0x1700, 0x949a, 0xa2c4, 0xf826, 0xce78,
+ 0x29af, 0x1ff1, 0x4513, 0x734d, 0xf0d7, 0xc689, 0x9c6b, 0xaa35,
+ 0xd626, 0xe078, 0xba9a, 0x8cc4, 0x0f5e, 0x3900, 0x63e2, 0x55bc,
+ 0x9bc4, 0xad9a, 0xf778, 0xc126, 0x42bc, 0x74e2, 0x2e00, 0x185e,
+ 0x644d, 0x5213, 0x08f1, 0x3eaf, 0xbd35, 0x8b6b, 0xd189, 0xe7d7,
+ 0x535e, 0x6500, 0x3fe2, 0x09bc, 0x8a26, 0xbc78, 0xe69a, 0xd0c4,
+ 0xacd7, 0x9a89, 0xc06b, 0xf635, 0x75af, 0x43f1, 0x1913, 0x2f4d,
+ 0xe135, 0xd76b, 0x8d89, 0xbbd7, 0x384d, 0x0e13, 0x54f1, 0x62af,
+ 0x1ebc, 0x28e2, 0x7200, 0x445e, 0xc7c4, 0xf19a, 0xab78, 0x9d26,
+ 0x7af1, 0x4caf, 0x164d, 0x2013, 0xa389, 0x95d7, 0xcf35, 0xf96b,
+ 0x8578, 0xb326, 0xe9c4, 0xdf9a, 0x5c00, 0x6a5e, 0x30bc, 0x06e2,
+ 0xc89a, 0xfec4, 0xa426, 0x9278, 0x11e2, 0x27bc, 0x7d5e, 0x4b00,
+ 0x3713, 0x014d, 0x5baf, 0x6df1, 0xee6b, 0xd835, 0x82d7, 0xb489,
+ 0xa6bc, 0x90e2, 0xca00, 0xfc5e, 0x7fc4, 0x499a, 0x1378, 0x2526,
+ 0x5935, 0x6f6b, 0x3589, 0x03d7, 0x804d, 0xb613, 0xecf1, 0xdaaf,
+ 0x14d7, 0x2289, 0x786b, 0x4e35, 0xcdaf, 0xfbf1, 0xa113, 0x974d,
+ 0xeb5e, 0xdd00, 0x87e2, 0xb1bc, 0x3226, 0x0478, 0x5e9a, 0x68c4,
+ 0x8f13, 0xb94d, 0xe3af, 0xd5f1, 0x566b, 0x6035, 0x3ad7, 0x0c89,
+ 0x709a, 0x46c4, 0x1c26, 0x2a78, 0xa9e2, 0x9fbc, 0xc55e, 0xf300,
+ 0x3d78, 0x0b26, 0x51c4, 0x679a, 0xe400, 0xd25e, 0x88bc, 0xbee2,
+ 0xc2f1, 0xf4af, 0xae4d, 0x9813, 0x1b89, 0x2dd7, 0x7735, 0x416b,
+ 0xf5e2, 0xc3bc, 0x995e, 0xaf00, 0x2c9a, 0x1ac4, 0x4026, 0x7678,
+ 0x0a6b, 0x3c35, 0x66d7, 0x5089, 0xd313, 0xe54d, 0xbfaf, 0x89f1,
+ 0x4789, 0x71d7, 0x2b35, 0x1d6b, 0x9ef1, 0xa8af, 0xf24d, 0xc413,
+ 0xb800, 0x8e5e, 0xd4bc, 0xe2e2, 0x6178, 0x5726, 0x0dc4, 0x3b9a,
+ 0xdc4d, 0xea13, 0xb0f1, 0x86af, 0x0535, 0x336b, 0x6989, 0x5fd7,
+ 0x23c4, 0x159a, 0x4f78, 0x7926, 0xfabc, 0xcce2, 0x9600, 0xa05e,
+ 0x6e26, 0x5878, 0x029a, 0x34c4, 0xb75e, 0x8100, 0xdbe2, 0xedbc,
+ 0x91af, 0xa7f1, 0xfd13, 0xcb4d, 0x48d7, 0x7e89, 0x246b, 0x1235
+};
+
diff --git a/libs/libmf/source/crc16msb.c b/libs/libmf/source/crc16msb.c
new file mode 100644
index 00000000..f32dd6e3
--- /dev/null
+++ b/libs/libmf/source/crc16msb.c
@@ -0,0 +1,63 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_msb_byte crc_crc16_msb_byte
+#define crc_msbtable crc_crc16_msbtable
+#define crc_msbtable_asm _crc_crc16_msbtable
+#elif CRCMODE == 1
+#define crc_msb_byte crc_crc16dnp_msb_byte
+#define crc_msbtable crc_crc16dnp_msbtable
+#define crc_msbtable_asm _crc_crc16dnp_msbtable
+#elif CRCMODE == 2
+#define crc_msb_byte crc_ccitt_msb_byte
+#define crc_msbtable crc_ccitt_msbtable
+#define crc_msbtable_asm _crc_ccitt_msbtable
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dph
+ clr c
+ rlc a
+ mov r2,a
+ clr a
+ rlc a
+ mov r3,a
+ mov a,#crc_msbtable_asm
+ add a,r2
+ xch a,dpl
+ mov r2,a
+ mov a,#(crc_msbtable_asm >> 8)
+ addc a,r3
+ mov dph,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t crc_msb_byte(uint16_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 8) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/source/crc16msbtable.c b/libs/libmf/source/crc16msbtable.c
new file mode 100644
index 00000000..01e5e77e
--- /dev/null
+++ b/libs/libmf/source/crc16msbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^15 + x^2 + 1 = 0x18005 MSB first */
+
+const uint16_t __code crc_crc16_msbtable[256] = {
+ 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011,
+ 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022,
+ 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072,
+ 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041,
+ 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2,
+ 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1,
+ 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1,
+ 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082,
+ 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192,
+ 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1,
+ 0x01e0, 0x81e5, 0x81ef, 0x01ea, 0x81fb, 0x01fe, 0x01f4, 0x81f1,
+ 0x81d3, 0x01d6, 0x01dc, 0x81d9, 0x01c8, 0x81cd, 0x81c7, 0x01c2,
+ 0x0140, 0x8145, 0x814f, 0x014a, 0x815b, 0x015e, 0x0154, 0x8151,
+ 0x8173, 0x0176, 0x017c, 0x8179, 0x0168, 0x816d, 0x8167, 0x0162,
+ 0x8123, 0x0126, 0x012c, 0x8129, 0x0138, 0x813d, 0x8137, 0x0132,
+ 0x0110, 0x8115, 0x811f, 0x011a, 0x810b, 0x010e, 0x0104, 0x8101,
+ 0x8303, 0x0306, 0x030c, 0x8309, 0x0318, 0x831d, 0x8317, 0x0312,
+ 0x0330, 0x8335, 0x833f, 0x033a, 0x832b, 0x032e, 0x0324, 0x8321,
+ 0x0360, 0x8365, 0x836f, 0x036a, 0x837b, 0x037e, 0x0374, 0x8371,
+ 0x8353, 0x0356, 0x035c, 0x8359, 0x0348, 0x834d, 0x8347, 0x0342,
+ 0x03c0, 0x83c5, 0x83cf, 0x03ca, 0x83db, 0x03de, 0x03d4, 0x83d1,
+ 0x83f3, 0x03f6, 0x03fc, 0x83f9, 0x03e8, 0x83ed, 0x83e7, 0x03e2,
+ 0x83a3, 0x03a6, 0x03ac, 0x83a9, 0x03b8, 0x83bd, 0x83b7, 0x03b2,
+ 0x0390, 0x8395, 0x839f, 0x039a, 0x838b, 0x038e, 0x0384, 0x8381,
+ 0x0280, 0x8285, 0x828f, 0x028a, 0x829b, 0x029e, 0x0294, 0x8291,
+ 0x82b3, 0x02b6, 0x02bc, 0x82b9, 0x02a8, 0x82ad, 0x82a7, 0x02a2,
+ 0x82e3, 0x02e6, 0x02ec, 0x82e9, 0x02f8, 0x82fd, 0x82f7, 0x02f2,
+ 0x02d0, 0x82d5, 0x82df, 0x02da, 0x82cb, 0x02ce, 0x02c4, 0x82c1,
+ 0x8243, 0x0246, 0x024c, 0x8249, 0x0258, 0x825d, 0x8257, 0x0252,
+ 0x0270, 0x8275, 0x827f, 0x027a, 0x826b, 0x026e, 0x0264, 0x8261,
+ 0x0220, 0x8225, 0x822f, 0x022a, 0x823b, 0x023e, 0x0234, 0x8231,
+ 0x8213, 0x0216, 0x021c, 0x8219, 0x0208, 0x820d, 0x8207, 0x0202
+};
+
diff --git a/libs/libmf/source/crc16table.c b/libs/libmf/source/crc16table.c
new file mode 100644
index 00000000..265ef235
--- /dev/null
+++ b/libs/libmf/source/crc16table.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^15 + x^2 + 1 = 0x18005 LSB first */
+
+const uint16_t __code crc_crc16_table[256] = {
+ 0x0000, 0xc0c1, 0xc181, 0x0140, 0xc301, 0x03c0, 0x0280, 0xc241,
+ 0xc601, 0x06c0, 0x0780, 0xc741, 0x0500, 0xc5c1, 0xc481, 0x0440,
+ 0xcc01, 0x0cc0, 0x0d80, 0xcd41, 0x0f00, 0xcfc1, 0xce81, 0x0e40,
+ 0x0a00, 0xcac1, 0xcb81, 0x0b40, 0xc901, 0x09c0, 0x0880, 0xc841,
+ 0xd801, 0x18c0, 0x1980, 0xd941, 0x1b00, 0xdbc1, 0xda81, 0x1a40,
+ 0x1e00, 0xdec1, 0xdf81, 0x1f40, 0xdd01, 0x1dc0, 0x1c80, 0xdc41,
+ 0x1400, 0xd4c1, 0xd581, 0x1540, 0xd701, 0x17c0, 0x1680, 0xd641,
+ 0xd201, 0x12c0, 0x1380, 0xd341, 0x1100, 0xd1c1, 0xd081, 0x1040,
+ 0xf001, 0x30c0, 0x3180, 0xf141, 0x3300, 0xf3c1, 0xf281, 0x3240,
+ 0x3600, 0xf6c1, 0xf781, 0x3740, 0xf501, 0x35c0, 0x3480, 0xf441,
+ 0x3c00, 0xfcc1, 0xfd81, 0x3d40, 0xff01, 0x3fc0, 0x3e80, 0xfe41,
+ 0xfa01, 0x3ac0, 0x3b80, 0xfb41, 0x3900, 0xf9c1, 0xf881, 0x3840,
+ 0x2800, 0xe8c1, 0xe981, 0x2940, 0xeb01, 0x2bc0, 0x2a80, 0xea41,
+ 0xee01, 0x2ec0, 0x2f80, 0xef41, 0x2d00, 0xedc1, 0xec81, 0x2c40,
+ 0xe401, 0x24c0, 0x2580, 0xe541, 0x2700, 0xe7c1, 0xe681, 0x2640,
+ 0x2200, 0xe2c1, 0xe381, 0x2340, 0xe101, 0x21c0, 0x2080, 0xe041,
+ 0xa001, 0x60c0, 0x6180, 0xa141, 0x6300, 0xa3c1, 0xa281, 0x6240,
+ 0x6600, 0xa6c1, 0xa781, 0x6740, 0xa501, 0x65c0, 0x6480, 0xa441,
+ 0x6c00, 0xacc1, 0xad81, 0x6d40, 0xaf01, 0x6fc0, 0x6e80, 0xae41,
+ 0xaa01, 0x6ac0, 0x6b80, 0xab41, 0x6900, 0xa9c1, 0xa881, 0x6840,
+ 0x7800, 0xb8c1, 0xb981, 0x7940, 0xbb01, 0x7bc0, 0x7a80, 0xba41,
+ 0xbe01, 0x7ec0, 0x7f80, 0xbf41, 0x7d00, 0xbdc1, 0xbc81, 0x7c40,
+ 0xb401, 0x74c0, 0x7580, 0xb541, 0x7700, 0xb7c1, 0xb681, 0x7640,
+ 0x7200, 0xb2c1, 0xb381, 0x7340, 0xb101, 0x71c0, 0x7080, 0xb041,
+ 0x5000, 0x90c1, 0x9181, 0x5140, 0x9301, 0x53c0, 0x5280, 0x9241,
+ 0x9601, 0x56c0, 0x5780, 0x9741, 0x5500, 0x95c1, 0x9481, 0x5440,
+ 0x9c01, 0x5cc0, 0x5d80, 0x9d41, 0x5f00, 0x9fc1, 0x9e81, 0x5e40,
+ 0x5a00, 0x9ac1, 0x9b81, 0x5b40, 0x9901, 0x59c0, 0x5880, 0x9841,
+ 0x8801, 0x48c0, 0x4980, 0x8941, 0x4b00, 0x8bc1, 0x8a81, 0x4a40,
+ 0x4e00, 0x8ec1, 0x8f81, 0x4f40, 0x8d01, 0x4dc0, 0x4c80, 0x8c41,
+ 0x4400, 0x84c1, 0x8581, 0x4540, 0x8701, 0x47c0, 0x4680, 0x8641,
+ 0x8201, 0x42c0, 0x4380, 0x8341, 0x4100, 0x81c1, 0x8081, 0x4040
+};
+
diff --git a/libs/libmf/source/crc32.c b/libs/libmf/source/crc32.c
new file mode 100644
index 00000000..c2a1a56c
--- /dev/null
+++ b/libs/libmf/source/crc32.c
@@ -0,0 +1,64 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_byte crc_crc32_byte
+#define crc_table crc_crc32_table
+#define crc_table_asm _crc_crc32_table
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_byte(uint32_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r4,a
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ rl a
+ rl a
+ mov r3,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ mov dpl,a
+ mov a,r3
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ xch a,dph
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r4
+ mov r3,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,b
+ mov dph,a
+ mov dpl,r2
+ mov b,r3
+ mov a,r4
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_byte(uint32_t crc, uint8_t c) __reentrant
+{
+ return (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/source/crc32b.c b/libs/libmf/source/crc32b.c
new file mode 100644
index 00000000..dda2fcfb
--- /dev/null
+++ b/libs/libmf/source/crc32b.c
@@ -0,0 +1,335 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_buf crc_crc32
+#define crc_byte crc_crc32_byte
+#define crc_table_asm _crc_crc32_table
+#define CRCMSB 0
+#elif CRCMODE == 1
+#define crc_buf crc_crc32_msb
+#define crc_byte crc_crc32_msb_byte
+#define crc_table_asm _crc_crc32_msbtable
+#define CRCMSB 1
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r5,a
+ inc r0
+ mov a,@r0
+ mov r6,a
+ inc r0
+ mov a,@r0
+ mov r7,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00011$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ mov b,r6
+ mov a,r7
+ ret
+
+00011$:
+ sjmp 00010$
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+#if !CRCMSB
+ ;; lsb: crc = (crc >> 8) ^ crc_table[((uint8_t)crc ^ c) & (uint8_t)0xff]
+ xrl a,r4
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ clr a
+ movc a,@a+dptr
+ xrl a,r5
+ mov r4,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r6
+ mov r5,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r7
+ mov r6,a
+ mov a,#3
+ movc a,@a+dptr
+ mov r7,a
+#else
+ ;; msb: crc = (crc << 8) ^ crc_table[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff]
+ xrl a,r7
+ rl a
+ rl a
+ mov dpl,a
+ anl a,#0xfc
+ add a,#crc_table_asm
+ xch a,dpl
+ anl a,#0x03
+ addc a,#(crc_table_asm >> 8)
+ mov dph,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,r6
+ mov r7,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r5
+ mov r6,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r4
+ mov r5,a
+ clr a
+ movc a,@a+dptr
+ mov r4,a
+#endif
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/source/crc32msb.c b/libs/libmf/source/crc32msb.c
new file mode 100644
index 00000000..a78d175b
--- /dev/null
+++ b/libs/libmf/source/crc32msb.c
@@ -0,0 +1,65 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_msb_byte crc_crc32_msb_byte
+#define crc_msbtable crc_crc32_msbtable
+#define crc_msbtable_asm _crc_crc32_msbtable
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint32_t crc_msb_byte(uint32_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r2,a
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,r2
+ rl a
+ rl a
+ mov r3,a
+ anl a,#0xfc
+ add a,#crc_msbtable_asm
+ xch a,dpl
+ mov r2,a
+ mov a,r3
+ anl a,#0x03
+ addc a,#(crc_msbtable_asm >> 8)
+ xch a,dph
+ mov r3,a
+ mov a,#1
+ movc a,@a+dptr
+ xrl a,r2
+ mov r2,a
+ mov a,#2
+ movc a,@a+dptr
+ xrl a,r3
+ mov r3,a
+ mov a,#3
+ movc a,@a+dptr
+ xrl a,b
+ mov r4,a
+ clr a
+ movc a,@a+dptr
+ mov dpl,a
+ mov dph,r2
+ mov b,r3
+ mov a,r4
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t crc_msb_byte(uint32_t crc, uint8_t c) __reentrant
+{
+ return (crc << 8) ^ crc_msbtable[((uint8_t)(crc >> 24) ^ c) & (uint8_t)0xff];
+}
+
+#endif
diff --git a/libs/libmf/source/crc32msbtable.c b/libs/libmf/source/crc32msbtable.c
new file mode 100644
index 00000000..512f5831
--- /dev/null
+++ b/libs/libmf/source/crc32msbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1 = 0x104c11db7 MSB first */
+
+const uint32_t __code crc_crc32_msbtable[256] = {
+ 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005,
+ 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd,
+ 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75,
+ 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd,
+ 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5,
+ 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d,
+ 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95,
+ 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d,
+ 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072,
+ 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca,
+ 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02,
+ 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba,
+ 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692,
+ 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a,
+ 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2,
+ 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a,
+ 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb,
+ 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53,
+ 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b,
+ 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623,
+ 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b,
+ 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3,
+ 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b,
+ 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3,
+ 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c,
+ 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24,
+ 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec,
+ 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654,
+ 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c,
+ 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4,
+ 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c,
+ 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
+};
+
diff --git a/libs/libmf/source/crc32table.c b/libs/libmf/source/crc32table.c
new file mode 100644
index 00000000..128e3939
--- /dev/null
+++ b/libs/libmf/source/crc32table.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1 = 0x104c11db7 LSB first */
+
+const uint32_t __code crc_crc32_table[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+ 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+ 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+ 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+ 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+ 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+ 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+ 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+ 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+ 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+ 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+ 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+ 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+ 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+ 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+ 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+ 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+ 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+ 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+ 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+ 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+ 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
diff --git a/libs/libmf/source/crc8.c b/libs/libmf/source/crc8.c
new file mode 100644
index 00000000..8f6c3f53
--- /dev/null
+++ b/libs/libmf/source/crc8.c
@@ -0,0 +1,41 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_byte crc_crc8ccitt_byte
+#define crc_table crc_crc8ccitt_table
+#define crc_table_asm _crc_crc8ccitt_table
+#elif CRCMODE == 1
+#define crc_byte crc_crc8onewire_byte
+#define crc_table crc_crc8onewire_table
+#define crc_table_asm _crc_crc8onewire_table
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_table[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/source/crc8b.c b/libs/libmf/source/crc8b.c
new file mode 100644
index 00000000..18f2264a
--- /dev/null
+++ b/libs/libmf/source/crc8b.c
@@ -0,0 +1,130 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_buf crc_crc8ccitt
+#define crc_byte crc_crc8ccitt_byte
+#define crc_table_asm _crc_crc8ccitt_table
+#define CRCMSB 0
+#elif CRCMODE == 1
+#define crc_buf crc_crc8ccitt_msb
+#define crc_byte crc_crc8ccitt_msb_byte
+#define crc_table_asm _crc_crc8ccitt_msbtable
+#define CRCMSB 1
+#elif CRCMODE == 2
+#define crc_buf crc_crc8onewire
+#define crc_byte crc_crc8onewire_byte
+#define crc_table_asm _crc_crc8onewire_table
+#define CRCMSB 0
+#elif CRCMODE == 3
+#define crc_buf crc_crc8onewire_msb
+#define crc_byte crc_crc8onewire_msb_byte
+#define crc_table_asm _crc_crc8onewire_msbtable
+#define CRCMSB 1
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant __naked
+{
+ buf;
+ buflen;
+ crc;
+ __asm;
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,@r0
+ mov r4,a
+ inc r0
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00040$
+ djnz r3,00040$
+ sjmp 00001$
+
+00030$: movx a,@r0
+ inc r0
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ djnz r2,00030$
+ djnz r3,00030$
+
+00001$:
+ mov dpl,r4
+ ret
+
+00020$: movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r1,dph
+ ;; lsb/msb: crc = crc_table[crc ^ c]
+ xrl a,r4
+ mov dptr,#crc_table_asm
+ movc a,@a+dptr
+ mov r4,a
+ ;; loop
+ mov dph,r1
+ mov dpl,r0
+ djnz r2,00010$
+ djnz r3,00010$
+ sjmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_buf(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant
+{
+ if (!buflen)
+ return crc;
+ do {
+ crc = crc_byte(crc, *buf++);
+ } while (--buflen);
+ return crc;
+}
+
+#endif
diff --git a/libs/libmf/source/crc8ccitt.c b/libs/libmf/source/crc8ccitt.c
new file mode 100644
index 00000000..d2bcd9c0
--- /dev/null
+++ b/libs/libmf/source/crc8ccitt.c
@@ -0,0 +1,155 @@
+#include "ax8052.h"
+#include "libmfcrc.h"
+
+
+#if defined(SDCC)
+
+uint8_t crc8_ccitt_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r0,sp
+ dec r0
+ dec r0
+ mov a,@r0
+ xrl a,dpl
+ mov r0,#8
+00000$: clr c
+ rlc a
+ jnc 00001$
+ xrl a,#0x07
+00001$: djnz r0,00000$
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t crc8_ccitt(const __generic uint8_t *buf, uint8_t len, uint8_t init) __reentrant __naked
+{
+ buf;
+ len;
+ init;
+ __asm;
+ mov r0,sp
+ dec r0
+ dec r0
+ mov a,@r0
+ mov r2,a
+ dec r0
+ mov a,@r0
+ mov r3,a
+ jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; data
+00000$: mov a,@r0
+ inc r0
+ xrl a,r3
+ mov r4,#8
+00001$: clr c
+ rlc a
+ jnc 00002$
+ xrl a,#0x07
+00002$: djnz r4,00001$
+ mov r3,a
+ djnz r2,00000$
+ sjmp 00040$
+
+ ;; code
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ xrl a,r3
+ mov r4,#8
+00011$: clr c
+ rlc a
+ jnc 00012$
+ xrl a,#0x07
+00012$: djnz r4,00011$
+ mov r3,a
+ djnz r2,00010$
+ sjmp 00040$
+
+ ;; xdata
+00020$: movx a,@dptr
+ inc dptr
+ xrl a,r3
+ mov r4,#8
+00021$: clr c
+ rlc a
+ jnc 00022$
+ xrl a,#0x07
+00022$: djnz r4,00021$
+ mov r3,a
+ djnz r2,00020$
+ sjmp 00040$
+
+ ;; pdata
+00030$: movx a,@r0
+ inc r0
+ xrl a,r3
+ mov r4,#8
+00031$: clr c
+ rlc a
+ jnc 00032$
+ xrl a,#0x07
+00032$: djnz r4,00031$
+ mov r3,a
+ djnz r2,00030$
+ ;sjmp 00040$
+
+00040$: mov dpl,r3
+ ret
+ __endasm;
+}
+
+#else
+
+#if defined __CX51__ || defined __C51__
+
+static uint8_t crc8_reduce(uint8_t idx)
+{
+#pragma asm
+ mov a,r7
+ mov r0,#8
+c8red0: clr c
+ rlc a
+ jnc c8red1
+ xrl a,#0x07
+c8red1: djnz r0,c8red0
+ mov r7,a
+#pragma endasm
+}
+
+#else
+
+static __reentrantb uint8_t crc8_reduce(uint8_t idx) __reentrant
+{
+ uint8_t cnt = 8;
+ do {
+ uint8_t m = idx & 0x80;
+ idx <<= 1;
+ if (m)
+ idx ^= 0x07;
+ } while (--cnt);
+ return idx;
+}
+
+#endif
+
+__reentrantb uint8_t crc8_ccitt_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc8_reduce(crc ^ c);
+}
+
+__reentrantb uint8_t crc8_ccitt(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant
+{
+ do {
+ init = crc8_reduce(init ^ *buf++);
+ } while (len--);
+ return init;
+}
+
+#endif
diff --git a/libs/libmf/source/crc8ccittmsbtable.c b/libs/libmf/source/crc8ccittmsbtable.c
new file mode 100644
index 00000000..33e20178
--- /dev/null
+++ b/libs/libmf/source/crc8ccittmsbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc8, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^8 + x^2 + x^1 + 1 = 0x1000 MSB first */
+
+const uint8_t __code crc_crc8ccitt_msbtable[256] = {
+ 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
+ 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d,
+ 0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65,
+ 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d,
+ 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5,
+ 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd,
+ 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85,
+ 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd,
+ 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2,
+ 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea,
+ 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2,
+ 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a,
+ 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32,
+ 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a,
+ 0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42,
+ 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a,
+ 0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c,
+ 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4,
+ 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec,
+ 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4,
+ 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c,
+ 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44,
+ 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c,
+ 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34,
+ 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b,
+ 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63,
+ 0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b,
+ 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13,
+ 0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb,
+ 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83,
+ 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb,
+ 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3
+};
+
diff --git a/libs/libmf/source/crc8ccitttable.c b/libs/libmf/source/crc8ccitttable.c
new file mode 100644
index 00000000..4b88b5a8
--- /dev/null
+++ b/libs/libmf/source/crc8ccitttable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc8, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^8 + x^2 + x^1 + 1 = 0x1000 LSB first */
+
+const uint8_t __code crc_crc8ccitt_table[256] = {
+ 0x00, 0x91, 0xe3, 0x72, 0x07, 0x96, 0xe4, 0x75,
+ 0x0e, 0x9f, 0xed, 0x7c, 0x09, 0x98, 0xea, 0x7b,
+ 0x1c, 0x8d, 0xff, 0x6e, 0x1b, 0x8a, 0xf8, 0x69,
+ 0x12, 0x83, 0xf1, 0x60, 0x15, 0x84, 0xf6, 0x67,
+ 0x38, 0xa9, 0xdb, 0x4a, 0x3f, 0xae, 0xdc, 0x4d,
+ 0x36, 0xa7, 0xd5, 0x44, 0x31, 0xa0, 0xd2, 0x43,
+ 0x24, 0xb5, 0xc7, 0x56, 0x23, 0xb2, 0xc0, 0x51,
+ 0x2a, 0xbb, 0xc9, 0x58, 0x2d, 0xbc, 0xce, 0x5f,
+ 0x70, 0xe1, 0x93, 0x02, 0x77, 0xe6, 0x94, 0x05,
+ 0x7e, 0xef, 0x9d, 0x0c, 0x79, 0xe8, 0x9a, 0x0b,
+ 0x6c, 0xfd, 0x8f, 0x1e, 0x6b, 0xfa, 0x88, 0x19,
+ 0x62, 0xf3, 0x81, 0x10, 0x65, 0xf4, 0x86, 0x17,
+ 0x48, 0xd9, 0xab, 0x3a, 0x4f, 0xde, 0xac, 0x3d,
+ 0x46, 0xd7, 0xa5, 0x34, 0x41, 0xd0, 0xa2, 0x33,
+ 0x54, 0xc5, 0xb7, 0x26, 0x53, 0xc2, 0xb0, 0x21,
+ 0x5a, 0xcb, 0xb9, 0x28, 0x5d, 0xcc, 0xbe, 0x2f,
+ 0xe0, 0x71, 0x03, 0x92, 0xe7, 0x76, 0x04, 0x95,
+ 0xee, 0x7f, 0x0d, 0x9c, 0xe9, 0x78, 0x0a, 0x9b,
+ 0xfc, 0x6d, 0x1f, 0x8e, 0xfb, 0x6a, 0x18, 0x89,
+ 0xf2, 0x63, 0x11, 0x80, 0xf5, 0x64, 0x16, 0x87,
+ 0xd8, 0x49, 0x3b, 0xaa, 0xdf, 0x4e, 0x3c, 0xad,
+ 0xd6, 0x47, 0x35, 0xa4, 0xd1, 0x40, 0x32, 0xa3,
+ 0xc4, 0x55, 0x27, 0xb6, 0xc3, 0x52, 0x20, 0xb1,
+ 0xca, 0x5b, 0x29, 0xb8, 0xcd, 0x5c, 0x2e, 0xbf,
+ 0x90, 0x01, 0x73, 0xe2, 0x97, 0x06, 0x74, 0xe5,
+ 0x9e, 0x0f, 0x7d, 0xec, 0x99, 0x08, 0x7a, 0xeb,
+ 0x8c, 0x1d, 0x6f, 0xfe, 0x8b, 0x1a, 0x68, 0xf9,
+ 0x82, 0x13, 0x61, 0xf0, 0x85, 0x14, 0x66, 0xf7,
+ 0xa8, 0x39, 0x4b, 0xda, 0xaf, 0x3e, 0x4c, 0xdd,
+ 0xa6, 0x37, 0x45, 0xd4, 0xa1, 0x30, 0x42, 0xd3,
+ 0xb4, 0x25, 0x57, 0xc6, 0xb3, 0x22, 0x50, 0xc1,
+ 0xba, 0x2b, 0x59, 0xc8, 0xbd, 0x2c, 0x5e, 0xcf
+};
+
diff --git a/libs/libmf/source/crc8msb.c b/libs/libmf/source/crc8msb.c
new file mode 100644
index 00000000..6a0256f0
--- /dev/null
+++ b/libs/libmf/source/crc8msb.c
@@ -0,0 +1,41 @@
+#include "libmfcrc.h"
+
+#if CRCMODE == 0
+#define crc_msb_byte crc_crc8ccitt_msb_byte
+#define crc_msbtable crc_crc8ccitt_msbtable
+#define crc_msbtable_asm _crc_crc8ccitt_msbtable
+#elif CRCMODE == 1
+#define crc_msb_byte crc_crc8onewire_msb_byte
+#define crc_msbtable crc_crc8onewire_msbtable
+#define crc_msbtable_asm _crc_crc8onewire_msbtable
+#else
+#error "invalid CRCMODE"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ xrl a,dpl
+ mov dptr,#crc_msbtable_asm
+ movc a,@a+dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t crc_msb_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc_msbtable[crc ^ c];
+}
+
+#endif
diff --git a/libs/libmf/source/crc8onewire.c b/libs/libmf/source/crc8onewire.c
new file mode 100644
index 00000000..b80158ae
--- /dev/null
+++ b/libs/libmf/source/crc8onewire.c
@@ -0,0 +1,155 @@
+#include "ax8052.h"
+#include "libmfcrc.h"
+
+
+#if defined(SDCC)
+
+uint8_t crc8_onewire_byte(uint8_t crc, uint8_t c) __reentrant __naked
+{
+ crc;
+ c;
+ __asm;
+ mov r0,sp
+ dec r0
+ dec r0
+ mov a,@r0
+ xrl a,dpl
+ mov r0,#8
+00000$: clr c
+ rlc a
+ jnc 00001$
+ xrl a,#0x31
+00001$: djnz r0,00000$
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t crc8_onewire(const __generic uint8_t *buf, uint8_t len, uint8_t init) __reentrant __naked
+{
+ buf;
+ len;
+ init;
+ __asm;
+ mov r0,sp
+ dec r0
+ dec r0
+ mov a,@r0
+ mov r2,a
+ dec r0
+ mov a,@r0
+ mov r3,a
+ jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00020$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; data
+00000$: mov a,@r0
+ inc r0
+ xrl a,r3
+ mov r4,#8
+00001$: clr c
+ rlc a
+ jnc 00002$
+ xrl a,#0x31
+00002$: djnz r4,00001$
+ mov r3,a
+ djnz r2,00000$
+ sjmp 00040$
+
+ ;; code
+00010$: clr a
+ movc a,@a+dptr
+ inc dptr
+ xrl a,r3
+ mov r4,#8
+00011$: clr c
+ rlc a
+ jnc 00012$
+ xrl a,#0x31
+00012$: djnz r4,00011$
+ mov r3,a
+ djnz r2,00010$
+ sjmp 00040$
+
+ ;; xdata
+00020$: movx a,@dptr
+ inc dptr
+ xrl a,r3
+ mov r4,#8
+00021$: clr c
+ rlc a
+ jnc 00022$
+ xrl a,#0x31
+00022$: djnz r4,00021$
+ mov r3,a
+ djnz r2,00020$
+ sjmp 00040$
+
+ ;; pdata
+00030$: movx a,@r0
+ inc r0
+ xrl a,r3
+ mov r4,#8
+00031$: clr c
+ rlc a
+ jnc 00032$
+ xrl a,#0x31
+00032$: djnz r4,00031$
+ mov r3,a
+ djnz r2,00030$
+ ;sjmp 00040$
+
+00040$: mov dpl,r3
+ ret
+ __endasm;
+}
+
+#else
+
+#if defined __CX51__ || defined __C51__
+
+static uint8_t crc8_reduce(uint8_t idx)
+{
+#pragma asm
+ mov a,r7
+ mov r0,#8
+c8red0: clr c
+ rlc a
+ jnc c8red1
+ xrl a,#0x31
+c8red1: djnz r0,c8red0
+ mov r7,a
+#pragma endasm
+}
+
+#else
+
+static __reentrantb uint8_t crc8_reduce(uint8_t idx) __reentrant
+{
+ uint8_t cnt = 8;
+ do {
+ uint8_t m = idx & 0x80;
+ idx <<= 1;
+ if (m)
+ idx ^= 0x31;
+ } while (--cnt);
+ return idx;
+}
+
+#endif
+
+__reentrantb uint8_t crc8_onewire_byte(uint8_t crc, uint8_t c) __reentrant
+{
+ return crc8_reduce(crc ^ c);
+}
+
+__reentrantb uint8_t crc8_onewire(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant
+{
+ do {
+ init = crc8_reduce(init ^ *buf++);
+ } while (len--);
+ return init;
+}
+
+#endif
diff --git a/libs/libmf/source/crc8onewiremsbtable.c b/libs/libmf/source/crc8onewiremsbtable.c
new file mode 100644
index 00000000..1a1162fc
--- /dev/null
+++ b/libs/libmf/source/crc8onewiremsbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc8, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^8 + x^5 + x^4 + 1 = 0x10001 MSB first */
+
+const uint8_t __code crc_crc8onewire_msbtable[256] = {
+ 0x00, 0x31, 0x62, 0x53, 0xc4, 0xf5, 0xa6, 0x97,
+ 0xb9, 0x88, 0xdb, 0xea, 0x7d, 0x4c, 0x1f, 0x2e,
+ 0x43, 0x72, 0x21, 0x10, 0x87, 0xb6, 0xe5, 0xd4,
+ 0xfa, 0xcb, 0x98, 0xa9, 0x3e, 0x0f, 0x5c, 0x6d,
+ 0x86, 0xb7, 0xe4, 0xd5, 0x42, 0x73, 0x20, 0x11,
+ 0x3f, 0x0e, 0x5d, 0x6c, 0xfb, 0xca, 0x99, 0xa8,
+ 0xc5, 0xf4, 0xa7, 0x96, 0x01, 0x30, 0x63, 0x52,
+ 0x7c, 0x4d, 0x1e, 0x2f, 0xb8, 0x89, 0xda, 0xeb,
+ 0x3d, 0x0c, 0x5f, 0x6e, 0xf9, 0xc8, 0x9b, 0xaa,
+ 0x84, 0xb5, 0xe6, 0xd7, 0x40, 0x71, 0x22, 0x13,
+ 0x7e, 0x4f, 0x1c, 0x2d, 0xba, 0x8b, 0xd8, 0xe9,
+ 0xc7, 0xf6, 0xa5, 0x94, 0x03, 0x32, 0x61, 0x50,
+ 0xbb, 0x8a, 0xd9, 0xe8, 0x7f, 0x4e, 0x1d, 0x2c,
+ 0x02, 0x33, 0x60, 0x51, 0xc6, 0xf7, 0xa4, 0x95,
+ 0xf8, 0xc9, 0x9a, 0xab, 0x3c, 0x0d, 0x5e, 0x6f,
+ 0x41, 0x70, 0x23, 0x12, 0x85, 0xb4, 0xe7, 0xd6,
+ 0x7a, 0x4b, 0x18, 0x29, 0xbe, 0x8f, 0xdc, 0xed,
+ 0xc3, 0xf2, 0xa1, 0x90, 0x07, 0x36, 0x65, 0x54,
+ 0x39, 0x08, 0x5b, 0x6a, 0xfd, 0xcc, 0x9f, 0xae,
+ 0x80, 0xb1, 0xe2, 0xd3, 0x44, 0x75, 0x26, 0x17,
+ 0xfc, 0xcd, 0x9e, 0xaf, 0x38, 0x09, 0x5a, 0x6b,
+ 0x45, 0x74, 0x27, 0x16, 0x81, 0xb0, 0xe3, 0xd2,
+ 0xbf, 0x8e, 0xdd, 0xec, 0x7b, 0x4a, 0x19, 0x28,
+ 0x06, 0x37, 0x64, 0x55, 0xc2, 0xf3, 0xa0, 0x91,
+ 0x47, 0x76, 0x25, 0x14, 0x83, 0xb2, 0xe1, 0xd0,
+ 0xfe, 0xcf, 0x9c, 0xad, 0x3a, 0x0b, 0x58, 0x69,
+ 0x04, 0x35, 0x66, 0x57, 0xc0, 0xf1, 0xa2, 0x93,
+ 0xbd, 0x8c, 0xdf, 0xee, 0x79, 0x48, 0x1b, 0x2a,
+ 0xc1, 0xf0, 0xa3, 0x92, 0x05, 0x34, 0x67, 0x56,
+ 0x78, 0x49, 0x1a, 0x2b, 0xbc, 0x8d, 0xde, 0xef,
+ 0x82, 0xb3, 0xe0, 0xd1, 0x46, 0x77, 0x24, 0x15,
+ 0x3b, 0x0a, 0x59, 0x68, 0xff, 0xce, 0x9d, 0xac
+};
+
diff --git a/libs/libmf/source/crc8onewiretable.c b/libs/libmf/source/crc8onewiretable.c
new file mode 100644
index 00000000..5ad46565
--- /dev/null
+++ b/libs/libmf/source/crc8onewiretable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc8, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^8 + x^5 + x^4 + 1 = 0x10001 LSB first */
+
+const uint8_t __code crc_crc8onewire_table[256] = {
+ 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
+ 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
+ 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+ 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
+ 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
+ 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+ 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
+ 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
+ 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+ 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
+ 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
+ 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+ 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
+ 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
+ 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+ 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
+ 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
+ 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+ 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
+ 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
+ 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+ 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
+ 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
+ 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+ 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
+ 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
+ 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+ 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
+ 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
+ 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+ 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
+ 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
+};
+
diff --git a/libs/libmf/source/crcccittmsbtable.c b/libs/libmf/source/crcccittmsbtable.c
new file mode 100644
index 00000000..df3eeffb
--- /dev/null
+++ b/libs/libmf/source/crcccittmsbtable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^12 + x^5 + 1 = 0x11021 MSB first */
+
+const uint16_t __code crc_ccitt_msbtable[256] = {
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
+ 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+ 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
+ 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
+ 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
+ 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
+ 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
+ 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+ 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
+ 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
+ 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
+ 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
+ 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
+ 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
+ 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+ 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
+ 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
+ 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+ 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
+ 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
+ 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
+ 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
+ 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
+};
+
diff --git a/libs/libmf/source/crcccitttable.c b/libs/libmf/source/crcccitttable.c
new file mode 100644
index 00000000..b4c86f9c
--- /dev/null
+++ b/libs/libmf/source/crcccitttable.c
@@ -0,0 +1,41 @@
+/* automatically generated by gencrc16, do not edit! */
+
+#include "libmfcrc.h"
+
+/* Polynomial: x^16 + x^12 + x^5 + 1 = 0x11021 LSB first */
+
+const uint16_t __code crc_ccitt_table[256] = {
+ 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+ 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+ 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+ 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+ 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+ 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+ 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+ 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+ 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+ 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+ 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+ 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+ 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+ 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+ 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+ 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+ 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+ 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+ 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+ 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+ 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+ 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+ 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+ 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+ 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+ 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+ 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+ 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+ 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+ 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+ 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+ 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
diff --git a/libs/libmf/source/dbglink.c b/libs/libmf/source/dbglink.c
new file mode 100644
index 00000000..b32eda01
--- /dev/null
+++ b/libs/libmf/source/dbglink.c
@@ -0,0 +1,963 @@
+#include "ax8052.h"
+#include "libmfdbglink.h"
+
+static volatile uint8_t __data dbglink_fiforxwr;
+static volatile uint8_t __data dbglink_fiforxrd;
+static volatile uint8_t __data dbglink_fifotxwr;
+static volatile uint8_t __data dbglink_fifotxrd;
+
+extern uint8_t __xdata dbglink_rxbuffer[];
+extern uint8_t __xdata dbglink_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code dbglink_rxbuffer_size[];
+extern const uint8_t __code dbglink_txbuffer_size[];
+#endif
+
+#if defined(SDCC)
+
+static void dummy0(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ .area DBGLINK0 (CODE)
+ .area DBGLINK1 (CODE)
+ .area DBGLINK2 (CODE)
+ .area DBGLINK3 (CODE)
+ .area DBGLINK4 (CODE)
+ .area DBGLINK5 (CODE)
+
+ .area HOME (CODE)
+ __endasm;
+}
+
+static __reentrantb void dbglink_iocore(void) __reentrant __naked;
+
+void dbglink_irq(void) __interrupt(21) __naked
+{
+ __asm;
+ push acc
+ push psw
+ push _DPS
+ push dpl
+ push dph
+ push b
+ mov _DPS,#0
+ mov psw,#0
+ lcall _dbglink_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop _DPS
+ pop psw
+ pop acc
+ reti
+ __endasm;
+}
+
+uint8_t dbglink_poll(void) __reentrant __naked
+{
+ __asm;
+ mov a,#0x80
+ anl a,_IE
+ rl a
+ mov b,a
+ clr _EA
+ lcall _dbglink_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov _EA,c
+ mov dpl,a
+ ret
+
+ .area HOME (CODE)
+ .area DBGLINK0 (CODE)
+ .area DBGLINK1 (CODE)
+ .area DBGLINK2 (CODE)
+ .area DBGLINK3 (CODE)
+ .area DBGLINK4 (CODE)
+ .area DBGLINK5 (CODE)
+
+ .area DBGLINK0 (CODE)
+ __endasm;
+}
+
+static __reentrantb void dbglink_iocore(void) __reentrant __naked
+{
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,_DBGLNKSTAT
+ jnb acc.0,iocnorx
+ mov dptr,#_dbglink_rxbuffer
+ mov a,_dbglink_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ mov a,#_dbglink_buffer_negsize+3-00010$
+ movc a,@a+pc
+00010$: add a,_dbglink_fiforxwr
+ jc 00001$
+ mov a,_dbglink_fiforxwr
+ inc a
+00001$: cjne a,_dbglink_fiforxrd,00000$
+ anl _DBGLNKSTAT,#~0x40
+ sjmp iocnorx
+00000$: mov _dbglink_fiforxwr,a
+ mov a,_DBGLNKBUF
+ movx @dptr,a
+ orl _DBGLNKSTAT,#0x40
+ setb _B_1
+iocnorx:
+ mov a,_DBGLNKSTAT
+ jnb acc.2,iocnotx
+ mov a,_dbglink_fifotxrd
+ cjne a,_dbglink_fifotxwr,00000$
+ anl _DBGLNKSTAT,#~0x80
+ sjmp iocnotx
+00000$: mov dptr,#_dbglink_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov _DBGLNKBUF,a
+ mov a,#_dbglink_buffer_negsize+1-00010$
+ movc a,@a+pc
+00010$: add a,_dbglink_fifotxrd
+ jc 00001$
+ mov a,_dbglink_fifotxrd
+ inc a
+00001$: mov _dbglink_fifotxrd,a
+ orl _DBGLNKSTAT,#0x80
+ setb _B_2
+iocnotx:
+ ret
+ __endasm;
+}
+
+void dbglink_rxadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_dbglink_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_dbglink_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _dbglink_fiforxrd,a
+ orl _DBGLNKSTAT,#0x40
+00000$: ret
+ __endasm;
+}
+
+void dbglink_txadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_dbglink_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_dbglink_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _dbglink_fifotxwr,a
+ orl _DBGLNKSTAT,#0x80
+00000$: ret
+ __endasm;
+}
+
+__reentrantb const uint8_t __xdata *dbglink_rxbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_dbglink_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_dbglink_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_dbglink_rxbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+ __endasm;
+}
+
+__reentrantb uint8_t __xdata *dbglink_txbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_dbglink_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_dbglink_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_dbglink_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+
+_dbglink_buffer_negsize:
+ .area DBGLINK3 (CODE)
+ __endasm;
+}
+
+uint8_t dbglink_txfreelinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_dbglink_fifotxrd
+ setb c
+ subb a,_dbglink_fifotxwr
+ jnc 00000$
+ mov a,_dbglink_fifotxrd
+ add a,#0xff
+ cpl c
+ mov a,#_dbglink_buffer_size-00001$
+ movc a,@a+pc
+00001$: subb a,_dbglink_fifotxwr
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t dbglink_txfree(void) __reentrant __naked
+{
+ __asm;
+ mov a,_dbglink_fifotxrd
+ setb c
+ subb a,_dbglink_fifotxwr
+ mov dpl,a
+ jnc 00000$
+ mov a,#_dbglink_buffer_size-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t dbglink_rxcountlinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_dbglink_fiforxwr
+ clr c
+ subb a,_dbglink_fiforxrd
+ jnc 00000$
+ mov a,#_dbglink_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: clr c
+ subb a,_dbglink_fiforxrd
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t dbglink_rxcount(void) __reentrant __naked
+{
+ __asm;
+ mov a,_dbglink_fiforxwr
+ clr c
+ subb a,_dbglink_fiforxrd
+ mov dpl,a
+ jnc 00000$
+ mov a,#_dbglink_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t dbglink_txbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_dbglink_buffer_size-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t dbglink_rxbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_dbglink_buffer_size+1-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+
+_dbglink_buffer_size:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+uint8_t dbglink_rxpeek(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ lcall _dbglink_rxbufptr
+ movx a,@dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+void dbglink_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+_dbglink_txpoke_hexentry:
+ lcall _dbglink_txbufptr
+ mov a,@r0
+ movx @dptr,a
+ pop ar0
+ ret
+ __endasm;
+}
+
+void dbglink_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ anl a,#0x0F
+ add a,#256-10
+ jnc 00000$
+ add a,#'A-'9-1
+00000$: add a,#10+'0 ; '
+ mov @r0,a
+ ljmp _dbglink_txpoke_hexentry
+ __endasm;
+}
+
+uint8_t dbglink_txidle(void) __reentrant __naked
+{
+ __asm;
+ mov a,_DBGLNKSTAT
+ anl a,#0x84
+ cjne a,#0x04,00000$
+ mov dpl,#1
+ ret
+00000$:
+ mov dpl,#0
+ ret
+ __endasm;
+}
+
+static void wtimer_cansleep_dummy(void) __naked
+{
+ __asm
+ .area HOME (CODE)
+ .area WTCANSLP0 (CODE)
+ .area WTCANSLP1 (CODE)
+ .area WTCANSLP2 (CODE)
+
+ .area WTCANSLP1 (CODE)
+ lcall _dbglink_txidle
+ mov a,dpl
+ jnz 00000$
+ ret
+00000$:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+static __reentrantb void dbglink_iocore(void) __reentrant __naked;
+
+void dbglink_irq(void) interrupt 21
+{
+#pragma asm
+ push acc
+ push psw
+ push DPS
+ push dpl
+ push dph
+ push b
+ mov DPS,#0
+ mov psw,#0
+ lcall _dbglink_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop DPS
+ pop psw
+ pop acc
+#pragma endasm
+}
+
+uint8_t dbglink_poll(void) __reentrant
+{
+#pragma asm
+ mov a,#0x80
+ anl a,IE
+ rl a
+ mov b,a
+ clr EA
+ lcall _dbglink_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov EA,c
+ mov r7,a
+#pragma endasm
+}
+
+static __reentrantb void dbglink_iocore(void) __reentrant __naked
+{
+ dbglink_rxbuffer[0];
+ dbglink_rxbuffer_size[0];
+ dbglink_txbuffer[0];
+ dbglink_txbuffer_size[0];
+#pragma asm
+;ar2 equ 0x02
+;ar3 equ 0x03
+;ar4 equ 0x04
+;ar5 equ 0x05
+;ar6 equ 0x06
+;ar7 equ 0x07
+;ar0 equ 0x00
+;ar1 equ 0x01
+
+_dbglink_iocore:
+ mov a,DBGLNKSTAT
+ jnb acc.0,iocnorx
+ clr a
+ mov dptr,#dbglink_rxbuffer_size+2
+ movc a,@a+dptr
+ push acc
+ mov dptr,#dbglink_rxbuffer
+ mov a,dbglink_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ pop acc
+ add a,dbglink_fiforxwr
+ jc ioc1
+ mov a,dbglink_fiforxwr
+ inc a
+ioc1: cjne a,dbglink_fiforxrd,ioc0
+ anl DBGLNKSTAT,#~0x40
+ sjmp iocnorx
+ioc0: mov dbglink_fiforxwr,a
+ mov a,DBGLNKBUF
+ movx @dptr,a
+ orl DBGLNKSTAT,#0x40
+ setb B_1
+iocnorx:
+ mov a,DBGLNKSTAT
+ jnb acc.2,iocnotx
+ mov a,dbglink_fifotxrd
+ cjne a,dbglink_fifotxwr,ioc2
+ anl DBGLNKSTAT,#~0x80
+ sjmp iocnotx
+ioc2: mov dptr,#dbglink_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov DBGLNKBUF,a
+ clr a
+ mov dptr,#dbglink_txbuffer_size+2
+ movc a,@a+dptr
+ add a,dbglink_fifotxrd
+ jc ioc3
+ mov a,dbglink_fifotxrd
+ inc a
+ioc3: mov dbglink_fifotxrd,a
+ orl DBGLNKSTAT,#0x80
+ setb B_2
+iocnotx:
+#pragma endasm
+}
+
+__reentrantb void dbglink_rxadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#dbglink_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz rxad0
+ add a,dbglink_fiforxrd
+ jnc rxad2
+ add a,r7
+ sjmp rxad1
+rxad2: xch a,r7
+ add a,r7
+ jc rxad1
+ mov a,r7
+rxad1: mov dbglink_fiforxrd,a
+ orl DBGLNKSTAT,#0x40
+rxad0:
+#pragma endasm
+}
+
+__reentrantb void dbglink_txadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#dbglink_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz txad0
+ add a,dbglink_fifotxwr
+ jnc txad2
+ add a,r7
+ sjmp txad1
+txad2: xch a,r7
+ add a,r7
+ jc txad1
+ mov a,r7
+txad1: mov dbglink_fifotxwr,a
+ orl DBGLNKSTAT,#0x80
+txad0:
+#pragma endasm
+}
+
+__reentrantb const uint8_t __xdata *dbglink_rxbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_dbglink_rxbufptr:
+ clr a
+ mov dptr,#dbglink_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,dbglink_fiforxrd
+ jnc rxp2
+ add a,r7
+ sjmp rxp1
+rxp2: xch a,r7
+ add a,r7
+ jc rxp1
+ mov a,r7
+rxp1: mov dptr,#dbglink_rxbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t __xdata *dbglink_txbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_dbglink_txbufptr:
+ clr a
+ mov dptr,#dbglink_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,dbglink_fifotxwr
+ jnc txp2
+ add a,r7
+ sjmp txp1
+txp2: xch a,r7
+ add a,r7
+ jc txp1
+ mov a,r7
+txp1: mov dptr,#dbglink_txbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_txfreelinear(void) __reentrant
+{
+#pragma asm
+ mov a,dbglink_fifotxrd
+ setb c
+ subb a,dbglink_fifotxwr
+ jnc txfrl0
+ mov a,dbglink_fifotxrd
+ add a,#0xff
+ cpl c
+ clr a
+ mov dptr,#dbglink_txbuffer_size
+ movc a,@a+dptr
+ subb a,dbglink_fifotxwr
+txfrl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_txfree(void) __reentrant
+{
+#pragma asm
+ mov a,dbglink_fifotxrd
+ setb c
+ subb a,dbglink_fifotxwr
+ mov r7,a
+ jnc txfr0
+ clr a
+ mov dptr,#dbglink_txbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+txfr0:
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_rxcountlinear(void) __reentrant
+{
+#pragma asm
+ mov a,dbglink_fiforxwr
+ clr c
+ subb a,dbglink_fiforxrd
+ mov r7,a
+ jnc rxcl0
+ clr a
+ mov dptr,#dbglink_rxbuffer_size
+ movc a,@a+dptr
+ add a,r7
+rxcl0: mov r7,a
+
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_rxcount(void) __reentrant
+{
+#pragma asm
+ mov a,dbglink_fiforxwr
+ clr c
+ subb a,dbglink_fiforxrd
+ mov r7,a
+ jnc rxc0
+ clr a
+ mov dptr,#dbglink_rxbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+rxc0:
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_txbuffersize(void) __reentrant
+{
+ return dbglink_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t dbglink_rxbuffersize(void) __reentrant
+{
+ return dbglink_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t dbglink_rxpeek(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ lcall _dbglink_rxbufptr
+ mov dpl,r7
+ mov dph,r6
+ movx a,@dptr
+ mov r7,a
+#pragma endasm
+}
+
+__reentrantb void dbglink_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+_dbglink_txpokehex_entry:
+ lcall _dbglink_txbufptr
+ mov dpl,r7
+ mov dph,r6
+ mov a,r5
+ movx @dptr,a
+#pragma endasm
+}
+
+__reentrantb void dbglink_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+ mov a,r5
+ anl a,#0x0F
+ add a,#256-10
+ jnc txph0
+ add a,#'A'-'9'-1
+txph0: add a,#10+'0'
+ mov r5,a
+ ljmp _dbglink_txpokehex_entry
+#pragma endasm
+}
+
+__reentrantb uint8_t dbglink_txidle(void) __reentrant
+{
+#pragma asm
+ mov a,DBGLNKSTAT
+ anl a,#0x84
+ mov r7,#0
+ cjne a,#0x04,txnotidle
+ mov r7,#1
+txnotidle:
+#pragma endasm
+}
+
+#elif defined __ICC8051__
+
+static __reentrantb uint8_t dbglink_iocore(void) __reentrant;
+
+#pragma vector=0xab
+__interrupt void dbglink_irq(void)
+{
+ uint8_t __autodata dpssave = DPS;
+ DPS = 0;
+ dbglink_iocore();
+ DPS = dpssave;
+}
+
+__reentrantb uint8_t dbglink_poll(void) __reentrant
+{
+ uint8_t flg;
+ uint8_t irq = IE & 0x80;
+ EA = 0;
+ flg = dbglink_iocore();
+ IE |= irq;
+ return flg;
+}
+
+static __reentrantb uint8_t dbglink_iocore(void) __reentrant
+{
+ uint8_t flg = 0;
+ if (DBGLNKSTAT & 0x01) {
+ uint8_t wp = dbglink_fiforxwr + 1;
+ uint8_t sz = dbglink_rxbuffer_size[0];
+ if (wp >= sz)
+ wp -= sz;
+ if (wp != dbglink_fiforxrd) {
+ dbglink_rxbuffer[dbglink_fiforxwr] = DBGLNKBUF;
+ dbglink_fiforxwr = wp;
+ DBGLNKSTAT |= 0x40;
+ flg |= 1;
+ } else {
+ DBGLNKSTAT &= (uint8_t)~0x40;
+ }
+ }
+ if (DBGLNKSTAT & 0x04) {
+ if (dbglink_fifotxrd != dbglink_fifotxwr) {
+ uint8_t rp = dbglink_fifotxrd + 1;
+ uint8_t sz = dbglink_txbuffer_size[0];
+ DBGLNKBUF = dbglink_txbuffer[dbglink_fifotxrd];
+ if (rp >= sz)
+ rp -= sz;
+ dbglink_fifotxrd = rp;
+ DBGLNKSTAT |= 0x80;
+ flg |= 2;
+ } else {
+ DBGLNKSTAT &= (uint8_t)~0x80;
+ }
+ }
+ return flg;
+}
+
+__reentrantb void dbglink_rxadvance(uint8_t idx) __reentrant
+{
+ uint8_t rd;
+ uint8_t sz;
+ if (!idx)
+ return;
+ rd = dbglink_fiforxrd;
+ idx += rd;
+ sz = dbglink_rxbuffer_size[0];
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ dbglink_fiforxrd = idx;
+ DBGLNKSTAT |= 0x40;
+}
+
+__reentrantb void dbglink_txadvance(uint8_t idx) __reentrant
+{
+ uint8_t wr;
+ uint8_t sz;
+ if (!idx)
+ return;
+ wr = dbglink_fifotxwr;
+ idx += wr;
+ sz = dbglink_txbuffer_size[0];
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ dbglink_fifotxwr = idx;
+ DBGLNKSTAT |= 0x80;
+}
+
+__reentrantb const uint8_t __xdata *dbglink_rxbufptr(uint8_t idx) __reentrant
+{
+ uint8_t rd = dbglink_fiforxrd;
+ uint8_t sz = dbglink_rxbuffer_size[0];
+ idx += rd;
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ return &dbglink_rxbuffer[idx];
+}
+
+__reentrantb uint8_t __xdata *dbglink_txbufptr(uint8_t idx) __reentrant
+{
+ uint8_t wr = dbglink_fifotxwr;
+ uint8_t sz = dbglink_txbuffer_size[0];
+ idx += wr;
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ return &dbglink_txbuffer[idx];
+}
+
+__reentrantb uint8_t dbglink_txfreelinear(void) __reentrant
+{
+ uint8_t rd = dbglink_fifotxrd;
+ uint8_t wr = dbglink_fifotxwr;
+ if (rd <= wr) {
+ uint8_t r = dbglink_txbuffer_size[0] - wr;
+ if (!rd)
+ --r;
+ return r;
+ }
+ return rd - wr - 1;
+}
+
+__reentrantb uint8_t dbglink_txfree(void) __reentrant
+{
+ uint8_t rd = dbglink_fifotxrd;
+ uint8_t wr = dbglink_fifotxwr;
+ uint8_t r = rd - wr;
+ if (rd <= wr)
+ r += dbglink_txbuffer_size[0];
+ --r;
+ return r;
+}
+
+__reentrantb uint8_t dbglink_rxcountlinear(void) __reentrant
+{
+ uint8_t rd = dbglink_fiforxrd;
+ uint8_t wr = dbglink_fiforxwr;
+ if (wr < rd)
+ return dbglink_rxbuffer_size[0] - rd;
+ return wr - rd;
+}
+
+__reentrantb uint8_t dbglink_rxcount(void) __reentrant
+{
+ uint8_t rd = dbglink_fiforxrd;
+ uint8_t wr = dbglink_fiforxwr;
+ uint8_t r = wr - rd;
+ if (wr < rd)
+ r += dbglink_rxbuffer_size[0];
+ return r;
+}
+
+__reentrantb uint8_t dbglink_txbuffersize(void) __reentrant
+{
+ return dbglink_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t dbglink_rxbuffersize(void) __reentrant
+{
+ return dbglink_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t dbglink_rxpeek(uint8_t idx) __reentrant
+{
+ const uint8_t __xdata *bp = dbglink_rxbufptr(idx);
+ return *bp;
+}
+
+__reentrantb void dbglink_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ uint8_t __xdata *bp = dbglink_txbufptr(idx);
+ *bp = ch;
+}
+
+__reentrantb void dbglink_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ ch &= 0x0F;
+ if (ch >= 10)
+ ch += 'A' - '9' - 1;
+ ch += '0';
+ dbglink_txpoke(idx, ch);
+}
+
+__reentrantb uint8_t dbglink_txidle(void) __reentrant
+{
+ if ((DBGLNKSTAT & 0x84) == 0x04)
+ return 1;
+ return 0;
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
+
+__reentrantb void dbglink_init(void) __reentrant
+{
+ dbglink_fiforxwr = dbglink_fiforxrd = dbglink_fifotxwr = dbglink_fifotxrd = 0;
+ DBGLNKSTAT = 0x40;
+ E2IE |= 0x40;
+}
diff --git a/libs/libmf/source/deepsleep.c b/libs/libmf/source/deepsleep.c
new file mode 100644
index 00000000..eb1a97c8
--- /dev/null
+++ b/libs/libmf/source/deepsleep.c
@@ -0,0 +1,70 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#ifdef SDCC
+
+/**
+ * \brief enter sleep mode
+ *
+ */
+__reentrantb void enter_deepsleep(void) __reentrant __naked
+{
+ __asm
+ mov dptr,#_RADIOMUX
+ movx a,@dptr
+ anl a,#~0x40
+ movx @dptr,a
+ clr _EA
+ clr a
+ mov dptr,#_GPIOENABLE
+ movx @dptr,a
+ mov r0,#0xff
+ mov @r0,a
+ dec r0
+ mov @r0,a
+ mov _PCON,#0x03
+ mov _CODECONFIG,#0xd3
+ ljmp 0xe047
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+__reentrantb void enter_deepsleep(void) __reentrant
+{
+ for (;;) {
+ RADIOMUX &= (uint8_t)~0x40;
+ EA = 0;
+ GPIOENABLE = 0;
+ PCON = 0x03;
+ CODECONFIG = 0xD3;
+#pragma asm
+ ljmp 0xE047
+#pragma endasm
+ }
+}
+
+#elif defined __ICC8051__
+
+__noreturn __reentrantb void enter_deepsleep(void) __reentrant
+{
+ for (;;) {
+ RADIOMUX &= (uint8_t)~0x40;
+ EA = 0;
+ GPIOENABLE = 0;
+ asm("clr a");
+ asm("mov r0,#0xff");
+ asm("mov @r0,a");
+ asm("dec r0");
+ asm("mov @r0,a");
+ PCON = 0x03;
+ CODECONFIG = 0xD3;
+ asm("ljmp 0xE047");
+ }
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
diff --git a/libs/libmf/source/delay.c b/libs/libmf/source/delay.c
new file mode 100644
index 00000000..6c823e46
--- /dev/null
+++ b/libs/libmf/source/delay.c
@@ -0,0 +1,57 @@
+#include "libmftypes.h"
+
+#ifdef SDCC
+
+/**
+ * \brief delay (busy waiting)
+ *
+ */
+__reentrantb void delay(uint16_t us) __reentrant __naked
+{
+ us;
+ __asm
+ mov a,dpl
+ jz 00002$
+ inc dph
+00002$: nop
+ nop
+00000$: mov a,#3
+00001$: djnz acc,00001$
+ djnz dpl,00002$
+ djnz dph,00000$
+ ret
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+__reentrantb void delay(uint16_t us) __reentrant
+{
+#pragma asm
+ mov a,r7 ;
+ jz dly2 ;
+ inc r6 ;
+dly2: nop ;
+ nop ;
+dly0: mov a,#3 ;
+dly1: djnz acc,dly1 ;
+ djnz r7,dly2 ;
+ djnz r6,dly0 ;
+#pragma endasm
+}
+
+#else
+
+__reentrantb void delay(uint16_t us) __reentrant
+{
+ uint8_t x;
+ do {
+ x = 3;
+ do {
+ --x;
+ } while (x);
+ --us;
+ } while (us);
+}
+
+#endif
diff --git a/libs/libmf/source/flashcal.c b/libs/libmf/source/flashcal.c
new file mode 100644
index 00000000..94c1f73f
--- /dev/null
+++ b/libs/libmf/source/flashcal.c
@@ -0,0 +1,363 @@
+#include "ax8052.h"
+#include "libmf.h"
+#include "libmfflash.h"
+#include "libmfcrc.h"
+#include "libmfcalsector.h"
+
+SFRX(REF, 0x7F16) /* Reference Tuning */
+SFRX(POWCTRL0, 0x7F10) /* Power Control 0 */
+SFRX(POWCTRL1, 0x7F11) /* Power Control 1 */
+SFRX(ADCCALG00GAIN0, 0x7030) /* ADC Calibration Range 00 Gain Low Byte */
+SFRX(ADCCALG00GAIN1, 0x7031) /* ADC Calibration Range 00 Gain High Byte */
+SFRX(ADCCALG01GAIN0, 0x7032) /* ADC Calibration Range 01 Gain Low Byte */
+SFRX(ADCCALG01GAIN1, 0x7033) /* ADC Calibration Range 01 Gain High Byte */
+SFRX(ADCCALG10GAIN0, 0x7034) /* ADC Calibration Range 10 Gain Low Byte */
+SFRX(ADCCALG10GAIN1, 0x7035) /* ADC Calibration Range 10 Gain High Byte */
+SFRX(ADCCALTEMPGAIN0, 0x7038) /* ADC Calibration Temperature Gain Low Byte */
+SFRX(ADCCALTEMPGAIN1, 0x7039) /* ADC Calibration Temperature Gain High Byte */
+SFRX(ADCCALTEMPOFFS0, 0x703A) /* ADC Calibration Temperature Offset Low Byte */
+SFRX(ADCCALTEMPOFFS1, 0x703B) /* ADC Calibration Temperature Offset High Byte */
+
+#if defined(SDCC)
+
+uint8_t flash_apply_calibration(void)
+{
+ __asm
+ ;; REF = 0x04;
+ mov dptr,#_REF
+ mov a,#0x04
+ movx @dptr,a
+ ;; ADCTUNE1 = 0x06;
+ mov dptr,#_ADCTUNE1
+ mov a,#0x06
+ movx @dptr,a
+ ;; check signature
+ mov dptr,#_flash_calsector
+ movx a,@dptr
+ xrl a,#0x80
+ jnz 00001$
+ inc dptr
+ movx a,@dptr
+ xrl a,#0xfe
+ jnz 00001$
+ inc dptr
+ movx a,@dptr
+ xrl a,#'C'
+ jnz 00001$
+ inc dptr
+ movx a,@dptr
+ xrl a,#'A'
+ jnz 00001$
+ inc dptr
+ movx a,@dptr
+ xrl a,#'L'
+ jnz 00001$
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ add a,#-26
+ jnc 00001$
+ inc dptr
+ mov r3,#0xff
+ mov r4,_IE
+ clr _EA
+ mov r5,_XPAGE
+ mov _XPAGE,dph
+ mov r0,dpl
+ mov dptr,#_crc_crc8ccitt_msbtable
+00002$: movx a,@r0
+ inc r0
+ xrl a,r3
+ movc a,@a+dptr
+ mov r3,a
+ djnz r2,00002$
+ mov _XPAGE,r5
+ mov _IE,r4
+ xrl a,#0xf3
+ jz 00003$
+ ;; error exit
+00001$: mov dptr,#_ADCCALG00GAIN0
+ mov a,#14429 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#14429 >> 8
+ movx @dptr,a
+ inc dptr
+ mov a,#15873 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#15873 >> 8
+ movx @dptr,a
+ inc dptr
+ mov a,#16603 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#16603 >> 8
+ movx @dptr,a
+ mov dptr,#_ADCCALTEMPGAIN0
+ mov a,#10407 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#10407 >> 8
+ movx @dptr,a
+ inc dptr
+ mov a,#5671 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#5671 >> 8
+ movx @dptr,a
+ mov dptr,#_FRCOSCFREQ0
+ mov a,#2114 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#2114 >> 8
+ movx @dptr,a
+ mov dptr,#_LPOSCCONFIG
+ movx a,@dptr
+ mov dptr,#_LPOSCFREQ0
+ jnb acc.6,00004$
+ mov a,#52779 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#52779 >> 8
+ movx @dptr,a
+ mov dptr,#0
+ ret
+00004$: mov a,#53443 & 0xff
+ movx @dptr,a
+ inc dptr
+ mov a,#53443 >> 8
+ movx @dptr,a
+ mov dptr,#0
+ ret
+
+ ;; restore calibration
+ ;; POWCTRL0, POWCTRL1, REF
+00003$: mov dptr,#(_flash_calsector + 0x001c)
+ movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ mov dptr,#_POWCTRL0
+ mov a,r0
+ movx @dptr,a
+ inc dptr
+ mov a,r1
+ movx @dptr,a
+ mov dptr,#_REF
+ mov a,r2
+ movx @dptr,a
+ ;; ADCCALGxxGAINy
+ mov dptr,#(_flash_calsector + 0x000c)
+ movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ mov dptr,#_ADCCALG00GAIN0
+ mov a,r0
+ movx @dptr,a
+ inc dptr
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov a,r2
+ movx @dptr,a
+ inc dptr
+ mov a,r3
+ movx @dptr,a
+ inc dptr
+ mov a,r4
+ movx @dptr,a
+ inc dptr
+ mov a,r5
+ movx @dptr,a
+ ;; ADCCALTEMPGAINx, ADCCALTEMPOFFSx
+ mov dptr,#(_flash_calsector + 0x0012)
+ movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ mov a,r1
+ add a,#-20
+ jc 00005$
+ mov a,r1
+ rl a
+ rl a
+ anl a,#0xfc
+ mov r1,a
+ mov a,r0
+ rl a
+ rl a
+ mov r0,a
+ anl a,#0x03
+ orl a,r1
+ mov r1,a
+ mov a,r0
+ anl a,#0xfc
+ mov r0,a
+ mov a,r3
+ rl a
+ rl a
+ anl a,#0xfc
+ mov r3,a
+ mov a,r2
+ rl a
+ rl a
+ mov r2,a
+ anl a,#0x03
+ orl a,r3
+ mov r3,a
+ mov a,r2
+ anl a,#0xfc
+ mov r2,a
+00005$: mov dptr,#_ADCCALTEMPGAIN0
+ mov a,r0
+ movx @dptr,a
+ inc dptr
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov a,r2
+ movx @dptr,a
+ inc dptr
+ mov a,r3
+ movx @dptr,a
+ ;; FRCOSCFREQx
+ mov dptr,#(_flash_calsector + 0x0016)
+ movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ mov dptr,#_FRCOSCFREQ0
+ mov a,r0
+ movx @dptr,a
+ inc dptr
+ mov a,r1
+ movx @dptr,a
+ ;; LPOSCFREQx
+ mov dptr,#_LPOSCCONFIG
+ movx a,@dptr
+ mov dptr,#(_flash_calsector + 0x0018)
+ jnb acc.6,00006$
+ mov dptr,#(_flash_calsector + 0x001a)
+00006$: movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ mov dptr,#_LPOSCFREQ0
+ mov a,r0
+ movx @dptr,a
+ inc dptr
+ mov a,r1
+ movx @dptr,a
+ mov dptr,#1
+ __endasm;
+}
+
+#else
+
+uint8_t flash_apply_calibration(void)
+{
+ REF = 0x04;
+ ADCTUNE1 = 0x06;
+ if (flash_calsector.id[0] != 0x80) {
+ err:
+ ADCCALG00GAIN0 = 14429 & 0xff;
+ ADCCALG00GAIN1 = 14429 >> 8;
+ ADCCALG01GAIN0 = 15873 & 0xff;
+ ADCCALG01GAIN1 = 15873 >> 8;
+ ADCCALG10GAIN0 = 16603 & 0xff;
+ ADCCALG10GAIN1 = 16603 >> 8;
+ ADCCALTEMPGAIN0 = 10407 & 0xff;
+ ADCCALTEMPGAIN1 = 10407 >> 8;
+ ADCCALTEMPOFFS0 = 5671 & 0xff;
+ ADCCALTEMPOFFS1 = 5671 >> 8;
+ FRCOSCFREQ0 = 2114 & 0xff;
+ FRCOSCFREQ1 = 2114 >> 8;
+ if (LPOSCCONFIG & 0x40) {
+ LPOSCFREQ0 = 52779 & 0xff;
+ LPOSCFREQ1 = 52779 >> 8;
+ } else {
+ LPOSCFREQ0 = 53443 & 0xff;
+ LPOSCFREQ1 = 53443 >> 8;
+ }
+ return 0;
+ }
+ if (flash_calsector.id[1] != 0xfe)
+ goto err;
+ if (flash_calsector.id[2] != (uint8_t)'C')
+ goto err;
+ if (flash_calsector.id[3] != (uint8_t)'A')
+ goto err;
+ if (flash_calsector.id[4] != (uint8_t)'L')
+ goto err;
+ if (flash_calsector.len < (uint8_t)26)
+ goto err;
+ if (crc_crc8ccitt_msb((&flash_calsector.len) + 1, flash_calsector.len, 0xff) != 0xf3)
+ goto err;
+ POWCTRL0 = flash_calsector.powctrl0;
+ POWCTRL1 = flash_calsector.powctrl1;
+ REF = flash_calsector.ref;
+ ADCCALG00GAIN0 = flash_calsector.calg00gain[0];
+ ADCCALG00GAIN1 = flash_calsector.calg00gain[1];
+ ADCCALG01GAIN0 = flash_calsector.calg01gain[0];
+ ADCCALG01GAIN1 = flash_calsector.calg01gain[1];
+ ADCCALG10GAIN0 = flash_calsector.calg10gain[0];
+ ADCCALG10GAIN1 = flash_calsector.calg10gain[1];
+ {
+ uint8_t __autodata g0, g1, o0, o1;
+ g0 = flash_calsector.caltempgain[0];
+ g1 = flash_calsector.caltempgain[1];
+ o0 = flash_calsector.caltempoffs[0];
+ o1 = flash_calsector.caltempoffs[1];
+ if (g1 < 20) {
+ ADCCALTEMPGAIN0 = g0 << 2;
+ ADCCALTEMPGAIN1 = (g1 << 2) | (g0 >> 6);
+ ADCCALTEMPOFFS0 = o0 << 2;
+ ADCCALTEMPOFFS1 = (o1 << 2) | (o0 >> 6);
+ } else {
+ ADCCALTEMPGAIN0 = g0;
+ ADCCALTEMPGAIN1 = g1;
+ ADCCALTEMPOFFS0 = o0;
+ ADCCALTEMPOFFS1 = o1;
+ }
+ }
+ FRCOSCFREQ0 = flash_calsector.frcoscfreq[0];
+ FRCOSCFREQ1 = flash_calsector.frcoscfreq[1];
+ if (LPOSCCONFIG & 0x40) {
+ LPOSCFREQ0 = flash_calsector.lposcfreq_fast[0];
+ LPOSCFREQ1 = flash_calsector.lposcfreq_fast[1];
+ } else {
+ LPOSCFREQ0 = flash_calsector.lposcfreq[0];
+ LPOSCFREQ1 = flash_calsector.lposcfreq[1];
+ }
+ return 1;
+}
+
+#endif
diff --git a/libs/libmf/source/flashcsec.c b/libs/libmf/source/flashcsec.c
new file mode 100644
index 00000000..390eb408
--- /dev/null
+++ b/libs/libmf/source/flashcsec.c
@@ -0,0 +1,7 @@
+#include "libmfcalsector.h"
+
+#if defined __ICC8051__
+
+__no_init __root struct calsector __xdata flash_calsector @ 0xfc00;
+
+#endif
diff --git a/libs/libmf/source/flashlock.c b/libs/libmf/source/flashlock.c
new file mode 100644
index 00000000..694471b3
--- /dev/null
+++ b/libs/libmf/source/flashlock.c
@@ -0,0 +1,7 @@
+#include "ax8052.h"
+#include "libmfflash.h"
+
+void flash_lock(void)
+{
+ NVKEY = 0;
+}
diff --git a/libs/libmf/source/flashpgerase.c b/libs/libmf/source/flashpgerase.c
new file mode 100644
index 00000000..15c669e2
--- /dev/null
+++ b/libs/libmf/source/flashpgerase.c
@@ -0,0 +1,10 @@
+#include "ax8052.h"
+#include "libmfflash.h"
+
+int8_t flash_pageerase(uint16_t pgaddr)
+{
+ NVADDR0 = pgaddr;
+ NVADDR1 = pgaddr >> 8;
+ NVSTATUS = 0x20;
+ return flash_wait(65535);
+}
diff --git a/libs/libmf/source/flashread.c b/libs/libmf/source/flashread.c
new file mode 100644
index 00000000..15a9965d
--- /dev/null
+++ b/libs/libmf/source/flashread.c
@@ -0,0 +1,7 @@
+#include "libmfflash.h"
+
+uint16_t flash_read(uint16_t raddr)
+{
+ const uint16_t __code *p = (const uint16_t __code *)(raddr & ~1U);
+ return *p;
+}
diff --git a/libs/libmf/source/flashunlock.c b/libs/libmf/source/flashunlock.c
new file mode 100644
index 00000000..7144ae96
--- /dev/null
+++ b/libs/libmf/source/flashunlock.c
@@ -0,0 +1,11 @@
+#include "ax8052.h"
+#include "libmfflash.h"
+
+void flash_unlock(void)
+{
+ uint8_t __autodata iesave = IE & 0x80;
+ EA = 0;
+ NVKEY = 0x41;
+ NVKEY = 0x78;
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/flashwait.c b/libs/libmf/source/flashwait.c
new file mode 100644
index 00000000..5c150f03
--- /dev/null
+++ b/libs/libmf/source/flashwait.c
@@ -0,0 +1,23 @@
+#include "ax8052.h"
+#include "libmfflash.h"
+
+int8_t flash_wait(uint16_t timeout)
+{
+ uint8_t __autodata st;
+ uint8_t __autodata cnth = timeout >> 8;
+ uint8_t __autodata cntl = timeout;
+ ++cnth;
+ ++cntl;
+ do {
+ do {
+ st = NVSTATUS;
+ if (!(st & 2))
+ return -2;
+ if (!(st & 1))
+ return 0;
+ --cntl;
+ } while (cntl);
+ --cnth;
+ } while (cnth);
+ return -1;
+}
diff --git a/libs/libmf/source/flashwrite.c b/libs/libmf/source/flashwrite.c
new file mode 100644
index 00000000..d70eb88f
--- /dev/null
+++ b/libs/libmf/source/flashwrite.c
@@ -0,0 +1,12 @@
+#include "ax8052.h"
+#include "libmfflash.h"
+
+int8_t flash_write(uint16_t waddr, uint16_t wdata)
+{
+ NVADDR0 = waddr;
+ NVADDR1 = waddr >> 8;
+ NVDATA0 = wdata;
+ NVDATA1 = wdata >> 8;
+ NVSTATUS = 0x30;
+ return flash_wait(128);
+}
diff --git a/libs/libmf/source/fmemcpy.c b/libs/libmf/source/fmemcpy.c
new file mode 100644
index 00000000..d1ed866f
--- /dev/null
+++ b/libs/libmf/source/fmemcpy.c
@@ -0,0 +1,238 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#if defined SDCC
+
+/**
+ * \brief fast memset
+ *
+ */
+__reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant __naked
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov r0,sp
+ dec r0
+ dec r0
+ mov ar3,@r0
+ dec r0
+ mov ar2,@r0
+ dec r0
+ mov ar1,@r0
+ dec r0
+ mov ar7,@r0
+ dec r0
+ mov a,@r0
+ mov r6,a
+ jnz 00001$
+ orl a,r7
+ jnz 00000$
+00002$: ret
+00001$: inc r7
+00000$: ;; decide memory space
+ mov a,r3
+ jb _B_7,00002$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dpl,r1
+ mov dph,r2
+ jnb _B_5,idataptr$ ; >0x60 pdata
+ ljmp pdataptr$
+idataptr$:
+ jb acc.7,idatacodeloop$ ; >0x80 code
+ jnb acc.6,idataxdataloop$ ; <0x40 far
+ jb acc.5,idatapdataloop$ ; >0x60 pdata
+idataidataloop$:
+ mov a,@r1
+ inc r1
+ mov @r0,a
+ inc r0
+ djnz r6,idataidataloop$
+ djnz r7,idataidataloop$
+ ret
+idatapdataloop$:
+ movx a,@r1
+ inc r1
+ mov @r0,a
+ inc r0
+ djnz r6,idatapdataloop$
+ djnz r7,idatapdataloop$
+ ret
+idataxdataloop$:
+ movx a,@dptr
+ inc dptr
+ mov @r0,a
+ inc r0
+ djnz r6,idataxdataloop$
+ djnz r7,idataxdataloop$
+ ret
+idatacodeloop$:
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ mov @r0,a
+ inc r0
+ djnz r6,idatacodeloop$
+ djnz r7,idatacodeloop$
+ ret
+xdataptr$:
+ jb acc.7,xdatacodeloop$ ; >0x80 code
+ jnb acc.6,xdataxdataloop$ ; <0x40 far
+ jb acc.5,xdatapdataloop$ ; >0x60 pdata
+xdataidataloop$:
+ mov a,@r1
+ inc r1
+ movx @dptr,a
+ inc dptr
+ djnz r6,xdataidataloop$
+ djnz r7,xdataidataloop$
+ ret
+xdatapdataloop$:
+ movx a,@r1
+ inc r1
+ movx @dptr,a
+ inc dptr
+ djnz r6,xdatapdataloop$
+ djnz r7,xdatapdataloop$
+ ret
+xdataxdataloop$:
+ push _IE
+ clr EA
+ push _DPL1
+ push _DPH1
+ mov _DPL1,r1
+ mov _DPH1,r2
+xdataxdataloop1$:
+ xrl _DPS,#1
+ movx a,@dptr
+ inc dptr
+ xrl _DPS,#1
+ movx @dptr,a
+ inc dptr
+ djnz r6,xdataxdataloop1$
+ djnz r7,xdataxdataloop1$
+ pop _DPH1
+ pop _DPL1
+ pop _IE
+ ret
+xdatacodeloop$:
+ push _IE
+ clr EA
+ push _DPL1
+ push _DPH1
+ mov _DPL1,r1
+ mov _DPH1,r2
+xdatacodeloop1$:
+ xrl _DPS,#1
+ clr a
+ movc a,@a+dptr
+ xrl _DPS,#1
+ inc dptr
+ movx @dptr,a
+ inc dptr
+ djnz r6,xdatacodeloop1$
+ djnz r7,xdatacodeloop1$
+ pop _DPH1
+ pop _DPL1
+ pop _IE
+ ret
+pdataptr$:
+ jb acc.7,pdatacodeloop$ ; >0x80 code
+ jnb acc.6,pdataxdataloop$ ; <0x40 far
+ jb acc.5,pdatapdataloop$ ; >0x60 pdata
+pdataidataloop$:
+ mov a,@r1
+ inc r1
+ movx @r0,a
+ inc r0
+ djnz r6,pdataidataloop$
+ djnz r7,pdataidataloop$
+ ret
+pdatapdataloop$:
+ movx a,@r1
+ inc r1
+ movx @r0,a
+ inc r0
+ djnz r6,pdatapdataloop$
+ djnz r7,pdatapdataloop$
+ ret
+pdataxdataloop$:
+ movx a,@dptr
+ inc dptr
+ movx @r0,a
+ inc r0
+ djnz r6,pdataxdataloop$
+ djnz r7,pdataxdataloop$
+ ret
+pdatacodeloop$:
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ movx @r0,a
+ inc r0
+ djnz r6,pdatacodeloop$
+ djnz r7,pdatacodeloop$
+ ret
+ __endasm;
+}
+
+#elif defined __ICC8051__
+
+__reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant
+{
+ uint8_t da = ((uint32_t)d)>>16;
+ uint8_t sa = ((uint32_t)s)>>16;
+ if (da & 0x80)
+ return;
+ if (da & 0x01) {
+ uint8_t __data *pd = (uint8_t __data *)(uint8_t)d;
+ if (sa & 0x80) {
+ const uint8_t __code *ps = (const uint8_t __code *)(uint16_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ } else if (sa & 0x01) {
+ const uint8_t __data *ps = (const uint8_t __data *)(uint8_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ } else {
+ const uint8_t __xdata *ps = (const uint8_t __xdata *)(uint16_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ }
+ } else {
+ uint8_t __xdata *pd = (uint8_t __xdata *)(uint16_t)d;
+ if (sa & 0x80) {
+ const uint8_t __code *ps = (const uint8_t __code *)(uint16_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ } else if (sa & 0x01) {
+ const uint8_t __data *ps = (const uint8_t __data *)(uint8_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ } else {
+ const uint8_t __xdata *ps = (const uint8_t __xdata *)(uint16_t)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+ }
+ }
+}
+
+#else
+
+__reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant
+{
+ char __generic *pd = (char __generic *)d;
+ const char __generic *ps = (const char __generic *)s;
+ for (; n; --n)
+ *pd++ = *ps++;
+}
+
+#endif
diff --git a/libs/libmf/source/fmemcpyiar.s51 b/libs/libmf/source/fmemcpyiar.s51
new file mode 100644
index 00000000..744faa12
--- /dev/null
+++ b/libs/libmf/source/fmemcpyiar.s51
@@ -0,0 +1,271 @@
+#include "iar_common.h"
+
+ NAME fmemcpy
+
+ //RTMODEL "__SystemLibrary", "CLib"
+ //RTMODEL "__calling_convention", "idata_reentrant"
+ RTMODEL "__code_model", "near"
+ RTMODEL "__core", "plain"
+ //RTMODEL "__data_model", "small"
+ RTMODEL "__dptr_size", "16"
+ RTMODEL "__extended_stack", "disabled"
+ //RTMODEL "__location_for_constants", "data"
+ RTMODEL "__number_of_dptrs", "1"
+ RTMODEL "__rt_version", "1"
+
+ RSEG DOVERLAY:DATA:NOROOT(0)
+ RSEG IOVERLAY:IDATA:NOROOT(0)
+ RSEG ISTACK:IDATA:NOROOT(0)
+ RSEG PSTACK:XDATA:NOROOT(0)
+ RSEG XSTACK:XDATA:NOROOT(0)
+
+ PUBWEAK IE
+ PUBWEAK EA
+ PUBWEAK DPH1
+ PUBWEAK DPL1
+ PUBWEAK DPS
+ PUBLIC fmemcpy
+ FUNCTION fmemcpy,0203H
+ ARGFRAME ISTACK, 3, STACK
+
+ CFI Names cfiNames0
+ CFI StackFrame CFA_SP SP IDATA
+ CFI StackFrame CFA_PSP16 PSP16 XDATA
+ CFI StackFrame CFA_XSP16 XSP16 XDATA
+ CFI StaticOverlayFrame CFA_IOVERLAY IOVERLAY
+ CFI StaticOverlayFrame CFA_DOVERLAY DOVERLAY
+ CFI Resource `PSW.CY`:1, `B.BR0`:1, `B.BR1`:1, `B.BR2`:1, `B.BR3`:1
+ CFI Resource `B.BR4`:1, `B.BR5`:1, `B.BR6`:1, `B.BR7`:1, `VB.BR8`:1
+ CFI Resource `VB.BR9`:1, `VB.BR10`:1, `VB.BR11`:1, `VB.BR12`:1
+ CFI Resource `VB.BR13`:1, `VB.BR14`:1, `VB.BR15`:1, VB:8, B:8, A:8
+ CFI Resource PSW:8, DPL0:8, DPH0:8, R0:8, R1:8, R2:8, R3:8, R4:8, R5:8
+ CFI Resource R6:8, R7:8, V0:8, V1:8, V2:8, V3:8, V4:8, V5:8, V6:8, V7:8
+ CFI Resource SP:8, PSPH:8, PSPL:8, PSP16:16, XSPH:8, XSPL:8, XSP16:16
+ CFI VirtualResource ?RET:16, ?RET_HIGH:8, ?RET_LOW:8
+ CFI ResourceParts PSP16 PSPH, PSPL
+ CFI ResourceParts XSP16 XSPH, XSPL
+ CFI ResourceParts ?RET ?RET_HIGH, ?RET_LOW
+ CFI EndNames cfiNames0
+
+ CFI Common cfiCommon0 Using cfiNames0
+ CFI CodeAlign 1
+ CFI DataAlign -1
+ CFI ReturnAddress ?RET CODE
+ CFI CFA_DOVERLAY Used
+ CFI CFA_IOVERLAY Used
+ CFI CFA_SP SP+-2
+ CFI CFA_PSP16 PSP16+0
+ CFI CFA_XSP16 XSP16+0
+ CFI `PSW.CY` SameValue
+ CFI `B.BR0` SameValue
+ CFI `B.BR1` SameValue
+ CFI `B.BR2` SameValue
+ CFI `B.BR3` SameValue
+ CFI `B.BR4` SameValue
+ CFI `B.BR5` SameValue
+ CFI `B.BR6` SameValue
+ CFI `B.BR7` SameValue
+ CFI `VB.BR8` SameValue
+ CFI `VB.BR9` SameValue
+ CFI `VB.BR10` SameValue
+ CFI `VB.BR11` SameValue
+ CFI `VB.BR12` SameValue
+ CFI `VB.BR13` SameValue
+ CFI `VB.BR14` SameValue
+ CFI `VB.BR15` SameValue
+ CFI VB SameValue
+ CFI B Undefined
+ CFI A Undefined
+ CFI PSW SameValue
+ CFI DPL0 Undefined
+ CFI DPH0 Undefined
+ CFI R0 Undefined
+ CFI R1 Undefined
+ CFI R2 Undefined
+ CFI R3 Undefined
+ CFI R4 Undefined
+ CFI R5 Undefined
+ CFI R6 SameValue
+ CFI R7 SameValue
+ CFI V0 SameValue
+ CFI V1 SameValue
+ CFI V2 SameValue
+ CFI V3 SameValue
+ CFI V4 SameValue
+ CFI V5 SameValue
+ CFI V6 SameValue
+ CFI V7 SameValue
+ CFI PSPH Undefined
+ CFI PSPL Undefined
+ CFI XSPH Undefined
+ CFI XSPL Undefined
+ CFI ?RET Concat
+ CFI ?RET_HIGH Frame(CFA_SP, 2)
+ CFI ?RET_LOW Frame(CFA_SP, 1)
+ CFI EndCommon cfiCommon0
+
+ ASEGN SFR_AN:DATA:NOROOT,085H
+DPH1:
+ DATA8
+ DS 1
+
+ ASEGN SFR_AN:DATA:NOROOT,084H
+DPL1:
+ DATA8
+ DS 1
+
+ ASEGN SFR_AN:DATA:NOROOT,086H
+DPS:
+ DATA8
+ DS 1
+
+ ASEGN SFR_AN:DATA:NOROOT,0a8H
+IE:
+ DATA8
+ DS 1
+
+ ASEGN BIT_AN:BIT:NOROOT,0afH
+EA:
+ DATA8
+ DS 1
+
+ RSEG NEAR_CODE:CODE:NOROOT(0)
+ // __reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant
+fmemcpy:
+ CFI Block cfiBlock0 Using cfiCommon0
+ CFI Function fmemcpy
+ CODE
+
+AR0 EQU 0
+AR1 EQU 1
+AR2 EQU 2
+AR3 EQU 3
+AR4 EQU 4
+AR5 EQU 5
+AR6 EQU 6
+AR7 EQU 7
+
+ MOV A,R4
+ JNZ nlownz
+ ORL A,R5
+ JNZ nnz
+doret: RET
+nlownz: INC R5
+nnz: MOV R0,SP
+ DEC R0
+ DEC R0
+
+ // decide memory space
+ MOV A,R3
+ JB ACC.7,doret // >=0x80 code
+ JNB ACC.0,xdataptr // ==0x01 xdata
+idataptr:
+ MOV A,@R0
+ DEC R0
+ JB ACC.7,idatacodeptr // >=0x80 code
+ JNB ACC.0,idataxdataptr // ==0x01 xdata
+idataidataptr:
+ DEC R0
+ MOV AR0,@R0
+idataidataloop:
+ MOV A,@R0
+ INC R0
+ MOV @R1,A
+ INC R1
+ DJNZ R4,idataidataloop
+ DJNZ R5,idataidataloop
+ RET
+idataxdataptr:
+ MOV DPH,@R0
+ DEC R0
+ MOV DPL,@R0
+idataxdataloop:
+ MOVX A,@DPTR
+ INC DPTR
+ MOV @R1,A
+ INC R1
+ DJNZ R4,idataxdataloop
+ DJNZ R5,idataxdataloop
+ RET
+idatacodeptr:
+ MOV DPH,@R0
+ DEC R0
+ MOV DPL,@R0
+idatacodeloop:
+ CLR A
+ MOVC A,@A+DPTR
+ INC DPTR
+ MOV @R1,A
+ INC R1
+ DJNZ R4,idatacodeloop
+ DJNZ R5,idatacodeloop
+ RET
+xdataptr:
+ MOV DPL,R1
+ MOV DPH,R2
+ MOV A,@R0
+ DEC R0
+ JB ACC.7,xdatacodeptr // >=0x80 code
+ JNB ACC.0,xdataxdataptr // ==0x01 xdata
+xdataidataptr:
+ DEC R0
+ MOV AR0,@R0
+xdataidataloop:
+ MOV A,@R1
+ INC R1
+ MOVX @DPTR,A
+ INC DPTR
+ DJNZ R4,xdataidataloop
+ DJNZ R5,xdataidataloop
+ RET
+xdataxdataptr:
+ PUSH IE
+ CLR EA
+ PUSH DPL1
+ PUSH DPH1
+ MOV DPH1,@R0
+ DEC R0
+ MOV DPL1,@R0
+xdataxdataloop:
+ XRL DPS,#1
+ MOVX A,@DPTR
+ INC DPTR
+ XRL DPS,#1
+ MOVX @DPTR,A
+ INC DPTR
+ DJNZ R4,xdataxdataloop
+ DJNZ R5,xdataxdataloop
+ POP DPH1
+ POP DPL1
+ POP IE
+ RET
+xdatacodeptr:
+ PUSH IE
+ CLR EA
+ PUSH DPL1
+ PUSH DPH1
+ MOV DPH1,@R0
+ DEC R0
+ MOV DPL1,@R0
+xdatacodeloop:
+ XRL DPS,#1
+ CLR A
+ MOVC A,@A+DPTR
+ INC DPTR
+ XRL DPS,#1
+ MOVX @DPTR,A
+ INC DPTR
+ DJNZ R4,xdatacodeloop
+ DJNZ R5,xdatacodeloop
+ POP DPH1
+ POP DPL1
+ POP IE
+ RET
+ CFI EndBlock cfiBlock0
+ REQUIRE IE
+ REQUIRE EA
+ REQUIRE DPS
+ REQUIRE DPL1
+ REQUIRE DPH1
+
+ END
diff --git a/libs/libmf/source/fmemset.c b/libs/libmf/source/fmemset.c
new file mode 100644
index 00000000..231d0d42
--- /dev/null
+++ b/libs/libmf/source/fmemset.c
@@ -0,0 +1,110 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#if defined SDCC
+
+/**
+ * \brief fast memset
+ *
+ */
+__reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant __naked
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov r0,sp
+ dec r0
+ dec r0
+ mov ar5,@r0
+ dec r0
+ mov ar7,@r0
+ dec r0
+ mov a,@r0
+ mov r6,a
+ jnz 00001$
+ orl a,r7
+ jnz 00000$
+00002$: ret
+00001$: inc r7
+00000$: ;; decide memory space
+ mov a,r5
+ jb _B_7,00002$ ; >0x80 code
+ jnb _B_6,xdataloop$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,pdataloop$ ; >0x60 pdata
+idataloop$:
+ mov @r0,a
+ inc r0
+ djnz r6,idataloop$
+ djnz r7,idataloop$
+ ret
+pdataloop$:
+ movx @r0,a
+ inc r0
+ djnz r6,pdataloop$
+ djnz r7,pdataloop$
+ ret
+xdataloop$:
+ movx @dptr,a
+ inc dptr
+ djnz r6,xdataloop$
+ djnz r7,xdataloop$
+ ret
+ __endasm;
+}
+
+#elif defined __ICC8051__
+
+__reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant
+{
+ union ptr {
+ void __generic *p;
+ uint8_t __data *pd;
+ uint8_t __xdata *px;
+ uint8_t b[3];
+ };
+ union ptr pp;
+ uint8_t pa;
+ uint8_t n0 = n, n1 = n >> 8;
+ if (n0)
+ ++n1;
+ else if (!n1)
+ return;
+ pp.p = p;
+ pa = pp.b[2];
+ if (pa & 0x80)
+ return;
+ if (pa & 0x01) {
+ uint8_t __data *p1 = pp.pd;
+ do {
+ do {
+ *p1++ = c;
+ } while (--n0);
+ } while (--n1);
+ } else {
+ uint8_t __xdata *p1 = pp.px;
+ do {
+ do {
+ *p1++ = c;
+ } while (--n0);
+ } while (--n1);
+ }
+}
+
+#else
+
+__reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant
+{
+ char __generic *pp = (char __generic *)p;
+ for (; n; --n)
+ *pp++ = c;
+}
+
+#endif
diff --git a/libs/libmf/source/fmemsetiar.s51 b/libs/libmf/source/fmemsetiar.s51
new file mode 100644
index 00000000..368e8034
--- /dev/null
+++ b/libs/libmf/source/fmemsetiar.s51
@@ -0,0 +1,154 @@
+#include "iar_common.h"
+
+ NAME fmemset
+
+ //RTMODEL "__SystemLibrary", "CLib"
+ //RTMODEL "__calling_convention", "idata_reentrant"
+ RTMODEL "__code_model", "near"
+ RTMODEL "__core", "plain"
+ //RTMODEL "__data_model", "small"
+ RTMODEL "__dptr_size", "16"
+ RTMODEL "__extended_stack", "disabled"
+ //RTMODEL "__location_for_constants", "data"
+ RTMODEL "__number_of_dptrs", "1"
+ RTMODEL "__rt_version", "1"
+
+ RSEG DOVERLAY:DATA:NOROOT(0)
+ RSEG IOVERLAY:IDATA:NOROOT(0)
+ RSEG ISTACK:IDATA:NOROOT(0)
+ RSEG PSTACK:XDATA:NOROOT(0)
+ RSEG XSTACK:XDATA:NOROOT(0)
+
+ PUBLIC fmemset
+ FUNCTION fmemset,0203H
+ ARGFRAME ISTACK, 2, STACK
+
+ CFI Names cfiNames0
+ CFI StackFrame CFA_SP SP IDATA
+ CFI StackFrame CFA_PSP16 PSP16 XDATA
+ CFI StackFrame CFA_XSP16 XSP16 XDATA
+ CFI StaticOverlayFrame CFA_IOVERLAY IOVERLAY
+ CFI StaticOverlayFrame CFA_DOVERLAY DOVERLAY
+ CFI Resource `PSW.CY`:1, `B.BR0`:1, `B.BR1`:1, `B.BR2`:1, `B.BR3`:1
+ CFI Resource `B.BR4`:1, `B.BR5`:1, `B.BR6`:1, `B.BR7`:1, `VB.BR8`:1
+ CFI Resource `VB.BR9`:1, `VB.BR10`:1, `VB.BR11`:1, `VB.BR12`:1
+ CFI Resource `VB.BR13`:1, `VB.BR14`:1, `VB.BR15`:1, VB:8, B:8, A:8
+ CFI Resource PSW:8, DPL0:8, DPH0:8, R0:8, R1:8, R2:8, R3:8, R4:8, R5:8
+ CFI Resource R6:8, R7:8, V0:8, V1:8, V2:8, V3:8, V4:8, V5:8, V6:8, V7:8
+ CFI Resource SP:8, PSPH:8, PSPL:8, PSP16:16, XSPH:8, XSPL:8, XSP16:16
+ CFI VirtualResource ?RET:16, ?RET_HIGH:8, ?RET_LOW:8
+ CFI ResourceParts PSP16 PSPH, PSPL
+ CFI ResourceParts XSP16 XSPH, XSPL
+ CFI ResourceParts ?RET ?RET_HIGH, ?RET_LOW
+ CFI EndNames cfiNames0
+
+ CFI Common cfiCommon0 Using cfiNames0
+ CFI CodeAlign 1
+ CFI DataAlign -1
+ CFI ReturnAddress ?RET CODE
+ CFI CFA_DOVERLAY Used
+ CFI CFA_IOVERLAY Used
+ CFI CFA_SP SP+-2
+ CFI CFA_PSP16 PSP16+0
+ CFI CFA_XSP16 XSP16+0
+ CFI `PSW.CY` SameValue
+ CFI `B.BR0` SameValue
+ CFI `B.BR1` SameValue
+ CFI `B.BR2` SameValue
+ CFI `B.BR3` SameValue
+ CFI `B.BR4` SameValue
+ CFI `B.BR5` SameValue
+ CFI `B.BR6` SameValue
+ CFI `B.BR7` SameValue
+ CFI `VB.BR8` SameValue
+ CFI `VB.BR9` SameValue
+ CFI `VB.BR10` SameValue
+ CFI `VB.BR11` SameValue
+ CFI `VB.BR12` SameValue
+ CFI `VB.BR13` SameValue
+ CFI `VB.BR14` SameValue
+ CFI `VB.BR15` SameValue
+ CFI VB SameValue
+ CFI B Undefined
+ CFI A Undefined
+ CFI PSW SameValue
+ CFI DPL0 Undefined
+ CFI DPH0 Undefined
+ CFI R0 Undefined
+ CFI R1 Undefined
+ CFI R2 Undefined
+ CFI R3 Undefined
+ CFI R4 Undefined
+ CFI R5 Undefined
+ CFI R6 SameValue
+ CFI R7 SameValue
+ CFI V0 SameValue
+ CFI V1 SameValue
+ CFI V2 SameValue
+ CFI V3 SameValue
+ CFI V4 SameValue
+ CFI V5 SameValue
+ CFI V6 SameValue
+ CFI V7 SameValue
+ CFI PSPH Undefined
+ CFI PSPL Undefined
+ CFI XSPH Undefined
+ CFI XSPL Undefined
+ CFI ?RET Concat
+ CFI ?RET_HIGH Frame(CFA_SP, 2)
+ CFI ?RET_LOW Frame(CFA_SP, 1)
+ CFI EndCommon cfiCommon0
+
+ RSEG NEAR_CODE:CODE:NOROOT(0)
+ // __reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant
+fmemset:
+ CFI Block cfiBlock0 Using cfiCommon0
+ CFI Function fmemset
+ CODE
+
+AR0 EQU 0
+AR1 EQU 1
+AR2 EQU 2
+AR3 EQU 3
+AR4 EQU 4
+AR5 EQU 5
+AR6 EQU 6
+AR7 EQU 7
+
+ MOV R0,SP
+ DEC R0
+ DEC R0
+ MOV AR7,@R0
+ DEC R0
+ MOV A,@R0
+ MOV R6,A
+ JNZ nlownz
+ ORL A,R7
+ JNZ nnz
+doret: RET
+nlownz: INC R7
+nnz: // decide memory space
+ MOV A,R3
+ JB ACC.7,doret // >=0x80 code
+ JNB ACC.0,xdataptr // ==0x01 xdata
+idataptr:
+ MOV A,R4
+idataloop:
+ MOV @R1,A
+ INC R1
+ DJNZ R6,idataloop
+ DJNZ R7,idataloop
+ RET
+xdataptr:
+ MOV DPL,R1
+ MOV DPH,R2
+ MOV A,R4
+xdataloop:
+ MOVX @DPTR,A
+ INC DPTR
+ DJNZ R6,xdataloop
+ DJNZ R7,xdataloop
+ RET
+ CFI EndBlock cfiBlock0
+
+ END
diff --git a/libs/libmf/source/getpspiar.s51 b/libs/libmf/source/getpspiar.s51
new file mode 100644
index 00000000..9e34dc2f
--- /dev/null
+++ b/libs/libmf/source/getpspiar.s51
@@ -0,0 +1,111 @@
+ MODULE getpsp
+
+ //RTMODEL "__SystemLibrary", "CLib"
+ //RTMODEL "__calling_convention", "data_overlay"
+ RTMODEL "__code_model", "near"
+ RTMODEL "__core", "plain"
+ //RTMODEL "__data_model", "small"
+ RTMODEL "__dptr_size", "16"
+ RTMODEL "__extended_stack", "disabled"
+ //RTMODEL "__location_for_constants", "code"
+ RTMODEL "__number_of_dptrs", "1"
+ RTMODEL "__rt_version", "1"
+
+ RSEG DOVERLAY:DATA:NOROOT(0)
+ RSEG IOVERLAY:IDATA:NOROOT(0)
+ RSEG ISTACK:IDATA:NOROOT(0)
+ RSEG PSTACK:XDATA:NOROOT(0)
+ RSEG XSTACK:XDATA:NOROOT(0)
+
+ PUBLIC getpsp
+ FUNCTION getpsp,0203H
+
+ CFI Names cfiNames0
+ CFI StackFrame CFA_SP SP IDATA
+ CFI StackFrame CFA_PSP16 PSP16 XDATA
+ CFI StackFrame CFA_XSP16 XSP16 XDATA
+ CFI StaticOverlayFrame CFA_IOVERLAY IOVERLAY
+ CFI StaticOverlayFrame CFA_DOVERLAY DOVERLAY
+ CFI Resource `PSW.CY`:1, `B.BR0`:1, `B.BR1`:1, `B.BR2`:1, `B.BR3`:1
+ CFI Resource `B.BR4`:1, `B.BR5`:1, `B.BR6`:1, `B.BR7`:1, `VB.BR8`:1
+ CFI Resource `VB.BR9`:1, `VB.BR10`:1, `VB.BR11`:1, `VB.BR12`:1
+ CFI Resource `VB.BR13`:1, `VB.BR14`:1, `VB.BR15`:1, VB:8, B:8, A:8
+ CFI Resource PSW:8, DPL0:8, DPH0:8, R0:8, R1:8, R2:8, R3:8, R4:8, R5:8
+ CFI Resource R6:8, R7:8, V0:8, V1:8, V2:8, V3:8, V4:8, V5:8, V6:8, V7:8
+ CFI Resource SP:8, PSPH:8, PSPL:8, PSP16:16, XSPH:8, XSPL:8, XSP16:16
+ CFI VirtualResource ?RET:16, ?RET_HIGH:8, ?RET_LOW:8
+ CFI ResourceParts PSP16 PSPH, PSPL
+ CFI ResourceParts XSP16 XSPH, XSPL
+ CFI ResourceParts ?RET ?RET_HIGH, ?RET_LOW
+ CFI EndNames cfiNames0
+
+ CFI Common cfiCommon0 Using cfiNames0
+ CFI CodeAlign 1
+ CFI DataAlign -1
+ CFI ReturnAddress ?RET CODE
+ CFI CFA_DOVERLAY Used
+ CFI CFA_IOVERLAY Used
+ CFI CFA_SP SP+-2
+ CFI CFA_PSP16 PSP16+0
+ CFI CFA_XSP16 XSP16+0
+ CFI `PSW.CY` SameValue
+ CFI `B.BR0` SameValue
+ CFI `B.BR1` SameValue
+ CFI `B.BR2` SameValue
+ CFI `B.BR3` SameValue
+ CFI `B.BR4` SameValue
+ CFI `B.BR5` SameValue
+ CFI `B.BR6` SameValue
+ CFI `B.BR7` SameValue
+ CFI `VB.BR8` SameValue
+ CFI `VB.BR9` SameValue
+ CFI `VB.BR10` SameValue
+ CFI `VB.BR11` SameValue
+ CFI `VB.BR12` SameValue
+ CFI `VB.BR13` SameValue
+ CFI `VB.BR14` SameValue
+ CFI `VB.BR15` SameValue
+ CFI VB SameValue
+ CFI B Undefined
+ CFI A Undefined
+ CFI PSW SameValue
+ CFI DPL0 Undefined
+ CFI DPH0 Undefined
+ CFI R0 Undefined
+ CFI R1 Undefined
+ CFI R2 Undefined
+ CFI R3 Undefined
+ CFI R4 Undefined
+ CFI R5 Undefined
+ CFI R6 SameValue
+ CFI R7 SameValue
+ CFI V0 SameValue
+ CFI V1 SameValue
+ CFI V2 SameValue
+ CFI V3 SameValue
+ CFI V4 SameValue
+ CFI V5 SameValue
+ CFI V6 SameValue
+ CFI V7 SameValue
+ CFI PSPH Undefined
+ CFI PSPL Undefined
+ CFI XSPH Undefined
+ CFI XSPL Undefined
+ CFI ?RET Concat
+ CFI ?RET_HIGH Frame(CFA_SP, 2)
+ CFI ?RET_LOW Frame(CFA_SP, 1)
+ CFI EndCommon cfiCommon0
+
+ EXTERN ?PSP
+
+ RSEG NEAR_CODE:CODE:NOROOT(0)
+ // void __pdata *getpsp(void)
+getpsp:
+ CFI Block cfiBlock0 Using cfiCommon0
+ CFI Function getpsp
+ CODE
+ MOV R1,?PSP
+ RET
+ CFI EndBlock cfiBlock0
+
+ END
diff --git a/libs/libmf/source/getxspiar.s51 b/libs/libmf/source/getxspiar.s51
new file mode 100644
index 00000000..0f178051
--- /dev/null
+++ b/libs/libmf/source/getxspiar.s51
@@ -0,0 +1,112 @@
+ MODULE getxsp
+
+ //RTMODEL "__SystemLibrary", "CLib"
+ //RTMODEL "__calling_convention", "data_overlay"
+ RTMODEL "__code_model", "near"
+ RTMODEL "__core", "plain"
+ //RTMODEL "__data_model", "small"
+ RTMODEL "__dptr_size", "16"
+ RTMODEL "__extended_stack", "disabled"
+ //RTMODEL "__location_for_constants", "code"
+ RTMODEL "__number_of_dptrs", "1"
+ RTMODEL "__rt_version", "1"
+
+ RSEG DOVERLAY:DATA:NOROOT(0)
+ RSEG IOVERLAY:IDATA:NOROOT(0)
+ RSEG ISTACK:IDATA:NOROOT(0)
+ RSEG PSTACK:XDATA:NOROOT(0)
+ RSEG XSTACK:XDATA:NOROOT(0)
+
+ PUBLIC getxsp
+ FUNCTION getxsp,0203H
+
+ CFI Names cfiNames0
+ CFI StackFrame CFA_SP SP IDATA
+ CFI StackFrame CFA_PSP16 PSP16 XDATA
+ CFI StackFrame CFA_XSP16 XSP16 XDATA
+ CFI StaticOverlayFrame CFA_IOVERLAY IOVERLAY
+ CFI StaticOverlayFrame CFA_DOVERLAY DOVERLAY
+ CFI Resource `PSW.CY`:1, `B.BR0`:1, `B.BR1`:1, `B.BR2`:1, `B.BR3`:1
+ CFI Resource `B.BR4`:1, `B.BR5`:1, `B.BR6`:1, `B.BR7`:1, `VB.BR8`:1
+ CFI Resource `VB.BR9`:1, `VB.BR10`:1, `VB.BR11`:1, `VB.BR12`:1
+ CFI Resource `VB.BR13`:1, `VB.BR14`:1, `VB.BR15`:1, VB:8, B:8, A:8
+ CFI Resource PSW:8, DPL0:8, DPH0:8, R0:8, R1:8, R2:8, R3:8, R4:8, R5:8
+ CFI Resource R6:8, R7:8, V0:8, V1:8, V2:8, V3:8, V4:8, V5:8, V6:8, V7:8
+ CFI Resource SP:8, PSPH:8, PSPL:8, PSP16:16, XSPH:8, XSPL:8, XSP16:16
+ CFI VirtualResource ?RET:16, ?RET_HIGH:8, ?RET_LOW:8
+ CFI ResourceParts PSP16 PSPH, PSPL
+ CFI ResourceParts XSP16 XSPH, XSPL
+ CFI ResourceParts ?RET ?RET_HIGH, ?RET_LOW
+ CFI EndNames cfiNames0
+
+ CFI Common cfiCommon0 Using cfiNames0
+ CFI CodeAlign 1
+ CFI DataAlign -1
+ CFI ReturnAddress ?RET CODE
+ CFI CFA_DOVERLAY Used
+ CFI CFA_IOVERLAY Used
+ CFI CFA_SP SP+-2
+ CFI CFA_PSP16 PSP16+0
+ CFI CFA_XSP16 XSP16+0
+ CFI `PSW.CY` SameValue
+ CFI `B.BR0` SameValue
+ CFI `B.BR1` SameValue
+ CFI `B.BR2` SameValue
+ CFI `B.BR3` SameValue
+ CFI `B.BR4` SameValue
+ CFI `B.BR5` SameValue
+ CFI `B.BR6` SameValue
+ CFI `B.BR7` SameValue
+ CFI `VB.BR8` SameValue
+ CFI `VB.BR9` SameValue
+ CFI `VB.BR10` SameValue
+ CFI `VB.BR11` SameValue
+ CFI `VB.BR12` SameValue
+ CFI `VB.BR13` SameValue
+ CFI `VB.BR14` SameValue
+ CFI `VB.BR15` SameValue
+ CFI VB SameValue
+ CFI B Undefined
+ CFI A Undefined
+ CFI PSW SameValue
+ CFI DPL0 Undefined
+ CFI DPH0 Undefined
+ CFI R0 Undefined
+ CFI R1 Undefined
+ CFI R2 Undefined
+ CFI R3 Undefined
+ CFI R4 Undefined
+ CFI R5 Undefined
+ CFI R6 SameValue
+ CFI R7 SameValue
+ CFI V0 SameValue
+ CFI V1 SameValue
+ CFI V2 SameValue
+ CFI V3 SameValue
+ CFI V4 SameValue
+ CFI V5 SameValue
+ CFI V6 SameValue
+ CFI V7 SameValue
+ CFI PSPH Undefined
+ CFI PSPL Undefined
+ CFI XSPH Undefined
+ CFI XSPL Undefined
+ CFI ?RET Concat
+ CFI ?RET_HIGH Frame(CFA_SP, 2)
+ CFI ?RET_LOW Frame(CFA_SP, 1)
+ CFI EndCommon cfiCommon0
+
+ EXTERN ?XSP
+
+ RSEG NEAR_CODE:CODE:NOROOT(0)
+ // void __xdata *getxsp(void)
+getxsp:
+ CFI Block cfiBlock0 Using cfiCommon0
+ CFI Function getxsp
+ CODE
+ MOV R2,?XSP
+ MOV R3,?XSP+1
+ RET
+ CFI EndBlock cfiBlock0
+
+ END
diff --git a/libs/libmf/source/graydec8.c b/libs/libmf/source/graydec8.c
new file mode 100644
index 00000000..7da5812c
--- /dev/null
+++ b/libs/libmf/source/graydec8.c
@@ -0,0 +1,54 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t gray_decode8(uint8_t x) __reentrant
+{
+ __asm
+ mov a,dpl
+ rr a
+ anl a,#0x40
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x20
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x10
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x08
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x04
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x02
+ xrl dpl,a
+ mov a,dpl
+ rr a
+ anl a,#0x01
+ xrl dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t gray_decode8(uint8_t x) __reentrant
+{
+ x ^= (x >> 1) & 0x40;
+ x ^= (x >> 1) & 0x20;
+ x ^= (x >> 1) & 0x10;
+ x ^= (x >> 1) & 0x08;
+ x ^= (x >> 1) & 0x04;
+ x ^= (x >> 1) & 0x02;
+ x ^= (x >> 1) & 0x01;
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/grayenc8.c b/libs/libmf/source/grayenc8.c
new file mode 100644
index 00000000..3dfa6b4b
--- /dev/null
+++ b/libs/libmf/source/grayenc8.c
@@ -0,0 +1,24 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t gray_encode8(uint8_t x) __reentrant
+{
+ __asm
+ mov a,dpl
+ clr c
+ rrc a
+ xrl dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t gray_encode8(uint8_t x) __reentrant
+{
+ x ^= x >> 1;
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/hweight16.c b/libs/libmf/source/hweight16.c
new file mode 100644
index 00000000..d4d19b15
--- /dev/null
+++ b/libs/libmf/source/hweight16.c
@@ -0,0 +1,28 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t hweight16(uint16_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ lcall _hweight8
+ mov a,dpl
+ xch a,dph
+ mov dpl,a
+ lcall _hweight8
+ mov a,dph
+ add a,dpl
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t hweight16(uint16_t x) __reentrant
+{
+ return hweight8(x) + hweight8(x >> 8);
+}
+
+#endif
diff --git a/libs/libmf/source/hweight32.c b/libs/libmf/source/hweight32.c
new file mode 100644
index 00000000..1ad01eb9
--- /dev/null
+++ b/libs/libmf/source/hweight32.c
@@ -0,0 +1,33 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t hweight32(uint32_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ push acc
+ lcall _hweight16
+ mov dph,a
+ pop dpl
+ lcall _hweight8
+ mov a,dph
+ add a,dpl
+ mov dph,a
+ mov dpl,b
+ lcall _hweight8
+ mov a,dph
+ add a,dpl
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t hweight32(uint32_t x) __reentrant
+{
+ return hweight8(x) + hweight8(x >> 8) + hweight8(x >> 16) + hweight8(x >> 24);
+}
+
+#endif
diff --git a/libs/libmf/source/hweight8.c b/libs/libmf/source/hweight8.c
new file mode 100644
index 00000000..1b0e4d1a
--- /dev/null
+++ b/libs/libmf/source/hweight8.c
@@ -0,0 +1,43 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb uint8_t hweight8(uint8_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ mov a,dpl
+ anl a,#0x55
+ xch a,dpl
+ rr a
+ anl a,#0x55
+ add a,dpl
+ mov dpl,a
+ anl a,#0x33
+ xch a,dpl
+ rr a
+ rr a
+ anl a,#0x33
+ add a,dpl
+ mov dpl,a
+ anl a,#0x0f
+ xch a,dpl
+ swap a
+ anl a,#0x0f
+ add a,dpl
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t hweight8(uint8_t x) __reentrant
+{
+ x = (x & 0x55) + ((x >> 1) & 0x55);
+ x = (x & 0x33) + ((x >> 2) & 0x33);
+ x = (x & 0x0F) + ((x >> 4) & 0x0F);
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/iorx.c b/libs/libmf/source/iorx.c
new file mode 100644
index 00000000..00ac15bf
--- /dev/null
+++ b/libs/libmf/source/iorx.c
@@ -0,0 +1,91 @@
+#include "ax8052.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_poll uart0_poll
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txdone uart0_wait_txdone
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_poll uart1_poll
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txdone uart1_wait_txdone
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_poll dbglink_poll
+#define uart_txidle dbglink_txidle
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txdone dbglink_wait_txdone
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#else
+#error "UART not set"
+#endif
+
+__reentrantb void uart_wait_rxcount(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_rxcount() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb uint8_t uart_rx(void) __reentrant
+{
+ uint8_t x;
+ uart_wait_rxcount(1);
+ x = uart_rxpeek(0);
+ uart_rxadvance(1);
+ return x;
+}
diff --git a/libs/libmf/source/iorxbuf.c b/libs/libmf/source/iorxbuf.c
new file mode 100644
index 00000000..b6bfc946
--- /dev/null
+++ b/libs/libmf/source/iorxbuf.c
@@ -0,0 +1,20 @@
+#include "ax8052.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+
+UART0_DEFINE_RXBUFFER(64)
+
+#elif UART == 1
+#include "libmfuart1.h"
+
+UART1_DEFINE_RXBUFFER(64)
+
+#elif UART == 2
+#include "libmfdbglink.h"
+
+DBGLINK_DEFINE_RXBUFFER(64)
+
+#else
+#error "UART not set"
+#endif
diff --git a/libs/libmf/source/iotx.c b/libs/libmf/source/iotx.c
new file mode 100644
index 00000000..0c8a9a44
--- /dev/null
+++ b/libs/libmf/source/iotx.c
@@ -0,0 +1,119 @@
+#include "ax8052.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_poll uart0_poll
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txdone uart0_wait_txdone
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_poll uart1_poll
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txdone uart1_wait_txdone
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_poll dbglink_poll
+#define uart_txidle dbglink_txidle
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txdone dbglink_wait_txdone
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#elif UART == 4
+#include "libaxlcd2.h"
+#define uart_poll lcd2_poll
+#define uart_txidle lcd2_txidle
+#define uart_txfree lcd2_txfree
+#define uart_wait_txdone lcd2_wait_txdone
+#define uart_wait_txfree lcd2_wait_txfree
+#define uart_txpokehex lcd2_txpokehex
+#define uart_txpoke lcd2_txpoke
+#define uart_txadvance lcd2_txadvance
+#define uart_tx lcd2_tx
+#define uart_writestr lcd2_writestr
+#define uart_writehexu16 lcd2_writehexu16
+#define uart_writehexu32 lcd2_writehexu32
+#define uart_writeu16 lcd2_writeu16
+#define uart_writeu32 lcd2_writeu32
+#else
+#error "UART not set"
+#endif
+
+__reentrantb void uart_wait_txfree(uint8_t v) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txfree() >= v)
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_wait_txdone(void) __reentrant
+{
+ uint8_t iesave = (IE & 0x80);
+ for (;;) {
+ EA = 0;
+ if (uart_txidle())
+ break;
+ if (!uart_poll())
+ wtimer_standby();
+ IE |= iesave;
+ }
+ IE |= iesave;
+}
+
+__reentrantb void uart_tx(uint8_t v) __reentrant
+{
+ uart_wait_txfree(1);
+ uart_txpoke(0, v);
+ uart_txadvance(1);
+}
diff --git a/libs/libmf/source/iotxbuf.c b/libs/libmf/source/iotxbuf.c
new file mode 100644
index 00000000..e41247aa
--- /dev/null
+++ b/libs/libmf/source/iotxbuf.c
@@ -0,0 +1,20 @@
+#include "ax8052.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+
+UART0_DEFINE_TXBUFFER(64)
+
+#elif UART == 1
+#include "libmfuart1.h"
+
+UART1_DEFINE_TXBUFFER(64)
+
+#elif UART == 2
+#include "libmfdbglink.h"
+
+DBGLINK_DEFINE_TXBUFFER(64)
+
+#else
+#error "UART not set"
+#endif
diff --git a/libs/libmf/source/iowrhex16.c b/libs/libmf/source/iowrhex16.c
new file mode 100644
index 00000000..cc1759d4
--- /dev/null
+++ b/libs/libmf/source/iowrhex16.c
@@ -0,0 +1,358 @@
+#include "wrnum.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writehex16 uart0_writehex16
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writehex16 uart1_writehex16
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writehex16 dbglink_writehex16
+#elif UART == 3
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writehex16 lcd_writehex16
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_tx(x) do { lcd2_tx(x); } while (0)
+#define _uart_tx _lcd2_tx
+#define uart_writehex16 lcd2_writehex16
+#else
+#error "UART not set"
+#endif
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writehex16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 4;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/source/iowrhex32.c b/libs/libmf/source/iowrhex32.c
new file mode 100644
index 00000000..d92e23c9
--- /dev/null
+++ b/libs/libmf/source/iowrhex32.c
@@ -0,0 +1,376 @@
+#include "wrnum.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writehex32 uart0_writehex32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writehex32 uart1_writehex32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writehex32 dbglink_writehex32
+#elif UART == 3
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writehex32 lcd_writehex32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_tx(x) do { lcd2_tx(x); } while (0)
+#define _uart_tx _lcd2_tx
+#define uart_writehex32 lcd2_writehex32
+#else
+#error "UART not set"
+#endif
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 4)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-5
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = val >> (4 * (cnt - 1));
+ mov a,r3
+ dec a
+ clr c
+ rrc a
+ jnz 00032$
+ mov a,dpl
+ sjmp 00031$
+00032$: dec a
+ jnz 00033$
+ mov a,dph
+ sjmp 00031$
+00033$: dec a
+ jnz 00034$
+ mov a,r7
+ sjmp 00031$
+00034$: dec a
+ jnz 00035$
+ mov a,r6
+ sjmp 00031$
+00035$: clr a
+00031$: jnc 00036$
+ swap a
+00036$:
+ ; d &= 0x0F;
+ anl a,#0x0F
+ ; if (d >= 10) {
+ ; if (flags & WRNUM_LCHEX)
+ ; d += 'a' - '9' - 1;
+ ; else
+ ; d += 'A' - '9' - 1;
+ ; }
+ add a,#-10
+ jc 00051$
+ add a,#10
+ sjmp 00050$
+00051$: add a,#17
+ jnb WRNUM_BIT_LCHEX,00050$
+ add a,#32
+00050$: mov r4,a
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ ;mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-5
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writehex32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 8;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 4)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = val >> (4 * (cnt - 1));
+ d &= 0x0F;
+ if (d >= 10) {
+ if (flags & WRNUM_LCHEX)
+ d += 'a' - '9' - 1;
+ else
+ d += 'A' - '9' - 1;
+ }
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 5)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/source/iowrhexu16.c b/libs/libmf/source/iowrhexu16.c
new file mode 100644
index 00000000..1586353c
--- /dev/null
+++ b/libs/libmf/source/iowrhexu16.c
@@ -0,0 +1,86 @@
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_poll lcd2_poll
+#define uart_txidle lcd2_txidle
+#define uart_txfree lcd2_txfree
+#define uart_wait_txdone lcd2_wait_txdone
+#define uart_wait_txfree lcd2_wait_txfree
+#define uart_txpokehex lcd2_txpokehex
+#define uart_txpoke lcd2_txpoke
+#define uart_txadvance lcd2_txadvance
+#define uart_tx lcd2_tx
+#define uart_writestr lcd2_writestr
+#define uart_writehexu16 lcd2_writehexu16
+#define uart_writehexu32 lcd2_writehexu32
+#define uart_writeu16 lcd2_writeu16
+#define uart_writeu32 lcd2_writeu32
+#else
+#error "UART not set"
+#endif
+
+__reentrantb void uart_writehexu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/source/iowrhexu32.c b/libs/libmf/source/iowrhexu32.c
new file mode 100644
index 00000000..d15cf0c8
--- /dev/null
+++ b/libs/libmf/source/iowrhexu32.c
@@ -0,0 +1,86 @@
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_poll lcd2_poll
+#define uart_txidle lcd2_txidle
+#define uart_txfree lcd2_txfree
+#define uart_wait_txdone lcd2_wait_txdone
+#define uart_wait_txfree lcd2_wait_txfree
+#define uart_txpokehex lcd2_txpokehex
+#define uart_txpoke lcd2_txpoke
+#define uart_txadvance lcd2_txadvance
+#define uart_tx lcd2_tx
+#define uart_writestr lcd2_writestr
+#define uart_writehexu16 lcd2_writehexu16
+#define uart_writehexu32 lcd2_writehexu32
+#define uart_writeu16 lcd2_writeu16
+#define uart_writeu32 lcd2_writeu32
+#else
+#error "UART not set"
+#endif
+
+void uart_writehexu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ --digit;
+ uart_txpokehex(digit, val);
+ val >>= 4;
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/source/iowrnum16.c b/libs/libmf/source/iowrnum16.c
new file mode 100644
index 00000000..718ae5aa
--- /dev/null
+++ b/libs/libmf/source/iowrnum16.c
@@ -0,0 +1,328 @@
+#include "wrnum.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writenum16 uart0_writenum16
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writenum16 uart1_writenum16
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writenum16 dbglink_writenum16
+#elif UART == 3
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writenum16 lcd_writenum16
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_tx(x) do { lcd2_tx(x); } while (0)
+#define _uart_tx _lcd2_tx
+#define uart_writenum16 lcd2_writenum16
+#else
+#error "UART not set"
+#endif
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 5;
+ mov r3,#5
+ ; if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,dph
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00020$
+ mov a,r2
+ add a,#-4
+ jnc 00020$
+ dec r2
+00020$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ mov a,r3
+ mov r4,a
+ ; val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ mov a,#ar4
+ push acc
+ lcall _libmf_num16_digit
+ dec sp
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov a,r4
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jnz 00038$
+ ; uart_tx('\'');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t uart_writenum16(uint16_t val, uint8_t nrdig1, uint8_t flags1) __reentrant
+{
+ char ch = 0;
+ uint8_t d;
+ uint8_t cnt = 5;
+ uint8_t flags = flags1;
+ uint8_t nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && (int16_t)val < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num16_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/source/iowrnum32.c b/libs/libmf/source/iowrnum32.c
new file mode 100644
index 00000000..af11954b
--- /dev/null
+++ b/libs/libmf/source/iowrnum32.c
@@ -0,0 +1,368 @@
+#include "wrnum.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_tx(x) do { uart0_tx(x); } while (0)
+#define _uart_tx _uart0_tx
+#define uart_writenum32 uart0_writenum32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_tx(x) do { uart1_tx(x); } while (0)
+#define _uart_tx _uart1_tx
+#define uart_writenum32 uart1_writenum32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_tx(x) do { dbglink_tx(x); } while (0)
+#define _uart_tx _dbglink_tx
+#define uart_writenum32 dbglink_writenum32
+#elif UART == 3
+#include "libmflcd.h"
+#define uart_tx(x) do { lcd_writedata(x); lcd_waitshort(); } while (0)
+#define uart_writenum32 lcd_writenum32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_tx(x) do { lcd2_tx(x); } while (0)
+#define _uart_tx _lcd2_tx
+#define uart_writenum32 lcd2_writenum32
+#else
+#error "UART not set"
+#endif
+
+#if defined(SDCC) && UART != 3
+
+#define WRNUM_BIT_SIGNED _B_0
+#define WRNUM_BIT_PLUS _B_1
+#define WRNUM_BIT_ZEROPLUS _B_2
+#define WRNUM_BIT_PADZERO _B_3
+#define WRNUM_BIT_TSDSEP _B_4
+#define WRNUM_BIT_LCHEX _B_5
+#define WRNUM_BIT_DIGSET _B_6
+#define WRNUM_BIT_DIGCONT _B_7
+
+#define ASCII_PLUS 0x2b
+#define ASCII_MINUS 0x2d
+#define ASCII_SPACE 0x20
+#define ASCII_0 0x30
+#define ASCII_APOSTROPHE 0x27
+
+__reentrantb uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1) __reentrant __naked
+{
+ val;
+ nrdig1;
+ flags1;
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ mov r6,a
+ mov r7,b
+ ; uint8_t flags = flags1;
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ inc r0
+ anl a,#WRNUM_MASK
+ mov b,a
+ ; uint8_t nrdig = nrdig1;
+ mov a,@r0
+ mov r2,a
+ ; char ch = 0
+ mov r0,#0
+ ; uint8_t d;
+ ; --> r4
+ ; uint8_t cnt = 10;
+ mov r3,#10
+ ; if ((flags & WRNUM_SIGNED) && (int32_t)val < 0) {
+ ; val = -val;
+ ; ch = '-';
+ ; } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ; ch = '+';
+ ; }
+ jnb WRNUM_BIT_SIGNED,00011$
+ mov a,r6
+ jnb acc.7,00011$
+ clr c
+ clr a
+ subb a,dpl
+ mov dpl,a
+ clr a
+ subb a,dph
+ mov dph,a
+ clr a
+ subb a,r7
+ mov r7,a
+ clr a
+ subb a,r6
+ mov r6,a
+ mov r0,#ASCII_MINUS
+ sjmp 00010$
+00011$: jb WRNUM_BIT_ZEROPLUS,00012$
+ jnb WRNUM_BIT_PLUS,00010$
+ mov a,dph
+ orl a,dpl
+ orl a,r7
+ orl a,r6
+ jz 00010$
+00012$: mov r0,#ASCII_PLUS
+00010$:
+ ; if (ch && nrdig > 0)
+ ; --nrdig;
+ mov a,r0
+ jz 00018$
+ mov a,r2
+ jz 00018$
+ dec a
+ mov r2,a
+00018$:
+ ; if (flags & WRNUM_TSDSEP) {
+ ; if (nrdig > 9)
+ ; --nrdig;
+ ; if (nrdig > 6)
+ ; --nrdig;
+ ; if (nrdig > 3)
+ ; --nrdig;
+ ; }
+ jnb WRNUM_BIT_TSDSEP,00022$
+ mov a,r2
+ add a,#-10
+ jnc 00020$
+ dec r2
+00020$: mov a,r2
+ add a,#-7
+ jnc 00021$
+ dec r2
+00021$: mov a,r2
+ add a,#-4
+ jnc 00022$
+ dec r2
+00022$:
+ ; flags &= WRNUM_MASK;
+ ; if (cnt < nrdig)
+ ; cnt = nrdig;
+ clr c
+ mov a,r3
+ subb a,r2
+ jnc 00028$
+ mov a,r2
+ mov r3,a
+00028$:
+ ; do {
+00030$:
+ ; d = cnt;
+ push ar3
+ ; val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ mov a,sp
+ push b
+ push acc
+ mov b,r7
+ mov a,r6
+ lcall _libmf_num32_digit
+ mov r6,a
+ mov r7,b
+ dec sp
+ pop b
+ pop acc
+
+ ; if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ mov r4,a
+ jnz 00040$
+ mov a,r3
+ dec a
+ jz 00040$
+ jb WRNUM_BIT_DIGCONT,00040$
+ ; if (cnt > nrdig)
+ ; continue;
+ mov a,r2
+ clr c
+ subb a,r3
+ jc 00038$
+ ; if (!(flags & WRNUM_PADZERO)) {
+ jb WRNUM_BIT_PADZERO,00040$
+ ; if (!(flags & WRNUM_DIGSET)) {
+ jb WRNUM_BIT_DIGSET,00041$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+ ; flags |= WRNUM_DIGSET;
+ setb WRNUM_BIT_DIGSET
+ ; }
+00041$:
+ ; uart_tx(' ');
+ push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00042$
+ add a,#-3
+ jz 00042$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx(' ');
+00042$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_SPACE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; continue;
+ ;sjmp 00038$
+ ; }
+ ; }
+
+ ; } while (--cnt);
+00038$: djnz r3,00030$
+ ; return nrdig;
+ mov dpl,r2
+ ret
+
+00040$:
+ ; if (!(flags & WRNUM_DIGCONT)) {
+ jb WRNUM_BIT_DIGCONT,00048$
+ ; if (!(flags & WRNUM_DIGSET))
+ jb WRNUM_BIT_DIGSET,00049$
+ ; nrdig = cnt;
+ mov a,r3
+ mov r2,a
+00049$:
+ ; flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ mov a,#WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET
+ orl b,a
+ ; if (ch) {
+ mov a,r0
+ jz 00048$
+ ; uart_tx(ch);
+ push b
+ push dpl
+ push dph
+ mov dpl,r0
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ ; }
+00048$:
+ ; uart_tx('0' + d);
+ push b
+ push dpl
+ push dph
+ mov a,r4
+ add a,#ASCII_0
+ mov dpl,a
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ jnb WRNUM_BIT_TSDSEP,00038$
+ mov a,r3
+ add a,#-4
+ jz 00050$
+ add a,#-3
+ jz 00050$
+ add a,#-3
+ jnz 00038$
+ ; uart_tx('\'');
+00050$: push b
+ push dpl
+ push dph
+ mov dpl,#ASCII_APOSTROPHE
+ lcall _uart_tx
+ pop dph
+ pop dpl
+ pop b
+ ; ++nrdig;
+ inc r2
+ ; }
+ sjmp 00038$
+ __endasm;
+}
+
+#else
+
+uint8_t uart_writenum32(uint32_t val, uint8_t nrdig1, uint8_t flags1)
+{
+ char __autodata ch = 0;
+ uint8_t __autodata d;
+ uint8_t __autodata cnt = 10;
+ uint8_t __autodata flags = flags1;
+ uint8_t __autodata nrdig = nrdig1;
+
+ if ((flags & WRNUM_SIGNED) && ((int32_t)val) < 0) {
+ val = -val;
+ ch = '-';
+ } else if ((flags & WRNUM_ZEROPLUS) || ((flags & WRNUM_PLUS) && val)) {
+ ch = '+';
+ }
+ if (ch && nrdig > 0)
+ --nrdig;
+ if (flags & WRNUM_TSDSEP) {
+ if (nrdig > 9)
+ --nrdig;
+ if (nrdig > 6)
+ --nrdig;
+ if (nrdig > 3)
+ --nrdig;
+ }
+ flags &= WRNUM_MASK;
+ if (cnt < nrdig)
+ cnt = nrdig;
+ do {
+ d = cnt;
+ val = libmf_num32_digit(val, (uint8_t __auto *)&d);
+ if (!d && cnt != 1 && !(flags & WRNUM_DIGCONT)) {
+ if (cnt > nrdig)
+ continue;
+ if (!(flags & WRNUM_PADZERO)) {
+ if (!(flags & WRNUM_DIGSET)) {
+ nrdig = cnt;
+ flags |= WRNUM_DIGSET;
+ }
+ uart_tx(' ');
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx(' ');
+ ++nrdig;
+ }
+ continue;
+ }
+ }
+ if (!(flags & WRNUM_DIGCONT)) {
+ if (!(flags & WRNUM_DIGSET))
+ nrdig = cnt;
+ flags |= WRNUM_PADZERO | WRNUM_DIGCONT | WRNUM_DIGSET;
+ if (ch) {
+ uart_tx(ch);
+ ++nrdig;
+ }
+ }
+ uart_tx('0' + d);
+ if ((flags & WRNUM_TSDSEP) && (cnt == 4 || cnt == 7 || cnt == 10)) {
+ uart_tx('\'');
+ ++nrdig;
+ }
+ } while (--cnt);
+ return nrdig;
+}
+
+#endif
diff --git a/libs/libmf/source/iowrstr.c b/libs/libmf/source/iowrstr.c
new file mode 100644
index 00000000..1aa7c004
--- /dev/null
+++ b/libs/libmf/source/iowrstr.c
@@ -0,0 +1,187 @@
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define _uart_wait_txfree _uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txfreelinear _uart0_txfreelinear
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define _uart_txadvance _uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define _uart_wait_txfree _uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txfreelinear _uart1_txfreelinear
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define _uart_txadvance _uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define _uart_wait_txfree _dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_txbufptr dbglink_txbufptr
+#define _uart_txbufptr _dbglink_txbufptr
+#define uart_txfreelinear dbglink_txfreelinear
+#define _uart_txfreelinear _dbglink_txfreelinear
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define _uart_txadvance _dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#else
+#error "UART not set"
+#endif
+
+#if defined(SDCC)
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ ch;
+ __asm;
+ mov r0,dpl
+ mov r7,dph
+ clr a
+ mov r3,a
+ mov r2,a
+00000$: jb _B_7,00010$ ; >0x80 code
+ jnb _B_6,00011$ ; <0x40 far
+ jb _B_5,00012$ ; >0x60 pdata
+ ;; idata
+ mov a,@r0
+ inc r0
+ sjmp 00013$
+00010$: ;; code
+ mov dpl,r0
+ mov dph,r7
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00011$: ;; xdata
+ mov dpl,r0
+ mov dph,r7
+ movx a,@dptr
+ inc dptr
+ mov r0,dpl
+ mov r7,dph
+ sjmp 00013$
+00012$: ;; pdata
+ movx a,@r0
+ inc r0
+00013$: jz 00001$
+ mov r1,a
+ mov a,r3
+ jnz 00002$
+ mov a,r2
+ jz 00003$
+ mov dpl,a
+ lcall _uart_txadvance
+00003$: lcall _uart_txfreelinear
+ mov a,dpl
+ jnz 00004$
+ mov r4,b
+ mov dpl,#1
+ lcall _uart_wait_txfree
+ mov b,r4
+ lcall _uart_txfreelinear
+ mov a,dpl
+00004$: mov r3,a
+ clr a
+ mov r2,a
+ mov dpl,a
+ lcall _uart_txbufptr
+ mov r4,dpl
+ mov r5,dph
+00002$: mov dpl,r4
+ mov dph,r5
+ mov a,r1
+ movx @dptr,a
+ inc dptr
+ mov r4,dpl
+ mov r5,dph
+ inc r2
+ dec r3
+ sjmp 00000$
+00001$: mov a,r2
+ jz 00005$
+ mov dpl,a
+ lcall _uart_txadvance
+00005$:
+ __endasm;
+}
+
+#else
+
+__reentrantb void uart_writestr(const char __generic *ch) __reentrant
+{
+ uint8_t __xdata *p;
+ uint8_t f = 0;
+ uint8_t a = 0;
+ for (;;) {
+ char c = *ch++;
+ if (!c)
+ break;
+ if (!f) {
+ if (a)
+ uart_txadvance(a);
+ f = uart_txfreelinear();
+ if (!f) {
+ uart_wait_txfree(1);
+ f = uart_txfreelinear();
+ }
+ p = uart_txbufptr(0);
+ a = 0;
+ }
+ *p++ = c;
+ ++a;
+ --f;
+ }
+ if (a)
+ uart_txadvance(a);
+}
+
+#endif
diff --git a/libs/libmf/source/iowru16.c b/libs/libmf/source/iowru16.c
new file mode 100644
index 00000000..8bab080c
--- /dev/null
+++ b/libs/libmf/source/iowru16.c
@@ -0,0 +1,88 @@
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_poll lcd2_poll
+#define uart_txidle lcd2_txidle
+#define uart_txfree lcd2_txfree
+#define uart_wait_txdone lcd2_wait_txdone
+#define uart_wait_txfree lcd2_wait_txfree
+#define uart_txpokehex lcd2_txpokehex
+#define uart_txpoke lcd2_txpoke
+#define uart_txadvance lcd2_txadvance
+#define uart_tx lcd2_tx
+#define uart_writestr lcd2_writestr
+#define uart_writehexu16 lcd2_writehexu16
+#define uart_writehexu32 lcd2_writehexu32
+#define uart_writeu16 lcd2_writeu16
+#define uart_writeu32 lcd2_writeu32
+#else
+#error "UART not set"
+#endif
+
+__reentrantb void uart_writeu16(uint16_t val, uint8_t nrdig) __reentrant
+{
+ uint8_t nrdig1 = nrdig;
+ uint8_t digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/source/iowru32.c b/libs/libmf/source/iowru32.c
new file mode 100644
index 00000000..7b5805f1
--- /dev/null
+++ b/libs/libmf/source/iowru32.c
@@ -0,0 +1,88 @@
+#if UART == 0
+#include "libmfuart0.h"
+#define uart_txfree uart0_txfree
+#define uart_rxcount uart0_rxcount
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define uart_writestr uart0_writestr
+#define uart_writehexu16 uart0_writehexu16
+#define uart_writehexu32 uart0_writehexu32
+#define uart_writeu16 uart0_writeu16
+#define uart_writeu32 uart0_writeu32
+#elif UART == 1
+#include "libmfuart1.h"
+#define uart_txfree uart1_txfree
+#define uart_rxcount uart1_rxcount
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define uart_writestr uart1_writestr
+#define uart_writehexu16 uart1_writehexu16
+#define uart_writehexu32 uart1_writehexu32
+#define uart_writeu16 uart1_writeu16
+#define uart_writeu32 uart1_writeu32
+#elif UART == 2
+#include "libmfdbglink.h"
+#define uart_txfree dbglink_txfree
+#define uart_rxcount dbglink_rxcount
+#define uart_wait_txfree dbglink_wait_txfree
+#define uart_wait_rxcount dbglink_wait_rxcount
+#define uart_rxpeek dbglink_rxpeek
+#define uart_txpokehex dbglink_txpokehex
+#define uart_txpoke dbglink_txpoke
+#define uart_rxadvance dbglink_rxadvance
+#define uart_txadvance dbglink_txadvance
+#define uart_rx dbglink_rx
+#define uart_tx dbglink_tx
+#define uart_writestr dbglink_writestr
+#define uart_writehexu16 dbglink_writehexu16
+#define uart_writehexu32 dbglink_writehexu32
+#define uart_writeu16 dbglink_writeu16
+#define uart_writeu32 dbglink_writeu32
+#elif UART == 4
+#include "libmflcd2.h"
+#define uart_poll lcd2_poll
+#define uart_txidle lcd2_txidle
+#define uart_txfree lcd2_txfree
+#define uart_wait_txdone lcd2_wait_txdone
+#define uart_wait_txfree lcd2_wait_txfree
+#define uart_txpokehex lcd2_txpokehex
+#define uart_txpoke lcd2_txpoke
+#define uart_txadvance lcd2_txadvance
+#define uart_tx lcd2_tx
+#define uart_writestr lcd2_writestr
+#define uart_writehexu16 lcd2_writehexu16
+#define uart_writehexu32 lcd2_writehexu32
+#define uart_writeu16 lcd2_writeu16
+#define uart_writeu32 lcd2_writeu32
+#else
+#error "UART not set"
+#endif
+
+void uart_writeu32(uint32_t val, uint8_t nrdig)
+{
+ uint8_t __autodata nrdig1 = nrdig;
+ uint8_t __autodata digit = nrdig1;
+ uart_wait_txfree(nrdig1);
+ while (digit) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ --digit;
+ uart_txpoke(digit, '0' + v1);
+ }
+ uart_txadvance(nrdig1);
+}
diff --git a/libs/libmf/source/lcdclear.c b/libs/libmf/source/lcdclear.c
new file mode 100644
index 00000000..aae8f656
--- /dev/null
+++ b/libs/libmf/source/lcdclear.c
@@ -0,0 +1,19 @@
+#include "libmflcd.h"
+
+void lcd_clear(uint8_t pos, uint8_t len)
+{
+ uint8_t __autodata x;
+ lcd_setpos(pos);
+ if (!len)
+ return;
+ x = pos & 0x3f;
+ if (x >= 0x10)
+ return;
+ x = 0x10 - x;
+ if (len > x)
+ len = x;
+ do {
+ lcd_waitshort();
+ lcd_writedata(' ');
+ } while (--len);
+}
diff --git a/libs/libmf/source/lcdclrdisp.c b/libs/libmf/source/lcdclrdisp.c
new file mode 100644
index 00000000..676a3809
--- /dev/null
+++ b/libs/libmf/source/lcdclrdisp.c
@@ -0,0 +1,6 @@
+#include "libmflcd.h"
+
+void lcd_cleardisplay(void)
+{
+ lcd_writecmd(0x01);
+}
diff --git a/libs/libmf/source/lcdinit.c b/libs/libmf/source/lcdinit.c
new file mode 100644
index 00000000..e3e82152
--- /dev/null
+++ b/libs/libmf/source/lcdinit.c
@@ -0,0 +1,121 @@
+#include "ax8052.h"
+#include "libmflcd.h"
+
+void lcd_waitlong(void)
+{
+ uint8_t __autodata a = 0x40;
+ do {
+ uint8_t __autodata b = 0;
+ do {
+ --b;
+ } while (b);
+ --a;
+ } while (a);
+}
+
+void lcd_waitshort(void)
+{
+ uint8_t __autodata a = 0;
+ do {
+ --a;
+ } while (a);
+}
+
+void lcd_write(uint8_t v)
+{
+ PORTC_0 = 0;
+ SPSHREG = v;
+ for (;;) {
+ uint8_t __autodata st = SPSTATUS;
+ if (st & 0x01)
+ break;
+ }
+ v = SPSHREG;
+ PORTC_0 = 1;
+}
+
+void lcd_writecmd(uint8_t cmd)
+{
+ PORTB_0 = 0;
+ lcd_write(cmd);
+}
+
+void lcd_writedata(uint8_t d)
+{
+ PORTB_0 = 1;
+ lcd_write(d);
+}
+
+void lcd_portoff(void)
+{
+ SPCLKSRC = 0x07;
+ SPMODE = 0x00;
+}
+
+void lcd_portinit(void)
+{
+ uint8_t __autodata x;
+ DIRB |= 0x03;
+ PORTB &= (uint8_t)~0x01;
+ PORTB_1 = 1;
+ DIRC |= 0x07;
+ PORTC |= 0x03;
+ PORTC &= (uint8_t)~0x04;
+ SPCLKSRC = 0xD8;
+ SPMODE = 0x01;
+ x = SPSHREG;
+}
+
+void lcd_init(void)
+{
+ uint8_t __autodata x;
+ DIRB |= 0x03;
+ PORTB &= (uint8_t)~0x03;
+ DIRC |= 0x07;
+ PORTC |= 0x03;
+ PORTC &= (uint8_t)~0x04;
+ SPCLKSRC = 0xD8;
+ SPMODE = 0x01;
+ x = SPSHREG;
+ PORTB_1 = 0;
+ lcd_waitlong();
+ PORTB_1 = 1;
+ // Init Display
+ lcd_waitlong();
+ // wake-up
+ lcd_writecmd(0x30);
+ lcd_waitlong();
+ // wake-up
+ lcd_writecmd(0x30);
+ lcd_waitshort();
+ // wake-up
+ lcd_writecmd(0x30);
+ lcd_waitshort();
+ // function set
+ lcd_writecmd(0x39);
+ lcd_waitshort();
+ // internal osc frequency
+ lcd_writecmd(0x14);
+ lcd_waitshort();
+ // power control
+ lcd_writecmd(0x56);
+ lcd_waitshort();
+ // follower control
+ lcd_writecmd(0x6d);
+ lcd_waitshort();
+ // contrast
+ lcd_writecmd(0x78);
+ lcd_waitshort();
+ // display on
+ lcd_writecmd(0x0c);
+ lcd_waitshort();
+ // entry mode
+ lcd_writecmd(0x06);
+ lcd_waitshort();
+ // clear display
+ lcd_writecmd(0x01);
+ lcd_waitlong();
+ // display on; cursor on
+ //lcd_writecmd(0x0f);
+ //lcd_waitshort();
+}
diff --git a/libs/libmf/source/lcdsetpos.c b/libs/libmf/source/lcdsetpos.c
new file mode 100644
index 00000000..067f79fe
--- /dev/null
+++ b/libs/libmf/source/lcdsetpos.c
@@ -0,0 +1,6 @@
+#include "libmflcd.h"
+
+void lcd_setpos(uint8_t v)
+{
+ lcd_writecmd(0x80 | v);
+}
diff --git a/libs/libmf/source/lcdwrhexu16.c b/libs/libmf/source/lcdwrhexu16.c
new file mode 100644
index 00000000..27a4c111
--- /dev/null
+++ b/libs/libmf/source/lcdwrhexu16.c
@@ -0,0 +1,18 @@
+#include "libmflcd.h"
+
+void lcd_writehexu16(uint16_t val, uint8_t nrdig, uint8_t pos)
+{
+ while (nrdig) {
+ uint8_t __autodata v1 = val;
+ val >>= 4;
+ v1 &= 0x0F;
+ if (v1 >= 10)
+ v1 += 'A' - '9' - 1;
+ lcd_setpos(pos);
+ lcd_waitshort();
+ lcd_writedata('0' + v1);
+ lcd_waitshort();
+ --pos;
+ --nrdig;
+ }
+}
diff --git a/libs/libmf/source/lcdwrhexu32.c b/libs/libmf/source/lcdwrhexu32.c
new file mode 100644
index 00000000..7580ec21
--- /dev/null
+++ b/libs/libmf/source/lcdwrhexu32.c
@@ -0,0 +1,18 @@
+#include "libmflcd.h"
+
+void lcd_writehexu32(uint32_t val, uint8_t nrdig, uint8_t pos)
+{
+ while (nrdig) {
+ uint8_t __autodata v1 = val;
+ val >>= 4;
+ v1 &= 0x0F;
+ if (v1 >= 10)
+ v1 += 'A' - '9' - 1;
+ lcd_setpos(pos);
+ lcd_waitshort();
+ lcd_writedata('0' + v1);
+ lcd_waitshort();
+ --pos;
+ --nrdig;
+ }
+}
diff --git a/libs/libmf/source/lcdwrstr.c b/libs/libmf/source/lcdwrstr.c
new file mode 100644
index 00000000..c2f751db
--- /dev/null
+++ b/libs/libmf/source/lcdwrstr.c
@@ -0,0 +1,16 @@
+#include "libmflcd.h"
+
+void lcd_writestr(const char __generic *ch)
+{
+ for (;;) {
+ char __autodata c = *ch++;
+ if (!c)
+ break;
+ if (c == '\n') {
+ lcd_writecmd(0xc0);
+ } else {
+ lcd_writedata(c);
+ }
+ lcd_waitshort();
+ }
+}
diff --git a/libs/libmf/source/lcdwru16.c b/libs/libmf/source/lcdwru16.c
new file mode 100644
index 00000000..9f5dde54
--- /dev/null
+++ b/libs/libmf/source/lcdwru16.c
@@ -0,0 +1,16 @@
+#include "libmflcd.h"
+
+void lcd_writeu16(uint16_t val, uint8_t nrdig, uint8_t pos)
+{
+ while (nrdig) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ lcd_setpos(pos);
+ lcd_waitshort();
+ lcd_writedata('0' + v1);
+ lcd_waitshort();
+ --pos;
+ --nrdig;
+ }
+}
diff --git a/libs/libmf/source/lcdwru32.c b/libs/libmf/source/lcdwru32.c
new file mode 100644
index 00000000..c8c43ca3
--- /dev/null
+++ b/libs/libmf/source/lcdwru32.c
@@ -0,0 +1,16 @@
+#include "libmflcd.h"
+
+void lcd_writeu32(uint32_t val, uint8_t nrdig, uint8_t pos)
+{
+ while (nrdig) {
+ uint8_t __autodata v1 = val;
+ val /= 10;
+ v1 -= 10 * (uint8_t)val;
+ lcd_setpos(pos);
+ lcd_waitshort();
+ lcd_writedata('0' + v1);
+ lcd_waitshort();
+ --pos;
+ --nrdig;
+ }
+}
diff --git a/libs/libmf/source/libmf.h b/libs/libmf/source/libmf.h
new file mode 100644
index 00000000..84245000
--- /dev/null
+++ b/libs/libmf/source/libmf.h
@@ -0,0 +1,14 @@
+#ifndef LIBMF_H
+#define LIBMF_H
+
+#include "libmftypes.h"
+#include "libmfdbglink.h"
+#include "libmfcrc.h"
+#include "libmfflash.h"
+#include "libmfuart.h"
+#include "libmfadc.h"
+#include "libmfbch.h"
+#include "libmfcalsector.h"
+#include "libmfradio.h"
+
+#endif /* LIBMF_H */
diff --git a/libs/libmf/source/libmfadc.h b/libs/libmf/source/libmfadc.h
new file mode 100644
index 00000000..5ad25272
--- /dev/null
+++ b/libs/libmf/source/libmfadc.h
@@ -0,0 +1,19 @@
+#ifndef LIBMFADC_H
+#define LIBMFADC_H
+
+#include "libmftypes.h"
+
+/*
+ * AD Converter
+ */
+extern __reentrantb int16_t adc_measure_temperature(void) __reentrant;
+
+extern void adc_calibrate_gain(void);
+extern void adc_calibrate_temp(void);
+extern void adc_calibrate(void);
+extern void adc_uncalibrate(void);
+extern uint16_t adc_singleended_offset_x01(void);
+extern uint16_t adc_singleended_offset_x1(void);
+extern uint16_t adc_singleended_offset_x10(void);
+
+#endif /* LIBMFADC_H */
diff --git a/libs/libmf/source/libmfbch.h b/libs/libmf/source/libmfbch.h
new file mode 100644
index 00000000..e212a34b
--- /dev/null
+++ b/libs/libmf/source/libmfbch.h
@@ -0,0 +1,27 @@
+#ifndef LIBMFBCH_H
+#define LIBMFBCH_H
+
+#include "libmftypes.h"
+
+/*
+ * BCH(31,21,5) Code (with and without parity) routines
+ * Data Format:
+ * Bits 31-11: Data
+ * Bits 10- 1: BCH Parity Bits
+ * Bit 0: Even Parity Bit
+ */
+
+extern uint16_t bch3121_syndrome(uint32_t cw);
+extern uint32_t bch3121_encode(uint32_t cw);
+extern uint32_t bch3121_encode_parity(uint32_t cw);
+
+/* Bit 0 of the return value indicates decoding error */
+extern uint32_t bch3121_decode(uint32_t cw);
+extern uint32_t bch3121_decode_parity(uint32_t cw);
+
+/*
+ * BCH Internals
+ */
+extern const uint16_t __code bch3121_syndrometable[1024];
+
+#endif /* LIBMFBCH_H */
diff --git a/libs/libmf/source/libmfcalsector.h b/libs/libmf/source/libmfcalsector.h
new file mode 100644
index 00000000..55f19d31
--- /dev/null
+++ b/libs/libmf/source/libmfcalsector.h
@@ -0,0 +1,35 @@
+#ifndef LIBMFCALSECTOR_H
+#define LIBMFCALSECTOR_H
+
+#include "libmftypes.h"
+
+/*
+ * FLASH Calibration Sector Layout
+ */
+
+struct calsector {
+ uint8_t id[5]; /* ID: 0x80, 0xFE, CAL */
+ uint8_t len; /* Length, excluding id, but including len */
+ uint8_t devid[6]; /* arbitrary device ID */
+ uint8_t calg00gain[2]; /* ADC x0.1 Gain Calibration */
+ uint8_t calg01gain[2]; /* ADC x1 Gain Calibration */
+ uint8_t calg10gain[2]; /* ADC x10 Gain Calibration */
+ uint8_t caltempgain[2]; /* ADC Temperature Gain Calibration */
+ uint8_t caltempoffs[2]; /* ADC Temperature Offset Calibration */
+ uint8_t frcoscfreq[2]; /* Fast RC Oscillator Frequency Calibration */
+ uint8_t lposcfreq[2]; /* Low Power Oscillator Frequency Calibration, Slow Mode */
+ uint8_t lposcfreq_fast[2]; /* Low Power Oscillator Frequency Calibration, Fast Mode */
+ uint8_t powctrl0; /* VDD_CORE Calibration */
+ uint8_t powctrl1; /* VDD_SLEEP Calibration */
+ uint8_t ref; /* Ref Calibration */
+};
+
+#if defined(SDCC)
+static struct calsector __xdata __at(0xfc00) flash_calsector;
+#elif defined __CX51__ || defined __C51__
+static struct calsector xdata flash_calsector _at_ 0xfc00;
+#elif defined __ICC8051__
+extern __no_init struct calsector __xdata flash_calsector @ 0xfc00;
+#endif
+
+#endif /* LIBMFCALSECTOR_H */
diff --git a/libs/libmf/source/libmfcrc.h b/libs/libmf/source/libmfcrc.h
new file mode 100644
index 00000000..21ce7817
--- /dev/null
+++ b/libs/libmf/source/libmfcrc.h
@@ -0,0 +1,98 @@
+#ifndef LIBMFCRC_H
+#define LIBMFCRC_H
+
+#include "libmftypes.h"
+
+/*
+ * CRC-16 CCITT
+ */
+extern __reentrantb uint16_t crc_ccitt_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_ccitt_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_ccitt(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_ccitt_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_ccitt_table[256];
+extern const uint16_t __code crc_ccitt_msbtable[256];
+
+/*
+ * CRC-16
+ */
+extern __reentrantb uint16_t crc_crc16_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_crc16_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_crc16_table[256];
+extern const uint16_t __code crc_crc16_msbtable[256];
+
+/*
+ * CRC-16 DNP
+ */
+extern __reentrantb uint16_t crc_crc16dnp_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp_msb_byte(uint16_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern __reentrantb uint16_t crc_crc16dnp_msb(const uint8_t __generic *buf, uint16_t buflen, uint16_t crc) __reentrant;
+extern const uint16_t __code crc_crc16dnp_table[256];
+extern const uint16_t __code crc_crc16dnp_msbtable[256];
+
+/*
+ * CRC-32
+ */
+extern __reentrantb uint32_t crc_crc32_byte(uint32_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint32_t crc_crc32_msb_byte(uint32_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint32_t crc_crc32(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant;
+extern __reentrantb uint32_t crc_crc32_msb(const uint8_t __generic *buf, uint16_t buflen, uint32_t crc) __reentrant;
+extern const uint32_t __code crc_crc32_table[256];
+extern const uint32_t __code crc_crc32_msbtable[256];
+
+/*
+ * CRC-8 CCITT
+ */
+
+extern __reentrantb uint8_t crc_crc8ccitt_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt_msb_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern __reentrantb uint8_t crc_crc8ccitt_msb(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern const uint8_t __code crc_crc8ccitt_table[256];
+extern const uint8_t __code crc_crc8ccitt_msbtable[256];
+
+/*
+ * CRC-8 OneWire
+ */
+
+extern __reentrantb uint8_t crc_crc8onewire_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire_msb_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern __reentrantb uint8_t crc_crc8onewire_msb(const uint8_t __generic *buf, uint16_t buflen, uint8_t crc) __reentrant;
+extern const uint8_t __code crc_crc8onewire_table[256];
+extern const uint8_t __code crc_crc8onewire_msbtable[256];
+
+/*
+ * CRC-8 CCITT, non-table driven routines (slower, but more compact)
+ */
+extern __reentrantb uint8_t crc8_ccitt_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc8_ccitt(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant;
+
+/*
+ * CRC-8 OneWire, non-table driven routines (slower, but more compact)
+ */
+extern __reentrantb uint8_t crc8_onewire_byte(uint8_t crc, uint8_t c) __reentrant;
+extern __reentrantb uint8_t crc8_onewire(const uint8_t __generic *buf, uint8_t len, uint8_t init) __reentrant;
+
+/*
+ * PN9 Whitening Sequence
+ */
+extern __reentrantb uint16_t pn9_advance(uint16_t pn9) __reentrant;
+extern const uint8_t __code pn9_table[512];
+extern __reentrantb uint16_t pn9_advance_bit(uint16_t pn9) __reentrant;
+extern __reentrantb uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits) __reentrant;
+extern __reentrantb uint16_t pn9_advance_byte(uint16_t pn9) __reentrant;
+extern __reentrantb uint16_t pn9_buffer(uint8_t __generic *buf, uint16_t buflen, uint16_t pn9, uint8_t xor) __reentrant;
+
+/*
+ * PN15 Whitening Sequence
+ */
+extern __reentrantb uint16_t pn15_advance(uint16_t pn15) __reentrant;
+extern __reentrantb uint8_t pn15_output(uint16_t pn15) __reentrant;
+extern const uint16_t __code pn15_adv_table[256];
+extern const uint8_t __code pn15_out_table[256];
+
+#endif /* LIBMFCRC_H */
diff --git a/libs/libmf/source/libmfdbglink.h b/libs/libmf/source/libmfdbglink.h
new file mode 100644
index 00000000..47a0a0f4
--- /dev/null
+++ b/libs/libmf/source/libmfdbglink.h
@@ -0,0 +1,140 @@
+#ifndef LIBMFDBGLINK_H
+#define LIBMFDBGLINK_H
+
+#include "libmftypes.h"
+
+/*
+ * DebugLink
+ */
+#if defined SDCC
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+static void dbglink_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _dbglink_rxbuffer \
+_dbglink_rxbuffer: \
+ .ds (sz) \
+ \
+ .area HOME (CODE) \
+ .area DBGLINK0 (CODE) \
+ .area DBGLINK1 (CODE) \
+ .area DBGLINK2 (CODE) \
+ .area DBGLINK3 (CODE) \
+ .area DBGLINK4 (CODE) \
+ .area DBGLINK5 (CODE) \
+ \
+ .area DBGLINK2 (CODE) \
+ .db 256-(sz) \
+ .db 257-(sz) \
+ \
+ .area DBGLINK5 (CODE) \
+ .db (sz) \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+static void dbglink_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _dbglink_txbuffer \
+_dbglink_txbuffer: \
+ .ds (sz) \
+ \
+ .area HOME (CODE) \
+ .area DBGLINK0 (CODE) \
+ .area DBGLINK1 (CODE) \
+ .area DBGLINK2 (CODE) \
+ .area DBGLINK3 (CODE) \
+ .area DBGLINK4 (CODE) \
+ .area DBGLINK5 (CODE) \
+ \
+ .area DBGLINK1 (CODE) \
+ .db 256-(sz) \
+ .db 257-(sz) \
+ \
+ .area DBGLINK4 (CODE) \
+ .db (sz) \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata dbglink_rxbuffer[sz]; \
+const uint8_t __code dbglink_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata dbglink_txbuffer[sz]; \
+const uint8_t __code dbglink_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define DBGLINK_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata dbglink_rxbuffer[sz]; \
+const uint8_t __code dbglink_rxbuffer_size[] = { sz };
+
+#define DBGLINK_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata dbglink_txbuffer[sz]; \
+const uint8_t __code dbglink_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves dbglink_txbufptr,dbglink_txfreelinear,dbglink_rxbufptr,dbglink_rxcountlinear
+#pragma callee_saves dbglink_txfree,dbglink_rxcount,dbglink_wait_txfree,dbglink_wait_rxcount
+#pragma callee_saves dbglink_txbuffersize,dbglink_rxbuffersize,dbglink_rxpeek,dbglink_txpoke,dbglink_txpokehex
+#pragma callee_saves dbglink_init,dbglink_poll,dbglink_wait_txfree,dbglink_wait_rxcount,dbglink_rx,dbglink_tx
+extern void dbglink_irq(void) __interrupt(21) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t dbglink_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *dbglink_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *dbglink_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t dbglink_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void dbglink_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void dbglink_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void dbglink_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void dbglink_txadvance(uint8_t idx) __reentrant __naked;
+
+extern __reentrantb void dbglink_init(void) __reentrant;
+extern __reentrantb void dbglink_wait_txdone(void) __reentrant;
+extern __reentrantb void dbglink_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void dbglink_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t dbglink_rx(void) __reentrant;
+extern __reentrantb void dbglink_tx(uint8_t v) __reentrant;
+extern __reentrantb void dbglink_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t dbglink_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t dbglink_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t dbglink_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t dbglink_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t dbglink_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t dbglink_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void dbglink_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void dbglink_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void dbglink_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void dbglink_writeu32(uint32_t val, uint8_t nrdig);
+
+#endif /* LIBMFDBGLINK_H */
diff --git a/libs/libmf/source/libmfflash.h b/libs/libmf/source/libmfflash.h
new file mode 100644
index 00000000..1a3a1e44
--- /dev/null
+++ b/libs/libmf/source/libmfflash.h
@@ -0,0 +1,26 @@
+#ifndef LIBMFFLASH_H
+#define LIBMFFLASH_H
+
+#include "libmftypes.h"
+
+/*
+ * FLASH
+ */
+extern void flash_unlock(void);
+extern void flash_lock(void);
+extern int8_t flash_wait(uint16_t timeout);
+extern int8_t flash_pageerase(uint16_t pgaddr);
+extern int8_t flash_write(uint16_t waddr, uint16_t wdata);
+extern uint16_t flash_read(uint16_t raddr);
+
+extern uint8_t flash_apply_calibration(void);
+typedef uint8_t flash_deviceid_t[6];
+#if defined(SDCC)
+static __xdata flash_deviceid_t __at(0xfc06) flash_deviceid;
+#elif defined __CX51__ || defined __C51__
+static flash_deviceid_t xdata flash_deviceid _at_ 0xfc06;
+#elif defined __ICC8051__
+static __xdata __no_init flash_deviceid_t flash_deviceid @ 0xfc06;
+#endif
+
+#endif /* LIBMFFLASH_H */
diff --git a/libs/libmf/source/libmflcd.h b/libs/libmf/source/libmflcd.h
new file mode 100644
index 00000000..30ed43ad
--- /dev/null
+++ b/libs/libmf/source/libmflcd.h
@@ -0,0 +1,36 @@
+#ifndef LIBMFLCD_H
+#define LIBMFLCD_H
+
+#include "libmftypes.h"
+
+/*
+ * LC Display
+ */
+#if defined SDCC
+#pragma callee_saves lcd_waitlong,lcd_waitshort,lcd_write,lcd_writecmd,lcd_writedata,lcd_portoff,lcd_portinit,lcd_init,lcd_setpos
+#endif
+
+extern void lcd_waitlong(void);
+extern void lcd_waitshort(void);
+extern void lcd_write(uint8_t v);
+extern void lcd_writecmd(uint8_t cmd);
+extern void lcd_writedata(uint8_t d);
+extern void lcd_portoff(void);
+extern void lcd_portinit(void);
+extern void lcd_init(void);
+extern void lcd_setpos(uint8_t v);
+extern void lcd_writestr(const char __generic *ch);
+extern void lcd_cleardisplay(void);
+extern void lcd_clear(uint8_t pos, uint8_t len);
+extern __reentrantb uint8_t lcd_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern uint8_t lcd_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern __reentrantb uint8_t lcd_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern uint8_t lcd_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+
+/* legacy */
+extern void lcd_writehexu16(uint16_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writehexu32(uint32_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writeu16(uint16_t val, uint8_t nrdig, uint8_t pos);
+extern void lcd_writeu32(uint32_t val, uint8_t nrdig, uint8_t pos);
+
+#endif /* LIBMFLCD_H */
diff --git a/libs/libmf/source/libmfosc.h b/libs/libmf/source/libmfosc.h
new file mode 100644
index 00000000..3b430a0a
--- /dev/null
+++ b/libs/libmf/source/libmfosc.h
@@ -0,0 +1,154 @@
+#ifndef LIBMFOSC_H
+#define LIBMFOSC_H
+
+#include "libmftypes.h"
+
+extern __reentrantb void turn_off_xosc(void) __reentrant;
+extern __reentrantb void turn_off_lpxosc(void) __reentrant;
+
+#if defined SDCC
+#pragma callee_saves setup_xosc,setup_lpxosc
+#endif
+extern __reentrantb void setup_xosc(void) __reentrant;
+extern __reentrantb void setup_lpxosc(void) __reentrant;
+
+extern __reentrantb uint8_t setup_osc_calibration(uint32_t reffreq, uint8_t refosc) __reentrant;
+
+/*
+ * Clock Sources
+ */
+#define CLKSRC_FRCOSC 0
+#define CLKSRC_LPOSC 1
+#define CLKSRC_XOSC 2
+#define CLKSRC_LPXOSC 3
+#define CLKSRC_RSYSCLK 4
+#define CLKSRC_TCLK 5
+#define CLKSRC_SYSCLK 6
+#define CLKSRC_OFF 7
+
+#if defined(__ICC8051__)
+#define __osc_set_frcoscref(x) do { FRCOSCREF0 = (x); FRCOSCREF1 = (x) >> 8; } while(0)
+#define __osc_set_lposcref(x) do { LPOSCREF0 = (x); LPOSCREF1 = (x) >> 8; } while(0)
+#define __osc_set_filt() do { FRCOSCKFILT0 = 0x00; FRCOSCKFILT1 = 0x40; LPOSCKFILT0 = 0x00; LPOSCKFILT1 = 0x40; } while (0)
+#else
+#define __osc_set_frcoscref(x) do { FRCOSCREF = (x); } while(0)
+#define __osc_set_lposcref(x) do { LPOSCREF = (x); } while(0)
+#define __osc_set_filt() do { FRCOSCKFILT = 0x4000; LPOSCKFILT = 0x4000; } while (0)
+#endif
+
+#define setup_osc_calibration_const(reffreq,refosc) \
+do { \
+ uint8_t ret = 0; \
+ uint8_t lposccfg; \
+ uint8_t frcosccfg; \
+ if ((reffreq) >= 32768000UL) { \
+ frcosccfg = 0; \
+ ret |= 1; \
+ } else if ((reffreq) >= 16384000UL) { \
+ frcosccfg = 0x78 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 7)); \
+ } else if ((reffreq) >= 8192000UL) { \
+ frcosccfg = 0x70 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 6)); \
+ } else if ((reffreq) >= 4096000UL) { \
+ frcosccfg = 0x68 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 5)); \
+ } else if ((reffreq) >= 2048000UL) { \
+ frcosccfg = 0x60 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 4)); \
+ } else if ((reffreq) >= 1024000UL) { \
+ frcosccfg = 0x58 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 3)); \
+ } else if ((reffreq) >= 512000UL) { \
+ frcosccfg = 0x50 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 2)); \
+ } else if ((reffreq) >= 256000UL) { \
+ frcosccfg = 0x48 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / ((reffreq) >> 1)); \
+ } else if ((reffreq) >= 128000UL) { \
+ frcosccfg = 0x40 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 8) / (reffreq)); \
+ } else if ((reffreq) >= 64000UL) { \
+ frcosccfg = 0x38 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 7) / (reffreq)); \
+ } else if ((reffreq) >= 32000UL) { \
+ frcosccfg = 0x30 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 6) / (reffreq)); \
+ } else if ((reffreq) >= 16000UL) { \
+ frcosccfg = 0x28 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 5) / (reffreq)); \
+ } else if ((reffreq) >= 8000UL) { \
+ frcosccfg = 0x20 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 4) / (reffreq)); \
+ } else if ((reffreq) >= 4000UL) { \
+ frcosccfg = 0x18 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 3) / (reffreq)); \
+ } else if ((reffreq) >= 2000UL) { \
+ frcosccfg = 0x10 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 2) / (reffreq)); \
+ } else if ((reffreq) >= 1000UL) { \
+ frcosccfg = 0x08 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 1) / (reffreq)); \
+ } else if ((reffreq) >= 500UL) { \
+ frcosccfg = 0x00 | ((refosc) & 0x07); \
+ __osc_set_frcoscref((10000000UL << 0) / (reffreq)); \
+ } else { \
+ frcosccfg = 0; \
+ ret |= 1; \
+ } \
+ if ((reffreq) >= 2013265920UL || (reffreq) < 7864320UL) { \
+ lposccfg = 0x08 | CLKSRC_FRCOSC; \
+ __osc_set_lposcref(31250); \
+ } else if ((reffreq) >= 1006632960UL) { \
+ lposccfg = 0x38 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 40960UL); \
+ } else if ((reffreq) >= 503316480UL) { \
+ lposccfg = 0x30 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 20480UL); \
+ } else if ((reffreq) >= 251658240UL) { \
+ lposccfg = 0x28 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 10240UL); \
+ } else if ((reffreq) >= 125829120UL) { \
+ lposccfg = 0x20 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 5120UL); \
+ } else if ((reffreq) >= 62914560UL) { \
+ lposccfg = 0x18 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 2560UL); \
+ } else if ((reffreq) >= 31457280UL) { \
+ lposccfg = 0x10 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 1280UL); \
+ } else if ((reffreq) >= 15728640UL) { \
+ lposccfg = 0x08 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 640UL); \
+ } else { \
+ lposccfg = 0x00 | ((refosc) & 0x07); \
+ __osc_set_lposcref((reffreq) / 320UL); \
+ } \
+ if (!ret) { \
+ switch (refosc) { \
+ case CLKSRC_XOSC: \
+ setup_xosc(); \
+ OSCFORCERUN |= 0x04; \
+ break; \
+ \
+ case CLKSRC_LPXOSC: \
+ setup_lpxosc(); \
+ OSCFORCERUN |= 0x08; \
+ break; \
+ \
+ case CLKSRC_RSYSCLK: \
+ break; \
+ \
+ default: \
+ ret = 2; \
+ break; \
+ } \
+ if (!ret) { \
+ __osc_set_filt(); \
+ FRCOSCCONFIG = frcosccfg; \
+ LPOSCCONFIG = lposccfg; \
+ } \
+ } \
+} while (0)
+
+#endif /* LIBMFOSC_H */
diff --git a/libs/libmf/source/libmfradio.h b/libs/libmf/source/libmfradio.h
new file mode 100644
index 00000000..e41b9e6c
--- /dev/null
+++ b/libs/libmf/source/libmfradio.h
@@ -0,0 +1,62 @@
+#ifndef LIBMFRADIO_H
+#define LIBMFRADIO_H
+
+#include "libmftypes.h"
+
+#if defined(SDCC)
+#pragma callee_saves radio_read16,radio_read24,radio_read32,radio_write16,radio_write24,radio_write32
+#endif
+extern __reentrantb uint16_t radio_read16(uint16_t addr) __reentrant;
+extern __reentrantb uint32_t radio_read24(uint16_t addr) __reentrant;
+extern __reentrantb uint32_t radio_read32(uint16_t addr) __reentrant;
+extern __reentrantb void radio_write16(uint16_t addr, uint16_t d) __reentrant;
+extern __reentrantb void radio_write24(uint16_t addr, uint32_t d) __reentrant;
+extern __reentrantb void radio_write32(uint16_t addr, uint32_t d) __reentrant;
+
+/*
+ * AX5031
+ */
+extern __reentrantb void ax5031_comminit(void) __reentrant;
+extern __reentrantb void ax5031_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5031_reset(void) __reentrant;
+extern __reentrantb void ax5031_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5031_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5031_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5031_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5042
+ */
+extern __reentrantb void ax5042_comminit(void) __reentrant;
+extern __reentrantb void ax5042_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5042_reset(void) __reentrant;
+extern __reentrantb void ax5042_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5042_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5042_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5042_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5043
+ */
+extern __reentrantb void ax5043_comminit(void) __reentrant;
+extern __reentrantb void ax5043_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5043_reset(void) __reentrant;
+extern __reentrantb void ax5043_enter_deepsleep(void) __reentrant;
+extern __reentrantb uint8_t ax5043_wakeup_deepsleep(void) __reentrant;
+extern __reentrantb void ax5043_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5043_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5043_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5043_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+/*
+ * AX5051
+ */
+extern __reentrantb void ax5051_comminit(void) __reentrant;
+extern __reentrantb void ax5051_commsleepexit(void) __reentrant;
+extern __reentrantb uint8_t ax5051_reset(void) __reentrant;
+extern __reentrantb void ax5051_rclk_enable(uint8_t div) __reentrant;
+extern __reentrantb void ax5051_rclk_disable(void) __reentrant;
+extern __reentrantb void ax5051_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant;
+extern __reentrantb void ax5051_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant;
+
+#endif /* LIBMFRADIO_H */
diff --git a/libs/libmf/source/libmftypes.h b/libs/libmf/source/libmftypes.h
new file mode 100644
index 00000000..c9df7225
--- /dev/null
+++ b/libs/libmf/source/libmftypes.h
@@ -0,0 +1,235 @@
+#ifndef LIBMFTYPES_H
+#define LIBMFTYPES_H
+
+#define LIBMFVERSION 20160321L
+
+/*
+ * Address Space Tags
+ */
+
+#if defined SDCC
+#define __autodata __data
+#define __auto __data
+#define __generic
+#define __reentrantb
+#define __interruptb(x)
+#endif
+
+#if defined __CX51__ || defined __C51__
+#include
+
+#define __autodata
+#define __auto data
+#define __code code
+#define __data data
+#define __xdata xdata
+#define __pdata pdata
+#define __generic
+#define __reentrantb
+#define __reentrant small reentrant
+#define __naked
+#define __interruptb(x)
+#define __interrupt(x) interrupt x
+#endif
+
+#if defined __ICC8051__
+#include
+#pragma language=extended
+
+#define __autodata
+#if !defined(__CALLING_CONVENTION__) || __CALLING_CONVENTION__ < 3
+#define __auto __data
+#elif __CALLING_CONVENTION__ == 3
+#define __auto __pdata
+#else
+#define __auto __xdata
+#endif
+#if !defined(__CALLING_CONVENTION__) || __CALLING_CONVENTION__ < 2
+#define __reentrantb __idata_reentrant
+#else
+#define __reentrantb
+#endif
+#define __reentrant
+#define __naked
+#define __interrupt_0 _Pragma("vector=0x03")
+#define __interrupt_1 _Pragma("vector=0x0B")
+#define __interrupt_2 _Pragma("vector=0x13")
+#define __interrupt_3 _Pragma("vector=0x1B")
+#define __interrupt_4 _Pragma("vector=0x23")
+#define __interrupt_5 _Pragma("vector=0x2B")
+#define __interrupt_6 _Pragma("vector=0x33")
+#define __interrupt_7 _Pragma("vector=0x3B")
+#define __interrupt_8 _Pragma("vector=0x43")
+#define __interrupt_9 _Pragma("vector=0x4B")
+#define __interrupt_10 _Pragma("vector=0x53")
+#define __interrupt_11 _Pragma("vector=0x5B")
+#define __interrupt_12 _Pragma("vector=0x63")
+#define __interrupt_13 _Pragma("vector=0x6B")
+#define __interrupt_14 _Pragma("vector=0x73")
+#define __interrupt_15 _Pragma("vector=0x7B")
+#define __interrupt_16 _Pragma("vector=0x83")
+#define __interrupt_17 _Pragma("vector=0x8B")
+#define __interrupt_18 _Pragma("vector=0x93")
+#define __interrupt_19 _Pragma("vector=0x9B")
+#define __interrupt_20 _Pragma("vector=0xA3")
+#define __interrupt_21 _Pragma("vector=0xAB")
+#define __interrupt_INT_EXTERNAL0 __interrupt_0
+#define __interrupt_INT_WAKEUPTIMER __interrupt_1
+#define __interrupt_INT_EXTERNAL1 __interrupt_2
+#define __interrupt_INT_GPIO __interrupt_3
+#define __interrupt_INT_RADIO __interrupt_4
+#define __interrupt_INT_CLOCKMGMT __interrupt_5
+#define __interrupt_INT_POWERMGMT __interrupt_6
+#define __interrupt_INT_TIMER0 __interrupt_7
+#define __interrupt_INT_TIMER1 __interrupt_8
+#define __interrupt_INT_TIMER2 __interrupt_9
+#define __interrupt_INT_SPI0 __interrupt_10
+#define __interrupt_INT_UART0 __interrupt_11
+#define __interrupt_INT_UART1 __interrupt_12
+#define __interrupt_INT_GPADC __interrupt_13
+#define __interrupt_INT_DMA __interrupt_14
+#define __interrupt_INT_OUTPUTCOMP0 __interrupt_15
+#define __interrupt_INT_OUTPUTCOMP1 __interrupt_16
+#define __interrupt_INT_INPUTCAPT0 __interrupt_17
+#define __interrupt_INT_INPUTCAPT1 __interrupt_18
+#define __interrupt_INT_DEBUGLINK __interrupt_21
+#define __interruptb(x) __interrupt_##x __interrupt
+#define __interrupt(x)
+#endif
+
+/*
+ * C99 size types
+ */
+
+typedef signed char int8_t; /**< \brief C99 signed 8bit type */
+typedef signed int int16_t; /**< \brief C99 signed 16bit type */
+typedef signed long int32_t; /**< \brief C99 signed 32bit type */
+typedef unsigned char uint8_t; /**< \brief C99 unsigned 8bit type */
+typedef unsigned int uint16_t; /**< \brief C99 unsigned 16bit type */
+typedef unsigned long uint32_t; /**< \brief C99 unsigned 32bit type */
+
+/*
+ * Delay
+ */
+extern __reentrantb void delay(uint16_t us) __reentrant __naked;
+
+/*
+ * Random Number Generator
+ */
+extern uint16_t __data random_seed;
+extern uint16_t random(void);
+
+/*
+ * Hamming Weight - also sometimes called population count
+ */
+#if defined SDCC
+#pragma callee_saves hweight8,hweight16,hweight32
+#pragma callee_saves signextend12,signextend16,signextend20,signextend24
+extern __reentrantb int32_t signextend12(int16_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend16(int16_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend20(int32_t x) __reentrant __naked;
+extern __reentrantb int32_t signextend24(int32_t x) __reentrant __naked;
+#else
+extern __reentrantb int32_t signextend12(int16_t x) __reentrant;
+extern __reentrantb int32_t signextend16(int16_t x) __reentrant;
+extern __reentrantb int32_t signextend20(int32_t x) __reentrant;
+extern __reentrantb int32_t signextend24(int32_t x) __reentrant;
+#endif
+extern __reentrantb uint8_t hweight8(uint8_t x) __reentrant;
+extern __reentrantb uint8_t hweight16(uint16_t x) __reentrant;
+extern __reentrantb uint8_t hweight32(uint32_t x) __reentrant;
+#define parity8(x) (hweight8(x) & 1)
+#define parity16(x) (hweight16(x) & 1)
+#define parity32(x) (hweight32(x) & 1)
+#if defined SDCC
+#pragma callee_saves signedlimit16,checksignedlimit16,signedlimit32,checksignedlimit32
+#pragma callee_saves gray_encode8,gray_decode8
+extern __reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant __naked;
+extern __reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant __naked;
+extern __reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant __naked;
+extern __reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant __naked;
+extern __reentrantb uint8_t gray_encode8(uint8_t x) __reentrant __naked;
+extern __reentrantb uint8_t gray_decode8(uint8_t x) __reentrant __naked;
+#else
+extern __reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant;
+extern __reentrantb uint8_t checksignedlimit16(int16_t x, int16_t lim) __reentrant;
+extern __reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant;
+extern __reentrantb uint8_t checksignedlimit32(int32_t x, int32_t lim) __reentrant;
+extern __reentrantb uint8_t gray_encode8(uint8_t x) __reentrant;
+extern __reentrantb uint8_t gray_decode8(uint8_t x) __reentrant;
+#endif
+
+/*
+ * Reverse Bits
+ */
+extern __reentrantb uint8_t rev8(uint8_t x) __reentrant;
+
+/*
+ * fast memset and memcpy
+ */
+
+#if defined __ICC8051__
+__idata_reentrant void fmemset(void __generic *p, char c, uint16_t n);
+__idata_reentrant void fmemcpy(void __generic *d, const void __generic *s, uint16_t n);
+#else
+__reentrantb void fmemset(void __generic *p, char c, uint16_t n) __reentrant;
+__reentrantb void fmemcpy(void __generic *d, const void __generic *s, uint16_t n) __reentrant;
+#endif
+
+/*
+ * Power Management
+ */
+
+#if defined SDCC
+#define nop() do { __asm nop __endasm; } while (0)
+#elif defined __CX51__ || defined __C51__
+#define nop() do { _nop_(); } while (0)
+#elif defined __ICC8051__
+#define nop() do { __no_operation(); } while (0)
+#endif
+
+#if defined SDCC
+#pragma callee_saves wtimer_standby,enter_standby,enter_sleep,enter_deepsleep
+#endif
+extern __reentrantb void wtimer_standby(void) __reentrant;
+extern __reentrantb void enter_standby(void) __reentrant;
+extern __reentrantb void enter_sleep(void) __reentrant;
+#if defined(SDCC) || defined(__ICC8051__)
+extern __reentrantb void enter_sleep_cont(void) __reentrant;
+#endif
+extern __reentrantb void enter_deepsleep(void) __reentrant;
+extern __reentrantb void reset_cpu(void) __reentrant;
+extern __reentrantb void turn_off_xosc(void) __reentrant;
+extern __reentrantb void turn_off_lpxosc(void) __reentrant;
+
+/*
+ * Clock Sources
+ */
+#define CLKSRC_FRCOSC 0
+#define CLKSRC_LPOSC 1
+#define CLKSRC_XOSC 2
+#define CLKSRC_LPXOSC 3
+#define CLKSRC_RSYSCLK 4
+#define CLKSRC_TCLK 5
+#define CLKSRC_SYSCLK 6
+#define CLKSRC_OFF 7
+
+/*
+ * wrnum Flags
+ */
+#define WRNUM_SIGNED 0x01
+#define WRNUM_PLUS 0x02
+#define WRNUM_ZEROPLUS 0x04
+#define WRNUM_PADZERO 0x08
+#define WRNUM_TSDSEP 0x10
+#define WRNUM_LCHEX 0x20
+
+/*
+ * IAR Stacks
+ */
+#if defined __ICC8051__
+extern __reentrantb void __pdata *getpsp(void) __reentrant;
+extern __reentrantb void __xdata *getxsp(void) __reentrant;
+#endif
+
+#endif /* LIBMFTYPES_H */
diff --git a/libs/libmf/source/libmfuart.h b/libs/libmf/source/libmfuart.h
new file mode 100644
index 00000000..686a19ad
--- /dev/null
+++ b/libs/libmf/source/libmfuart.h
@@ -0,0 +1,13 @@
+#ifndef LIBMFUART_H
+#define LIBMFUART_H
+
+#include "libmftypes.h"
+
+/*
+ * UART
+ */
+extern __reentrantb void uart_timer0_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+extern __reentrantb void uart_timer1_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+extern __reentrantb void uart_timer2_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant;
+
+#endif /* LIBMFUART_H */
diff --git a/libs/libmf/source/libmfuart0.h b/libs/libmf/source/libmfuart0.h
new file mode 100644
index 00000000..2012d656
--- /dev/null
+++ b/libs/libmf/source/libmfuart0.h
@@ -0,0 +1,142 @@
+#ifndef LIBMFUART0_H
+#define LIBMFUART0_H
+
+#include "libmftypes.h"
+
+/*
+ * UART 0
+ */
+#if defined SDCC
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+static void uart0_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart0_rxbuffer \
+_uart0_rxbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART0S0 (CODE) \
+ .area UART0S1 (CODE) \
+ .area UART0S2 (CODE) \
+ .area UART0S3 (CODE) \
+ .area UART0S4 (CODE) \
+ .area UART0S5 (CODE) \
+ \
+ .area UART0S2 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART0S5 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+static void uart0_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart0_txbuffer \
+_uart0_txbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART0S0 (CODE) \
+ .area UART0S1 (CODE) \
+ .area UART0S2 (CODE) \
+ .area UART0S3 (CODE) \
+ .area UART0S4 (CODE) \
+ .area UART0S5 (CODE) \
+ \
+ .area UART0S1 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART0S4 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart0_rxbuffer[sz]; \
+const uint8_t __code uart0_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart0_txbuffer[sz]; \
+const uint8_t __code uart0_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define UART0_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart0_rxbuffer[sz]; \
+const uint8_t __code uart0_rxbuffer_size[] = { sz };
+
+#define UART0_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart0_txbuffer[sz]; \
+const uint8_t __code uart0_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves uart0_txbufptr,uart0_txfreelinear,uart0_rxbufptr,uart0_rxcountlinear
+#pragma callee_saves uart0_txfree,uart0_rxcount,uart0_wait_txfree,uart0_wait_rxcount
+#pragma callee_saves uart0_txbuffersize,uart0_rxbuffersize,uart0_rxpeek,uart0_txpoke,uart0_txpokehex
+#pragma callee_saves uart0_init,uart0_poll,uart0_wait_txfree,uart0_wait_rxcount,uart0_rx,uart0_tx
+extern __reentrantb void uart0_irq(void) __interrupt(11) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t uart0_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *uart0_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *uart0_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart0_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart0_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart0_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart0_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart0_txadvance(uint8_t idx) __reentrant __naked;
+
+extern void uart0_init(uint8_t timernr, uint8_t wl, uint8_t stop);
+extern void uart0_stop(void);
+extern __reentrantb void uart0_wait_txdone(void) __reentrant;
+extern __reentrantb void uart0_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void uart0_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t uart0_rx(void) __reentrant;
+extern __reentrantb void uart0_tx(uint8_t v) __reentrant;
+extern __reentrantb void uart0_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t uart0_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart0_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t uart0_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart0_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t uart0_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t uart0_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void uart0_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart0_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void uart0_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart0_writeu32(uint32_t val, uint8_t nrdig);
+
+
+#endif /* LIBMFUART0_H */
diff --git a/libs/libmf/source/libmfuart1.h b/libs/libmf/source/libmfuart1.h
new file mode 100644
index 00000000..4a1a4d13
--- /dev/null
+++ b/libs/libmf/source/libmfuart1.h
@@ -0,0 +1,142 @@
+#ifndef LIBMFUART1_H
+#define LIBMFUART1_H
+
+#include "libmftypes.h"
+
+/*
+ * UART 1
+ */
+#if defined SDCC
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+static void uart1_define_rxbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart1_rxbuffer \
+_uart1_rxbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART1S0 (CODE) \
+ .area UART1S1 (CODE) \
+ .area UART1S2 (CODE) \
+ .area UART1S3 (CODE) \
+ .area UART1S4 (CODE) \
+ .area UART1S5 (CODE) \
+ \
+ .area UART1S2 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART1S5 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+static void uart1_define_txbuffer(void) __naked \
+{ \
+ __asm \
+ .area XSEG (XDATA) \
+ .globl _uart1_txbuffer \
+_uart1_txbuffer: \
+ .ds sz \
+ \
+ .area HOME (CODE) \
+ .area UART1S0 (CODE) \
+ .area UART1S1 (CODE) \
+ .area UART1S2 (CODE) \
+ .area UART1S3 (CODE) \
+ .area UART1S4 (CODE) \
+ .area UART1S5 (CODE) \
+ \
+ .area UART1S1 (CODE) \
+ .db 256-sz \
+ .db 257-sz \
+ \
+ .area UART1S4 (CODE) \
+ .db sz \
+ \
+ .area CSEG (CODE) \
+ __endasm; \
+}
+
+#elif defined __CX51__ || defined __C51__
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart1_rxbuffer[sz]; \
+const uint8_t __code uart1_rxbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart1_txbuffer[sz]; \
+const uint8_t __code uart1_txbuffer_size[] = { sz, 256-(sz), 257-(sz) };
+
+#else
+
+#define UART1_DEFINE_RXBUFFER(sz) \
+uint8_t __xdata uart1_rxbuffer[sz]; \
+const uint8_t __code uart1_rxbuffer_size[] = { sz };
+
+#define UART1_DEFINE_TXBUFFER(sz) \
+uint8_t __xdata uart1_txbuffer[sz]; \
+const uint8_t __code uart1_txbuffer_size[] = { sz };
+
+#endif
+
+#if defined SDCC
+#pragma callee_saves uart1_txbufptr,uart1_txfreelinear,uart1_rxbufptr,uart1_rxcountlinear
+#pragma callee_saves uart1_txfree,uart1_rxcount,uart1_wait_txfree,uart1_wait_rxcount
+#pragma callee_saves uart1_txbuffersize,uart1_rxbuffersize,uart1_rxpeek,uart1_txpoke,uart1_txpokehex
+#pragma callee_saves uart1_init,uart1_poll,uart1_wait_txfree,uart1_wait_rxcount,uart1_rx,uart1_tx
+extern __reentrantb void uart1_irq(void) __interrupt(12) __naked;
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+extern __reentrantb uint8_t uart1_poll(void) __reentrant __naked;
+extern __reentrantb uint8_t __xdata *uart1_txbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txfreelinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txidle(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txfree(void) __reentrant __naked;
+extern __reentrantb const uint8_t __xdata *uart1_rxbufptr(uint8_t idx) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxcountlinear(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxcount(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_txbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxbuffersize(void) __reentrant __naked;
+extern __reentrantb uint8_t uart1_rxpeek(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart1_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart1_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked;
+extern __reentrantb void uart1_rxadvance(uint8_t idx) __reentrant __naked;
+extern __reentrantb void uart1_txadvance(uint8_t idx) __reentrant __naked;
+
+extern void uart1_init(uint8_t timernr, uint8_t wl, uint8_t stop);
+extern void uart1_stop(void);
+extern __reentrantb void uart1_wait_txdone(void) __reentrant;
+extern __reentrantb void uart1_wait_txfree(uint8_t v) __reentrant;
+extern __reentrantb void uart1_wait_rxcount(uint8_t v) __reentrant;
+extern __reentrantb uint8_t uart1_rx(void) __reentrant;
+extern __reentrantb void uart1_tx(uint8_t v) __reentrant;
+extern __reentrantb void uart1_writestr(const char __generic *ch) __reentrant;
+extern __reentrantb uint8_t uart1_writenum16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart1_writehex16(uint16_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#if defined(SDCC)
+extern __reentrantb uint8_t uart1_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+extern __reentrantb uint8_t uart1_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags) __reentrant;
+#else
+extern uint8_t uart1_writenum32(uint32_t val, uint8_t nrdig, uint8_t flags);
+extern uint8_t uart1_writehex32(uint32_t val, uint8_t nrdig, uint8_t flags);
+#endif
+
+/* legacy */
+extern __reentrantb void uart1_writehexu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart1_writehexu32(uint32_t val, uint8_t nrdig);
+extern __reentrantb void uart1_writeu16(uint16_t val, uint8_t nrdig) __reentrant;
+extern void uart1_writeu32(uint32_t val, uint8_t nrdig);
+
+
+#endif /* LIBMFUART1_H */
diff --git a/libs/libmf/source/libmfwtimer.h b/libs/libmf/source/libmfwtimer.h
new file mode 100644
index 00000000..e35194bc
--- /dev/null
+++ b/libs/libmf/source/libmfwtimer.h
@@ -0,0 +1,87 @@
+#ifndef LIBMFWTIMER_H
+#define LIBMFWTIMER_H
+
+#include "libmftypes.h"
+
+struct wtimer_callback;
+struct wtimer_desc;
+
+#if defined(__ICC8051__)
+typedef void (*wtimer_callback_handler_t)(struct wtimer_callback __xdata *desc);
+typedef void (*wtimer_desc_handler_t)(struct wtimer_desc __xdata *desc);
+#else
+typedef __reentrantb void (*wtimer_callback_handler_t)(struct wtimer_callback __xdata *desc) __reentrant;
+typedef __reentrantb void (*wtimer_desc_handler_t)(struct wtimer_desc __xdata *desc) __reentrant;
+#endif
+
+struct wtimer_callback {
+ // do not change the order
+ // must be compatible with wtimer_desc
+ struct wtimer_callback __xdata *next;
+ wtimer_callback_handler_t handler;
+};
+
+struct wtimer_desc {
+ // do not change the order
+ struct wtimer_desc __xdata *next;
+ wtimer_desc_handler_t handler;
+ uint32_t time;
+};
+
+#define WTFLAG_CANSLEEP 0x01
+#define WTFLAG_CANSTANDBY 0x02
+#define WTFLAG_CANSLEEPCONT 0x04
+
+#define WTIDLE_WORK 0x01
+#define WTIDLE_SLEEP 0x02
+
+extern __reentrantb void wtimer0_setconfig(uint8_t cfg) __reentrant;
+extern __reentrantb void wtimer1_setconfig(uint8_t cfg) __reentrant;
+
+#define wtimer0_setclksrc(clksrc, prescaler) \
+do { \
+ uint8_t c = clksrc, p = prescaler; \
+ wtimer0_setconfig((c & 0x07) | ((p & 0x07) << 3)); \
+} while (0)
+
+#define wtimer1_setclksrc(clksrc, prescaler) \
+do { \
+ uint8_t c = clksrc, p = prescaler; \
+ wtimer1_setconfig((c & 0x07) | ((p & 0x07) << 3)); \
+} while (0)
+
+extern __reentrantb void wtimer_init(void) __reentrant;
+extern __reentrantb void wtimer_init_deepsleep(void) __reentrant;
+extern __reentrantb uint8_t wtimer_idle(uint8_t flags) __reentrant;
+#if defined(__ICC8051__)
+extern uint8_t wtimer_runcallbacks(void);
+#else
+// note: wtimer_runcallbacks is only reentrant if the handlers
+// it might call are reentrant too
+extern __reentrantb uint8_t wtimer_runcallbacks(void) __reentrant;
+#endif
+
+extern __reentrantb uint32_t wtimer0_curtime(void) __reentrant;
+extern __reentrantb uint32_t wtimer1_curtime(void) __reentrant;
+extern __reentrantb void wtimer0_addabsolute(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer1_addabsolute(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer0_addrelative(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer1_addrelative(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer_remove(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer0_remove(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer1_remove(struct wtimer_desc __xdata *desc) __reentrant;
+
+extern __reentrantb void wtimer_add_callback(struct wtimer_callback __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer_remove_callback(struct wtimer_callback __xdata *desc) __reentrant;
+
+extern __reentrantb uint8_t wtimer_cansleep(void) __reentrant;
+
+#if defined SDCC
+extern void wtimer_irq(void) __interrupt(1);
+#elif defined __CX51__ || defined __C51__
+#elif defined __ICC8051__
+#else
+#error "Compiler unsupported"
+#endif
+
+#endif /* LIBMFWTIMER_H */
diff --git a/libs/libmf/source/offlpxosc.c b/libs/libmf/source/offlpxosc.c
new file mode 100644
index 00000000..0744ac06
--- /dev/null
+++ b/libs/libmf/source/offlpxosc.c
@@ -0,0 +1,34 @@
+#include "ax8052.h"
+#include "libmfosc.h"
+
+/**
+ * \brief turn off LPXOSC if accidentally enabled
+ *
+ */
+__reentrantb void turn_off_lpxosc(void) __reentrant
+{
+ uint8_t iesave, portasave, dirasave, i;
+
+ if (SILICONREV != SILICONREVISION_V1 && (MISCCTRL & 0x01))
+ return;
+ MISCCTRL |= 0x01;
+ iesave = IE & 0x80;
+ EA = 0;
+ portasave = PORTA;
+ dirasave = DIRA;
+ PORTA_4 = 1;
+ PORTA_5 = 0;
+ DIRA |= 0x18;
+ OSCFORCERUN &= (uint8_t)~0x08;
+ i = 6;
+ do {
+ uint8_t j = 0x80;
+ do {
+ nop();
+ } while (--j);
+ PORTA ^= 0x18;
+ } while (--i);
+ DIRA = dirasave;
+ PORTA = portasave;
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/offxosc.c b/libs/libmf/source/offxosc.c
new file mode 100644
index 00000000..3add8104
--- /dev/null
+++ b/libs/libmf/source/offxosc.c
@@ -0,0 +1,33 @@
+#include "ax8052.h"
+#include "libmfosc.h"
+
+/**
+ * \brief turn off XOSC if accidentally enabled
+ *
+ */
+__reentrantb void turn_off_xosc(void) __reentrant
+{
+ uint8_t iesave, portasave, dirasave, xtalreadysave, i;
+
+ if (SILICONREV != SILICONREVISION_V1 && (MISCCTRL & 0x02))
+ return;
+ MISCCTRL |= 0x02;
+ iesave = IE & 0x80;
+ EA = 0;
+ portasave = PORTA;
+ dirasave = DIRA;
+ xtalreadysave = XTALREADY;
+ XTALREADY = 0x00;
+ PORTA_0 = 1;
+ PORTA_1 = 0;
+ DIRA |= 0x03;
+ OSCFORCERUN &= (uint8_t)~0x04;
+ i = 6;
+ do {
+ PORTA ^= 0x03;
+ } while (--i);
+ DIRA = dirasave;
+ PORTA = portasave;
+ XTALREADY = xtalreadysave;
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/pn15adv.c b/libs/libmf/source/pn15adv.c
new file mode 100644
index 00000000..fd0bfa71
--- /dev/null
+++ b/libs/libmf/source/pn15adv.c
@@ -0,0 +1,7 @@
+#include "libmfcrc.h"
+
+__reentrantb uint16_t pn15_advance(uint16_t pn15) __reentrant
+{
+ pn15 &= 0x7FFF;
+ return (pn15 >> 8) ^ pn15_adv_table[pn15 & 0xff];
+}
diff --git a/libs/libmf/source/pn15advtable.c b/libs/libmf/source/pn15advtable.c
new file mode 100644
index 00000000..45cb3c8a
--- /dev/null
+++ b/libs/libmf/source/pn15advtable.c
@@ -0,0 +1,39 @@
+/* automatically generated by genpn9, do not edit! */
+
+#include "libmfcrc.h"
+
+const uint16_t __code pn15_adv_table[256] = {
+ 0x0000, 0x7f81, 0x7f01, 0x0080, 0x7e01, 0x0180, 0x0100, 0x7e81,
+ 0x7c01, 0x0380, 0x0300, 0x7c81, 0x0200, 0x7d81, 0x7d01, 0x0280,
+ 0x7801, 0x0780, 0x0700, 0x7881, 0x0600, 0x7981, 0x7901, 0x0680,
+ 0x0400, 0x7b81, 0x7b01, 0x0480, 0x7a01, 0x0580, 0x0500, 0x7a81,
+ 0x7001, 0x0f80, 0x0f00, 0x7081, 0x0e00, 0x7181, 0x7101, 0x0e80,
+ 0x0c00, 0x7381, 0x7301, 0x0c80, 0x7201, 0x0d80, 0x0d00, 0x7281,
+ 0x0800, 0x7781, 0x7701, 0x0880, 0x7601, 0x0980, 0x0900, 0x7681,
+ 0x7401, 0x0b80, 0x0b00, 0x7481, 0x0a00, 0x7581, 0x7501, 0x0a80,
+ 0x6001, 0x1f80, 0x1f00, 0x6081, 0x1e00, 0x6181, 0x6101, 0x1e80,
+ 0x1c00, 0x6381, 0x6301, 0x1c80, 0x6201, 0x1d80, 0x1d00, 0x6281,
+ 0x1800, 0x6781, 0x6701, 0x1880, 0x6601, 0x1980, 0x1900, 0x6681,
+ 0x6401, 0x1b80, 0x1b00, 0x6481, 0x1a00, 0x6581, 0x6501, 0x1a80,
+ 0x1000, 0x6f81, 0x6f01, 0x1080, 0x6e01, 0x1180, 0x1100, 0x6e81,
+ 0x6c01, 0x1380, 0x1300, 0x6c81, 0x1200, 0x6d81, 0x6d01, 0x1280,
+ 0x6801, 0x1780, 0x1700, 0x6881, 0x1600, 0x6981, 0x6901, 0x1680,
+ 0x1400, 0x6b81, 0x6b01, 0x1480, 0x6a01, 0x1580, 0x1500, 0x6a81,
+ 0x4001, 0x3f80, 0x3f00, 0x4081, 0x3e00, 0x4181, 0x4101, 0x3e80,
+ 0x3c00, 0x4381, 0x4301, 0x3c80, 0x4201, 0x3d80, 0x3d00, 0x4281,
+ 0x3800, 0x4781, 0x4701, 0x3880, 0x4601, 0x3980, 0x3900, 0x4681,
+ 0x4401, 0x3b80, 0x3b00, 0x4481, 0x3a00, 0x4581, 0x4501, 0x3a80,
+ 0x3000, 0x4f81, 0x4f01, 0x3080, 0x4e01, 0x3180, 0x3100, 0x4e81,
+ 0x4c01, 0x3380, 0x3300, 0x4c81, 0x3200, 0x4d81, 0x4d01, 0x3280,
+ 0x4801, 0x3780, 0x3700, 0x4881, 0x3600, 0x4981, 0x4901, 0x3680,
+ 0x3400, 0x4b81, 0x4b01, 0x3480, 0x4a01, 0x3580, 0x3500, 0x4a81,
+ 0x2000, 0x5f81, 0x5f01, 0x2080, 0x5e01, 0x2180, 0x2100, 0x5e81,
+ 0x5c01, 0x2380, 0x2300, 0x5c81, 0x2200, 0x5d81, 0x5d01, 0x2280,
+ 0x5801, 0x2780, 0x2700, 0x5881, 0x2600, 0x5981, 0x5901, 0x2680,
+ 0x2400, 0x5b81, 0x5b01, 0x2480, 0x5a01, 0x2580, 0x2500, 0x5a81,
+ 0x5001, 0x2f80, 0x2f00, 0x5081, 0x2e00, 0x5181, 0x5101, 0x2e80,
+ 0x2c00, 0x5381, 0x5301, 0x2c80, 0x5201, 0x2d80, 0x2d00, 0x5281,
+ 0x2800, 0x5781, 0x5701, 0x2880, 0x5601, 0x2980, 0x2900, 0x5681,
+ 0x5401, 0x2b80, 0x2b00, 0x5481, 0x2a00, 0x5581, 0x5501, 0x2a80
+};
+
diff --git a/libs/libmf/source/pn15out.c b/libs/libmf/source/pn15out.c
new file mode 100644
index 00000000..587ff782
--- /dev/null
+++ b/libs/libmf/source/pn15out.c
@@ -0,0 +1,6 @@
+#include "libmfcrc.h"
+
+__reentrantb uint8_t pn15_output(uint16_t pn15) __reentrant
+{
+ return pn15_out_table[pn15 & 0xff];
+}
diff --git a/libs/libmf/source/pn15outtable.c b/libs/libmf/source/pn15outtable.c
new file mode 100644
index 00000000..36699467
--- /dev/null
+++ b/libs/libmf/source/pn15outtable.c
@@ -0,0 +1,39 @@
+/* automatically generated by genpn9, do not edit! */
+
+#include "libmfcrc.h"
+
+const uint8_t __code pn15_out_table[256] = {
+ 0x00, 0xff, 0xfe, 0x01, 0xfc, 0x03, 0x02, 0xfd,
+ 0xf8, 0x07, 0x06, 0xf9, 0x04, 0xfb, 0xfa, 0x05,
+ 0xf0, 0x0f, 0x0e, 0xf1, 0x0c, 0xf3, 0xf2, 0x0d,
+ 0x08, 0xf7, 0xf6, 0x09, 0xf4, 0x0b, 0x0a, 0xf5,
+ 0xe0, 0x1f, 0x1e, 0xe1, 0x1c, 0xe3, 0xe2, 0x1d,
+ 0x18, 0xe7, 0xe6, 0x19, 0xe4, 0x1b, 0x1a, 0xe5,
+ 0x10, 0xef, 0xee, 0x11, 0xec, 0x13, 0x12, 0xed,
+ 0xe8, 0x17, 0x16, 0xe9, 0x14, 0xeb, 0xea, 0x15,
+ 0xc0, 0x3f, 0x3e, 0xc1, 0x3c, 0xc3, 0xc2, 0x3d,
+ 0x38, 0xc7, 0xc6, 0x39, 0xc4, 0x3b, 0x3a, 0xc5,
+ 0x30, 0xcf, 0xce, 0x31, 0xcc, 0x33, 0x32, 0xcd,
+ 0xc8, 0x37, 0x36, 0xc9, 0x34, 0xcb, 0xca, 0x35,
+ 0x20, 0xdf, 0xde, 0x21, 0xdc, 0x23, 0x22, 0xdd,
+ 0xd8, 0x27, 0x26, 0xd9, 0x24, 0xdb, 0xda, 0x25,
+ 0xd0, 0x2f, 0x2e, 0xd1, 0x2c, 0xd3, 0xd2, 0x2d,
+ 0x28, 0xd7, 0xd6, 0x29, 0xd4, 0x2b, 0x2a, 0xd5,
+ 0x80, 0x7f, 0x7e, 0x81, 0x7c, 0x83, 0x82, 0x7d,
+ 0x78, 0x87, 0x86, 0x79, 0x84, 0x7b, 0x7a, 0x85,
+ 0x70, 0x8f, 0x8e, 0x71, 0x8c, 0x73, 0x72, 0x8d,
+ 0x88, 0x77, 0x76, 0x89, 0x74, 0x8b, 0x8a, 0x75,
+ 0x60, 0x9f, 0x9e, 0x61, 0x9c, 0x63, 0x62, 0x9d,
+ 0x98, 0x67, 0x66, 0x99, 0x64, 0x9b, 0x9a, 0x65,
+ 0x90, 0x6f, 0x6e, 0x91, 0x6c, 0x93, 0x92, 0x6d,
+ 0x68, 0x97, 0x96, 0x69, 0x94, 0x6b, 0x6a, 0x95,
+ 0x40, 0xbf, 0xbe, 0x41, 0xbc, 0x43, 0x42, 0xbd,
+ 0xb8, 0x47, 0x46, 0xb9, 0x44, 0xbb, 0xba, 0x45,
+ 0xb0, 0x4f, 0x4e, 0xb1, 0x4c, 0xb3, 0xb2, 0x4d,
+ 0x48, 0xb7, 0xb6, 0x49, 0xb4, 0x4b, 0x4a, 0xb5,
+ 0xa0, 0x5f, 0x5e, 0xa1, 0x5c, 0xa3, 0xa2, 0x5d,
+ 0x58, 0xa7, 0xa6, 0x59, 0xa4, 0x5b, 0x5a, 0xa5,
+ 0x50, 0xaf, 0xae, 0x51, 0xac, 0x53, 0x52, 0xad,
+ 0xa8, 0x57, 0x56, 0xa9, 0x54, 0xab, 0xaa, 0x55
+};
+
diff --git a/libs/libmf/source/pn9.c b/libs/libmf/source/pn9.c
new file mode 100644
index 00000000..c0d06883
--- /dev/null
+++ b/libs/libmf/source/pn9.c
@@ -0,0 +1,7 @@
+#include "libmfcrc.h"
+
+__reentrantb uint16_t pn9_advance(uint16_t pn9) __reentrant
+{
+ pn9 &= 0x1FF;
+ return (pn9 >> 8) ^ (pn9_table[pn9] << 1);
+}
diff --git a/libs/libmf/source/pn9bit.c b/libs/libmf/source/pn9bit.c
new file mode 100644
index 00000000..1c84266a
--- /dev/null
+++ b/libs/libmf/source/pn9bit.c
@@ -0,0 +1,30 @@
+#include "libmfcrc.h"
+
+#if defined(SDCC)
+
+__reentrantb uint16_t pn9_advance_bit(uint16_t pn9) __reentrant __naked
+{
+ pn9;
+ __asm
+ mov a,dph
+ rrc a
+ mov a,dpl
+ rrc a
+ jnb acc.4,00000$
+ cpl c
+00000$: mov dpl,a
+ clr a
+ rlc a
+ mov dph,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t pn9_advance_bit(uint16_t pn9) __reentrant
+{
+ return (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
+}
+
+#endif
diff --git a/libs/libmf/source/pn9bits.c b/libs/libmf/source/pn9bits.c
new file mode 100644
index 00000000..624c73f5
--- /dev/null
+++ b/libs/libmf/source/pn9bits.c
@@ -0,0 +1,51 @@
+#include "libmfcrc.h"
+
+#if defined(SDCC)
+
+__reentrantb uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits) __reentrant __naked
+{
+ pn9;
+ bits;
+ __asm
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ mov r2,a
+ inc r0
+ mov a,@r0
+ mov r3,a
+ orl a,r2
+ jz 00000$
+ mov a,r2
+ jz 00003$
+ inc r3
+00003$: mov a,dph
+ rrc a
+ mov a,dpl
+00001$: rrc a
+ jnb acc.4,00002$
+ cpl c
+00002$: djnz r2,00001$
+ djnz r3,00001$
+ mov dpl,a
+ clr a
+ rlc a
+ mov dph,a
+00000$: ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t pn9_advance_bits(uint16_t pn9, uint16_t bits) __reentrant
+{
+ if (!bits)
+ return pn9;
+ do {
+ pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
+ } while (--bits);
+ return pn9;
+}
+
+#endif
diff --git a/libs/libmf/source/pn9buf.c b/libs/libmf/source/pn9buf.c
new file mode 100644
index 00000000..43de5af6
--- /dev/null
+++ b/libs/libmf/source/pn9buf.c
@@ -0,0 +1,219 @@
+#include "libmfcrc.h"
+
+#if defined(SDCC)
+
+__reentrantb uint16_t pn9_buffer(uint8_t __generic *buf, uint16_t buflen, uint16_t pn9, uint8_t xor) __reentrant __naked
+{
+ buf;
+ buflen;
+ pn9;
+ xor;
+ __asm;
+ mov a,sp
+ add a,#-6
+ mov r0,a
+ mov a,@r0
+ mov r7,a ; xor
+ inc r0
+ mov a,@r0
+ mov r4,a ; pn9 lo
+ inc r0
+ mov a,@r0
+ mov r5,a ; pn9 hi
+ inc r0
+ mov a,@r0
+ mov r2,a ; buflen lo
+ inc r0
+ mov a,@r0
+ mov r3,a ; buflen hi
+ orl a,r2
+ jz 00001$
+ mov a,r2
+ jz 00000$
+ inc r3
+00000$: jb _B_7,00019$ ; >0x80 code
+ jnb _B_6,00029$ ; <0x40 far
+ mov r0,dpl
+ jb _B_5,00030$ ; >0x60 pdata
+ ;; idata
+00040$: mov a,@r0
+ xrl a,r4
+ xrl a,r7
+ mov @r0,a
+ inc r0
+ mov a,r5
+ rrc a
+ mov a,r4
+ rrc a
+ jnb acc.4,00041$
+ cpl c
+00041$: rrc a
+ jnb acc.4,00042$
+ cpl c
+00042$: rrc a
+ jnb acc.4,00043$
+ cpl c
+00043$: rrc a
+ jnb acc.4,00044$
+ cpl c
+00044$: rrc a
+ jnb acc.4,00045$
+ cpl c
+00045$: rrc a
+ jnb acc.4,00046$
+ cpl c
+00046$: rrc a
+ jnb acc.4,00047$
+ cpl c
+00047$: rrc a
+ jnb acc.4,00048$
+ cpl c
+00048$: mov r4,a
+ clr a
+ rlc a
+ mov r5,a
+ djnz r2,00040$
+ djnz r3,00040$
+
+00001$:
+ mov dpl,r4
+ mov dph,r5
+ ret
+
+00019$:
+ ljmp 00010$
+
+00029$:
+ ljmp 00020$
+
+00030$: movx a,@r0
+ xrl a,r4
+ xrl a,r7
+ movx @r0,a
+ inc r0
+ mov a,r5
+ rrc a
+ mov a,r4
+ rrc a
+ jnb acc.4,00031$
+ cpl c
+00031$: rrc a
+ jnb acc.4,00032$
+ cpl c
+00032$: rrc a
+ jnb acc.4,00033$
+ cpl c
+00033$: rrc a
+ jnb acc.4,00034$
+ cpl c
+00034$: rrc a
+ jnb acc.4,00035$
+ cpl c
+00035$: rrc a
+ jnb acc.4,00036$
+ cpl c
+00036$: rrc a
+ jnb acc.4,00037$
+ cpl c
+00037$: rrc a
+ jnb acc.4,00038$
+ cpl c
+00038$: mov r4,a
+ clr a
+ rlc a
+ mov r5,a
+ djnz r2,00030$
+ djnz r3,00030$
+ sjmp 00001$
+
+00020$: movx a,@dptr
+ xrl a,r4
+ xrl a,r7
+ movx @dptr,a
+ inc dptr
+ mov a,r5
+ rrc a
+ mov a,r4
+ rrc a
+ jnb acc.4,00021$
+ cpl c
+00021$: rrc a
+ jnb acc.4,00022$
+ cpl c
+00022$: rrc a
+ jnb acc.4,00023$
+ cpl c
+00023$: rrc a
+ jnb acc.4,00024$
+ cpl c
+00024$: rrc a
+ jnb acc.4,00025$
+ cpl c
+00025$: rrc a
+ jnb acc.4,00026$
+ cpl c
+00026$: rrc a
+ jnb acc.4,00027$
+ cpl c
+00027$: rrc a
+ jnb acc.4,00028$
+ cpl c
+00028$: mov r4,a
+ clr a
+ rlc a
+ mov r5,a
+ djnz r2,00020$
+ djnz r3,00020$
+ sjmp 00001$
+
+00010$: mov a,r5
+ rrc a
+ mov a,r4
+ rrc a
+ jnb acc.4,00011$
+ cpl c
+00011$: rrc a
+ jnb acc.4,00012$
+ cpl c
+00012$: rrc a
+ jnb acc.4,00013$
+ cpl c
+00013$: rrc a
+ jnb acc.4,00014$
+ cpl c
+00014$: rrc a
+ jnb acc.4,00015$
+ cpl c
+00015$: rrc a
+ jnb acc.4,00016$
+ cpl c
+00016$: rrc a
+ jnb acc.4,00017$
+ cpl c
+00017$: rrc a
+ jnb acc.4,00018$
+ cpl c
+00018$: mov r4,a
+ clr a
+ rlc a
+ mov r5,a
+ djnz r2,00010$
+ djnz r3,00010$
+ ljmp 00001$
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t pn9_buffer(uint8_t __generic *buf, uint16_t buflen, uint16_t pn9, uint8_t xor) __reentrant
+{
+ if (!buflen)
+ return pn9;
+ do {
+ *buf++ ^= pn9 ^ xor;
+ pn9 = pn9_advance_byte(pn9);
+ } while (--buflen);
+ return pn9;
+}
+
+#endif
diff --git a/libs/libmf/source/pn9byte.c b/libs/libmf/source/pn9byte.c
new file mode 100644
index 00000000..f473a976
--- /dev/null
+++ b/libs/libmf/source/pn9byte.c
@@ -0,0 +1,55 @@
+#include "libmfcrc.h"
+
+#if defined(SDCC)
+
+__reentrantb uint16_t pn9_advance_byte(uint16_t pn9) __reentrant __naked
+{
+ pn9;
+ __asm
+ mov a,dph
+ rrc a
+ mov a,dpl
+ rrc a
+ jnb acc.4,00000$
+ cpl c
+00000$: rrc a
+ jnb acc.4,00001$
+ cpl c
+00001$: rrc a
+ jnb acc.4,00002$
+ cpl c
+00002$: rrc a
+ jnb acc.4,00003$
+ cpl c
+00003$: rrc a
+ jnb acc.4,00004$
+ cpl c
+00004$: rrc a
+ jnb acc.4,00005$
+ cpl c
+00005$: rrc a
+ jnb acc.4,00006$
+ cpl c
+00006$: rrc a
+ jnb acc.4,00007$
+ cpl c
+00007$: mov dpl,a
+ clr a
+ rlc a
+ mov dph,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t pn9_advance_byte(uint16_t pn9) __reentrant
+{
+ uint8_t bits = 8;
+ do {
+ pn9 = (uint8_t)(pn9 >> 1) | (((pn9 << 3) ^ (pn9 << 8)) & 0x100);
+ } while (--bits);
+ return pn9;
+}
+
+#endif
diff --git a/libs/libmf/source/pn9table.c b/libs/libmf/source/pn9table.c
new file mode 100644
index 00000000..d59f88f5
--- /dev/null
+++ b/libs/libmf/source/pn9table.c
@@ -0,0 +1,71 @@
+/* automatically generated by genpn9, do not edit! */
+
+#include "libmfcrc.h"
+
+const uint8_t __code pn9_table[512] = {
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+ 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+ 0x10, 0x01, 0x32, 0x23, 0x54, 0x45, 0x76, 0x67,
+ 0x98, 0x89, 0xba, 0xab, 0xdc, 0xcd, 0xfe, 0xef,
+ 0x31, 0x20, 0x13, 0x02, 0x75, 0x64, 0x57, 0x46,
+ 0xb9, 0xa8, 0x9b, 0x8a, 0xfd, 0xec, 0xdf, 0xce,
+ 0x21, 0x30, 0x03, 0x12, 0x65, 0x74, 0x47, 0x56,
+ 0xa9, 0xb8, 0x8b, 0x9a, 0xed, 0xfc, 0xcf, 0xde,
+ 0x62, 0x73, 0x40, 0x51, 0x26, 0x37, 0x04, 0x15,
+ 0xea, 0xfb, 0xc8, 0xd9, 0xae, 0xbf, 0x8c, 0x9d,
+ 0x72, 0x63, 0x50, 0x41, 0x36, 0x27, 0x14, 0x05,
+ 0xfa, 0xeb, 0xd8, 0xc9, 0xbe, 0xaf, 0x9c, 0x8d,
+ 0x53, 0x42, 0x71, 0x60, 0x17, 0x06, 0x35, 0x24,
+ 0xdb, 0xca, 0xf9, 0xe8, 0x9f, 0x8e, 0xbd, 0xac,
+ 0x43, 0x52, 0x61, 0x70, 0x07, 0x16, 0x25, 0x34,
+ 0xcb, 0xda, 0xe9, 0xf8, 0x8f, 0x9e, 0xad, 0xbc,
+ 0xc4, 0xd5, 0xe6, 0xf7, 0x80, 0x91, 0xa2, 0xb3,
+ 0x4c, 0x5d, 0x6e, 0x7f, 0x08, 0x19, 0x2a, 0x3b,
+ 0xd4, 0xc5, 0xf6, 0xe7, 0x90, 0x81, 0xb2, 0xa3,
+ 0x5c, 0x4d, 0x7e, 0x6f, 0x18, 0x09, 0x3a, 0x2b,
+ 0xf5, 0xe4, 0xd7, 0xc6, 0xb1, 0xa0, 0x93, 0x82,
+ 0x7d, 0x6c, 0x5f, 0x4e, 0x39, 0x28, 0x1b, 0x0a,
+ 0xe5, 0xf4, 0xc7, 0xd6, 0xa1, 0xb0, 0x83, 0x92,
+ 0x6d, 0x7c, 0x4f, 0x5e, 0x29, 0x38, 0x0b, 0x1a,
+ 0xa6, 0xb7, 0x84, 0x95, 0xe2, 0xf3, 0xc0, 0xd1,
+ 0x2e, 0x3f, 0x0c, 0x1d, 0x6a, 0x7b, 0x48, 0x59,
+ 0xb6, 0xa7, 0x94, 0x85, 0xf2, 0xe3, 0xd0, 0xc1,
+ 0x3e, 0x2f, 0x1c, 0x0d, 0x7a, 0x6b, 0x58, 0x49,
+ 0x97, 0x86, 0xb5, 0xa4, 0xd3, 0xc2, 0xf1, 0xe0,
+ 0x1f, 0x0e, 0x3d, 0x2c, 0x5b, 0x4a, 0x79, 0x68,
+ 0x87, 0x96, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0,
+ 0x0f, 0x1e, 0x2d, 0x3c, 0x4b, 0x5a, 0x69, 0x78,
+ 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+ 0x98, 0x89, 0xba, 0xab, 0xdc, 0xcd, 0xfe, 0xef,
+ 0x10, 0x01, 0x32, 0x23, 0x54, 0x45, 0x76, 0x67,
+ 0xb9, 0xa8, 0x9b, 0x8a, 0xfd, 0xec, 0xdf, 0xce,
+ 0x31, 0x20, 0x13, 0x02, 0x75, 0x64, 0x57, 0x46,
+ 0xa9, 0xb8, 0x8b, 0x9a, 0xed, 0xfc, 0xcf, 0xde,
+ 0x21, 0x30, 0x03, 0x12, 0x65, 0x74, 0x47, 0x56,
+ 0xea, 0xfb, 0xc8, 0xd9, 0xae, 0xbf, 0x8c, 0x9d,
+ 0x62, 0x73, 0x40, 0x51, 0x26, 0x37, 0x04, 0x15,
+ 0xfa, 0xeb, 0xd8, 0xc9, 0xbe, 0xaf, 0x9c, 0x8d,
+ 0x72, 0x63, 0x50, 0x41, 0x36, 0x27, 0x14, 0x05,
+ 0xdb, 0xca, 0xf9, 0xe8, 0x9f, 0x8e, 0xbd, 0xac,
+ 0x53, 0x42, 0x71, 0x60, 0x17, 0x06, 0x35, 0x24,
+ 0xcb, 0xda, 0xe9, 0xf8, 0x8f, 0x9e, 0xad, 0xbc,
+ 0x43, 0x52, 0x61, 0x70, 0x07, 0x16, 0x25, 0x34,
+ 0x4c, 0x5d, 0x6e, 0x7f, 0x08, 0x19, 0x2a, 0x3b,
+ 0xc4, 0xd5, 0xe6, 0xf7, 0x80, 0x91, 0xa2, 0xb3,
+ 0x5c, 0x4d, 0x7e, 0x6f, 0x18, 0x09, 0x3a, 0x2b,
+ 0xd4, 0xc5, 0xf6, 0xe7, 0x90, 0x81, 0xb2, 0xa3,
+ 0x7d, 0x6c, 0x5f, 0x4e, 0x39, 0x28, 0x1b, 0x0a,
+ 0xf5, 0xe4, 0xd7, 0xc6, 0xb1, 0xa0, 0x93, 0x82,
+ 0x6d, 0x7c, 0x4f, 0x5e, 0x29, 0x38, 0x0b, 0x1a,
+ 0xe5, 0xf4, 0xc7, 0xd6, 0xa1, 0xb0, 0x83, 0x92,
+ 0x2e, 0x3f, 0x0c, 0x1d, 0x6a, 0x7b, 0x48, 0x59,
+ 0xa6, 0xb7, 0x84, 0x95, 0xe2, 0xf3, 0xc0, 0xd1,
+ 0x3e, 0x2f, 0x1c, 0x0d, 0x7a, 0x6b, 0x58, 0x49,
+ 0xb6, 0xa7, 0x94, 0x85, 0xf2, 0xe3, 0xd0, 0xc1,
+ 0x1f, 0x0e, 0x3d, 0x2c, 0x5b, 0x4a, 0x79, 0x68,
+ 0x97, 0x86, 0xb5, 0xa4, 0xd3, 0xc2, 0xf1, 0xe0,
+ 0x0f, 0x1e, 0x2d, 0x3c, 0x4b, 0x5a, 0x69, 0x78,
+ 0x87, 0x96, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0
+};
+
diff --git a/libs/libmf/source/radiocomminit.c b/libs/libmf/source/radiocomminit.c
new file mode 100644
index 00000000..1fe3fd6d
--- /dev/null
+++ b/libs/libmf/source/radiocomminit.c
@@ -0,0 +1,32 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+__reentrantb void radio_comminit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x47;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+}
diff --git a/libs/libmf/source/radiocommslpexit.c b/libs/libmf/source/radiocommslpexit.c
new file mode 100644
index 00000000..ccd97661
--- /dev/null
+++ b/libs/libmf/source/radiocommslpexit.c
@@ -0,0 +1,33 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+__reentrantb void radio_commsleepexit(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX |= 0x40;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ // restore IRQ setting and pullup
+ radio_probeirq();
+}
diff --git a/libs/libmf/source/radiodeepsleep.c b/libs/libmf/source/radiodeepsleep.c
new file mode 100644
index 00000000..86689bb4
--- /dev/null
+++ b/libs/libmf/source/radiodeepsleep.c
@@ -0,0 +1,62 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+#if DEEPSLEEP
+
+__reentrantb void radio_enter_deepsleep(void) __reentrant
+{
+#if RADIO == 5043
+ PORTR |= 0x0B;
+ AX5043_PINFUNCSYSCLK = 0x01;
+#else
+ PORTR |= 0x09;
+#endif
+ // ensure last bit read before entering deep sleep is a zero;
+ // this is held until after wakeup is complete; otherwise,
+ // the wakeup protocol will not work
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ RADIO_PWRMODE = PWRMODE_DEEPSLEEP;
+ RADIOMUX &= (uint8_t)~0x40;
+ // turn off pull-up if MISO is driven low
+ PORTR &= 0xF7 | PINR;
+}
+
+__reentrantb uint8_t radio_wakeup_deepsleep(void) __reentrant
+{
+ DIRR = 0x15;
+ PORTR = 0xEB;
+ RADIOMUX = 0x07;
+ RADIOACC = RACC;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+ GPIOENABLE = 1;
+ {
+ uint8_t i = radio_wakeup_deepsleep_core();
+ if (i)
+ return i;
+ }
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/source/radiodefs.h b/libs/libmf/source/radiodefs.h
new file mode 100644
index 00000000..7ee65a5b
--- /dev/null
+++ b/libs/libmf/source/radiodefs.h
@@ -0,0 +1,120 @@
+#ifndef RADIODEFS_H
+#define RADIODEFS_H
+
+#if RADIO == 5031
+
+#include "ax8052f131.h"
+
+#define radio_probeirq ax5031_probeirq
+#define radio_comminit ax5031_comminit
+#define radio_commsleepexit ax5031_commsleepexit
+#define radio_reset ax5031_reset
+#define radio_readfifo ax5031_readfifo
+#define radio_writefifo ax5031_writefifo
+#define RACC 0x00
+#define FDATA 0x005
+#define FSTAT 0x004
+#define DEEPSLEEP 0
+#define VREGDELAY 10
+
+#define RADIO_SILICONREVISION AX5031_SILICONREVISION
+#define RADIO_SCRATCH AX5031_SCRATCH
+#define RADIO_PWRMODE AX5031_PWRMODE
+
+#define PWRMODE_PWRDOWN 0x00
+
+#define SILICONREV1 0x21
+#undef SILICONREV2
+
+#elif RADIO == 5042
+
+#include "ax8052f142.h"
+
+#define radio_probeirq ax5042_probeirq
+#define radio_comminit ax5042_comminit
+#define radio_commsleepexit ax5042_commsleepexit
+#define radio_reset ax5042_reset
+#define radio_readfifo ax5042_readfifo
+#define radio_writefifo ax5042_writefifo
+#define RACC 0x00
+#define FDATA 0x005
+#define FSTAT 0x004
+#define DEEPSLEEP 0
+#define VREGDELAY 0
+
+#define RADIO_SILICONREVISION AX5042_SILICONREVISION
+#define RADIO_SCRATCH AX5042_SCRATCH
+#define RADIO_PWRMODE AX5042_PWRMODE
+
+#define PWRMODE_PWRDOWN 0x00
+
+#define SILICONREV1 0x02
+#undef SILICONREV2
+
+#elif RADIO == 5043
+
+#include "ax8052f143.h"
+
+#define radio_probeirq ax5043_probeirq
+#define radio_comminit ax5043_comminit
+#define radio_commsleepexit ax5043_commsleepexit
+#define radio_reset ax5043_reset
+#define radio_readfifo ax5043_readfifo
+#define radio_writefifo ax5043_writefifo
+#define radio_enter_deepsleep ax5043_enter_deepsleep
+#define radio_wakeup_deepsleep ax5043_wakeup_deepsleep
+#define RACC 0x0c
+#define FDATA 0x029
+#define FSTAT 0x028
+#define DEEPSLEEP 1
+#define VREGDELAY 10
+
+#define RADIO_SILICONREVISION AX5043_SILICONREVISION
+#define RADIO_SCRATCH AX5043_SCRATCH
+#define RADIO_PWRMODE AX5043_PWRMODE
+
+#define PWRMODE_PWRDOWN 0x00
+#define PWRMODE_DEEPSLEEP 0x01
+
+#define SILICONREV1 0x51
+#undef SILICONREV2
+
+#elif RADIO == 5051
+
+#include "ax8052f151.h"
+
+#define radio_probeirq ax5051_probeirq
+#define radio_comminit ax5051_comminit
+#define radio_commsleepexit ax5051_commsleepexit
+#define radio_reset ax5051_reset
+#define radio_readfifo ax5051_readfifo
+#define radio_writefifo ax5051_writefifo
+#define RACC 0x00
+#define FDATA 0x005
+#define FSTAT 0x004
+#define DEEPSLEEP 0
+#define VREGDELAY 0
+
+#define RADIO_SILICONREVISION AX5051_SILICONREVISION
+#define RADIO_SCRATCH AX5051_SCRATCH
+#define RADIO_PWRMODE AX5051_PWRMODE
+
+#define PWRMODE_PWRDOWN 0x00
+
+#define SILICONREV1 0x16
+#define SILICONREV2 0x14
+
+#else
+#error unknown radio
+#endif
+
+#define RADIO_OK 0
+#define RADIO_ERR_REVISION 1
+#define RADIO_ERR_COMM 2
+#define RADIO_ERR_IRQ 3
+#define RADIO_ERR_WAKEUPTIMEOUT 4
+
+extern __reentrantb uint8_t radio_probeirq(void) __reentrant;
+extern __reentrantb uint8_t radio_wakeup_deepsleep_core(void) __reentrant;
+
+#endif /* RADIODEFS_H */
diff --git a/libs/libmf/source/radiodswakecore.c b/libs/libmf/source/radiodswakecore.c
new file mode 100644
index 00000000..6d50a8bd
--- /dev/null
+++ b/libs/libmf/source/radiodswakecore.c
@@ -0,0 +1,27 @@
+#include "libmftypes.h"
+#define RADIO 5043
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_wakeup_deepsleep_core(void) __reentrant
+{
+ uint8_t i = 3, j = 0;
+ PORTR &= (uint8_t)~0x08;
+ do {
+ do {
+ // precharge
+ DIRR |= 0x08;
+ DIRR &= (uint8_t)~0x08;
+ PORTR &= (uint8_t)~1;
+ if (PINR & 0x08) {
+ i = 0;
+ goto dswakeup;
+ }
+ PORTR |= 1;
+ } while (--j);
+ } while (--i);
+ i = RADIO_ERR_WAKEUPTIMEOUT;
+ dswakeup:
+ PORTR |= 0x09;
+ RADIOMUX = 0x47;
+ return i;
+}
diff --git a/libs/libmf/source/radiord16.c b/libs/libmf/source/radiord16.c
new file mode 100644
index 00000000..ea9b770b
--- /dev/null
+++ b/libs/libmf/source/radiord16.c
@@ -0,0 +1,52 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb uint16_t radio_read16(uint16_t addr) __reentrant __naked
+{
+ addr;
+ __asm;
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x01
+ mov _RADIOACC,a
+ movx a,@dptr
+ mov _RADIOACC,b
+ mov dph,a
+ mov dpl,_RADIODATA2
+ mov _EA,c
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t radio_read16(uint16_t addr) __reentrant
+{
+ uint8_t iesave, racc;
+ uint16_t r;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x01;
+ r = *(uint8_t __xdata *)addr;
+ r <<= 8;
+ r |= RADIODATA2;
+ RADIOACC = racc;
+ IE |= iesave;
+ return r;
+}
+
+#endif
diff --git a/libs/libmf/source/radiord24.c b/libs/libmf/source/radiord24.c
new file mode 100644
index 00000000..8e06740d
--- /dev/null
+++ b/libs/libmf/source/radiord24.c
@@ -0,0 +1,56 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb uint32_t radio_read24(uint16_t addr) __reentrant __naked
+{
+ addr;
+ __asm;
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x02
+ mov _RADIOACC,a
+ movx a,@dptr
+ mov _RADIOACC,b
+ mov b,a
+ mov dph,_RADIODATA2
+ mov dpl,_RADIODATA1
+ mov _EA,c
+ clr a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t radio_read24(uint16_t addr) __reentrant
+{
+ uint8_t iesave, racc;
+ uint32_t r;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x02;
+ r = *(uint8_t __xdata *)addr;
+ r <<= 8;
+ r |= RADIODATA2;
+ r <<= 8;
+ r |= RADIODATA1;
+ RADIOACC = racc;
+ IE |= iesave;
+ return r;
+}
+
+#endif
diff --git a/libs/libmf/source/radiord32.c b/libs/libmf/source/radiord32.c
new file mode 100644
index 00000000..5014f1ba
--- /dev/null
+++ b/libs/libmf/source/radiord32.c
@@ -0,0 +1,57 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb uint32_t radio_read32(uint16_t addr) __reentrant __naked
+{
+ addr;
+ __asm;
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x03
+ mov _RADIOACC,a
+ movx a,@dptr
+ mov _RADIOACC,b
+ mov b,_RADIODATA2
+ mov dph,_RADIODATA1
+ mov dpl,_RADIODATA0
+ mov _EA,c
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint32_t radio_read32(uint16_t addr) __reentrant
+{
+ uint8_t iesave, racc;
+ uint32_t r;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x03;
+ r = *(uint8_t __xdata *)addr;
+ r <<= 8;
+ r |= RADIODATA2;
+ r <<= 8;
+ r |= RADIODATA1;
+ r <<= 8;
+ r |= RADIODATA0;
+ RADIOACC = racc;
+ IE |= iesave;
+ return r;
+}
+
+#endif
diff --git a/libs/libmf/source/radiordfifo.c b/libs/libmf/source/radiordfifo.c
new file mode 100644
index 00000000..1521eaf9
--- /dev/null
+++ b/libs/libmf/source/radiordfifo.c
@@ -0,0 +1,96 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ movx a,@dptr
+ mov @r0,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ movx a,@r0
+ ;movc @dptr,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_readfifo(uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *ptr++ = *(const uint8_t __xdata *)(AX8052_RADIOBASE | FDATA);
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/source/radioreset.c b/libs/libmf/source/radioreset.c
new file mode 100644
index 00000000..dd885383
--- /dev/null
+++ b/libs/libmf/source/radioreset.c
@@ -0,0 +1,244 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+__reentrantb uint8_t radio_reset(void) __reentrant
+{
+ uint8_t i;
+ // Initialize Interface
+ DIRR = 0x15;
+ PORTR = 0xEB;
+#if DEEPSLEEP
+ RADIOMUX = 0x07;
+#else
+ RADIOMUX = 0x47;
+#endif
+ RADIOACC = RACC;
+ GPIOENABLE = 1;
+#if defined SDCC
+ RADIOFDATAADDR = FDATA;
+ RADIOFSTATADDR = FSTAT;
+#else
+ RADIOFDATAADDR0 = (FDATA) & 0xFF;
+ RADIOFDATAADDR1 = (FDATA) >> 8;
+ RADIOFSTATADDR0 = (FSTAT) & 0xFF;
+ RADIOFSTATADDR1 = (FSTAT) >> 8;
+#endif
+#if DEEPSLEEP
+ // Ensure Device is not in Deep Sleep
+ radio_wakeup_deepsleep_core();
+#endif
+ // Reset Device
+ RADIO_PWRMODE = 0x80;
+ RADIO_PWRMODE = PWRMODE_PWRDOWN;
+ // Wait some time for regulator startup
+#if defined(VREGDELAY) && VREGDELAY > 0
+ delay(VREGDELAY);
+#endif
+ // Check Scratch
+ i = RADIO_SILICONREVISION;
+ i = RADIO_SILICONREVISION;
+#ifdef SILICONREV2
+ if (i != SILICONREV1 && i != SILICONREV2)
+ return RADIO_ERR_REVISION;
+#else
+ if (i != SILICONREV1)
+ return RADIO_ERR_REVISION;
+#endif
+ RADIO_SCRATCH = 0x55;
+ if (RADIO_SCRATCH != 0x55)
+ return RADIO_ERR_COMM;
+ RADIO_SCRATCH = 0xAA;
+ if (RADIO_SCRATCH != 0xAA)
+ return RADIO_ERR_COMM;
+ // Initialize Radio Interface Registers
+#if RADIO == 5031
+#elif RADIO == 5042
+ AX5042_IFMODE = 0x00;
+ AX5042_AGCTARGET = 0x0E;
+ AX5042_PLLRNGMISC = 0x01;
+ AX5042_RXMISC = 0x35;
+#elif RADIO == 5043
+#elif RADIO == 5051
+ AX5051_IFMODE = 0x00;
+ AX5051_PLLVCOI = 0x01;
+ AX5051_RXMISC = 0x35;
+#endif
+ if (radio_probeirq())
+ return RADIO_ERR_IRQ;
+ return RADIO_OK;
+}
+
+#if RADIO == 5031
+
+__reentrantb uint8_t ax5031_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5031_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5031_PINCFG1 = pc1;
+ AX5031_PINCFG2 = 0x22; /* IRQ Line 1 */
+ p &= PINR;
+ AX5031_PINCFG2 = 0x20; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5031_PINCFG2 = 0x00;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5031_PINCFG1 = 0x20 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
+#elif RADIO == 5042
+
+__reentrantb uint8_t ax5042_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5042_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5042_PINCFG1 = 0xD0 | pc1;
+ AX5042_PINCFG2 = 0xE2; /* IRQ Line 1 */
+ p &= PINR;
+ AX5042_PINCFG2 = 0xE0; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5042_PINCFG2 = 0xC0;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5042_PINCFG1 = 0xF0 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
+#elif RADIO == 5043
+
+SFRX(RADIODRV, 0x7045)
+
+__reentrantb uint8_t ax5043_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR &= 0xEB;
+ PORTR |= 0x2B;
+ AX5043_PINFUNCIRQ = 0x01; /* IRQ Line 1 */
+ p &= PINR;
+ AX5043_PINFUNCIRQ = 0x00; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5043_PINFUNCIRQ = 0x03;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5043_PINFUNCIRQ = 0x02; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ IE = iesave;
+ return 0;
+}
+
+#elif RADIO == 5051
+
+__reentrantb uint8_t ax5051_probeirq(void) __reentrant
+{
+ uint8_t p = 0x60;
+ uint8_t pc1 = AX5051_PINCFG1 & 0x0F;
+ uint8_t iesave = IE;
+ IE_4 = 0;
+ PORTR = 0xEB;
+ AX5051_PINCFG1 = 0xD0 | pc1;
+ AX5051_PINCFG2 = 0xF2; /* IRQ Line 1 */
+ p &= PINR;
+ AX5051_PINCFG2 = 0xF0; /* IRQ Line 0 */
+ p &= (uint8_t)~PINR;
+ AX5051_PINCFG2 = 0xD0;
+ switch (p) {
+ case 0x20: /* IRQ on PR5 */
+ RADIOMUX &= (uint8_t)~0x08;
+ break;
+
+ case 0x40: /* IRQ on PR6 */
+ RADIOMUX |= 0x08;
+ break;
+
+ default:
+ /* Error */
+ AX5051_PINCFG1 = 0xA0 | pc1; /* Disable IRQ line */
+ IE = iesave;
+ return 1;
+ }
+ PORTR &= (uint8_t)~p; /* disable pullup */
+ /*
+ * Check voltage on test mode pins and drive them
+ * to the correct level. This is somewhat dangerous - we
+ * may momentarily short circuit the output driver (4mA)
+ * no short circuit will happen if the board complies
+ * to AX5051/AX5151/AX8052F151 programming manual
+ */
+ EA = 0;
+ /* check T2 */
+ AX5051_PINCFG1 = 0xC0 | pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x01;
+ /* check T1 */
+ AX5051_PINCFG1 = 0x80 | pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x04;
+ /* check TST3 */
+ AX5051_PINCFG1 = pc1;
+ AX5051_PINCFG2 |= AX5051_PINCFG3 & 0x08;
+ IE |= p;
+ /* check whether TST3 is connected to PR5 - if so disable pullup */
+ PORTR &= PINR | (uint8_t)~0x20;
+ IE = iesave;
+ return 0;
+}
+
+#endif
diff --git a/libs/libmf/source/radiowr16.c b/libs/libmf/source/radiowr16.c
new file mode 100644
index 00000000..297f6cfb
--- /dev/null
+++ b/libs/libmf/source/radiowr16.c
@@ -0,0 +1,66 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_write16(uint16_t addr, uint16_t d) __reentrant __naked
+{
+ addr;
+ d;
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,sp
+ add a,#-3
+ push ar0
+ mov r0,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x01
+ mov _RADIOACC,a
+ mov _RADIODATA2,@r0
+ inc r0
+ mov a,@r0
+ movx @dptr,a
+ mov _RADIOACC,b
+ mov _EA,c
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_write16(uint16_t addr, uint16_t d) __reentrant
+{
+ uint8_t iesave, racc;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x01;
+ RADIODATA2 = d;
+ d >>= 8;
+ *(uint8_t __xdata *)addr = d;
+ RADIOACC = racc;
+ IE |= iesave;
+}
+
+#endif
diff --git a/libs/libmf/source/radiowr24.c b/libs/libmf/source/radiowr24.c
new file mode 100644
index 00000000..7fd80e69
--- /dev/null
+++ b/libs/libmf/source/radiowr24.c
@@ -0,0 +1,70 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_write24(uint16_t addr, uint32_t d) __reentrant __naked
+{
+ addr;
+ d;
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,sp
+ add a,#-5
+ push ar0
+ mov r0,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x01
+ mov _RADIOACC,a
+ mov _RADIODATA1,@r0
+ inc r0
+ mov _RADIODATA2,@r0
+ inc r0
+ mov a,@r0
+ movx @dptr,a
+ mov _RADIOACC,b
+ mov _EA,c
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_write24(uint16_t addr, uint32_t d) __reentrant
+{
+ uint8_t iesave, racc;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x02;
+ RADIODATA1 = d;
+ d >>= 8;
+ RADIODATA2 = d;
+ d >>= 8;
+ *(uint8_t __xdata *)addr = d;
+ RADIOACC = racc;
+ IE |= iesave;
+}
+
+#endif
diff --git a/libs/libmf/source/radiowr32.c b/libs/libmf/source/radiowr32.c
new file mode 100644
index 00000000..02781fc5
--- /dev/null
+++ b/libs/libmf/source/radiowr32.c
@@ -0,0 +1,74 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_write32(uint16_t addr, uint32_t d) __reentrant __naked
+{
+ addr;
+ d;
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,dph
+ anl a,#0x0F
+ orl a,#(AX8052_RADIOBASE >> 8)
+ mov dph,a
+ mov a,sp
+ add a,#-5
+ push ar0
+ mov r0,a
+ mov a,_IE
+ rlc a
+ clr _EA
+ mov a,_RADIOACC
+ mov b,a
+ anl a,#0xFC
+ orl a,#0x01
+ mov _RADIOACC,a
+ mov _RADIODATA0,@r0
+ inc r0
+ mov _RADIODATA1,@r0
+ inc r0
+ mov _RADIODATA2,@r0
+ inc r0
+ mov a,@r0
+ movx @dptr,a
+ mov _RADIOACC,b
+ mov _EA,c
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_write32(uint16_t addr, uint32_t d) __reentrant
+{
+ uint8_t iesave, racc;
+ addr &= 0xFFF;
+ addr |= AX8052_RADIOBASE;
+ iesave = IE & 0x80;
+ EA = 0;
+ racc = RADIOACC;
+ RADIOACC = (racc & 0xFC) | 0x03;
+ RADIODATA0 = d;
+ d >>= 8;
+ RADIODATA1 = d;
+ d >>= 8;
+ RADIODATA2 = d;
+ d >>= 8;
+ *(uint8_t __xdata *)addr = d;
+ RADIOACC = racc;
+ IE |= iesave;
+}
+
+#endif
diff --git a/libs/libmf/source/radiowrfifo.c b/libs/libmf/source/radiowrfifo.c
new file mode 100644
index 00000000..21d25f8f
--- /dev/null
+++ b/libs/libmf/source/radiowrfifo.c
@@ -0,0 +1,97 @@
+#include "libmftypes.h"
+#include "libmfradio.h"
+
+#if RADIO == 5031
+#define RADIO 5031
+#elif RADIO == 5042
+#define RADIO 5042
+#elif RADIO == 5043
+#define RADIO 5043
+#elif RADIO == 5051
+#define RADIO 5051
+#endif
+
+#include "radiodefs.h"
+
+#if defined(SDCC)
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant __naked
+{
+ ptr;
+ len;
+ __asm;
+ mov a,sp
+ add a,#-2
+ mov r0,a
+ mov a,@r0
+ jz nodata$
+ mov r7,a
+ jb _B_7,codeptr$ ; >0x80 code
+ jnb _B_6,xdataptr$ ; <0x40 far
+ mov r0,dpl
+ mov dptr,#(AX8052_RADIOBASE | FDATA)
+ jb _B_5,pdataptr$ ; >0x60 pdata
+idataloop$:
+ mov a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,idataloop$
+nodata$:
+ ret
+pdataptr$:
+pdataloop$:
+ movx a,@r0
+ movx @dptr,a
+ inc r0
+ djnz r7,pdataloop$
+ ret
+xdataptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+xdataloop$:
+ movx a,@dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,xdataloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+codeptr$:
+ mov a,#0x80
+ anl a,_IE
+ mov r5,a
+ clr _EA
+ mov r6,_XPAGE
+ mov _XPAGE,#((AX8052_RADIOBASE | FDATA) >> 8)
+ mov r0,#(AX8052_RADIOBASE | FDATA)
+codeloop$:
+ clr a
+ movc a,@a+dptr
+ movx @r0,a
+ inc dptr
+ djnz r7,codeloop$
+ mov _XPAGE,r6
+ mov a,r5
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void radio_writefifo(const uint8_t __generic *ptr, uint8_t len) __reentrant
+{
+ if (!len)
+ return;
+ do {
+ *(uint8_t __xdata *)(AX8052_RADIOBASE | FDATA) = *ptr++;
+ } while (--len);
+}
+
+#endif
diff --git a/libs/libmf/source/random.c b/libs/libmf/source/random.c
new file mode 100644
index 00000000..dcd960b5
--- /dev/null
+++ b/libs/libmf/source/random.c
@@ -0,0 +1,46 @@
+#include "libmftypes.h"
+
+__data uint16_t random_seed;
+
+#ifdef SDCC
+
+/**
+ * \brief Pseudo Random Number Generator for Channel Access
+ *
+ */
+uint16_t random(void)
+{
+ __asm
+ mov a,_random_seed
+ mov b,#<28629
+ mul ab
+ add a,#<157
+ mov dpl,a
+ mov a,b
+ addc a,#>157
+ mov dph,a
+ mov a,_random_seed
+ mov b,#>28629
+ mul ab
+ add a,dph
+ mov dph,a
+ mov a,_random_seed+1
+ mov b,#<28629
+ mul ab
+ add a,dph
+ mov dph,a
+ mov _random_seed,dpl
+ mov _random_seed+1,a
+ ret
+ __endasm;
+}
+
+#else
+
+uint16_t random(void)
+{
+ random_seed = 28629U * random_seed + 157U;
+ return random_seed;
+}
+
+#endif
diff --git a/libs/libmf/source/resetcpu.c b/libs/libmf/source/resetcpu.c
new file mode 100644
index 00000000..9a68b305
--- /dev/null
+++ b/libs/libmf/source/resetcpu.c
@@ -0,0 +1,46 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#ifdef SDCC
+
+/**
+ * \brief reset the CPU
+ *
+ */
+__reentrantb void reset_cpu(void) __reentrant
+{
+ EA = 0;
+ GPIOENABLE = 0;
+ CODECONFIG = 0xD3;
+ __asm
+ ljmp 0xE047
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+__reentrantb void reset_cpu(void) __reentrant
+{
+ EA = 0;
+ GPIOENABLE = 0;
+ CODECONFIG = 0xD3;
+#pragma asm
+ ljmp 0xE047
+#pragma endasm
+}
+
+#elif defined __ICC8051__
+
+__noreturn __reentrantb void reset_cpu(void) __reentrant
+{
+ EA = 0;
+ GPIOENABLE = 0;
+ CODECONFIG = 0xD3;
+ asm("ljmp 0xE047");
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
diff --git a/libs/libmf/source/rev8.c b/libs/libmf/source/rev8.c
new file mode 100644
index 00000000..13c3204d
--- /dev/null
+++ b/libs/libmf/source/rev8.c
@@ -0,0 +1,9 @@
+#include "libmftypes.h"
+
+__reentrantb uint8_t rev8(uint8_t x) __reentrant
+{
+ x = ((x >> 4) & 0x0F) | ((x << 4) & 0xF0);
+ x = ((x >> 2) & 0x33) | ((x << 2) & 0xCC);
+ x = ((x >> 1) & 0x55) | ((x << 1) & 0xAA);
+ return x;
+}
diff --git a/libs/libmf/source/setupcal.c b/libs/libmf/source/setupcal.c
new file mode 100644
index 00000000..e4eaffc3
--- /dev/null
+++ b/libs/libmf/source/setupcal.c
@@ -0,0 +1,124 @@
+#include "ax8052.h"
+#include "libmfosc.h"
+
+/**
+ * \brief set up oscillator calibration
+ *
+ */
+
+static __reentrantb uint8_t compute_frcosccfg(uint32_t reffreq) __reentrant
+{
+ uint8_t x = 0;
+ while (reffreq >= 500) {
+ if (x & 0x80)
+ return x;
+ x += 0x08;
+ reffreq >>= 1;
+ }
+ if (reffreq < 250)
+ return 0x80;
+ return x;
+}
+
+static __reentrantb void compute_frcoscref(uint32_t reffreq, uint8_t calcfg) __reentrant
+{
+ static const uint32_t __code refs[9] = {
+ 10000000, 10000000 << 1, 10000000 << 2, 10000000 << 3, 10000000 << 4, 10000000 << 5, 10000000 << 6, 10000000 << 7, 10000000 << 8
+ };
+ calcfg >>= 3;
+ if (calcfg > 8) {
+ calcfg -= 8;
+ reffreq >>= calcfg;
+ calcfg = 8;
+ }
+#ifdef SDCC
+ FRCOSCREF = refs[calcfg] / reffreq;
+#else
+ {
+ uint16_t x = refs[calcfg] / reffreq;
+ FRCOSCREF0 = x;
+ FRCOSCREF1 = x >> 8;
+ }
+#endif
+}
+
+static __reentrantb uint8_t compute_lposccfg(uint32_t reffreq) __reentrant
+{
+ uint8_t x = 0;
+ reffreq /= 320;
+ while (reffreq >= 0xC000) {
+ if (x & 0x40)
+ return x;
+ x += 0x08;
+ reffreq >>= 1;
+ }
+ if (reffreq < 0x6000)
+ return 0x40;
+#ifdef SDCC
+ LPOSCREF = reffreq;
+#else
+ LPOSCREF0 = reffreq;
+ LPOSCREF1 = reffreq >> 8;
+#endif
+ return x;
+}
+
+__reentrantb uint8_t setup_osc_calibration(uint32_t reffreq, uint8_t refosc) __reentrant
+{
+ uint8_t refosc1 = refosc;
+ uint8_t lposccfg;
+ uint8_t frcosccfg;
+
+ frcosccfg = compute_frcosccfg(reffreq);
+ if (frcosccfg & 0x80)
+ return 1;
+ compute_frcoscref(reffreq, frcosccfg);
+ lposccfg = compute_lposccfg(reffreq);
+ if (lposccfg & 0x40) {
+#ifdef SDCC
+ LPOSCREF = 0x7A12;
+#else
+ LPOSCREF0 = 0x12;
+ LPOSCREF1 = 0x7A;
+#endif
+ lposccfg = 0x80;
+ } else {
+ lposccfg |= 0x07;
+ }
+ lposccfg |= LPOSCCONFIG & 0x40;
+ switch (refosc1) {
+ case CLKSRC_XOSC:
+ setup_xosc();
+ OSCFORCERUN |= 0x04;
+ frcosccfg |= 0x02;
+ lposccfg &= 0xF8 | 0x02;
+ break;
+
+ case CLKSRC_LPXOSC:
+ setup_lpxosc();
+ OSCFORCERUN |= 0x08;
+ frcosccfg |= 0x03;
+ lposccfg &= 0xF8 | 0x03;
+ break;
+
+ case CLKSRC_RSYSCLK:
+ frcosccfg |= 0x04;
+ lposccfg &= 0xF8 | 0x04;
+ break;
+
+ default:
+ return 2;
+ }
+#ifdef SDCC
+ FRCOSCKFILT = 0x4000;
+ LPOSCKFILT = 0x4000;
+#else
+ FRCOSCKFILT0 = 0x00;
+ FRCOSCKFILT1 = 0x40;
+ LPOSCKFILT0 = 0x00;
+ LPOSCKFILT1 = 0x40;
+#endif
+ FRCOSCCONFIG = frcosccfg;
+ LPOSCCONFIG = lposccfg;
+ return 0;
+}
diff --git a/libs/libmf/source/setuplpxosc.c b/libs/libmf/source/setuplpxosc.c
new file mode 100644
index 00000000..7a51a815
--- /dev/null
+++ b/libs/libmf/source/setuplpxosc.c
@@ -0,0 +1,14 @@
+#include "ax8052.h"
+#include "libmfosc.h"
+
+/**
+ * \brief set up LPXOSC
+ *
+ */
+__reentrantb void setup_lpxosc(void) __reentrant
+{
+ ANALOGA |= 0x18;
+ DIRA &= (uint8_t)~0x18;
+ PORTA &= (uint8_t)~0x18;
+ MISCCTRL &= (uint8_t)~0x01;
+}
diff --git a/libs/libmf/source/setupxosc.c b/libs/libmf/source/setupxosc.c
new file mode 100644
index 00000000..7c8962cd
--- /dev/null
+++ b/libs/libmf/source/setupxosc.c
@@ -0,0 +1,14 @@
+#include "ax8052.h"
+#include "libmfosc.h"
+
+/**
+ * \brief set up XOSC
+ *
+ */
+__reentrantb void setup_xosc(void) __reentrant
+{
+ ANALOGA |= 0x03;
+ DIRA &= (uint8_t)~0x03;
+ PORTA &= (uint8_t)~0x03;
+ MISCCTRL &= (uint8_t)~0x02;
+}
diff --git a/libs/libmf/source/sgnlim16.c b/libs/libmf/source/sgnlim16.c
new file mode 100644
index 00000000..451bd44c
--- /dev/null
+++ b/libs/libmf/source/sgnlim16.c
@@ -0,0 +1,76 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ push ar0
+ mov a,sp
+ add a,#-4
+ mov r0,a
+ mov a,dph
+ jnb acc.7,00010$
+ mov a,dpl
+ add a,@r0
+ inc r0
+ mov a,dph
+ addc a,@r0
+ jnb acc.7,00000$
+ dec r0
+ clr c
+ clr a
+ subb a,@r0
+ inc r0
+ mov dpl,a
+ clr a
+ subb a,@r0
+ sjmp 00001$
+00010$: setb c
+ mov a,dpl
+ subb a,@r0
+ inc r0
+ mov a,dph
+ subb a,@r0
+ jb acc.7,00000$
+ dec r0
+ mov a,@r0
+ inc r0
+ mov dpl,a
+ mov a,@r0
+00001$: mov dph,a
+00000$: pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+#include
+
+__reentrantb int16_t signedlimit16(int16_t x, int16_t lim) __reentrant
+{
+ if (x < 0) {
+ int16_t xx = x + lim;
+ if (xx >= 0)
+ return x;
+ return -lim;
+ }
+ {
+ int16_t xx = x - lim;
+ if (xx <= 0)
+ return x;
+ return lim;
+ }
+}
+
+#endif
diff --git a/libs/libmf/source/sgnlim32.c b/libs/libmf/source/sgnlim32.c
new file mode 100644
index 00000000..da5da4c0
--- /dev/null
+++ b/libs/libmf/source/sgnlim32.c
@@ -0,0 +1,110 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant __naked
+{
+ __asm
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ push ar0
+ push ar1
+ mov r1,a
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,r1
+ jnb acc.7,00010$
+ mov a,dpl
+ add a,@r0
+ inc r0
+ mov a,dph
+ addc a,@r0
+ inc r0
+ mov a,b
+ addc a,@r0
+ inc r0
+ mov a,r1
+ addc a,@r0
+ jnb acc.7,00000$
+ dec r0
+ dec r0
+ dec r0
+ clr c
+ clr a
+ subb a,@r0
+ inc r0
+ mov dpl,a
+ clr a
+ subb a,@r0
+ inc r0
+ mov dph,a
+ clr a
+ subb a,@r0
+ inc r0
+ mov b,a
+ clr a
+ subb a,@r0
+ sjmp 00001$
+00010$: setb c
+ mov a,dpl
+ subb a,@r0
+ inc r0
+ mov a,dph
+ subb a,@r0
+ inc r0
+ mov a,b
+ subb a,@r0
+ inc r0
+ mov a,r1
+ subb a,@r0
+ jb acc.7,00000$
+ dec r0
+ dec r0
+ dec r0
+ mov a,@r0
+ inc r0
+ mov dpl,a
+ mov a,@r0
+ inc r0
+ mov dph,a
+ mov a,@r0
+ inc r0
+ mov b,a
+ mov a,@r0
+ sjmp 00001$
+00000$: mov a,r1
+00001$: pop ar1
+ pop ar0
+ ret
+ __endasm;
+}
+
+#else
+
+#include
+
+__reentrantb int32_t signedlimit32(int32_t x, int32_t lim) __reentrant
+{
+ if (x < 0) {
+ int32_t xx = x + lim;
+ if (xx >= 0)
+ return x;
+ return -lim;
+ }
+ {
+ int32_t xx = x - lim;
+ if (xx <= 0)
+ return x;
+ return lim;
+ }
+}
+
+#endif
diff --git a/libs/libmf/source/signext12.c b/libs/libmf/source/signext12.c
new file mode 100644
index 00000000..5f78b1c3
--- /dev/null
+++ b/libs/libmf/source/signext12.c
@@ -0,0 +1,33 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int32_t signextend12(int16_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ mov a,dph
+ anl a,#0x0F
+ mov dph,a
+ anl a,#0x08
+ cpl a
+ inc a
+ orl a,dph
+ mov dph,a
+ rlc a
+ subb a,acc
+ mov b,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb int32_t signextend12(int16_t x) __reentrant
+{
+ x &= 0xFFF;
+ x |= -(x & 0x800);
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/signext16.c b/libs/libmf/source/signext16.c
new file mode 100644
index 00000000..b9e310fb
--- /dev/null
+++ b/libs/libmf/source/signext16.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int32_t signextend16(int16_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ mov a,dph
+ rlc a
+ subb a,acc
+ mov b,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb int32_t signextend16(int16_t x) __reentrant
+{
+ return x;
+}
+
+
+#endif
diff --git a/libs/libmf/source/signext20.c b/libs/libmf/source/signext20.c
new file mode 100644
index 00000000..a5b86785
--- /dev/null
+++ b/libs/libmf/source/signext20.c
@@ -0,0 +1,32 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int32_t signextend20(int32_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ mov a,b
+ anl a,#0x0F
+ mov b,a
+ anl a,#0x08
+ cpl a
+ inc a
+ orl a,b
+ mov b,a
+ rlc a
+ subb a,acc
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb int32_t signextend20(int32_t x) __reentrant
+{
+ x &= 0xFFFFF;
+ x |= -(x & 0x80000);
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/signext24.c b/libs/libmf/source/signext24.c
new file mode 100644
index 00000000..6632b2d1
--- /dev/null
+++ b/libs/libmf/source/signext24.c
@@ -0,0 +1,25 @@
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+__reentrantb int32_t signextend24(int32_t x) __reentrant __naked
+{
+ x;
+ __asm;
+ mov a,b
+ rlc a
+ subb a,acc
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb int32_t signextend24(int32_t x) __reentrant
+{
+ x &= 0xFFFFFF;
+ x |= -(x & 0x800000);
+ return x;
+}
+
+#endif
diff --git a/libs/libmf/source/sleep.c b/libs/libmf/source/sleep.c
new file mode 100644
index 00000000..9971e0df
--- /dev/null
+++ b/libs/libmf/source/sleep.c
@@ -0,0 +1,79 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#ifdef SDCC
+
+/**
+ * \brief enter sleep mode
+ *
+ */
+__reentrantb void enter_sleep(void) __reentrant __naked
+{
+ __asm
+ mov dptr,#_RADIOMUX
+ movx a,@dptr
+ anl a,#~0x40
+ movx @dptr,a
+ clr _EA
+ clr a
+ mov _EIE,a
+ mov _E2IE,a
+ mov dptr,#_GPIOENABLE
+ movx @dptr,a
+ mov r0,#0xff
+ mov @r0,a
+ dec r0
+ mov @r0,a
+ mov a,_PCON
+ anl a,#0x0c
+ orl a,#0x02
+ mov _PCON,a
+ mov _CODECONFIG,#0xd3
+ ljmp 0xe047
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+__reentrantb void enter_sleep(void) __reentrant
+{
+ for (;;) {
+ RADIOMUX &= (uint8_t)~0x40;
+ EA = 0;
+ EIE = 0x00;
+ E2IE = 0x00;
+ GPIOENABLE = 0;
+ PCON = 0x02 | (PCON & 0x0C);
+ CODECONFIG = 0xD3;
+#pragma asm
+ ljmp 0xE047
+#pragma endasm
+ }
+}
+
+#elif defined __ICC8051__
+
+__noreturn __reentrantb void enter_sleep(void) __reentrant
+{
+ for (;;) {
+ RADIOMUX &= (uint8_t)~0x40;
+ EA = 0;
+ EIE = 0x00;
+ E2IE = 0x00;
+ asm("clr a");
+ asm("mov r0,#0xff");
+ asm("mov @r0,a");
+ asm("dec r0");
+ asm("mov @r0,a");
+ GPIOENABLE = 0;
+ PCON = 0x02 | (PCON & 0x0C);
+ CODECONFIG = 0xD3;
+ asm("ljmp 0xE047");
+ }
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
diff --git a/libs/libmf/source/sleepcont.c b/libs/libmf/source/sleepcont.c
new file mode 100644
index 00000000..6cc34b32
--- /dev/null
+++ b/libs/libmf/source/sleepcont.c
@@ -0,0 +1,96 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+#define REGTABLE_SIG0 0xBE
+#define REGTABLE_SIG1 0x37
+
+/**
+ * \brief enter sleep mode, continue after call
+ *
+ */
+__reentrantb void enter_sleep_cont(void) __reentrant __naked
+{
+ __asm
+ mov dptr,#_RADIOMUX
+ movx a,@dptr
+ anl a,#~0x40
+ movx @dptr,a
+ clr _EA
+ clr a
+ mov _EIE,a
+ mov _E2IE,a
+ mov dptr,#_GPIOENABLE
+ movx @dptr,a
+ mov r0,#0xff
+ mov @r0,#REGTABLE_SIG0
+ dec r0
+ mov @r0,#REGTABLE_SIG1
+ dec r0
+ mov @r0,sp
+ mov a,_PCON
+ anl a,#0x0c
+ orl a,#0x02
+ mov _PCON,a
+ mov _CODECONFIG,#0xd3
+ ljmp 0xe047
+ __endasm;
+}
+
+static void dummy(void) __naked
+{
+ __asm
+ .area CSEG (CODE)
+ .area GSINIT0 (CODE)
+ .area GSINIT1 (CODE)
+ .area GSINIT2 (CODE)
+ .area GSINIT3 (CODE)
+ .area GSINIT4 (CODE)
+ .area GSINIT5 (CODE)
+ .area GSINIT (CODE)
+ .area GSFINAL (CODE)
+
+ .area GSINIT1 (CODE)
+ mov r0,#0xff
+ mov a,_PCON
+ jb acc.6,00001$
+ clr a
+ mov @r0,a
+ dec r0
+ mov @r0,a
+ sjmp 00000$
+00001$:
+ cjne @r0,#REGTABLE_SIG0,00000$
+ dec r0
+ cjne @r0,#REGTABLE_SIG1,00000$
+ dec r0
+ mov sp,@r0
+ ljmp __sdcc_external_startup
+00000$:
+ __endasm;
+}
+
+#elif defined(__ICC8051__)
+
+__reentrantb void enter_sleep_cont(void) __reentrant
+{
+ for (;;) {
+ RADIOMUX &= (uint8_t)~0x40;
+ EA = 0;
+ EIE = 0x00;
+ E2IE = 0x00;
+ asm("mov r0,#0xff");
+ asm("mov @r0,#0xBE");
+ asm("dec r0");
+ asm("mov @r0,#0x37");
+ asm("dec r0");
+ asm("mov @r0,sp");
+ GPIOENABLE = 0;
+ PCON = 0x02 | (PCON & 0x0C);
+ CODECONFIG = 0xD3;
+ asm("ljmp 0xE047");
+ }
+}
+
+#endif
diff --git a/libs/libmf/source/standby.c b/libs/libmf/source/standby.c
new file mode 100644
index 00000000..ebb1e166
--- /dev/null
+++ b/libs/libmf/source/standby.c
@@ -0,0 +1,60 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+/**
+ * \brief enter standby mode
+ *
+ */
+__reentrantb void enter_standby(void) __reentrant __naked
+{
+ __asm
+ mov a,_PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov _PCON,a
+ nop
+ ret
+ nop
+ nop
+ nop
+ nop
+ nop
+ __endasm;
+}
+
+#elif 0 && (defined(__CX51__) || defined(__C51__))
+
+__reentrantb void enter_standby(void) __reentrant
+{
+#pragma asm
+ mov a,_PCON
+ anl a,#0x0C
+ orl a,#0x01
+ mov _PCON,a
+ nop
+ ret
+ nop
+ nop
+ nop
+ nop
+ nop
+#pragma endasm
+}
+
+#else
+
+__reentrantb void enter_standby(void) __reentrant
+{
+ PCON = (PCON & 0x0C) | 0x01;
+ nop();
+ nop();
+ nop();
+ nop();
+ nop();
+ nop();
+ nop();
+}
+
+#endif
diff --git a/libs/libmf/source/uartinit.c b/libs/libmf/source/uartinit.c
new file mode 100644
index 00000000..beeb65ba
--- /dev/null
+++ b/libs/libmf/source/uartinit.c
@@ -0,0 +1,1108 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define UARTS0 UART0S0
+#define UARTS1 UART0S1
+#define UARTS2 UART0S2
+#define UARTS3 UART0S3
+#define UARTS4 UART0S4
+#define UARTS5 UART0S5
+#define USHREG U0SHREG
+#define UMODE U0MODE
+#define UCTRL U0CTRL
+#define USTATUS U0STATUS
+#define _USHREG _U0SHREG
+#define _UMODE _U0MODE
+#define _UCTRL _U0CTRL
+#define _USTATUS _U0STATUS
+#define IRQENA EIE_4
+#define uart_irq_nr 11
+#define uart_vector_addr 0x5B
+#define uart_init uart0_init
+#define uart_stop uart0_stop
+#define uart_iocore uart0_iocore
+#define _uart_iocore _uart0_iocore
+#define uart_irq uart0_irq
+#define uart_poll uart0_poll
+#define uart_rxbufptr uart0_rxbufptr
+#define _uart_rxbufptr _uart0_rxbufptr
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txidle _uart0_txidle
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcountlinear uart0_rxcountlinear
+#define uart_rxcount uart0_rxcount
+#define uart_txbuffersize uart0_txbuffersize
+#define uart_rxbuffersize uart0_rxbuffersize
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define _uart_txpoke _uart0_txpoke
+#define uart_rxbuffer uart0_rxbuffer
+#define _uart_rxbuffer _uart0_rxbuffer
+#define uart_txbuffer uart0_txbuffer
+#define _uart_txbuffer _uart0_txbuffer
+#define _uart_buffer_size _uart0_buffer_size
+#define _uart_buffer_negsize _uart0_buffer_negsize
+#define uart_rxbuffer_size uart0_rxbuffer_size
+#define _uart_rxbuffer_size _uart0_rxbuffer_size
+#define uart_txbuffer_size uart0_txbuffer_size
+#define _uart_txbuffer_size _uart0_txbuffer_size
+#define uart_fiforxwr uart0_fiforxwr
+#define _uart_fiforxwr _uart0_fiforxwr
+#define uart_fiforxrd uart0_fiforxrd
+#define _uart_fiforxrd _uart0_fiforxrd
+#define uart_fifotxwr uart0_fifotxwr
+#define _uart_fifotxwr _uart0_fifotxwr
+#define uart_fifotxrd uart0_fifotxrd
+#define _uart_fifotxrd _uart0_fifotxrd
+#elif UART == 1
+#include "libmfuart1.h"
+#define UARTS0 UART1S0
+#define UARTS1 UART1S1
+#define UARTS2 UART1S2
+#define UARTS3 UART1S3
+#define UARTS4 UART1S4
+#define UARTS5 UART1S5
+#define USHREG U1SHREG
+#define UMODE U1MODE
+#define UCTRL U1CTRL
+#define USTATUS U1STATUS
+#define _USHREG _U1SHREG
+#define _UMODE _U1MODE
+#define _UCTRL _U1CTRL
+#define _USTATUS _U1STATUS
+#define IRQENA EIE_5
+#define uart_irq_nr 12
+#define uart_vector_addr 0x63
+#define uart_init uart1_init
+#define uart_stop uart1_stop
+#define uart_iocore uart1_iocore
+#define _uart_iocore _uart1_iocore
+#define uart_irq uart1_irq
+#define uart_poll uart1_poll
+#define uart_rxbufptr uart1_rxbufptr
+#define _uart_rxbufptr _uart1_rxbufptr
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txidle _uart1_txidle
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcountlinear uart1_rxcountlinear
+#define uart_rxcount uart1_rxcount
+#define uart_txbuffersize uart1_txbuffersize
+#define uart_rxbuffersize uart1_rxbuffersize
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define _uart_txpoke _uart1_txpoke
+#define uart_rxbuffer uart1_rxbuffer
+#define _uart_rxbuffer _uart1_rxbuffer
+#define uart_txbuffer uart1_txbuffer
+#define _uart_txbuffer _uart1_txbuffer
+#define _uart_buffer_size _uart1_buffer_size
+#define _uart_buffer_negsize _uart1_buffer_negsize
+#define uart_rxbuffer_size uart1_rxbuffer_size
+#define _uart_rxbuffer_size _uart1_rxbuffer_size
+#define uart_txbuffer_size uart1_txbuffer_size
+#define _uart_txbuffer_size _uart1_txbuffer_size
+#define uart_fiforxwr uart1_fiforxwr
+#define _uart_fiforxwr _uart1_fiforxwr
+#define uart_fiforxrd uart1_fiforxrd
+#define _uart_fiforxrd _uart1_fiforxrd
+#define uart_fifotxwr uart1_fifotxwr
+#define _uart_fifotxwr _uart1_fifotxwr
+#define uart_fifotxrd uart1_fifotxrd
+#define _uart_fifotxrd _uart1_fifotxrd
+#else
+#error "UART not set"
+#endif
+
+static volatile uint8_t __data uart_fiforxwr;
+static volatile uint8_t __data uart_fiforxrd;
+static volatile uint8_t __data uart_fifotxwr;
+static volatile uint8_t __data uart_fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+#if defined(SDCC)
+
+static void dummy0(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area HOME (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) __interrupt(uart_irq_nr) __naked
+{
+ __asm;
+ push acc
+ push psw
+ push _DPS
+ push dpl
+ push dph
+ push b
+ mov _DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop _DPS
+ pop psw
+ pop acc
+ reti
+ __endasm;
+}
+
+uint8_t uart_poll(void) __reentrant __naked
+{
+ __asm;
+ mov a,#0x80
+ anl a,_IE
+ rl a
+ mov b,a
+ clr _EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov _EA,c
+ mov dpl,a
+ ret
+
+ .area HOME (CODE)
+ .area UARTS0 (CODE)
+ .area UARTS1 (CODE)
+ .area UARTS2 (CODE)
+ .area UARTS3 (CODE)
+ .area UARTS4 (CODE)
+ .area UARTS5 (CODE)
+
+ .area UARTS0 (CODE)
+ __endasm;
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ __asm;
+ ar2=0x02
+ ar3=0x03
+ ar4=0x04
+ ar5=0x05
+ ar6=0x06
+ ar7=0x07
+ ar0=0x00
+ ar1=0x01
+
+ mov a,_USTATUS
+ jnb acc.0,iocnorx
+ mov dptr,#_uart_rxbuffer
+ mov a,_uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ mov a,#_uart_buffer_negsize+3-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fiforxwr
+ jc 00001$
+ mov a,_uart_fiforxwr
+ inc a
+00001$: cjne a,_uart_fiforxrd,00000$
+ anl _UCTRL,#~0x04
+ sjmp iocnorx
+00000$: mov _uart_fiforxwr,a
+ mov a,_USHREG
+ movx @dptr,a
+ orl _UCTRL,#0x04
+ setb _B_1
+iocnorx:
+ mov a,_USTATUS
+ jnb acc.2,iocnotx
+ mov a,_uart_fifotxrd
+ cjne a,_uart_fifotxwr,00000$
+ anl _UCTRL,#~0x08
+ sjmp iocnotx
+00000$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov _USHREG,a
+ mov a,#_uart_buffer_negsize+1-00010$
+ movc a,@a+pc
+00010$: add a,_uart_fifotxrd
+ jc 00001$
+ mov a,_uart_fifotxrd
+ inc a
+00001$: mov _uart_fifotxrd,a
+ orl _UCTRL,#0x08
+ setb _B_2
+iocnotx:
+ ret
+ __endasm;
+}
+
+void uart_rxadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fiforxrd,a
+ orl _UCTRL,#0x04
+00000$: ret
+ __endasm;
+}
+
+void uart_txadvance(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ jz 00000$
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov _uart_fifotxwr,a
+ orl _UCTRL,#0x08
+00000$: ret
+ __endasm;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize+2-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fiforxrd
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_rxbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+ __endasm;
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ mov a,#_uart_buffer_negsize-00003$
+ movc a,@a+pc
+00003$: xch a,dpl
+ add a,_uart_fifotxwr
+ jnc 00002$
+ add a,dpl
+ sjmp 00001$
+00002$: xch a,dpl
+ add a,dpl
+ jc 00001$
+ mov a,dpl
+00001$: mov dptr,#_uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ ret
+
+_uart_buffer_negsize:
+ .area UARTS3 (CODE)
+ __endasm;
+}
+
+uint8_t uart_txfreelinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ jnc 00000$
+ mov a,_uart_fifotxrd
+ add a,#0xff
+ cpl c
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: subb a,_uart_fifotxwr
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_txfree(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fifotxrd
+ setb c
+ subb a,_uart_fifotxwr
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_rxcountlinear(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: clr c
+ subb a,_uart_fiforxrd
+00000$: mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxcount(void) __reentrant __naked
+{
+ __asm;
+ mov a,_uart_fiforxwr
+ clr c
+ subb a,_uart_fiforxrd
+ mov dpl,a
+ jnc 00000$
+ mov a,#_uart_buffer_size+1-00001$
+ movc a,@a+pc
+00001$: add a,dpl
+ mov dpl,a
+00000$: ret
+ __endasm;
+}
+
+uint8_t uart_txbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+uint8_t uart_rxbuffersize(void) __reentrant __naked
+{
+ __asm;
+ mov a,#_uart_buffer_size+1-00000$
+ movc a,@a+pc
+00000$: dec a
+ mov dpl,a
+ ret
+
+_uart_buffer_size:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+uint8_t uart_rxpeek(uint8_t idx) __reentrant __naked
+{
+ idx;
+ __asm;
+ lcall _uart_rxbufptr
+ movx a,@dptr
+ mov dpl,a
+ ret
+ __endasm;
+}
+
+void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+_uart_txpoke_hexentry:
+ lcall _uart_txbufptr
+ mov a,@r0
+ movx @dptr,a
+ pop ar0
+ ret
+ __endasm;
+}
+
+void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant __naked
+{
+ idx;
+ ch;
+ __asm;
+ push ar0
+ mov a,sp
+ add a,#-3
+ mov r0,a
+ mov a,@r0
+ anl a,#0x0F
+ add a,#256-10
+ jnc 00000$
+ add a,#'A-'9-1
+00000$: add a,#10+'0 ; '
+ mov @r0,a
+ ljmp _uart_txpoke_hexentry
+ __endasm;
+}
+
+uint8_t uart_txidle(void) __reentrant __naked
+{
+ __asm;
+ mov a,_UCTRL
+ jnb acc.1,00001$
+ anl a,#0x08
+ jnz 00000$
+ mov a,_USTATUS
+ anl a,#0x40
+ jz 00000$
+00001$: mov dpl,#1
+ ret
+00000$: mov dpl,#0
+ ret
+ __endasm;
+}
+
+static void wtimer_cansleep_dummy(void) __naked
+{
+ __asm
+ .area HOME (CODE)
+ .area WTCANSLP0 (CODE)
+ .area WTCANSLP1 (CODE)
+ .area WTCANSLP2 (CODE)
+
+ .area WTCANSLP1 (CODE)
+ lcall _uart_txidle
+ mov a,dpl
+ jnz 00000$
+ ret
+00000$:
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+static __reentrantb void uart_iocore(void) __reentrant __naked;
+
+void uart_irq(void) interrupt uart_irq_nr
+{
+#pragma asm
+ push acc
+ push psw
+ push DPS
+ push dpl
+ push dph
+ push b
+ mov DPS,#0
+ mov psw,#0
+ lcall _uart_iocore
+ pop b
+ pop dph
+ pop dpl
+ pop DPS
+ pop psw
+ pop acc
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant __naked
+{
+#pragma asm
+ mov a,#0x80
+ anl a,IE
+ rl a
+ mov b,a
+ clr EA
+ lcall _uart_iocore
+ mov a,b
+ clr c
+ rrc a
+ mov EA,c
+ mov r7,a
+#pragma endasm
+}
+
+static __reentrantb void uart_iocore(void) __reentrant __naked
+{
+ uart_rxbuffer[0];
+ uart_rxbuffer_size[0];
+ uart_txbuffer[0];
+ uart_txbuffer_size[0];
+#pragma asm
+;ar2 equ 0x02
+;ar3 equ 0x03
+;ar4 equ 0x04
+;ar5 equ 0x05
+;ar6 equ 0x06
+;ar7 equ 0x07
+;ar0 equ 0x00
+;ar1 equ 0x01
+
+_uart_iocore:
+ mov a,USTATUS
+ jnb acc.0,iocnorx
+ clr a
+ mov dptr,#uart_rxbuffer_size+2
+ movc a,@a+dptr
+ push acc
+ mov dptr,#uart_rxbuffer
+ mov a,uart_fiforxwr
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ pop acc
+ add a,uart_fiforxwr
+ jc ioc1
+ mov a,uart_fiforxwr
+ inc a
+ioc1: cjne a,uart_fiforxrd,ioc0
+ anl UCTRL,#~0x04
+ sjmp iocnorx
+ioc0: mov uart_fiforxwr,a
+ mov a,USHREG
+ movx @dptr,a
+ orl UCTRL,#0x04
+ setb B_1
+iocnorx:
+ mov a,USTATUS
+ jnb acc.2,iocnotx
+ mov a,uart_fifotxrd
+ cjne a,uart_fifotxwr,ioc2
+ anl UCTRL,#~0x08
+ sjmp iocnotx
+ioc2: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ movx a,@dptr
+ mov USHREG,a
+ clr a
+ mov dptr,#uart_txbuffer_size+2
+ movc a,@a+dptr
+ add a,uart_fifotxrd
+ jc ioc3
+ mov a,uart_fifotxrd
+ inc a
+ioc3: mov uart_fifotxrd,a
+ orl UCTRL,#0x08
+ setb B_2
+iocnotx:
+#pragma endasm
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz rxad0
+ add a,uart_fiforxrd
+ jnc rxad2
+ add a,r7
+ sjmp rxad1
+rxad2: xch a,r7
+ add a,r7
+ jc rxad1
+ mov a,r7
+rxad1: mov uart_fiforxrd,a
+ orl UCTRL,#0x04
+rxad0:
+#pragma endasm
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ jz txad0
+ add a,uart_fifotxwr
+ jnc txad2
+ add a,r7
+ sjmp txad1
+txad2: xch a,r7
+ add a,r7
+ jc txad1
+ mov a,r7
+txad1: mov uart_fifotxwr,a
+ orl UCTRL,#0x08
+txad0:
+#pragma endasm
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_rxbufptr:
+ clr a
+ mov dptr,#uart_rxbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fiforxrd
+ jnc rxp2
+ add a,r7
+ sjmp rxp1
+rxp2: xch a,r7
+ add a,r7
+ jc rxp1
+ mov a,r7
+rxp1: mov dptr,#uart_rxbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+_uart_txbufptr:
+ clr a
+ mov dptr,#uart_txbuffer_size+1
+ movc a,@a+dptr
+ xch a,r7
+ add a,uart_fifotxwr
+ jnc txp2
+ add a,r7
+ sjmp txp1
+txp2: xch a,r7
+ add a,r7
+ jc txp1
+ mov a,r7
+txp1: mov dptr,#uart_txbuffer
+ add a,dpl
+ mov r7,a
+ clr a
+ addc a,dph
+ mov r6,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfrl0
+ mov a,uart_fifotxrd
+ add a,#0xff
+ cpl c
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ subb a,uart_fifotxwr
+txfrl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fifotxrd
+ setb c
+ subb a,uart_fifotxwr
+ mov r7,a
+ jnc txfr0
+ clr a
+ mov dptr,#uart_txbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+txfr0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ jnc rxcl0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ clr c
+ subb a,uart_fiforxrd
+rxcl0: mov r7,a
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+#pragma asm
+ mov a,uart_fiforxwr
+ clr c
+ subb a,uart_fiforxrd
+ mov r7,a
+ jnc rxc0
+ clr a
+ mov dptr,#uart_rxbuffer_size
+ movc a,@a+dptr
+ add a,r7
+ mov r7,a
+rxc0:
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ idx;
+#pragma asm
+ lcall _uart_rxbufptr
+ mov dpl,r7
+ mov dph,r6
+ movx a,@dptr
+ mov r7,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+_uart_txpokehex_entry:
+ lcall _uart_txbufptr
+ mov dpl,r7
+ mov dph,r6
+ mov a,r5
+ movx @dptr,a
+#pragma endasm
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ idx;
+ ch;
+#pragma asm
+ mov a,r5
+ anl a,#0x0F
+ add a,#256-10
+ jnc txph0
+ add a,#'A'-'9'-1
+txph0: add a,#10+'0'
+ mov r5,a
+ ljmp _uart_txpokehex_entry
+#pragma endasm
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+#pragma asm
+ mov r7,#0
+ mov a,UCTRL
+ jnb acc.1,txidle
+ anl a,#0x08
+ jnz txnotidle
+ mov a,USTATUS
+ anl a,#0x40
+ jz txnotidle
+txidle:
+ mov r7,#1
+txnotidle:
+#pragma endasm
+}
+
+#elif defined __ICC8051__
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant;
+
+#pragma vector=uart_vector_addr
+__interrupt void uart_irq(void)
+{
+ uint8_t __autodata dpssave = DPS;
+ DPS = 0;
+ uart_iocore();
+ DPS = dpssave;
+}
+
+__reentrantb uint8_t uart_poll(void) __reentrant
+{
+ uint8_t flg;
+ uint8_t irq = IE & 0x80;
+ EA = 0;
+ flg = uart_iocore();
+ IE |= irq;
+ return flg;
+}
+
+static __reentrantb uint8_t uart_iocore(void) __reentrant
+{
+ uint8_t flg = 0;
+ if (USTATUS & 0x01) {
+ uint8_t wp = uart_fiforxwr + 1;
+ uint8_t sz = uart_rxbuffer_size[0];
+ if (wp >= sz)
+ wp -= sz;
+ if (wp != uart_fiforxrd) {
+ uart_rxbuffer[uart_fiforxwr] = USHREG;
+ uart_fiforxwr = wp;
+ UCTRL |= 0x04;
+ flg |= 1;
+ } else {
+ UCTRL &= (uint8_t)~0x04;
+ }
+ }
+ if (USTATUS & 0x04) {
+ if (uart_fifotxrd != uart_fifotxwr) {
+ uint8_t rp = uart_fifotxrd + 1;
+ uint8_t sz = uart_txbuffer_size[0];
+ USHREG = uart_txbuffer[uart_fifotxrd];
+ if (rp >= sz)
+ rp -= sz;
+ uart_fifotxrd = rp;
+ UCTRL |= 0x08;
+ flg |= 2;
+ } else {
+ UCTRL &= (uint8_t)~0x08;
+ }
+ }
+ return flg;
+}
+
+__reentrantb void uart_rxadvance(uint8_t idx) __reentrant
+{
+ uint8_t rd;
+ uint8_t sz;
+ if (!idx)
+ return;
+ rd = uart_fiforxrd;
+ idx += rd;
+ sz = uart_rxbuffer_size[0];
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ uart_fiforxrd = idx;
+ UCTRL |= 0x04;
+}
+
+__reentrantb void uart_txadvance(uint8_t idx) __reentrant
+{
+ uint8_t wr;
+ uint8_t sz;
+ if (!idx)
+ return;
+ wr = uart_fifotxwr;
+ idx += wr;
+ sz = uart_txbuffer_size[0];
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ uart_fifotxwr = idx;
+ UCTRL |= 0x08;
+}
+
+__reentrantb const uint8_t __xdata *uart_rxbufptr(uint8_t idx) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t sz = uart_rxbuffer_size[0];
+ idx += rd;
+ if (idx < rd || idx >= sz)
+ idx -= sz;
+ return &uart_rxbuffer[idx];
+}
+
+__reentrantb uint8_t __xdata *uart_txbufptr(uint8_t idx) __reentrant
+{
+ uint8_t wr = uart_fifotxwr;
+ uint8_t sz = uart_txbuffer_size[0];
+ idx += wr;
+ if (idx < wr || idx >= sz)
+ idx -= sz;
+ return &uart_txbuffer[idx];
+}
+
+__reentrantb uint8_t uart_txfreelinear(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ if (rd <= wr) {
+ uint8_t r = uart_txbuffer_size[0] - wr;
+ if (!rd)
+ --r;
+ return r;
+ }
+ return rd - wr - 1;
+}
+
+__reentrantb uint8_t uart_txfree(void) __reentrant
+{
+ uint8_t rd = uart_fifotxrd;
+ uint8_t wr = uart_fifotxwr;
+ uint8_t r = rd - wr;
+ if (rd <= wr)
+ r += uart_txbuffer_size[0];
+ --r;
+ return r;
+}
+
+__reentrantb uint8_t uart_rxcountlinear(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ if (wr < rd)
+ return uart_rxbuffer_size[0] - rd;
+ return wr - rd;
+}
+
+__reentrantb uint8_t uart_rxcount(void) __reentrant
+{
+ uint8_t rd = uart_fiforxrd;
+ uint8_t wr = uart_fiforxwr;
+ uint8_t r = wr - rd;
+ if (wr < rd)
+ r += uart_rxbuffer_size[0];
+ return r;
+}
+
+__reentrantb uint8_t uart_txbuffersize(void) __reentrant
+{
+ return uart_txbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxbuffersize(void) __reentrant
+{
+ return uart_rxbuffer_size[0]-1;
+}
+
+__reentrantb uint8_t uart_rxpeek(uint8_t idx) __reentrant
+{
+ const uint8_t __xdata *bp = uart_rxbufptr(idx);
+ return *bp;
+}
+
+__reentrantb void uart_txpoke(uint8_t idx, uint8_t ch) __reentrant
+{
+ uint8_t __xdata *bp = uart_txbufptr(idx);
+ *bp = ch;
+}
+
+__reentrantb void uart_txpokehex(uint8_t idx, uint8_t ch) __reentrant
+{
+ ch &= 0x0F;
+ if (ch >= 10)
+ ch += 'A' - '9' - 1;
+ ch += '0';
+ uart_txpoke(idx, ch);
+}
+
+__reentrantb uint8_t uart_txidle(void) __reentrant
+{
+ if (!(UCTRL & 0x02))
+ return 1;
+ if ((UCTRL & 0x08) || !(USTATUS & 0x40))
+ return 0;
+ return 1;
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
+
+void uart_init(uint8_t timernr, uint8_t wl, uint8_t stop)
+{
+ uart_fiforxwr = uart_fiforxrd = uart_fifotxwr = uart_fifotxrd = 0;
+ UMODE = ((timernr + 1) & 3) | ((wl & 7) << 2) | ((stop >= 2) << 5) | 0x40;
+ UCTRL = 0x07;
+ IRQENA = 1;
+}
diff --git a/libs/libmf/source/uartstop.c b/libs/libmf/source/uartstop.c
new file mode 100644
index 00000000..43220204
--- /dev/null
+++ b/libs/libmf/source/uartstop.c
@@ -0,0 +1,140 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#if UART == 0
+#include "libmfuart0.h"
+#define UARTS0 UART0S0
+#define UARTS1 UART0S1
+#define UARTS2 UART0S2
+#define UARTS3 UART0S3
+#define UARTS4 UART0S4
+#define UARTS5 UART0S5
+#define USHREG U0SHREG
+#define UMODE U0MODE
+#define UCTRL U0CTRL
+#define USTATUS U0STATUS
+#define _USHREG _U0SHREG
+#define _UMODE _U0MODE
+#define _UCTRL _U0CTRL
+#define _USTATUS _U0STATUS
+#define IRQENA EIE_4
+#define uart_irq_nr 11
+#define uart_vector_addr 0x5B
+#define uart_init uart0_init
+#define uart_stop uart0_stop
+#define uart_iocore uart0_iocore
+#define _uart_iocore _uart0_iocore
+#define uart_irq uart0_irq
+#define uart_poll uart0_poll
+#define uart_rxbufptr uart0_rxbufptr
+#define _uart_rxbufptr _uart0_rxbufptr
+#define uart_txbufptr uart0_txbufptr
+#define _uart_txbufptr _uart0_txbufptr
+#define uart_txfreelinear uart0_txfreelinear
+#define _uart_txidle _uart0_txidle
+#define uart_txidle uart0_txidle
+#define uart_txfree uart0_txfree
+#define uart_rxcountlinear uart0_rxcountlinear
+#define uart_rxcount uart0_rxcount
+#define uart_txbuffersize uart0_txbuffersize
+#define uart_rxbuffersize uart0_rxbuffersize
+#define uart_wait_txfree uart0_wait_txfree
+#define uart_wait_rxcount uart0_wait_rxcount
+#define uart_rxpeek uart0_rxpeek
+#define uart_txpokehex uart0_txpokehex
+#define uart_txpoke uart0_txpoke
+#define uart_rxadvance uart0_rxadvance
+#define uart_txadvance uart0_txadvance
+#define uart_rx uart0_rx
+#define uart_tx uart0_tx
+#define _uart_txpoke _uart0_txpoke
+#define uart_rxbuffer uart0_rxbuffer
+#define _uart_rxbuffer _uart0_rxbuffer
+#define uart_txbuffer uart0_txbuffer
+#define _uart_txbuffer _uart0_txbuffer
+#define _uart_buffer_size _uart0_buffer_size
+#define _uart_buffer_negsize _uart0_buffer_negsize
+#define uart_rxbuffer_size uart0_rxbuffer_size
+#define _uart_rxbuffer_size _uart0_rxbuffer_size
+#define uart_txbuffer_size uart0_txbuffer_size
+#define _uart_txbuffer_size _uart0_txbuffer_size
+#elif UART == 1
+#include "libmfuart1.h"
+#define UARTS0 UART1S0
+#define UARTS1 UART1S1
+#define UARTS2 UART1S2
+#define UARTS3 UART1S3
+#define UARTS4 UART1S4
+#define UARTS5 UART1S5
+#define USHREG U1SHREG
+#define UMODE U1MODE
+#define UCTRL U1CTRL
+#define USTATUS U1STATUS
+#define _USHREG _U1SHREG
+#define _UMODE _U1MODE
+#define _UCTRL _U1CTRL
+#define _USTATUS _U1STATUS
+#define IRQENA EIE_5
+#define uart_irq_nr 12
+#define uart_vector_addr 0x63
+#define uart_init uart1_init
+#define uart_stop uart1_stop
+#define uart_iocore uart1_iocore
+#define _uart_iocore _uart1_iocore
+#define uart_irq uart1_irq
+#define uart_poll uart1_poll
+#define uart_rxbufptr uart1_rxbufptr
+#define _uart_rxbufptr _uart1_rxbufptr
+#define uart_txbufptr uart1_txbufptr
+#define _uart_txbufptr _uart1_txbufptr
+#define uart_txfreelinear uart1_txfreelinear
+#define _uart_txidle _uart1_txidle
+#define uart_txidle uart1_txidle
+#define uart_txfree uart1_txfree
+#define uart_rxcountlinear uart1_rxcountlinear
+#define uart_rxcount uart1_rxcount
+#define uart_txbuffersize uart1_txbuffersize
+#define uart_rxbuffersize uart1_rxbuffersize
+#define uart_wait_txfree uart1_wait_txfree
+#define uart_wait_rxcount uart1_wait_rxcount
+#define uart_rxpeek uart1_rxpeek
+#define uart_txpokehex uart1_txpokehex
+#define uart_txpoke uart1_txpoke
+#define uart_rxadvance uart1_rxadvance
+#define uart_txadvance uart1_txadvance
+#define uart_rx uart1_rx
+#define uart_tx uart1_tx
+#define _uart_txpoke _uart1_txpoke
+#define uart_rxbuffer uart1_rxbuffer
+#define _uart_rxbuffer _uart1_rxbuffer
+#define uart_txbuffer uart1_txbuffer
+#define _uart_txbuffer _uart1_txbuffer
+#define _uart_buffer_size _uart1_buffer_size
+#define _uart_buffer_negsize _uart1_buffer_negsize
+#define uart_rxbuffer_size uart1_rxbuffer_size
+#define _uart_rxbuffer_size _uart1_rxbuffer_size
+#define uart_txbuffer_size uart1_txbuffer_size
+#define _uart_txbuffer_size _uart1_txbuffer_size
+#else
+#error "UART not set"
+#endif
+
+static volatile uint8_t __data fiforxwr;
+static volatile uint8_t __data fiforxrd;
+static volatile uint8_t __data fifotxwr;
+static volatile uint8_t __data fifotxrd;
+
+extern uint8_t __xdata uart_rxbuffer[];
+extern uint8_t __xdata uart_txbuffer[];
+
+#if !defined(SDCC)
+extern const uint8_t __code uart_rxbuffer_size[];
+extern const uint8_t __code uart_txbuffer_size[];
+#endif
+
+void uart_stop(void)
+{
+ IRQENA = 0;
+ UMODE = 0;
+ UCTRL = 0;
+}
diff --git a/libs/libmf/source/uarttimer.c b/libs/libmf/source/uarttimer.c
new file mode 100644
index 00000000..ca5daa33
--- /dev/null
+++ b/libs/libmf/source/uarttimer.c
@@ -0,0 +1,60 @@
+#include "ax8052.h"
+#include "libmfuart.h"
+
+#if TIMER == 0
+#define uart_timer_baud uart_timer0_baud
+#define TCLKSRC T0CLKSRC
+#define TMODE T0MODE
+#define TPERIOD T0PERIOD
+#elif TIMER == 1
+#define uart_timer_baud uart_timer1_baud
+#define TCLKSRC T1CLKSRC
+#define TMODE T1MODE
+#define TPERIOD T1PERIOD
+#elif TIMER == 2
+#define uart_timer_baud uart_timer2_baud
+#define TCLKSRC T2CLKSRC
+#define TMODE T2MODE
+#define TPERIOD T2PERIOD
+#else
+#error "TIMER not set"
+#endif
+
+__reentrantb void uart_timer_baud(uint8_t clksrc, uint32_t baud, uint32_t clkfreq) __reentrant
+{
+ uint8_t sh = 26;
+ while (sh) {
+ uint8_t bdhi = baud >> 24;
+ if (!bdhi && sh >= 8) {
+ baud <<= 8;
+ sh -= 8;
+ continue;
+ }
+ if (!(bdhi & 0xF0) && sh >= 4) {
+ baud <<= 4;
+ sh -= 4;
+ continue;
+ }
+ if (!(bdhi & 0xC0) && sh >= 2) {
+ baud <<= 2;
+ sh -= 2;
+ continue;
+ }
+ if (!(bdhi & 0x80)) {
+ baud <<= 1;
+ --sh;
+ continue;
+ }
+ break;
+ }
+ clkfreq >>= sh;
+ baud /= clkfreq;
+ sh = 0x38;
+ while (baud >= 16384 && (sh & 0xF0)) {
+ baud >>= 1;
+ sh -= 8;
+ }
+ TCLKSRC = sh | (clksrc & 7);
+ TMODE = 0x04;
+ TPERIOD = baud;
+}
diff --git a/libs/libmf/source/wrnum.h b/libs/libmf/source/wrnum.h
new file mode 100644
index 00000000..9b7bf629
--- /dev/null
+++ b/libs/libmf/source/wrnum.h
@@ -0,0 +1,20 @@
+#ifndef WRNUM_H
+#define WRNUM_H
+
+#include "libmftypes.h"
+
+#define WRNUM_MASK (WRNUM_SIGNED | WRNUM_PLUS | WRNUM_ZEROPLUS | WRNUM_PADZERO | WRNUM_TSDSEP | WRNUM_LCHEX)
+#define WRNUM_DIGCONT 0x80
+#define WRNUM_DIGSET 0x40
+
+#if defined SDCC
+#pragma callee_saves libmf_num16_digit,libmf_num32_digit
+
+extern __reentrantb uint32_t libmf_num32_digit(uint32_t v, uint8_t __auto *dp) __reentrant;
+#else
+extern uint32_t libmf_num32_digit(uint32_t v, uint8_t __auto *dp);
+#endif
+
+extern __reentrantb uint16_t libmf_num16_digit(uint16_t v, uint8_t __auto *dp) __reentrant;
+
+#endif /* WRNUM_H */
diff --git a/libs/libmf/source/wrnum16.c b/libs/libmf/source/wrnum16.c
new file mode 100644
index 00000000..34b0ad22
--- /dev/null
+++ b/libs/libmf/source/wrnum16.c
@@ -0,0 +1,123 @@
+#include "wrnum.h"
+
+static const uint16_t __code subtbl[4*4] = {
+ -80, -40, -20, -10,
+ -800, -400, -200, -100,
+ -8000, -4000, -2000, -1000,
+ 0, -40000, -20000, -10000
+};
+
+#if defined(SDCC)
+
+__reentrantb uint16_t libmf_num16_digit(uint16_t val, uint8_t __auto *dp) __reentrant __naked
+{
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ push ar3
+ push ar6
+ push ar7
+ push ar0
+ push ar1
+ mov a,sp
+ add a,#-7
+ mov r0,a
+ mov a,@r0
+ mov r0,a
+ mov a,@r0
+ add a,#-6
+ jnc 00001$
+ clr a
+ mov @r0,a
+ sjmp 00000$
+00001$: add a,#4
+ jc 00002$
+ mov a,dpl
+ mov @r0,a
+ mov dptr,#0
+ sjmp 00000$
+00002$: swap a
+ rr a
+ mov r7,dpl
+ mov r6,dph
+ mov dptr,#_subtbl
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ clr a
+ mov @r0,a
+ mov a,#8
+00010$: mov r1,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ add a,r7
+ mov r3,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ addc a,r6
+ jnc 00011$
+ mov r6,a
+ mov a,r3
+ mov r7,a
+ mov a,@r0
+ orl a,r1
+ mov @r0,a
+00011$: mov a,r1
+ clr c
+ rrc a
+ jnz 00010$
+ mov dpl,r7
+ mov dph,r6
+00000$: pop ar1
+ pop ar0
+ pop ar7
+ pop ar6
+ pop ar3
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb uint16_t libmf_num16_digit(uint16_t val, uint8_t __auto *dp) __reentrant
+{
+ const uint16_t __code *s;
+ uint8_t cnt, r;
+ {
+ uint8_t i = *dp;
+ if (i > 5) {
+ *dp = 0;
+ return val;
+ }
+ i -= 2;
+ if (i >= 4) {
+ *dp = val;
+ return 0;
+ }
+ s = &subtbl[4*i];
+ }
+ cnt = 8;
+ r = 0;
+ do {
+ uint16_t rv = val + *s++;
+ if (rv < val) {
+ val = rv;
+ r |= cnt;
+ }
+ cnt >>= 1;
+ } while (cnt);
+ *dp = r;
+ return val;
+}
+
+#endif
diff --git a/libs/libmf/source/wrnum32.c b/libs/libmf/source/wrnum32.c
new file mode 100644
index 00000000..d554889b
--- /dev/null
+++ b/libs/libmf/source/wrnum32.c
@@ -0,0 +1,161 @@
+#include "wrnum.h"
+
+#if defined(SDCC)
+
+static const uint32_t __code subtbl[9*4] = {
+ -80, -40, -20, -10,
+ -800, -400, -200, -100,
+ -8000, -4000, -2000, -1000,
+ -80000, -40000, -20000, -10000,
+ -800000, -400000, -200000, -100000,
+ -8000000, -4000000, -2000000, -1000000,
+ -80000000, -40000000, -20000000, -10000000,
+ -800000000, -400000000, -200000000, -100000000,
+ 0, -4000000000, -2000000000, -1000000000
+};
+
+__reentrantb uint32_t libmf_num32_digit(uint32_t val, uint8_t __auto *dp) __reentrant __naked
+{
+ __asm;
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+ push ar2
+ push ar3
+ push ar4
+ push ar5
+ push ar6
+ push ar7
+ push ar0
+ push ar1
+ mov r4,a
+ mov a,sp
+ add a,#-10
+ mov r0,a
+ mov a,@r0
+ mov r0,a
+ mov a,@r0
+ add a,#-11
+ jnc 00001$
+ clr a
+ mov @r0,a
+ mov a,r4
+ sjmp 00000$
+00001$: add a,#9
+ jc 00002$
+ mov a,dpl
+ mov @r0,a
+ clr a
+ mov b,a
+ mov dptr,#0
+ sjmp 00000$
+00002$: swap a
+ mov r7,dpl
+ mov r6,dph
+ mov r5,b
+ mov dptr,#_subtbl
+ add a,dpl
+ mov dpl,a
+ clr a
+ addc a,dph
+ mov dph,a
+ clr a
+ mov @r0,a
+ mov a,#8
+00010$: mov r1,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ add a,r7
+ mov r3,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ addc a,r6
+ mov r2,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ addc a,r5
+ mov b,a
+ clr a
+ movc a,@a+dptr
+ inc dptr
+ addc a,r4
+ jnc 00011$
+ mov r4,a
+ mov a,b
+ mov r5,a
+ mov a,r2
+ mov r6,a
+ mov a,r3
+ mov r7,a
+ mov a,@r0
+ orl a,r1
+ mov @r0,a
+00011$: mov a,r1
+ clr c
+ rrc a
+ jnz 00010$
+ mov dpl,r7
+ mov dph,r6
+ mov b,r5
+ mov a,r4
+00000$: pop ar1
+ pop ar0
+ pop ar7
+ pop ar6
+ pop ar5
+ pop ar4
+ pop ar3
+ pop ar2
+ ret
+ __endasm;
+}
+
+#else
+
+static const uint32_t __code subtbl[6*4] = {
+ -80000, -40000, -20000, -10000,
+ -800000, -400000, -200000, -100000,
+ -8000000, -4000000, -2000000, -1000000,
+ -80000000, -40000000, -20000000, -10000000,
+ -800000000, -400000000, -200000000, -100000000,
+ 0, -4000000000, -2000000000, -1000000000
+};
+
+uint32_t libmf_num32_digit(uint32_t val, uint8_t __auto *dp)
+{
+ const uint32_t __code *s;
+ uint8_t __autodata cnt, r;
+ {
+ uint8_t __autodata i = *dp;
+ if (i > 10) {
+ *dp = 0;
+ return val;
+ }
+ i -= 5;
+ if (i >= 6)
+ return libmf_num16_digit(val, dp);
+ s = &subtbl[4*i];
+ }
+ cnt = 8;
+ r = 0;
+ do {
+ uint32_t __autodata rv = val + *s++;
+ if (rv < val) {
+ val = rv;
+ r |= cnt;
+ }
+ cnt >>= 1;
+ } while (cnt);
+ *dp = r;
+ return val;
+}
+
+#endif
diff --git a/libs/libmf/source/wt01rem.c b/libs/libmf/source/wt01rem.c
new file mode 100644
index 00000000..5ecaded0
--- /dev/null
+++ b/libs/libmf/source/wt01rem.c
@@ -0,0 +1,15 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint8_t wtimer_remove(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ ret = wtimer_removecb_core((struct wtimer_callback __xdata *)desc);
+ ret += wtimer0_removecb_core(desc);
+ ret += wtimer1_removecb_core(desc);
+ IE |= iesave;
+ return ret;
+}
diff --git a/libs/libmf/source/wt0adda.c b/libs/libmf/source/wt0adda.c
new file mode 100644
index 00000000..2a48fb02
--- /dev/null
+++ b/libs/libmf/source/wt0adda.c
@@ -0,0 +1,12 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb void wtimer0_addabsolute(struct wtimer_desc __xdata *desc) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer0_update();
+ wtimer0_addcore(desc);
+ wtimer0_schedq();
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/wt0addr.c b/libs/libmf/source/wt0addr.c
new file mode 100644
index 00000000..ac30bcb1
--- /dev/null
+++ b/libs/libmf/source/wt0addr.c
@@ -0,0 +1,75 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+#if defined(WTIMER_USEASM) && defined(SDCC)
+
+__reentrantb void wtimer0_addrelative(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ mov a,_IE
+ anl a,#0x80
+ push acc
+ clr _EA
+ push dpl
+ push dph
+ lcall _wtimer0_update
+ ;; desc->time += wtimer_state[0].time.cur
+ mov dptr,#(_wtimer_state + 0x0000)
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ pop dph
+ pop dpl
+ mov r6,dpl
+ mov r7,dph
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ movx a,@dptr
+ add a,r2
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r3
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r4
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r5
+ movx @dptr,a
+ mov dpl,r6
+ mov dph,r7
+ lcall _wtimer0_addcore
+ lcall _wtimer0_schedq
+ pop acc
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void wtimer0_addrelative(struct wtimer_desc __xdata *desc) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer0_update();
+ desc->time += wtimer_state[0].time.cur;
+ wtimer0_addcore(desc);
+ wtimer0_schedq();
+ IE |= iesave;
+}
+
+#endif
diff --git a/libs/libmf/source/wt0curt.c b/libs/libmf/source/wt0curt.c
new file mode 100644
index 00000000..eff2afd9
--- /dev/null
+++ b/libs/libmf/source/wt0curt.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint32_t wtimer0_curtime(void) __reentrant
+{
+ uint32_t r;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer0_update();
+ r = wtimer_state[0].time.cur;
+ IE |= iesave;
+ return r;
+}
diff --git a/libs/libmf/source/wt0rem.c b/libs/libmf/source/wt0rem.c
new file mode 100644
index 00000000..01108fd4
--- /dev/null
+++ b/libs/libmf/source/wt0rem.c
@@ -0,0 +1,14 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint8_t wtimer0_remove(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ ret = wtimer_removecb_core((struct wtimer_callback __xdata *)desc);
+ ret += wtimer0_removecb_core(desc);
+ IE |= iesave;
+ return ret;
+}
diff --git a/libs/libmf/source/wt0setcfg.c b/libs/libmf/source/wt0setcfg.c
new file mode 100644
index 00000000..e4368c88
--- /dev/null
+++ b/libs/libmf/source/wt0setcfg.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb void wtimer0_setconfig(uint8_t cfg) __reentrant
+{
+ if (!((WTCFGA ^ cfg) & 0x3F))
+ return;
+ cfg &= 0x3F;
+ WTCFGA |= 0x04;
+ WTCFGA = 0x0F;
+ WTCFGA &= cfg | 0xFC;
+ WTCFGA = cfg;
+}
diff --git a/libs/libmf/source/wt1adda.c b/libs/libmf/source/wt1adda.c
new file mode 100644
index 00000000..7e1da834
--- /dev/null
+++ b/libs/libmf/source/wt1adda.c
@@ -0,0 +1,12 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb void wtimer1_addabsolute(struct wtimer_desc __xdata *desc) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer1_update();
+ wtimer1_addcore(desc);
+ wtimer1_schedq();
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/wt1addr.c b/libs/libmf/source/wt1addr.c
new file mode 100644
index 00000000..9cc9f56e
--- /dev/null
+++ b/libs/libmf/source/wt1addr.c
@@ -0,0 +1,75 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+#if defined(WTIMER_USEASM) && defined(SDCC)
+
+__reentrantb void wtimer1_addrelative(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ mov a,_IE
+ anl a,#0x80
+ push acc
+ clr _EA
+ push dpl
+ push dph
+ lcall _wtimer1_update
+ ;; desc->time += wtimer_state[1].time.cur
+ mov dptr,#(_wtimer_state + 0x0008)
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ pop dph
+ pop dpl
+ mov r6,dpl
+ mov r7,dph
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ movx a,@dptr
+ add a,r2
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r3
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r4
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r5
+ movx @dptr,a
+ mov dpl,r6
+ mov dph,r7
+ lcall _wtimer1_addcore
+ lcall _wtimer1_schedq
+ pop acc
+ orl _IE,a
+ ret
+ __endasm;
+}
+
+#else
+
+__reentrantb void wtimer1_addrelative(struct wtimer_desc __xdata *desc) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer1_update();
+ desc->time += wtimer_state[1].time.cur;
+ wtimer1_addcore(desc);
+ wtimer1_schedq();
+ IE |= iesave;
+}
+
+#endif
diff --git a/libs/libmf/source/wt1curt.c b/libs/libmf/source/wt1curt.c
new file mode 100644
index 00000000..586e7523
--- /dev/null
+++ b/libs/libmf/source/wt1curt.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint32_t wtimer1_curtime(void) __reentrant
+{
+ uint32_t r;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer1_update();
+ r = wtimer_state[1].time.cur;
+ IE |= iesave;
+ return r;
+}
diff --git a/libs/libmf/source/wt1rem.c b/libs/libmf/source/wt1rem.c
new file mode 100644
index 00000000..f62ae3c6
--- /dev/null
+++ b/libs/libmf/source/wt1rem.c
@@ -0,0 +1,14 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint8_t wtimer1_remove(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ ret = wtimer_removecb_core((struct wtimer_callback __xdata *)desc);
+ ret += wtimer1_removecb_core(desc);
+ IE |= iesave;
+ return ret;
+}
diff --git a/libs/libmf/source/wt1setcfg.c b/libs/libmf/source/wt1setcfg.c
new file mode 100644
index 00000000..fa6ad8f8
--- /dev/null
+++ b/libs/libmf/source/wt1setcfg.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb void wtimer1_setconfig(uint8_t cfg) __reentrant
+{
+ if (!((WTCFGB ^ cfg) & 0x3F))
+ return;
+ cfg &= 0x3F;
+ WTCFGB |= 0x04;
+ WTCFGB = 0x0F;
+ WTCFGB &= cfg | 0xFC;
+ WTCFGB = cfg;
+}
diff --git a/libs/libmf/source/wtcbadd.c b/libs/libmf/source/wtcbadd.c
new file mode 100644
index 00000000..68dabf01
--- /dev/null
+++ b/libs/libmf/source/wtcbadd.c
@@ -0,0 +1,10 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb void wtimer_add_callback(struct wtimer_callback __xdata *desc) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ wtimer_addcb_core(desc);
+ IE |= iesave;
+}
diff --git a/libs/libmf/source/wtcbrem.c b/libs/libmf/source/wtcbrem.c
new file mode 100644
index 00000000..dd6f419c
--- /dev/null
+++ b/libs/libmf/source/wtcbrem.c
@@ -0,0 +1,13 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+__reentrantb uint8_t wtimer_remove_callback(struct wtimer_callback __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret;
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ ret = wtimer_removecb_core(desc);
+ IE |= iesave;
+ return ret;
+}
diff --git a/libs/libmf/source/wtimer.c b/libs/libmf/source/wtimer.c
new file mode 100644
index 00000000..0c5903c6
--- /dev/null
+++ b/libs/libmf/source/wtimer.c
@@ -0,0 +1,1021 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+#define WTIMER0_MARGIN 0x1000
+#define WTIMER1_MARGIN 0x1000
+#define WTIMER_LPXOSC_SLEEP 8
+
+struct wtimer_state __xdata wtimer_state[2];
+struct wtimer_callback __xdata * __xdata wtimer_pending;
+
+#if defined(SDCC)
+
+static void dummy0(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ __endasm;
+}
+
+void wtimer_irq(void) __interrupt(1)
+{
+ uint8_t __autodata dpssave = DPS;
+ uint8_t __autodata s = WTSTAT;
+ DPS = 0;
+ if (s & 0x01) {
+ wtimer0_update();
+ wtimer0_schedq();
+ s |= WTSTAT;
+ }
+ if (s & 0x20) {
+ wtimer1_update();
+ wtimer1_schedq();
+ WTSTAT;
+ }
+ DPS = dpssave;
+}
+
+static void dummy1(void) __naked
+{
+ __asm;
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#elif defined __CX51__ || defined __C51__
+
+void wtimer_irq(void) interrupt 1
+{
+ uint8_t __autodata dpssave = DPS;
+ uint8_t __autodata s = WTSTAT;
+ DPS = 0;
+ if (s & 0x01) {
+ wtimer0_update();
+ wtimer0_schedq();
+ s |= WTSTAT;
+ }
+ if (s & 0x20) {
+ wtimer1_update();
+ wtimer1_schedq();
+ WTSTAT;
+ }
+ DPS = dpssave;
+}
+
+#elif defined __ICC8051__
+
+#pragma vector=0x0b
+__interrupt void wtimer_irq(void)
+{
+ uint8_t __autodata dpssave = DPS;
+ uint8_t __autodata s = WTSTAT;
+ DPS = 0;
+ if (s & 0x01) {
+ wtimer0_update();
+ wtimer0_schedq();
+ s |= WTSTAT;
+ }
+ if (s & 0x20) {
+ wtimer1_update();
+ wtimer1_schedq();
+ WTSTAT;
+ }
+ DPS = dpssave;
+}
+
+#else
+
+#error "Compiler unsupported"
+
+#endif
+
+static __reentrantb void wtimer_doinit(uint8_t wakeup) __reentrant
+{
+ IE_1 = 0;
+ wtimer_pending = WTIMER_NULLCB;
+ WTIRQEN = 0x21;
+ if (wakeup) {
+ if (SILICONREV == 0x8E && !(DBGLNKSTAT & 0x10))
+ wtimer_state[0].time.ref = 0;
+ wtimer0_update();
+ } else {
+ wtimer_state[0].time.ref = WTCNTA0;
+ wtimer_state[0].time.ref |= ((uint16_t)WTCNTR1) << 8;
+ wtimer_state[0].time.cur = 0;
+ wtimer_state[0].queue = WTIMER_NULLDESC;
+ }
+ wtimer_state[1].time.ref = WTCNTB0;
+ wtimer_state[1].time.ref |= ((uint16_t)WTCNTR1) << 8;
+ wtimer_state[1].time.cur = 0;
+ wtimer_state[1].queue = WTIMER_NULLDESC;
+ wtimer0_schedq();
+ wtimer1_schedq();
+ IE_1 = 1;
+}
+
+__reentrantb void wtimer_init(void) __reentrant
+{
+ wtimer_doinit(PCON & 0x40);
+}
+
+__reentrantb void wtimer_init_deepsleep(void) __reentrant
+{
+ wtimer_doinit(0);
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer_addcb_core(struct wtimer_callback __xdata *desc) __reentrant
+{
+ struct wtimer_callback __xdata *d = WTIMER_CBPTR(wtimer_pending);
+ for (;;) {
+ struct wtimer_callback __xdata *dn = d->next;
+ if (dn == WTIMER_NULLCB)
+ break;
+ d = dn;
+ }
+ d->next = (struct wtimer_callback __xdata *)desc;
+ desc->next = WTIMER_NULLCB;
+}
+
+#if defined(WTIMER_USEASM) && defined(SDCC)
+
+static void dummy2(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_schedq(void) __reentrant
+{
+ __asm
+ ;; check wtimer_state[0].queue != WTIMER_NULL
+ mov dptr,#(_wtimer_state + 0x0006)
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ cjne r6,#(WTIMER_NULL & 0xFF),00000$
+ cjne r7,#(WTIMER_NULL >> 8),00000$
+00001$:
+ ;; WTEVTA = wtimer_state[0].time.ref + (0x10000-WTIMER0_MARGIN)
+ mov dptr,#(_wtimer_state + 0x0004)
+ movx a,@dptr
+ add a,#((0x10000-WTIMER0_MARGIN) & 0xFF)
+ mov _WTEVTA0,a
+ inc dptr
+ movx a,@dptr
+ addc a,#((0x10000-WTIMER0_MARGIN) >> 8)
+ mov _WTEVTA1,a
+ ret
+00000$:
+ ;; R5:R4:R3:R2 = wtimer_state[0].time.cur - wtimer_state[0].queue->time;
+ mov dpl,r6
+ mov dph,r7
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ mov dptr,#(_wtimer_state + 0x0000)
+ movx a,@dptr
+ clr c
+ subb a,r2
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ subb a,r3
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ subb a,r4
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ subb a,r5
+ mov r5,a
+ jb acc.7,00002$
+ ;; case R5:R4:R3:R2 >= 0
+ ;; wtimer_state[0].queue = wtimer_state[0].queue->next
+ mov dpl,r6
+ mov dph,r7
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ mov dptr,#(_wtimer_state + 0x0006)
+ mov a,r2
+ movx @dptr,a
+ inc dptr
+ mov a,r3
+ movx @dptr,a
+ ;; wtimer_addcb_core(old wtimer_state[0].queue)
+ mov dpl,r6
+ mov dph,r7
+ lcall _wtimer_addcb_core
+ sjmp _wtimer0_schedq
+00002$:
+ ;; check R5:R4:R3:R2 < -(0x10000-WTIMER0_MARGIN)
+ ;; equivalent: (R5:R4:R3:R2 + (0x10000-WTIMER0_MARGIN)) < 0
+ mov a,r2
+ add a,#((0x10000-WTIMER0_MARGIN) & 0xFF)
+ mov a,r3
+ addc a,#((0x10000-WTIMER0_MARGIN) >> 8)
+ clr a
+ addc a,r4
+ clr a
+ addc a,r5
+ jb acc.7,00001$
+ ;; WTEVTA = wtimer_state[0].time.ref - R3:R2
+ mov dptr,#(_wtimer_state + 0x0004)
+ movx a,@dptr
+ inc dptr
+ clr c
+ subb a,r2
+ mov _WTEVTA0,a
+ movx a,@dptr
+ subb a,r3
+ mov _WTEVTA1,a
+ ret
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_update(void) __reentrant __naked
+{
+ __asm
+ mov r2,_WTCNTA0
+ mov r3,_WTCNTR1
+ mov dptr,#(_wtimer_state + 0x0004)
+ movx a,@dptr
+ xch a,r2
+ movx @dptr,a
+ inc dptr
+ clr c
+ subb a,r2
+ mov r2,a
+ movx a,@dptr
+ xch a,r3
+ movx @dptr,a
+ subb a,r3
+ mov r3,a
+ orl a,ar2
+ jz 00000$
+ mov dptr,#(_wtimer_state + 0x0000)
+ movx a,@dptr
+ add a,r2
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r3
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,#0
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,#0
+ movx @dptr,a
+00000$: ret
+ __endasm;
+}
+
+static void dummy3(void) __naked
+{
+ __asm;
+ .area CSEG (CODE)
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_addcore(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ ;; R5:R4 = &wtimer_state[0].queue
+ mov r4,#(_wtimer_state + 0x0006)
+ mov r5,#((_wtimer_state + 0x0006) >> 8)
+_wtimer_addcore:
+ ;; R3:R2 = desc
+ mov r2,dpl
+ mov r3,dph
+00000$:
+ ;; R7:R6 = R5:R4->next
+ mov dpl,r4
+ mov dph,r5
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ ;; check R7:R6 != WTIMER_NULL
+ cjne r6,#(WTIMER_NULL & 0xFF),00002$
+ cjne r7,#(WTIMER_NULL >> 8),00002$
+00001$:
+ ;; R3:R2->next = R7:R6
+ mov dpl,r2
+ mov dph,r3
+ mov a,r6
+ movx @dptr,a
+ inc dptr
+ mov a,r7
+ movx @dptr,a
+ ;; R5:R4->next = R3:R2
+ mov dpl,r4
+ mov dph,r5
+ mov a,r2
+ movx @dptr,a
+ inc dptr
+ mov a,r3
+ movx @dptr,a
+ ret
+00002$:
+ ;; A.7 = sign (R3:R2->time - R7:R6->time)
+ push ar6
+ push ar7
+ mov dpl,r6
+ mov dph,r7
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ movx a,@dptr
+ mov r0,a
+ inc dptr
+ movx a,@dptr
+ mov r1,a
+ inc dptr
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ mov dpl,r2
+ mov dph,r3
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ clr c
+ movx a,@dptr
+ subb a,r0
+ inc dptr
+ movx a,@dptr
+ subb a,r1
+ inc dptr
+ movx a,@dptr
+ subb a,r6
+ inc dptr
+ movx a,@dptr
+ subb a,r7
+ jb acc.7,00003$
+ pop ar5
+ pop ar4
+ sjmp 00000$
+00003$:
+ pop ar7
+ pop ar6
+ sjmp 00001$
+ __endasm;
+}
+
+static void dummy4(void) __naked
+{
+ __asm;
+ .area HOME (CODE)
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_schedq(void) __reentrant
+{
+ __asm
+ ;; check wtimer_state[1].queue != WTIMER_NULL
+ mov dptr,#(_wtimer_state + 0x000E)
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ cjne r6,#(WTIMER_NULL & 0xFF),00000$
+ cjne r7,#(WTIMER_NULL >> 8),00000$
+00001$:
+ ;; WTEVTB = wtimer_state[1].time.ref + (0x10000-WTIMER1_MARGIN)
+ mov dptr,#(_wtimer_state + 0x000C)
+ movx a,@dptr
+ add a,#((0x10000-WTIMER1_MARGIN) & 0xFF)
+ mov _WTEVTB0,a
+ inc dptr
+ movx a,@dptr
+ addc a,#((0x10000-WTIMER1_MARGIN) >> 8)
+ mov _WTEVTB1,a
+ ret
+00000$:
+ ;; R5:R4:R3:R2 = wtimer_state[1].time.cur - wtimer_state[1].queue->time;
+ mov dpl,r6
+ mov dph,r7
+ inc dptr
+ inc dptr
+ inc dptr
+ inc dptr
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ mov r5,a
+ mov dptr,#(_wtimer_state + 0x0008)
+ movx a,@dptr
+ clr c
+ subb a,r2
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ subb a,r3
+ mov r3,a
+ inc dptr
+ movx a,@dptr
+ subb a,r4
+ mov r4,a
+ inc dptr
+ movx a,@dptr
+ subb a,r5
+ mov r5,a
+ jb acc.7,00002$
+ ;; case R5:R4:R3:R2 >= 0
+ ;; wtimer_state[1].queue = wtimer_state[1].queue->next
+ mov dpl,r6
+ mov dph,r7
+ movx a,@dptr
+ mov r2,a
+ inc dptr
+ movx a,@dptr
+ mov r3,a
+ mov dptr,#(_wtimer_state + 0x000E)
+ mov a,r2
+ movx @dptr,a
+ inc dptr
+ mov a,r3
+ movx @dptr,a
+ ;; wtimer_addcb_core(old wtimer_state[1].queue)
+ mov dpl,r6
+ mov dph,r7
+ lcall _wtimer_addcb_core
+ sjmp _wtimer1_schedq
+00002$:
+ ;; check R5:R4:R3:R2 < -(0x10000-WTIMER1_MARGIN)
+ ;; equivalent: (R5:R4:R3:R2 + (0x10000-WTIMER1_MARGIN)) < 0
+ mov a,r2
+ add a,#((0x10000-WTIMER1_MARGIN) & 0xFF)
+ mov a,r3
+ addc a,#((0x10000-WTIMER1_MARGIN) >> 8)
+ clr a
+ addc a,r4
+ clr a
+ addc a,r5
+ jb acc.7,00001$
+ ;; WTEVTB = wtimer_state[1].time.ref - R3:R2
+ mov dptr,#(_wtimer_state + 0x000C)
+ movx a,@dptr
+ inc dptr
+ clr c
+ subb a,r2
+ mov _WTEVTB0,a
+ movx a,@dptr
+ subb a,r3
+ mov _WTEVTB1,a
+ ret
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_update(void) __reentrant __naked
+{
+ __asm
+ mov r2,_WTCNTB0
+ mov r3,_WTCNTR1
+ mov dptr,#(_wtimer_state + 0x000C)
+ movx a,@dptr
+ xch a,r2
+ movx @dptr,a
+ inc dptr
+ clr c
+ subb a,r2
+ mov r2,a
+ movx a,@dptr
+ xch a,r3
+ movx @dptr,a
+ subb a,r3
+ mov r3,a
+ orl a,ar2
+ jz 00000$
+ mov dptr,#(_wtimer_state + 0x0008)
+ movx a,@dptr
+ add a,r2
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r3
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,#0
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,#0
+ movx @dptr,a
+00000$: ret
+ __endasm;
+}
+
+static void dummy5(void) __naked
+{
+ __asm;
+ .area CSEG (CODE)
+ __endasm;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_addcore(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ ;; R5:R4 = &wtimer_state[1].queue
+ mov r4,#(_wtimer_state + 0x000E)
+ mov r5,#((_wtimer_state + 0x000E) >> 8)
+ ljmp _wtimer_addcore
+ __endasm;
+}
+
+static void wtimer_preparesleep(void) __naked
+{
+ __asm
+ mov _WTCFGB,#0x0F
+ mov _WTIRQEN,#0x01
+ mov dptr,#_SILICONREV
+ movx a,@dptr
+ cjne a,#0x8E,00000$
+ ;; R3:R2 = WTEVTA - wtimer_state[0].time.ref
+ ;; wtimer_state[0].time.ref = WTEVTA
+ mov dptr,#(_wtimer_state + 0x0004)
+ mov r2,_WTEVTA0
+ movx a,@dptr
+ xch a,r2
+ movx @dptr,a
+ clr c
+ subb a,r2
+ mov r2,a
+ inc dptr
+ mov r3,_WTEVTA1
+ movx a,@dptr
+ xch a,r3
+ movx @dptr,a
+ subb a,r3
+ mov r3,a
+ mov r4,#0
+ ;; check for LPXOSC source
+ mov a,_DBGLNKSTAT
+ anl a,#0x10
+ jnz 00001$
+ mov a,_WTCFGA
+ anl a,#0x07
+ cjne a,#CLKSRC_LPXOSC,00001$
+ mov a,_WTCFGA
+ swap a
+ rl a
+ anl a,#0x07
+ inc a
+ mov r4,a
+ mov a,#((WTIMER_LPXOSC_SLEEP) << 2)
+00002$:
+ clr c
+ rrc a
+ djnz r4,00002$
+ add a,r2
+ mov r2,a
+ clr a
+ addc a,r3
+ mov r3,a
+ clr a
+ addc a,r4
+ mov r4,a
+00001$:
+ ;; wtimer_state[0].time.cur += R4:R3:R2
+ mov dptr,#(_wtimer_state + 0x0000)
+ movx a,@dptr
+ add a,r2
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r3
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,r4
+ movx @dptr,a
+ inc dptr
+ movx a,@dptr
+ addc a,#0
+ movx @dptr,a
+00000$:
+ ret
+ __endasm;
+}
+
+static uint8_t wtimer_checkexpired(void) __naked
+{
+ __asm
+ ;; R3:R2 = WTEVTA1:WTEVTA0 - WTCNTR1:WTCNTA0 - 1
+ setb c
+ mov a,_WTEVTA0
+ subb a,_WTCNTA0
+ mov r2,a
+ mov a,_WTEVTA1
+ subb a,_WTCNTR1
+ mov r3,a
+ ;; R3:R2 + WTIMER0_MARGIN
+ .if (WTIMER0_MARGIN & 0xFF)
+ mov a,#(WTIMER0_MARGIN & 0xFF)
+ add a,r2
+ mov a,#(WTIMER0_MARGIN >> 8)
+ addc a,r3
+ .else
+ mov a,#(WTIMER0_MARGIN >> 8)
+ add a,r3
+ .endif
+ jc 00000$
+ ;; R3:R2 = WTEVTB1:WTEVTB0 - WTCNTR1:WTCNTB0 - 1
+ setb c
+ mov a,_WTEVTB0
+ subb a,_WTCNTB0
+ mov r2,a
+ mov a,_WTEVTB1
+ subb a,_WTCNTR1
+ mov r3,a
+ ;; R3:R2 + WTIMER1_MARGIN
+ .if (WTIMER1_MARGIN & 0xFF)
+ mov a,#(WTIMER1_MARGIN & 0xFF)
+ add a,r2
+ mov a,#(WTIMER1_MARGIN >> 8)
+ addc a,r3
+ .else
+ mov a,#(WTIMER1_MARGIN >> 8)
+ add a,r3
+ .endif
+ jc 00000$
+ ;; check WTSTAT & 0x21
+ mov a,_WTSTAT
+ anl a,#0x21
+ jnz 00000$
+ mov dpl,a
+ ret
+00000$:
+ mov dpl,#1
+ ret
+ __endasm;
+}
+
+#else
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_schedq(void) __reentrant
+{
+ while (wtimer_state[0].queue != WTIMER_NULLDESC) {
+ int32_t __autodata td = wtimer_state[0].time.cur - wtimer_state[0].queue->time;
+ if (td >= 0) {
+ struct wtimer_callback __xdata * __autodata d = (struct wtimer_callback __xdata *)wtimer_state[0].queue;
+ wtimer_state[0].queue = wtimer_state[0].queue->next;
+ wtimer_addcb_core(d);
+ continue;
+ }
+ if (td < -(0x10000-WTIMER0_MARGIN))
+ break;
+ {
+ uint16_t __autodata nxt = wtimer_state[0].time.ref - (uint16_t)td;
+ WTEVTA0 = nxt;
+ WTEVTA1 = nxt >> 8;
+ }
+ return;
+ }
+ {
+ uint16_t __autodata nxt = wtimer_state[0].time.ref + (uint16_t)(0x10000-WTIMER0_MARGIN);
+ WTEVTA0 = nxt;
+ WTEVTA1 = nxt >> 8;
+ }
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_update(void) __reentrant
+{
+ uint16_t __autodata t;
+ t = WTCNTA0;
+ t |= ((uint16_t)WTCNTR1) << 8;
+ {
+ uint16_t __autodata t1 = wtimer_state[0].time.ref;
+ wtimer_state[0].time.ref = t;
+ t -= t1;
+ }
+ if (!t)
+ return;
+ wtimer_state[0].time.cur += t;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer0_addcore(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata * __autodata d = WTIMER_PTR(wtimer_state[0].queue);
+ for (;;) {
+ struct wtimer_desc __xdata * __autodata dn = d->next;
+ int32_t __autodata td;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ td = desc->time - dn->time;
+ if (td < 0)
+ break;
+ d = dn;
+ }
+ desc->next = d->next;
+ d->next = desc;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_schedq(void) __reentrant
+{
+ while (wtimer_state[1].queue != WTIMER_NULLDESC) {
+ int32_t __autodata td = wtimer_state[1].time.cur - wtimer_state[1].queue->time;
+ if (td >= 0) {
+ struct wtimer_callback __xdata * __autodata d = (struct wtimer_callback __xdata *)wtimer_state[1].queue;
+ wtimer_state[1].queue = wtimer_state[1].queue->next;
+ wtimer_addcb_core(d);
+ continue;
+ }
+ if (td < -(0x10000-WTIMER1_MARGIN))
+ break;
+ {
+ uint16_t __autodata nxt = wtimer_state[1].time.ref - (uint16_t)td;
+ WTEVTB0 = nxt;
+ WTEVTB1 = nxt >> 8;
+ }
+ return;
+ }
+ {
+ uint16_t __autodata nxt = wtimer_state[1].time.ref + (uint16_t)(0x10000-WTIMER1_MARGIN);
+ WTEVTB0 = nxt;
+ WTEVTB1 = nxt >> 8;
+ }
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_update(void) __reentrant
+{
+ uint16_t __autodata t;
+ t = WTCNTB0;
+ t |= ((uint16_t)WTCNTR1) << 8;
+ {
+ uint16_t __autodata t1 = wtimer_state[1].time.ref;
+ wtimer_state[1].time.ref = t;
+ t -= t1;
+ }
+ if (!t)
+ return;
+ wtimer_state[1].time.cur += t;
+}
+
+// Must be called with (wtimer) interrupts disabled
+__reentrantb void wtimer1_addcore(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata * __autodata d = WTIMER_PTR(wtimer_state[1].queue);
+ for (;;) {
+ struct wtimer_desc __xdata * __autodata dn = d->next;
+ int32_t __autodata td;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ td = desc->time - dn->time;
+ if (td < 0)
+ break;
+ d = dn;
+ }
+ desc->next = d->next;
+ d->next = desc;
+}
+
+static __reentrantb void wtimer_preparesleep(void) __reentrant
+{
+ uint16_t __autodata t;
+ WTCFGB = 0x0F;
+ WTIRQEN = 0x01;
+ if (SILICONREV != 0x8E)
+ return;
+ t = WTEVTA0;
+ t |= ((uint16_t)WTEVTA1) << 8;
+ {
+ uint16_t t1 = wtimer_state[0].time.ref;
+ wtimer_state[0].time.ref = t;
+ t -= t1;
+ }
+ if (!(DBGLNKSTAT & 0x10))
+ if ((WTCFGA & 0x07) == CLKSRC_LPXOSC)
+ t += (((uint8_t)(WTIMER_LPXOSC_SLEEP)) << 1) >> ((WTCFGA >> 3) & 0x07);
+ wtimer_state[0].time.cur += t;
+}
+
+static __reentrantb uint8_t wtimer_checkexpired(void) __reentrant
+{
+ {
+ uint16_t __autodata t;
+ t = WTCNTA0;
+ t |= ((uint16_t)WTCNTR1) << 8;
+ t -= WTEVTA0 | (((uint16_t)WTEVTA1) << 8);
+ if (t < WTIMER0_MARGIN)
+ return 1;
+ }
+ {
+ uint16_t __autodata t;
+ t = WTCNTB0;
+ t |= ((uint16_t)WTCNTR1) << 8;
+ t -= WTEVTB0 | (((uint16_t)WTEVTB1) << 8);
+ if (t < WTIMER1_MARGIN)
+ return 1;
+ }
+ if (WTSTAT & 0x21)
+ return 1;
+ return 0;
+}
+
+#endif
+
+#if defined(SDCC)
+extern __reentrantb uint8_t wtimer_cansleep(void) __reentrant;
+
+static void wtimer_cansleep_dummy(void) __naked
+{
+ __asm
+ .area HOME (CODE)
+ .area WTCANSLP0 (CODE)
+ .area WTCANSLP1 (CODE)
+ .area WTCANSLP2 (CODE)
+
+ .area WTCANSLP0 (CODE)
+_wtimer_cansleep_ret0:
+ mov dpl,#0x00
+ ret
+
+ .globl _wtimer_cansleep
+_wtimer_cansleep:
+ ;; wtimer_state[1].queue == WTIMER_NULLDESC
+ mov dptr,#(_wtimer_state + 0x000e)
+ movx a,@dptr
+ cpl a
+ jnz _wtimer_cansleep_ret0
+ inc dptr
+ movx a,@dptr
+ cpl a
+ jnz _wtimer_cansleep_ret0
+
+ .area WTCANSLP2 (CODE)
+ mov dpl,#0x01
+ ret
+
+ .area HOME (CODE)
+ .area WTSTDBY0 (CODE)
+ .area WTSTDBY1 (CODE)
+ .area WTSTDBY2 (CODE)
+
+ .area WTSTDBY1 (CODE)
+ push ar0
+ push ar1
+ push ar2
+ push ar3
+ push ar4
+ push ar5
+ push ar6
+ push ar7
+ lcall _wtimer_runcallbacks
+ mov dpl,#WTFLAG_CANSTANDBY
+ lcall _wtimer_idle
+ pop ar7
+ pop ar6
+ pop ar5
+ pop ar4
+ pop ar3
+ pop ar2
+ pop ar1
+ pop ar0
+ ret
+
+ .area CSEG (CODE)
+ __endasm;
+}
+
+#else
+__reentrantb uint8_t wtimer_cansleep(void) __reentrant
+{
+ return wtimer_state[1].queue == WTIMER_NULLDESC;
+}
+#endif
+
+#if defined(SDCC)
+typedef __reentrantb void (*handler_t)(struct wtimer_callback __xdata *desc) __reentrant;
+#else
+typedef void (*handler_t)(struct wtimer_callback __xdata *desc);
+#endif
+
+/*
+ * This function is reentrant even though it is not marked reentrant.
+ * When marked reentrant, code generation gets worse for SDCC
+ * (IE is placed on stack rather than a register)
+ */
+
+#if defined(SDCC)
+#pragma nooverlay wtimer_runcallbacks
+uint8_t wtimer_runcallbacks(void)
+#elif defined(__ICC8051__)
+uint8_t wtimer_runcallbacks(void)
+#else
+__reentrantb uint8_t wtimer_runcallbacks(void) __reentrant
+#endif
+{
+ uint8_t __autodata ret = 0;
+ for (;;) {
+ uint8_t __autodata iesave = IE & 0x80;
+ EA = 0;
+ wtimer0_update();
+ wtimer0_schedq();
+ wtimer1_update();
+ wtimer1_schedq();
+ for (;;) {
+ {
+ struct wtimer_callback __xdata * __autodata d = wtimer_pending;
+ if (d != WTIMER_NULLCB) {
+ wtimer_pending = d->next;
+ IE |= iesave;
+ ++ret;
+ ((handler_t)(d->handler))(d);
+ EA = 0;
+ continue;
+ }
+ }
+ {
+ uint8_t __autodata exp = wtimer_checkexpired();
+ IE |= iesave;
+ if (exp)
+ break;
+ return ret;
+ }
+ }
+ }
+}
+
+#if defined(SDCC) || defined(__ICC8051__)
+#define WTFLAG_CANSLEEPANY (WTFLAG_CANSLEEP | WTFLAG_CANSLEEPCONT)
+#else
+#define WTFLAG_CANSLEEPANY (WTFLAG_CANSLEEP)
+#endif
+
+__reentrantb uint8_t wtimer_idle(uint8_t flags) __reentrant
+{
+ uint8_t iesave = IE & 0x80;
+ EA = 0;
+ if (wtimer_pending != WTIMER_NULLCB || wtimer_checkexpired()) {
+ IE |= iesave;
+ return WTIDLE_WORK;
+ }
+ if (flags & WTFLAG_CANSLEEPANY && wtimer_cansleep()) {
+ wtimer_preparesleep();
+ // FIXME: copy wtimer_state[0] to IRAM if there are not too many cb's?
+ if ((void __xdata *)(&wtimer_state[0]) < (void __xdata *)0x1000)
+ PCON = (PCON & 0x0C) | 0x04;
+ if ((void __xdata *)(&wtimer_state[0]) >= (void __xdata *)(0x1000-sizeof(wtimer_state[0])))
+ PCON = (PCON & 0x0C) | 0x08;
+#if defined(SDCC) || defined(__ICC8051__)
+ if (flags & WTFLAG_CANSLEEPCONT) {
+ enter_sleep_cont();
+ IE |= iesave;
+ return WTIDLE_SLEEP;
+ }
+#endif
+ enter_sleep();
+ } else if (flags & WTFLAG_CANSTANDBY) {
+ enter_standby();
+ }
+ IE |= iesave;
+ return 0;
+}
diff --git a/libs/libmf/source/wtimer.h b/libs/libmf/source/wtimer.h
new file mode 100644
index 00000000..b7c6e884
--- /dev/null
+++ b/libs/libmf/source/wtimer.h
@@ -0,0 +1,37 @@
+#ifndef WTIMER_H
+#define WTIMER_H
+
+#include "libmfwtimer.h"
+
+struct wtimer_state {
+ struct wtimer_state_time {
+ uint32_t cur;
+ uint16_t ref;
+ } time;
+ struct wtimer_desc __xdata *queue;
+};
+
+extern struct wtimer_state __xdata wtimer_state[2];
+extern struct wtimer_callback __xdata * __xdata wtimer_pending;
+
+#define WTIMER_NULL (0xFFFF)
+#define WTIMER_NULLDESC ((struct wtimer_desc __xdata *)WTIMER_NULL)
+#define WTIMER_NULLCB ((struct wtimer_callback __xdata *)WTIMER_NULL)
+#define WTIMER_PTR(x) ((struct wtimer_desc __xdata *)((char __xdata *)&(x) - (char __xdata *)&((struct wtimer_desc __xdata *)0)->next))
+#define WTIMER_CBPTR(x) ((struct wtimer_callback __xdata *)((char __xdata *)&(x) - (char __xdata *)&((struct wtimer_callback __xdata *)0)->next))
+
+// the following routines must be called with (wtimer) interrupts disabled
+extern __reentrantb void wtimer_addcb_core(struct wtimer_callback __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer_removecb_core(struct wtimer_callback __xdata *desc) __reentrant;
+extern __reentrantb void wtimer0_schedq(void) __reentrant;
+extern __reentrantb void wtimer0_update(void) __reentrant;
+extern __reentrantb void wtimer0_addcore(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer0_removecb_core(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb void wtimer1_schedq(void) __reentrant;
+extern __reentrantb void wtimer1_update(void) __reentrant;
+extern __reentrantb void wtimer1_addcore(struct wtimer_desc __xdata *desc) __reentrant;
+extern __reentrantb uint8_t wtimer1_removecb_core(struct wtimer_desc __xdata *desc) __reentrant;
+
+#define WTIMER_USEASM
+
+#endif /* WTIMER_H */
diff --git a/libs/libmf/source/wtrem.c b/libs/libmf/source/wtrem.c
new file mode 100644
index 00000000..304cebc1
--- /dev/null
+++ b/libs/libmf/source/wtrem.c
@@ -0,0 +1,163 @@
+#include "ax8052.h"
+#include "wtimer.h"
+
+#if defined(WTIMER_USEASM) && defined(SDCC)
+
+__reentrantb uint8_t wtimer_removecb_core(struct wtimer_callback __xdata *desc) __reentrant __naked
+{
+ __asm
+ ar7 = 0x07
+ ar6 = 0x06
+ ar5 = 0x05
+ ar4 = 0x04
+ ar3 = 0x03
+ ar2 = 0x02
+ ar1 = 0x01
+ ar0 = 0x00
+
+ ;; R5:R4 = &wtimer_pending
+ mov r4,#_wtimer_pending
+ mov r5,#(_wtimer_pending >> 8)
+_wtimer_removecb_core_body:
+ ;; R0 = 0
+ mov r0,#0
+ ;; R3:R2 = desc
+ mov r2,dpl
+ mov r3,dph
+00000$:
+ ;; R7:R6 = R5:R4->next
+ mov dpl,r4
+ mov dph,r5
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ ;; check R7:R6 == WTIMER_NULL
+ cjne r6,#(WTIMER_NULL & 0xFF),00002$
+ cjne r7,#(WTIMER_NULL >> 8),00002$
+00001$:
+ mov dpl,r0
+ ret
+00002$:
+ ;; check R7:R6 == R3:R2
+ mov a,r2
+ cjne a,ar6,00003$
+ mov a,r3
+ cjne a,ar7,00003$
+ ;; R7:R6 = R7:R6->next
+ mov dpl,r6
+ mov dph,r7
+ movx a,@dptr
+ mov r6,a
+ inc dptr
+ movx a,@dptr
+ mov r7,a
+ ;; R5:R4->next = R7:R6
+ mov dpl,r4
+ mov dph,r5
+ mov a,r6
+ movx @dptr,a
+ inc dptr
+ mov a,r7
+ movx @dptr,a
+ ;; ++R0
+ inc r0
+ ;; check R7:R6 == WTIMER_NULL
+ cjne r6,#(WTIMER_NULL & 0xFF),00003$
+ cjne r7,#(WTIMER_NULL >> 8),00003$
+ sjmp 00001$
+00003$:
+ ;; R5:R4 = R7:R6
+ mov r4,ar6
+ mov r5,ar7
+ sjmp 00000$
+ __endasm;
+}
+
+__reentrantb uint8_t wtimer0_removecb_core(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ ;; R5:R4 = &wtimer_state[0].queue
+ mov r4,#(_wtimer_state + 0x0006)
+ mov r5,#((_wtimer_state + 0x0006) >> 8)
+ sjmp _wtimer_removecb_core_body
+ __endasm;
+}
+
+__reentrantb uint8_t wtimer1_removecb_core(struct wtimer_desc __xdata *desc) __reentrant __naked
+{
+ __asm
+ ;; R5:R4 = &wtimer_state[1].queue
+ mov r4,#(_wtimer_state + 0x000E)
+ mov r5,#((_wtimer_state + 0x000E) >> 8)
+ sjmp _wtimer_removecb_core_body
+ __endasm;
+}
+
+#else
+
+__reentrantb uint8_t wtimer_removecb_core(struct wtimer_callback __xdata *desc) __reentrant
+{
+ struct wtimer_callback __xdata *d;
+ uint8_t ret = 0;
+ d = WTIMER_CBPTR(wtimer_pending);
+ for (;;) {
+ struct wtimer_callback __xdata *dn = d->next;
+ if (dn == WTIMER_NULLCB)
+ break;
+ if (dn == desc) {
+ dn = dn->next;
+ d->next = dn;
+ ++ret;
+ if (dn == WTIMER_NULLCB)
+ break;
+ }
+ d = dn;
+ }
+ return ret;
+}
+
+__reentrantb uint8_t wtimer0_removecb_core(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret = 0;
+ d = WTIMER_PTR(wtimer_state[0].queue);
+ for (;;) {
+ struct wtimer_desc __xdata *dn = d->next;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ if (dn == desc) {
+ dn = dn->next;
+ d->next = dn;
+ ++ret;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ }
+ d = dn;
+ }
+ return ret;
+}
+
+__reentrantb uint8_t wtimer1_removecb_core(struct wtimer_desc __xdata *desc) __reentrant
+{
+ struct wtimer_desc __xdata *d;
+ uint8_t ret = 0;
+ d = WTIMER_PTR(wtimer_state[1].queue);
+ for (;;) {
+ struct wtimer_desc __xdata *dn = d->next;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ if (dn == desc) {
+ dn = dn->next;
+ d->next = dn;
+ ++ret;
+ if (dn == WTIMER_NULLDESC)
+ break;
+ }
+ d = dn;
+ }
+ return ret;
+}
+
+#endif
diff --git a/libs/libmf/source/wtstdby.c b/libs/libmf/source/wtstdby.c
new file mode 100644
index 00000000..6e0bcc85
--- /dev/null
+++ b/libs/libmf/source/wtstdby.c
@@ -0,0 +1,35 @@
+#include "ax8052.h"
+#include "libmftypes.h"
+
+#if defined(SDCC)
+
+#pragma codeseg WTSTDBY0
+
+// fixme: make enter_* reentrant, make wtimer_runcallbacks/idle reentrant
+
+__reentrantb void wtimer_standby(void) __reentrant
+{
+ __asm
+ .area HOME (CODE)
+ .area WTSTDBY0 (CODE)
+ .area WTSTDBY1 (CODE)
+ .area WTSTDBY2 (CODE)
+
+ .area WTSTDBY2 (CODE)
+ mov a,#0x0C
+ anl a,_PCON
+ orl a,#0x01
+ mov _PCON,a
+ ret
+ __endasm;
+}
+
+
+#else
+
+__reentrantb void wtimer_standby(void) __reentrant
+{
+ enter_standby();
+}
+
+#endif
diff --git a/libs/pthreads-w32-2-9-1-release/ANNOUNCE b/libs/pthreads-w32-2-9-1-release/ANNOUNCE
new file mode 100644
index 00000000..950c86ff
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/ANNOUNCE
@@ -0,0 +1,483 @@
+PTHREADS-WIN32 RELEASE 2.9.0 (2012-05-25)
+-----------------------------------------
+Web Site: http://sourceware.org/pthreads-win32/
+FTP Site: ftp://sourceware.org/pub/pthreads-win32
+Maintainer: Ross Johnson
+
+
+We are pleased to announce the availability of a new release of
+Pthreads-win32, an Open Source Software implementation of the
+Threads component of the POSIX 1003.1 2001 Standard for Microsoft's
+Win32 environment. Some functions from other sections of POSIX
+1003.1 2001 are also supported including semaphores and scheduling
+functions.
+
+Some common non-portable functions are also implemented for
+additional compatibility, as are a few functions specific
+to pthreads-win32 for easier integration with Win32 applications.
+
+Pthreads-win32 is free software, distributed under the GNU Lesser
+General Public License (LGPL).
+
+
+Acknowledgements
+----------------
+This library is based originally on a Win32 pthreads
+implementation contributed by John Bossom.
+
+The implementation of Condition Variables uses algorithms developed
+by Alexander Terekhov and Louis Thomas.
+
+The implementation of POSIX mutexes has been improved by Thomas Pfaff
+and later by Alexander Terekhov.
+
+The implementation of Spinlocks and Barriers was contributed
+by Ross Johnson.
+
+The implementation of read/write locks was contributed by
+Aurelio Medina and improved by Alexander Terekhov.
+
+Many others have contributed significant time and effort to solve crutial
+problems in order to make the library workable, robust and reliable.
+
+Thanks to Xavier Leroy for granting permission to use and modify his
+LinuxThreads manual pages.
+
+Thanks to The Open Group for making the Single Unix Specification
+publicly available - many of the manual pages included in the package
+were extracted from it.
+
+There is also a separate CONTRIBUTORS file. This file and others are
+on the web site:
+
+ http://sourceware.org/pthreads-win32
+
+As much as possible, the ChangeLog file acknowledges contributions to the
+code base in more detail.
+
+
+Changes since the last release
+------------------------------
+These are now documented in the NEWS file.
+See the ChangeLog file also.
+
+
+Known Bugs
+----------
+These are now documented in the BUGS file.
+
+
+Level of standards conformance
+------------------------------
+
+The following POSIX 1003.1 2001 options are defined and set to 200112L:
+
+ _POSIX_THREADS
+ _POSIX_THREAD_SAFE_FUNCTIONS
+ _POSIX_THREAD_ATTR_STACKSIZE
+ _POSIX_THREAD_PRIORITY_SCHEDULING
+ _POSIX_SEMAPHORES
+ _POSIX_READER_WRITER_LOCKS
+ _POSIX_SPIN_LOCKS
+ _POSIX_BARRIERS
+
+
+The following POSIX 1003.1 2001 options are defined and set to -1:
+
+ _POSIX_THREAD_ATTR_STACKADDR
+ _POSIX_THREAD_PRIO_INHERIT
+ _POSIX_THREAD_PRIO_PROTECT
+ _POSIX_THREAD_PROCESS_SHARED
+
+
+The following POSIX 1003.1 2001 limits are defined and set:
+
+ _POSIX_THREAD_THREADS_MAX
+ _POSIX_SEM_VALUE_MAX
+ _POSIX_SEM_NSEMS_MAX
+ _POSIX_THREAD_KEYS_MAX
+ _POSIX_THREAD_DESTRUCTOR_ITERATIONS
+ PTHREAD_STACK_MIN
+ PTHREAD_THREADS_MAX
+ SEM_VALUE_MAX
+ SEM_NSEMS_MAX
+ PTHREAD_KEYS_MAX
+ PTHREAD_DESTRUCTOR_ITERATIONS
+
+
+The following functions are implemented:
+
+ ---------------------------
+ PThreads
+ ---------------------------
+ pthread_attr_init
+ pthread_attr_destroy
+ pthread_attr_getdetachstate
+ pthread_attr_getstackaddr
+ pthread_attr_getstacksize
+ pthread_attr_setdetachstate
+ pthread_attr_setstackaddr
+ pthread_attr_setstacksize
+
+ pthread_create
+ pthread_detach
+ pthread_equal
+ pthread_exit
+ pthread_join
+ pthread_once
+ pthread_self
+
+ pthread_cancel
+ pthread_cleanup_pop
+ pthread_cleanup_push
+ pthread_setcancelstate
+ pthread_setcanceltype
+ pthread_testcancel
+
+ ---------------------------
+ Thread Specific Data
+ ---------------------------
+ pthread_key_create
+ pthread_key_delete
+ pthread_setspecific
+ pthread_getspecific
+
+ ---------------------------
+ Mutexes
+ ---------------------------
+ pthread_mutexattr_init
+ pthread_mutexattr_destroy
+ pthread_mutexattr_getpshared
+ pthread_mutexattr_setpshared
+ pthread_mutexattr_gettype
+ pthread_mutexattr_settype (types: PTHREAD_MUTEX_DEFAULT
+ PTHREAD_MUTEX_NORMAL
+ PTHREAD_MUTEX_ERRORCHECK
+ PTHREAD_MUTEX_RECURSIVE )
+ pthread_mutexattr_getrobust
+ pthread_mutexattr_setrobust (values: PTHREAD_MUTEX_STALLED
+ PTHREAD_MUTEX_ROBUST)
+ pthread_mutex_init
+ pthread_mutex_destroy
+ pthread_mutex_lock
+ pthread_mutex_trylock
+ pthread_mutex_timedlock
+ pthread_mutex_unlock
+ pthread_mutex_consistent
+
+ ---------------------------
+ Condition Variables
+ ---------------------------
+ pthread_condattr_init
+ pthread_condattr_destroy
+ pthread_condattr_getpshared
+ pthread_condattr_setpshared
+
+ pthread_cond_init
+ pthread_cond_destroy
+ pthread_cond_wait
+ pthread_cond_timedwait
+ pthread_cond_signal
+ pthread_cond_broadcast
+
+ ---------------------------
+ Read/Write Locks
+ ---------------------------
+ pthread_rwlock_init
+ pthread_rwlock_destroy
+ pthread_rwlock_tryrdlock
+ pthread_rwlock_trywrlock
+ pthread_rwlock_rdlock
+ pthread_rwlock_timedrdlock
+ pthread_rwlock_rwlock
+ pthread_rwlock_timedwrlock
+ pthread_rwlock_unlock
+ pthread_rwlockattr_init
+ pthread_rwlockattr_destroy
+ pthread_rwlockattr_getpshared
+ pthread_rwlockattr_setpshared
+
+ ---------------------------
+ Spin Locks
+ ---------------------------
+ pthread_spin_init
+ pthread_spin_destroy
+ pthread_spin_lock
+ pthread_spin_unlock
+ pthread_spin_trylock
+
+ ---------------------------
+ Barriers
+ ---------------------------
+ pthread_barrier_init
+ pthread_barrier_destroy
+ pthread_barrier_wait
+ pthread_barrierattr_init
+ pthread_barrierattr_destroy
+ pthread_barrierattr_getpshared
+ pthread_barrierattr_setpshared
+
+ ---------------------------
+ Semaphores
+ ---------------------------
+ sem_init
+ sem_destroy
+ sem_post
+ sem_wait
+ sem_trywait
+ sem_timedwait
+ sem_getvalue (# free if +ve, # of waiters if -ve)
+ sem_open (returns an error ENOSYS)
+ sem_close (returns an error ENOSYS)
+ sem_unlink (returns an error ENOSYS)
+
+ ---------------------------
+ RealTime Scheduling
+ ---------------------------
+ pthread_attr_getschedparam
+ pthread_attr_setschedparam
+ pthread_attr_getinheritsched
+ pthread_attr_setinheritsched
+ pthread_attr_getschedpolicy (only supports SCHED_OTHER)
+ pthread_attr_setschedpolicy (only supports SCHED_OTHER)
+ pthread_getschedparam
+ pthread_setschedparam
+ pthread_getconcurrency
+ pthread_setconcurrency
+ pthread_attr_getscope
+ pthread_attr_setscope (only supports PTHREAD_SCOPE_SYSTEM)
+ sched_get_priority_max
+ sched_get_priority_min
+ sched_rr_get_interval (returns an error ENOTSUP)
+ sched_setscheduler (only supports SCHED_OTHER)
+ sched_getscheduler (only supports SCHED_OTHER)
+ sched_yield
+
+ ---------------------------
+ Signals
+ ---------------------------
+ pthread_sigmask
+ pthread_kill (only supports zero sig value,
+ for thread validity checking)
+
+ ---------------------------
+ Non-portable routines (see the README.NONPORTABLE file for usage)
+ ---------------------------
+ pthread_getw32threadhandle_np
+ pthread_timechange_handler_np
+ pthread_delay_np
+ pthread_getunique_np
+ pthread_mutexattr_getkind_np
+ pthread_mutexattr_setkind_np (types: PTHREAD_MUTEX_FAST_NP,
+ PTHREAD_MUTEX_ERRORCHECK_NP,
+ PTHREAD_MUTEX_RECURSIVE_NP,
+ PTHREAD_MUTEX_ADAPTIVE_NP,
+ PTHREAD_MUTEX_TIMED_NP)
+ pthread_num_processors_np
+ (The following four routines may be required when linking statically.
+ The process_* routines should not be needed for MSVC or GCC.)
+ pthread_win32_process_attach_np
+ pthread_win32_process_detach_np
+ (The following routines should only be needed to manage implicit
+ POSIX handles i.e. when Win native threads call POSIX thread routines
+ (other than pthread_create))
+ pthread_win32_thread_attach_np
+ pthread_win32_thread_detach_np
+
+ ---------------------------
+ Static Initializers
+ ---------------------------
+ PTHREAD_ONCE_INIT
+ PTHREAD_MUTEX_INITIALIZER
+ PTHREAD_RECURSIVE_MUTEX_INITIALIZER
+ PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP
+ PTHREAD_ERRORCHECK_MUTEX_INITIALIZER
+ PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP
+ PTHREAD_COND_INITIALIZER
+ PTHREAD_RWLOCK_INITIALIZER
+ PTHREAD_SPINLOCK_INITIALIZER
+
+
+The library includes two non-API functions for creating cancellation
+points in applications and libraries:
+
+ pthreadCancelableWait
+ pthreadCancelableTimedWait
+
+
+The following functions are not implemented:
+
+ ---------------------------
+ RealTime Scheduling
+ ---------------------------
+ pthread_mutex_getprioceiling
+ pthread_mutex_setprioceiling
+ pthread_mutex_attr_getprioceiling
+ pthread_mutex_attr_getprotocol
+ pthread_mutex_attr_setprioceiling
+ pthread_mutex_attr_setprotocol
+
+ ---------------------------
+ Fork Handlers
+ ---------------------------
+ pthread_atfork
+
+ ---------------------------
+ Stdio
+ ---------------------------
+ flockfile
+ ftrylockfile
+ funlockfile
+ getc_unlocked
+ getchar_unlocked
+ putc_unlocked
+ putchar_unlocked
+
+ ---------------------------
+ Thread-Safe C Runtime Library
+ ---------------------------
+ readdir_r
+ getgrgid_r
+ getgrnam_r
+ getpwuid_r
+ getpwnam_r
+
+ ---------------------------
+ Signals
+ ---------------------------
+ sigtimedwait
+ sigwait
+ sigwaitinfo
+
+ ---------------------------
+ General
+ ---------------------------
+ sysconf
+
+ ---------------------------
+ Thread-Safe C Runtime Library (macros)
+ ---------------------------
+ strtok_r
+ asctime_r
+ ctime_r
+ gmtime_r
+ localtime_r
+ rand_r
+
+
+Availability
+------------
+
+The prebuilt DLL, export libs (for both MSVC and Mingw32), and the header
+files (pthread.h, semaphore.h, sched.h) are available along with the
+complete source code.
+
+The source code can be found at:
+
+ ftp://sources.redhat.com/pub/pthreads-win32
+
+and as individual source code files at
+
+ ftp://sources.redhat.com/pub/pthreads-win32/source
+
+The pre-built DLL, export libraries and include files can be found at:
+
+ ftp://sources.redhat.com/pub/pthreads-win32/dll-latest
+
+
+
+Mailing List
+------------
+
+There is a mailing list for discussing pthreads on Win32. To join,
+send email to:
+
+ pthreads-win32-subscribe@sourceware.cygnus.com
+
+
+Application Development Environments
+------------------------------------
+
+See the README file for more information.
+
+MSVC:
+MSVC using SEH works. Distribute pthreadVSE.dll with your application.
+MSVC using C++ EH works. Distribute pthreadVCE.dll with your application.
+MSVC using C setjmp/longjmp works. Distribute pthreadVC.dll with your application.
+
+
+Mingw32:
+See the FAQ, Questions 6 and 10.
+
+Mingw using C++ EH works. Distribute pthreadGCE.dll with your application.
+Mingw using C setjmp/longjmp works. Distribute pthreadGC.dll with your application.
+
+
+Cygwin: (http://sourceware.cygnus.com/cygwin/)
+Developers using Cygwin do not need pthreads-win32 since it has POSIX threads
+support. Refer to its documentation for details and extent.
+
+
+UWIN:
+UWIN is a complete Unix-like environment for Windows from AT&T. Pthreads-win32
+doesn't currently support UWIN (and vice versa), but that may change in the
+future.
+
+Generally:
+For convenience, the following pre-built files are available on the FTP site
+(see Availability above):
+
+ pthread.h - for POSIX threads
+ semaphore.h - for POSIX semaphores
+ sched.h - for POSIX scheduling
+ pthreadVCE.dll - built with MSVC++ compiler using C++ EH
+ pthreadVCE.lib
+ pthreadVC.dll - built with MSVC compiler using C setjmp/longjmp
+ pthreadVC.lib
+ pthreadVSE.dll - built with MSVC compiler using SEH
+ pthreadVSE.lib
+ pthreadGCE.dll - built with Mingw32 G++ 2.95.2-1
+ pthreadGC.dll - built with Mingw32 GCC 2.95.2-1 using setjmp/longjmp
+ libpthreadGCE.a - derived from pthreadGCE.dll
+ libpthreadGC.a - derived from pthreadGC.dll
+ gcc.dll - needed if distributing applications that use
+ pthreadGCE.dll (but see the FAQ Q 10 for the latest
+ related information)
+
+These are the only files you need in order to build POSIX threads
+applications for Win32 using either MSVC or Mingw32.
+
+See the FAQ file in the source tree for additional information.
+
+
+Documentation
+-------------
+
+For the authoritative reference, see the online POSIX
+standard reference at:
+
+ http://www.OpenGroup.org
+
+For POSIX Thread API programming, several reference books are
+available:
+
+ Programming with POSIX Threads
+ David R. Butenhof
+ Addison-Wesley (pub)
+
+ Pthreads Programming
+ By Bradford Nichols, Dick Buttlar & Jacqueline Proulx Farrell
+ O'Reilly (pub)
+
+On the web: see the links at the bottom of the pthreads-win32 site:
+
+ http://sources.redhat.com/pthreads-win32/
+
+ Currently, there is no documentation included in the package apart
+ from the copious comments in the source code.
+
+
+
+Enjoy!
+
+Ross Johnson
diff --git a/libs/pthreads-w32-2-9-1-release/BUGS b/libs/pthreads-w32-2-9-1-release/BUGS
new file mode 100644
index 00000000..285ba4eb
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/BUGS
@@ -0,0 +1,141 @@
+----------
+Known bugs
+----------
+
+1. Not strictly a bug, more of a gotcha.
+
+ Under MS VC++ (only tested with version 6.0), a term_func
+ set via the standard C++ set_terminate() function causes the
+ application to abort.
+
+ Notes from the MSVC++ manual:
+ 1) A term_func() should call exit(), otherwise
+ abort() will be called on return to the caller.
+ A call to abort() raises SIGABRT and the default signal handler
+ for all signals terminates the calling program with
+ exit code 3.
+ 2) A term_func() must not throw an exception. Therefore
+ term_func() should not call pthread_exit(), which
+ works by throwing an exception (pthreadVCE or pthreadVSE)
+ or by calling longjmp (pthreadVC).
+
+ Workaround: avoid using pthread_exit() in C++ applications. Exit
+ threads by dropping through the end of the thread routine.
+
+2. Cancellation problems in C++ builds
+ - Milan Gardian
+
+ [Note: It's not clear if this problem isn't simply due to the context
+ switch in pthread_cancel() which occurs unless the QueueUserAPCEx
+ library and driver are installed and used. Just like setjmp/longjmp,
+ this is probably not going to work well in C++. In any case, unless for
+ some very unusual reason you really must use the C++ build then please
+ use the C build pthreadVC2.dll or pthreadGC2.dll, i.e. for C++
+ applications.]
+
+ This is suspected to be a compiler bug in VC6.0, and also seen in
+ VC7.0 and VS .NET 2003. The GNU C++ compiler does not have a problem
+ with this, and it has been reported that the Intel C++ 8.1 compiler
+ and Visual C++ 2005 Express Edition Beta2 pass tests\semaphore4.c
+ (which exposes the bug).
+
+ Workaround [rpj - 2 Feb 2002]
+ -----------------------------
+ [Please note: this workaround did not solve a similar problem in
+ snapshot-2004-11-03 or later, even though similar symptoms were seen.
+ tests\semaphore4.c fails in that snapshot for the VCE version of the
+ DLL.]
+
+ The problem disappears when /Ob0 is used, i.e. /O2 /Ob0 works OK,
+ but if you want to use inlining optimisation you can be much more
+ specific about where it's switched off and on by using a pragma.
+
+ So the inlining optimisation is interfering with the way that cleanup
+ handlers are run. It appears to relate to auto-inlining of class methods
+ since this is the only auto inlining that is performed at /O1 optimisation
+ (functions with the "inline" qualifier are also inlined, but the problem
+ doesn't appear to involve any such functions in the library or testsuite).
+
+ In order to confirm the inlining culprit, the following use of pragmas
+ eliminate the problem but I don't know how to make it transparent, putting
+ it in, say, pthread.h where pthread_cleanup_push defined as a macro.
+
+ #pragma inline_depth(0)
+ pthread_cleanup_push(handlerFunc, (void *) &arg);
+
+ /* ... */
+
+ pthread_cleanup_pop(0);
+ #pragma inline_depth()
+
+ Note the empty () pragma value after the pop macro. This resets depth to the
+ default. Or you can specify a non-zero depth here.
+
+ The pragma is also needed (and now used) within the library itself wherever
+ cleanup handlers are used (condvar.c and rwlock.c).
+
+ Use of these pragmas allows compiler optimisations /O1 and /O2 to be
+ used for either or both the library and applications.
+
+ Experimenting further, I found that wrapping the actual cleanup handler
+ function with #pragma auto_inline(off|on) does NOT work.
+
+ MSVC6.0 doesn't appear to support the C99 standard's _Pragma directive,
+ however, later versions may. This form is embeddable inside #define
+ macros, which would be ideal because it would mean that it could be added
+ to the push/pop macro definitions in pthread.h and hidden from the
+ application programmer.
+
+ [/rpj]
+
+ Original problem description
+ ----------------------------
+
+ The cancellation (actually, cleanup-after-cancel) tests fail when using VC
+ (professional) optimisation switches (/O1 or /O2) in pthreads library. I
+ have not investigated which concrete optimisation technique causes this
+ problem (/Og, /Oi, /Ot, /Oy, /Ob1, /Gs, /Gf, /Gy, etc.), but here is a
+ summary of builds and corresponding failures:
+
+ * pthreads VSE (optimised tests): OK
+ * pthreads VCE (optimised tests): Failed "cleanup1" test (runtime)
+
+ * pthreads VSE (DLL in CRT, optimised tests): OK
+ * pthreads VCE (DLL in CRT, optimised tests): Failed "cleanup1" test
+ (runtime)
+
+ Please note that while in VSE version of the pthreads library the
+ optimisation does not really have any impact on the tests (they pass OK), in
+ VCE version addition of optimisation (/O2 in this case) causes the tests to
+ fail uniformly - either in "cleanup0" or "cleanup1" test cases.
+
+ Please note that all the tests above use default pthreads DLL (no
+ optimisations, linked with either static or DLL CRT, based on test type).
+ Therefore the problem lies not within the pthreads DLL but within the
+ compiled client code (the application using pthreads -> involvement of
+ "pthread.h").
+
+ I think the message of this section is that usage of VCE version of pthreads
+ in applications relying on cancellation/cleanup AND using optimisations for
+ creation of production code is highly unreliable for the current version of
+ the pthreads library.
+
+3. The Borland Builder 5.5 version of the library produces memory read exceptions
+in some tests.
+
+4. pthread_barrier_wait() can deadlock if the number of potential calling
+threads for a particular barrier is greater than the barrier count parameter
+given to pthread_barrier_init() for that barrier.
+
+This is due to the very lightweight implementation of pthread-win32 barriers.
+To cope with more than "count" possible waiters, barriers must effectively
+implement all the same safeguards as condition variables, making them much
+"heavier" than at present.
+
+The workaround is to ensure that no more than "count" threads attempt to wait
+at the barrier.
+
+5. Canceling a thread blocked on pthread_once appears not to work in the MSVC++
+version of the library "pthreadVCE.dll". The test case "once3.c" hangs. I have no
+clues on this at present. All other versions pass this test ok - pthreadsVC.dll,
+pthreadsVSE.dll, pthreadsGC.dll and pthreadsGCE.dll.
diff --git a/libs/pthreads-w32-2-9-1-release/Bmakefile b/libs/pthreads-w32-2-9-1-release/Bmakefile
new file mode 100644
index 00000000..ea25dec4
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/Bmakefile
@@ -0,0 +1,268 @@
+# This makefile is compatible with BCB make. Use "make -fBMakefile" to compile.
+#
+# The variables $DLLDEST and $LIBDEST hold the destination directories for the
+# dll and the lib, respectively. Probably all that needs to change is $DEVROOT.
+#
+# Currently only the recommended pthreadBC.dll is built by this makefile.
+#
+
+
+DLL_VER = 2
+
+DEVROOT = .
+
+DLLDEST = $(DEVROOT)\DLL
+LIBDEST = $(DEVROOT)\DLL
+
+DLLS = pthreadBC$(DLL_VER).dll
+
+OPTIM = /O2
+
+RC = brcc32
+RCFLAGS = -i.
+
+CFLAGS = /q /I. /D_WIN32_WINNT=0x400 /DHAVE_PTW32_CONFIG_H=1 /4 /tWD /tWM \
+ /w-aus /w-asc /w-par
+
+#C cleanup code
+BCFLAGS = $(PTW32_FLAGS) $(CFLAGS)
+
+# Agregate modules for inlinability
+DLL_OBJS = \
+ attr.obj \
+ barrier.obj \
+ cancel.obj \
+ cleanup.obj \
+ condvar.obj \
+ create.obj \
+ dll.obj \
+ errno.obj \
+ exit.obj \
+ fork.obj \
+ global.obj \
+ misc.obj \
+ mutex.obj \
+ nonportable.obj \
+ private.obj \
+ rwlock.obj \
+ sched.obj \
+ semaphore.obj \
+ signal.obj \
+ spin.obj \
+ sync.obj \
+ tsd.obj
+
+INCL = config.h implement.h semaphore.h pthread.h need_errno.h
+
+ATTR_SRCS = \
+ pthread_attr_init.c \
+ pthread_attr_destroy.c \
+ pthread_attr_getdetachstate.c \
+ pthread_attr_setdetachstate.c \
+ pthread_attr_getstackaddr.c \
+ pthread_attr_setstackaddr.c \
+ pthread_attr_getstacksize.c \
+ pthread_attr_setstacksize.c \
+ pthread_attr_getscope.c \
+ pthread_attr_setscope.c
+
+BARRIER_SRCS = \
+ pthread_barrier_init.c \
+ pthread_barrier_destroy.c \
+ pthread_barrier_wait.c \
+ pthread_barrierattr_init.c \
+ pthread_barrierattr_destroy.c \
+ pthread_barrierattr_setpshared.c \
+ pthread_barrierattr_getpshared.c
+
+CANCEL_SRCS = \
+ pthread_setcancelstate.c \
+ pthread_setcanceltype.c \
+ pthread_testcancel.c \
+ pthread_cancel.c
+
+CONDVAR_SRCS = \
+ ptw32_cond_check_need_init.c \
+ pthread_condattr_destroy.c \
+ pthread_condattr_getpshared.c \
+ pthread_condattr_init.c \
+ pthread_condattr_setpshared.c \
+ pthread_cond_destroy.c \
+ pthread_cond_init.c \
+ pthread_cond_signal.c \
+ pthread_cond_wait.c
+
+EXIT_SRCS = \
+ pthread_exit.c
+
+MISC_SRCS = \
+ pthread_equal.c \
+ pthread_getconcurrency.c \
+ pthread_once.c \
+ pthread_self.c \
+ pthread_setconcurrency.c \
+ ptw32_calloc.c \
+ ptw32_MCS_lock.c \
+ ptw32_new.c \
+ w32_CancelableWait.c
+
+MUTEX_SRCS = \
+ ptw32_mutex_check_need_init.c \
+ pthread_mutex_init.c \
+ pthread_mutex_destroy.c \
+ pthread_mutexattr_init.c \
+ pthread_mutexattr_destroy.c \
+ pthread_mutexattr_getpshared.c \
+ pthread_mutexattr_setpshared.c \
+ pthread_mutexattr_settype.c \
+ pthread_mutexattr_gettype.c \
+ pthread_mutexattr_setrobust.c \
+ pthread_mutexattr_getrobust.c \
+ pthread_mutex_lock.c \
+ pthread_mutex_timedlock.c \
+ pthread_mutex_unlock.c \
+ pthread_mutex_trylock.c \
+ pthread_mutex_consistent.c
+
+NONPORTABLE_SRCS = \
+ pthread_mutexattr_setkind_np.c \
+ pthread_mutexattr_getkind_np.c \
+ pthread_getw32threadhandle_np.c \
+ pthread_delay_np.c \
+ pthread_num_processors_np.c \
+ pthread_win32_attach_detach_np.c \
+ pthread_timechange_handler_np.c
+
+PRIVATE_SRCS = \
+ ptw32_is_attr.c \
+ ptw32_processInitialize.c \
+ ptw32_processTerminate.c \
+ ptw32_threadStart.c \
+ ptw32_threadDestroy.c \
+ ptw32_tkAssocCreate.c \
+ ptw32_tkAssocDestroy.c \
+ ptw32_callUserDestroyRoutines.c \
+ ptw32_timespec.c \
+ ptw32_relmillisecs.c \
+ ptw32_throw.c \
+ ptw32_getprocessors.c
+
+RWLOCK_SRCS = \
+ ptw32_rwlock_check_need_init.c \
+ ptw32_rwlock_cancelwrwait.c \
+ pthread_rwlock_init.c \
+ pthread_rwlock_destroy.c \
+ pthread_rwlockattr_init.c \
+ pthread_rwlockattr_destroy.c \
+ pthread_rwlockattr_getpshared.c \
+ pthread_rwlockattr_setpshared.c \
+ pthread_rwlock_rdlock.c \
+ pthread_rwlock_timedrdlock.c \
+ pthread_rwlock_wrlock.c \
+ pthread_rwlock_timedwrlock.c \
+ pthread_rwlock_unlock.c \
+ pthread_rwlock_tryrdlock.c \
+ pthread_rwlock_trywrlock.c
+
+SCHED_SRCS = \
+ pthread_attr_setschedpolicy.c \
+ pthread_attr_getschedpolicy.c \
+ pthread_attr_setschedparam.c \
+ pthread_attr_getschedparam.c \
+ pthread_attr_setinheritsched.c \
+ pthread_attr_getinheritsched.c \
+ pthread_setschedparam.c \
+ pthread_getschedparam.c \
+ sched_get_priority_max.c \
+ sched_get_priority_min.c \
+ sched_setscheduler.c \
+ sched_getscheduler.c \
+ sched_yield.c
+
+SEMAPHORE_SRCS = \
+ sem_init.c \
+ sem_destroy.c \
+ sem_trywait.c \
+ sem_timedwait.c \
+ sem_wait.c \
+ sem_post.c \
+ sem_post_multiple.c \
+ sem_getvalue.c \
+ sem_open.c \
+ sem_close.c \
+ sem_unlink.c
+
+SPIN_SRCS = \
+ ptw32_spinlock_check_need_init.c \
+ pthread_spin_init.c \
+ pthread_spin_destroy.c \
+ pthread_spin_lock.c \
+ pthread_spin_unlock.c \
+ pthread_spin_trylock.c
+
+SYNC_SRCS = \
+ pthread_detach.c \
+ pthread_join.c
+
+TSD_SRCS = \
+ pthread_key_create.c \
+ pthread_key_delete.c \
+ pthread_setspecific.c \
+ pthread_getspecific.c
+
+
+all: clean $(DLLS)
+
+realclean: clean
+ if exist pthread*.dll del pthread*.dll
+ if exist pthread*.lib del pthread*.lib
+ if exist *.stamp del *.stamp
+
+clean:
+ if exist *.obj del *.obj
+ if exist *.ilk del *.ilk
+ if exist *.ilc del *.ilc
+ if exist *.ild del *.ild
+ if exist *.ilf del *.ilf
+ if exist *.ils del *.ils
+ if exist *.tds del *.tds
+ if exist *.pdb del *.pdb
+ if exist *.exp del *.exp
+ if exist *.map del *.map
+ if exist *.o del *.o
+ if exist *.i del *.i
+ if exist *.res del *.res
+
+
+install: $(DLLS)
+ copy pthread*.dll $(DLLDEST)
+ copy pthread*.lib $(LIBDEST)
+
+$(DLLS): $(DLL_OBJS) version.res
+ ilink32 /Tpd /Gi c0d32x.obj $(DLL_OBJS), \
+ $@, ,\
+ cw32mti.lib import32.lib, ,\
+ version.res
+
+.c.obj:
+ $(CC) $(OPTIM) $(BCFLAGS) -c $<
+
+.rc.res:
+ $(RC) $(RCFLAGS) $<
+
+attr.obj: attr.c $(ATTR_SRCS) $(INCL)
+barrier.obj: barrier.c $(BARRIER_SRCS) $(INCL)
+cancel.obj: cancel.c $(CANCEL_SRCS) $(INCL)
+condvar.obj: condvar.c $(CONDVAR_SRCS) $(INCL)
+exit.obj: exit.c $(EXIT_SRCS) $(INCL)
+misc.obj: misc.c $(MISC_SRCS) $(INCL)
+mutex.obj: mutex.c $(MUTEX_SRCS) $(INCL)
+nonportable.obj: nonportable.c $(NONPORTABLE_SRCS) $(INCL)
+private.obj: private.c $(PRIVATE_SRCS) $(INCL)
+rwlock.obj: rwlock.c $(RWLOCK_SRCS) $(INCL)
+sched.obj: sched.c $(SCHED_SRCS) $(INCL)
+semaphore.obj: semaphore.c $(SEMAPHORE_SRCS) $(INCL)
+spin.obj: spin.c $(SPIN_SRCS) $(INCL)
+sync.obj: sync.c $(SYNC_SRCS) $(INCL)
+tsd.obj: tsd.c $(TSD_SRCS) $(INCL)
+version.res: version.rc $(INCL)
diff --git a/libs/pthreads-w32-2-9-1-release/CONTRIBUTORS b/libs/pthreads-w32-2-9-1-release/CONTRIBUTORS
new file mode 100644
index 00000000..da31ff26
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/CONTRIBUTORS
@@ -0,0 +1,140 @@
+Contributors (in approximate order of appearance)
+
+[See also the ChangeLog file where individuals are
+attributed in log entries. Likewise in the FAQ file.]
+
+Ben Elliston bje at cygnus dot com
+ Initiated the project;
+ setup the project infrastructure (CVS, web page, etc.);
+ early prototype routines.
+Ross Johnson Ross dot Johnson at dot homemail dot com dot au
+ early prototype routines;
+ ongoing project coordination/maintenance;
+ implementation of spin locks and barriers;
+ various enhancements;
+ bug fixes;
+ documentation;
+ testsuite.
+Robert Colquhoun rjc at trump dot net dot au
+ Early bug fixes.
+John E. Bossom John dot Bossom at cognos dot com
+ Contributed substantial original working implementation;
+ bug fixes;
+ ongoing guidance and standards interpretation.
+Anders Norlander anorland at hem2 dot passagen dot se
+ Early enhancements and runtime checking for supported
+ Win32 routines.
+Tor Lillqvist tml at iki dot fi
+ General enhancements;
+ early bug fixes to condition variables.
+Scott Lightner scott at curriculum dot com
+ Bug fix.
+Kevin Ruland Kevin dot Ruland at anheuser-busch dot com
+ Various bug fixes.
+Mike Russo miker at eai dot com
+ Bug fix.
+Mark E. Armstrong avail at pacbell dot net
+ Bug fixes.
+Lorin Hochstein lmh at xiphos dot ca
+ general bug fixes; bug fixes to condition variables.
+Peter Slacik Peter dot Slacik at tatramed dot sk
+ Bug fixes.
+Mumit Khan khan at xraylith dot wisc dot edu
+ Fixes to work with Mingw32.
+Milan Gardian mg at tatramed dot sk
+ Bug fixes and reports/analyses of obscure problems.
+Aurelio Medina aureliom at crt dot com
+ First implementation of read-write locks.
+Graham Dumpleton Graham dot Dumpleton at ra dot pad dot otc dot telstra dot com dot au
+ Bug fix in condition variables.
+Tristan Savatier tristan at mpegtv dot com
+ WinCE port.
+Erik Hensema erik at hensema dot xs4all dot nl
+ Bug fixes.
+Rich Peters rpeters at micro-magic dot com
+Todd Owen towen at lucidcalm dot dropbear dot id dot au
+ Bug fixes to dll loading.
+Jason Nye jnye at nbnet dot nb dot ca
+ Implementation of async cancelation.
+Fred Forester fforest at eticomm dot net
+Kevin D. Clark kclark at cabletron dot com
+David Baggett dmb at itasoftware dot com
+ Bug fixes.
+Paul Redondo paul at matchvision dot com
+Scott McCaskill scott at 3dfx dot com
+ Bug fixes.
+Jef Gearhart jgearhart at tpssys dot com
+ Bug fix.
+Arthur Kantor akantor at bexusa dot com
+ Mutex enhancements.
+Steven Reddie smr at essemer dot com dot au
+ Bug fix.
+Alexander Terekhov TEREKHOV at de dot ibm dot com
+ Re-implemented and improved read-write locks;
+ (with Louis Thomas) re-implemented and improved
+ condition variables;
+ enhancements to semaphores;
+ enhancements to mutexes;
+ new mutex implementation in 'futex' style;
+ suggested a robust implementation of pthread_once
+ similar to that implemented by V.Kliathcko;
+ system clock change handling re CV timeouts;
+ bug fixes.
+Thomas Pfaff tpfaff at gmx dot net
+ Changes to make C version usable with C++ applications;
+ re-implemented mutex routines to avoid Win32 mutexes
+ and TryEnterCriticalSection;
+ procedure to fix Mingw32 thread-safety issues.
+Franco Bez franco dot bez at gmx dot de
+ procedure to fix Mingw32 thread-safety issues.
+Louis Thomas lthomas at arbitrade dot com
+ (with Alexander Terekhov) re-implemented and improved
+ condition variables.
+David Korn dgk at research dot att dot com
+ Ported to UWIN.
+Phil Frisbie, Jr. phil at hawksoft dot com
+ Bug fix.
+Ralf Brese Ralf dot Brese at pdb4 dot siemens dot de
+ Bug fix.
+prionx at juno dot com prionx at juno dot com
+ Bug fixes.
+Max Woodbury mtew at cds dot duke dot edu
+ POSIX versioning conditionals;
+ reduced namespace pollution;
+ idea to separate routines to reduce statically
+ linked image sizes.
+Rob Fanner rfanner at stonethree dot com
+ Bug fix.
+Michael Johnson michaelj at maine dot rr dot com
+ Bug fix.
+Nicolas Barry boozai at yahoo dot com
+ Bug fixes.
+Piet van Bruggen pietvb at newbridges dot nl
+ Bug fix.
+Makoto Kato raven at oldskool dot jp
+ AMD64 port.
+Panagiotis E. Hadjidoukas peh at hpclab dot ceid dot upatras dot gr
+ phadjido at cs dot uoi dot gr
+ Contributed the QueueUserAPCEx package which
+ makes preemptive async cancelation possible.
+Will Bryant will dot bryant at ecosm dot com
+ Borland compiler patch and makefile.
+Anuj Goyal anuj dot goyal at gmail dot com
+ Port to Digital Mars compiler.
+Gottlob Frege gottlobfrege at gmail dot com
+ re-implemented pthread_once (version 2)
+ (pthread_once cancellation added by rpj).
+Vladimir Kliatchko vladimir at kliatchko dot com
+ reimplemented pthread_once with the same form
+ as described by A.Terekhov (later version 2);
+ implementation of MCS (Mellor-Crummey/Scott) locks.
+Ramiro Polla ramiro.polla at gmail dot com
+ static library auto init/cleanup on application
+ start/exit via RT hooks (MSC and GCC compilers only).
+Daniel Richard G. skunk at iSKUNK dot org
+ Patches and cleanups for x86 and x64, particularly
+ across a range of MS build environments.
+John Kamp john dot kamp at globalgraphics dot com
+ Patches to fix various problems on x64; brutal testing
+ particularly using high memory run environments.
+
diff --git a/libs/pthreads-w32-2-9-1-release/COPYING b/libs/pthreads-w32-2-9-1-release/COPYING
new file mode 100644
index 00000000..5cfea0d0
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/COPYING
@@ -0,0 +1,150 @@
+ pthreads-win32 - a POSIX threads library for Microsoft Windows
+
+
+This file is Copyrighted
+------------------------
+
+ This file is covered under the following Copyright:
+
+ Copyright (C) 2001,2006 Ross P. Johnson
+ All rights reserved.
+
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+Pthreads-win32 is covered by the GNU Lesser General Public License
+------------------------------------------------------------------
+
+ Pthreads-win32 is open software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public License
+ as published by the Free Software Foundation version 2.1 of the
+ License.
+
+ Pthreads-win32 is several binary link libraries, several modules,
+ associated interface definition files and scripts used to control
+ its compilation and installation.
+
+ Pthreads-win32 is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU Lesser General Public License for more details.
+
+ A copy of the GNU Lesser General Public License is distributed with
+ pthreads-win32 under the filename:
+
+ COPYING.LIB
+
+ You should have received a copy of the version 2.1 GNU Lesser General
+ Public License with pthreads-win32; if not, write to:
+
+ Free Software Foundation, Inc.
+ 59 Temple Place
+ Suite 330
+ Boston, MA 02111-1307
+ USA
+
+ The contact addresses for pthreads-win32 is as follows:
+
+ Web: http://sources.redhat.com/pthreads-win32
+ Email: Ross Johnson
+ Please use: Firstname.Lastname@homemail.com.au
+
+
+
+Pthreads-win32 copyrights and exception files
+---------------------------------------------
+
+ With the exception of the files listed below, Pthreads-win32
+ is covered under the following GNU Lesser General Public License
+ Copyrights:
+
+ Pthreads-win32 - POSIX Threads Library for Win32
+ Copyright(C) 1998 John E. Bossom
+ Copyright(C) 1999,2006 Pthreads-win32 contributors
+
+ The current list of contributors is contained
+ in the file CONTRIBUTORS included with the source
+ code distribution. The current list of CONTRIBUTORS
+ can also be seen at the following WWW location:
+ http://sources.redhat.com/pthreads-win32/contributors.html
+
+ Contact Email: Ross Johnson
+ Please use: Firstname.Lastname@homemail.com.au
+
+ These files are not covered under one of the Copyrights listed above:
+
+ COPYING
+ COPYING.LIB
+ tests/rwlock7.c
+
+ This file, COPYING, is distributed under the Copyright found at the
+ top of this file. It is important to note that you may distribute
+ verbatim copies of this file but you may not modify this file.
+
+ The file COPYING.LIB, which contains a copy of the version 2.1
+ GNU Lesser General Public License, is itself copyrighted by the
+ Free Software Foundation, Inc. Please note that the Free Software
+ Foundation, Inc. does NOT have a copyright over Pthreads-win32,
+ only the COPYING.LIB that is supplied with pthreads-win32.
+
+ The file tests/rwlock7.c is derived from code written by
+ Dave Butenhof for his book 'Programming With POSIX(R) Threads'.
+ The original code was obtained by free download from his website
+ http://home.earthlink.net/~anneart/family/Threads/source.html
+ and did not contain a copyright or author notice. It is assumed to
+ be freely distributable.
+
+ In all cases one may use and distribute these exception files freely.
+ And because one may freely distribute the LGPL covered files, the
+ entire pthreads-win32 source may be freely used and distributed.
+
+
+
+General Copyleft and License info
+---------------------------------
+
+ For general information on Copylefts, see:
+
+ http://www.gnu.org/copyleft/
+
+ For information on GNU Lesser General Public Licenses, see:
+
+ http://www.gnu.org/copyleft/lesser.html
+ http://www.gnu.org/copyleft/lesser.txt
+
+
+Why pthreads-win32 did not use the GNU General Public License
+-------------------------------------------------------------
+
+ The goal of the pthreads-win32 project has been to
+ provide a quality and complete implementation of the POSIX
+ threads API for Microsoft Windows within the limits imposed
+ by virtue of it being a stand-alone library and not
+ linked directly to other POSIX compliant libraries. For
+ example, some functions and features, such as those based
+ on POSIX signals, are missing.
+
+ Pthreads-win32 is a library, available in several different
+ versions depending on supported compilers, and may be used
+ as a dynamically linked module or a statically linked set of
+ binary modules. It is not an application on it's own.
+
+ It was fully intended that pthreads-win32 be usable with
+ commercial software not covered by either the GPL or the LGPL
+ licenses. Pthreads-win32 has many contributors to it's
+ code base, many of whom have done so because they have
+ used the library in commercial or proprietry software
+ projects.
+
+ Releasing pthreads-win32 under the LGPL ensures that the
+ library can be used widely, while at the same time ensures
+ that bug fixes and improvements to the pthreads-win32 code
+ itself is returned to benefit all current and future users
+ of the library.
+
+ Although pthreads-win32 makes it possible for applications
+ that use POSIX threads to be ported to Win32 platforms, the
+ broader goal of the project is to encourage the use of open
+ standards, and in particular, to make it just a little easier
+ for developers writing Win32 applications to consider
+ widening the potential market for their products.
diff --git a/libs/pthreads-w32-2-9-1-release/COPYING.LIB b/libs/pthreads-w32-2-9-1-release/COPYING.LIB
new file mode 100644
index 00000000..b1e3f5a2
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/COPYING.LIB
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
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+ Everyone is permitted to copy and distribute verbatim copies
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+possible use to the public, we recommend making it free software that
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+safest to attach them to the start of each source file to most effectively
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+
diff --git a/libs/pthreads-w32-2-9-1-release/ChangeLog b/libs/pthreads-w32-2-9-1-release/ChangeLog
new file mode 100644
index 00000000..42abcc45
--- /dev/null
+++ b/libs/pthreads-w32-2-9-1-release/ChangeLog
@@ -0,0 +1,5211 @@
+2012-03-18 Ross Johnson
+
+ * create.c (pthread_create): add __cdecl attribute to thread routine
+ arg
+ * implement.h (pthread_key_t): add __cdecl attribute to destructor
+ element
+ (ThreadParms): likewise for start element
+ * pthread.h (pthread_create): add __cdecl to prototype start arg
+ (pthread_once): likewise for init_routine arg
+ (pthread_key_create): likewise for destructor arg
+ (ptw32_cleanup_push): replace type of routine arg with previously
+ defined ptw32_cleanup_callback_t
+ * pthread_key_create.c: add __cdecl attribute to destructor arg
+ * pthread_once.c: add __cdecl attribute to init_routine arg
+ * ptw32_threadStart.c (start): add __cdecl to start variable type
+
+
+2011-07-06 Ross Johnson
+
+ * pthread_cond_wait.c (pragma inline_depth): this is almost redundant
+ now nevertheless fixed thei controlling MSC_VER from "< 800" to
+ "< 1400" (i.e. any prior to VC++ 8.0).
+ * pthread_once.ci (pragma inline_depth): Likewise.
+ * pthread_rwlock_timedwrlock.ci (pragma inline_depth): Likewise.
+ * pthread_rwlock_wrlock.ci (pragma inline_depth): Likewise.
+ * sem_timedwait.ci (pragma inline_depth): Likewise.
+ * sem_wait.ci (pragma inline_depth): Likewise.
+
+2011-07-05 Ross Johnson
+
+ * pthread_win32_attach_detach_np.c: Use strncat_s if available
+ to removei a compile warning; MingW supports this routine but we
+ continue to use strncat anyway there because it is secure if
+ given the correct parameters; fix strncat param 3 to avoid
+ buffer overrun exploitation potential.
+
+2011-07-03 Ross Johnson
+
+ * pthread_spin_unlock.c (EPERM): Return success if unlocking a lock
+ that is not locked, because single CPU machines wrap a
+ PTHREAD_MUTEX_NORMAL mutex, which returns success in this case.
+ * pthread_win32_attach_detach_np.c (QUSEREX.DLL): Load from an
+ absolute path only which must be the Windows System folder.
+
+2011-07-03 Daniel Richard G.
+
+ * Makefile (_WIN32_WINNT): Removed; duplicate definition in
+ implement.h; more cleanup and enhancements.
+
+2011-07-02 Daniel Richard G.
+
+ * Makefile: Cleanups and implovements.
+ * ptw32_MCS_locks.c: Casting fixes.
+ * implement.h: Interlocked call and argument casting macro fixes
+ to support older and newer build environments.
+
+2011-07-01 Ross Johnson
+
+ * *.[ch] (PTW32_INTERLOCKED_*): Redo 23 and 64 bit versions of these
+ macros and re-apply in code to undo the incorrect changes from
+ 2011-06-29; remove some size_t casts which should not be required
+ and may be problematic.a
+ There are now two sets of macros:
+ PTW32_INTERLOCKED_*_LONG which work only on 32 bit integer variables;
+ PTW32_INTERLOCKED_*_SIZE which work on size_t integer variables, i.e.
+ LONG for 32 bit systems and LONGLONG for 64 bit systems.
+ * implement.h (MCS locks): nextFlag and waitFlag are now HANDLE type.
+ * ptw32_MCS_locks.c: Likewise.
+ * pthread.h (#include ): Removed.
+ * ptw32_throw.c (#include ): Added.
+ * ptw32_threadStart.c (#include ): Added.
+ * implement.h (#include ): Added.
+
+2011-06-30 Ross Johnson
+
+ * pthread_once.c: Tighten 'if' statement casting; fix interlocked
+ pointer cast for 64 bit compatibility (missed yesterday); remove
+ the superfluous static cleanup routine and call the release routine
+ directly if popped.
+ * create.c (stackSize): Now type size_t.
+ * pthread.h (struct ptw32_thread_t_): Rearrange to fix element alignments.
+
+2011-06-29 Daniel Richard G.
+
+ * ptw32_relmillisecs.c (ftime):
+ _ftime64_s() is only available in MSVC 2005 or later;
+ _ftime64() is available in MinGW or MSVC 2002 or later;
+ _ftime() is always available.
+ * pthread.h (long long): Not defined in older MSVC 6.
+ * implement.h (long long): Likewise.
+ * pthread_getunique_np.c (long long): Likewise.
+
+2011-06-29 Ross Johnson
+
+ * *.[ch] (PTW32_INTERLOCKED_*): These macros should now work for
+ both 32 and 64 bit builds. The MingW versions are all inlined asm
+ while the MSVC versions expand to their Interlocked* or Interlocked*64
+ counterparts appropriately. The argument type have also been changed
+ to cast to the appropriate value or pointer size for the architecture.
+
+2011-05-29 Ross Johnson
+
+ * *.[ch] (#ifdef): Extended cleanup to whole project.
+
+2011-05-29 Daniel Richard G.
+
+ * Makefile (CC): Define CC to allow use of other compatible
+ compilers such as the Intel compilter icl.
+ * implement.h (#if): Fix forms like #if HAVE_SOMETHING.
+ * pthread.h: Likewise.
+ * sched.h: Likewise; PTW32_LEVEL_* becomes PTW32_SCHED_LEVEL_*.
+ * semaphore.h: Likewise.
+
+2011-05-11 Ross Johnson
+
+ * ptw32_callUserDestroyRoutines.c (terminate): Altered includes
+ to match ptw32_threadStart.c.
+ * GNUmakefile (GCE-inlined-debug, DOPT): Fixed.
+
+2011-04-31 Ross Johnson
+
+ * (robust mutexes): Added this API. The API is not
+ mandatory for implementations that don't support PROCESS_SHARED
+ mutexes, nevertheless it was considered useful both functionally
+ and for source-level compatibility.
+
+2011-03-26 Ross Johnson
+
+ * pthread_getunique_np.c: New non-POSIX interface for compatibility
+ with some other implementations; returns a 64 bit sequence number
+ that is unique to each thread in the process.
+ * pthread.h (pthread_getunique_np): Added.
+ * global.c: Add global sequence counter for above.
+ * implement.h: Likewise.
+
+2011-03-25 Ross Johnson
+
+ * (cancelLock): Convert to an MCS lock and rename to stateLock.
+ * (threadLock): Likewise.
+ * (keyLock): Likewise.
+ * pthread_mutex*.c: First working robust mutexes.
+
+2011-03-11 Ross Johnson
+
+ * implement.h (PTW32_INTERLOCKED_*CREMENT macros): increment/decrement
+ using ++/-- instead of add/subtract 1.
+ * ptw32_MCS_lock.c: Make casts consistent.
+
+2011-03-09 Ross Johnson
+
+ * implement.h (ptw32_thread_t_): Add process unique sequence number.
+ * global.c: Replace global Critical Section objects with MCS
+ queue locks.
+ * implement.h: Likewise.
+ * pthread_cond_destroy.c: Likewise.
+ * pthread_cond_init.c: Likewise.
+ * pthread_detach.c: Likewise.
+ * pthread_join.c: Likewise.
+ * pthread_kill.c: Likewise.
+ * pthread_mutex_destroy.c: Likewise.
+ * pthread_rwlock_destroy.c: Likewise.
+ * pthread_spin_destroy.c: Likewise.
+ * pthread_timechange_handler_np.c: Likewise.
+ * ptw32_cond_check_need_init.c: Likewise.
+ * ptw32_mutex_check_need_init.c: Likewise.
+ * ptw32_processInitialize.c: Likewise.
+ * ptw32_processTerminate.c: Likewise.
+ * ptw32_reuse.c: Likewise.
+ * ptw32_rwlock_check_need_init.c: Likewise.
+ * ptw32_spinlock_check_need_init.c: Likewise.
+
+2011-03-06 Ross Johnson
+
+ * several (MINGW64): Cast and call fixups for 64 bit compatibility;
+ clean build via x86_64-w64-mingw32 cross toolchain on Linux i686
+ targeting x86_64 win64.
+ * ptw32_threadStart.c (ptw32_threadStart): Routine no longer attempts
+ to pass [unexpected C++] exceptions out of scope but ends the thread
+ normally setting EINTR as the exit status.
+ * ptw32_throw.c: Fix C++ exception throwing warnings; ignore
+ informational warning.
+ * implement.h: Likewise with the corresponding header definition.
+
+2011-03-04 Ross Johnson
+
+ * implement.h (PTW32_INTERLOCKED_*): Mingw32 does not provide
+ the __sync_* intrinsics so implemented them here as macro
+ assembler routines. MSVS Interlocked* are emmitted as intrinsics
+ wherever possible, so we want mingw to match it; Extended to
+ include all interlocked routines used by the library; implemented
+ x86_64 versions also.
+ * ptw32_InterlockedCompareExchange.c: No code remaining here.
+ * ptw32_MCS_lock.c: Converted interlocked calls to use new macros.
+ * pthread_barrier_wait.c: Likewise.
+ * pthread_once.c: Likewise.
+ * ptw32_MCS_lock.c (ptw32_mcs_node_substitute): Name changed to
+ ptw32_mcs_node_transfer.
+
+2011-02-28 Ross Johnson
+
+ * ptw32_relmillisecs.c: If possible, use _ftime64_s or _ftime64
+ before resorting to _ftime.
+
+2011-02-27 Ross Johnson
+
+ * sched_setscheduler.c: Ensure the handle is closed after use.
+ * sched_getscheduler.c: Likewise.
+ * pthread.h: Remove POSIX compatibility macros; don't define
+ timespec if already defined.
+ * context.h: Changes for 64 bit.
+ * pthread_cancel.c: Likewise.
+ * pthread_exit.c: Likewise.
+ * pthread_spin_destroy.c: Likewise.
+ * pthread_timechange_handler_np.c: Likewise.
+ * ptw32_MCS_lock.c: Likewise; some of these changes may
+ not be compatible with pre Windows 2000 systems; reverse the order of
+ the includes.
+ * ptw32_threadStart.c: Likewise.
+ * ptw32_throw.c: Likewise.
+
+2011-02-13 Ross Johnson
+
+ * pthread_self: Add comment re returning 'nil' value to
+ indicate failure only to win32 threads that call us.
+ * pthread_attr_setstackaddr: Fix comments; note this
+ function and it's compliment are now removed from SUSv4.
+
+2011-02-12 Ross Johnson
+
+ README.NONPORTABLE: Record a description of an obvious
+ method for nulling/comparing/hashing pthread_t using a
+ union; plus and investigation of a change of type for
+ pthread_t (to a union) to neutralise any padding bits and
+ bytes if they occur in pthread_t (the current pthread_t struct
+ does not contain padding AFAIK, but porting the library to a
+ future architecture may introduce them). Padding affects
+ byte-by-byte copies and compare operations.
+
+2010-11-16 Ross Johnson
+
+ * ChangeLog: Add this entry ;-)
+ Restore entries from 2007 through 2009 that went missing
+ at the last update.
+
+2010-06-19 Ross Johnson
+
+ * ptw32_MCS_lock.c (ptw32_mcs_node_substitute): Fix variable
+ names to avoid using C++ keyword ("new").
+ * implement.h (ptw32_mcs_node_substitute): Likewise.
+ * pthread_barrier_wait.c: Fix signed/unsigned comparison warning.
+
+2010-06-18 Ramiro Polla
+
+ * autostatic.c: New file; call pthread_win32_process_*()
+ libary init/cleanup routines automatically on application start
+ when statically linked.
+ * pthread.c (autostatic.c): Included.
+ * pthread.h (declspec): Remove import/export defines if compiler
+ is MINGW.
+ * sched.h (declspec): Likewise.
+ * semaphore.h (declspec): Likewise.
+ * need_errno.h (declspec): Likewise.
+ * Makefile (autostatic.obj): Add for small static builds.
+ * GNUmakefile (autostatic.o): Likewise.
+ * NEWS (Version 2.9.0): Add changes.
+ * README.NONPORTABLE (pthread_win32_process_*): Update
+ description.
+
+2010-06-15 Ramiro Polla
+
+ * Makefile: Remove linkage with the winsock library by default.
+ * GNUmakefile: Likewise.
+ * pthread_getspecific.c: Likewise by removing calls to WSA
+ functions.
+ * config.h (RETAIN_WSALASTERROR): Can be defined if necessary.
+
+2010-01-26 Ross Johnson
+
+ * ptw32_MCS_lock.c (ptw32_mcs_node_substitute): New routine
+ to allow relocating the lock owners thread-local node to somewhere
+ else, e.g. to global space so that another thread can release the
+ lock. Used in pthread_barrier_wait.
+ (ptw32_mcs_lock_try_acquire): New routine.
+ * pthread_barrier_init: Only one semaphore is used now.
+ * pthread_barrier_wait: Added an MCS guard lock with the last thread
+ to leave the barrier releasing the lock. This removes a deadlock bug
+ observed when there are greater than barrier-count threads
+ attempting to cross.
+ * pthread_barrier_destroy: Added an MCS guard lock.
+
+2009-03-03 Stephan O'Farrill
+
+ * pthread_attr_getschedpolicy.c: Add "const" to function parameter
+ in accordance with SUSv3 (POSIX).
+ * pthread_attr_getinheritsched.c: Likewise.
+ * pthread_mutexattr_gettype.c: Likewise.
+
+2008-06-06 Robert Kindred
+
+ * ptw32_throw.c (ptw32_throw): Remove possible reference to NULL
+ pointer. (At the same time made the switch block conditionally
+ included only if exitCode is needed - RPJ.)
+ * pthread_testcancel.c (pthread_testcancel): Remove duplicate and
+ misplaced pthread_mutex_unlock().
+
+2008-02-21 Sebastian Gottschalk
+
+ * pthread_attr_getdetachstate.c (pthread_attr_getdetachstate):
+ Remove potential and superfluous null pointer assignment.
+
+2007-11-22 Ivan Pizhenko
+
+ * pthread.h (gmtime_r): gmtime returns 0 if tm represents a time
+ prior to 1/1/1970. Notice this to prevent raising an exception.
+ * pthread.h (localtime_r): Likewise for localtime.
+
+2007-07-14 Marcel Ruff
+
+ * errno.c (_errno): Fix test for pthread_self() success.
+ * need_errno.h: Remove unintentional line wrap from #if line.
+
+2007-07-14 Mike Romanchuk
+
+ * pthread.h (timespec): Fix tv_sec type.
+
+2007-01-07 Sinan Kaya
+
+ * need_errno.h: Fix declaration of _errno - the local version of
+ _errno() is used, e.g. by WinCE.
+
+2007-01-06 Ross Johnson
+
+ * ptw32_semwait.c: Add check for invalid sem_t after acquiring the
+ sem_t state guard mutex and before affecting changes to sema state.
+
+2007-01-06 Marcel Ruff
+
+ * error.c: Fix reference to pthread handle exitStatus member for
+ builds that use NEED_ERRNO (i.e. WINCE).
+ * context.h: Add support for ARM processor (WinCE).
+ * mutex.c (process.h): Exclude for WINCE.
+ * create.c: Likewise.
+ * exit.c: Likewise.
+ * implement.h: Likewise.
+ * pthread_detach.c (signal.h): Exclude for WINCE.
+ * pthread_join.c: Likewise.
+ * pthread_kill.c: Likewise.
+ * pthread_rwlock_init.c (errno.h): Remove - included by pthread.h.
+ * pthread_rwlock_destroy.c: Likewise.
+ * pthread_rwlock_rdlock.c: Likewise.
+ * pthread_rwlock_timedrdlock.c: Likewise.
+ * pthread_rwlock_timedwrlock.c: Likewise.
+ * pthread_rwlock_tryrdlock.c: Likewise.
+ * pthread_rwlock_trywrlock.c: likewise.
+ * pthread_rwlock_unlock.c: Likewise.
+ * pthread_rwlock_wrlock.c: Likewise.
+ * pthread_rwlockattr_destroy.c: Likewise.
+ * pthread_rwlockattr_getpshared.c: Likewise.
+ * pthread_rwlockattr_init.c: Likewise.
+ * pthread_rwlockattr_setpshared.c: Likewise.
+
+2007-01-06 Romano Paolo Tenca
+
+ * pthread_cond_destroy.c: Replace sem_wait() with non-cancelable
+ ptw32_semwait() since pthread_cond_destroy() is not a cancelation
+ point.
+ * implement.h (ptw32_spinlock_check_need_init): Add prototype.
+ * ptw32_MCS_lock.c: Reverse order of includes.
+
+2007-01-06 Eric Berge
+
+ * pthread_cond_destroy.c: Add LeaveCriticalSection before returning
+ after errors.
+
+2007-01-04 Ross Johnson
+
+ * ptw32_InterlockedCompareExchange.c: Conditionally skip for
+ Win64 as not required.
+ * pthread_win32_attach_detach_np.c (pthread_win32_process_attach_np):
+ Test for InterlockedCompareExchange is not required for Win64.
+ * context.h: New file. Included by pthread_cancel.h and any tests
+ that need it (e.g. context1.c).
+ * pthread_cancel.c: Architecture-dependent context macros moved
+ to context.h.
+
+2007-01-04 Kip Streithorst
+
+ * implement.h (PTW32_INTERLOCKED_COMPARE_EXCHANGE): Add Win64
+ support.
+
+2006-12-20 Ross Johnson
+
+ * sem_destroy.c: Fix the race involving invalidation of the sema;
+ fix incorrect return of EBUSY resulting from the mutex trylock
+ on the private mutex guard.
+ * sem_wait.c: Add check for invalid sem_t after acquiring the
+ sem_t state guard mutex and before affecting changes to sema state.
+ * sem_trywait.c: Likewise.
+ * sem_timedwait.c: Likewise.
+ * sem_getvalue.c: Likewise.
+ * sem_post.c: Similar.
+ * sem_post_multiple.c: Likewise.
+ * sem_init.c: Set max Win32 semaphore count to SEM_VALUE_MAX (was
+ _POSIX_SEM_VALUE_MAX, which is a lower value - the minimum).
+
+ * pthread_win32_attach_detach_np.c (pthread_win32_process_attach_np):
+ Load COREDLL.DLL under WINCE to check existence of
+ InterlockedCompareExchange() routine. This used to be done to test
+ for TryEnterCriticalSection() but was removed when this was no
+ longer needed.
+
+2006-01-25 Prashant Thakre
+
+ * pthread_cancel.c: Added _M_IA64 register context support.
+
+2005-05-13 Ross Johnson
+
+ * pthread_kill.c (pthread_kill): Remove check for Win32 thread
+ priority (to confirm HANDLE validity). Useless since thread HANDLEs
+ a not recycle-unique.
+
+2005-05-30 Vladimir Kliatchko
+
+ * pthread_once.c: Re-implement using an MCS queue-based lock. The form
+ of pthread_once is as proposed by Alexander Terekhov (see entry of
+ 2005-03-13). The MCS lock implementation does not require a unique
+ 'name' to identify the lock between threads. Attempts to get the Event
+ or Semaphore based versions of pthread_once to a satisfactory level
+ of robustness have thus far failed. The last problem (avoiding races
+ involving non recycle-unique Win32 HANDLEs) was giving everyone
+ grey hair trying to solve it.
+
+ * ptw32_MCS_lock.c: New MCS queue-based lock implementation. These
+ locks are efficient: they have very low overhead in the uncontended case;
+ are efficient in contention and minimise cache-coherence updates in
+ managing the user level FIFO queue; do not require an ABI change in the
+ library.
+
+2005-05-27 Alexander Gottwald
+
+ * pthread.h: Some things, like HANDLE, were only defined if
+ PTW32_LEVEL was >= 3. They should always be defined.
+
+2005-05-25 Vladimir Kliatchko
+
+ * pthread_once.c: Eliminate all priority operations and other
+ complexity by replacing the event with a semaphore. The advantage
+ of the change is the ability to release just one waiter if the
+ init_routine thread is cancelled yet still release all waiters when
+ done. Simplify once_control state checks to improve efficiency
+ further.
+
+2005-05-24 Mikael Magnusson
+
+ * GNUmakefile: Patched to allow cross-compile with mingw32 on Linux.
+ It uses macros instead of referencing dlltool, gcc and g++ directly;
+ added a call to ranlib. For example the GC static library can be
+ built with:
+ make CC=i586-mingw32msvc-gcc RC=i586-mingw32msvc-windres \
+ RANLIB=i586-mingw32msvc-ranlib clean GC-static
+
+2005-05-13 Ross Johnson
+
+ * pthread_win32_attach_detach_np.c (pthread_win32_thread_detach_np):
+ Move on-exit-only stuff from ptw32_threadDestroy() to here.
+ * ptw32_threadDestroy.c: It's purpose is now only to reclaim thread
+ resources for detached threads, or via pthread_join() or
+ pthread_detach() on joinable threads.
+ * ptw32_threadStart.c: Calling user destruct routines has moved to
+ pthread_win32_thread_detach_np(); call pthread_win32_thread_detach_np()
+ directly if statically linking, otherwise do so via dllMain; store
+ thread return value in thread struct for all cases, including
+ cancellation and exception exits; thread abnormal exits go via
+ pthread_win32_thread_detach_np.
+ * pthread_join.c (pthread_join): Don't try to get return code from
+ Win32 thread - always get it from he thread struct.
+ * pthread_detach.c (pthread_detach): reduce extent of the thread
+ existence check since we now don't care if the Win32 thread HANDLE has
+ been closed; reclaim thread resources if the thread has exited already.
+ * ptw32_throw.c (ptw32_throw): For Win32 threads that are not implicit,
+ only Call thread cleanup if statically linking, otherwise leave it to
+ dllMain.
+ * sem_post.c (_POSIX_SEM_VALUE_MAX): Change to SEM_VALUE_MAX.
+ * sem_post_multiple.c: Likewise.
+ * sem_init.c: Likewise.
+
+2005-05-10 Ross Johnson
+
+ * pthread_join.c (pthread_join): Add missing check for thread ID
+ reference count in thread existence test; reduce extent of the
+ existence test since we don't care if the Win32 thread HANDLE has
+ been closed.
+
+2005-05-09 Ross Johnson
+
+ * ptw32_callUserDestroyRoutines.c: Run destructor process (i.e.
+ loop over all keys calling destructors) up to
+ PTHREAD_DESTRUCTOR_ITERATIONS times if TSD value isn't NULL yet;
+ modify assoc management.
+ * pthread_key_delete.c: Modify assoc management.
+ * ptw32_tkAssocDestroy.c: Fix error in assoc removal from chains.
+ * pthread.h
+ (_POSIX_THREAD_DESTRUCTOR_ITERATIONS): Define to value specified by
+ POSIX.
+ (_POSIX_THREAD_KEYS_MAX): Define to value specified by POSIX.
+ (PTHREAD_KEYS_MAX): Redefine [upward] to minimum required by POSIX.
+ (SEM_NSEMS_MAX): Define to implementation value.
+ (SEM_VALUE_MAX): Define to implementation value.
+ (_POSIX_SEM_NSEMS_MAX): Redefine to value specified by POSIX.
+ (_POSIX_SEM_VALUE_MAX): Redefine to value specified by POSIX.
+
+2005-05-06 Ross Johnson
+
+ * signal.c (sigwait): Add a cancellation point to this otherwise
+ no-op.
+ * sem_init.c (sem_init): Check for and return ERANGE error.
+ * sem_post.c (sem_post): Likewise.
+ * sem_post_multiple.c (sem_post_multiple): Likewise.
+ * manual (directory): Added; see ChangeLog inside.
+
+2005-05-02 Ross Johnson
+
+ * implement.h (struct pthread_key_t_): Change threadsLock to keyLock
+ so as not to be confused with the per thread lock 'threadlock';
+ change all references to it.
+ * implement.h (struct ThreadKeyAssoc): Remove lock; add prevKey
+ and prevThread pointers; re-implemented all routines that use this
+ struct. The effect of this is to save one handle per association,
+ which could potentially equal the number of keys multiplied by the
+ number of threads, accumulating over time - and to free the
+ association memory as soon as it is no longer referenced by either
+ the key or the thread. Previously, the handle and memory were
+ released only after BOTH key and thread no longer referenced the
+ association. That is, often no association resources were released
+ until the process itself exited. In addition, at least one race
+ condition has been removed - where two threads could attempt to
+ release the association resources simultaneously - one via
+ ptw32_callUserDestroyRoutines and the other via
+ pthread_key_delete.
+ - thanks to Richard Hughes at Aculab for discovering the problem.
+ * pthread_key_create.c: See above.
+ * pthread_key_delete.c: See above.
+ * pthread_setspecific.c: See above.
+ * ptw32_callUserDestroyRoutines.c: See above.
+ * ptw32_tkAssocCreate.c: See above.
+ * ptw32_tkAssocDestroy.c: See above.
+
+2005-04-27 Ross Johnson
+
+ * sem_wait.c (ptw32_sem_wait_cleanup): after cancellation re-attempt
+ to acquire the semaphore to avoid a race with a late sem_post.
+ * sem_timedwait.c: Modify comments.
+
+2005-04-25 Ross Johnson
+
+ * ptw32_relmillisecs.c: New module; converts future abstime to
+ milliseconds relative to 'now'.
+ * pthread_mutex_timedlock.c: Use new ptw32_relmillisecs routine in
+ place of internal code; remove the NEED_SEM code - this routine is now
+ implemented for builds that define NEED_SEM (WinCE etc)
+ * sem_timedwait.c: Likewise; after timeout or cancellation,
+ re-attempt to acquire the semaphore in case one has been posted since
+ the timeout/cancel occurred. Thanks to Stefan Mueller.
+ * Makefile: Add ptw32_relmillisecs.c module; remove
+ ptw32_{in,de}crease_semaphore.c modules.
+ * GNUmakefile: Likewise.
+ * Bmakefile: Likewise.
+
+ * sem_init.c: Re-write the NEED_SEM code to be consistent with the
+ non-NEED_SEM code, but retaining use of an event in place of the w32 sema
+ for w32 systems that don't include semaphores (WinCE);
+ the NEED_SEM versions of semaphores has been broken for a long time but is
+ now fixed and supports all of the same routines as the non-NEED_SEM case.
+ * sem_destroy.c: Likewise.
+ * sem_wait.c: Likewise.
+ * sem_post.c: Likewise.
+ * sem_post_multple.c: Likewise.
+ * implement.h: Likewise.
+ * sem_timedwait.c: Likewise; this routine is now
+ implemented for builds that define NEED_SEM (WinCE etc).
+ * sem_trywait.c: Likewise.
+ * sem_getvalue.c: Likewise.
+
+ * pthread_once.c: Yet more changes, reverting closer to Gottlob Frege's
+ first design, but retaining cancellation, priority boosting, and adding
+ preservation of W32 error codes to make pthread_once transparent to
+ GetLastError.
+
+2005-04-11 Ross Johnson
+
+ * pthread_once.c (pthread_once): Added priority boosting to
+ solve starvation problem after once_routine cancellation.
+ See notes in file.
+
+2005-04-06 Kevin Lussier
+
+ * Makefile: Added debug targets for all versions of the library.
+
+2005-04-01 Ross Johnson
+
+ * GNUmakefile: Add target to build libpthreadGC1.a as a static link
+ library.
+ * Makefile: Likewise for pthreadGC1.lib.
+
+2005-04-01 Kevin Lussier
+
+ * sem_timedwait.c (sem_timedwait): Increase size of temp variables to
+ avoid int overflows for large timeout values.
+ * implement.h (int64_t): Include or define.
+
+2005-03-31 Dimitar Panayotov ^M
+
+ * pthread.h: Fix conditional defines for static linking.
+ * sched.h: Liekwise.
+ * semaphore.h: Likewise.
+ * dll.c (PTW32_STATIC_LIB): Module is conditionally included
+ in the build.
+
+2005-03-16 Ross Johnson ^M
+
+ * pthread_setcancelstate.c: Undo the last change.
+
+2005-03-16 Ross Johnson ^M
+
+ * pthread_setcancelstate.c: Don't check for an async cancel event
+ if the library is using alertable async cancel..
+
+2005-03-14 Ross Johnson
+
+ * pthread_once.c (pthread_once): Downgrade interlocked operations to simple
+ memory operations where these are protected by the critical section; edit
+ comments.
+
+2005-03-13 Ross Johnson
+
+ * pthread_once.c (pthread_once): Completely redesigned; a change was
+ required to the ABI (pthread_once_t_), and resulting in a version
+ compatibility index increment.
+
+ NOTES:
+ The design (based on pseudo code contributed by Gottlob Frege) avoids
+ creating a kernel object if there is no contention. See URL for details:-
+ http://sources.redhat.com/ml/pthreads-win32/2005/msg00029.html
+ This uses late initialisation similar to the technique already used for
+ pthreads-win32 mutexes and semaphores (from Alexander Terekhov).
+
+ The subsequent cancelation cleanup additions (by rpj) could not be implemented
+ without sacrificing some of the efficiency in Gottlob's design. In particular,
+ although each once_control uses it's own event to block on, a global CS is
+ required to manage it - since the event must be either re-usable or
+ re-creatable under cancelation. This is not needed in the non-cancelable
+ design because it is able to mark the event as closed (forever).
+
+ When uncontested, a CS operation is equivalent to an Interlocked operation
+ in speed. So, in the final design with cancelability, an uncontested
+ once_control operation involves a minimum of five interlocked operations
+ (including the LeaveCS operation).
+
+ ALTERNATIVES:
+ An alternative design from Alexander Terekhov proposed using a named mutex,
+ as sketched below:-
+
+ if (!once_control) { // May be in TLS
+ named_mutex::guard guard(&once_control2);
+ if (!once_control2) {
+
+ once_control2 = true;
+ }
+ once_control = true;
+ }
+
+ A more detailed description of this can be found here:-
+ http://groups.yahoo.com/group/boost/message/15442
+
+ [Although the definition of a suitable PTHREAD_ONCE_INIT precludes use of the
+ TLS located flag, this is not critical.]
+
+ There are three primary concerns though:-
+ 1) The [named] mutex is 'created' even in the uncontended case.
+ 2) A system wide unique name must be generated.
+ 3) Win32 mutexes are VERY slow even in the uncontended case. An uncontested
+ Win32 mutex lock operation can be 50 (or more) times slower than an
+ uncontested EnterCS operation.
+
+ Ultimately, the named mutex trick is making use of the global locks maintained
+ by the kernel.
+
+ * pthread.h (pthread_once_t_): One flag and an event HANDLE added.
+ (PTHREAD_ONCE_INIT): Additional values included.
+
+2005-03-08 Ross Johnson
+
+ * pthread_once.c (pthread_once): Redesigned to elliminate potential
+ starvation problem.
+ - reported by Gottlob Frege
+
+ * ptw32_threadDestroy.c (ptw32_threadDestroy): Implicit threads were
+ not closing their Win32 thread duplicate handle.
+ - reported by Dmitrii Semii
+
+2005-01-25 Ralf Kubis
+
+ * Attempted acquisition of recursive mutex was causing waiting
+ threads to not be woken when the mutex is released.
+
+ * GNUmakefile (GCE): Generate correct version resource comments.
+
+2005-01-01 Konstantin Voronkov
+
+ * pthread_mutex_lock.c (pthread_mutex_lock): The new atomic exchange
+ mutex algorithm is known to allow a thread to steal the lock off
+ FIFO waiting threads. The next waiting FIFO thread gets a spurious
+ wake-up and must attempt to re-acquire the lock. The woken thread
+ was setting itself as the mutex's owner before the re-acquisition.
+
+2004-11-22 Ross Johnson
+
+ * pthread_cond_wait.c (ptw32_cond_wait_cleanup): Undo change
+ from 2004-11-02.
+ * Makefile (DLL_VER): Added for DLL naming suffix - see README.
+ * GNUmakefile (DLL_VER): Likewise.
+ * Wmakefile (DLL_VER): Likewise.
+ * Bmakefile (DLL_VER): Likewise.
+ * pthread.dsw (version.rc): Added to MSVS workspace.
+
+2004-11-20 Boudewijn Dekker
+
+ * pthread_getspecific.c (pthread_getspecific): Check for
+ invalid (NULL) key argument.
+
+2004-11-19 Ross Johnson
+
+ * config.h (PTW32_THREAD_ID_REUSE_INCREMENT): Added to allow
+ building the library for either unique thread IDs like Solaris
+ or non-unique thread IDs like Linux; allows application developers
+ to override the library's default insensitivity to some apps
+ that may not be strictly POSIX compliant.
+ * version.rc: New resource module to encode version information
+ within the DLL.
+ * pthread.h: Added PTW32_VERSION* defines and grouped sections
+ required by resource compiler together; bulk of file is skipped
+ if RC_INVOKED. Defined some error numbers and other names for
+ Borland compiler.
+
+2004-11-02 Ross Johnson
+
+ * pthread_cond_wait.c (ptw32_cond_wait_cleanup): Lock CV mutex at
+ start of cleanup handler rather than at the end.
+ * implement.h (PTW32_THREAD_REUSE_EMPTY): Renamed from *_BOTTOM.
+ (ptw32_threadReuseBottom): New global variable.
+ * global.c (ptw32_threadReuseBottom): Declare new variable.
+ * ptw32_reuse.c (ptw32_reuse): Change reuse LIFO stack to LILO queue
+ to more evenly distribute use of reusable thread IDs; use renamed
+ PTW32_THREAD_REUSE_EMPTY.
+ * ptw32_processTerminate.c (ptw2_processTerminate): Use renamed
+ PTW32_THREAD_REUSE_EMPTY.
+
+2004-10-31 Ross Johnson
+
+ * implement.h (PThreadState): Add new state value
+ 'PThreadStateCancelPending'.
+ * pthread_testcancel.c (pthread_testcancel): Use new thread
+ 'PThreadStateCancelPending' state as short cut to avoid entering
+ kernel space via WaitForSingleObject() call. This was obviated
+ by user space sema acquisition in sem_wait() and sem_timedwait(),
+ which are also cancelation points. A call to pthread_testcancel()
+ was required, which introduced a kernel call, effectively nullifying
+ any gains made by the user space sem acquisition checks.
+ * pthread_cancel.c (pthread_cancel): Set new thread
+ 'PThreadStateCancelPending' state.
+
+2004-10-29 Ross Johnson
+
+ * implement.h (pthread_t): Renamed to ptw32_thread_t; struct contains
+ all thread state.
+ * pthread.h (ptw32_handle_t): New general purpose struct to serve
+ as a handle for various reusable object IDs - currently only used
+ by pthread_t; contains a pointer to ptw32_thread_t (thread state)
+ and a general purpose uint for use as a reuse counter or flags etc.
+ (pthread_t): typedef'ed to ptw32_handle_t; the uint is the reuse
+ counter that allows the library to maintain unique POSIX thread IDs.
+ When the pthread struct reuse stack was introduced, threads would
+ often acquire an identical ID to a previously destroyed thread. The
+ same was true for the pre-reuse stack library, by virtue of pthread_t
+ being the address of the thread struct. The new pthread_t retains
+ the reuse stack but provides virtually unique thread IDs.
+ * sem_wait.c (ptw32_sem_wait_cleanup): New routine used for
+ cancelation cleanup.
+ * sem_timedwait.c (ptw32_sem_timedwait_cleanup): Likewise.
+
+2004-10-22 Ross Johnson
+
+ * sem_init.c (sem_init): Introduce a 'lock' element in order to
+ replace the interlocked operations with conventional serialisation.
+ This is needed in order to be able to atomically modify the sema
+ value and perform Win32 sema release operations. Win32 semaphores are
+ used instead of events in order to support efficient multiple posting.
+ If the whole modify/release isn't atomic, a race between
+ sem_timedwait() and sem_post() could result in a release when there is
+ no waiting semaphore, which would cause too many threads to proceed.
+ * sem_wait.c (sem_wait): Use new 'lock'element.
+ * sem_timedwait.c (sem_timedwait): Likewise.
+ * sem_trywait.c (sem_trywait): Likewise.
+ * sem_post.c (sem_post): Likewise.
+ * sem_post_multiple.c (sem_post_multiple): Likewise.
+ * sem_getvalue.c (sem_getvalue): Likewise.
+ * ptw32_semwait.c (ptw32_semwait): Likewise.
+ * sem_destroy.c (sem_destroy): Likewise; also tightened the conditions
+ for semaphore destruction; in particular, a semaphore will not be
+ destroyed if it has waiters.
+ * sem_timedwait.c (sem_timedwait): Added cancel cleanup handler to
+ restore sema value when cancelled.
+ * sem_wait.c (sem_wait): Likewise.
+
+2004-10-21 Ross Johnson
+
+ * pthread_mutex_unlock.c (pthread_mutex_unlock): Must use PulseEvent()
+ rather than SetEvent() to reset the event if there are no waiters.
+
+2004-10-19 Ross Johnson
+
+ * sem_init.c (sem_init): New semaphore model based on the same idea
+ as mutexes, i.e. user space interlocked check to avoid
+ unnecessarily entering kernel space. Wraps the Win32 semaphore and
+ keeps it's own counter. Although the motivation to do this has existed
+ for a long time, credit goes to Alexander Terekhov for providing
+ the logic. I have deviated slightly from AT's logic to add the waiters
+ count, which has made the code more complicated by adding cancelation
+ cleanup. This also appears to have broken the VCE (C++ EH) version of
+ the library (the same problem as previously reported - see BUGS #2),
+ only apparently not fixable using the usual workaround, nor by turning
+ all optimisation off. The GCE version works fine, so it is presumed to
+ be a bug in MSVC++ 6.0. The cancelation exception is thrown and caught
+ correctly, but the cleanup class destructor is never called. The failing
+ test is tests\semaphore4.c.
+ * sem_wait.c (sem_wait): Implemented user space check model.
+ * sem_post.c (sem_post): Likewise.
+ * sem_trywait.c (sem_trywait): Likewise.
+ * sem_timedwait.c (sem_timedwait): Likewise.
+ * sem_post_multiple.c (sem_post_multiple): Likewise.
+ * sem_getvalue.c (sem_getvalue): Likewise.
+ * ptw32_semwait.c (ptw32_semwait): Likewise.
+ * implement.h (sem_t_): Add counter element.
+
+2004-10-15 Ross Johnson
+
+ * implement.h (pthread_mutex_t_): Use an event in place of
+ the POSIX semaphore.
+ * pthread_mutex_init.c: Create the event; remove semaphore init.
+ * pthread_mutex_destroy.c: Delete the event.
+ * pthread_mutex_lock.c: Replace the semaphore wait with the event wait.
+ * pthread_mutex_trylock.c: Likewise.
+ * pthread_mutex_timedlock.c: Likewise.
+ * pthread_mutex_unlock.c: Set the event.
+
+2004-10-14 Ross Johnson
+
+ * pthread_mutex_lock.c (pthread_mutex_lock): New algorithm using
+ Terekhov's xchg based variation of Drepper's cmpxchg model.
+ Theoretically, xchg uses fewer clock cycles than cmpxchg (using IA-32
+ as a reference), however, in my opinion bus locking dominates the
+ equation on smp systems, so the model with the least number of bus
+ lock operations in the execution path should win, which is Terekhov's
+ variant. On IA-32 uni-processor systems, it's faster to use the
+ CMPXCHG instruction without locking the bus than to use the XCHG
+ instruction, which always locks the bus. This makes the two variants
+ equal for the non-contended lock (fast lane) execution path on up
+ IA-32. Testing shows that the xchg variant is faster on up IA-32 as
+ well if the test forces higher lock contention frequency, even though
+ kernel calls should be dominating the times (on up IA-32, both
+ variants used CMPXCHG instructions and neither locked the bus).
+ * pthread_mutex_timedlock.c pthread_mutex_timedlock(): Similarly.
+ * pthread_mutex_trylock.c (pthread_mutex_trylock): Similarly.
+ * pthread_mutex_unlock.c (pthread_mutex_unlock): Similarly.
+ * ptw32_InterlockedCompareExchange.c (ptw32_InterlockExchange): New
+ function.
+ (PTW32_INTERLOCKED_EXCHANGE): Sets up macro to use inlined
+ ptw32_InterlockedExchange.
+ * implement.h (PTW32_INTERLOCKED_EXCHANGE): Set default to
+ InterlockedExchange().
+ * Makefile: Building using /Ob2 so that asm sections within inline
+ functions are inlined.
+
+2004-10-08 Ross Johnson
+
+ * pthread_mutex_destroy.c (pthread_mutex_destroy): Critical Section
+ element is no longer required.
+ * pthread_mutex_init.c (pthread_mutex_init): Likewise.
+ * pthread_mutex_lock.c (pthread_mutex_lock): New algorithm following
+ Drepper's paper at http://people.redhat.com/drepper/futex.pdf, but
+ using the existing semaphore in place of the futex described in the
+ paper. Idea suggested by Alexander Terekhov - see:
+ http://sources.redhat.com/ml/pthreads-win32/2003/msg00108.html
+ * pthread_mutex_timedlock.c pthread_mutex_timedlock(): Similarly.
+ * pthread_mutex_trylock.c (pthread_mutex_trylock): Similarly.
+ * pthread_mutex_unlock.c (pthread_mutex_unlock): Similarly.
+ * pthread_barrier_wait.c (pthread_barrier_wait): Use inlined version
+ of InterlockedCompareExchange() if possible - determined at
+ build-time.
+ * pthread_spin_destroy.c pthread_spin_destroy(): Likewise.
+ * pthread_spin_lock.c pthread_spin_lock():Likewise.
+ * pthread_spin_trylock.c (pthread_spin_trylock):Likewise.
+ * pthread_spin_unlock.c (pthread_spin_unlock):Likewise.
+ * ptw32_InterlockedCompareExchange.c: Sets up macro for inlined use.
+ * implement.h (pthread_mutex_t_): Remove Critical Section element.
+ (PTW32_INTERLOCKED_COMPARE_EXCHANGE): Set to default non-inlined
+ version of InterlockedCompareExchange().
+ * private.c: Include ptw32_InterlockedCompareExchange.c first for
+ inlining.
+ * GNUmakefile: Add commandline option to use inlined
+ InterlockedCompareExchange().
+ * Makefile: Likewise.
+
+2004-09-27 Ross Johnson
+
+ * pthread_mutex_lock.c (pthread_mutex_lock): Separate
+ PTHREAD_MUTEX_NORMAL logic since we do not need to keep or check some
+ state required by other mutex types; do not check mutex pointer arg
+ for validity - leave this to the system since we are only checking
+ for NULL pointers. This should improve speed of NORMAL mutexes and
+ marginally improve speed of other type.
+ * pthread_mutex_trylock.c (pthread_mutex_trylock): Likewise.
+ * pthread_mutex_unlock.c (pthread_mutex_unlock): Likewise; also avoid
+ entering the critical section for the no-waiters case, with approx.
+ 30% reduction in lock/unlock overhead for this case.
+ * pthread_mutex_timedlock.c (pthread_mutex_timedlock): Likewise; also
+ no longer keeps mutex if post-timeout second attempt succeeds - this
+ will assist applications that wish to impose strict lock deadlines,
+ rather than simply to escape from frozen locks.
+
+2004-09-09 Tristan Savatier
+ * pthread.h (struct pthread_once_t_): Qualify the 'done' element
+ as 'volatile'.
+ * pthread_once.c: Concerned about possible race condition,
+ specifically on MPU systems re concurrent access to multibyte types.
+ [Maintainer's note: the race condition is harmless on SPU systems
+ and only a problem on MPU systems if concurrent access results in an
+ exception (presumably generated by a hardware interrupt). There are
+ other instances of similar harmless race conditions that have not
+ been identified as issues.]
+
+2004-09-09 Ross Johnson
+
+ * pthread.h: Declare additional types as volatile.
+
+2004-08-27 Ross Johnson
+
+ * pthread_barrier_wait.c (pthread_barrier_wait): Remove excessive code
+ by substituting the internal non-cancelable version of sem_wait
+ (ptw32_semwait).
+
+2004-08-25 Ross Johnson
+
+ * pthread_join.c (pthread_join): Rewrite and re-order the conditional
+ tests in an attempt to improve efficiency and remove a race
+ condition.
+
+2004-08-23 Ross Johnson
+
+ * create.c (pthread_create): Don't create a thread if the thread
+ id pointer location (first arg) is inaccessible. A memory
+ protection fault will result if the thread id arg isn't an accessible
+ location. This is consistent with GNU/Linux but different to
+ Solaris or MKS (and possibly others), which accept NULL as meaning
+ 'don't return the created thread's ID'. Applications that run
+ using pthreads-win32 will run on all other POSIX threads
+ implementations, at least w.r.t. this feature.
+
+ It was decided not to copy the Solaris et al behaviour because,
+ although it would have simplified some application porting (but only
+ from Solaris to Windows), the feature is not technically necessary,
+ and the alternative segfault behaviour helps avoid buggy application
+ code.
+
+2004-07-01 Anuj Goyal
+
+ * builddmc.bat: New; Windows bat file to build the library.
+ * config.h (__DMC__): Support for Digital Mars compiler.
+ * create.c (__DMC__): Likewise.
+ * pthread_exit.c (__DMC__): Likewise.
+ * pthread_join.c (__DMC__): Likewise.
+ * ptw32_threadDestroy.c (__DMC__): Likewise.
+ * ptw32_threadStart.c (__DMC__): Likewise.
+ * ptw32_throw.c (__DMC__): Likewise.
+
+2004-06-29 Anuj Goyal
+
+ * pthread.h (__DMC__): Initial support for Digital Mars compiler.
+
+2004-06-29 Will Bryant
+
+ * README.Borland: New; description of Borland changes.
+ * Bmakefile: New makefile for the Borland make utility.
+ * ptw32_InterlockedCompareExchange.c:
+ Add Borland compatible asm code.
+
+2004-06-26 Jason Bard
+
+ * pthread.h (HAVE_STRUCT_TIMESPEC): If undefined, define it
+ to avoid timespec struct redefined errors elsewhere in an
+ application.
+
+2004-06-21 Ross Johnson
+
+ * pthread.h (PTHREAD_RECURSIVE_MUTEX_INITIALIZER): Mutex
+ initialiser added for compatibility with Linux threads and
+ others; currently not included in SUSV3.
+ * pthread.h (PTHREAD_ERRORCHECK_MUTEX_INITIALIZER): Likewise.
+ * pthread.h (PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP): Likewise.
+ * pthread.h (PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP): Likewise.
+
+ * ptw32_mutex_check_need_init.c (ptw32_mutex_check_need_init):
+ Add new initialisers.
+
+ * pthread_mutex_lock.c (pthread_mutex_lock): Check for new
+ initialisers.
+ * pthread_mutex_trylock.c (pthread_mutex_trylock): Likewise.
+ * pthread_mutex_timedlock.c (pthread_mutex_timedlock): Likewise.
+ * pthread_mutex_unlock.c (pthread_mutex_unlock): Likewise.
+ * pthread_mutex_destroy.c (pthread_mutex_destroy): Likewise.
+
+2004-05-20 Ross Johnson
+
+ * README.NONPORTABLE: Document pthread_win32_test_features_np().
+ * FAQ: Update various answers.
+
+2004-05-19 Ross Johnson
+
+ * Makefile: Don't define _WIN32_WINNT on compiler command line.
+ * GNUmakefile: Likewise.
+
+2004-05-16 Ross Johnson
+
+ * pthread_cancel.c (pthread_cancel): Adapted to use auto-detected
+ QueueUserAPCEx features at run-time.
+ (ptw32_RegisterCancelation): Drop in replacement for QueueUserAPCEx()
+ if it can't be used. Provides older style non-preemptive async
+ cancelation.
+ * pthread_win32_attach_detach_np.c (pthread_win32_attach_np):
+ Auto-detect quserex.dll and the availability of alertdrv.sys;
+ initialise and close on process attach/detach.
+ * global.c (ptw32_register_cancelation): Pointer to either
+ QueueUserAPCEx() or ptw32_RegisterCancelation() depending on
+ availability. QueueUserAPCEx makes pre-emptive async cancelation
+ possible.
+ * implement.h: Add definitions and prototypes related to QueueUserAPC.
+
+2004-05-16 Panagiotis E. Hadjidoukas
+
+ * QueueUserAPCEx (separate contributed package): Provides preemptive
+ APC feature.
+ * pthread_cancel.c (pthread_cancel): Initial integration of
+ QueueUserAPCEx into pthreads-win32 to provide true pre-emptive
+ async cancelation of threads, including blocked threads.
+
+2004-05-06 Makoto Kato
+
+ * pthread.h (DWORD_PTR): Define typedef for older MSVC.
+ * pthread_cancel.c (AMD64): Add architecture specific Context register.
+ * ptw32_getprocessors.c: Use correct types (DWORD_PTR) for mask
+ variables.
+
+2004-04-06 P. van Bruggen
+
+ * ptw32_threadDestroy.c: Destroy threadLock mutex to
+ close a memory leak.
+
+2004-02-13 Gustav Hallberg
+
+ * pthread_equal.c: Remove redundant equality logic.
+
+2003-12-10 Philippe Di Cristo
+
+ * sem_timedwait.c (sem_timedwait): Fix timeout calculations.
+
+2003-10-20 Alexander Terekhov
+
+ * pthread_mutex_timedlock.c (ptw32_semwait): Move to individual module.
+ * ptw32_semwait.c: New module.
+ * pthread_cond_wait.c (ptw32_cond_wait_cleanup): Replace cancelable
+ sem_wait() call with non-cancelable ptw32_semwait() call.
+ * pthread.c (private.c): Re-order for inlining. GNU C warned that
+ function ptw32_semwait() was defined 'inline' after it was called.
+ * pthread_cond_signal.c (ptw32_cond_unblock): Likewise.
+ * pthread_delay_np.c: Disable Watcom warning with comment.
+ * *.c (process.h): Remove include from .c files. This is conditionally
+ included by the common project include files.
+
+2003-10-20 James Ewing
+
+ * ptw32_getprocessors.c: Some Win32 environments don't have
+ GetProcessAffinityMask(), so always return CPU count = 1 for them.
+ * config.h (NEED_PROCESSOR_AFFINITY_MASK): Define for WinCE.
+
+2003-10-15 Ross Johnson
+
+ * Re-indented all .c files using default GNU style to remove assorted
+ editor ugliness (used GNU indent utility in default style).
+
+2003-10-15 Alex Blanco
+
+ * sem_init.c (sem_init): Would call CreateSemaphore even if the sema
+ struct calloc failed; was not freeing calloced memory if either
+ CreateSemaphore or CreateEvent failed.
+
+2003-10-14 Ross Johnson
+
+ * pthread.h: Add Watcom compiler compatibility. Esssentially just add
+ the cdecl attribute to all exposed function prototypes so that Watcom
+ generates function call code compatible with non-Watcom built libraries.
+ By default, Watcom uses registers to pass function args if possible rather
+ than pushing to stack.
+ * semaphore.h: Likewise.
+ * sched.h: Likewise.
+ * pthread_cond_wait.c (ptw32_cond_wait_cleanup): Define with cdecl attribute
+ for Watcom compatibility. This routine is called via pthread_cleanup_push so
+ it had to match function arg definition.
+ * Wmakefile: New makefile for Watcom builds.
+
+2003-09-14 Ross Johnson
+
+ * pthread_setschedparam.c (pthread_setschedparam): Attempt to map
+ all priority levels between max and min (as returned by
+ sched_get_priority_min/max) to reasonable Win32 priority levels - i.e.
+ levels between THREAD_PRIORITY_LOWEST/IDLE to THREAD_PRIORITY_LOWEST and
+ between THREAD_PRIORITY_HIGHEST/TIME_CRITICAL to THREAD_PRIORITY_HIGHEST
+ while others remain unchanged; record specified thread priority level
+ for return by pthread_getschedparam.
+
+ Note that, previously, specified levels not matching Win32 priority levels
+ would silently leave the current thread priority unaltered.
+
+ * pthread_getschedparam.c (pthread_getschedparam): Return the priority
+ level specified by the latest pthread_setschedparam or pthread_create rather
+ than the actual running thread priority as returned by GetThreadPriority - as
+ required by POSIX. I.e. temporary or adjusted actual priority levels are not
+ returned by this routine.
+
+ * pthread_create.c (pthread_create): For priority levels specified via
+ pthread attributes, attempt to map all priority levels between max and
+ min (as returned by sched_get_priority_min/max) to reasonable Win32
+ priority levels; record priority level given via attributes, or
+ inherited from parent thread, for later return by pthread_getschedparam.
+
+ * ptw32_new.c (ptw32_new): Initialise pthread_t_ sched_priority element.
+
+ * pthread_self.c (pthread_self): Set newly created implicit POSIX thread
+ sched_priority to Win32 thread's current actual priority. Temporarily
+ altered priorities can't be avoided in this case.
+
+ * implement.h (struct pthread_t_): Add new sched_priority element.
+
+2003-09-12 Ross Johnson
+
+ * sched_get_priority_min.c (sched_get_priority_min): On error should return -1
+ with errno set.
+ * sched_get_priority_max.c (sched_get_priority_max): Likewise.
+
+2003-09-03 Ross Johnson
+
+ * w32_cancelableWait.c (ptw32_cancelable_wait): Allow cancelation
+ of implicit POSIX threads as well.
+
+2003-09-02 Ross Johnson
+
+ * pthread_win32_attach_detach_np.c (pthread_win32_thread_detach_np):
+ Add comment.
+
+ * pthread_exit.c (pthread_exit): Fix to recycle the POSIX thread handle in
+ addition to calling user TSD destructors. Move the implicit POSIX thread exit
+ handling to ptw32_throw to centralise the logic.
+
+ * ptw32_throw.c (ptw32_throw): Implicit POSIX threads have no point
+ to jump or throw to, so cleanup and exit the thread here in this case. For
+ processes using the C runtime, the exit code will be set to the POSIX
+ reason for the throw (i.e. PTHREAD_CANCEL or the value given to pthread_exit).
+ Note that pthread_exit() already had similar logic, which has been moved to
+ here.
+
+ * ptw32_threadDestroy.c (ptw32_threadDestroy): Don't close the Win32 handle
+ of implicit POSIX threads - expect this to be done by Win32?
+
+2003-09-01 Ross Johnson
+
+ * pthread_self.c (pthread_self): The newly aquired pthread_t must be
+ assigned to the reuse stack, not freed, if the routine fails somehow.
+
+2003-08-13 Ross Johnson
+
+ * pthread_getschedparam.c (pthread_getschedparam): An invalid thread ID
+ parameter was returning an incorrect error value; now uses a more exhaustive
+ check for validity.
+
+ * pthread_setschedparam.c (pthread_setschedparam): Likewise.
+
+ * pthread_join.c (pthread_join): Now uses a more exhaustive
+ check for validity.
+
+ * pthread_detach.c (pthread_detach): Likewise.
+
+ * pthread_cancel.c (pthread_cancel): Likewise.
+
+ * ptw32_threadDestroy.c (ptw32_threadDestroy): pthread_t structs are
+ never freed - push them onto a stack for reuse.
+
+ * ptw32_new.c (ptw32_new): Check for reusable pthread_t before dynamically
+ allocating new memory for the struct.
+
+ * pthread_kill.c (pthread_kill): New file; new routine; takes only a zero
+ signal arg so that applications can check the thread arg for validity; checks
+ that the underlying Win32 thread HANDLE is valid.
+
+ * pthread.h (pthread_kill): Add prototype.
+
+ * ptw32_reuse.c (ptw32_threadReusePop): New file; new routine; pop a
+ pthread_t off the reuse stack. pthread_t_ structs that have been destroyed, i.e.
+ have exited detached or have been joined, are cleaned up and put onto a reuse
+ stack. Consequently, thread IDs are no longer freed once calloced. The library
+ will attempt to get a struct off this stack before asking the system to alloc
+ new memory when creating threads. The stack is guarded by a global mutex.
+ (ptw32_threadReusePush): New routine; push a pthread_t onto the reuse stack.
+
+ * implement.h (ptw32_threadReusePush): Add new prototype.
+ (ptw32_threadReusePop): Likewise.
+ (pthread_t): Add new element.
+
+ * ptw32_processTerminate.c (ptw32_processTerminate): Delete the thread
+ reuse lock; free all thread ID structs on the thread reuse stack.
+
+ * ptw32_processInitialize.c (ptw32_processInitialize): Initialise the
+ thread reuse lock.
+
+2003-07-19 Ross Johnson
+
+ * GNUmakefile: modified to work under MsysDTK environment.
+ * pthread_spin_lock.c (pthread_spin_lock): Check for NULL arg.
+ * pthread_spin_unlock.c (pthread_spin_unlock): Likewise.
+ * pthread_spin_trylock.c (pthread_spin_trylock): Likewise;
+ fix incorrect pointer value if lock is dynamically initialised by
+ this function.
+ * sem_init.c (sem_init): Initialise sem_t value to quell compiler warning.
+ * sem_destroy.c (sem_destroy): Likewise.
+ * ptw32_threadStart.c (non-MSVC code sections): Include rather
+ than old-style ; fix all std:: namespace entities such as
+ std::terminate_handler instances and associated methods.
+ * ptw32_callUserDestroyRoutines.c (non-MSVC code sections): Likewise.
+
+2003-06-24 Piet van Bruggen
+
+ * pthread_spin_destroy.c (pthread_spin_destroy): Was not freeing the
+ spinlock struct.
+
+2003-06-22 Nicolas Barry
+
+ * pthread_mutex_destroy.c (pthread_mutex_destroy): When called
+ with a recursive mutex that was locked by the current thread, the
+ function was failing with a success return code.
+
+2003-05-15 Steven Reddie
+
+ * pthread_win32_attach_detach_np.c (pthread_win32_process_detach_np):
+ NULLify ptw32_selfThreadKey after the thread is destroyed, otherwise
+ destructors calling pthreads routines might resurrect it again, creating
+ memory leaks. Call the underlying Win32 Tls routine directly rather than
+ pthread_setspecific().
+ (pthread_win32_thread_detach_np): Likewise.
+
+2003-05-14 Viv
+
+ * pthread.dsp: Change /MT compile flag to /MD.
+
+2003-03-04 Alexander Terekhov
+
+ * pthread_mutex_timedlock.c (pthread_mutex_timedlock): Fix failure to
+ set ownership of mutex on second grab after abstime timeout.
+ - bug reported by Robert Strycek
+
+2002-12-17 Thomas Pfaff
+
+ * pthread_mutex_lock.c (ptw32_semwait): New static routine to provide
+ a non-cancelable sem_wait() function. This is consistent with the
+ way that pthread_mutex_timedlock.c does it.
+ (pthread_mutex_lock): Use ptw32_semwait() instead of sem_wait().
+
+2002-12-11 Thomas Pfaff
+
+ * pthread_mutex_trylock.c: Should return EBUSY rather than EDEADLK.
+ * pthread_mutex_destroy.c: Remove redundant ownership test (the
+ trylock call does this for us); do not destroy a recursively locked
+ mutex.
+
+2002-09-20 Michael Johnson
+
+ * pthread_cond_destroy.c (pthread_cond_destroy):
+ When two different threads exist, and one is attempting to
+ destroy a condition variable while the other is attempting to
+ initialize a condition variable that was created with
+ PTHREAD_COND_INITIALIZER, a deadlock can occur. Shrink
+ the ptw32_cond_list_lock critical section to fix it.
+
+2002-07-31 Ross Johnson
+
+ * ptw32_threadStart.c (ptw32_threadStart): Thread cancelLock
+ destruction moved to ptw32_threadDestroy().
+
+ * ptw32_threadDestroy.c (ptw32_threadDestroy): Destroy
+ the thread's cancelLock. Moved here from ptw32_threadStart.c
+ to cleanup implicit threads as well.
+
+2002-07-30 Alexander Terekhov
+
+ * pthread_cond_wait.c (ptw32_cond_wait_cleanup):
+ Remove code designed to avoid/prevent spurious wakeup
+ problems. It is believed that the sem_timedwait() call
+ is consuming a CV signal that it shouldn't and this is
+ breaking the avoidance logic.
+
+2002-07-30 Ross Johnson
+
+ * sem_timedwait.c (sem_timedwait): Tighten checks for
+ unreasonable abstime values - that would result in
+ unexpected timeout values.
+
+ * w32_CancelableWait.c (ptw32_cancelable_wait):
+ Tighten up return value checking and add comments.
+
+
+2002-06-08 Ross Johnson
+
+ * sem_getvalue.c (sem_getvalue): Now returns a value for the
+ NEED_SEM version (i.e. earlier versions of WinCE).
+
+
+2002-06-04 Rob Fanner
+
+ * sem_getvalue.c (sem_getvalue): The Johnson M. Hart
+ approach didn't work - we are forced to take an
+ intrusive approach. We try to decrement the sema
+ and then immediately release it again to get the
+ value. There is a small probability that this may
+ block other threads, but only momentarily.
+
+2002-06-03 Ross Johnson
+
+ * sem_init.c (sem_init): Initialise Win32 semaphores
+ to _POSIX_SEM_VALUE_MAX (which this implementation
+ defines in pthread.h) so that sem_getvalue() can use
+ the trick described in the comments in sem_getvalue().
+ * pthread.h (_POSIX_SEM_VALUE_MAX): Defined.
+ (_POSIX_SEM_NSEMS_MAX): Defined - not used but may be
+ useful for source code portability.
+
+2002-06-03 Rob Fanner
+
+ * sem_getvalue.c (sem_getvalue): Did not work on NT.
+ Use approach suggested by Johnson M. Hart in his book
+ "Win32 System Programming".
+
+2002-02-28 Ross Johnson
+
+ * errno.c: Compiler directive was incorrectly including code.
+ * pthread.h: Conditionally added some #defines from config.h
+ needed when not building the library. e.g. NEED_ERRNO, NEED_SEM.
+ (PTW32_DLLPORT): Now only defined if _DLL defined.
+ (_errno): Compiler directive was incorrectly including prototype.
+ * sched.h: Conditionally added some #defines from config.h
+ needed when not building the library.
+ * semaphore.h: Replace an instance of NEED_SEM that should
+ have been NEED_ERRNO. This change currently has nil effect.
+
+ * GNUmakefile: Correct some recent changes.
+
+ * Makefile: Add rule to generate pre-processor output.
+
+2002-02-23 Ross Johnson
+
+ * pthread_rwlock_timedrdlock.c: New - untested.
+ * pthread_rwlock_timedwrlock.c: New - untested.
+
+ * Testsuite passed (except known MSVC++ problems)
+
+ * pthread_cond_destroy.c: Expand the time change
+ critical section to solve deadlock problem.
+
+ * pthread.c: Add all remaining C modules.
+ * pthread.h: Use dllexport/dllimport attributes on functions
+ to avoid using pthread.def.
+ * sched.h: Likewise.
+ * semaphore.h: Likewise.
+ * GNUmakefile: Add new targets for single translation
+ unit build to maximise inlining potential; generate
+ pthread.def automatically.
+ * Makefile: Likewise, but no longer uses pthread.def.
+
+2002-02-20 Ross Johnson
+
+ * pthread_cond_destroy.c (pthread_cond_destroy):
+ Enter the time change critical section earlier.
+
+2002-02-17 Ross Johnson